Dot Graphic VFD Module GU128X32-800 � 128 x 32 Dot Graphic The module includes the Vacuum Fluorescent Display � Operating Temp -40°°C to +85°°C glass, driver and control ASIC, with integral refresh Graphic °° °° � Single 5V Supply. RAM and logic for parallel and synchronous serial interfaces. The high speed 8 bit parallel interface is 5V � High Brightness Blue Green Display CMOS compatible suitable for connection to a host CPU � Selectable Parallel (i80/M68)/Serial Interface � Twin Screen Graphic RAM bus. Brightness control and power down functions are provided. A full data sheet is available. � 16 Level Brightness Control Function 130.0 1.0 126.5 1.5 33.0 20.65 38.5 30.5 4.0 10.0 83.05 1.75 4 x ø3.5 Mounting Holes 23.5 110.0 1.6 11.4 10.0 65.0 Dimensions in mm See full spec for tolerances PWR(JST-B3B-XH-A) IDC(IMSA-9032B-26P) BLOCK DIAGRAM ELECTRICAL SPECIFICATION Parameter Symbol Value Condition D0~D7 Power Supply Voltage VCC 5.0VDC +/- 5% GND=0V DISPLAY TXD BD VFD CONTROLLER Power Supply Current ICC 450mADC typ. VCC= 5V RXD WR (R/W) Logic High Input VIH 0.8Vcc VDC min. IIH = 2uA RD (EN)(SCK) GRAPHIC Logic Low Input VIL 0.2Vcc VDC max. IIL = -600uA CSS RAM C/D Logic High Output VOH Vcc-0.3 VDC min. IOH = -300uA FRP Logic Low Output VOL 0.3 VDC max. IOL = 300uA The power on rise time should be less than 100ms.The inrush current at power on can be 2 x ICC. FILAMENT (AC) VCC DC/DC + AC OPTICAL and ENVIRONMENTAL SPECIFICATIONS Conv. ANODE + GRID (DC) GND Parameter Value Display Area (XxY mm) 83.05 x 20.65 GRAPHIC RAM Dot Size/Pitch (XxY mm) 0.5 x 0.5/0.65 x 0.65 X ADDRESS BYTE FORMAT 00H………………………….7FH 2 Luminance 350 cd/m Min. D0 0H D1 1H Colour of Illumination Blue-Green (Filter for colours) D2 2H …………….7FH Operating Temperature -40°C to +85°C 3H D3 GRAM 4H D4 Layer 0 Storage Temperature -40°C to +85°C 5H D5 Operating Humidity (non condensing) 20 to 80% RH @ 25°C 6H D6 GRAM Y ADDRESS 7H D7 SOFTWARE COMMANDS Layer 1 The Graphic RAM is composed of 16384 DH Instruction C/D Instruction Byte No. Bytes bits arranged as (128 x 64 bits) x 2 and the EH Set Display On/Off / Layer Merge 1 20H→2FH 2 access is operated by 8 bit vertical data FH Set Display Brightness 1 40H→4FH 1 IDC DATA CONNECTOR 3 PIN POWER CONNECTOR Clear Display 1 52H→5FH 1 Pin i80 M68 Serial Pin Sig Pin Sig Set Cursor XY Address 1 60H→67H 3 1 D7 D7 X 2GND 1Vcc Set Display Start X Address 1 70H→7FH 2 D6 D6 X 3 4GND 2Test (Factory only) Set Write Address Mode 1 80H→8FH 1 D5 D5 X 5 6GND 3GND Scroll Display Vertically Up/Down 1 B0H→BFH 1 PCB JUMPERS (O)pen (L)ink 7 D4 D4 X 8GND Read Data At XY Address 1 D4H→D7H 3 D3 D3 X Interface J1 J2 9 10 GND Write Data 0 00H→FFH 1 D2 D2 X Serial L O / L 11 12 GND TIMING PARAMETERS (min) 13 D1 D1 SO 14 GND i80 Parallel O L i80/M68 Parameters Time Serial Parameters Time 15 D0 D0 SI 16 GND M68 Parallel O O Write WR/EN Cycle Time 750ns SCK Cycle Time 500ns WR R/W X CONTACT 17 18 GND Write WR/EN Pulse Width 100ns SCK Pulse Width 200ns C/D C/D C/D 19 20 GND th Noritake Co., Inc, Hold after Write WR/EN 30ns Delay After 8 bit, CSS=″L″ 150ns 21 RD EN SCK 22 GND Chicago, USA Set Up To Write WR/EN 30ns Set Up To SCK, CSS=″L″ 60ns 23 CSS CSS CSS 24 GND Tel: 1-800-779-5846 SCROLLING GRAPHIC DISPLAY FRP FRP FRP 25 26 /RES Fax: (847)-593-2285 The pattern in GRAM can be scrolled around the display. Horizontal scroll is achieved by www.noritake-elec.com increment/decrement of the Display Start X Address. The vertical scroll process considers Subject to change without notice. layer 0, then layer 1 as a continuous 128 bit high vertical area within RAM. IUK Doc Ref: 00939 Iss:3 25NOV99 noritake@compuserve.com NORITAKE ITRON VFD MODULES 128 x 32 Dot Graphic