NT5117405J 4,194,304-word X 4-bit Dynamic RAM : Fast Page Mode with EDO NT 511740C5J Data Sheet NANYA TECHNOLOGY CORP. reserves the right to change products and specifications without notice. 1 NANYA TECHNOLOGY CORP © NT5117405J 4,194,304-word X 4-bit Dynamic RAM : Fast Page Mode with EDO TABLE OF CONTENTS 1. Description.............................................................................................3 2. Features.................................................................................................3 3. Product Family........................................................................................3 4. Pin Configuration....................................................................................4 5. Block Diagram........................................................................................5 6. Electrical Characteristics.......................................................................6 7. DC Characteristics.................................................................................7 8. AC Characteristics.................................................................................8~11 9. DRAM AC Timing Waveforms..............................................................12~18 NANYA TECHNOLOGY CORP. reserves the right to change products and specifications without notice. 2 NANYA TECHNOLOGY CORP © NT5117405J 4,194,304-word X 4-bit Dynamic RAM : Fast Page Mode with EDO 1. DESCRIPTION The NT511740C5J is a 4,194,304-word x 4-bit dynamic RAM fabricated in NTC’s CMOS silicon gate technology. The NT511740C5J achieves high integration , high-speed operation , and low- power consumption due to quadruple polysilicon double metal CMOS. The NT511740C5J is available in a 26/24-pin plastic SOJ. 2. FEATURES l 4,194,304-word x 4-bit configuration l Single 5V power supply,+/-10% tolerance l Input :TTL compatible , low input capacitance l Output :TTL compatible , 3-state l Refresh :2048 cycles/32 ms l Fast page mode with EDO, read modify write capability l /CAS before /RAS refresh, hidden refresh, /RAS-only refresh capability l Multi-bit test mode capability l Package options: 26/24-Pin 300 mil plastic SOJ (SOJ26/24-P300) (Product:NT511740C5J-XX) XX indicates speed rank. 3. PRODUCT FAMILY Access Time (Max.) Cycle Time Power Dissipation Family t t t t (Min.) Operation(Max.) Standby(Max.) RAC AA CAC OEA NT511740C5J-50 50ns 25ns 13ns 13ns 84ns 660mW NT511740C5J-60 60 ns 30 ns 15 ns 15 ns 104 ns 605mW 5.5 mW NT511740C5J-70 70 ns 35 ns 20 ns 20 ns 124 ns 550 mW NANYA TECHNOLOGY CORP. reserves the right to change products and specifications without notice. 3 NANYA TECHNOLOGY CORP © NT5117405J 4,194,304-word X 4-bit Dynamic RAM : Fast Page Mode with EDO 4. PIN CONFIGURATION (TOPVIEW) 1 26 Vcc Vss 2 25 DQ1 DQ4 DQ2 3 24 DQ3 4 23 WE CAS RAS 5 22 OE 6 21 A9 NC 8 A10 19 A8 9 A0 18 A7 10 17 A1 A6 11 16 A2 A5 12 15 A3 A4 13 14 Vcc Vss 26/24-Pin Plastic SOJ Pin Name Function Adress input A0-A10 RAS Row Adress Strobe CAS Column Adress Strobe DQ1-DQ4 Data Input/Data Output OE Output Enable WE Write Enable Vcc Power Supply (5v) Vss Ground(0V) NC No Connection Note:The same power supply voltage must be provided to every Vcc pin , and the same GND voltage level must be provided to every Vss pin. NANYA TECHNOLOGY CORP. reserves the right to change products and specifications without notice. 4 NANYA TECHNOLOGY CORP © 11 NT5117405J 4,194,304-word X 4-bit Dynamic RAM : Fast Page Mode with EDO 5. BLOCK DIAGRAM Timing RAS Generator Timing Generator CAS Write Column Clock Column WE 11 Address Generator Decoders Buffer OE Output 4 Buffers Internal Refresh Sense I/O 4 4 4 Address DQ1-DQ4 A0-A10 Control Clock Amplifiers Selector Counter Input 4 4 Buffers Row Row Word Memory 11 Address 11 Decoders Drivers Cells Buffer V CC On Chip V Generator BB On Chip IV Generator CC V SS NANYA TECHNOLOGY CORP. reserves the right to change products and specifications without notice. 5 NANYA TECHNOLOGY CORP © NT5117405J 4,194,304-word X 4-bit Dynamic RAM : Fast Page Mode with EDO 6. ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter Symbol Rating Unit SS CC Voltage on Any Pin Relative to V V V -0.3 to V +0.3 V IN, OUT SS Voltage on V Supply Relative to V V -0.5 to 7 V CC CC Short Circuit Output Cuttent I 50 mA OS Po/WEr Dissipation P*1 W D o Operation Temperature T 0 to 70 C opr o Storage Temperature T -55 to 150 C stg o C *:Ta = 25 Recommended Operating Conditions o o C C (Ta=0 to70 ) Parameter Symbol Min. Typ. Max. Unit Po/WEr Supply Voltage V 4.5 5.0 5.5 V CC V 00 0 V SS Input High Voltage V 2.4 - V +0.3 V IH CC Input Low Voltage V -0.3 - 0.8 V IL Capacitance o C (Vcc = 5V+/-10%,Ta=25 , f=1 MHZ) Parameter Symbol Typ. Max. Unit Input Capacitance (A0-A10) C -5 pF IN1 Input Capacitance (/RAS,/CAS,/WE,/OE) C -7 pF IN2 Output Capacitance (DQ1-DQ4) C -7 pF I/O NANYA TECHNOLOGY CORP. reserves the right to change products and specifications without notice. 6 NANYA TECHNOLOGY CORP © NT5117405J 4,194,304-word X 4-bit Dynamic RAM : Fast Page Mode with EDO 7. DC Characteristics o o (Vcc=5V+/-10% ,Ta=0 C to 70 C) NT511740C NT511740C NT511740C 5J-50 5J-60 5J-70 Parameter Symbol Condition Unit Note Min. Max. Min. Max. Min. Max. I =-5.0 mA OH Output High Voltage V 2.4 Vcc 2.4 Vcc 2.4 Vcc V OH I =4.2 mA OL Output LOW Voltage V 00.4 00.4 00.4 V OL 0V<=V <=6.5V; I All other pins not μ Input Leakage Current I under test = 0V -10 10 -10 10 -10 10 L1 A DQ disable μ Output Leakage I -10 10 -10 10 -10 10 L0 0V<=V <=5.5V A o Current Average Power /RAS,CAC cycling, Supply Current I - 120 - 110 - 100 mA 1,2 cc1 tRC = Min. (Operating) -2 -2 -2 /RAS , /CAS=VIH Power Supply I cc2 mA 1 /RAS, /CAS Current (Standby) -1 -1 -1 >=Vcc-0.2V Average Power /RAS cycling, Supply Current I - 120 - 110 - 110 mA 1,2 cc3 /CAS = VIH, (/RAS-only Refresh) tRC=Min. /RAS= VIH, Power Supply I cc5 -5 -5 -5 mA 1 /CAS= VIL, Current (Standby) DQ = enable Average Power /RAS cycling, Supply Current I - 110 - 100 - 90 mA 1,2 cc6 /CAS before /RAS (/CAS before /RAS Refresh) Average Power /RAS=VIL, Supply Current I - 110 - 100 - 90 mA 1,3 cc7 /CAS cycling (Fast Page Mode) tpc=Min. Notes¡G 1. ICC Max. is specified as Icc for output open condition. 2. Address can be changed once or less while /RAS=V . IL 3. Address can be changed once or less while /CAS=V . IH NANYA TECHNOLOGY CORP. reserves the right to change products and specifications without notice. 7 NANYA TECHNOLOGY CORP © NT5117405J 4,194,304-word X 4-bit Dynamic RAM : Fast Page Mode with EDO 8. AC Characteristics (1/3) o o ¡� (Vcc=5V 10% ,Ta=0 C to 70 C ) Note:1,2,3,12,13 NT511740C5J- NT511740C5J- NT511740C5J- 50 60 70 Parameter Symbol Unit Note Min. Max. Min. Max. Min. Max. Random Read or Write Cycle Time t 84 - 104 - 124 - ns RC Read Modify Write Cycle Time t 110 - 135 - 160 - ns RWC Fast Page Mode Cycle Time t 20 - 25 - 30 - ns HPC Fast Page Mode Read Modify Write Cycle Time t 58 - 68 - 78 - ns PRWC Access Time form /RAS t -50 - 60 - 70 ns4,5,6 RAC Access Time form /CAS t -13 - 15 - 20 ns4,5 CAC Access Time form Column Address t -25 - 30 - 35 ns4,6 AA Access Time form /CAS Precharge t -30 - 35 - 40 ns 4 CPA Access Time form /OE t -13 - 15 - 20 ns 4 /OEA Output Low Impedance Time from /CAS t 0 - 0- 0- ns 4 CLZ Data Output Hold After /CAS Low t 5 - 5- 5- ns DOH /CAS to Data Output Buffer Turn-off Delay Time t 0 13 0 15 0 20 ns 7,8 CEZ /RAS to Data Output Buffer Turn-off Delay t 0 13 0 15 0 20 ns 7,8 REZ Time /OE to Data Output Buffer Turn-off Delay Time t 0 13 0 15 0 20 ns 7 /OEZ /WE to Data Output Buffer Turn-off Delay t 0 13 0 15 0 20 ns 7 /WEZ Time Transition Time t 1 50 1 50 1 50 ns 3 T Refresh Period t -32 - 32 - 32 ms REF /RAS Precharge Time t 30 - 40 - 50 - ns RP /RAS Pulse Width t 50 10,0006010,000 70 10,000 ns /RAS /RAS Pulse Width (Fast Page Mode with EDO) t 50 100,00060100,000 70 100,000 ns /RASP NANYA TECHNOLOGY CORP. reserves the right to change products and specifications without notice. 8 NANYA TECHNOLOGY CORP © NT5117405J 4,194,304-word X 4-bit Dynamic RAM : Fast Page Mode with EDO AC Characteristics (2/3) NT10511740C5J- NT511740C5J- NT511740C5J- 50 60 70 Symbol Unit Note Parameter Min. Max. Min. Max. Min. Max. /RAS Hold Time 7 - 10 - 13 - ns t RSH /RAS Hold Time referenced to /OE 7 - 10 - 13 - ns t ROH /CAS Precharge Time (Fast Page Mode with EDO) 7 - 10 - 13 - ns t CP /CAS Pulse Width 710,000 10 10,000 13 10,000 ns t /CAS /CAS Hold Time 35 - 40 - 45 - ns t CSH /CAS to /RAS Precharge Time 5 - 5- 5- ns t CRP /RAS Hold Time from /CAS Precharge Time 30 - 35 - 40 - ns t RHCP /OE Hold Time from /CAS (DQ Disable) 5 - 5- 5- ns t CHO /RAS to /CAS Delay Time 11 37 14 45 14 50 ns 5 t RCD /RAS to Column Address Delay Time 9 2512301235 ns 6 t RAD Row Address Set-up Time 0 - 0- 0- ns t ASR Row Address Hold Time 7 - 10 - 13 - ns t RAH Column Address Set-up Time 0 - 0- 0- ns t ASC Column Address Hold Time 7 - 10 - 13 - ns t CAH Column Address to /RAS Lead Time 25 - 30 - 35 - ns t RAL Read Command Set-up Time 0 - 0- 0- ns tRCS Read Command Hold Time 0 - 0- 0- ns 9 tRCH Read Command Hold Time referenced to /RAS 0 - 0- 0- ns 9 t RRH Write Command Set-up Time 0 - 0- 0- ns 10 tWCS NANYA TECHNOLOGY CORP. reserves the right to change products and specifications without notice. 9 NANYA TECHNOLOGY CORP © NT5117405J 4,194,304-word X 4-bit Dynamic RAM : Fast Page Mode with EDO AC Characteristics (3/3) o o (Vcc=5V +/-10% ,Ta=0 C to 70 C) Note 1,2,3,12,13 NT511740C5J- NT511740C5J- NT511740A5J- 50 60 70 Unit Note Symbol Parameter Min. Max. Min. Max. Min. Max. Write Command Hold Time 7 - 10 - 13 - ns tWCH Write Command Pulse Width 7 - 10 - 10 - ns tWP /WE Pulse Width (DQ Disable) 7 - 10 - 10 - ns t WPE /OE Command Hold Time 7 - 10 - 13 - ns t /OEH /OE Precharge Time 7 - 10 - 10 - ns t/OEP /OE Command Hold Time 7 - 10 - 10 - ns tOCH Write Command to /RAS Lead Time 7 - 10 - 13 - ns tRWL Write Command to /CAS Lead Time 7 - 10 - 13 - ns t CWL Data-in Set-up Time 0 - 0- 0- ns 11 tDS Data-in Hold Time 7 - 10 - 13 - ns 11 tDH /OE to Data-in Delay Time 13 - 15 - 20 - ns t/OED /CAS to /WE Delay Time 30 - 34 - 44 - ns 10 t CWD Column Address to /WE Delay Time 42 - 49 - 59 - ns 10 t AWD /RAS to /WE Delay Time 67 - 79 - 94 - ns 10 tRWD /CAS Precharge /WE Delay Time 47 - 54 - 64 - ns 10 tCPWD /CAS Active Delay Time from /RAS Precharge 5 - 5- 5- ns t RPC /RAS to /CAS Set-up Time (/CAS before /RAS) 5 - 5- 5- ns t CSR /RAS to /CAS Hold Time (/CAS before /RAS) 10 - 10 - 10 - ns tCHR /WE to /RAS Precharge Time (/CAS before /RAS) 10 - 10 - 10 - ns tWRP /WE Hold Time /RAS (/CAS before /RAS) 10 - 10 - 10 - ns tWRH /RAS to /WE Set-up Time (Test Mode) 10 - 10 - 10 - ns t WTS /RAS to /WE Hold Time (Test Mode) 10 - 10 - 10 - ns tWTH NANYA TECHNOLOGY CORP. reserves the right to change products and specifications without notice. 10 NANYA TECHNOLOGY CORP © NT5117405J 4,194,304-word X 4-bit Dynamic RAM : Fast Page Mode with EDO Notes: μ 1. A start-up delay of 200 s is required after po/WEr-up,follo/WEd by a minimum of eight initialization cycles (/RAS-only refresh or /CAS before /RAS refresh) before proper device operation is achieved. 2. The AC characteristics assume t =2 ns. T 3. V (Min.) and V (Max.) are reference levels for measuring input timing signals. Transition time (t ) IH IL T are measured bet/WEen V and V . IH IL 4. This parameter is measured with a load circuit equivalent to 2 TTL loads and 100 pF. 5. Operation within the t (Max.) limit ensures that t (Max.) can be met. RCD RAC t (Max.) is specified as a reference point only . If t is greater than the specified RCD RCD t (Max.) limit, access time is controlled by t . RCD CAC 6. Operation within the t (Max.) limit ensures that t (Max.) can be met. RAD RAC t (Max.) is specified as a reference point only . If t is greater than the specified RAD RAD t (Max.) limit, access time is controlled by t . RAD AA 7. t (Max.), t (Max.), t (Max.) and t (Max.) define the time at which the output achieves the CEZ REZ /WEZ /OEZ open circuit condition and are not referenced to output voltage levels. 8. t and t must be satisfied for open circuit condition . CEZ REZ 9. t or t must be satisfied for a read cycle. RCH RRH 10. t , t , t , t , and t are not restrictive operating parameters. They are included in the data WCS CWD RWD AWD CPWD ¡� sheet as electrical characteristics only . If t t (Min.), the cycle is an early write cycle and the WCS WCS ¡� data out will remain open circuit (high impedance) throughout the entire cycle. If t t (Min.) , CWD CWD ¡� ¡� ¡� t t (Min.) , t t (Min.) and t t (Min.), the cycle is a read modify write cycle RWD RWD AWD AWD CPWD CPWD and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 11. These parameters are referenced to /CAS leading edge in an early write cycle, and to /WE leading edge in an /OE control write cycle or a read modify write cycle . 12. The test mode is initiated by performing a /WE and /CAS before /RAS refresh cycle. This mode is latched and remains in effect until the exit cycle is generated. In a test mode CA0 and CA1 are not used and each DQ pin now accesses 8-bit locations .Since all 4 DQ pins are used, a total of 32 data bits can be written in parallel into the memory array. In a read cycle, if 8 data bits are equal the DQ pin will indicate a high level. If the 8 data bits are not equal, the DQ pin will indicate a low level. The test mode is cleared and the memory device returned to its normal operating state by performing a /RAS-only refresh cycle or a /CAS before /RAS refresh cycle. 13. In a test mode read cycle , the value of access time parameters is delayed for 5 ns for the specified value . These parameters should be specified in test mode cycle by adding the above value to the specified value in this data sheet. NANYA TECHNOLOGY CORP. reserves the right to change products and specifications without notice. 11 NANYA TECHNOLOGY CORP © NT5117405J 4,194,304-word X 4-bit Dynamic RAM : Fast Page Mode with EDO 9.DRAM AC Timing Waveforms Read Cycle tRC tRP tRAS VIH RAS tCRP VIL tCSH tCRP tRCD tRSH VIH tCAS CAS VIL tRAD tRAL tASR tRAH tASC tCAH VIH Row Column Address VIL tRCH tRCS tRRH VIH tAA WE VIL tROH tREZ tOEA VIH OE VIL tCEZ tCAC tRAC tOEZ VIH DQ Open Valid Data-out VIL tCLZ "H" or "L" Write Cycle(Early Write) tRC tRP tRAS VIH RAS tCRP VIL tCSH tCRP tRCD tRSH VIH tCAS CAS VIL tRAD tRAL tASR tRAH tASC tCAH VIH Row Column Address VIL tCWL tWCS tWCH VIH tWP WE VIL tRWL VIH OE VIL tDS tDH VIH DQ Valid data-in Open VIL "H" or "L" NANYA TECHNOLOGY CORP. reserves the right to change products and specifications without notice. 12 NANYA TECHNOLOGY CORP © NT5117405J 4,194,304-word X 4-bit Dynamic RAM : Fast Page Mode with EDO Read Modify Write Cycle tRWC tRP tRAS VIH RAS VIL tCRP tCSH tCRP tRCD tRSH VIH tCAS CAS VIL tASR tRAH tASC tCAH VIH Row Column Address VIL tCWD tRAD tCWL tRWD tRWL VIH tWP tAA WE VIL tAWD tRCS tOEA VIH OE tOED tOEH VIL tCAC tRAC tOEZ tDS tDH VIH Valid Valid DQ Data-out Data-in VIL tCLZ "H" or "L" NANYA TECHNOLOGY CORP. reserves the right to change products and specifications without notice. 13 NANYA TECHNOLOGY CORP © NT5117405J 4,194,304-word X 4-bit Dynamic RAM : Fast Page Mode with EDO Fast Page Mode Read Cycle (Part-1) tRP tRASP VIH tRHCP RAS VIL tHPC tCRP tRCD tCP tCP VIH tCAS tCAS tCAS CAS VIL tRAD tCSH tASR tRAH tASC tCAH tASC tCAH tASC tCAH VIH Row Column Column Column Address VIL tRRH tRCS VIH tOCH tCHO WE VIL tRAC tOEP tOEP tAA VIH tAA OE VIL tAA tOEA tOEA tCPA tOEA tCAC tREZ tOEZ tCAC tOEZ tCAC tDOH VIH Valid Valid Valid Valid DQ Data-out Data-out Data-out Data-out VIL tCLZ "H" or "L" Fast Page Mode Read Cycle(Part-2) tRASP tRP VIH tRHCP RAS VIL tCRP tHPC tCRP tRCD tCP tCP VIH tCAS tCAS tCAS CAS VIL tRAD tCSH tASR tRAH tASC tCAH tASC tCAH tASC tCAH VIH Row Column Column Column Address VIL tRCS tRCS VIH WE VIL tRCH tWPE tAA tRAC tAA tAA VIH tCPA OE VIL tOEA tCAC tWEZ tCAC tCEZ tCAC tDOH VIH Valid Valid Valid DQ Data-out Data-out Data-out tCLZ VIL "H" or "L" NANYA TECHNOLOGY CORP. reserves the right to change products and specifications without notice. 14 NANYA TECHNOLOGY CORP © NT5117405J 4,194,304-word X 4-bit Dynamic RAM : Fast Page Mode with EDO Fast page Mode Write Cycle(Early Write) tRASP tRP VIH RAS VIL tHPC tHPC tCRP tRCD tCP tCP VIH tCAS tCAS tCAS CAS VIL tRAD tRSH tCSH tASR tRAH tASC tCAH tASC tCAH tASC tCAH VIH Row Column Column Column Address VIL tWCS tWCH tWCS tWCH tWCS tWCH VIH WE VIL VIH OE VIL tDH tDS tDH tDS tDH tDS VIH Valid Valid Valid DQ Data-in Data-in Data-in VIL "H" or "L" Fast Page Mode Read Modify Write Cycle tRASP VIH tRWD RAS VIL tCRP tCP tRCD VIH tCWD CAS VIL tRAD tCPWD tHPRWC tRWL tCPA tASR tRAH tASC tCAH tCWL tASC tCAH VIH Row Column Column Address VIL tAWD tRCS tCWD tRCS VIH WE tAWD VIL tDS tWP tRAC tDS tWP tAA tAA VIH tOEH tOEH OE VIL tOEA tOEA tOED tOED tDH tCAC tOEZ tDH tCAC tOEZ VIH Valid Valid Valid Valid DQ Data-out Data-in Data-out Data-in VIL tCLZ tCLZ "H" or "L" NANYA TECHNOLOGY CORP. reserves the right to change products and specifications without notice. 15 NANYA TECHNOLOGY CORP © NT5117405J 4,194,304-word X 4-bit Dynamic RAM : Fast Page Mode with EDO RAS-only Refresh Cycle tRC tRP tRAS VIH RAS VIL tRPC tCRP VIH CAS VIL tASR tRAH VIH Row Address VIL tCEZ VIH Open DQ VIL Note:WE,OE="H" or "L" "H" or "L" CAS before RAS Refresh Cycle tRC tRAS tRP tRP VIH RAS VIL tRPC tRPC tCP tCSR tCHR VIH CAS VIL tWRP tWRP tWRH VIH WE VIL tCEZ VIH Open DQ VIL Note:OE,Address="H" or "L" "H" or "L" NANYA TECHNOLOGY CORP. reserves the right to change products and specifications without notice. 16 NANYA TECHNOLOGY CORP © NT5117405J 4,194,304-word X 4-bit Dynamic RAM : Fast Page Mode with EDO Hidden Refresh Read Cycle tRC tRC tRP tRAS tRP tRAS VIH RAS VIL tCHR tCRP tRCD tRSH VIH CAS VIL tRAD tRAH tASC tASR tCAH VIH Row Column Address VIL tRCS tRAL tRRH VIH tAA WE VIL tROH tOEA VIH OE VIL tCAC tCEZ tCLZ tREZ tRAC tOEZ VIH DQ Open Valid Data-out VIL "H" or "L" Hidden Refresh Write Cycle tRC tRC tRP tRAS tRP tRAS VIH RAS VIL tCHR tCRP tRCD tRSH VIH CAS VIL tRAD tRAL tRAH tASC tASR tCAH VIH Row Column Address VIL tRWL tWCS tWCH VIH tWP WE VIL VIH OE VIL tDH tDS VIH DQ Valid Data-in VIL "H" or "L" NANYA TECHNOLOGY CORP. reserves the right to change products and specifications without notice. 17 NANYA TECHNOLOGY CORP © NT5117405J 4,194,304-word X 4-bit Dynamic RAM : Fast Page Mode with EDO Test Mode Initiate Cycle tRC tRP tRAS VIH RAS VIL tRPC tCSR tCHR tCP VIH CAS VIL tWTS tWTH VIH WE VIL tOFF VIH Open DQ VIL Note:OE,Address="H" or "L" "H" or "L" NANYA TECHNOLOGY CORP. reserves the right to change products and specifications without notice. 18 NANYA TECHNOLOGY CORP ©