DTL Series DTL3A Model Digitally Programmable, 2A/200V 100 Watt, Electronic Loads DATEL’s new DTL3A is a digitally controlled, optically isolated, serial-input elec- Features tronic load that offers high compliance voltage and unprecedented control over low- ■12-bit, optically isolated (500Vdc), level currents. The DTL3A is essentially a computer controlled current source that CMOS/TTL-compatible serial input sinks currents from 0 to 2 Amps, at loading voltages from 2.5 to 200 Volts, up to a ■0-2 Amp output in 500µA increments maximum power of 100 Watts. The DTL3A accepts a serialized, 12-bit, CMOS/TTL ■Output voltage to 200 Volts digital input word, optically isolates (500Vdc) the data, latches it, and presents it to an on-board, 12-bit, digital-to-analog (D/A) converter. The D/A output drives a near-ideal ■Output power to 100 Watts (10MΩ output impedance), voltage-controlled current source. ■10MΩ minimum output impedance One LSB (least signi cant bit) of the D/A corresponds to a mere 500µA (0.025% of ■±500µA offset error; ±0.1% gain error 2A) of load current. Combined with the DTL3A’s ±500µA max. offset error and ±0.1% ■100µsec full-scale step response max. gain error, this precise digital control gives users extraordinary command over the generation of low-level load currents. A 100mA current, for example, is guaranteed ■Update rates to 20kHz to have ±1mA accuracy over all speci ed load-voltage conditions. ■Operate in parallel for higher power The DTL3A has impressive speed performance. Digital update rates to 20kHz ■Miniature, 2" x 2" metal package are possible, and settling time for a full 2A step is 100µsec. The unit is housed in a thermally ef cient, 2" x 2" x 0.5" metal package that has an aluminum baseplate with Applications through-hole spacers for easy pcb mounting and/or external heat-sink attachment. ■Static/dynamic power-supply burn-in The DTL-3A has an output compliance-voltage requirement 2.5 to 200V. Should ■Power-supply test and characterization the output/load voltage drop below the 2.5V minimum required for proper biasing, an internal monitoring circuit activates the DTL3A's output Fault line. See DATEL’s ■Battery capacity testing DTL2A-LC for compliance voltages as low as 0.6V. ■Current-source testing DATEL’s electronic loads, controller boards and companion software are outstand- ■Capacitor discharge testing ing building-block components for power-supply (AC/DC and DC/DC) and power- ■Real-time load simulation component (diodes, FET’s, etc.) burn-in and test systems. They are an extremely reliable, cost-effective solution that enables you to quickly con gure exible, impres- sively accurate systems. INPUT OPTO BUFFERS ISOLATORS CONTROL STROBE (CS) +LOAD +LOAD CLOCK (CLK) AMPLIFIER AND POWER DEVICE DATA 12-BIT LATCH CURRENT UNDER TEST D/A SERIAL DATA INPUT (SDI) SENSOR –LOAD LATCH DATA (LD) –LOAD FAULT UNDERVOLTAGE DETECTION ISOLATED +5V SUPPLY DC/DC GROUND CONVERTER Figure 1. SimpliŢ ed Schematic DTL Series 100 WATT, HIGH-VOLTAGE ELECTRONIC LOADS ➀Performance SpeciŢ cations and Ordering Guide Input Output Compliance Resolution Logic Current Resolution Voltage Power Package Model (Bits) Compatibility (Amps) (mA) ➁ (Volts) ➂ (Watts) (Case, Pinout) DTL3A 12 CMOS/TTL ➃ 0-2 0.5 2.5-200 0-100 C24, P31 ➀ Typical at TA = +25°C with nominal +5V supply voltage unless noted. ➁ The smallest increment/decrement in output current is defi ned by one LSB (least signifi cant bit) of the 12-bit digital input word. One LSB is equal to full scale (FS) divided by 4096 which corresponds to 0.0244% of 2A or 488µA. ➂ For proper operation, the unit's output/load voltage must remain within this range. Voltages greater than the listed maximum can damage the device. Voltages less than the minimum provide insuffi cient bias for the output stage and will result in unpredictable or no operation. See Output Compliance Voltage and the Fault Line for details. ➃ See Performance/Functional Specifi cations for details. PART NUMBER STRUCTURE MECHANICAL SPECIFICATIONS 2.00 DTL 3 A (50.80) ALUMINUM BASEPLATE DATEL A-Series METAL CASE 0.50 Case C24 Electronic Load High Reliability (12.70) Voltage Range: 3 = 2.5 to 200V 0.060 ±0.002 DIA. 0.040 ±0.002 DIA. (1.524 ±0.051) (1.016 ±0.051) 0.20 MIN 1.800 0.10 (5.08) (45.72) (2.54) 1.640 0.08 (41.66) (2.03) TEMPERATURE DERATIN 8 7 100 6 5 9 90 1.20 2.00 (30.48) 4 1.640 6 EQ. SP. @ (41.66) (50.80) 80 3 10 0.200 (5.08) 2 70 1 11 60 0.40 (10.16) 50 BOTTOM VIEW 0.22 #4-40 CLEAR THRU 40 (5.59) (TYP. 4 PL) 30 I/O Connections 20 Pin Function P31 Pin Function P31 10 1 Fault 7 Control Strobe (CS) 2 Ground 8 –Load 0 10 2030 40 5060 708090 100 3 +5 Volt Supply 9 –Load Baseplate Temperature (°C) 4 Latch Data (LD) 10 +Load 5 Serial Data In (SDI) 11 +Load The horizontal axis of the above chart references the temperature of the DTL3A’s alumi- 6 Clock (CLK) num baseplate. The device can continually dissipate up to 100 Watts if the baseplate is maintained at or below +50°C. At +25°C ambient temperature, with no heat sink or supplemental air fl ow, the DTL3A can reliably dissipate a continuous 10 Watts. Contact DATEL for Heat Sink information. 2 Output Power/Load (Watts) 100 WATT, HIGH-VOLTAGE ELECTRONIC LOADS DTL3A Model Performance/Functional SpeciŢ cations Typical @ TA = +25°C with nominal +5V supply voltage, unless noted. ➀ The smallest increment/decrement in output current is defi ned by one LSB (least signifi cant bit) of the 12-bit digital input word. One LSB is equal to full scale (FS) divided by 4096 which Digital Inputs/Outputs corresponds to 0.0244% of 2A or 488µA. Logic Compatibility (Pins 1, 4-7) CMOS/TTL ➁ For proper operation, the unit's output/load voltage must remain within this range. Voltages greater than the listed maximum can damage the device. Voltages less than the minimum Input Logic Levels: provide insuffi cient bias for the output stage and will result in unpredictable or no operation. Logic "1" +2 Volts, minimum See Output Compliance Voltage and the Fault Line for details. Logic "0" +0.8 Volts, maximum ➂ Offset error is defi ned as the current sunk/sourced by the DTL3A’s output, under any output voltage conditions, when the digital input word is all "0's." Input Logic Loading: ➃ Full scale step (2 Amps) settling to within ±0.5mA of its fi nal value. Logic "1" (IIH @ VIH = 5 Volts) 20µA, maximum ➄ See Temperature Derating. Logic "0" (IIL @ VIL = 0 Volts) –0.6mA, maximum ➅ Applies over all specifi ed ranges/combinations of load voltage/current, operating temperature, Output Logic Levels: and VCC. Logic "1" (@ 150µA) +3.5 Volts, minimum Logic "0" (@ 1.6mA) +0.4 Volts, maximum Absolute Maximum Ratings Timing See Timing Diagram Power Supply Voltage (+VCC, Pin 3) –0.5 to +5.5 Volts Output Digital Input Voltage (Pins 4-7) –0.5 to +5.5 Volts Current: Range 0-2 Amps Output Reverse-Polarity Protection No protection Resolution ➀ 0.024%FS (488µA) Output Overvoltage Protection No protection Accuracy ➅ ±1%, maximum Voltage Range ➁ 2.5-200 Volts Output Undervoltage Protection Yes (See Fault Line) Power Range 0-100 Watts Case Temperature +105°C Impedance 10MΩ, minimum Storage Temperature (Ambient) –40 to +125°C Offset Error ➂ ±0.5mA, maximum Lead Temperature (Soldering, 10 sec.) +300°C Gain Error ±0.1%, maximum These are stress ratings. Exposure of devices to any of these conditions may adversely Isolation Voltage: affect long-term reliability. Proper operation under conditions other than those listed in the Digital Inputs/Output to ±Load 500Vdc, minimum Performance/Functional Specifi cations Table is not implied. Any Pin to Case 500Vdc, minimum Isolation Resistance 100MΩ, minimum Dynamic Performance TECHNICAL NOTES Output Slew Rate ±10A/µsec, minimum Output Settling Time ➃ 100µsec Overview Digital Input Update Rate to 20kHz The DTL3A is a digitally programmable, CMOS/TTL-compatible, serial-input Power Requirements current sink. It’s output/load current range is 0 to 2 Amps (in 488µA Power Supply Range (+VCC, Pin 3) +4.75-5.25 Volts (+5V nominal) increments), over a compliance voltage range of 2.5 to 200 Volts and an output/ Power Supply Current 110mA typ., 150mA max. load power range of 0 to 100 Watts. The device’s digital I/O coding is straight Environmental binary (see table below). A digital input of all "0’s" forces a load current of 0 Operating Temperature ➄ –40 to +100°C (Case) Amps. A digital input of all "1’s" forces a load current of 1.9995 Amps. Storage Temperature –40 to +125°C (Ambient) In a typical power-supply test or burn-in application, the output pins of the Humidity (Non-condensing) to 95% device under test (DUT) are connected to the DTL3A’s +Load (pins 10 and 11) Altitude Above Sea Level 10,000 feet and –Load (pins 8 and 9) outputs. The DTL3A’s operation is controlled by its Physical four digital input lines (Serial Data In, Clock, Latch Data and Control Strobe). Dimensions 2" x 2" x 0.5" (51 x 51 x 12.7mm) Shielding 6-sided (Connected to pin 2) Serial Input Data Word Load Current (Amps) Case Material Tin-plated steel shell with MSB LSB DTL3A aluminum baseplate 1111 1111 1111 1.9995 Pin Material Brass, solder coated 1100 0000 0000 1.5000 Mounting Holes Through-hole spacers, #4-40 clearance 1000 0000 0000 1.0000 Weight 1.9 ounces (54 grams) 0111 1111 1111 0.9995 0100 0000 0000 0.5000 0010 0000 0000 0.2500 0000 0000 0001 0.0005 0000 0000 0000 0.0000 Mapping of the Serial-Input Data to Load Current 3 DTL Series 100 WATT, HIGH-VOLTAGE ELECTRONIC LOADS Initialization Output Compliance Voltage and the Fault Line Preparing the DTL3A to accept new digital data is accomplished by applying For proper operation, the DTL3A’s output/load voltage must always be between 2.5 and 200 Volts. The device cannot be used to directly load low- logic "1's" to Control Strobe (CS, pin 7), Latch Data (LD, pin 4) and Clock (CLK, pin 6) with all signals present and stable for a minimum of 1µsec. voltage, e.g. 1.8V or 2.5V, power components or to simulate a true short circuit (0 Volts). Voltages greater than 200V can damage the device. Voltages During this interval, it does not matter whether or not data is present on the Serial Data In (SDI, pin 5) line. <2.5V will result in insuffi cient biasing of the output current source and consequently unpredictable or no operation. Accordingly, we have installed Serial Data an internal output/load-voltage monitoring circuit. If the output/load voltage drops below 2.5V and the DTL3A’s output is at risk of becoming disabled, Following initialization, the 12-bit digital word representing the desired output the Fault line activates. current is applied to the SDI pin. The serial data should appear starting with the most signifi cant bit (MSB, bit 1, D11) and ending with the least signifi cant The Fault line is an optically isolated, active-low function with an open- bit (LSB, bit 12, D0). With each data bit present and stable on the SDI line, collector output (internal 10kΩ pull-up resistor to +5V). Under normal condi- the CLK must be toggled through a low-to-high transition to register that bit. tions, its output is high (logic "1"). Under fault conditions (VOUT < 2.5V), its Twelve rising clock edges, at rates up to 500kHz, are required to clock all 12 output drops to a logic "0." There is no output/load-voltage monitoring circuit digital bits into the DTL3A’s input register. for voltages greater than 200V, and operation above 200V can damage the device. Latching Data and Presenting It to the D/A An "offset supply" can be inserted between the DTL3A’s –Load output (pins After loading the LSB, the serial data word is latched by bringing the Control 8 and 9) and the power device under test (DUT) to "translate" the DTL3A’s Strobe (pin 7) high and then toggling the Latch Data pin (pin 4) through a 197.5V output/load voltage range. The offset supply must have adequate high-low-high sequence. Approximately 100µsec later, the output current will current capabilities and be connected with the polarities indicated in Figure 2 settle to its fi nal desired value. below. Under no circumstances should the voltage across the DTL3A’s output be allowed to experience a polarity reversal. Software: C Language If a 5V/20A offset supply is inserted as shown, the range of DUT voltages The following steps describe a typical timing sequence when using the will be –2.5 to +195 Volts. Such a confi guration can be used for true short- DTL3A’s 4 digital inputs and a programming language such as C. Using 4 bits circuit testing. A mechanical relay can be used to short the outputs of the of a typical 8-bit port, assign BIT_0 to the Control Strobe (CS, pin 7), BIT_1 DUT while the offset supply ensures the DTL3A always sees at least 5 Volts to Latch Data (LD, pin 4), BIT_2 to Serial Data In (SDI, pin 5), and BIT_3 across its outputs. to the Clock (CLK, pin 6). 1. Initialize with Control Strobe, Latch Data, and Clock high: BIT_0 = 1, BIT_1 = 1, BIT_2 = X (don’t care), BIT_3 = 1 11 +LOAD 2. Bring the Control Strobe low. 10 + BIT_0 = 0 SHORT DTL3A DUT CIRCUIT 3. Apply the MSB (D11) of the serial data word to Serial Data In. RELAY 5V BIT_2 = 0 or 1 – + 9 – –LOAD 4. Toggle the Clock high-low-high. 8 BIT_3 = 1 to 0 to 1 5. Apply D10 of the serial data word to Serial Data In. BIT_2 = 0 or 1 Figure 2. An "Offset Supply" Enables True Short-Circuit Testing 6. Toggle the Clock high-low-high. BIT_3 = 1 to 0 to 1 Thermal Considerations 7. Repeat the process for remaining data bits D9 through D0. The DTL3A can reliably handle 100W loads if its case temperature is 8. Drive the Control Strobe high. maintained at or below +50°C. With no heat sinking or auxiliary cooling, the BIT_0 = 1 device can only handle loads up to 10 Watts. Please refer to the Temperature 9. Toggle the Latch Data input high-low-high. Derating Curve for additional information. DATEL’s Electronic Load Applica- BIT_1 = 1 to 0 to 1. tions Engineers can assist you in developing heat-sink solutions for your higher-power DTL3A applications. Please contact us for details. 4 100 WATT, HIGH-VOLTAGE ELECTRONIC LOADS DTL3A Model tdh D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SDI tds tin CLK tcss tcl tcsh tch CS tld1 tld2 LD tldw Timing Min. Typ. Max. Units CLK – – 200 Hz tin 1 – – µsec tcl = tch 1 – – µsec tcss 1 – – µsec tcsh 1 – – µsec tld1 2 – – µsec tld2 2 – – µsec tldw 2 – – µsec tds 0.5 – – µsec tdh 0.5 – – µsec Figure 3. DTL3A Timing Diagram