IXDN430 / IXDI430 / IXDD430 / IXDS430 30 Amp Low-Side Ultrafast MOSFET / IGBT Driver General Description Features • Built using the advantages and compatibility The IXDN430/IXDI430/IXDD430/IXDS430 are high speed high TM of CMOS and IXYS HDMOS processes current gate drivers specifically designed to drive MOSFETs • Latch-Up Protected and IGBTs to their minimum switching time and maximum • High Peak Output Current: 30A Peak practical frequency limits. The IXD_430 can source and sink • Wide Operating Range: 8.5V to 35V 30A of peak current while producing voltage rise and fall times • Under Voltage Lockout Protection of less than 30ns. The input of the drivers are compatible with • Ability to Disable Output under Faults TTL or CMOS and are fully immune to latch up over the entire • High Capacitive Load operating range. Designed with small internal delays, cross Drive Capability: 5600 pF in <25ns conduction/current shoot-through is virtually eliminated in all • Matched Rise And Fall Times configurations. Their features and wide safety margin in • Low Propagation Delay Time operating voltage and power make the drivers unmatched in • Low Output Impedance performance and value. • Low Supply Current The IXD_430 incorporates a unique ability to disable the output under fault conditions. The standard undervoltage lockout is at Applications 12.5V which can also be set to 8.5V in the IXDS430SI. When a • Driving MOSFETs and IGBTs logical low is forced into the Enable inputs, both final output • Motor Controls stage MOSFETs (NMOS and PMOS) are turned off. As a • Line Drivers result, the output of the IXDD430 enters a tristate mode and • Pulse Generators enables a Soft Turn-Off of the MOSFET when a short circuit is • Local Power ON / OFF Switch detected. This helps prevent damage that could occur to the • Switch Mode Power Supplies (SMPS) MOSFET if it were to be switched off abruptly due to a dv/dt • DC to DC Converters over-voltage transient. • Pulse Transformer Driver The IXDN430 is configured as a noninverting gate driver, and the • Limiting di/dt Under Short Circuit IXDI430 is an inverting gate driver. The IXDS430 can be configured • Class D Switching Amplifiers either as a noninverting or inverting driver. The IXD_430 are available in the standard 28-pin SIOC (SI-CT), 5-pin TO-220 (CI), and in the TO-263 (YI) surface mount packages. CT or 'Cool Tab' for the 28- pin SOIC package refers to the backside metal heatsink tab. Ordering Information Part Num ber Package Type Tem p. Range Configuration IXDD430YI 5-pin TO-263 Non Inverting with -55°C to +125° Enable IXDD430CI 5-pin TO-220 IXDI430YI 5-pin TO-263 -55°C to +125° Inverting IXDI430CI 5-pin TO-220 IXDN430YI 5-pin TO-263 -55°C to +125° Non Inverting IXDN430CI 5-pin TO-220 Inverting / Non -55°C to +125° IXDS430SI 28-pin SOIC Inverting with Enable and UVSEL Copyright © IXYS CORPORATION 2004 DS99045B(8/04) First Release IXDN430 / IXDI430 / IXDD430 / IXDS430 Figure 1A - IXDD430 (Non Inverting With Enable) Diagram Vcc Vcc 400k OUT P 1K IN OUT N EN GND GND Figure 1B - IXDN430 (Non-Inverting) Diagram Vcc Vcc OUT P 1K IN OUT N GND GND Figure 1C - IXDI430 (Inverting) Diagram Vcc Vcc OUT P 1K IN OUT N GND GND Figure 1D - IXDS430 (Inverting and Non Inverting with Enable) Diagram Vcc Vcc OUT P 1K IN 400K OUT N EN 400K INV GND GND Note: Out P and Out N are connected together in the 5 lead TO-220 and TO-263 packages. 2 IXDN430 / IXDI430 / IXDD430 / IXDS430 Absolute Maximum Ratings (Note 1) Operating Ratings Param eter Value Parameter Value Maxim um Junction Tem perature o 150 C Supply Voltage 40 V Operating Temperature Range o o All Other Pins -0.3 V to V + 0.3 V -55 C to 125 C CC Therm al Impedance TO220 (CI), TO263 (YI) o Power Dissipation, T ≤25 C AMBIENT θ (Junction To Case) o JC 0.95 C/W TO220 (CI), TO263 (YI) 2W o θJA (Junction To Ambient) 62.5 C/W Derating Factors (to Ambient) Therm al Impedance 28 pin SOIC with Heat Slug (SI) TO220 (CI), TO263 (YI) o 0.016W/ C θ (Junction To Case) o JC 3 C/W Storage Temperature o o -65 C to 150 C Lead Temperature (10 sec) o 300 C Electrical Characteristics o Unless otherwise noted, T = 25 C, 8.5V ≤ V ≤ 35V . A CC All voltage measurements with respect to GND. IXDD430 configured as described in Test Conditions. Symbol Parameter Test Conditions Min Typ Max Units V High input voltage 3.5 V IH 4.5V ≤ V ≤ 18V CC V Low input voltage 0.8 V IL 4.5V ≤ V ≤ 18V CC V Input voltage range -5 V + 0.3 V IN CC I Input current -10 10 IN 0V ≤ V ≤ V µA IN CC V High output voltage V - 0.025 V OH CC V Low output voltage 0.025 V OL ROH Output resistance VCC = 18V 0.3 0.4 Ω @ Output high R Output resistance V = 18V 0.2 0.3 OL CC Ω @ Output Low I Peak output current V = 18V 30 A PEAK CC I Continuous output Limited by package power 8 A DC current dissipation V Enable voltage range IXDD430 Only - 0.3 Vcc + 0.3 V EN V High En Input Voltage IXDD430 Only 2/3 Vcc V ENH V Low En Input Voltage IXDD430 Only 1/3 Vcc V ENL R EN Input Resistance IXDS430 Only 400 Kohm EN V INV Voltage Range IXDS430 Only - 0.3 Vcc + 0.3 V INV V INVH High INV Input Voltage IXDS430 Only 2/3 Vcc V V Low INV Input Voltage IXDS430 Only 1/3 Vcc V INVL R INV Input Resistance IXDS430 Only 400 Kohm INV t Rise time C =5600pF Vcc=18V 18 20 ns R L t Fall time C =5600pF Vcc=18V 16 18 ns F L t On-time propagation C =5600pF Vcc=18V 41 45 ns ONDLY L delay t Off-time propagation C =5600pF Vcc=18V 35 39 ns OFFDLY L delay t Enable to output high IXDD430 Only, Vcc=18V 47 ns ENOH delay time t Disable to output low IXDD430 Only, Vcc=18V 120 ns DOLD delay time V Power supply voltage 8.5 18 35 V CC I Power supply current V = 3.5V 1 3 mA CC IN V = 0V 0 10 IN µA V = + V 10 IN CC µA Specifications Subject To Change Without Notice Note 1: Operating the device beyond parameters with listed “absolute maximum ratings” may cause permanent damage to the device. Typical values indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. The guaranteed specifications apply only for the test conditions listed. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 3 IXDN430 / IXDI430 / IXDD430 / IXDS430 Electrical Characteristics o o Unless otherwise noted, temperature over -55 C to +125 C, 4.5 ≤ V ≤ 35V . CC All voltage measurements with respect to GND. IXDD430 configured as described in Test Conditions. Symbol Parameter Test Conditions Min Typ Max Units V High input voltage 3.2 V IH 4.5V ≤ V ≤ 18V CC V Low input voltage 1.1 V IL 4.5V ≤ V ≤ 18V CC V Input voltage range -5 V + 0.3 V IN CC R Output resistance V = 18V 0.46 OH CC Ω @ Output high R Output resistance V = 18V 0.4 OL CC Ω @ Output Low t Rise time C =5600pF Vcc=18V 20 ns R L t Fall time C =5600pF Vcc=18V 18 ns F L t On-time propagation C =5600pF Vcc=18V 58 ns ONDLY L delay t Off-time propagation C =5600pF Vcc=18V 51 ns OFFDLY L delay V Power supply voltage 8.5 18 35 V CC 5-lead TO-220 Outline (IXD_430CI) 5-lead TO-263 Outline (IXD_430YI) 28-pin SOIC Outline (IXD_430SI) NOTE: Mounting tabs, solder tabs, or heat sink metalization on all packages are connected to ground. 4 IXDN430 / IXDI430 / IXDD430 / IXDS430 Pin Configurations Vcc 1 28 Vcc Vcc 2 27 Vcc Vcc 3 26 Vcc Vcc 4 25 Vcc N/C 5 28 Pin SOIC 24 OUT P 1 Vcc UVSEL 6 (SI-CT) 23 OUT P 2 OU T N/C 7 22 OUT P GND 3 IN 8 21 OUT N 4 IN EN 9 20 OUT N 5 E N * INV 10 19 OUT N GND 11 18 GND TO220 (CI) GND 12 17 GND TO263 (YI) GND 13 16 GND GND 14 15 GND Pin Description SYMBOL FUNCTION DESCRIPTION Positive power-supply voltage input. This pin provides power to the VCC Supply Voltage entire chip. The range for this voltage is from 8.5V to 35V. IN Input Input signal-TTL or CMOS compatible. The system enable pin. This pin, when driven low, disables the chip, EN * Enable forcing high impedance state to the output (IXDD430 Only). Forcing INV low causes the IXDS430 to become non-inverted, while INV Invert forcing INV high causes the IXDS430 to become inverted. Respective P and N driver outputs. For application purposes this pin OUT P is connected, through a resistor, to Gate of a MOSFET/IGBT. The P Output OUT N and N output pins are connected together in the TO-263 and TO-220 packages. The system ground pin. Internally connected to all circuitry, this pin provides ground reference for the entire chip. This pin should be GND Ground connected to a low noise analog ground plane for optimum performance. Select Under With UVSEL connected to Vcc, IXDS430 outputs go low at Vcc < UVSEL Voltage Level 8.5V; With UVSEL open, under voltage level is set at Vcc < 12.5V * This pin is used only on the IXDD430, and is N/C (not connected) on the IXDI430 and IXDN430. CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD procedures when handling and assembling this component. Figure 2 - Characteristics Test Diagram . . Vcc Vcc + OUT C BYPASS/ - IXDD430 GND FILTER C LOAD IN EN + Vin - 5 IXDN430 / IXDI430 / IXDD430 / IXDS430 Typical Performance Characteristics Fig. 3 Fig. 4 Rise Times vs. Supply Voltage Fall Times vs. Supply Voltage 35 30 30 25 15000 pF 15000 pF 25 20 10000 pF 10000 pF 20 5600 pF 15 5600 pF 15 10 10 1000 pF 1000 pF 5 5 0 0 10 15 20 25 30 35 10 15 20 25 30 35 Supply Voltage (V) Supply Voltage (V) Fig. 6 Output Fall Times vs. Load Capacitance Fig. 5 Output Rise Times vs. Load Capacitance 30 13V 30 18V 35V 25 35V 25 18V 13V 20 20 15 15 10 10 5 5 0 1000 3000 5000 7000 9000 11000 13000 15000 1000 3000 5000 7000 9000 11000 13000 15000 Load Capacitance (pF) Load Capacitance (pF) Rise and Fall Times vs. Temperature Max / Min Input vs. Temperature Fig. 7 Fig. 8 C = 5600 pF, Vcc = 18V CL = 5600pF, Vcc = 18V L 25 4 3.5 Min Input High 20 t R 3 Max Input Low 2.5 15 t F 2 10 1.5 1 5 0.5 0 0 -60 -10 40 90 140 190 -60 -10 40 90 140 190 Temperature (C) Temperature (C) 6 Rise Time (ns) Rise Time (ns) Time (ns) Fall Time (ns) Max / Min Input Voltage Fall Time (ns) IXDN430 / IXDI430 / IXDD430 / IXDS430 Supply Current vs. Load Capacitance Fig. 9 Supply Current vs. Frequency Fig. 10 Vcc = 13V Vcc = 13V 300 1000 15000 pF 2 MHz 10000 pF 5600 pF 1000 pF 250 100 1 MHz 200 10 150 500 kHz 100 1 50 100 kHz 50 kHz 10 kHz 0.1 0 1 10 100 1000 10000 1000 10000 100000 Frequency (kHz) Load Capacitance (pF) Supply Current vs. Load Capacitance Fig. 11 Fig. 12 Supply Current vs. Frequency Vcc = 18V Vcc = 18V 300 15000 pF 1000 10000 pF 2 MHz 1 MHz 5600 pF 1000 pF 250 100 200 500 kHz 150 10 100 1 50 z 100 kH 50 kHz 10 kHz 0 0.1 1000 10000 100000 1 10 100 1000 10000 Frequency (kHz) Load Capacitance (pF) Supply Current vs. Frequency Fig. 14 Fig. 13 Supply Current vs. Load Capacitance Vcc = 25V Vcc = 25V 15000 pF 1000 400 10000 pF 5600 pF 1000 pF 350 2 MHz 1 MHz 100 300 250 10 200 500 kHz 150 1 100 100 kHz 50 50 kHz 10 kHz 0 0.1 1000 10000 100000 1 10 100 1000 10000 Frequency (kHz) Load Capacitance (pF) 7 Supply Current (mA) Supply Current (mA) Supply Current (mA) Supply Current (mA) Supply Current (mA) Supply Current (mA) IXDN430 / IXDI430 / IXDD430 / IXDS430 Fig. 15 Supply Current vs. Load Capacitance Fig. 16 Supply Current vs. Frequency Vcc = 35V Vcc = 35V 15000 pF 400 1000 10000 pF 5600 pF 350 1000 pF 1 MHz 300 500 kHz 100 250 200 150 10 100 100 kHz 50 kHz 50 10 kHz 1 0 1000 10000 100000 1 10 100 1000 10000 Load Capacitance (pF) Frequency (kHz) Propagation Delay vs. Input Voltage Fig. 18 Propagation Delay vs. Supply Voltage Fig. 17 C = 5600 pF Vcc = 18V L C = 5600 pF Vin = 15V@1kHz L 50 50 45 45 t ONDLY tONDLY 40 40 35 35 t OFFDLY t OFFDLY 30 30 25 25 20 20 15 15 10 10 5 5 0 0 10 15 20 25 30 35 5 10152025 Input Voltage (V) Supply Voltage (V) Fig. 20 Fig. 19 Quiescent Supply Current vs. Temperature Propagation Delay Times vs. Temperature Vcc = 18V, Vin = 15V@1kHz, C = 5600pF L C = 5600pF, Vcc = 18V L 0.6 70 60 0.5 50 0.4 t ONDLY 40 0.3 t OFFDLY 30 0.2 20 0.1 10 0 0 -60 -10 40 90 140 190 -60 -10 40 90 140 190 Temperature (C) Temperature (C) 8 Supply Current (mA) Propagation Delay (ns) Time (ns) Supply Current (mA) Quiescent Vcc Input Current (mA) Propagation Delay (ns) IXDN430 / IXDI430 / IXDD430 / IXDS430 High State Output Resistance vs. Supply Voltage Fig. 21 Fig. 22 Low State Output Resistance vs. Supply Voltage 0.25 0.35 0.3 0.2 0.25 0.15 0.2 0.15 0.1 0.1 0.05 0.05 0 0 10 15 20 25 30 35 40 10 15 20 25 30 35 40 Supply Voltage (V) Supply Voltage (V) Fig. 23 P Channel Output Current vs. Vcc Fig. 24 N Channel Output Current vs. Vcc 0 70 -10 60 -20 50 -30 40 -40 30 -50 20 -60 10 -70 -80 0 10 15 20 25 30 35 40 10 15 20 25 30 35 40 Vcc (V) Vcc (V) Fig. 25 P Channel Output Current vs. Temperature N Channel Output Current vs. Temperature Fig. 26 Vcc = 18V Vcc = 18V 40 45 40 35 35 30 30 25 25 20 20 15 15 10 10 5 5 0 0 -60 -10 40 90 140 190 -60 -10 40 90 140 190 Temperature (C) Temperature (C) 9 P Channel Output Current (A) P Channel Output Current (A) High State Output Resistance (Ohms) N Channel Output Current (A) Low State Output Resistance (Ohms) N Channel Output Current (A) IXDN430 / IXDI430 / IXDD430 / IXDS430 Figure 27 - Typical circuit to decrease di/dt during turn-off Figure 28 - IXDD430 Application Test Diagram + VB Ld - 10uH Rd IXDD430 0.1ohm VCC Rg VCCA High_Power OUT VMO580-02F IN 1ohm Rsh EN 1.5k ohm + + VCC VIN GND - - SUB Rs Low_Power 2N7002/PLP Ls R+ 10kohm 20nH One Shot Circuit Rcomp 0 Comp 5kohm + LM339 NAND V+ NOT2 C+ NOT1 CD4011A CD4049A V- CD4049A 100pF Ccomp - Ros 1pF + R 1Mohm - REF Cos Q 1pF NOT3 NOR1 S CD4049A CD4001A EN NOR2 CD4001A SR Flip-Flop 10 IXDN430 / IXDI430 / IXDD430 / IXDS430 APPLICATIONS INFORMATION Short Circuit di/dt Limit A short circuit in a high-power MOSFET module such as the In this way, the high-power MOSFET module is softly turned off VM0580-02F, (580A, 200V), as shown in Figure 27, can cause by the IXDD430, preventing its destruction. the current through the module to flow in excess of 1500A for 10µs or more prior to self-destruction due to thermal runaway. For this reason, some protection circuitry is needed to turn off Supply Bypassing and Grounding Practices, the MOSFET module. However, if the module is switched off Output Lead inductance too fast, there is a danger of voltage transients occuring on the drain due to Ldi/dt, (where L represents total inductance in When designing a circuit to drive a high speed MOSFET series with drain). If these voltage transients exceed the utilizing the IXDD430/IXDI430/IXDN430, it is very important to MOSFET's voltage rating, this can cause an avalanche break- keep certain design criteria in mind, in order to optimize down. performance of the driver. Particular attention needs to be paid to Supply Bypassing, Grounding, and minimizing the Output The IXDD430 has the unique capability to softly switch off the Lead Inductance. high-power MOSFET module, significantly reducing these Ldi/dt transients. Say, for example, we are using the IXDD430 to charge a 15nF capacitive load from 0 to 25 volts in 25ns. Thus, the IXDD430 helps to prevent device destruction from both dangers; over-current, and avalanche breakdown due to Using the formula: I= C ∆V / ∆t, where ∆V=25V C=15nF & di/dt induced over-voltage transients. ∆t=25ns we can determine that to charge 15nF to 25 volts in 25ns will take a constant current of 15A. (In reality, the charging The IXDD430 is designed to not only provide ±30A under current won’t be constant, and will peak somewhere around normal conditions, but also to allow it's output to go into a high 30A). impedance state. This permits the IXDD430 output to control a separate weak pull-down circuit during detected overcurrent SUPPLY BYPASSING shutdown conditions to limit and separately control d /dt gate VGS In order for our design to turn the load on properly, the IXDD430 turnoff. This circuit is shown in Figure 28. must be able to draw this 5A of current from the power supply in the 25ns. This means that there must be very low impedance Referring to Figure 28, the protection circuitry should include between the driver and the power supply. The most common a comparator, whose positive input is connected to the source method of achieving this low impedance is to bypass the power of the VM0580-02. A low pass filter should be added to the input supply at the driver with a capacitance value that is a magnitude of the comparator to eliminate any glitches in voltage caused larger than the load capacitance. Usually, this would be by the inductance of the wire connecting the source resistor to achieved by placing two different types of bypassing capacitors, ground. (Those glitches might cause false triggering of the with complementary impedance curves, very close to the driver comparator). itself. (These capacitors should be carefully selected, low inductance, low resistance, high-pulse current-service The comparator's output should be connected to a SRFF(Set capacitors). Lead lengths may radiate at high frequency due Reset Flip Flop). The flip-flop controls both the Enable signal, to inductance, so care should be taken to keep the lengths of and the low power MOSFET gate. Please note that CMOS the leads between these bypass capacitors and the IXDD430 4000-series devices operate with a V range from 3 to 15 VDC, CC to an absolute minimum. (with 18 VDC being the maximum allowable limit). GROUNDING A low power MOSFET, such as the 2N7000, in series with a In order for the design to turn the load off properly, the IXDD430 resistor, will enable the VMO580-02F gate voltage to drop must be able to drain this 5A of current into an adequate gradually. The resistor should be chosen so that the RC time grounding system. There are three paths for returning current constant will be 100us, where "C" is the Miller capacitance of that need to be considered: Path #1 is between the IXDD430 the VMO580-02F. and it’s load. Path #2 is between the IXDD430 and it’s power supply. Path #3 is between the IXDD430 and whatever logic is For resuming normal operation, a Reset signal is needed at driving it. All three of these paths should be as low in resistance the SRFF's input to enable the IXDD430 again. This Reset can and inductance as possible, and thus as short as practical. In be generated by connecting a One Shot circuit between the addition, every effort should be made to keep these three IXDD430 Input signal and the SRFF restart input. The One Shot ground paths distinctly separate. Otherwise, (for instance), the will create a pulse on the rise of the IXDD430 input, and this returning ground current from the load may develop a voltage pulse will reset the SRFF outputs to normal operation. that would have a detrimental effect on the logic line driving the IXDD430. When a short circuit occurs, the voltage drop across the low- value, current-sensing resistor, (Rs=0.005 Ohm), connected between the MOSFET Source and ground, increases. This triggers the comparator at a preset level. The SRFF drives a low input into the Enable pin disabling the IXDD430 output. The SRFF also turns on the low power MOSFET, (2N7000). 11 IXDN430 / IXDI430 / IXDD430 / IXDS430 OUTPUT LEAD INDUCTANCE Of equal importance to Supply Bypassing and Grounding are A TTL or 5V CMOS logic low, V =~<0.8V, input applied to the TTLLOW issues related to the Output Lead Inductance. Every effort Q1 emitter will drive it on. This causes the level translator should be made to keep the leads between the driver and it’s output, the Q1 collector output to settle to V + CESATQ1 load as short and wide as possible. If the driver must be placed V =<~2V, which is sufficiently low to be correctly interpreted TTLLOW farther than 2” from the load, then the output leads should be as a high voltage CMOS logic low (<1/3V =5V for V =15V given CC CC treated as transmission lines. In this case, a twisted-pair in the IXDD430 data sheet.) should be considered, and the return line of each twisted pair should be placed as close as possible to the ground pin of the A TTL high, V =>~2.4V, or a 5V CMOS high, TTLHIGH driver, and connect directly to the ground terminal of the load. V =~>3.5V, applied to the EN input of the circuit in 5VCMOSHIGH Figure 29 will cause Q1 to be biased off. This results in Q1 TTL to High Voltage CMOS Level Translation collector being pulled up by R3 to V =15V, and provides a CC (IXDD430 Only) high voltage CMOS logic high output. The high voltage CMOS logical EN output applied to the IXDD430 EN input will enable it, allowing the gate driver to fully function as an 30 Amp The enable (EN) input to the IXDD430 is a high voltage CMOS logic level input where the EN input threshold is ½ output driver. V , and may not be compatible with 5V CMOS or TTL input CC The total component cost of the circuit in Figure 29 is less levels. The IXDD430 EN input was intentionally designed than $0.10 if purchased in quantities >1K pieces. It is for enhanced noise immunity with the high voltage CMOS recommended that the physical placement of the level logic levels. In a typical gate driver application, V =15V CC and the EN input threshold at 7.5V, a 5V CMOS logical high translator circuit be placed close to the source of the TTL or input applied to this typical IXDD430 application’s EN input CMOS logic circuits to maximize noise rejection. will be misinterpreted as a logical low, and may cause undesirable or unexpected results. The note below is for optional adaptation of TTL or 5V CMOS levels. The circuit in Figure 29 alleviates this potential logic level misinterpretation by translating a TTL or 5V CMOS logic input to high voltage CMOS logic levels needed by the IXDD430 EN input. From the figure, V is the gate driver CC power supply, typically set between 8V to 20V, and V is DD the logic power supply, typically between 3.3V to 5.5V. Resistors R1 and R2 form a voltage divider network so that the Q1 base is positioned at the midpoint of the expected TTL logic transition levels. Figure 29 - TTL to High Voltage CMOS Level Translator (From gate driver Vcc power supply) Vdd (From logic power supply) R3 10K R1 10K High Voltage CMOS EN output (To IXDD430 EN input) Q1 2N3904 R2 10K 5V CMOS or TTL input EN IXYS Corporation IXYS Semiconductor GmbH 3540 Bassett St; Santa Clara, CA 95054 Edisonstrasse15 ; D-68623; Lampertheim Tel: 408-982-0700; Fax: 408-496-0670 Tel: +49-6206-503-0; Fax: +49-6206-503627 www.ixys.com e-mail: marcom@ixys.de e-mail: sales@ixys.net 12 This datasheet has been download from: www.datasheetcatalog.com Datasheets for electronics components.