CPC5622 ® LITELINK III Phone Line Interface IC (DAA) INTEGRATED CIRCUITS DIVISION Features Description • Superior voice solution with low noise and excellent LITELINK III is a single-package silicon phone line part-to-part gain accuracy interface (PLI) DAA used in voice and data • 3 kV line isolation communication applications to make connections RMS between low-voltage equipment and high-voltage • Simultaneous ringing detection and CID monitoring telephone networks. for worldwide applications • Provides both full-wave ringing detect and half-wave LITELINK uses on-chip optical components and a few ringing detect for maximum versatility inexpensive external components to form the required • Transmit power of up to +10 dBm into 600  high voltage isolation barrier. LITELINK eliminates the • Data access arrangement (DAA) solution for modem need for large isolation transformers or capacitors speeds up to V.92 used in other phone line interface configurations. • 3.3V or 5 V power supply operation LITELINK also provides AC and DC phone line • Easy interface with modem ICs and voice CODECs terminations, switchhook, 2-wire to 4-wire hybrid, • Worldwide dial-up telephone network compatibility ringing detection, and full time receive on-hook • CPC5622 can be used in circuits that comply with transmission capability. the requirements of TIA/EIA/IS-968 (FCC part 68), UL60950 (UL1950), EN/IEC 60950-1 The CPC5622 is a member of, and builds upon, IXYS Supplementary Isolation Compliant, IEC60950, Integrated Circuits Division’s third generation of EN55022B, CISPR22B, EN55024, and TBR-21 LITELINK products with improved insertion loss • Line-side circuit powered from telephone line performance and lower minimum current draw from • Compared to other silicon DAA solutions, LITELINK: the phone line. The CPC5622 version of LITELINK III - Uses fewer passive components provides concurrent ringing detection and CID - Takes up less printed-circuit board space monitoring for world wide applications. Both half-wave - Uses less telephone line power and full-wave ringing detection are provided for - Is a single-IC solution maximum versatility. Applications Ordering Information • Computer telephony and gateways, such as VoIP Part Number Description • PBXs • Satellite and cable set-top boxes CPC5622A 32-Pin SOIC Phone Line Interface, 50/tube • V.92 (and other standard) modems 32-Pin SOIC Phone Line Interface, CPC5622ATR • Fax machines tape and reel, 1000/reel • Voicemail systems • Embedded modems for POS terminals, automated CPC5622 Block Diagram banking, remote metering, vending machines, security, and surveillance Isolation Barrier Tx+ Transmit Diff. TIP Amplifier Tx- Transmit Isolation Tx. MODE Amplifier Gain Trim Transconductance Stage 2-4 Wire Hybrid OH AC/DC Termination Hook Switch Rx. Gain Receive Trim Isolation Amplifier RING Rx+ Receive Diff. Rx- Amplifier Rx Amp & Ringing Det. Ringing Detect Outputs C SNOOP R SNOOP Half Wave RING Snoop C SNOOP Full Wave R Amplifier SNOOP RING2 Pb e3 DS-CPC5622-R03 www.ixysic.com 1 3kV rms Isolation CPC5622 INTEGRATED CIRCUITS DIVISION 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.3 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2. Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 Resistive Termination Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1.1 Resistive Termination Application Circuit Part List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 Reactive Termination Application Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2.1 Reactive Termination Application Circuit Part List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3. Using LITELINK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 Switch Hook Control (On-hook and Off-hook States) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2 On-hook Operation: OH=1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2.1 Ringing Signal Reception via the Snoop Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.3 Off-Hook Operation: OH=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3.1 Receive Signal Path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3.2 Transmit Signal Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.4 Initialization Requirement Following Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.5 DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.5.1 Setting a Current Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.6 AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.6.1 Resistive Termination Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.6.2 Reactive Termination Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.6.3 Mode Pin Usage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4. Regulatory Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5. LITELINK Design Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6. LITELINK Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7. Manufacturing Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.1 Mechanical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2 www.ixysic.com R03 CPC5622 INTEGRATED CIRCUITS DIVISION 1. Electrical Specifications 1.1 Absolute Maximum Ratings Absolute maximum ratings are stress ratings. Parameter Minimum Maximum Unit Stresses in excess of these ratings can cause V -0.3 6 V permanent damage to the device. Functional DD operation of the device at conditions beyond those V + 0.3 Logic Inputs -0.3 V DD indicated in the operational sections of this data sheet Continuous Tip to Ring is not implied. -150 mA Current (R = 5.2) ZDC Total Package Power -1 W Dissipation V Isolation Voltage - 3000 rms Operating temperature -40 +85 °C Storage temperature -40 +125 °C Unless otherwise specified all specifications are at 25C and V =5.0V. DD R03 www.ixysic.com 3 CPC5622 INTEGRATED CIRCUITS DIVISION 1.2 Performance Parameter Minimum Typical Maximum Unit Conditions DC Characteristics Operating Voltage V 3.0 - 5.5 V Low-voltage side DD Operating Current I - 9 13 mA Low-voltage side DD Operating Voltage V 2.8 - 3.2 V Line side, derived from tip and ring DDL Operating Current I - 7 8 mA Line side, drawn from tip and ring while off-hook DDL On-hook Characteristics Metallic DC Resistance 10 - - M Tip to ring, 100 Vdc applied Longitudinal DC Resistance 10 - - M 150 Vdc applied from tip and ring to Earth ground Ringing Signal Detect Level 5 - - V 68 Hz ringing signal applied across tip and ring rms Ringing Signal Detect Level 28 - - V 15 Hz ringing signal applied across tip and ring rms -3 dB corner frequency @ 166 Hz, in IXYS Integrated Snoop Circuit Frequency Response 166 - >4000 Hz Circuits Division application circuit 120 V 60 Hz common-mode signal across tip and RMS 1 -40- dB Snoop Circuit CMRR ring Ringer Equivalence - 0.01B - REN 1 60 - - dB Per FCC part 68 Longitudinal Balance Off-Hook Characteristics AC Impedance - 600 -  Tip to ring, using resistive termination application circuit 1 60 - - dB Per FCC part 68 Longitudinal Balance Return Loss - 26 - dB Into 600  at 1800 Hz Transmit and Receive Characteristics Frequency Response 30 - 4000 Hz -3 dB corner frequency 30 Hz Into 600  at 1800 Hz, with C18 in the resistive Transhybrid Loss - 36 - dB termination application circuit 30 Hz to 4 kHz, Resistive termination application circuit with MODE Transmit and Receive Insertion Loss -0.4 0 0.4 dB de-asserted. Reactive termination application circuit with MODE asserted. Average In-band Noise - -126 - dBm/Hz 4 kHz flat bandwidth nd Harmonic Distortion - -80 - dB -3 dBm, 600 Hz, 2 harmonic V Transmit Level - - 2.2 Single-tone sine wave. Or 0 dBm into 600 . P-P V Receive Level - - 2.2 Single-tone sine wave. Or 0 dBm into 600  P-P RX+/RX- Output Drive Current - - 0.5 mA Sink and source TX+/TX- Input Impedance 60 90 120 k Isolation Characteristics V Isolation Voltage 3000 - - Line side to Low-voltage side, one minute duration rms Surge Rise Time 2000 - - V/S No damage via tip and ring MODE and OH Control Logic Inputs Input Low Voltage - - 0.8 V IL V Input High Voltage 2.0 - - IH V V High Level Input Current - - -120 A IN DD V = GND Low Level Input Current - - -120 A IN RING and RING2 Output Logic Levels V -0.4 I = -400 A Output High Voltage -- V DD OUT I = 1 mA Output Low Voltage - - 0.4 V OUT Specifications subject to change without notice. All performance characteristics based on the use of IXYS Integrated Circuits Division application circuits. Functional operation of the device at conditions beyond those specified here is not implied. NOTES: 1) This parameter is layout and component tolerance dependent. 4 www.ixysic.com R03 CPC5622 INTEGRATED CIRCUITS DIVISION 1.3 Pin Description Figure 1. Pinout Pin Name Function V 1 Low-voltage (CPE) side power supply DD 1 V REFL 32 DD 2 TXSM Transmit summing junction 2 TXSM 31 TXF 3 TX- ZTX 30 Negative differential transmit signal to DAA 3TX- 4 TX+ ZN 29 T from low-voltage side 5 TXSL 28 TX Positive differential transmit signal to DAA from 6 MODE BR 27 - 4TX+ 7 GND NT 26 low-voltage side S 8 GA 25 OH T 5 TX Transmit differential amplifier output 9 RING NT 24 F When asserted low, changes gain of TX path 10 DCS 23 RING2 1 11 DCS 22 RX- 2 6MODE (-7 dB) and RX path (+7 dB) to accommodate 12 21 RX+ ZD C reactive termination networks 13 BR 20 SNP+ - 7 GND Low-voltage (CPE) side analog ground 14 RP 19 SNP- B 15 RX 18 S RXF 8OH Assert logic low for off-hook operation 16 V 17 RX DDL 9RING Half wave ringing detect output signal 10 RING2 Full wave ringing detect output signal Negative differential analog signal received 11 RX- from the telephone line. Must be AC coupled with 0.1 F. Positive differential analog signal received from 12 RX+ the telephone line. Must be AC coupled with 0.1 F. 13 SNP+ Positive differential snoop input 14 SNP- Negative differential snoop input 15 RXF Receive photodiode amplifier output 16 RX Receive photodiode summing junction Power supply for line side, regulated from tip V 17 DDL and ring. 18 RXS Receive isolation amp summing junction 19 RPB Receive LED pre-bias current set 20 BR- Bridge rectifier return 21 ZDC Electronic inductor DCR/current limit 22 DCS2 DC feedback output 23 DCS1 V to I slope control 24 NTF Network amplifier feedback 25 GAT External MOSFET gate control 26 NTS Receive signal input 27 BR- Bridge rectifier return 28 TXSL Transmit photodiode summing junction 29 ZNT Receiver impedance set 30 ZTX Transmit transconductance gain set 31 TXF Transmit photodiode amplifier output 1.25 V reference 32 REFL DC R03 www.ixysic.com 5 CPC5622 INTEGRATED CIRCUITS DIVISION 2. Application Circuits LITELINK can be used with telephone networks The application circuits that follow address both types worldwide. Some public telephone networks, notably of line termination models. A reactive termination in North America and Japan require a resistive line application circuit that describes the TBR-21 termination. Other telephone networks, such as in implementation is shown in Figure 3 on page 8. This Europe, China and elsewhere, require a reactive line circuit can be easily adapted for other reactive termination. termination needs. 2.1 Resistive Termination Application Circuit Figure 2. Resistive Termination Application Circuit Schematic 3.3 or 5V 2 R23 C1 10 1μ FB1 C16 600 Ω 10μ 200 mA A C9 U1 A 0.1μ R1 32 1 REFL VDD LITELINK (R ) TX BR- 80.6K 2 31 TXSM TXF 30 C13 0.1μ 3 - TX- ZTX TX CPC5622 C2 0.1μ 29 R5 4 TX+ ZNT + TX C10 (R ) TXF 0.01μ 60.4K 5 28 TX TXSL 500V R75 R13 27 6 (R ) MODE BR- (R ) BR- NTX NTS 261K 1M A R22 7 26 GND NTS (R ) R14 DCS1A Q1 6.49 M (R ) GAT 8 25 OH GAT CPC5602C OH R12 C21 47 R21 (R ) NTF 100p 24 9 5% RING NTF RING (R ) (C ) DCS1B C15 BR- GAT 499K 6.49M 0.01μ 10 23 RING2 DCS1 RING2 500V C12 R15 R20 (R ) (C ) 0.1μ DCS2 DCS BR- C14 11 22 (R ) RX- DCS2 VDDL RX- 0.027μ 2 1.69M BR- 5% C4 0.1μ 21 12 RX+ ZDC RX+ R16 3 + (R ) DB1 ZDC 13 20 8.2 SNP+ BR- BR- 19 R76 (R ) 14 HTF SNP- RPB TIP 200K R8 18 (R ) HTX - 221K 15 RXF RXS R18 BR- 16 17 1 RX VDDL (R ) SP1 C18 ZTX 3 15p 3.32K R10 R4 BR- R2 (R ) (R ) RING (R ) ZNT PB RXF 68.1 301 130K BR- BR- C7 4 (C ) R6 R44 SNP- (R ) (R ) 220pF SNP-2 SNP-1 1.8M 1.8M R3 (R ) SNPD R7 R45 1.5M (R ) (R ) SNP+2 SNP+1 1.8M 1.8M C8 4 (C ) SNP+ 220pF NOTE: Unless otherwise noted: Resistor values are in Ohms All resistors are 1%. Capacitor values are in Farads. ¹This design was tested and found to comply with FCC Part 68 with this ³Optional for enhanced transhybrid loss. Sidactor. Other compliance requirements may require a different part. 4 Use voltage ratings based on the isolation requirements of your ²Higher-noise power supplies may require substitution of a 220 H inductor, application. Toko 380HB-2215 or similar. See the Power Quality section of IXYS Integrated Circuits Division application note AN-146, Guidelines for Effective LITELINK Designs for more information. 6 www.ixysic.com R03 CPC5622 INTEGRATED CIRCUITS DIVISION 2.1.1 Resistive Termination Application Circuit Part List Quantity Reference Designator Description Supplier(s) 1C1 1 F, 16 V, ±10% 5 C2, C4, C9, C13, C14 0.1 F, 16 V, ±10% 1 2 220 pF, ±5% C7, C8 2 C10, C15 0.01 F, 500 V, ±10% AVX, Murata, Novacap, Panasonic, SMEC, Tecate, etc. 1 C12 0.027 F, 16 V, ±10% 1C16 10 F, 16 V, ±10% 1 C18 (optional) 15 pF, 16 V, ±10% 1 C21 100 pF, 16 V, 10% 1 R1 80.6 k, 1/16 W, ±1% 1 R2 130 k, 1/16 W, ±1% 1 R3 1.5 M, 1/16 W, ±1% 1 R4 68.1 , 1/16 W, ±1% 1 R5 60.4 k, 1/16 W, ±1% 2 4 1.8 M, 1/10 W, ±1% R6, R7, R44, R45 1 R8 221 k, 1/16 W, ±1% 1 R10 301 , 1/16 W, ±1% 1 R12 499 k, 1/16 W, ±1% Panasonic, Electro Films, FMI, Vishay, 1R13 1 M, 1/16 W, ±1% etc. 1R14 47 , 1/16 W, ±5% 1 R15 1.69 M, 1/16 W, ±1% 1 R16 8.2 , 1/8 W, ±1% 1 R18 3.32 k 1/16 W, ±1% 1R20 2 , 1/16 W, ±5% 1 R21, R22 6.49 M, 1/16 W, ±1% 1R23 10  1/16 W, ±5%, or 220 H inductor 1 R75 261 k, 1/16 W, ±1% 1 R76 200 k, 1/16 W, ±1% 1 FB1 600 , 200 mA ferrite bead Murata BLM11A601S or similar 1 DB1 S1ZB60 bridge rectifier Shindengen, Diodes, Inc. Bourns (TISP4350H3) or 1 SP1 350 V Teccor (P3100SC) 1 Q1 CPC5602 FET IXYS Integrated Circuits Division 1 U1 CPC5622 LITELINK 1 Use voltage ratings based on the isolation requirements of your application. Typical applications will require 2kV to safely hold off the isolation voltage. 2 Use components that allow enough space to account for the possibility of high-voltage arcing. R03 www.ixysic.com 7 CPC5622 INTEGRATED CIRCUITS DIVISION 2.2 Reactive Termination Application Circuit Figure 3. Reactive Termination Application Circuit Schematic 3.3 or 5V 2 R23 10 C1 1μ FB1 C16 600 Ω 10μ 200 mA A C9 U1 A 0.1μ R1 1 32 VDD REFL LITELINK (R ) TX BR- 80.6K 2 31 TXSM TXF C13 0.1μ 30 3 TX- ZTX - TX C2 0.1μ R5 29 4 TX+ ZNT + TX (R ) C10 TXF 0.01μ 60.4K 28 5 TX TXSL 500V R75 R13 27 6 (R ) MODE BR- (R ) BR- NTX NTS 110K 1M A R22 26 7 GND NTS (R ) R14 DCS1A Q1 6.49M (R ) GAT 8 25 OH GAT CPC5602C OH R12 C21 47 R21 (R ) 100p NTF 9 24 RING NTF 5% (R ) RING C15 (C ) DCS1B BR- GAT 221K 6.49M 0.01μ 10 23 RING2 DCS1 RING2 500V C12 R15 R20 (R ) (C ) 0.1μ BR- C14 DCS2 DCS 22 (R ) 11 RX- DCS2 VDDL 0.027μ RX- 2 1.69M BR- 0.1μ 5% C4 21 12 RX+ ZDC RX+ R16 3 + (R ) DB1 ZDC 20 8.2 13 SNP+ BR- BR- 19 R76 (R ) 14 HTF SNP- RPB TIP 200K 18 - R8 (R ) 15 HTX RXF RXS 200K R18 BR- 16 17 1 RX VDDL (R ) SP1 ZTX R10 10K R4 (R ) 59 ZNT1 (R ) PB BR- R2 68.1 RING (R ) RXF C20 130K (C ) R11 BR- ZNT (R ) 169 ZNT2 0.68μ BR- C7 4 (C ) R6 R44 SNP- (R ) (R ) 220p SNP-2 SNP-1 1.8M 1.8M R3 (R ) SNPD R7 R45 1.5M (R ) (R ) SNP+1 SNP+2 1.8M 1.8M C8 4 (C ) SNP+ 220p NOTE: Unless otherwise noted: Resistor values are in Ohms All resistors are 1%. Capacitor values are in Farads. ¹This design was tested and found to comply with FCC Part 68 with this 3 R sets the loop-current limit, see “Setting a Current Limit” on ZDC Sidactor. Other compliance requirements may require a different part. page 13. Also see IXYS Integrated Circuits Division application note ²Higher-noise power supplies may require substitution of a 220 H inductor, AN-146 for heat sinking recommendations for the CPC5602C FET. Toko 380HB-2215 or similar. See the Power Quality section of IXYS 4 Use voltage ratings based on the isolation requirements of your Integrated Circuits Division application note AN-146, Guidelines for application. Effective LITELINK Designs for more information. 8 www.ixysic.com R03 CPC5622 INTEGRATED CIRCUITS DIVISION 2.2.1 Reactive Termination Application Circuit Part List Quantity Reference Designator Description Supplier 1C1 1 F, 16 V, ±10% 5 C2, C4, C9, C13, C14 0.1 F, 16 V, ±10% 1 2 220 pF, ±5% C7, C8 2 C10, C15 0.01 F, 500 V, ±10% AVX, Murata, Novacap, Panasonic, SMEC, Tecate, etc. 1 C12 0.027 F, 16 V, ±10% 1C16 10 F, 16 V, ±10% 1 C20 0.68 F, 16 V, ±10% 1 C21 100 pF, 16 V, 10% 1 R1 80.6 k, 1/16 W, ±1% 1 R2 130 k, 1/16 W, ±1% 1 R3 1.5 M, 1/16 W, ±1% 1 R4 68.1 , 1/16 W, ±1% 1 R5 60.4 k 1/16 W, ±1% 2 4 1.8 M, 1/10 W, ±1% R6, R7, R44, R45 1 R8 200 k, 1/16 W, ±1% 1R10 59 , 1/16 W, ±1% 1 R11 169 , 1/16 W, ±1% Panasonic, Electro Films, FMI, Vishay, 1 R12 221 k, 1/16 W, ±1% etc. 1R13 1 M, 1/16 W, ±1% 1R14 47 , 1/16 W, ±5% 1 R15 1.69 M, 1/16 W, ±1% 1 R16 8.2 , 1/8 W, ±1% 1R18 10 k, 1/16 W, ±1% 1R20 2 , 1/16 W, ±5% 1 R21, R22 6.49 M, 1/16 W, ±1% 1R23 10 , 1/16 W, ±5%, or 220 H inductor 1 R75 110 k, 1/16 W, ±1% 1 R76 200 k, 1/16 W, ±1% 1 FB1 600  200 mA ferrite bead Murata BLM11A601S or similar 1 DB1 S1ZB60 bridge rectifier Shindengen, Diodes, Inc. Bourns (TISP4350H3) or 1 SP1 350 V Teccor (P3100SC) 1 Q1 CPC5602 FET IXYS Integrated Circuits Division 1 U1 CPC5622 LITELINK 1 Use voltage ratings based on the isolation requirements of your application. Typical applications will require 2kV to safely hold off the isolation voltage. 2 Use components that allow enough space to account for the possibility of high-voltage arcing. R03 www.ixysic.com 9 CPC5622 INTEGRATED CIRCUITS DIVISION 3. Using LITELINK As a full-featured telephone line interface, LITELINK LITELINK’s ringing detector and CID amplifiers are performs the following functions: both active. • DC termination and V/I slope control Asserting OH low causes LITELINK to answer or • AC impedance control originate a call by entering the off-hook state. In the • 2-wire to 4-wire conversion (hybrid) off-hook state, loop current flows through LITELINK. • Current limiting • Ringing detect signalling reception 3.2 On-hook Operation: OH=1 • Caller ID signalling reception The LITELINK application circuit leakage current is • Switch hook less than 10 A with 100 V across ring and tip, LITELINK can accommodate specific application equivalent to greater than 10 M on-hook resistance. features without sacrificing basic functionality or 3.2.1 Ringing Signal Reception via the performance. Application features include, but are not limited to: Snoop Circuit In the on-hook state (OH not asserted), an internal • High transmit power operation multiplexer engages the snoop circuitry. This circuit • Pulse dialing simultaneously monitors the telephone line for two • Ground start conditions; incoming ringing signal and caller ID data • Loop start bursts. • Parallel telephone off-hook detection (line intrusion) • Battery reversal detection Refer to the application schematic diagram (see Figure • Line presence detection 2 on page 6). C7 (C ) and C8 (C ) provide a SNP- SNP+ • World-wide programmable operation high-voltage isolation barrier between the telephone line and SNP- and SNP+ input pins of the LITELINK This section of the data sheet describes LITELINK while coupling AC signals to the snoop amplifier. The operation in standard configuration for usual snoop circuit “snoops” the telephone line continuously operation. IXYS Integrated Circuits Division offers while drawing no dc current. In the LITELINK, the additional application information on-line (see Section 5 incoming ringing signals are compared to a reference on page 14) for the following topics: level. When the ringing signal exceeds the preset • Circuit isolation considerations threshold, the internal comparators generate the • Optimizing LITELINK performance RING and RING2 signals which are output from • Data Access Arrangement architecture LITELINK at pins 9 and 10, respectively. Selection of • LITELINK circuit descriptions which output to use is dependent upon the support • Surge protection logic responsible for monitoring and filtering the • EMI considerations ringing detect signals. To reduce or eliminate false ringing detects this signal should be digitally filtered Other specific application materials are also and qualified by the system as a valid ringing signal. A referenced in this section as appropriate. logic low output on RING or RING2 indicates that the LITELINK ringing signal detect threshold has been exceeded. In the absence of any incoming ac signal 3.1 Switch Hook Control (On-hook the RING and RING2 outputs are held high. and Off-hook States) The CPC5622 RING output signal is generated by a LITELINK operates in one of two conditions, on-hook half-wave ringing detector while the RING2 output is and off-hook. In the on-hook condition the telephone generated by a full-wave ringing detector. A half-wave line is available for calls. In the off-hook condition the ringing detector’s output frequency follows the telephone line is engaged. The OH control input is frequency of the incoming ringing signal from the used to place LITELINK in one of these two states. Central Office (CO) while a full-wave ringing detector’s With OH high, LITELINK is on-hook and ready to output frequency is twice that of the incoming signal. make or receive a call. Also while on-hook, Because RING is the output of a half-wave detector, it 10 www.ixysic.com R03 CPC5622 INTEGRATED CIRCUITS DIVISION will output one logic low pulse per cycle of the ringing 3.2.2 Polarity Reversal Detection in On-hook frequency. Also, because the RING2 is the output of a State full-wave detector it will output two logic low pulses The full-wave ringing detector in the CPC5622 makes per cycle of the ringing frequency. Hence, the it possible to detect an on-hook tip and ring battery nomenclature RING2 for twice the output pulses. polarity reversal using the RING2 output. When the polarity of the battery voltage applied to tip and ring The set-up of the ringing detector comparator causes reverses, a pulse on RING2 indicates the event. The the RING output pulses to remain low for most of one system logic must be able to discriminate a single half-cycle of the ringing signal and remains high for the pulse of approximately 1 msec when using the entire second half-cycle of the ringing signal. For the recommended external snoop circuit components RING2 output, the pulses remain low during most of from a valid ringing signal. both halves of the ringing cycle and returns high for only a short period near the zero-crossing of the 3.2.3 On-hook Caller ID Signal Reception ringing signal. Both of the ringing outputs remain high On-hook Caller IDentity (CID) data burst signals are during the silent interval between ringing bursts. coupled through the snoop components, buffered Hysteresis is employed in the LITELINK ringing through LITELINK and output at the RX+ and RX- detector circuit to improve noise immunity. pins. The ringing detection threshold depends on the values In North America, CID data signals are typically sent of R3 (R ), R6 & R44 (R ), R7 & R45 (R ), SNPD SNP- SNP+ between the first and second ringing signal while in C7 (C ), and C8 (C ). The value of these SNP- SNP+ other countries the CID information may arrive prior to components shown in the application circuits are any other signalling state. recommended for typical operation. The ringing detection threshold can be changed according to the In applications that transmit CID after the first ringing following formula: burst such as in North American, follow these steps to receive on-hook caller ID data via the LITELINK RX outputs: 750mV 2 1  V = ----------------- R +R + -------------------------------------- RINGPK SNP SNPD  TOTAL 2 R SNPD  f C RING SNP 1. Detect the first full ringing signal burst on RING or RING2. Where: 2. Monitor and process the CID data from the RX outputs. • R = R3 in the application circuits shown in this SNPD data sheet. For applications as in China and Brazil where CID may • RSNP = the total of R6, R7, R44, and R45 in TOTAL arrive prior to ringing, follow these steps to receive the application circuits shown in this data sheet. on-hook caller ID data via the LITELINK RX outputs: • C = C7 = C8 in the application circuits shown in SNP 1. Simultaneously monitor for CID data from the RX this data sheet. outputs and for ringing on RING or RING2. • And ƒ is the frequency of the ringing signal. RING 2. Process the appropriate signalling data. IXYS Integrated Circuits Division Application Note AN-117 Customize Caller ID Gain and Ring Detect Voltage Note: Taking LITELINK off-hook (via the OH pin) Threshold is a spreadsheet for trying different disconnects the snoop path from the receive outputs component values in this circuit. Changing the ringing and disables the ringing detector outputs RING and detection threshold will also change the caller ID gain RING2. and the timing of the polarity reversal detection pulse, CID gain from tip and ring to RX+ and RX- is if used. determined by: R03 www.ixysic.com 11 CPC5622 INTEGRATED CIRCUITS DIVISION To accommodate single-supply operation, LITELINK includes a small DC bias on the RX+ and RX- outputs 6R SNPD of 1.0 Vdc. Most applications should AC couple the GAIN  dB = 20log ------------------------------------------------------------------------------------------------- CID receive outputs as shown in Figure 4. 2 1  R +R + -------------------------- SNP SNPD TOTAL 2  fC SNP LITELINK may be used for differential or single-ended output as shown in Figure 4. Single-ended use will Where: produce 6 dB less signal output amplitude. Do not exceed 0 dBm referenced to 600  (2.2 V ) signal P-P • R = R3 in the application circuits in this data SNPD output level with the standard application circuits. See sheet. application note AN-157, Increased LITELINK III Transmit • RSNP = the total of R6, R7, R44, and R45 in TOTAL Power for more information. the application circuits in this data sheet. • C = C7 = C8 in the application circuits in this data SNP Figure 4. Differential and Single-ended Receive sheet. Path Connections to LITELINK • and ƒ is the frequency of the CID signal Low-Voltage Side CODEC LITELINK or Voice Circuit The recommended components in the application circuits yield a gain 0.26 dB at 2000 Hz. IXYS 0.1μF RX+ RX+ Integrated Circuits Division Application Note AN-117 0.1μF Customize Caller ID Gain and Ring Detect Voltage Threshold RX- is a spreadsheet for trying different component values RX- in this circuit. Changing the CID gain will also change the ringing detection threshold and the timing of the polarity reversal detection pulse, if used. 0.1μF RX+ RX For single-ended receive applications where only one RX output is used, the snoop circuit gain can be adjusted back to 0 dB by changing the value of the snoop series resistors R6, R7, R44 and R45 from 1.8M to 715k This change results in negligible 3.3.2 Transmit Signal Path modification to the ringing detect threshold. Transmit signals from the CODEC to the TX+ and TX- pins of LITELINK should be coupled through 3.3 Off-Hook Operation: OH=0 capacitors as shown in Figure 5 to minimize dc offset errors. Differential transmit signals are converted to 3.3.1 Receive Signal Path single-ended signals within LITELINK then coupled to the optical transmit amplifier in a manner similar to the Signals to and from the telephone network appear on receive path. the tip and ring connections of the application circuit. Receive signals are extracted from transmit signals by The output of the optical amplifier is coupled to a the LITELINK two-wire to four-wire hybrid then voltage-to-current converter via a transconductance converted to infrared light by the receive path LED. stage where the transmit signal modulates the The intensity of the light is modulated by the receive telephone line loop current. As in the receive path, the signal and coupled across the electrical isolation transmit gain is calibrated at the factory, limiting barrier by a reflective dome. insertion loss to 0 ±0.4 dB. On the low voltage side of the barrier, the receive Differential and single-ended transmit signals into signal is converted by a photodiode into photocurrent. LITELINK should not exceed a signal level of 0 dBm The photocurrent, a linear representation of the referenced to 600  (or 2.2 V ). For output power P-P receive signal, is amplified and converted to a levels above 0dBm consult the application note differential voltage output on RX+ and RX-. AN-157, Increased LITELINK III Transmit Power for more Variations in gain are controlled to within ±0.4 dB by information. factory gain trim, which sets the output to unity gain. 12 www.ixysic.com R03 CPC5622 INTEGRATED CIRCUITS DIVISION Figure 5. Differential and Single-ended Transmit Whether using the recommended value above or Path Connections to LITELINK when setting R higher for a lower loop current limit ZDC refer to the guidelines for FET thermal management Low-Voltage Side CODEC or LITELINK provided in AN-146, Guidelines for Effective Transmit Circuit LITELINK Designs. 0.1μf TX- TXA1 - 3.6 AC Characteristics 0.1μf TX+ TXA2 + 3.6.1 Resistive Termination Applications North American and Japanese telephone line AC termination requirements are met with a resistive Low-Voltage Side CODEC or LITELINK Transmit Circuit 600 ac 2-wire termination. For these applications LITELINK’s 2-wire network termination impedance is set by the resistor R (R10) located at the ZNT pin, ZNT 0.1μf TX- TXA1 - pin 29, with a value of 301. TX+ N/C + 3.6.2 Reactive Termination Applications Many countries use a single-pole complex impedance to model the telephone network transmission line characteristic impedance as shown in the table below. 3.4 Initialization Requirement Line Impedance Model Following Power-up OH must be de-asserted (set logic high) once after Australia China TBR 21 power-up for at least 50ms to transfer internal gain R 220  200  270  S trim values within LITELINK. This would be normal R S operation in most applications. Failure to comply with R 820  680  750  P this requirement will result in transmission gain errors R C P P C 120 nF 100 nF 150 nF and possibly distortion. P Proper gain and termination impedance circuits for a 3.5 DC Characteristics complex impedance requires the use of complex The CPC5622 is designed for worldwide applications. network on ZNT as shown in the “Reactive Termination Modification of the values of the components at the Application Circuit” on page 8. ZDC, DCS1, and DCS2 pins allow for control of the VI slope characteristics of LITELINK. Selecting 3.6.3 Mode Pin Usage appropriate resistor values for R (R16) and ZDC Asserting the MODE pin low (MODE = 0) introduces a R (R15) in the provided application circuits DCS2 7 dB pad into the transmit path and adds 7 dB of gain enable compliance with various DC requirements. to the receive path. These changes compensate for the gain changes made to the transmit and receive 3.5.1 Setting a Current Limit paths necessary for reactive termination LITELINK includes a telephone line current limit implementations. Overall insertion loss with the feature that is selectable by choosing the desired reactive termination application circuit and MODE value for R (R16) using the following formula: ZDC asserted is 0 dB. 1V Overall insertion loss with MODE de-asserted I Amps = ------------- + 0.008A CL R ZDC (MODE = 1) for the resistive termination application circuit is 0 dB. IXYS Integrated Circuits Division recommends using 8.2  for R for most applications, limiting ZDC telephone line current to 130 mA. R03 www.ixysic.com 13 CPC5622 INTEGRATED CIRCUITS DIVISION 4. Regulatory Information LITELINK III can be used to build products that comply The information provided in this document is intended with the requirements of TIA/EIA/IS-968 (formerly to inform the equipment designer but it is not sufficient FCC part 68), FCC part 15B, TBR-21, EN60950, to assure proper system design or regulatory UL1950, EN55022B, IEC950/IEC60950, CISPR22B, compliance. Since it is the equipment manufacturer's EN55024, and many other standards. LITELINK responsibility to have their equipment properly provides supplementary isolation. Metallic surge designed to conform to all relevant regulations, requirements are met through the inclusion of a crow designers using LITELINK are advised to carefully bar protection device in the application circuit. verify that their end-product design complies with all Longitudinal surge protection is provided by applicable safety, EMC, and other relevant standards LITELINK’s optical-across-the-barrier technology and and regulations. Semiconductor components are not the use of high-voltage components in the application rated to withstand electrical overstress or electrostatic circuit as needed. discharges resulting from inadequate protection measures at the board or system level. 5. LITELINK Design Resources The IXYS Integrated Circuits Division web site has a wealth of information useful for designing with LITELINK, including application notes and reference designs that already meet all applicable regulatory requirements. LITELINK data sheets also contains additional application and design information. See the following links: LITELINK datasheets and reference designs Application note AN-117 Customize Caller ID Gain and Ring Detect Voltage Threshold Application note AN-146, Guidelines for Effective LITELINK Designs Application note AN-155 Understanding LITELINK Display Feature Signal Routing and Applications 14 www.ixysic.com R03 CPC5622 INTEGRATED CIRCUITS DIVISION 6. LITELINK Performance The following graphs show LITELINK performance using the North American application circuit shown in this data sheet. Figure 6. Receive Frequency Response at RX Figure 9. Transmit THD on Tip and Ring 2 0 0 -20 -2 -40 -4 -60 Gain THD+N -6 dBm dB -80 -8 -100 -10 -12 -120 -14 -140 0 500 1000 1500 2000 2500 3000 3500 4000 0 500 1000 1500 2000 2500 3000 3500 4000 Frequency Frequency Figure 10.Transhybrid Loss Figure 7. Transmit Frequency Response at TX 0 2 -5 0 -10 -2 -15 -4 Gain THL -20 dBm dB -6 -25 -8 -30 -10 -35 -12 -40 0 500 1000 1500 2000 2500 3000 3500 4000 0 500 1000 1500 2000 2500 3000 3500 4000 Frequency Frequency Figure 8. Receive THD on RX Figure 11.Return Loss 60 0 -20 55 -40 50 -60 THD+N Return dB Loss 45 -80 (dB) 40 -100 -120 35 -140 0 500 1000 1500 2000 2500 3000 3500 4000 30 Frequency 0 500 1000 1500 2000 2500 3000 3500 4000 Frequency (Hz) R03 www.ixysic.com 15 CPC5622 INTEGRATED CIRCUITS DIVISION Figure 12.Snoop Circuit Frequency Response 5 0 -5 Gain (dBm) -10 -15 -20 -25 0 500 1000 1500 2000 2500 3000 3500 4000 Frequency (Hz) Figure 13.Snoop Circuit THD + N +0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 0 500 1k 1.5k 2k 2.5k 3k 3.5k 4k Hz Figure 14.Snoop Circuit Common Mode Rejection +0 -2.5 -5 -7.5 -10 -12.5 -15 -17.5 -20 -22.5 -25 -27.5 CMRR -30 (dBm) -32.5 -35 -37.5 -40 -42.5 -45 -47.5 -50 -52.5 -55 -57.5 -60 20 50 100 200 500 1K 2K 4K Frequency (Hz) 16 www.ixysic.com R03 CPC5622 INTEGRATED CIRCUITS DIVISION 7. Manufacturing Information 7.1 Moisture Sensitivity All plastic encapsulated semiconductor packages are susceptible to moisture ingression. IXYS Integrated Circuits Division classified all of its plastic encapsulated devices for moisture sensitivity according to the latest version of the joint industry standard, IPC/JEDEC J-STD-020, in force at the time of product evaluation. We test all of our products to the maximum conditions set forth in the standard, and guarantee proper operation of our devices when handled according to the limitations and information in that standard as well as to any limitations set forth in the information or standards referenced below. Failure to adhere to the warnings or limitations as established by the listed specifications could result in reduced product performance, reduction of operable life, and/or reduction of overall reliability. This product carries a Moisture Sensitivity Level (MSL) rating as shown below, and should be handled according to the requirements of the latest version of the joint industry standard IPC/JEDEC J-STD-033. Device Moisture Sensitivity Level (MSL) Rating CPC5622A MSL 3 7.2 ESD Sensitivity This product is ESD Sensitive, and should be handled according to the industry standard JESD-625. 7.3 Reflow Profile This product has a maximum body temperature and time rating as shown below. All other guidelines of J-STD-020 must be observed. Device Maximum Temperature x Time CPC5622A 260°C for 30 seconds 7.4 Board Wash IXYS Integrated Circuits Division recommends the use of no-clean flux formulations. However, board washing to remove flux residue is acceptable. Since IXYS Integrated Circuits Division employs the use of silicone coating as an optical waveguide in many of its optically isolated products, the use of a short drying bake could be necessary if a wash is used after solder reflow processes. Chlorine-based or Fluorine-based solvents or fluxes should not be used. Cleaning methods that employ ultrasonic energy should not be used Pb e3 R03 www.ixysic.com 17 CPC5622 INTEGRATED CIRCUITS DIVISION 7.5 Mechanical Dimensions Figure 15. CPC5622A Package Dimensions ± 7.239 0.051 PCB Land Pattern ± (0.285 0.002) 10.287 ± .254 ± (0.405 0.010) 0.203 (0.008) ± 7.493 0.127 9.30 (0.295 ± 0.005) (0.366) 1.90 ± 10.363 0.127 (0.0748) ± (0.408 0.005) Pin 1 0.635 ± 0.076 ± 0.330 0.051 0.635 0.40 0.635 x 45º 1.016 Typ. ± (0.025 0.003) (0.013 ± 0.002) (0.025 x 45º) (0.040 Typ.) (0.025) (0.0157) ± 1.981 0.051 ± (0.078 0.002) 2.134 Max (0.084 Max) Dimensions ± 9.525 0.076 mm MIN 0, MAX 0.102 ± (0.375 0.003) (MIN 0, MAX 0.004) (inches) Figure 16. CPC5622ATR Tape and Reel Dimensions 330.2 DIA. (13.00 DIA.) W=16 (0.630) B =10.70 0 Top Cover (0.421) Tape Thickness 0.102 MAX. (0.004 MAX.) A =10.90 P=12.00 0 K =3.20 (0.429) (0.472) 0 (0.126) K =2.70 1 (0.106) Embossed Carrier NOTES: 1. All dimensions carry tolerances of EIA Standard 481-2 Dimensions 2. The tape complies with all “Notes” for constant dimensions mm Embossment listed on page 5 of EIA-481-2 (inches) For additional information please visit www.ixysic.com IXYS Integrated Circuits Division makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses nor indemnity are expressed or implied. Except as set forth in IXYS Integrated Circuits Division’s Standard Terms and Conditions of Sale, IXYS Integrated Circuits Division assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. The products described in this document are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or where malfunction of IXYS Integrated Circuits Division’s product may result in direct physical harm, injury, or death to a person or severe property or environmental damage. IXYS Integrated Circuits Division reserves the right to discontinue or make changes to its products at any time without notice. Specification: DS-CPC5622-R03 Copyright © 2012, IXYS Integrated Circuits Division ® LITELINK is a registered trademark of IXYS Integrated Circuits Division All rights reserved. Printed in USA. 12/22/2012 18 www.ixysic.com R03