X5-210M V 1.4 4/7/10 PCI Express XMC Module with Four 250 MSPS 14-bit A/Ds, Virtex5 FPGA, and DDR2/QDR-II Memory FEATURES • Four 250 MSPS 14-bit A/D channels • +/-1V, DC-Coupled, 50 ohm, SMA inputs • Xilinx Virtex5, SX95T or LX155T • 512MByte DDR2 DRAM • 4MByte QDR-II SRAM • 8 RocketIO private links, 2.5 Gbps each • >1 GB/s, 8-lane PCI Express Host Interface • Power Management features • XMC Module (75x150 mm) • PCI Express (VITA 42.3) APPLICATIONS • Wireless Receiver • WLAN, WCDMA, WiMAX front end DESCRIPTION • RADAR The X5-210M is an XMC IO module featuring four 14-bit 250 MSPS • Medical Imaging A/Ds with a Virtex5 FPGA computing core, DRAM and SRAM memory, and eight lane PCI Express host interface. • High Speed Data Recording and Playback • High speed servo controls A Xilinx Virtex5 SX95T or LX155T with 512MB DDR2 DRAM and • IP development 4MB QDR-II memory provide a very high performance DSP core for demanding applications such as emerging wireless standards. The close integration of the analog IO, memory and host interface with SOFTWARE the FPGA enables real-time signal processing at extremely high • MATLAB/VHDL FrameWork Logic rates exceeding 300 GMACs per second. • Windows/Linux Drivers The X5 XMC modules couple Innovative's powerful Velocia • C++ Host Tools architecture with a high performance, 8-lane PCI Express interface that provides over 1 GB/s sustained transfer rates to the host. Private links to host cards with > 1.6 GB/s capacity using P16 are provided for system integration. The X5 family logic can be fully customized using VHDL and MATLAB using the FrameWork Logic toolset. The MATLAB BSP supports real-time hardware-in-the-loop development using the graphical, block diagram Simulink environment with Xilinx System Generator. Software tools for host development include C++ libraries and drivers for Windows and Linux. Application examples demonstrating the module features and use are provided. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Innovative Integration products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Innovative Integration standard warranty. Production processing does not necessarily include testing of all parameters. 04/07/10 © 2007 Innovative Integration • phone 805.578.4260 • fax 805.578.4225 • www.innovative-dsp.com X5-210M This electronics assembly can be damaged by ESD. Innovative Integration recommends that all electronic assemblies and components circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION Product Part Description Number X5-210M 80190-0 PCI Express XMC module with four 250 MSPS A/Ds, Virtex5 SX95T FPGA, 4MB SRAM, 512MB DRAM, onboard 250 MHz sample clock oscillator X5-210M 80190-1 PCI Express XMC module with four 250 MSPS A/Ds, Virtex5 LX155T FPGA, 4MB SRAM, 512MB DRAM, onboard 250 MHz sample clock oscillator X5-210M 80190-9 PCI Express XMC module with four 250 MSPS A/Ds, Virtex5 SX95T FPGA, 4MB SRAM, 512MB DRAM, external sample clock input X5-210M 80190-10 PCI Express XMC module with four 250 MSPS A/Ds, Virtex5 LX155T FPGA, 4MB SRAM, 512MB DRAM, external sample clock input X5-210M FrameWork 55018 X5-210M FrameWork Logic board support package for RTL and MATLAB. Includes Logic technical support for one year. SMA to BNC cable 67048 IO cable with SMA (male) to BNC (female), 1 meter XMC-PCIe Adapter 80172-0 PCI Express Carrier card for XMC PCI Express modules, x1 lanes XMC-PCI Adapter 80167-0 PCI Carrier card for XMC PCI Express modules, 64-bit PCI XMC-PCIe Adapter 80173-0 PCI Express Carrier card for XMC PCI Express modules, x8 lanes XMC-cPCI Adapter 80207 3U Compact PCI Carrier card for XMC PCI Express modules, 64-bit PCI XMC- Cabled PCIe 90181 Cabled PCI Express Carrier card for XMC PCI Express modules, single-lane. Adapter Embedded PC XMC 90199 SBC COMEX embedded PC with support for two XMC modules for standalone applications. host Innovative Integration • phone 805.578.4260 • fax 805.578.4225 • www.innovative-dsp.com 2 of 14 X5-210M Standard Features Analog Inputs 4 Memories Input Range +/- 1V DRAM Size 512 MB total Input Type Single ended, DC coupled 4 devices @ 64Mx16 each Input 50 ohm DRAM Type DDR2 DRAM Impedance DRAM Controller for DRAM implemented in A/D Device Texas Instruments ADS6149 (250 MSPS) Controller logic. DRAM is controlled as a single bank. A/D 14-bit Resolution DRAM Rate 3.8 GB/ sustained transfer rate A/D Sample 1 MHz to 250 MHz SRAM Size 4 MB total Rate 2 devices @ 512Kx32 each SRAM Two independent SRAM controllers FPGA Controller implemented in FPGA logic Device Xilinx Virtex5 SRAM Type QDR-II XC5VSX95T-1FF1136C SRAM Rate 1.2 GB/s sustained transfer rate for read XC5VLX155T-1FF1136C and write simultaneously (2.4 GB/s total) Speed Grade -1 (commercial) Size SX95T :~9M gate equivalent LX155T :~15M gate equivalent Flip-Flops SX95T: 69120 LX155T : 97280 Multipliers SX95T: 640 LX155T: 680 Slice SX95T: 17,280 LX155T: 24,320 Block RAMs SX95T: 296 (5328 Kbits) LX155T: 212 Rocket IO 16 lanes @ 2.5 Gbps Configuration SelectMAP from on-board flash EEPROM - JTAG during development Innovative Integration • phone 805.578.4260 • fax 805.578.4225 • www.innovative-dsp.com 3 of 14 X5-210M Host Interface Acquisition Monitoring Type PCI Express; 8 lanes Alerts Trigger Start, Trigger Stop, Queue Overflow, Channel Over-range, Sustained Data Rate 1 GB/s Timestamp Rollover, Temperature Warning, Temperature Failure Protocol PCI Express with Velocia packet system Alert 5 ns resolution, 32-bit counter Timestamping Connector XMC P15 Interface Standard PCIe 1.0a; VITA 42.3 P16 Digital IO Logic Update In-system reconfiguration Rocket IO Channels 8 Rocket IO data rate 2.5 Gbps/lane (2 Gbps effective Clocks and Triggering rate when 8b/10b encoded) Clock Sources Onboard low jitter fixed oscillator, DIO Bits, total 16 250MHz default frequency Signal Standard LVTTL (3.3V) External: Sine source 10 to 250 MHz, 2.1-3.3Vp-p (10.5 to 14.3 dBm) Drive +/-12 mA AC-coupled, 50-ohm terminated Connector XMC P16 Jitter Internal: 340 fs total External: 90 fs additive Power Management Triggering External or software; Continuous or N-sample-wide frame Temperature Monitor May be read by the host software Ext Trigger SMA female, Alarms Software programmable warning and failure levels LVTTL (0 to 3.3V max) DC-coupled, 50-ohm terminated. Over-temp Monitor Disables power supplies Decimation 1:1 to 1:4095 in FPGA Power Control Channel enables and power up enables Channel Clocking All channels are synchronous Heat Sinking Conduction cooling supported Multi-card External triggering input is used to (VITA20 subset) Synchronization synchronize sample clocks or an external clock and trigger may be used. Physicals Form Factor Single width IEEE 1386 Mezzanine Card Size 75 x 150 mm Weight 130g Hazardous Materials Lead-free and RoHS compliant Innovative Integration • phone 805.578.4260 • fax 805.578.4225 • www.innovative-dsp.com 4 of 14 X5-210M ABSOLUTE MAXIMUM RATINGS !Exposure to conditions exceeding these ratings may cause damage! Parameter Min Max Units Conditions Supply Voltage, 3.3V to GND +3.0 +3.6 V Supply Voltage, VPWR to GND +4.5 +12.5 V Analog Input Voltage, Vin+ or Vin- to GND -5.7 +5.7 V Operating Temperature 0 70 C Non-condensing, forced air cooling required Storage Temperature -65 +150 C ESD Rating - 1k V Human Body Model Vibration - 5 g 9-200 Hz, Class 3.3 per ETSI EN 300 019-1-3 V2.1.2 (2003-04) Shock - 40 g peak Class 3.3 per ETSI EN 300 019-1-3 V2.1.2 (2003-04) Innovative Integration • phone 805.578.4260 • fax 805.578.4225 • www.innovative-dsp.com 5 of 14 X5-210M RECOMMENDED OPERATING CONDITIONS Parameter Min Typ Max Units Conditions Supply Voltage +3.15 +3.3 +3.45 V Supply Voltage +11 +12 +13 V Operating Temperature 0 60 C Non-condensing, forced air cooling required Forced Air Cooling 2** 5 - CFM ** All systems should be characterized to determine the cooling requirements. ELECTRICAL CHARACTERISTICS Over recommended operating free-air temperature range at 0°C to +60°C, unless otherwise noted. Parameter Typ Units Notes Analog Input Bandwidth 320 MHz -3dB SFDR 89 dB 5 MHz sine input, 85%FS, Fs = 249 MSPS S/N 69.1 dB 5 MHz sine input, 85%FS, Fs = 249 MSPS THD 0.0053 % 5 MHz sine input, 85%FS, Fs = 249 MSPS ENOB 11 bits 5 MHz sine input, 85%FS, Fs = 249 MSPS Channel Crosstalk <80 dB 70 MHz, 2Vp-p on adjacent channels Noise 1.95 mVp-p Input Grounded, Fs = 249 MSPS, 1M samples Noise Floor -100 dB Input Grounded, Fs = 249 MSPS, 32K sample FFT, non- averaged Power Consumption 27 W All channels sampling at 210 MSPS, 24C ambient; specific applications may be may vary from 10 to 40W, module at 70C Gain Error <0.02 % of FS Calibrated Offset Error <500 μV Calibrated Innovative Integration • phone 805.578.4260 • fax 805.578.4225 • www.innovative-dsp.com 6 of 14 X5-210M Signal Quality versus Input Amplitude 90 85 80 75 70 SNR (dB) 65 SINAD (dB) SFDR (dB) 60 55 50 45 40 0 0.2 0.4 0.6 0.8 1 1.2 Signal Quality versus Sample Rate 95 0.015 Input Amplitude (Vp-p) 90 0.013 85 0.011 80 0.009 75 0.007 70 SNR (dB) 0.005 THD (%) 65 SFDR (dB) 0.003 60 0.001 55 50 -0.001 0 50 100 150 200 250 300 Sample Rate (MHz) Innovative Integration • phone 805.578.4260 • fax 805.578.4225 • www.innovative-dsp.com 7 of 14 dB dB X5-210M Signal Quality (Fin = 70MHz Fs = 249MSPS) Signal Quality (Fin = 5 MHz, Fs = 249 MSPS) SNR = 69.1dB, SINAD = 67.9dB, ENOB = 11, SFDR = 89.0dB, THD = 0.0053% SNR = 58.1dB, SINAD = 56.6dB, ENOB = 9.1, SFDR = 66.6dB, THD = 0.023% Innovative Integration • phone 805.578.4260 • fax 805.578.4225 • www.innovative-dsp.com 8 of 14 X5-210M Noise Floor (Fs = 249 MSPS, grounded input) X5-210M Analog Input Bandwidth 10 0 -10 A/D delta (dB normal- -20 ized to 5MHz) C1 = -30 6.8pF -40 -50 1 10 100 1000 Fin (MHz) Innovative Integration • phone 805.578.4260 • fax 805.578.4225 • www.innovative-dsp.com 9 of 14 Normalized Amplitude (dB) X5-210M Architecture and Features The X5-210M module architecture integrates analog IO with an FPGA computing core, memories and PCI Express host interface. This architecture tightly couples the FPGA to the analog and enables the module to perform real-time signal processing with low latency and extremely high Data flows between the IO and the rates making it ideal as a front-end for demanding host using a packet system applications in wireless, RADAR and medical imaging applications. Data Analog IO Buffer A/D Packetizer 128M A/D The analog front end of the X5-210M module has x16 four simultaneously sampling channels of 14-bit, 4 channels PCIe 210 MSPS A/D input. The A/D inputs have an Alerts Controller Host analog input bandwidth of 320 MHz for wideband 8 lanes and direct sampling applications. The A/Ds are directly connected to the FPGA for minimum data Triggering latency. In the standard logic, the A/Ds have an interface component that receives the data, provides digital error correction, and a FIFO memory for buffering. The digital error correction is used to compensate for gain and offset errors. This method is more stable than analog adjustments and X5 Architecture typically sacrifices less than 1% of the analog range. A non-volatile ROM on the card is used to store the calibration coefficients for the analog and is programmed during factory test. The A/D channels operate synchronously for simultaneously sampling systems using the external clock input. Controls for triggering allow precise control over the collection of data and are integrated into the FPGA logic. Trigger modes include frames of programmable size, external and software. Multiple cards can sample simultaneously by using external trigger inputs. The trigger component in the logic can be customized in the logic to accommodate a variety of triggering requirements. FPGA Core The X5 Module family has a Virtex5 FPGA and memory at its core for DSP and control. The Virtex5 FPGA is capable of 9 >300x10 MACs (SX95T operating at 500 MHz internally), about 20x faster than competing DSPs. In addition to the raw processing power, the FPGA fabric integrates logic, memory and connectivity features that make the FPGA capable of applying this processing power to virtually any algorithm and sustaining performance in real-time. The FPGA has direct access to 512MB of DDR2 DRAM capable of 3.8 GB/s data transfer rate and two independent banks of 2 MB QDR SRAM, each capable of 1.2GB/s transfer rate in each direction. These memories provide the FPGA working space for computations typically required by DSP functions like FFTs, and bulk data storage needed for system data buffering and algorithms like Doppler delay. A DRAM buffer control component in the FPGA implements a large virtual FIFO buffer in the DRAM that is used for system data buffering and algorithm support. The X5 module family uses the Virtex5 FPGA as a system-on-chip to integrate all the features for highest performance. As such, all IO, memory and host interfaces connect directly to the FPGA – providing direct connection to the data and control for maximum flexibility and performance. Firmware for the FPGA completely defines the dataflow, signal processing, controls and host interfaces, allowing complete customization of the X5 module functionality. Innovative Integration • phone 805.578.4260 • fax 805.578.4225 • www.innovative-dsp.com 10 of 14 X5-210M PCI Express Host Interface The X5 architecture delivers over 1 GB/s sustained data rates over PCI Express using the Velocia packet system. The Velocia packet system is an application interface layer on top of the fundamental PCI Express interface that provides an efficient and flexible host interface supporting high data rates with minimal host support. Using the Velocia packet system, data is transferred to the host as variable sized packets using the PCIe controller interface. The packet data system controls the flow of packets to the host, or other recipient, using a credit system managed in cooperation with the host software. The packets may be transmitted continuously for streams of data from the A/Ds, or as occasional packets for status, controls and analysis results. For all types of applications, the data buffering and flow control system delivers high throughput with low latency and complete flexibility for data types and packet sizes to match the application requirements. Firmware components for assembling and dissembling packets are provided in the FrameWork Logic that allow applications to rapidly integrate data streams and controls into the packet system with minimum effort. The PCI Express interface is implemented in the Virtex5 FPGA using 8 Rocket IO ports, for a maximum bit rate of over 20 Gbps, full duplex. Data encoding and protocol limit practical in-system data rates to about 200 MB/s per lane. Since PCI Express is not a share bus, but rather a point-to-point channel, system architectures can achieve high sustained data rates between devices – resulting in higher system-level performance and lower overall cost. Private Data Links The X5 module family has private data links on the P16 connector that can be used for system integration. The P16 connector has 8 Rocket IO links, each capable of 2.5 Gbps, and 16 sideband signals. The 8 RIO lanes can be used to provide low- latency, high rate data to the system in addition to the PCI Express interface. Maximum data rates, with deterministic performance can be implemented in performance-driven systems using little or no protocol. For more complex systems, protocols such as Aurora can be used. Module Management The data acquisition process can be monitored using the X5 alert mechanism. The alerts provide information on the timing of important events such as triggering, overranges and thermal overload. Packets containing data about the alert including an absolute system timestamp of the alert, and other information such as current temperature. This provides a precise overview of the card data acquisition process by recording the occurrence of these real-time events making the X5 cards easier to integrate into larger systems. FPGA Configuration The X5 modules have a 128Mb FLASH that holds the FPGA application image. The FLASH can be reprogrammed in- system using a software applet for field upgrades. PCIe-XMC Adapter PCI-XMC Adapter (80172) (80167) Innovative Integration • phone 805.578.4260 • fax 805.578.4225 • www.innovative-dsp.com 11 of 14 X5-210M During development, the JTAG interface to the FPGA is used for development tools such as ChipScope and MATLAB. The FPGA JTAG connector is compatible with Xilinx cables such as Platform USB and Parallel IV Cable. Software Tools Software development tools for the X5 modules provide comprehensive support including device drivers, data buffering, card controls, and utilities that allow developers to be productive from the start. At the most fundamental level, the software tools deliver data buffers to your application without the burden of low-level real-time control of the cards. Software classes provide C++ developers a powerful, high-level interface to the card that makes real-time, high speed data acquisition easier to integrate into applications. Software for data logging and analysis are provided with every X5 module. Data can be logged to system memory at full rate or to disk drives at rates supported by the drive and controller. Triggering and sample rate controls allow you to use the X5 performance in your applications without ever writing code. Innovative software applets include Binview which provides data viewing, analysis and import to MATLAB for large data files. Support for MS Visual C++ is provided. Supported OS include Windows and Linux. For more information, the software tools User Guide and on-line help may be downloaded. Logic Tools High speed DSP, analysis, customized triggering and eInstrument Node – Remote IO using SBC COMEX Embedded PC Host Cabled PCI Express for Dual PCI Express XMC Modules (x1 lane) to laptop or desktop system (90199) (90181) Using MATLAB Simulink for X5 Logic Design other unique features may be added to the X5 modules by modifying the logic. The FrameWork Logic tools provide support for RTL and MATLAB developments. The standard logic provides a hardware interface layer that allows designers to concentrate on the application-specific portions of the design. Designer can build upon the Innovative components for packet handling, hardware interfaces and system functions, the Xilinx IP core library, and third party IP. RTL source for the FrameWork Logic is provided for customization. Each design is provided as a Xilinx ISE project, with a ModelSim testbench illustrating logic functionality. The MATLAB Board Support Package (BSP) allows logic development using Simulink and Xilinx System Generator. These tools provide a graphical design environment that integrates the logic into MATLAB Simulink for complete hardware-in-the- loop testing and development. This is an extremely power design methodology, since MATLAB can be used to generate, analyze and display the signals in the logic real-time in the system. Once the development is complete, the logic can be embedded in the FrameWork logic using the RTL tools. The FrameWork Logic User sales brochure and User Guide more fully detail the development tools. Applications Information Innovative Integration • phone 805.578.4260 • fax 805.578.4225 • www.innovative-dsp.com 12 of 14 X5-210M Cables The X5-210M module uses coaxial cable assemblies for the analog I/O. The mating cable should have an SMA male connector and 50 ohm characteristic impedance for best signal quality. XMC Adapter Cards XMC modules can be used in standard desktop systems by using a XMC to PCIe adapter card (Innovative part number 80172-one lane, 80173-eight lane) or a XMC to PCI adapter card (Innovative part number 80167). An auxiliary power PCIe-XMC Adapter x8 lane (80173) connector to the PCI Express adapters provides additional power capability for XMC modules when the slot is unable to provide sufficient power. The adapter cards allow the XMC modules to be used in any PCIe or PCI system. The X5 module family uses the auxiliary P16 connector as a private host interface. Eight Rocket IO lanes with 16 LVTTL signals provide support for data transfer rates up to 1.6 GB/s sustained, as well as sideband signals for control and status. Protocols such as Serial Rapid IO and Aurora may be implemented for host communications or custom protocols. Note that the high speed Rocket IO lanes require a host card electrically capable of supporting the high speed signal pairs. Only the eight lane adapter, P/N 80195 is suitable for high speed P16 applications. Applications that need remote or portable IO can use either the eInstrument PC or eInstrument Node with X3 modules. The eInstrument PC hosts two XMC modules and provides an embedded Windows or Linux PC in a compact form-factor. The eInstrument Node hosts a single XMC module in a compact chassis that communicates with the host computer over cabled PCI Express. Innovative Integration • phone 805.578.4260 • fax 805.578.4225 • www.innovative-dsp.com 13 of 14 X5-210M IMPORTANT NOTICES Innovative Integration Incorporated reserves the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to Innovative Integration’s terms and conditions of sale supplied at the time of order acknowledgment. Innovative Integration warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with Innovative Integration’s standard warranty. Testing and other quality control techniques are used to the extent Innovative Integration deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. Innovative Integration assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using Innovative Integration products. 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For further information on Innovative Integration products and support see our web site: www.innovative-dsp.com Mailing Address: Innovative Integration, Inc. 2390A Ward Avenue, Simi Valley, California 93065 Copyright ©2007, Innovative Integration, Incorporated Innovative Integration • phone 805.578.4260 • fax 805.578.4225 • www.innovative-dsp.com 14 of 14