FPD4000AS 2.5W PACKAGED POWER PHEMT • PERFORMANCE (1.8 GHz) ♦ 34.5 dBm Output Power (P ) 1dB ♦ 12 dB Power Gain (G ) 1dB ♦ 45 dBm Output IP3 ♦ 8V Operation ♦ 50% Power-Added Efficiency ♦ Evaluation Boards Available ♦ Design Data Available on Website ♦ Suitable for applications to 5 GHz SEE PACKAGE OUTLINE FOR MARKING CODE • DESCRIPTION AND APPLICATIONS The FPD4000AS is a packaged depletion mode AlGaAs/InGaAs pseudomorphic High Electron Mobility Transistor (pHEMT), optimized for power applications in L-Band. The surface-mount package has been optimized for low parasitics. Typical applications include drivers or output stages in PCS/Cellular base station transmitter amplifiers, as well as other power applications in WLL/WLAN amplifiers. • ELECTRICAL SPECIFICATIONS AT 22°C Parameter Symbol Test Conditions Min Typ Max Units RF SPECIFICATIONS MEASURED AT f = 1.8 GHz USING CW SIGNAL Power at 1dB Gain Compression P V = 8V; I = 700 mA 33.5 34.5 dBm 1dB DS DQ Γ and Γ tuned for Optimum IP3 S L Power Gain at dB Gain Compression G V = 8V; I = 700 mA 10.5 12 1dB DS DQ Γ and Γ tuned for Optimum IP3 S L Maximum Stable Gain MSG V = 8V; I = 700 mA 18 dB DS DQ S /S 21 12 P = 0dBm, 50Ω system IN Power-Added Efficiency PAE V = 8V; I = 700 mA 50 % DS DQ at 1dB Gain Compression Γ and Γ tuned for Optimum IP3 S L rd 3 -Order Intermodulation Distortion IM3 V = 8V; I = 700 mA DS DQ P = 23 dBm (single-tone level) -46 dBc Γ and Γ tuned for Optimum IP3 S L OUT Saturated Drain-Source Current I V = 1.3 V; V = 0 V 1.9 2.3 2.65 mA DSS DS GS Maximum Drain-Source Current I 3.6 mA V = 1.3 V; V ≅ +1 V MAX DS GS Transconductance G V = 1.3 V; V = 0 V 2.4 mS M DS GS Gate-Source Leakage Current I V = -3 V 70 170 µA GSO GS Pinch-Off Voltage |V| V = 1.3 V; I = 8 mA 0.7 0.9 1.4 V P DS DS Gate-Source Breakdown Voltage |V| I = 8 mA 6 10 V BDGS GS Gate-Drain Breakdown Voltage |V| I = 8 mA 20 22 V BDGD GD Thermal Resistivity (channel-to-case) See Note on following page 16 Θ °C/W CC Phone: +1 408 850-5790 http:// www.filtronic.co.uk/semis Revised: 05/26/05 Fax: +1 408 850-5766 Email: sales@filcsi.com FPD4000AS 2.5W PACKAGED POWER PHEMT • RECOMMENDED OPERATING BIAS CONDITIONS Drain-Source Voltage: From 5V to 8V Quiescent Current: From 400 mA to 750 mA 1 • ABSOLUTE MAXIMUM RATINGS Parameter Symbol Test Conditions Min Max Units Drain-Source Voltage V -3V < V < +0V 12 V DS GS Gate-Source Voltage V 0V < V < +8V -3 V GS DS Drain-Source Current I For V > 2V I mA DS DS DSS Gate Current I Forward / Reverse current +20/-20 mA G 2 RF Input Power P Under any acceptable bias state 575 mW IN Channel Operating Temperature T Under any acceptable bias state 175 ºC CH Storage Temperature T Non-Operating Storage -40 150 ºC STG Total Power Dissipation P See De-Rating Note below 9.0 W TOT Gain Compression Comp. Under any bias conditions 5 dB 3 Simultaneous Combination of Limits 2 or more Max. Limits 80 % 1 2 T = 22°C unless otherwise noted Max. RF Input Limit must be further limited if input VSWR > 2.5:1 Ambient 3 Users should avoid exceeding 80% of 2 or more Limits simultaneously Notes: • Operating conditions that exceed the Absolute Maximum Ratings will result in permanent damage to the device. • Total Power Dissipation defined as: P ≡ (P + P ) – P , where: TOT DC IN OUT P : DC Bias Power DC P : RF Input Power IN P : RF Output Power OUT • Total Power Dissipation to be de-rated as follows above 22°C: P = 9.0 - (0.0625W/°C) x T TOT PACK where T = source tab lead temperature above 22°C PACK (coefficient of de-rating formula is the Thermal Conductivity) Example: For a 55°C source lead temperature: P = 9.0 - (0.0625 x (55 – 22)) = 6.94W TOT • For optimum heatsinking, metal-filled through (Source) via holes should be used directly below the central metallized ground pad on the bottom of the package. • Note on Thermal Resistivity: The nominal value of 16°C/W is measured with the package mounted on a large heatsink with thermal compound to ensure adequate (unsoldered) contact. The package temperature is referred to the Source leads. • HANDLING PRECAUTIONS To avoid damage to the devices care should be exercised during handling. Proper Electrostatic Discharge (ESD) precautions should be observed at all stages of storage, handling, assembly, and testing. This product has be tested to Class 1A (> 250V but < 500V) using JESD22 A114, Human Body Model, and to Class A, (< 200V) using JESD22 A115, Machine Model. Phone: +1 408 850-5790 http:// www.filtronic.co.uk/semis Revised: 05/26/05 Fax: +1 408 850-5766 Email: sales@filcsi.com FPD4000AS 2.5W PACKAGED POWER PHEMT • BIASING GUIDELINES ¾ Active bias circuits provide good performance stabilization over variations of operating temperature, but require a larger number of components compared to self-bias or dual-biased. Such circuits should include provisions to ensure that Gate bias is applied before Drain bias, otherwise the pHEMT may be induced to self-oscillate. Contact your Sales Representative for additional information. ¾ Dual-bias circuits are relatively simple to implement, but will require a regulated negative voltage supply for depletion-mode devices such as the FPD1000AS. ¾ Self-biased circuits employ an RF-bypassed Source resistor to provide the negative Gate-Source bias voltage, and such circuits provide some temperature stabilization for the device. A nominal value for circuit development is 3.25 Ω for the recommended 200mA operating point. ¾ The recommended 200mA bias point is nominally a Class AB mode. A small amount of RF gain expansion prior to the onset of compression is normal for this operating point. • PACKAGE OUTLINE AND RECOMMENDED PC BOARD LAYOUT (dimensions in millimeters – mm) PACKAGE MARKING CODE Example: f1ZD P1F f = Filtronic 1ZD = Lot / Date Code P1F = Status, Part Code, Part Type All information and specifications subject to change without notice. Phone: +1 408 850-5790 http:// www.filtronic.co.uk/semis Revised: 05/26/05 Fax: +1 408 850-5766 Email: sales@filcsi.com