esd electronics, inc. H A R D W A R E • S O F T W A R E • E N G I N E E R I N G CPCI-CAN/400-2 2x CAN: Layer 2, CANopen or ARINC 825, Optional PXI-Interface • 2x CAN ISO 11898 • ARINC 825 protocol available • 33/66 MHz CompactPCI interface CPCI CAN Interface The CPCI-CAN/400-2 is a CompactPCI board in 3U format that features two electrically isolated CAN High-Speed interfaces according to ISO 11898-2. CAN is driven by the esd Advanced CAN Core (esdACC) CAN controller implemented in the Xilinx Spartan 3e FPGA. The CPCI-CAN/400-2 provides high-resolu- tion hardware timestamps. CPCI-CAN/400-2 PXI Interface The CPCI-CAN-400-2 optionally features a PXI interface. The signals TRG 0-7, CLK 10 and STAR are controlled via the FPGA. The signals LBL/LBR1-12 are looped through. The PXI interface is available on request. Order Information: Designation order no. CPCI- 2x CAN C.2033.02 Software Support CAN/400-2 CAN layer 2 (CAN-API) software drivers are available for Win- CAN-DRV-LCD Object license and CD for VxWorks 5.x C.1101.55 dows, VxWorks, QNX, RTX1 and Linux supporting up to 24 VxWorks and 6.x CAN nets. Drivers for other operating systems are available on ARINC825-LCD ARINC 825 object license and VxWorks C.1140.18 VxWorks CD for VxWorks, incl. C.1101.55 request. The CANopen software package is available for Win- CAN-DRV-LCD CAN layer 2 (CAN-API) object Windows C.1101.02 dows, VxWorks, Linux, QNX, and RTX. ARINC 825 as another Windows/Linux / Linux license for Windows and Linux higher layer protocol is available as an option for Windows, 1, incl. CD VxWorks, QNX, Linux, and RTX. ARINC825-LCD ARINC825-LCD ARINC 825 object C.1140.06 Windows/Linux license and Windows / Linux CD for Windows and Linux, incl. C1101.02 CANopen-LCD CANopen object license for Windows C.1101.06 and Linux 1, incl. CD growing with the challenge Phone: 800-732-8006 • Fax: 800-732-8093 • Web: http://www.esd-electronics-usa.com• Email: us-sales@esd-electronics.com esd electronics, inc. H A R D W A R E • S O F T W A R E • E N G I N E E R I N G CPCI-CAN/400-2 2x CAN: Layer 2, CANopen or ARINC 825, Optional PXI-Interface Technical Specifications: CompactPCI interface and microprocessor: Interface: PCI bus according to PCI Local Bus Specification 2.2, 32 bit 33/66 MHz, 3.3 V (5 V tolerant), PCI bus master capability Memory: BlockRAM: 72 KB, DRAM: 64 MB Microprocessor: optional 32-bit mC in FPGA (MicroBlaze) CAN: Interface: 2x CAN high-speed interface acc. to ISO11898-2, dif- CPCI-CAN/400-2 ferential, electrically isolated, bit rate up to 1 Mbit/s CAN controller: according to ISO 11898-1 (CAN 2.0 A/B) General: Superior esdACC Features: Ambient temp.: standard: 0 ...+50 /C • Operating system independently programmable via esd’s NTCAN-API • 32-Bit register interface optimized for CAN needs Humidity: max. 90%, non-condensing Easy to program Connectors: P1, P2, 2x DSUB9 (male) Transmission and reception of CAN frames with a minimum of register accesses Power supply: 5 V, 3.3 V • RX and TX timestamping (64-Bit wide, bit accurate, resolution may vary with input clock, in any case = 62.5 ns, usually 20.833 ns) LEDs: CAN status, 1x module status • TX FIFO (8 CAN frames deep 2) Providing the means to generate 100% busload even with non-realtime operating systems Providing the means for real back-to-back transmission • Reactive and frame accurate abortion of transmissions, Driven by esdACC (Advanced CAN Core) e.g. for driver timeouts ISO11898-1 conform Basic Product Features: Aborted frames in FIFO not blocked by low priority TX • CAN ISO 11898-1 protocol compatibility • Hardware timer to provide accurate software timeouts beyond operating • 11-Bit and 29-Bit CAN IDs system accuracy • Bit rates from 10kbit/s up to 1 Mbit/s supported • Bus mastering in RX direction takes the load off host CPU (needs bus • Receive buffer (64 CAN messages 2) master capable local bus to host interface) • Complete access to CAN error counters • Optional integration w/ 32-Bit microcontroller to give further relief to • Programmable error warning limit host CPU • Error code capture register • Optional sources for timestamps (e.g. IRIG-B) • Error interrupt for each CAN bus error • FPGA technology allows tailoring features to customer needs, incl. • Arbitration lost interrupt with detailed bit position optional integration w/customer FPGA content. • Single-shot transmission (no re-transmission) • Driver Availability: Windows, Linux, QNX 1, VxWorks 1, RTX 1 • Listen only mode (no acknowledge, no active error flags) • Available higher-level protocols: CANopen, ARINC825, J1939 • Automatic bit rate detection (software supported bit rate detection) • Acceptance filter (4-byte code, 4-byte mask) For further information on the esdACC IP Core, please contact our sales • Self reception mode (Reception of ‘own’ messages team. For further information please visit http://www.esd-electronics-usa.com/CompactPCI-CPU-PowerPC-Ethernet- CANopen-DeviceNet-Graphic-Controller-Digital-I-Os-Analog-I-Os-Serial- esd electronics, Inc. Interface.html Phone: 800-732-8006 Fax: 800-732-8093 Web: http://www.esd-electronics-usa.com Email: us-sales@esd-electronics.com