Application Notes: PC-LineScan Specification Acquisition constraints and Video Input Timing Features Number of Video input � 1 Digital input (LVDS or RS-422) camera input Pixel format � Monochrome � Up to 4 taps of 8-bits/pixel � Up to two taps of 16-bits/pixel � Up to one tap of 32-bits/pixel � RGB 24-bits Scanning � Progressive � Multi-taps � Multi-channels � Four quadrant � Interleaved pixels � Interline � Interlace � Tap reversal Resolution Horizontal minimum: � 4 Pixels x tap Horizontal maximum: � 8-bits/pixel x 64K Pixels/line � 16-bits/pixel x 32K Pixels/line � 32-bits/pixel x 16K Pixels/line Note: The number of bits is per pixel, not the total input bits � Vertical minimum 1 line � Vertical maximum 64K lines Pixel clock � Up to 62.5 MHz Maximum for LVDS. range � Up to 25 MHz Maximum for RS-422. Timing � Pixel Clock CCLK programmable range 320 KHz to 100 outputs MHz, maximum usable frequency limited by signal standard (LVDS or RS-422) cable quality and length. � External Synchronization (EXSYNC) programmable period and pulse width 140 ns to 18.75 s. � Programmable Integration (PRI) or exposure control, programmable pulse width, delay, start and stop. 08/21/01 – DRA/RBE www.imaging.com 1 Application Notes: PC-LineScan Specification Timing Parameters Parameter Definition RS-422 LVDS LENmin Minimum LEN inactive (H Blanking) synchronous mode 1 PCLK cycle 1 PCLK cycle asynchronous mode 20 ns 10 ns LENact Minimum LEN Active, asynchronous mode 25 ns 25 ns FENmin Minimum FEN inactive (V Blanking) 1 PCLK cycle 1 PCLK cycle MULTImin Minimum MULTI inactive 1 PCLK cycle 1 PCLK cycle Vp Minimum PCLK period 40 ns 16 ns Vh Minimum PCLK high 20 ns 10 ns Vl Minimum PCLK low 20 ns 10 ns Tsu Data and timing set-up to selected edge of 12 ns 8 ns PCLK (synchronous mode) Th Data and timing hold from selected edge of 6 ns 2 ns PCLK (synchronous mode) PCLK LEN /LEN min FEN /FEN min Figure 1. Line and Frame Timing rising edge V p sample V V h l PCLK T T su h LEN, FEN,MULTI and Data falling edge V p sample V V h l PCLK T T su h LEN, FEN,MULTI and Data Figure 2. Synchronous Timing • Synchronous mode: LEN, FEN, and MULTI are sampled on selected edge of clock input PCLK. • Asynchronous LEN mode: LEN is edge sampled with programmable polarity. FEN and MULTI are still sampled on selected edge of PCLK. • Polarity of LEN, FEN, PCLK and MULTI are programmable. • Programmable image size (window) H Offset, H Active, V Offset, V Active. 08/21/01 – DRA/RBE www.imaging.com 2 Application Notes: PC-LineScan Specification Parallel Port � OPTO-22 compatible Parallel I/O port: 8 TTL inputs, 8 TTL/CMOS outputs Triggering Inputs � 2 independent programmable triggers � 2 TTL inputs, 2 differential inputs, 2 opto-coupled inputs, 2 software triggers. � Input divider 8-bit Physical Description � Requires a full-length PCI slot Environmental � Operating Temperature: 10 to 50 degree C � Relative Humidity: 5% to 90% (non-condensing) Power Consumption � 2.5 Amp on 5 Volts (12.5 Watts) typical Note: RS-422 is not stocked, but can be ordered. Factory will change driver and receiver chips to convert an LVDS to RS-422. 08/21/01 – DRA/RBE www.imaging.com 3