PC-CamLink TECHNICAL SPECS PCI frame grabber with TM CameraLink interface Benefits • 120MB/s sustained bus master transfer to host with no host CPU burden • CameraLink interface for line and area scan digital cameras simplifies camera integration • Ability to provide camera power • First in the industry with the ability to map the CameraLink serial port control directly into standard windows Com port • Single PCI slot solution for data and I/O. One CameraLink connector and one I/O connector allows all needed signals for data and I/O to be available on a single plate. No extra PCI slot needed to access I/O Overview PC-CamLink is an industrial PCI frame grabber that uti- time to process and analyze image data. PC-CamLink is lizes the CameraLink digital camera interface. It com- capable of bus mastering image data directly to the host bines a half-slot PCI-bus frame grabber featuring Coreco PC memory as lines become available. PC-CamLink’s ability Imaging’s high-speed image transfer architecture which to provide data in 4:2:2 image format means it is able to provides high performance, cost-effective interface to deliver non-destructive overlay on live images with almost cameras conforming to the CameraLink specification. no load on the host CPU - a first and only in the industry! Building upon Coreco Imaging’s experience in providing digital camera interfaces for the machine vision market, The scatter gather feature enables automated image trans- PC-CamLink provides the user with a flexible interface for fers. This further reduces CPU overhead and maximizes the high speed, high resolution, CameraLink cameras with sustained transfer speed, leaving much needed processing clock rates up to 62.5 MHz. cycles for demanding continuous inspection applications. Unique to the PC-Camlink is 16MB of on-board memory PC-CamLink provides one 8,10,12,16, or 24-bit Camera which maintains the required high data transfer rates while Link input. A data rate of up to 187.5MB/s can support minimizing CPU utilization and risk of data loss. On-board cameras with resolutions to 64K pixels wide by N lines. real-time image re-sequencing for multi-tap digital cameras Camera control can be accomplished via the Camera significantly reduces host CPU burden, giving the host more Link serial interface. CE www.imaging.com PC-CamLink Block Diagram CAMERA LINK CONNECTOR Camera Timing I/O SerTC SerTFG CC4 CC3 CC2 CC1 XCLX XO X1 X2 X3 • CameraLink timing inputs: Clock (PCLK), Line Valid (LVAL), Frame Valid (FVAL), Data Valid (DVAL), and a Spare input Rx Tx Camera Data Interface Camera Control Serial Camera Data (24) Interface Multiplexers Clock SPR DVAL LVAL FVAL Port (SPR) Timing Control CTL0 CTL1 CTL2 CTL3 • Camera Pixel Clock to 62.5 MHz EXSYNC PRI Sync & Exposure Input + 12DC Window • Camera Timing Outputs: sync, programmable integration Counters Pixel Generator LUTs TTL_IN0 (2) Trigger DIFF_IN0 Camera Power MUX OPTO_IN0 Trigger Divider Expansion • Fused 12 volt power (1A) is supplied on the 26pin DSUB TTL_IN1 Trigger Slot DIFF_IN1 MUX MUX OPTO_IN1 External Triggers TTL_IN2 PRI Image Image • Advanced multi-trigger acquisition modes DIFF_OUT (2) Output EXSYNC Memory Memory Control TTL_OUT (3) DIFF_OUT (2) Control Multiplexers OPTO_OUT (2) TTL_OUT (3) • Dual external triggers available as differential, TTL or Opto- OPTO_OUT (2) DMA 32 coupled Table Data In (8) • Software triggering for host controlled acquisition PCI-Bus Strobe In 8 Interface Parallel Control Interrupt Port Registers • Trigger divider allows precise control over incoming trigger Data Out (8) Strobe Out PIO Connector events 32 Multi-Tap Data Re-sequencing • Reformats multi-tap data on the fly Specifications • Provides line/row re-sequencing to output most any multi- tap image in normal scan format Image Buffering and Output • Color plane separation during transfer • 16MB of high bandwidth SDRAM supports acquisition rates up to 187.5MB/s (24-bits @ 62.5 MHz) PCI Interface • Provides ROI (cropped) transfer to reduce data volume • Scatter gather feature for highly efficient image transfers • On-the-fly re-sequencing of image data for multi-tap cameras • Bus master of image data at 120MB/s sustained • Data re-formatting to allow non-destructive overlays • Target access (random R/W) to on-board registers, image • Color plane separation during transfer memory and LUTs • Multiple interrupt sources Programmable Window Generator • Enables acquisition of subset of camera image Bus Requirements • Maximum Window - 64K x 64K • 32-bit PCI slot • Horizontal Resolution - 1 pixel • 1.3 A @ +5 Volts • Vertical Resolution - 1 line • 1/2 length PCI card • Programmable independent X/Y decimation (2, 4, 8, 16) performed during image acquisition • Color images stored using packed 24-bit or 16-bit formats, or sequential color planes To learn more about the PC-CamLink, read the complete data sheet on our website at www.imaging.com/pc-series All trademarks are registered by their respective companies. Coreco Imaging Inc. reserves the right to make changes at any time without notice. Coreco Imaging Inc. 2002 © Coreco Imaging, Inc. All rights reserved. 2