Three-State Buffers ADS774 ADS774 ADS774 ® ADS774 Microprocessor-Compatible Sampling CMOS ANALOG-to-DIGITAL CONVERTER FEATURES DESCRIPTION lREPLACES ADC574, ADC674 AND ADC774 The ADS774 is a 12-bit successive approximation FOR NEW DESIGNS analog-to-digital converter using an innovative capacitor array (CDAC) implemented in low-power lCOMPLETE SAMPLING A/D WITH CMOS technology. This is a drop-in replacement for REFERENCE, CLOCK AND ADC574, ADC674, and ADC774 models in most MICROPROCESSOR INTERFACE applications, with internal sampling, much lower power lFAST ACQUISITION AND CONVERSION: consumption, and the ability to operate from a single 8.5μs max OVER TEMPERATURE +5V supply. lELIMINATES EXTERNAL SAMPLE/HOLD The ADS774 is complete with internal clock, micro- IN MOST APPLICATIONS processor interface, three-state outputs, and internal lGUARANTEED AC AND DC PERFOR- scaling resistors for input ranges of 0V to +10V, 0V to MANCE +20V, ±5V, or ±10V. The maximum throughput time lSINGLE +5V SUPPLY OPERATION is 8.5μs over the full operating temperature range, including both acquisition and conversion.lLOW POWER: 120mW max Complete user control over the internal sampling func-lPACKAGE OPTIONS: 0.6" and 0.3" DIPs, tion facilitates elimination of external sample/hold SOIC amplifiers in most existing designs. The ADS774 requires +5V, with –15V optional. No +15V supply is required. Available packages include 0.3" or 0.6" wide 28-pin plastic DIP and 28-pin SOICs. Status Control Control Logic Inputs Bipolar Offset CDAC Clock – Parallel 20V Range Successive Data Approximation 10V Range + Output Register 2.5V Reference Comparator Input 2.5V Reference 2.5V Output Reference International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1991 Burr-Brown Corporation PDS-1109F Printed in U.S.A. July, 1995 SPECIFICATIONS ELECTRICAL At T = T to T , V = +5V, V = –15V to +5V, sampling frequency of 117kHz, f = 10kHz; unless otherwise specified. A MIN MAX DD EE IN ADS774JE, JP, JU ADS774KE, KP, KU PARAMETER MIN TYP MAX MIN TYP MAX UNITS RESOLUTION 12[Bits INPUTS ANALOG Voltage Ranges: Unipolar 0 to +10, 0 to +20 V Bipolar ±5, ±10 V Impedance: 0 to +10V, ±5V 8.5 12 [[ kΩ ±10V, 0V to +20V 35 50 [[ kΩ DIGITAL (CE, CS, R/C, A , 12/8) O Voltages: Logic 1 +2.0 +5.5[[ V Logic 0 –0.5 +0.8[[ V Current –5 0.1 +5 [[[ μA Capacitance 5[pF TRANSFER CHARACTERISTICS DC ACCURACY At +25°C Linearity Error ±1 ±1/2 LSB Unipolar Offset Error (adjustable to zero) ±2[LSB Bipolar Offset Error (adjustable to zero) ±10 ±4 LSB (1) (2) Full-Scale Calibration Error ±0.25[% of FS (adjustable to zero) No Missing Codes Resolution 12 12 Bits (3) T to T MIN MAX Linearity Error ±1 ±1/2 LSB Full-Scale Calibration Error ±0.47 ±0.37 % of FS Unipolar Offset ±4 ±3 LSB Bipolar Offset ±12 ±5 LSB No Missing Codes Resolution 12 12 Bits (4) AC ACCURACY Spurious Free Dynamic Range 73 78 76[dB Total Harmonic Distortion –77 –72[–75 dB Signal-to-Noise Ratio 69 72 71[dB Signal-to-(Noise + Distortion) Ratio 68 71 70[dB Intermodulation Distortion –75[ (F = 20kHz, F = 23kHz) IN1 IN2 (5) TEMPERATURE COEFFICIENTS Unipolar Offset ±1[ppm/°C Bipolar Offset ±2[ppm/°C Full-Scale Calibration ±12[ppm/°C POWER SUPPLY SENSITIVITY (6) Change in Full-Scale Calibration +4.75V < V < +5.25V DD Max Change ±1/2[LSB CONVERSION TIME (Including Acquisition Time) t + t at 25°C: AQ C 8-Bit Cycle 5.5 5.9 [[ μs 12-Bit Cycle 7.5 8 [[ μs 12-Bit Cycle, T to T : 8 8.5 [[ μs MIN MAX SAMPLING DYNAMICS Sampling Rate at 25°C 125[kHz T to T 117[kHz MIN MAX Aperture Delay, t AP With V = +5V 20[ns EE With V = 0V to –15V 1.6[μs EE Aperture Uncertainty (Jitter) With V = +5V 300[ps, rms EE With V = 0V to –15V 10[ns, rms EE Settling time to 0.01% for 1.4[μs Full-Scale Input Change ® ADS774 2 SPECIFICATIONS (CONT) ELECTRICAL At T = T to T , V = +5V, V = –15V to +5V, sampling frequency of 117kHz, f = 10kHz; unless otherwise specified. A MIN MAX DD EE IN ADS774JE, JP, JU ADS774KE, KP, KU PARAMETER MIN TYP MAX MIN TYP MAX UNITS OUTPUTS DIGITAL (DB - DB , STATUS) 11 0 Output Codes: Unipolar Unipolar Straight Binary (USB) Bipolar Bipolar Offset Binary (BOB) Logic Levels: Logic 0 (I = 1.6mA) +0.4[V SINK Logic 1 (I = 500μA) +2.4[V SOURCE Leakage, Data Bits Only, High-Z State –5 0.1 +5 [[[ μA Capacitance 5[pF INTERNAL REFERENCE VOLTAGE Voltage +2.4 +2.5 +2.6 [[[ V Source Current Available for External Loads 0.5[mA POWER SUPPLY REQUIREMENTS (7) Voltage: V –16.5 V [[ V EE DD V +4.5 +5.5[[ V DD (7) Current: I (V = –15V) –1[mA EE EE I +15 +24 [[ mA DD Power Dissipation (T to T ) MIN MAX (V = 0V to +5V) 75 120 [[ mW EE TEMPERATURE RANGE Specification 0 +70[[ °C Operating: –40 +85[[ °C Storage Temperature Range –65 +150[[ °C [ Same specification as ADS774JE, JP, JU. NOTES: (1) With fixed 50Ω resistor from REF OUT to REF IN. This parameter is also adjustable to zero at +25°C. (2) FS in this specification table means Full Scale Range. That is, for a ±10V input range, FS means 20V; for a 0 to +10V range, FS means 10V. (3) Maximum error at T and T . (4) Based on using V = MIN MAX EE +5V, which is the Control Mode. See the section "S/H Control Mode and ADC774 Emulation Mode." (5) Using internal reference. (6) This is worst case change in accuracy from accuracy with a +5V supply. (7) V is optional, and is only used to set the mode for the internal sample/hold. When V = –15V, I = –1mA EE EE EE typ; when V = 0V, I = ±5μA typ; when V = +5V, I = +167μA typ. EE EE EE EE The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® 3 ADS774 ABSOLUTE MAXIMUM RATINGS ELECTROSTATIC V to Digital Common ....................................................... +V to –16.5V DISCHARGE SENSITIVITY EE DD V to Digital Common .............................................................. 0V to +7V DD Analog Common to Digital Common .................................................... ±1V This integrated circuit can be damaged by ESD. Burr-Brown Control Inputs (CE, CS, A , 12/8, R/C) O recommends that all integrated circuits be handled with to Digital Common .................................................. –0.5V to V +0.5V DD appropriate precautions. Failure to observe proper handling Analog Inputs (Ref In, Bipolar Offset, 10V ) IN to Analog Common ...................................................................... ±16.5V and installation procedures can cause damage. 20V to Analog Common .................................................................. ±24V IN Ref Out .......................................................... Indefinite Short to Common, ESD damage can range from subtle performance degrada- Momentary Short to V DD tion to complete device failure. Precision integrated circuits Max Junction Temperature ............................................................ +165°C may be more susceptible to damage because very small Power Dissipation ........................................................................ 1000mW parametric changes could cause the device not to meet its Lead Temperature (soldering,10s) ................................................. +300°C Thermal Resistance, θ : Plastic DIPs ........................................ 100°C/W JA published specifications. SOIC ................................................... 100°C/W PACKAGE/ORDERING INFORMATION TEMPERATURE LINEARITY PACKAGE DRAWING (1) (2) PRODUCT SINAD RANGE ERROR PACKAGE NUMBER ADS774JE 68dB 0°C to +70°C ±1LSB 28-Pin 0.3" Plastic DIP 246 ADS774KE 70dB 0°C to +70°C ±1/2LSB 28-Pin 0.3" Plastic DIP 246 ADS774JP 68dB 0°C to +70°C ±1LSB 28-Pin 0.6" Plastic DIP 215 ADS774KP 70dB 0°C to +70°C ±1/2LSB 28-Pin 0.6" Plastic DIP 215 ADS774JU 68dB 0°C to +70°C ±1LSB 28-Lead SOIC 217 ADS774KU 70dB 0°C to +70°C ±1/2LSB 28-Lead SOIC 217 NOTES: (1) SINAD is Signal-to-(Noise + Distortion) expressed in dB. (2) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr- Brown IC Data Book. CONNECTION DIAGRAM +5VDC Supply Power-Up Reset 1 28 STATUS (V ) DD – 12/8 2 27 DB11 (MSB) Control CS 3 26 DB10 Logic Clock A 4 25 DB9 O – 24 R/C 5 DB8 CE 6 23 DB7 22 DB6 NC* 7 12 2.5V Ref 2.5V 12 Bits Bits 21 8 DB5 Out Reference Analog 20 9 DB4 Common 2.5V Ref 10 19 DB3 In V 11 18 DB2 EE 17 DB1 Bipolar 12 – Offset 10V Range 13 16 DB0 (LSB) + CDAC 20V Range 14 15 Digital Common *Not Internally Connected ® ADS774 4 Succesive Approximation Register Three-State Buffers and Control Nibble A Nibble C Nibble B TYPICAL PERFORMANCE CURVES At T = +25°C, V = V = +5V; Bipolar ±10V Input Range; sampling frequency of 110kHz; unless otherwise specified. All plots use 4096 point FFTs. A DD EE SIGNAL/(NOISE + DISTORTION) vs FREQUENCY SPECTRUM (±10V, 2kHz Input) INPUT FREQUENCY AND AMBIENT TEMPERATURE 0 75 S/(N + D) = 72.6dB –20 THD = –93.5dB SNR = 72.6dB –55°C –40 –60 70 +25°C +125°C –80 –100 –120 65 010 20 30 40 50 55 0.1 1 10 100 Input Frequency (kHz) Input Frequency (kHz) FREQUENCY SPECTRUM (±10V, 20kHz Input) FREQUENCY SPECTRUM (±1V, 20kHz Input) 0 0 S/(N + D) = 70.6dB S/(N + D) = 53.1dB –20 –20 THD = –77.5dB THD = –74.2dB SNR = 71.5dB SNR = 53.1dB –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 010 20 30 40 50 55 010 20 30 40 50 55 Input Frequency (kHz) Input Frequency (kHz) SPURIOUS FREE DYNAMIC RANGE, SNR AND THD POWER SUPPLY REJECTION vs INPUT FREQUENCY vs SUPPLY RIPPLE FREQUENCY 100 80 Spurious Free Dynamic Range 90 60 Total Harmonic Distortion (THD) 80 40 Signal-to-Noise Ratio (SNR) 70 20 60 10 0.1 1 10 100 10 100 1k 10k 100k 1M 10M Input Frequency (kHz) Supply Ripple Frequency (Hz) ® 5 ADS774 Magnitude (dB) Magnitude (dB) Spurious Free Dynamic Range, SNR, THD (dB) Magnitude (dB) Signal/(Noise + Distortion) (dB) Power Supply Rejection Ratio (V/V in dB) latch S in position “R” or “G”. Similarly, the second 1 THEORY OF OPERATION approximation is made by connecting S to the reference and 2 In the ADS774, the advantages of advanced CMOS technol- S to GND, and latching S according to the output of the 3 2 ogy—high logic density, stable capacitors, precision analog comparator. After three successive approximation steps have switches—and Burr-Brown’s state of the art laser trimming been made the voltage level at the comparator will be within techniques are combined to produce a fast, low power 1/2LSB of GND, and a digital word which represents the analog-to-digital converter with internal sample/hold. analog input can be determined from the positions of S , S 1 2 and S . The charge-redistribution successive-approximation circuitry 3 converts analog input voltages into digital words. A simple example of a charge-redistribution A/D converter OPERATION with only 3 bits is shown in Figure 1. BASIC OPERATION Figure 2 shows the minimum connections required to oper- ate the ADS774 in a basic ±10V range in the Control Mode Analog Comparator S C L Input (discussed in detail in a later section.) The falling edge of a o Convert Command (a pulse taking pin 5 LOW for a mini- 4C 2C C g Out Signal i mum of 25ns) both switches the ADS774 input to the hold S c S S S 1 2 3 state and initiates the conversion. Pin 28 (STATUS) will output a HIGH during the conversion, and falls only after the R R R G G G conversion is completed and the data has been latched on the data output pins (pins 16 to 27.) Thus, the falling edge of STATUS on pin 28 can be used to read the data from the + Reference conversion. Also, during conversion, the STATUS signal – Input puts the data output pins in a High-Z state and inhibits the input lines. This means that pulses on pin 5 are ignored, so FIGURE 1. 3-Bit Charge Redistribution A/D. that new conversions cannot be initiated during the conver- sion, either as a result of spurious signals or to short-cycle INPUT SCALING the ADS774. Precision laser-trimmed scaling resistors at the input divide The ADS774 will begin acquiring a new sample as soon as standard input ranges (0V to +10V, 0V to +20V, ±5V or the conversion is completed, even before the STATUS ±10V) into levels compatible with the CMOS characteristics output falls, and will track the input signal until the next of the internal capacitor array. conversion is started. The ADS774 is designed to complete a conversion and accurately acquire a new signal in 8.5μs max over the full operating temperature range, so that SAMPLING conversions can take place at a full 117kHz. While sampling, the capacitor array switch for the MSB capacitor (S ) is in position “S”, so that the charge on the 1 MSB capacitor is proportional to the voltage level of the CONTROLLING THE ADS774 analog input signal. The remaining array switches (S and 2 The Burr-Brown ADS774 can be easily interfaced to most S ) are set to position “G”. Switch S is closed, setting the 3 C microprocessor systems and other digital systems. The comparator input offset to zero. microprocessor may take full control of each conversion, or the converter may operate in a stand-alone mode, controlled only by the R/C input. Full control consists of selecting an CONVERSION 8- or 12-bit conversion cycle, initiating the conversion, and When a conversion command is received, switch S is 1 reading the output data when ready—choosing either 12 bits opened to trap a charge on the MSB capacitor proportional all at once, or the 8 MSB bits followed by the 4 LSB bits in to the analog input level at the time of the sampling com- a left-justified format. The five control inputs (12/8, CS, A , 0 mand, and switch S is opened to float the comparator input. C R/C, and CE) are all TTL/CMOS-compatible. The functions The charge trapped in the capacitor array can now be moved of the control inputs are described in Table II. The control between the three capacitors in the array by connecting function truth table is shown in Table III. switches S , S , and S to positions “R” (to connect to the 1 2 3 reference) or “G” (to connect to GND), thus changing the STAND-ALONE OPERATION voltage generated at the comparator input. For stand-alone operation, control of the converter is accom- During the first approximation, the MSB capacitor is con- plished by a single control line connected to R/C. In this nected through switch S to the reference, while switches S 1 2 mode CS and A are connected to digital common and CE 0 and S are connected to GND. Depending on whether the 3 and 12/8 are connected to +5V. The output data are comparator output is HIGH or LOW, the logic will then ® ADS774 6 Status +5V 1 28 Output 10µF 2 27 DB11 (MSB) 3 26 DB10 4 25 DB9 Convert Command 5 24 DB8 +5V 6 23 DB7 7 22 DB6 NC* ADS774 8 21 DB5 9 20 DB4 50Ω 10 19 DB3 (1) 11 18 DB2 50Ω 12 17 DB1 Leave Unconnected 13 16 DB0 (LSB) 14 15 ±10V Analog *Not internally connected Input NOTE: (1) Connect to GND or V for EE Emulation Mode. Connect to +5V for Control Mode. FIGURE 2. Basic ±10V Operation. presented as 12-bit words. The stand-alone mode is used in following an 8-bit conversion, the 4LSBs (DB0-DB3) will is latched because it is also involved systems containing dedicated input ports which do not be LOW (logic 0). A 0 require full bus interface capability. in enabling the output buffers. No other control inputs are latched. Conversion is initiated by a HIGH-to-LOW transition of R/C. The three-state data output buffers are enabled when CONVERSION START R/C is HIGH and STATUS is LOW. Thus, there are two possible modes of operation; data can be read with either a The converter initiates a conversion based on a transition positive pulse on R/C, or a negative pulse on STATUS. In occurring on any of three logic inputs (CE, CS, and R/C) as either case the R/C pulse must remain LOW for a minimum shown in Table III. Conversion is initiated by the last of the of 25ns. three to reach the required state and thus all three may be dynamically controlled. If necessary, all three may change Figure 3 illustrates timing with an R/C pulse which goes state simultaneously, and the nominal delay time is the same LOW and returns HIGH during the conversion. In this case, regardless of which input actually starts the conversion. If it the three-state outputs go to the high-impedance state in is desired that a particular input establish the actual start of response to the falling edge of R/C and are enabled for conversion, the other two should be stable a minimum of external access of the data after completion of the conver- 50ns prior to the transition of the critical input. Timing sion. relationships for start of conversion timing are illustrated in Figure 4 illustrates the timing when a positive R/C pulse is Figure 5. The specifications for timing are contained in used. In this mode the output data from the previous conver- Table V. sion is enabled during the time R/C is HIGH. A new The STATUS output indicates the current state of the con- conversion is started on the falling edge of R/C, and the verter by being in a high state only during conversion. three-state outputs return to the high-impedance state until During this time the three state output buffers remain in a the next occurrence of a HIGH R/C pulse. Timing specifica- high-impedance state, and therefore data cannot be read tions for stand-alone operation are listed in Table IV. during conversion. During this period additional transitions of the three digital inputs which control conversion will be FULLY CONTROLLED OPERATION ignored, so that conversion cannot be prematurely termi- Conversion Length nated or restarted. However, if A changes state after the 0 Conversion length (8-bit or 12-bit) is determined by the state beginning of conversion, any additional start conversion of the A input, which is latched upon receipt of a conver- 0 transition will latch the new state of A , possibly resulting in 0 sion start transition (described below). If A is latched 0 an incorrect conversion length (8 bits vs 12 bits) for that HIGH, the conversion continues for 8 bits. The full 12-bit conversion. conversion will occur if A is LOW. If all 12 bits are read 0 ® 7 ADS774 Binary (BIN) Output Input Voltage Range and LSB Values Analog Input Voltage Range Defined As: ±10V ±5V 0V to +10V 0V to +20V One Least Significant Bit FSR 20V 10V 10V 20V n n n n n (LSB) 2 2 2 2 2 n = 8 78.13mV 39.06mV 39.06mV 78.13mV n = 12 4.88mV 2.44mV 2.44mV 4.88mV Output Transition Values FFE to FFF + Full-Scale Calibration +10V – 3/2LSB +5V – 3/2LSB +10V – 3/2LSB +20V – 3/2LSB H H 7FFF to 800 Midscale Calibration (Bipolar Offset) 0V – 1/2LSB 0V – 1/2LSB +5V – 1/2LSB +10V – 1/2LSB H H 000 to 001 Zero Calibration ( – Full-Scale Calibration) –10V + 1/2LSB –5V + 1/2LSB 0V +1/2LSB 0V +1/2LSB H H TABLE I. Input Voltages, Transition Values, and LSB Values. DESIGNATION DEFINITION FUNCTION CE (Pin 6) Chip Enable Must be HIGH (“1”) to either initiate a conversion or read output data. 0-1 edge may be used to initiate a (active high) conversion. CS (Pin 3) Chip Select Must be LOW (“0”) to either initiate a conversion or read output data. 1-0 edge may be used to initiate a (active low) conversion. R/C (Pin 5) Read/Convert Must be LOW (“0”) to initiate either 8- or 12-bit conversions. 1-0 edge may be used to initiate a conversion. (“1” = read) Must be HIGH (“1”) to read output data. 0-1 edge may be used to initiate a read operation. (“0” = convert) A (Pin 4) Byte Address In the start-convert mode, A selects 8-bit (A = “1”) or 12-bit (A = “0”) conversion mode. When reading O O O O Short Cycle output data in two 8-bit bytes, A = “0” accesses 8 MSBs (high byte) and A = “1” accesses 4 LSBs and O O trailing “0s” (low byte). 12/8 (Pin 2) Data Mode Select When reading output data, 12/8 = “1” enables all 12 output bits simultaneously. 12/8 = “0” will enable the (“1” = 12 bits) MSBs or LSBs as determined by the A line. O (“0” = 8 bits) TABLE II. Control Line Functions. CE CS R/C 12/8 A OPERATION O 0 XXXX None X 1 X X X None ↑ 0 0 X 0 Initiate 12-bit conversion 0 0 X 1 Initiate 8-bit conversion ↑ 1 ↓ 0 X 0 Initiate 12-bit conversion ↓ 1 0 X 1 Initiate 8-bit conversion ↓ 1 0 X 0 Initiate 12-bit conversion ↓ 1 0 X 1 Initiate 8-bit conversion 1011 X Enable 12-bit output 10100 Enable 8 MSBs only 10101 Enable 4 LSBs plus 4 trailing zeroes TABLE III. Control Input Truth Table. READING OUTPUT DATA When 12/8 is LOW, the data is presented in the form of two 8-bit bytes, with selection of the byte of interest accom- After conversion is initiated, the output data buffers remain plished by the state of A during the read cycle. When A is in a high-impedance state until the following four logic 0 0 LOW, the byte addressed contains the 8MSBs. When A is 0 conditions are simultaneously met: R/C HIGH, STATUS HIGH, the byte addressed contains the 4LSBs from the LOW, CE HIGH, and CS LOW. Upon satisfaction of these conversion followed by four logic zeros which have been conditions the data lines are enabled according to the state of forced by the control logic. The left-justified formats of the inputs 12/8 and A . See Figure 6 and Table V for timing 0 two 8-bit bytes are shown in Figure 7. Connection of the relationships and specifications. ADS774 to an 8-bit bus for transfer of the data is illustrated In most applications the 12/8 input will be hard-wired in in Figure 8. The design of the ADS774 guarantees that the either the HIGH or LOW condition, although it is fully TTL A input may be toggled at any time with no damage to the 0 and CMOS-compatible and may be actively driven if de- converter; the outputs which are tied together in Figure 8 sired. When 12/8 is HIGH, all 12 output lines (DB0-DB11) cannot be enabled at the same time. The A input is usually 0 are enabled simultaneously for full data word transfer to a driven by the least significant bit of the address bus, allow- 12-bit or 16-bit bus. In this situation the A state is ignored 0 ing storage of the output data word in two consecutive when reading the data. memory locations. ® ADS774 8 t HRL R/C R/C t HRH t DS t DS STATUS t CONVERSION t t STATUS DDR HDR t CONVERSION t t HDR HS High-Z High-Z-State Data Valid DB11-DB0 High-Z-State DB11-DB0 Data Valid Data Valid FIGURE 3. R/C Pulse Low—Outputs Enabled After Conver- FIGURE 4. R/C Pulse High — Outputs Enabled Only While sion. R/C Is High. SYMBOL PARAMETER MIN TYP MAX UNITS t Low R/C Pulse Width 25 ns HRL t STS Delay from R/C 200 ns DS t Data Valid After R/C Low 25 ns HDR t High R/C Pulse Width 100 ns HRH t Data Access Time 150 ns DDR TABLE IV. Stand-Alone Mode Timing. (T = T to T ). A MIN MAX SYMBOL PARAMETER MIN TYP MAX UNITS Convert Mode t STS delay from CE 60 200 ns DSC t CE Pulse width 50 30 ns HEC t CS to CE setup 50 20 ns SSC t CS low during CE high 50 20 ns HSC t R/C to CE setup 50 0 ns SRC t R/C low during CE high 50 20 ns HRC t A to CE setup 0 ns SAC O t A valid during CE high 50 20 ns HAC O Read Mode t Access time from CE 75 150 ns DD t Data valid after CE low 25 35 ns HD t Output float delay 100 150 ns HL t CS to CE setup 50 0 ns SSR t R/C to CE setup 0 ns SRR t A to CE setup 50 25 ns SAR O t CS valid after CE low 0 ns HSR t R/C high after CE low 0 ns HRR t A valid after CE low 50 ns HAR O t STATUS delay after data valid 75 150 375 ns HS TABLE V. Timing Specifications, Fully Controlled Operation. (T = T to T ). A MIN MAX CE t CE HEC t t SSR HSR t SSC CS CS t t HRR HSC R/C R/C t SSR t t SRC HRC A 0 A 0 t SAC t t SAR HAR Status t HAC Status t * X t DSC t t HS HD High Impedance DB11-DB0 DB11-DB0 High-Z Data Valid * t includes t + t in ADC774 Emulation Mode, X AQ C t DD t only in S/H Control Mode. C t HL FIGURE 5. Conversion Cycle Timing. FIGURE 6. Read Cycle Timing. ® 9 ADS774 Word 1 Word 2 Processor DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Converter DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 FIGURE 7. 12-Bit Data Format for 8-Bit Systems. STATUS 28 2 27 12/8 DB11 (MSB) 26 A 4 A 25 O O 24 Address Data Bus Bus 23 22 ADS774 21 20 19 18 17 DB0 (LSB) 16 Digital Common 15 FIGURE 8. Connection to an 8-Bit Bus. S/H CONTROL MODE tion is made about the input level after the convert command AND ADC774 EMULATION MODE arrives, since the input signal is sampled and conversion begins immediately after the convert command. This means The Emulation Mode allows the ADS774 to be dropped into that a convert command can also be used to switch an input most existing ADC774 sockets without changes to other multiplexer or change gains on a programmable gain ampli- system hardware or software. In existing sockets, the analog fier, allowing the input signal to settle before the next input is held stable during the conversion period so that acquisition at the end of the conversion. Because aperture accurate conversions can proceed, but the input can change jitter is minimized in the Control Mode, a high input fre- rapidly at any time before the conversion starts. The Emula- quency can be converted without an external sample/hold. tion Mode uses the stability of the analog input during the conversion period to both acquire and convert in a maximum In the Emulation Mode, a delay time is introduced between of 8μs (8.5μs over temperature.) In fact, system throughput the convert command and the start of conversion to allow the can be increased, since the input to the ADS774 can start ADS774 enough time to acquire the input signal before slewing before the end of a conversion (after the acquisition converting. This increases the effective aperture delay time time), which is not possible with existing ADC774s. from 0.02μs to 1.6μs, but allows the ADS774 to replace the ADC774 in most circuits without additional changes. In The Control Mode is provided to allow full use of the designs where the input to the ADS774 is changing rapidly internal sample/hold, eliminating the need for an external in the 200ns prior to a convert command, system perfor- sample/hold in most applications. As compared with sys- mance may be enhanced by delaying the convert command tems using separate sample/hold and A/D, the ADS774 in by 200ns. the Control Mode also eliminates the need for one of the control signals, usually the convert command. The com- When using the ADS774 in the Emulation Mode to replace mand that puts the internal sample/hold in the hold state existing converters in current designs, a sample/hold ampli- also initiates a conversion, reducing timing constraints in fier often precedes the converter. In these cases, no addi- many systems. tional delay in the convert command will be needed. The existing sample/hold will not be slewing excessively when The basic difference between these two modes is the going from the sample mode to the hold mode prior to a assumptions about the state of the input signal both before conversion. and during the conversion. The differences are shown in Figure 9 and Table VI. In the Control Mode, it is assumed In both modes, as soon as the conversion is completed the that during the required 1.4μs acquisition time the signal is internal sample/hold circuit immediately begins slewing to not changing faster than the ADS774 can track. No assump- track the input signal. ® ADS774 10 In particular, the unused input pin should not be connected INSTALLATION to any capacitive load, including high impedance switches. LAYOUT PRECAUTIONS Even a few pF on the unused pin can degrade acquisition time. Analog (pin 9) and digital (pin 15) commons are not con- nected together internally in the ADS774, but should be Coupling between analog input and digital lines should be connected together as close to the unit as possible and to an minimized by careful layout. For instance, if the lines must analog common ground plane beneath the converter on the cross, they should do so at right angles. Parallel analog and component side of the board. In addition, a wide conductor digital lines should be separated from each other by a pattern pattern should run directly from pin 9 to the analog supply connected to common. common, and a separate wide conductor pattern from pin 15 If external full scale and offset potentiometers are used, the to the digital supply common. potentiometers and associated resistors should be as close as If the single-point system common cannot be established possible to the ADS774. directly at the converter, pin 9 and pin 15 should still be connected together at the converter. A single wide conductor POWER SUPPLY DECOUPLING pattern then connects these two pins to the system common. On the ADS774, +5V (to Pin 1) is the only power supply In either case, the common return of the analog input signal required for correct operation. Pin 7 is not connected inter- should be referenced to pin 9 of the ADC. This prevents any nally, so there is no problem in existing ADC774 sockets voltage drops that might occur in the power supply common where this is connected to +15V. Pin 11 (V ) is only used EE returns from appearing in series with the input signal. as a logic input to select modes of control over the sampling The speed of the ADS774 requires special caution regarding function as described above. When used in an existing whichever input pin is unused. For 10V input ranges, pin 14 ADC774 socket, the –15V on pin 11 selects the ADC774 (20V Range) must be unconnected, and for 20V input Emulation Mode. Since pin 11 is used as a logic input, it is ranges, pin 13 (10V Range) must be unconnected. In both immune to typical supply variations. cases, the unconnected input should be shielded with ground plane to reduce noise pickup. S/H CONTROL MODE ADC774 EMULATION MODE (Pin 11 Connected to +5V) (Pin 11 Connected to 0V to –15V) SYMBOL PARAMETER MIN TYP MAX MIN TYP MAX UNITS t + t Throughput Time: AQ C 12-bit Conversions 8 8.5 8 8.5 μs 8-bit Conversions 6 6.3 6 6.3 μs t Conversion Time: C 12-bit Conversions 6.4 6.4 μs 8-bit Conversions 4.4 4.4 μs t Acquisition Time 1.4 1.4 μs AQ t Aperture Delay 20 1600 ns AP t Aperture Uncertainty 0.3 10 ns J TABLE VI. Conversion Timing, T to T . MIN MAX R/C t C t AP Signal Signal S/H Control Mode Conversion Acquisition Acquisition Pin 11 connected to +5V. t AQ t C t AP ADC774 Emulation Mode* Signal Signal Conversion Acquisition Acquisition Pin 11 connected to V or ground. EE t AQ *In the ADC774 Emulation Mode, a convert command triggers a delay that allows the ADS774 enough time to acquire the input signal before converting. FIGURE 9. Signal Acquisition and Conversion Timing. ® 11 ADS774 connected either to Pin 9 (Analog Common) for unipolar +V CC operation, or to Pin 8 (2.5V Ref Out), or the external Unipolar Full-Scale reference, for bipolar operation. Full-scale and offset adjust- Offset Adjust Adjust ments are described below. R 1 R 2 100kΩ The input impedance of the ADS774 is typically 50kΩ in the 10 Ref In 20V ranges and 12kΩ in the 10V ranges. This is signifi- 100Ω ADS774 cantly higher than that of traditional ADC774 architectures, 100kΩ 2.5V 8 Ref Out reducing the load on the input source in most applications. –V CC 100Ω 12 Bipolar Offset INPUT STRUCTURE R 3 10V Figure 12 shows the resistor divider input structure of the Range ADS774. Since the input is driving a capacitor in the CDAC 13 Analog during acquisition, the input is looking into a high imped- Input ance node as compared with traditional ADC774 architec- 14 tures, where the resistor divider network looks into a com- 20V Range parator input node at virtual ground. 9 To understand how this circuit works, it is necessary to Analog know that the input range on the internal sampling capacitor Common is from 0V to +3.33V, and the analog input to the ADS774 must be converted to this range. Unipolar 20V range can be FIGURE 10. Unipolar Configuration. used as an example of how the divider network functions. In 20V operation, the analog input goes into pin 14. Pin 13 is Full-Scale Adjust left unconnected and pin 12 is connected to pin 9, analog R 2 common. From Figure 12, it is clear that the input to the 10 Ref In 100Ω capacitor array will be the analog input voltage on pin 14 ADS774 divided by the resistor network (42kΩ + 42kΩ || 10.5kΩ). A 2.5V 8 Ref Out 20V input at pin 14 is divided to 3.33V at the capacitor 100Ω array, while a 0V input at pin 14 gives 0V at the capacitor Bipolar 12 Bipolar Offset Offset array. R 1 Adjust The main effect of the 10kΩ internal resistor on pin 12 is to 13 provide the same offset adjust response as that of traditional Analog 10V Input ADC774 architectures without changing the external trimpot Range values. 14 20V Range SINGLE SUPPLY OPERATION 9 The ADS774 is designed to operate from a single +5V Analog supply, and handle all of the unipolar and bipolar input Common ranges, in either the Control Mode or the Emulation Mode as described above. Pin 7 is not connected internally. This is FIGURE 11. Bipolar Configuration. The +5V supply should be bypassed with a 10μF tantalum 42kΩ Pin 14 capacitor located close to the converter to promote noise- 20V Range free operations, as shown in Figure 2. Noise on the power supply lines can degrade the converter’s performance. Noise and spikes from a switching power supply are especially 21kΩ Pin 13 Capacitor troublesome. 10V Range Array* 21kΩ RANGE CONNECTIONS The ADS774 offers four standard input ranges: 0V to +10V, 0V to +20V, ±5V, or ±10V. Figures 10 and 11 show the 10.5kΩ Pin 12 necessary connections for each of these ranges, along with Bipolar the optional gain and offset trim circuits. If a 10V input Offset 10kΩ range is required, the analog input signal should be con- nected to pin 13 of the converter. A signal requiring a 20V *10pF when sampling range is connected to pin 14. In either case the other pin of the two is left unconnected. Pin 12 (Bipolar Offset) is FIGURE 12. ADS774 Input Structure. ® ADS774 12 where +12V or +15V is supplied on traditional ADC774s. If adjustment is required, connect the converter as shown in Pin 11, the –12V or –15V supply input on traditional Figure 10. Sweep the input through the end-point transition ADC774s, is used only as a logic input on the ADS774. voltage (0V + 1/2LSB; +1.22mV for the 10V range, +2.44mV There is a resistor divider internally on pin 11 to reduce that for the 20V range) that causes the output code to be DB0 ON input to a correct logic level within the ADS774, and this (HIGH). Adjust potentiometer R until DB0 is alternately 1 resistor will add 10mW to 15mW to the power consumption toggling ON and OFF with all other bits OFF. Then adjust of the ADS774 when –15V is supplied to pin 11. To full scale by applying an input voltage of nominal full-scale minimize power consumption in a system, pin 11 can be minus 3/2LSB, the value which should cause all bits to be simply grounded (for Emulation Mode) or tied to +5V (for ON. This value is +9.9963V for the 10V range and +19.9927V Control Mode.) for the 20V range. Adjust potentiometer R until bits DB1- 2 DB11 are ON and DB0 is toggling ON and OFF. There are no other modifications required for the ADS774 to function with a single +5V supply. CALIBRATION PROCEDURE—BIPOLAR RANGES If external adjustments of full-scale and bipolar offset are CALIBRATION not required, replace the potentiometers in Figure 11 by 50Ω, 1% metal film resistors. OPTIONAL EXTERNAL FULL-SCALE AND OFFSET ADJUSTMENTS If adjustments are required, connect the converter as shown in Figure 11. The calibration procedure is similar to that Offset and full-scale errors may be trimmed to zero using described above for unipolar operation, except that the offset external offset and full-scale trim potentiometers connected adjustment is performed with an input voltage which is to the ADS774 as shown in Figures 10 and 11 for unipolar 1/2LSB above the minus full-scale value (–4.9988V for the and bipolar operation. ±5V range, –9.9976V for the ±10V range). Adjust R for 1 DB0 to toggle ON and OFF with all other bits OFF. To CALIBRATION PROCEDURE— adjust full-scale, apply a DC input signal which is 3/2LSB UNIPOLAR RANGES below the nominal plus full-scale value (+4.9963V for ±5V If external adjustments of full-scale and offset are not range, +9.9927V for ±10V range) and adjust R for DB0 to 2 required, replace R in Figure 10 with a 50Ω 1% metal film 2 toggle ON and OFF with all other bits ON. resistor and connect pin 12 to pin 9, omitting the other adjustment components. ® 13 ADS774