• • Very Low Power/Voltage CMOS SRAM 512K X 8 bit BSI BS62LV4007 „ FEATURES „ DESCRIPTION • Vcc operation voltage : 4.5V ~ 5.5V The BS62LV4007 is a high performance, very low power CMOS • Very low power consumption : Static Random Access Memory organized as 524,288 words by 8 bits Vcc = 5.0V C-grade: 68mA (@55ns) operating current and operates from a range of 4.5V to 5.5V supply voltage. I -grade: 70mA (@55ns) operating current Advanced CMOS technology and circuit techniques provide both high C-grade: 58mA (@70ns) operating current speed and low power features with a typical CMOS standby current of I -grade: 60mA (@70ns) operating current o o 2.0uA at 5.0V/25 C and maximum access time of 55ns at 5.0V/85 C. 2.0uA (Typ.) CMOS standby current Easy memory expansion is provided by an active LOW chip enable • High speed access time : (CE) , and active LOW output enable (OE) and three-state output -55 55ns drivers. -70 70ns The BS62LV4007 has an automatic power down feature, reducing the • Automatic power down when chip is deselected power consumption significantly when chip is deselected. • Fully static operation The BS62LV4007 is available in the JEDEC standard 32L SOP, TSOP • Data retention supply voltage as low as 1.5V , PDIP, TSOP II and STSOP package. • Easy expansion with CE and OE options • Three state outputs and TTL compatible „ PRODUCT FAMILY POWER DISSIPATION SPEED STANDBY Operating ( ns ) PKG PRODUCT OPERATING Vcc ( I CCSB1 , Max ) ( I CC , Max ) TYPE FAMILY TEMPERATURE RANGE 55ns :4.5~5.5V Vcc = 5.0V Vcc =5.0V Vcc =5.0V 70ns :4.5~5.5V 55ns 70ns BS62LV4007TC - TSOP 32 BS62LV4007STC - STSOP 32 O O BS62LV4007SC +0 C to +70 C 4.5V ~ 5.5V 55 / 70 30uA 68mA 58mA SOP -32 BS62LV4007EC TSOP2-32 - BS62LV4007PC PDIP 32 BS62LV4007TI TSOP-32 BS62LV4007STI STSOP-32 O O BS62LV4007SI - 60uA - 40 C to +85 C 4.5V ~ 5.5V 55 / 70 70mA 60mA SOP 32 BS62LV4007EI TSOP2-32 BS62LV4007PI PDIP - 32 „ PIN CONFIGURATIONS „ BLOCK DIAGRAM A18 1 VCC 32 A16 2 A15 A13 31 A14 3 A17 A17 30 A15 A12 4 WE 29 Address A18 A7 Memory Array 5 A13 28 22 2048 A16 Row A6 6 27 A8 Input A14 A5 7 A9 26 A12 2048 X 2048 Decoder A4 BS62LV4007SC 8 25 A11 Buffer A7 A3 BS62LV4007SI 9 OE A6 24 BS62LV4007EC A2 A5 10 23 A10 BS62LV4007EI A1 A4 11 CE 22 BS62LV4007PC A0 12 DQ7 21 BS62LV4007PI 2048 DQ0 13 DQ6 20 DQ0 8 Data DQ1 14 DQ5 19 8 Column I/O Input DQ2 DQ1 15 DQ4 18 Buffer DQ2 Write Driver GND 16 DQ3 17 DQ3 Sense Amp 8 DQ4 8 Data DQ5 256 Output A11 1 32 OE Buffer DQ6 A9 2 31 A10 DQ7 Column Decoder 3 30 A8 CE A13 4 29 DQ7 16 WE 5 28 DQ6 6 27 CE A17 DQ5 BS62LV4007TC Control A15 7 26 DQ4 WE Address Input Buffer BS62LV4007STC VCC 8 25 DQ3 OE A18 9 BS62LV4007TI 24 GND BS62LV4007STI A16 10 23 DQ2 Vdd A14 11 22 DQ1 GND A11 A9 A8 A3 A2 A1 A0 A10 A12 12 21 DQ0 A7 13 20 A0 14 19 A6 A1 A5 15 18 A2 A4 16 17 A3 Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice. R0201-BS62LV4007 Revision 1.1 1 Jan. 2004 BSI BS62LV4007 „ PIN DESCRIPTIONS Name Function A0-A18 Address Input These 19 address inputs select one of the 524,288 x 8-bit words in the RAM CE Chip Enable Input CE is active LOW. Chip enables must be active when data read from or write to the device. if chip enable is not active, the device is deselected and is in a standby power mode. The DQ pins will be in the high impedance state when the device is deselected. WE Write Enable Input The write enable input is active LOW and controls read and write operations. With the chip selected, when WE is HIGH and OE is LOW, output data will be present on the DQ pins; when WE is LOW, the data present on the DQ pins will be written into the selected memory location. OE Output Enable Input The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impedance state when OE is inactive. DQ0-DQ7 Data Input/Output These 8 bi-directional ports are used to read data from or write data into the RAM. Ports Vcc Power Supply GND Ground „ TRUTH TABLE MODE WE CE OE I/O OPERATION Vcc CURRENT Not selected X H X High Z I , I CCSB CCSB1 Output Disabled H L H High Z I CC OUT Read H L L D I CC Write L L X DIN I CC (1) „ ABSOLUTE MAXIMUM RATINGS „ OPERATING RANGE AMBIENT SYMBOL PARAMETER RATING UNITS RANGE Vcc TEMPERATURE Terminal Voltage with -0.5 to V VTERM O O Respect to GND Vcc+0.5 Commercial 0 C to +70 C 4.5V ~ 5.5V O Temperature Under Bias -40 to +85 C TBIAS O O Industrial -40 C to +85 C 4.5V ~ 5.5V O TSTG Storage Temperature -60 to +150 C Power Dissipation 1.0 W PT (1) o „ CAPACITANCE (TA = 25 C, f = 1.0 MHz) DC Output Current 20 mA IOUT SYMBOL PARAMETER CONDITIONS MAX. UNIT 1. Stresses greater than those listed under ABSOLUTE MAXIMUM CIN Input VIN=0V 6 pF Capacitance RATINGS may cause permanent damage to the device. This is a Input/Output CDQ VI/O=0V 8 pF stress rating only and functional operation of the device at these Capacitance or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute 1. This parameter is guaranteed and not 100% tested. maximum rating conditions for extended periods may affect reliability. R0201-BS62LV4007 Revision 1.1 2 Jan. 2004 BSI BS62LV4007 o „ DC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85 C ) PARAMETER (1) PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNITS NAME Guaranteed Input Low VIL Vcc = 5.0 V -0.5 -- 0.8 V (3) Voltage Guaranteed Input High VIH Vcc = 5.0 V 2.2 -- Vcc+0.3 V (3) Voltage IIL Input Leakage Current Vcc = Max, VIN = 0V to Vcc -- -- 1 uA IH IH Vcc = Max, CE = V , or OE = V , ILO Output Leakage Current -- -- 1 uA VI/O = 0V to Vcc Vcc = 5.0 V -- OL -- 0.4 VOL Output Low Voltage Vcc = Max, I = 2.0mA V VOH V OH Output High Voltage Vcc = Min, I = -1.0mA Vcc = 5.0 V 2.4 -- -- (5) 55ns 70 CE = VIL, IDQ = 0mA, CC I Operating Power Supply Vcc = 5.0 V -- -- mA (2) Current F=Fmax 70ns 60 ICCSB CE = VIH, IDQ = 0mA Vcc = 5.0 V -- -- mA Standby Current-TTL 1.0 (4) CE Vcc-0.2V, ≧ ICCSB1 Standby Current-CMOS Vcc = 5.0 V -- uA 2.0 60 IN IN V ≧ Vcc - 0.2V or V ≦ 0.2V o 1. Typical characteristics are at TA = 25 C. 2. Fmax = 1/t . RC 3. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included. o o 4. IccSB1_MAX. is 30uA at Vcc=5.0V and TA=70 C. 5. Icc_MAX. is 68mA(@55ns) / 58mA(@70ns) at Vcc=5.0V and TA=0~70 C. o „ DATA RETENTION CHARACTERISTICS ( TA = -40 to + 85 C ) (1) SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNITS CE ≧ Vcc - 0.2V V Vcc for Data Retention 1.5 -- -- V DR VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V CE ≧ Vcc - 0.2V I CCDR Data Retention Current -- 0.3 1.3 uA VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V Chip Deselect to Data tCDR 0 -- -- ns Retention Time See Retention Waveform (2) t Operation Recovery Time T -- -- ns R RC O 1. Vcc = 1.5V, T = + 25 C A 2. t = Read Cycle Time RC O 3. IccDR_MAX. is 0.8uA at TA=70 C. „ LOW V DATA RETENTION WAVEFORM ( CE Controlled ) CC Data Retention Mode VDR≥ 1.5V Vcc Vcc Vcc t R t CDR CE V ≥ cc - 0.2V VIH VIH CE R0201-BS62LV4007 Revision 1.1 3 Jan. 2004 BSI BS62LV4007 „AC TEST CONDITIONS „ KEY TO SWITCHING WAVEFORMS (Test Load and Input/Output Reference) Input Pulse Levels Vcc / 0V WAVEFORM INPUTS OUTPUTS MUST BE MUST BE Input Rise and Fall Times 1V/ns STEADY STEADY MAY CHANGE WILL BE FROM H TO L CHANGE Input and Output 0.5Vcc FROM H TO L Timing Reference Level MAY CHANGE WILL BE Output Load C = 30pF+1TTL L FROM L TO H CHANGE C = 100pF+1TTL L FROM L TO H , DON T CARE: CHANGE : ANY CHANGE STATE PERMITTED UNKNOWN DOES NOT CENTER APPLY LINE IS HIGH IMPEDANCE ”OFF ”STATE o „ AC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85 C ) READ CYCLE JEDEC CYCLE TIME : 55ns CYCLE TIME : 70ns PARAMETER PARAMETER DESCRIPTION (Vcc = 4.5~5.5V) (Vcc = 4.5~5.5V) UNIT NAME MIN. TYP. MAX. MIN. TYP. MAX. NAME t t Read Cycle Time 55 -- -- 70 -- -- ns AVAX RC t t Address Access Time -- -- 55 -- -- 70 ns AVQV AA t t Chip Select Access Time -- -- 55 -- -- 70 ns ELQV ACS t t Output Enable to Output Valid -- -- 30 -- -- 35 ns GLQV OE t t Chip Select to Output Low Z 10 -- -- 10 -- -- ns ELQX CLZ t t Output Enable to Output in Low Z 10 -- -- 10 -- -- ns GLQX OLZ t t Chip Deselect to Output in High Z -- -- 30 -- -- 35 ns EHQZ CHZ t t Output Disable to Output in High Z -- -- 25 -- -- 30 ns GHQZ OHZ t t AXOX OH Data Hold from Address Change 10 -- -- 10 -- -- ns „ SWITCHING WAVEFORMS (READ CYCLE) (1,2,4) READ CYCLE1 t RC ADDRESS t AA t OH t OH D OUT R0201-BS62LV4007 Revision 1.1 4 Jan. 2004 BSI BS62LV4007 (1,3,4) READ CYCLE2 CE t ACS (5) t CHZ (5) t CLZ D OUT (1,4) READ CYCLE3 t RC ADDRESS t AA OE t OH t OE t OLZ CE t ACS (5) t OHZ (1,5) t CHZ (5) t CLZ D OUT NOTES: 1. WE is high in read Cycle. 2. Device is continuously selected when CE = VIL. 3. Address valid prior to or coincident with CE transition low. 4. OE = VIL . 5. The parameter is guaranteed but not 100% tested. R0201-BS62LV4007 Revision 1.1 5 Jan. 2004 BSI BS62LV4007 o „ AC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85 C ) WRITE CYCLE JEDEC CYCLE TIME : 55ns CYCLE TIME : 70ns PARAMETER (Vcc = 4.5~5.5V) (Vcc = 4.5~5.5V) PARAMETER DESCRIPTION UNIT NAME MIN. TYP. MAX. MIN. TYP. MAX. NAME t t Write Cycle Time AVAX WC 55 -- -- 70 -- -- ns t t E1LWH CW Chip Select to End of Write 55 -- -- 70 -- -- ns t t AVW L AS Address Set up Time 0 -- -- 0 -- -- ns t t Address Valid to End of Write AVWH AW 55 -- -- 70 -- -- ns t t WLWH WP Write Pulse Width 30 -- -- 35 -- -- ns t t Write Recovery Time (CE , WE) WHAX WR 0 -- -- 0 -- -- ns t t Write to Output in High Z WLOZ WHZ -- -- 25 -- -- 30 ns t t DVWH DW Data to Write Time Overlap 25 -- -- 30 -- -- ns t t Data Hold from Write Time WHDX DH 0 -- -- 0 -- -- ns t t GHOZ OHZ Output Disable to Output in High Z -- -- 25 -- -- 30 ns t t WHQX OW End ot Write to Output Active 5 -- -- 5 -- -- ns „ SWITCHING WAVEFORMS (WRITE CYCLE) (1) WRITE CYCLE1 t WC ADDRESS (3) t WR OE (11) t CW (5) CE t AW t WP (2) t AS WE (4,10) t OHZ D OUT t DH t DW D IN R0201-BS62LV4007 Revision 1.1 6 Jan. 2004 BSI BS62LV4007 (1,6) WRITE CYCLE2 t WC ADDRESS (11) t CW (5) CE t AW t WP (2) WE t AS (4,10) t OW t WHZ (7) (8) D OUT t DW (8,9) t DH D IN NOTES: 1. WE must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. TWR is measured from the earlier of CE or WE going high at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state. 6. OE is continuously low (OE = VIL ). 7. DOUT is the same phase of write data of this write cycle. 8. DOUT is the read data of next address. 9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. The parameter is guaranteed but not 100% tested. 11. TCW is measured from the later of CE going low to the end of write. R0201-BS62LV4007 Revision 1.1 7 Jan. 2004 BSI BS62LV4007 „ ORDERING INFORMATION BS62LV4007 X X Z Y Y SPEED 55: 55ns 70: 70ns PKG MATERIAL -: Normal G: Green P: Pb free GRADE o o C: +0 C ~ +70 C o o I: -40 C ~ +85 C PACKAGE S: SOP E: TSOP 2 ST: Small TSOP T: TSOP P: PDIP Note: BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support systems and critical medical instruments. „ PACKAGE DIMENSIONS b WITH PLATING c c1 b1 BASE METAL SECTION A-A SOP -32 R0201-BS62LV4007 Revision 1.1 8 Jan. 2004 BSI BS62LV4007 TSOP2 - 32 TSOP - 32 R0201-BS62LV4007 Revision 1.1 9 Jan. 2004 BSI BS62LV4007 „ PACKAGE DIMENSIONS (continued) STSOP - 32 PDIP - 32 R0201-BS62LV4007 Revision 1.1 10 Jan. 2004