ANALOG DEVICES ADA4896-2

1 nV/√Hz, Low Power, Rail-to-Rail Output Amplifiers Data Sheet ADA4896-2/ADA4897-1/ADA4897-2 FEATURES FUNCTIONAL BLOCK DIAGRAM Low wideband noise NC 1 8 DISABLE 1 nV/√Hz –IN 2 7 +V S 2.8 pA/√Hz +IN 3 6 OUT Low 1/f noise: 2.4 nV/√Hz at 10 Hz –V 4 5 NC S Low distortion: −115 dBc at 100 kHz, V = 2 V p-p OUT Figure 1. 8-Lead SOIC (ADA4897-1) Low power: 3 mA per amplifier Low input offset voltage: 0.5 mV maximum 8 High speed V = ±5V S −3 dB bandwidth: 230 MHz (G = +1) 7 Slew rate: 120 V/μs 6 Settling time to 0.1%: 45 ns Rail-to-rail output 5 Wide supply range: 3 V to 10 V Disable feature (ADA4897-1/ADA4897-2) 4 APPLICATIONS 3 Low noise preamplifier 2 Ultrasound amplifiers PLL loop filters 1 High performance ADC drivers 0 DAC buffers 1 10 100 1k 10k 100k 1M 5M FREQUENCY (Hz) Figure 2. Voltage Noise vs. Frequency GENERAL DESCRIPTION The ADA4896-2/ADA4897-1/ADA4897-2 are unity-gain stable, Table 1. Other Low Noise Amplifiers low noise, rail-to-rail output, high speed voltage feedback amplifiers V (nV/√Hz) Supply N that have a quiescent current of 3 mA. With a 1/f noise of Part No. At 1 kHz At 100 kHz BW (MHz) Voltage (V) 2.4 nV/√Hz at 10 Hz and a spurious-free dynamic range of −80 dBc AD797 0.9 0.9 8 10 to 30 at 2 MHz, the ADA4896-2/ADA4897-1/ADA4897-2 are ideal AD8021 5 2.1 490 5 to 24 solutions in a variety of applications, including ultrasound, low AD8099 3 0.95 510 5 to 12 AD8045 6 3 1000 3.3 to 12 noise preamplifiers, and drivers of high performance ADCs. The ADA4899-1 1.4 1 600 5 to 12 Analog Devices, Inc., proprietary next-generation SiGe bipolar ADA4898-1/ 0.9 0.9 65 10 to 32 process and innovative architecture enable such high performance ADA4898-2 amplifiers. The ADA4896-2/ADA4897-1/ADA4897-2 have 230 MHz Table 2. Complementary ADCs bandwidth, 120 V/μs slew rate, and settle to 0.1% in 45 ns. Part No. Bits Speed (MSPS) Power (mW) With a wide supply voltage range of 3 V to 10 V, the ADA4896-2/ AD7944 14 2.5 15.5 ADA4897-1/ADA4897-2 are ideal candidates for systems that AD7985 16 2.5 15.5 require high dynamic range, precision, low power, and high speed. AD7986 18 2 15 The ADA4896-2 is available in 8-lead LFCSP and 8-lead MSOP packages. The ADA4897-1 is available in 8-lead SOIC and 6-lead SOT-23 packages. The ADA4897-2 is available in a 10-lead MSOP package. The ADA4896-2/ADA4897-1/ADA4897-2 operate over the extended industrial temperature range of −40°C to +125°C. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. VOLTAGE NOISE (nV/√Hz) 09447-101 09447-102 ADA4896-2/ADA4897-1/ADA4897-2 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1  Theory of Operation ...................................................................... 17  Applications ....................................................................................... 1  Amplifier Description ................................................................ 17  General Description ......................................................................... 1  Input Protection ......................................................................... 17  Functional Block Diagram .............................................................. 1  Disable Operation ...................................................................... 17  Revision History ............................................................................... 2  DC Errors .................................................................................... 18  Specif ica t ions ..................................................................................... 3  Bias Current Cancellation ......................................................... 18  ±5 V Supply ................................................................................... 3  Noise Considerations ................................................................. 19  +5 V Supply ................................................................................... 4  Capacitance Drive ...................................................................... 19  +3 V Supply ................................................................................... 6  Applications Information .............................................................. 20  Absolute Maximum Ratings ............................................................ 8  Typical Performance Values ...................................................... 20  Thermal Resistance ...................................................................... 8  Low Noise, Gain Selectable Amplifier ..................................... 21  Maximum Power Dissipation ..................................................... 8  Medical Ultrasound Applications ............................................ 22  ESD Caution .................................................................................. 8  Layout Considerations ............................................................... 24  Pin Configurations and Function Descriptions ........................... 9  Outline Dimensions ....................................................................... 25  Typical Performance Characteristics ........................................... 11  Ordering Guide .......................................................................... 27  REVISION HISTORY 4/12—Rev. A to Rev. B Change to Figure 26; Moved Figure 26........................................ 13 Changes to Figure 37 ...................................................................... 15 Changed 6-Lead Single SOT-23 (ADA4897-1) Thermal Reistance from 306°C/W to 150°C/W ........................................... 8 Changes to Amplifier Description Section, Disable Operation Changes to Figure 3 .......................................................................... 8 Section, Figure 44, and Figure 45 ................................................. 17 10/11—Rev. 0 to Rev. A Added Bias Current Cancellation Section, Figure 47, Added ADA4897-2 and 10-Lead MSOP ......................... Universal Table 11, and Table 12 .................................................................... 18 Change to Table 1 ............................................................................. 1 Changes to Table 13 ....................................................................... 20 Changes to Table 3 ............................................................................ 3 Changes to Low Noise, Gain Selectable Amplifier Section Changes to Table 4 ............................................................................ 4 and Figure 52 ................................................................................... 21 Changes to Table 5 ............................................................................ 6 Deleted Figure 51 ............................................................................ 22 Changes to Table 7 and Figure 3 ..................................................... 8 Changes to Power Supply Bypassing Section ............................. 24 Changes to Figure 4, Table 8, and Table 9 ..................................... 9 Moved Figure 57 ............................................................................. 25 Added Figure 8 and Table 10; Renumbered Sequentially ......... 10 Moved Figure 58 ............................................................................. 26 Changed Summary Statement for Typical Performance Added Figure 60 ............................................................................. 27 Characteristics Section ................................................................... 11 Changes to Ordering Guide .......................................................... 27 Changes to Figure 18 ...................................................................... 12 7/11—Revision 0: Initial Version Change to Figure 20 ....................................................................... 12 Rev. B | Page 2 of 28 Data Sheet ADA4896-2/ADA4897-1/ADA4897-2 SPECIFICATIONS ±5 V SUPPLY T = 25°C, G = +1, R = 1 kΩ to ground, unless otherwise noted. A L Table 3. Parameter Test Conditions/Comments Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Bandwidth G = +1, VOUT = 0.02 V p-p 230 MHz G = +1, V = 2 V p-p 30 MHz OUT G = +2, V = 0.02 V p-p 90 MHz OUT Bandwidth for 0.1 dB Flatness G = +2, VOUT = 2 V p-p, RL = 100 Ω 7 MHz Slew Rate G = +2, VOUT = 6 V step 120 V/μs Settling Time to 0.1% G = +2, VOUT = 2 V step 45 ns Settling Time to 0.01% G = +2, V = 2 V step 90 ns OUT NOISE/HARMONIC PERFORMANCE Harmonic Distortion (SFDR) VOUT = 2 V p-p f = 100 kHz −115 dBc C f = 1 MHz −93 dBc C fC = 2 MHz −80 dBc fC = 5 MHz −61 dBc Input Voltage Noise f = 10 Hz 2.4 nV/√Hz f = 100 kHz 1 nV/√Hz Input Current Noise f = 10 Hz 11 pA/√Hz f = 100 kHz 2.8 pA/√Hz 0.1 Hz to 10 Hz Noise G = +101, RF = 1 kΩ, RG = 10 Ω 99 nV p-p DC PERFORMANCE Input Offset Voltage −500 −28 +500 μV Input Offset Voltage Drift 0.2 μV/°C Input Bias Current −17 −11 −4 μA Input Bias Current Drift 3 nA/°C Input Bias Offset Current −0.6 −0.02 +0.6 μA Open-Loop Gain V = −4 V to +4 V 100 110 dB OUT INPUT CHARACTERISTICS Input Resistance Common-Mode 10 MΩ Differential 10 kΩ Input Capacitance Common-Mode 3 pF Differential 11 pF Input Common-Mode Voltage Range −4.9 to +4.1 V V = −2 V to +2 V −92 −120 dB Common-Mode Rejection Ratio CM (CMRR) OUTPUT CHARACTERISTICS Output Overdrive Recovery Time V = ±5 V, G = +2 81 ns IN Output Voltage Swing Positive RL = 1 kΩ 4.85 4.96 V R = 100 Ω 4.5 4.73 V L Negative R = 1 kΩ −4.85 −4.97 V L R = 100 Ω −4.5 −4.84 V L Output Current SFDR = −45 dBc 80 mA Short-Circuit Current Sinking/sourcing 135 mA Capacitive Load Drive 30% overshoot, G = +2 39 pF Rev. B | Page 3 of 28 ADA4896-2/ADA4897-1/ADA4897-2 Data Sheet Parameter Test Conditions/Comments Min Typ Max Unit POWER SUPPLY Operating Range 3 to 10 V Quiescent Current per Amplifier 2.8 3.0 3.2 mA DISABLE = −5 V 0.13 0.25 mA Power Supply Rejection Ratio (PSRR) Positive +V = 4 V to 6 V, −V = −5 V −96 −125 dB S S Negative +VS = 5 V, −VS = −4 V to −6 V −96 −121 dB DISABLE PIN (ADA4897-1/ADA4897-2) Enabled >+V − 0.5 V DISABLE Voltage S Disabled <+VS − 2 V Input Current Enabled DISABLE = +5 V −1.2 μA Disabled DISABLE = −5 V −40 μA Switching Speed Enabled 0.25 μs Disabled 12 μs +5 V SUPPLY T = 25°C, G = +1, R = 1 kΩ to midsupply, unless otherwise noted. A L Table 4. Parameter Test Conditions/Comments Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Bandwidth G = +1, V = 0.02 V p-p 230 MHz OUT G = +1, V = 2 V p-p 30 MHz OUT G = +2, V = 0.02 V p-p 90 MHz OUT Bandwidth for 0.1 dB Flatness G = +2, VOUT = 2 V p-p, RL = 100 Ω 7 MHz Slew Rate G = +2, VOUT = 3 V step 100 V/μs Settling Time to 0.1% G = +2, VOUT = 2 V step 45 ns Settling Time to 0.01% G = +2, V = 2 V step 95 ns OUT NOISE/HARMONIC PERFORMANCE Harmonic Distortion (SFDR) V = 2 V p-p OUT f = 100 kHz −115 dBc C f = 1 MHz −93 dBc C fC = 2 MHz −80 dBc fC = 5 MHz −61 dBc Input Voltage Noise f = 10 Hz 2.4 nV/√Hz f = 100 kHz 1 nV/√Hz Input Current Noise f = 10 Hz 11 pA/√Hz f = 100 kHz 2.8 pA/√Hz 0.1 Hz to 10 Hz Noise G = +101, RF = 1 kΩ, RG = 10 Ω 99 nV p-p DC PERFORMANCE Input Offset Voltage −500 −30 +500 μV Input Offset Voltage Drift 0.2 μV/°C Input Bias Current −17 −11 −4 μA Input Bias Current Drift 3 nA/°C Input Bias Offset Current −0.6 −0.02 +0.6 μA Open-Loop Gain V = 0.5 V to 4.5 V 97 110 dB OUT Rev. B | Page 4 of 28 Data Sheet ADA4896-2/ADA4897-1/ADA4897-2 Parameter Test Conditions/Comments Min Typ Max Unit INPUT CHARACTERISTICS Input Resistance Common-Mode 10 MΩ Differential 10 kΩ Input Capacitance Common-Mode 3 pF Differential 11 pF Input Common-Mode Voltage Range 0.1 to 4.1 V Common-Mode Rejection Ratio V = 1 V to 4 V −91 −118 dB CM (CMRR) OUTPUT CHARACTERISTICS Output Overdrive Recovery Time V = 0 V to 5 V, G = +2 96 ns IN Output Voltage Swing Positive R = 1 kΩ 4.85 4.98 V L RL = 100 Ω 4.8 4.88 V Negative RL = 1 kΩ 0.15 0.014 V RL = 100 Ω 0.2 0.08 V Output Current SFDR = −45 dBc 70 mA Short-Circuit Current Sinking/sourcing 125 mA Capacitive Load Drive 30% overshoot, G = +2 39 pF POWER SUPPLY Operating Range 3 to 10 V Quiescent Current per Amplifier 2.6 2.8 2.9 mA DISABLE = 0 V 0.05 0.18 mA Power Supply Rejection Ratio (PSRR) Positive +V = 4.5 V to 5.5 V, −V = 0 V −96 −123 dB S S Negative +V = 5 V, −V = −0.5 V to +0.5 V −96 −121 dB S S DISABLE PIN (ADA4897-1/ADA4897-2) DISABLE Voltage Enabled >+V − 0.5 V S Disabled <+V − 2 V S Input Current Enabled DISABLE = +5 V −1.2 μA Disabled DISABLE = 0 V −20 μA Switching Speed Enabled 0.25 μs Disabled 12 μs Rev. B | Page 5 of 28 ADA4896-2/ADA4897-1/ADA4897-2 Data Sheet +3 V SUPPLY TA = 25°C, G = +1, RL = 1 kΩ to midsupply, unless otherwise noted. Table 5. Parameter Test Conditions/Comments Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Bandwidth G = +1, VOUT = 0.02 V p-p 230 MHz G = −1, VOUT = 1 V p-p 45 MHz G = +2, VOUT = 0.02 V p-p 90 MHz Bandwidth for 0.1 dB Flatness G = +2, V = 2 V p-p, R = 100 Ω 7 MHz OUT L Slew Rate G = +2, V = 1 V step 85 V/μs OUT Settling Time to 0.1% G = +2, VOUT = 2 V step 45 ns Settling Time to 0.01% G = +2, VOUT = 2 V step 96 ns NOISE/HARMONIC PERFORMANCE Harmonic Distortion (SFDR) fC = 100 kHz, VOUT = 2 V p-p, G = +2 −105 dBc fC = 1 MHz, VOUT = 1 V p-p, G = −1 −84 dBc fC = 2 MHz, VOUT = 1 V p-p, G = −1 −77 dBc f = 5 MHz, V = 1 V p-p, G = −1 −60 dBc C OUT Input Voltage Noise f = 10 Hz 2.3 nV/√Hz f = 100 kHz 1 nV/√Hz Input Current Noise f = 10 Hz 11 pA/√Hz f = 100 kHz 2.8 pA/√Hz 0.1 Hz to 10 Hz Noise G = +101, R = 1 kΩ, R = 10 Ω 99 nV p-p F G DC PERFORMANCE Input Offset Voltage −500 −30 +500 μV Input Offset Voltage Drift 0.2 μV/°C Input Bias Current −17 −11 −4 μA Input Bias Current Drift 3 nA/°C Input Bias Offset Current −0.6 −0.02 +0.6 μA Open-Loop Gain VOUT = 0.5 V to 2.5 V 95 108 dB INPUT CHARACTERISTICS Input Resistance Common-Mode 10 MΩ Differential 10 kΩ Input Capacitance Common-Mode 3 pF Differential 11 pF Input Common-Mode Voltage Range 0.1 to 2.1 V Common-Mode Rejection Ratio VCM = 1.1 V to 1.9 V −90 −124 dB (CMRR) OUTPUT CHARACTERISTICS Output Overdrive Recovery Time VIN = 0 V to 3 V, G = +2 83 ns Output Voltage Swing Positive R = 1 kΩ 2.85 2.97 V L R = 100 Ω 2.8 2.92 V L Negative RL = 1 kΩ 0.15 0.01 V RL = 100 Ω 0.2 0.05 V Output Current SFDR = −45 dBc 60 mA Short-Circuit Current Sinking/sourcing 120 mA Capacitive Load Drive 30% overshoot, G = +2 39 pF POWER SUPPLY Operating Range 3 to 10 V Quiescent Current per Amplifier 2.5 2.7 2.9 mA DISABLE = 0 V 0.035 0.15 mA Rev. B | Page 6 of 28 Data Sheet ADA4896-2/ADA4897-1/ADA4897-2 Parameter Test Conditions/Comments Min Typ Max Unit Power Supply Rejection Ratio (PSRR) Positive +VS = 2.7 V to 3.7 V, −VS = 0 V −96 −121 dB Negative +VS = 3 V, −VS = −0.3 V to +0.7 V −96 −120 dB DISABLE PIN (ADA4897-1/ADA4897-2) DISABLE Voltage Enabled >+VS − 0.5 V Disabled <−VS + 2 V Input Current Enabled DISABLE = +3 V −1.2 μA Disabled DISABLE = 0 V −15 μA Switching Speed Enabled 0.25 μs Disabled 12 μs Rev. B | Page 7 of 28 ADA4896-2/ADA4897-1/ADA4897-2 Data Sheet ABSOLUTE MAXIMUM RATINGS The quiescent power dissipation is the voltage between the supply Table 6. pins (±VS) multiplied by the quiescent current (IS). Parameter Rating PD = Quiescent Power + (Total Drive Power − Load Power) Supply Voltage 11 V Power Dissipation See Figure 3 2   V V V S OUT OUT   Common-Mode Input Voltage −V − 0.7 V to +V + 0.7 V P  V I    S S D S S   2 R R  L  L Differential Input Voltage 0.7 V Storage Temperature Range −65°C to +125°C RMS output voltages should be considered. If RL is referenced to Operating Temperature Range −40°C to +125°C −V , as in single-supply operation, the total drive power is V × S S Lead Temperature (Soldering 10 sec) 300°C I . If the rms signal levels are indeterminate, consider the worst OUT Junction Temperature 150°C case, when V = V /4 for R to midsupply. OUT S L 2 V / 4 S Stresses above those listed under Absolute Maximum Ratings P  V I  D S S R may cause permanent damage to the device. This is a stress L rating only; functional operation of the device at these or any In single-supply operation with R referenced to −V , worst case L S other conditions above those indicated in the operational is VOUT = VS/2. section of this specification is not implied. Exposure to absolute Airflow increases heat dissipation, effectively reducing θJA. maximum rating conditions for extended periods may affect Also, more metal directly in contact with the package leads device reliability. and exposed paddle from metal traces, through holes, ground, THERMAL RESISTANCE and power planes reduces θ . JA θJA is specified for the worst-case conditions, that is, θJA is Figure 3 shows the maximum safe power dissipation in the specified for a device soldered in a circuit board for surface- package vs. the ambient temperature on a JEDEC standard mount packages. Table 7 lists the θJA for the ADA4896-2/ values are approximations. 4-layer board. θJA ADA4897-1/ADA4897-2. 3.5 T = 150°C J Table 7. Thermal Resistance 3.0 Package Type θ Unit JA 2.5 8-Lead Dual MSOP (ADA4896-2) 222 °C/W 8-Lead Dual LFCSP (ADA4896-2) 61 °C/W 2.0 8-LEAD LFCSP 8-Lead Single SOIC (ADA4897-1) 133 °C/W 6-Lead Single SOT-23 (ADA4897-1) 150 °C/W 6-LEAD SOT-23 1.5 10-LEAD MSOP 10-Lead Dual MSOP (ADA4897-2) 210 °C/W 8-LEAD SOIC 1.0 MAXIMUM POWER DISSIPATION 0.5 The maximum safe power dissipation for the ADA4896-2/ 8-LEAD MSOP ADA4897-1/ADA4897-2 is limited by the associated rise in 0 –45 –35 –25 –15 –5 5 15 25 35 45 55 65 75 85 95 105 115 125 junction temperature (TJ) on the die. At approximately 150C, AMBIENT TEMPERATURE (°C) which is the glass transition temperature, the properties of the Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board plastic change. Even temporarily exceeding this temperature limit may change the stresses that the package exerts on the ESD CAUTION die, permanently shifting the parametric performance of the ADA4896-2/ADA4897-1/ADA4897-2. Exceeding a junction temperature of 175C for an extended period of time can result in changes in silicon devices, potentially causing degradation or loss of functionality. The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the die due to the ADA4896-2/ADA4897-1/ADA4897-2 drive at the output. Rev. B | Page 8 of 28 MAXIMUM POWER DISSIPATION (W) 09447-053 Data Sheet ADA4896-2/ADA4897-1/ADA4897-2 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS ADA4896-2 OUT1 1 8+V S 7OUT2 –IN1 2 ADA4896-2 +IN1 3 6–IN2 OUT1 1 8 +V S –IN1 2 7 OUT2 5+IN2 –V 4 S +IN1 3 6 –IN2 NOTES –V 4 5 +IN2 1. THE EXPOSED PAD CAN BE S CONNECTED TO GND OR POWER PLANES, OR IT CAN TOP VIEW BE LEFT FLOATING. (Not to Scale) Figure 4. 8-Lead LFCSP Pin Configuration Figure 5. 8-Lead MSOP Pin Configuration Table 8. ADA4896-2 Pin Function Descriptions Pin No. Mnemonic Description 1 OUT1 Output 1. 2 −IN1 Inverting Input 1. 3 +IN1 Noninverting Input 1. 4 −V Negative Supply. S 5 +IN2 Noninverting Input 2. 6 −IN2 Inverting Input 2. 7 OUT2 Output 2. 8 +VS Positive Supply. EPAD Exposed Pad (LFCSP Only). The exposed pad can be connected to GND or power planes, or it can be left floating. NC 1 8 DISABLE OUT 1 6 +V S –IN 2 7 +V S +IN 3 6 OUT –V 2 5 DISABLE S –V 4 5 NC S ADA4897-1 +IN 3 4 –IN NC = NO CONNECT. DO NOT ADA4897-1 CONNECT TO THIS PIN. Figure 6. 8-Lead SOIC Pin Configuration Figure 7. 6-Lead SOT-23 Pin Configuration Table 9. ADA4897-1 Pin Function Descriptions Pin No. SOIC SOT-23 Mnemonic Description 1, 5 N/A NC No Connect. Do not connect to these pins. 2 4 −IN Inverting Input. 3 3 +IN Noninverting Input. 4 2 −VS Negative Supply. 6 1 OUT Output. 7 6 +VS Positive Supply. 8 5 DISABLE Disable. Rev. B | Page 9 of 28 09447-016 09447-022 09447-002 09447-017 ADA4896-2/ADA4897-1/ADA4897-2 Data Sheet OUT1 1 10 +V S –IN1 2 9 OUT2 +IN1 3 8 –IN2 –V 4 7 +IN2 S DISABLE1 5 ADA4897-2 6 DISABLE2 Figure 8. 10-Lead MSOP Pin Configuration Table 10. ADA4897-2 Pin Function Descriptions Pin No. Mnemonic Description 1 OUT1 Output 1. 2 −IN1 Inverting Input 1. 3 +IN1 Noninverting Input 1. 4 −V Negative Supply. S 5 DISABLE1 Disable 1. 6 DISABLE2 Disable 2. 7 +IN2 Noninverting Input 2. 8 −IN2 Inverting Input 2. 9 OUT2 Output 2. 10 +V Positive Supply. S Rev. B | Page 10 of 28 09447-069 Data Sheet ADA4896-2/ADA4897-1/ADA4897-2 TYPICAL PERFORMANCE CHARACTERISTICS RL = 1 kΩ, unless otherwise noted. When G = +1, RF = 0 Ω; otherwise, RF = 249 Ω. 2 2 V = +5V V = ±5V S S V = 20mV p-p G = +1 OUT G = +1 1 1 20mV p-p 0 0 G = –1 OR G = +2 –1 100mV p-p –1 G = +10 –2 400mV p-p –2 –3 2V p-p –3 –4 –4 –5 –5 –6 0.1 1 10 100 300 0.1 1 10 100 500 FREQUENCY (MHz) FREQUENCY (MHz) Figure 9. Small Signal Frequency Response vs. Gain Figure 12. Frequency Response for Various Output Voltages 2 0.8 G = +1 V = +3V V = +5V V = +5V S S S V = 20mV p-p V = 2V p-p OUT 0.7 OUT G = +2 R = R = 249Ω F G 1 R = 1kΩ L 0.6 R = R = 100Ω F G 0.5 0 V = ±5V S 0.4 R = R = 49.9Ω F G –1 0.3 0.2 –2 0.1 –3 0 –0.1 –4 –0.2 –5 –0.3 0.1 1 10 100 500 0.1 1 10 50 FREQUENCY (MHz) FREQUENCY (MHz) Figure 10. Small Signal Frequency Response vs. Supply Voltage Figure 13. 0.1 dB Bandwidth at Selected R Values F 2 2 V = +5V S V = +5V –40°C S G = –1 G = +1 V = 2V p-p OUT V = 20mV p-p 1 1 OUT G = +1 0 0 –1 –1 +125°C G = +10 –2 –2 –3 +25°C –3 –4 –4 –5 –5 –6 100k 1M 10M 100M 1G 0.1 1 10 100 FREQUENCY (Hz) FREQUENCY (MHz) Figure 11. Small Signal Frequency Response vs. Temperature Figure 14. Large Signal Frequency Response vs. Gain Rev. B | Page 11 of 28 NORMALIZED CLOSED-LOOP GAIN (dB) NORMALIZED CLOSED-LOOP GAIN (dB) NORMALIZED CLOSED-LOOP GAIN (dB) 09447-010 09447-038 09447-005 NORMALIZED CLOSED-LOOP GAIN (dB) NORMALIZED CLOSED-LOOP GAIN (dB) NORMALIZED CLOSED-LOOP GAIN (dB) 09447-061 09447-006 09447-008 ADA4896-2/ADA4897-1/ADA4897-2 Data Sheet 4 –30 V = +5V V = +5V S S V = 2V p-p G = +2 C = 39pF OUT L G = +10 R = 100Ω –40 L 3 V = 20mV p-p OUT R = 100Ω, SECOND L –50 2 –60 1 –70 0 C = 20pF L R = 100Ω, THIRD –80 L –1 –90 R = 1kΩ, THIRD L C = 0pF L –2 –100 R = 1kΩ, SECOND L –110 –3 0.1 1 10 100 0.1 1 5 FREQUENCY (MHz) FREQUENCY (MHz) Figure 15. Small Signal Frequency Response vs. Capacitive Load Figure 18. Harmonic Distortion vs. Frequency, G = +10 –50 –50 V = +5V V = ±5V S S G = +1 V = 2V p-p OUT R = 1kΩ –60 G = +1 –60 L R = 100Ω, SECOND L –70 –70 –80 –80 R = 100Ω, THIRD L 8V p-p, THIRD –90 –90 8V p-p, SECOND 2V p-p, SECOND R = 1kΩ, THIRD 2V p-p, THIRD L –100 –100 4V p-p, SECOND 4V p-p, THIRD –110 –110 R = 1kΩ, SECOND L –120 –120 0.1 1 5 0.1 1 5 FREQUENCY (MHz) FREQUENCY (MHz) Figure 16. Harmonic Distortion vs. Frequency, G = +1 Figure 19. Harmonic Distortion vs. Frequency for Various Output Voltages –40 –50 V = +5V G = +2 S V = +5V, S V = 2V p-p R = 1kΩ OUT L SECOND G = +5 –60 –50 R = 100Ω, SECOND L –70 V = +5V, S –60 THIRD –80 –70 V = +3V, S –90 SECOND V = ±5V, S SECOND –80 –100 R = 100Ω, THIRD L –90 V = ±5V, –110 S R = 1kΩ, THIRD THIRD L –100 –120 V = +3V, S R = 1kΩ, SECOND L THIRD –110 –130 0.1 1 5 0.1 1 5 FREQUENCY (MHz) FREQUENCY (MHz) Figure 20. Harmonic Distortion vs. Frequency for Various Supplies Figure 17. Harmonic Distortion vs. Frequency, G = +5 Rev. B | Page 12 of 28 NORMALIZED CLOSED-LOOP GAIN (dB) DISTORTION (dBc) DISTORTION (dBc) 09447-021 09447-041 09447-007 DISTORTION (dBc) DISTORTION (dBc) DISTORTION (dBc) 09447-026 09447-070 09447-045 Data Sheet ADA4896-2/ADA4897-1/ADA4897-2 18 90 –80 V = ±5V S 100 UNITS 80 16 –100 σ = 309.2µV/°C 70 14 –120 60 PHASE 12 GAIN 50 –140 10 40 –160 30 8 –180 20 6 10 –200 4 0 –220 2 –10 –20 –240 0 10k 100k 1M 10M 100M 1G –600 –400 –200 0 200 400 600 800 1000 FREQUENCY (Hz) OFFSET VOLTAGE DRIFT DISTRIBUTION (nV/°C) Figure 21. Open-Loop Gain and Phase vs. Frequency Figure 24. Input Offset Voltage Drift Distribution 8 G = +1 V = +3V V = ±5V S S V = 20mV p-p OUT V = +5V S TIME = 100ns/DIV 7 10 V = ±5V 6 S 5 0 4 3 2 –10 1 0 1 10 100 1k 10k 100k 1M 5M FREQUENCY (Hz) Figure 22. Voltage Noise vs. Frequency Figure 25. Small Signal Transient Response for Various Supplies, G = +1 100 V = +3V G = +2 S V = ±5V S V = 20mV p-p OUT V = +5V S TIME = 100ns/DIV 10 V = ±5V S 0 10 –10 1 1 10 100 1k 10k 100k 1M 5M FREQUENCY (Hz) Figure 23. Current Noise vs. Frequency Figure 26. Small Signal Transient Response for Various Supplies, G = +2 Rev. B | Page 13 of 28 OPEN-LOOP GAIN (dB) CURRENT NOISE (pA/√Hz) VOLTAGE NOISE (nV/√Hz) 09447-027 09447-060 OPEN-LOOP PHASE (Degrees) 09447-044 NUMBER OF PARTS OUTPUT VOLTAGE (mV) OUTPUT VOLTAGE (mV) 09447-040 09447-050 09447-066 ADA4896-2/ADA4897-1/ADA4897-2 Data Sheet 3 V = ±5V S C = 39pF L 2× V V = +5V S IN G = +2 G = +2 C = 20pF L TIME = 100ns/DIV TIME = 100ns/DIV C = 0pF L 2 V OUT 10 1 0 0 –1 –10 –2 –3 Figure 27. Small Signal Transient Response for Various Capacitive Loads Figure 30. Output Overdrive Recovery Time 1.5 250 V = ±5V S V = +5V S V = 2V p-p G = +2 OUT G = +2 TIME = 100ns/DIV 1.0 200 G = +1 0.5 150 0 100 –0.5 50 –1.0 –1.5 0 0 100 200 300 400 500 600 700 800 900 OVERLOAD DURATION (ns) Figure 28. Large Signal Transient Response, G = +1 and G = +2 Figure 31. Average Output Overload Recovery Time vs. Overload Duration 4 105.0 V = 3V p-p V = +5V OUT S G = +1 V = +5V S 102.5 V TIME = 100ns/DIV 3 IN G = +2 RISING EDGE 100.0 2 97.5 1 V OUT 95.0 FALLING EDGE 0 92.5 90.0 –1 87.5 –2 85.0 –3 82.5 –4 80.0 –40 –25 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) Figure 29. Input Overdrive Recovery Time Figure 32. Slew Rate vs. Temperature Rev. B | Page 14 of 28 INPUT AND OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (mV) 09447-039 09447-049 09447-009 AVERAGE OUTPUT OVERLOAD RECOVERY TIME (ns) SLEW RATE (V/µs) INPUT AND OUTPUT VOLTAGE (V) 09447-051 09447-052 09447-055 Data Sheet ADA4896-2/ADA4897-1/ADA4897-2 0.3 100000 V = +5V V = +5V S S G = +2 G = +1 V = 2V STEP P = –30dBm OUT IN 10000 R = 1kΩ 0.2 L PART DISABLED TIME = 10ns/DIV 1000 0.1 100 0 10 PART ENABLED –0.1 1 –0.2 0.1 0.01 –0.3 0.1 1 10 100 500 FREQUENCY (MHz) Figure 33. Settling Time to 0.1% Figure 36. Output Impedance vs. Frequency –20 –26.0 V = +5V S –30 ΔV = 2V p-p CM –40 V = ±5V S –50 –28.5 V = +5V S –60 –70 V = +3V S –80 –90 –31.0 –100 –110 –120 –33.5 –130 1k 10k 100k 1M 10M 100M –40 –25 –10 5 20 35 50 65 80 95 110 125 FREQUENCY (Hz) TEMPERATURE (°C) Figure 34. CMRR vs. Frequency Figure 37. Input Offset Voltage vs. Temperature for Various Supplies 0 –10.50 V = +5V S V = ±5V –10 S ΔV = 2V p-p S G = +1 –20 –30 –10.75 –40 V = +5V S –50 –PSRR –60 –11.00 –70 +PSRR –80 V = +3V S –90 –11.25 –100 –110 –120 –130 –11.50 1k 10k 100k 1M 10M 100M –40 –25 –10 5 20 35 50 65 80 95 110 125 FREQUENCY (Hz) TEMPERATURE (°C) Figure 35. PSRR vs. Frequency Figure 38. Input Bias Current vs. Temperature for Various Supplies Rev. B | Page 15 of 28 CMRR (dB) PSRR (dB) SETTLING TIME (%) 09447-028 09447-030 09447-029 INPUT BIAS CURRENT (µA) INPUT OFFSET VOLTAGE (µV) OUTPUT IMPEDANCE (Ω) 09447-013 09447-042 09447-046 ADA4896-2/ADA4897-1/ADA4897-2 Data Sheet 3.2 5.5 3.875 TIME = 2µs/DIV DISABLE PIN V = +5V 5.0 3.750 S V = ±5V S G = +1 3.1 V = 1V 4.5 3.625 IN 4.0 +25°C 3.500 3.0 3.5 3.375 –40°C V = +5V S 3.0 3.250 2.9 2.5 3.125 2.8 2.0 3.000 1.5 2.875 2.7 V = +3V S 1.0 2.750 +125°C 0.5 2.625 2.6 0 2.500 2.5 –0.5 2.375 –40 –25 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) Figure 39. Supply Current vs. Temperature for Various Supplies Figure 42. Turn-Off Time vs. Temperature (ADA4897-1 and ADA4897-2) –40 –30 V = +5V V = +5V S S G = +2 G = +2 –40 –50 V = 2V p-p R = 100Ω OUT L V = 2V p-p OUT –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 –100 –110 –110 –120 –120 –130 –130 –140 0.01 0.1 1 10 100 0.01 0.1 1 10 100 FREQUENCY (MHz) FREQUENCY (MHz) Figure 40. Crosstalk, OUT1 to OUT2 (ADA4896-2 and ADA4897-2) Figure 43. Forward Isolation vs. Frequency 5.5 3.875 DISABLE PIN 5.0 3.750 4.5 3.625 4.0 3.500 3.5 3.375 +125°C +25°C 3.0 3.250 –40°C 2.5 3.125 3.000 2.0 2.875 1.5 TIME = 200ns/DIV 2.750 1.0 V = +5V S G = +1 2.625 0.5 V = 1V IN 0 2.500 –0.5 2.375 Figure 41. Turn-On Time vs. Temperature (ADA4897-1 and ADA4897-2) Rev. B | Page 16 of 28 DISABLE PIN (V) SUPPLY CURRENT (mA) CROSSTALK (dB) OUTPUT VOLTAGE (V) 09447-014 09447-043 09447-054 DISABLE PIN (V) ISOLATION (dB) 09447-015 OUTPUT VOLTAGE (V) 09447-056 Data Sheet ADA4896-2/ADA4897-1/ADA4897-2 THEORY OF OPERATION The ESD clamps begin to conduct for input voltages that are AMPLIFIER DESCRIPTION more than 0.7 V above the positive supply and input voltages The ADA4896-2/ADA4897-1/ADA4897-2 are 1 nV/√Hz input more than 0.7 V below the negative supply. If an overvoltage noise amplifiers that consume 3 mA from supplies ranging from condition is expected, it is recommended that the input current 3 V to 10 V. Fabricated on the Analog Devices SiGe bipolar process, be limited to less than 10 mA. the ADA4896-2/ADA4897-1/ADA4897-2 have a bandwidth in excess of 200 MHz. The amplifiers are unity-gain stable, and the DISABLE OPERATION input structure results in an extremely low input 1/f noise for a Figure 45 shows the ADA4897-1/ADA4897-2 power-down high speed amplifier. DISABLE circuitry. If the pin is left unconnected, the base of The rail-to-rail output stage is designed to drive the heavy feed- the input PNP transistor is pulled high through the internal back load required to achieve an overall low output referred noise. pull-up resistor to the positive supply and the part is turned To meet more demanding system requirements, the large signal DISABLE on. Pulling the pin to ≥2 V below the positive supply bandwidth of the ADA4896-2/ADA4897-1/ADA4897-2 was turns the part off, reducing the supply current to approximately increased beyond the typical fundamental limits of other low noise, 18 μA for a 5 V voltage supply. unity-gain stable amplifiers. The maximum offset voltage of 500 μV +V S and drift of 0.2 μV/°C make the ADA4896-2/ADA4897-1/ I BIAS ADA4897-2 excellent amplifier choices even when the low noise ESD performance is not needed because there is minimal power DISABLE penalty in achieving the low input noise or the high bandwidth. ESD TO INPUT PROTECTION AMPLIFIER BIAS The ADA4896-2/ADA4897-1/ADA4897-2 are fully protected from ESD events, withstanding human body model ESD events of 2.5 kV and charged-device model events of 1 kV with no mea- sured performance degradation. The precision input is protected –V S with an ESD network between the power supplies and diode DISABLE Figure 45. Circuit clamps across the input device pair, as shown in Figure 44. +V S The DISABLE pin is protected by ESD clamps, as shown in Figure 45. Voltages beyond the power supplies cause these BIAS DISABLE diodes to conduct. For protection of the pin, the ESD ESD voltage to this pin should not exceed 0.7 V above the positive +IN –IN supply or 0.7 V below the negative supply. If an overvoltage ESD ESD condition is expected, it is recommended that the input current be limited with a series resistor to less than 10 mA. –V S When the amplifier is disabled, its output goes to a high impedance state. The output impedance decreases as frequency TO THE REST OF THE AMPLIFIER increases; this effect can be observed in Figure 36. In disable Figure 44. Input Stage and Protection Diodes mode, a forward isolation of 50 dB can be achieved at 10 MHz. For differential voltages above approximately 0.7 V, the diode Figure 43 shows the forward isolation vs. frequency data. clamps begin to conduct. Too much current can cause damage due to excessive heating. If large differential voltages must be sustained across the input terminals, it is recommended that the current through the input clamps be limited to less than 10 mA. Series input resistors that are sized appropriately for the expected differential overvoltage provide the needed protection. Rev. B | Page 17 of 28 09447-068 09447-037 ADA4896-2/ADA4897-1/ADA4897-2 Data Sheet The output error due to the input currents can be estimated as DC ERRORS Figure 46 shows a typical connection diagram and the major ⎛ ⎞ ⎛ ⎞ R R F F ⎜ ⎟ ⎜ ⎟ V = (R || R )× 1+ × I − R × 1+ × I (5) OUT F G B− S B+ dc error sources. ERROR ⎜ ⎟ ⎜ ⎟ R R G G ⎝ ⎠ ⎝ ⎠ R F BIAS CURRENT CANCELLATION – V + + V – IN OS R G To cancel the output voltage error due to unmatched bias + V – OUT I – B and R can be used (see Figure 47). currents at the inputs, RBP BN – V + IP R R R G F S I + B Figure 46. Typical Connection Diagram and DC Error Sources R The ideal transfer function (all error sources set to 0 and BN infinite dc gain) can be written as R R S BP ⎛ R ⎞ ⎛ R ⎞ F F ⎜ ⎟ ⎜ ⎟ V = 1+ × V − × V (1) OUT IP IN Figure 47. Using RBP and RBN to Cancel Bias Current Error ⎜ ⎟ ⎜ ⎟ R R ⎝ G⎠ ⎝ G⎠ To compensate for the unmatched bias currents at the two This equation reduces to the familiar forms for noninverting inputs, set R and R as shown in Table 11. BP BN and inverting op amp gain expressions, as follows: Table 11. Setting RBN and RBP to Cancel Bias Current Errors For noninverting gain (V = 0 V) IN Value of RF||RG Value of RBP (Ω) Value of RBN (Ω) ⎛ R ⎞ F Greater Than R R ||R − R 0 S F G S ⎜ ⎟ (2) V = 1+ × V OUT IP ⎜ ⎟ R Less Than R 0 R − R ||R S S F G ⎝ G⎠ For inverting gain (V = 0 V) IP Table 12 shows sample values for RBP and RBN when RF||RG > RS and when R ||R < R . F G S ⎛− R ⎞ F ⎜ ⎟ V = × V (3) OUT IN ⎜ ⎟ R G Table 12. Examples of R and R Settings ⎝ ⎠ BN BP Gain R (Ω) R (Ω) R (Ω) R (Ω) R (Ω) F G S BP BN The total output voltage error is the sum of errors due to the +2 249 249 50 74.5 0 amplifier offset voltage and input currents. The output error +10 249 27.4 50 0 25.3 due to the offset voltage can be estimated as V = OUT ERROR (4) ⎛ ⎞ V V −V V R ⎛ ⎞ CM P PNOM OUT F ⎜ ⎟ V + + + × 1+ ⎜ ⎟ OFFSET NOM ⎜ ⎟ CMRR PSRR A R ⎝ ⎠ G ⎝ ⎠ where: V is the offset voltage at the specified supply voltage, OFFSET NOM which is measured with the input and output at midsupply. V is the common-mode voltage. CM V is the power supply voltage. P V is the specified power supply voltage. PNOM CMRR is the common-mode rejection ratio. PSRR is the power supply rejection ratio. A is the dc open-loop gain. Rev. B | Page 18 of 28 09447-031 09447-048 Data Sheet ADA4896-2/ADA4897-1/ADA4897-2 500 NOISE CONSIDERATIONS Figure 48 illustrates the primary noise contributors for the typical gain configurations. The total rms output noise is the root-mean-square of all the contributions. 50 R vn _ R = 4kT × R F F F AMPLIFIER AND RESISTOR NOISE ven R vn _ R = G 4kT × R G G + vout_en – ien 5 SOURCE RESISTANCE NOISE R vn _ R = 4kT × R S S S iep TOTAL AMPLIFIER NOISE Figure 48. Noise Sources in Typical Connection 0.5 50 500 5k 50k The output noise spectral density can be calculated by SOURCE RESISTANCE (Ω) Figure 49. RTI Noise vs. Source Resistance vout_en= 2 2 CAPACITANCE DRIVE ⎛ R ⎞ 2 2 ⎛R ⎞ 2 2 2 F F ⎜ ⎟ ⎜ ⎟ 4kTR + 1+[] 4kTRs+iep R +ven + 4kTR +ien R F S G F ⎜ ⎟ ⎜ ⎟ Capacitance at the output of an amplifier creates a delay within the R R ⎝ G⎠ ⎝ G⎠ feedback path that, if within the bandwidth of the loop, can create (6) excessive ringing and oscillation. The ADA4896-2/ADA4897-1/ where: ADA4897-2 show the most peaking at a gain of +2 (see Figure 9). k is Boltzmann’s constant. Placing a small snub resistor (RSNUB) in series with the amplifier T is the absolute temperature (degrees Kelvin). output and the capacitive load mitigates the problem. Figure 50 iep and ien represent the amplifier input current noise spectral shows the effect of using a snub resistor (RSNUB) on reducing the density (pA/√Hz). peaking for the worst-case frequency response (gain of +2). ven is the amplifier input voltage noise spectral density (nV/√Hz). Using R = 100 Ω eliminates the peaking entirely, with the SNUB R is the source resistance, as shown in Figure 48. S trade-off that the closed-loop gain is reduced by 0.8 dB due to R and R are the feedback network resistances, as shown in F G attenuation at the output. RSNUB can be adjusted from 0 Ω to Figure 48. 100 Ω to maintain an acceptable level of peaking and closed- Source resistance noise, amplifier voltage noise (ven), and the loop gain (see Figure 50). voltage noise from the amplifier current noise (iep × R ) are all S 3 V = +5V S subject to the noise gain term (1 + RF/RG). Note that with a V = 200mV p-p OUT 2 G = +2 1 nV/√Hz input voltage noise and 2.8 pA/√Hz input current R = 0Ω SNUB noise, the noise contributions of the amplifier are relatively 1 R = 50Ω SNUB small for source resistances from approximately 50 Ω to 700 Ω. R = 100Ω SNUB 0 Figure 49 shows the total RTI noise due to the amplifier vs. the –1 source resistance. In addition, the value of the feedback resistors R 2 249Ω used affects the noise. It is recommended that the value of the –2 R 1 feedback resistors be maintained between 250 Ω and 1 kΩ to 249Ω R –3 SNUB V OUT keep the total noise low. ADA4896-2 V C R IN L L –4 39pF 1kΩ –5 0.1 1 10 100 FREQUENCY (MHz) Figure 50. Using a Snub Resistor to Reduce Peaking Due to Output Capacitive Load Rev. B | Page 19 of 28 09447-034 NORMALIZED CLOSED-LOOP GAIN (dB) NOISE (nV/√Hz) 09447-057 09447-058 ADA4896-2/ADA4897-1/ADA4897-2 Data Sheet APPLICATIONS INFORMATION 2 TYPICAL PERFORMANCE VALUES V = +5V S V = 200mV p-p OUT 1 R = 249Ω To reduce design time and eliminate uncertainty, Table 13 F G = +5 R = 1kΩ L provides a reference for typical gains, component values, and G = +2 0 performance parameters. The supply voltage used is 5 V. The band- –1 width is obtained with a small signal output of 200 mV p-p, and G = +10 G = +1 the slew rate is obtained with a 2 V output step. –2 G = +20 Note that as the gain increases, the small signal bandwidth –3 decreases, as is expected from the gain bandwidth product –4 relationship. In addition, the phase margin improves with higher gains, and the amplifier becomes more stable. As a –5 result, the peaking in the frequency response is reduced –6 (see Figure 51). 0.1 1 10 100 500 FREQUENCY (MHz) Figure 51. Small Signal Frequency Response at Various Gains Table 13. Recommended Values and Typical Performance Total Output Noise Including Gain R (Ω) R (Ω) −3 dB BW (MHz) Slew Rate, t /t (V/μs) Peaking (dB) Resistors (nV/√Hz) F G R F +1 0 N/A 92 78/158 0.8 1.0 +2 249 249 54 101/140 1.2 3.6 +5 249 61.9 30 119/137 0 6.8 +10 249 27.4 17 87/88 0 12.0 +20 249 13.0 9 37/37 0 21.1 Rev. B | Page 20 of 28 NORMALIZED CLOSED-LOOP GAIN (dB) 09447-020 Data Sheet ADA4896-2/ADA4897-1/ADA4897-2 LOW NOISE, GAIN SELECTABLE AMPLIFIER USING S3B IS OPTIONAL R F2 S3B D3 ADG633 225Ω R F1 +5V 75Ω 8 +5V 6 R G1 8 75Ω 2 7 ADA4896-2 S1B S2B V 02 V1 R L D1 D2 1 5 ADA4896-2 V 4 01 V2 3 S1A S2A R V IN BALANCE 150Ω –5V 4 ADG633 –5V Figure 52. Using the ADA4896-2 and the ADG633 to Construct a Low Noise, Gain Selectable Amplifier to Drive a Low Resistive Load A gain selectable amplifier makes processing a wide range of to cancel out the varying offset. Placing a resistor equal to the input signals possible. A traditional gain selectable amplifier difference between RF2 and RF1 in series with Switch S2A results uses switches in the feedback loops connecting to the inverting in a more constant offset voltage. input. The switch resistances degrade the noise performance of The following derivation shows that sampling at V1 yields the the amplifier, as well as adding significant capacitance on the desired signal gain without gain error. R denotes the switch S inverting input node. The noise and capacitance issues can be resistance. V2 can be derived using the same method. especially bothersome when working with low noise amplifiers. ⎛ R + R ⎞ Also, the switch resistances contribute to nonlinear gain error, F1 S1 ⎜ ⎟ V = V × 1+ (7) 01 IN ⎜ ⎟ which is undesirable. R G1 ⎝ ⎠ Figure 52 presents an innovative switching technique used in ⎛ R + R ⎞ F1 G1 ⎜ the gain selectable amplifier such that the 1 nV/Hz noise per- ⎟ (8) V1= V × 01 ⎜ ⎟ R + R + R F1 G1 S1 ⎝ ⎠ formance of the ADA4896-2 is preserved while the nonlinear gain error is much reduced. With this technique, the user can Substituting Equation 1 into Equation 2, the following also choose switches with minimal capacitance to optimize the derivation is obtained. bandwidth of the circuit. ⎛ ⎞ R F1 ⎜ ⎟ V1= V × 1+ In the circuit shown in Figure 52, the switches are implemented (9) IN ⎜ ⎟ R G1 ⎝ ⎠ with the ADG633 and are configured such that either S1A and S2A are on, or S1B and S2B are on. In this example, when the Note that if V yields the desired signal gain without gain 01 S1A and S2A switches are on, the first stage amplifier gain is +4. error, the buffered output V will also be free from gain 02 When the S1B and S2B switches are on, the first stage amplifier error. Figure 53 shows the normalized frequency response of gain is +2. The first set of switches of the ADG633 is placed on the circuit at V02. the output side of the feedback loop, and the second set of switches 6 V = ±5V S is used to sample at a point (V1 or V2) where switch resistances V = 100mV p-p 3 IN R = 1kΩ L and nonlinear resistances do not matter. In this way, the gain 0 error can be reduced while preserving the noise performance –3 G = +2 G = +4 of the ADA4896-2. –6 –9 Note that the input bias current of the output buffer can cause –12 problems with the impedance of the S2A and S2B sampling –15 switches. Both sampling switches are not only nonlinear with –18 voltage but with temperature as well. If this is an issue, place the –21 unused switch of the ADG633 (S3B) in the feedback path of the –24 output buffer to balance the bias currents (see Figure 52). –27 In addition, the bias current of the input amplifier causes –30 0.1 1 10 100 500 an offset at the output that varies based on the gain setting. FREQUENCY (MHz) Because the input amplifier and the output buffer are mono- Figure 53. Frequency Response of V02/VIN lithic, the relative matching of their bias currents can be used Rev. B | Page 21 of 28 NORMALIZED CLOSED-LOOP GAIN (dB) 09447-100 09447-064 ADA4896-2/ADA4897-1/ADA4897-2 Data Sheet MEDICAL ULTRASOUND APPLICATIONS BEAMFORMER Tx BEAMFORMER CENTRAL CONTROL AD9279 HV Rx BEAMFORMER MUX/ T/R LNA VGA ADC (B AND F MODES) DEMUX SWITCHES AAF TRANSDUCER ARRAY CW (ANALOG) SPECTRAL IMAGE AND COLOR BEAMFORMER DOPPLER MOTION DOPPLER PROCESSING PROCESSING PROCESSING ADA4896-2/ MODE (B MODE) (F MODE) ADA4897-1/ ADA4897-2 AUDIO DISPLAY OUTPUT Figure 54. Simplified Ultrasound System Block Diagram Overview of the Ultrasound System The ultrasound system consists of two main operations: the time gain control (TGC) operation and the continuous wave Medical ultrasound systems are among the most sophisticated (CW) Doppler operation. The AD9279 integrates the essential signal processing systems in widespread use today. By transmit- components of these two operations into a single IC. It contains ting acoustic energy into the body and receiving and processing eight channels of a variable gain amplifier (VGA) with a low the returning reflections, ultrasound systems can generate images noise preamplifier (LNA), an antialiasing filter (AAF), an of internal organs and structures, map blood flow and tissue analog-to-digital converter (ADC), and an I/Q demodulator motion, and provide highly accurate blood velocity information. with programmable phase rotation. For detailed information Figure 54 shows a simplified block diagram of an ultrasound about how to use the AD9279 in an ultrasound system, see the system. AD9279 data sheet. Rev. B | Page 22 of 28 09447-033 Data Sheet ADA4896-2/ADA4897-1/ADA4897-2 ADA4896-2/ADA4897-1/ADA4897-2 in the Ultrasound System R FILT C FILT R A CWI+ Φ AD7982 50Ω 1.5V 2.5V ADA4896-2/ ADA4896-2/ LNA CHANNEL A ADA4897-1/ ADA4897-1/ 18-BIT ADC I ADA4897-2 ADA4897-2 1.5V 2.5V CWI– Φ 50Ω 4nF R A C FILT R FILT R FILT C FILT R A CWQ+ AD7982 50Ω Φ 1.5V ADA4896-2/ 2.5V ADA4896-2/ ADA4897-1/ ADA4897-1/ 18-BIT ADC Q ADA4897-2 ADA4897-2 1.5V 2.5V CHANNEL H LNA CWQ– 50Ω 4nF R A C FILT Φ R FILT 4 LO GENERATION AD9279 Figure 55. Using the ADA4896-2/ADA4897-1/ADA4897-2 as Filters, I-to-V Converters, Current Summers, and ADC Drivers After the I/Q Outputs of the AD9279 The ADA4896-2/ADA4897-1/ADA4897-2 are used in the CW The output-referred noise of the CW signal path depends on Doppler path in the ultrasound application after the I/Q demod- the LNA gain, the selection of the first stage summing amplifier, ulators of the AD9279. Doppler signals can be typically between and the value of R . To determine the output-referred noise, it FILT 100 Hz to 100 kHz. The low noise floor and high dynamic range is important to know the active low-pass filter (LPF) values RA, of the ADA4896-2/ADA4897-1/ADA4897-2 make them excellent RFILT, and CFILT, as shown as Figure 55. Typical filter values for choices for processing weak Doppler signals. all eight channels of a single AD9279 are 100 Ω for RA, 500 Ω for RFILT, and 2.0 nF for CFILT; these values implement a 100 kHz, The rail-to-rail output and the high output current drive of single-pole LPF. the ADA4896-2/ADA4897-1/ADA4897-2 make them suitable candidates for the I-to-V converter, current summer, and ADC The gain of the I-to-V converter can be increased by increasing driver. the filter resistor, R . To keep the corner frequency unchanged, FILT decrease the filter capacitor, C , by the same factor. The factor FILT Figure 55 shows an interconnection block diagram of all limiting the magnitude of the gain is the output swing and drive eight channels of the AD9279. Two stages of the ADA4896-2 capability of the op amp selected for the I-to-V converter, in this amplifiers are used. The first stage performs an I-to-V conver- example, the ADA4896-2/ADA4897-1/ADA4897-2. Because sion and filters the high frequency content that results from any amplifier has limited drive capability, a finite number of the demodulation process. The second stage of the ADA4896-2 channels can be summed. amplifiers is used to sum the output currents of multiple AD9279 devices, to provide gain, and to drive the AD7982 device, an 18-bit SAR ADC. Rev. B | Page 23 of 28 RESET 4LO+ 4LO– 09447-032 ADA4896-2/ADA4897-1/ADA4897-2 Data Sheet Paralleling different values and sizes of capacitors helps to ensure LAYOUT CONSIDERATIONS that the power supply pins are provided with a low ac impedance To ensure optimal performance, careful and deliberate attention across a wide band of frequencies. This is important for minimiz- must be paid to the board layout, signal routing, power supply ing the coupling of noise into the amplifier—especially when the bypassing, and grounding. amplifier PSRR begins to roll off—because the bypass capacitors Ground Plane can help lessen the degradation in PSRR performance. It is important to avoid ground in the areas under and around the The smallest value capacitor should be placed on the same side input and output of the ADA4896-2/ADA4897-1/ADA4897-2. of the board as the amplifier and as close as possible to the amp- Stray capacitance created between the ground plane and the lifier power supply pins. The ground end of the capacitor should input and output pads of a device is detrimental to high speed be connected directly to the ground plane. amplifier performance. Stray capacitance at the inverting input, It is recommended that a 0.1 μF ceramic capacitor with a 0508 along with the amplifier input capacitance, lowers the phase case size be used. The 0508 case size offers low series inductance margin and can cause instability. Stray capacitance at the output and excellent high frequency performance. A 10 μF electrolytic creates a pole in the feedback loop, which can reduce phase margin capacitor should be placed in parallel with the 0.1 μF capacitor. and can cause the circuit to become unstable. Depending on the circuit parameters, some enhancement to Power Supply Bypassing performance can be realized by adding additional capacitors. Power supply bypassing is a critical aspect in the performance Each circuit is different and should be analyzed individually for of the ADA4896-2/ADA4897-1/ADA4897-2. A parallel connec- optimal performance. tion of capacitors from each power supply pin to ground works best. Smaller value capacitor electrolytics offer better high frequency response, whereas larger value capacitor electrolytics offer better low frequency performance. Rev. B | Page 24 of 28 Data Sheet ADA4896-2/ADA4897-1/ADA4897-2 OUTLINE DIMENSIONS 3.20 3.00 2.80 8 5 5.15 3.20 4.90 3.00 4.65 1 2.80 4 PIN 1 IDENTIFIER 0.65 BSC 0.95 15° MAX 0.85 1.10 MAX 0.75 0.80 0.15 0.23 6° 0.55 0.40 0.05 0.09 0° 0.40 0.25 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 56. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters 2.44 2.34 3.10 2.24 3.00 SQ 0.50 BSC 2.90 5 8 PIN 1 INDEX EXPOSED 1.70 PAD AREA 1.60 1.50 0.50 0.40 0.30 4 1 BOTTOM VIEW TOP VIEW FOR PROPER CONNECTION OF 0.80 THE EXPOSED PAD, REFER TO 0.05 MAX 0.75 THE PIN CONFIGURATION AND 0.02 NOM 0.70 FUNCTION DESCRIPTIONS COPLANARITY SECTION OF THIS DATA SHEET. 0.08 SEATING 0.30 PLANE 0.203 REF 0.25 0.20 COMPLIANT TOJEDEC STANDARDS MO-229-WEED Figure 57. 8-Lead Lead Frame Chip Scale Package [LFCSP_WD] 3 mm × 3 mm Body, Very Very Thin, Dual Lead (CP-8-11) Dimensions shown in millimeters Rev. B | Page 25 of 28 PIN 1 INDICATOR (R 0.15) 10-07-2009-B 01-24-2011-B ADA4896-2/ADA4897-1/ADA4897-2 Data Sheet 5.00 (0.1968) 4.80 (0.1890) 85 6.20 (0.2441) 4.00 (0.1574) 1 5.80 (0.2284) 3.80 (0.1497) 4 0.50 (0.0196) 1.27 (0.0500) 45° BSC 1.75 (0.0688) 0.25 (0.0099) 1.35 (0.0532) 0.25 (0.0098) 8° 0.10 (0.0040) 0° COPLANARITY 0.51 (0.0201) 1.27 (0.0500) 0.10 0.31 (0.0122) 0.25 (0.0098) SEATING 0.40 (0.0157) PLANE 0.17 (0.0067) COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 58. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 3.00 2.90 2.80 65 4 3.00 1.70 2.80 1.60 2.60 1.50 123 PIN 1 INDICATOR 0.95 BSC 1.90 BSC 1.30 1.15 0.90 0.20 MAX 1.45 MAX 0.08 MIN 0.95 MIN 0.55 0.15 MAX 10° 0.45 SEATING 0.60 0.05 MIN 4° 0.50 MAX 0.35 PLANE BSC 0° 0.30 MIN COMPLIANT TO JEDEC STANDARDS MO-178-AB Figure 59. 6-Lead Small Outline Transistor Package [SOT-23] (RJ-6) Dimensions shown in millimeters Rev. B | Page 26 of 28 012407-A 12-16-2008-A Data Sheet ADA4896-2/ADA4897-1/ADA4897-2 3.10 3.00 2.90 10 6 5.15 3.10 4.90 3.00 4.65 1 2.90 5 PIN 1 IDENTIFIER 0.50 BSC 0.95 15° MAX 0.85 1.10 MAX 0.75 0.70 0.15 0.23 6° 0.55 0.30 0.05 0.13 0° 0.40 0.15 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA Figure 60. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters ORDERING GUIDE Package Ordering 1 Model Temperature Range Package Description Option Quantity Branding ADA4896-2ARMZ −40°C to +125°C 8-Lead MSOP RM-8 50 H2P ADA4896-2ARMZ-R7 −40°C to +125°C 8-Lead MSOP RM-8 1,000 H2P ADA4896-2ARMZ-RL −40°C to +125°C 8-Lead MSOP RM-8 3,000 H2P ADA4896-2ACPZ-R2 −40°C to +125°C 8-Lead LFCSP_WD CP-8-11 250 H2P ADA4896-2ACPZ-R7 −40°C to +125°C 8-Lead LFCSP_WD CP-8-11 1,500 H2P ADA4896-2ACPZ-RL −40°C to +125°C 8-Lead LFCSP_WD CP-8-11 5,000 H2P ADA4896-2ACP-EBZ Evaluation Board for the 8-Lead LFCSP ADA4896-2ARM-EBZ Evaluation Board for the 8-Lead MSOP ADA4897-1ARZ −40°C to +125°C 8-Lead SOIC_N R-8 98 ADA4897-1ARZ-R7 −40°C to +125°C 8-Lead SOIC_N R-8 1,000 ADA4897-1ARZ-RL −40°C to +125°C 8-Lead SOIC_N R-8 2,500 ADA4897-1ARJZ-R2 −40°C to +125°C 6-Lead SOT-23 RJ-6 250 H2K ADA4897-1ARJZ-R7 −40°C to +125°C 6-Lead SOT-23 RJ-6 3,000 H2K ADA4897-1ARJZ-RL −40°C to +125°C 6-Lead SOT-23 RJ-6 10,000 H2K ADA4897-1AR-EBZ Evaluation Board for the 8-Lead SOIC_N ADA4897-1ARJ-EBZ Evaluation Board for the 6-Lead SOT-23 ADA4897-2ARMZ −40°C to +125°C 10-Lead MSOP RM-10 50 H2N ADA4897-2ARMZ-R7 −40°C to +125°C 10-Lead MSOP RM-10 1,000 H2N ADA4897-2ARMZ-RL −40°C to +125°C 10-Lead MSOP RM-10 3,000 H2N ADA4897-2ARM-EBZ Evaluation Board for the 10-Lead MSOP 1 Z = RoHS Compliant Part. Rev. B | Page 27 of 28 091709-A ADA4896-2/ADA4897-1/ADA4897-2 Data Sheet NOTES ©2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09447-0-4/12(B) Rev. B | Page 28 of 28