2 8-Channel, I C, 12-Bit SAR ADC with Temperature Sensor Data Sheet AD7291 FEATURES FUNCTIONAL BLOCK DIAGRAM V DD GND 12-bit SAR ADC 8 single-ended analog input channels V Analog input range: 0 V to 2.5 V REF 12-bit temperature-to-digital converter REF BUF Temperature sensor accuracy of ±1°C typical 12-BIT Channel sequencer operation V IN0 SUCCESSIVE T/H Specified for V of 2.8 V to 3.6 V APPROXIMATION DD ADC Logic voltage V = 1.65 V to 3.6 V DRIVE INPUT Internal 2.5 V reference AD7291 V MUX IN7 2 I C-compatible serial interface supports standard and SEQUENCER fast speed modes SCL SDA CONTROL LOGIC Out of range indicator/alert function 2 I C INTERFACE AS1 Autocycle mode TEMP AS0 SENSOR Power-down current: 12 μA maximum V DRIVE Temperature range: −40°C to +125°C ALERT PD/RST 20-lead LFCSP package Figure 1. On-chip limit registers can be programmed with high and low GENERAL DESCRIPTION limits for the conversion results; an out-of-range indicator The AD7291 is a 12-bit, low power, 8-channel, successive output (ALERT) becomes active when the programmed high approximation analog-to-digital converter (ADC) with an or low limits are violated by the conversion result. This output internal temperature sensor. can be used as an interrupt. The part operates from a single 3.3 V power supply and features 2 PRODUCT HIGHLIGHTS an I C-compatible interface. The part contains a 9-channel multiplexer and a track-and-hold amplifier than can handle 1. Ideally suited to monitoring system variables in a variety frequencies up to 30 MHz. The device has an on-chip 2.5 V of systems including telecommunications, process control, reference that can be disabled to allow the use of an external and industrial control. 2 reference. 2. I C-compatible serial interface, which supports standard and fast modes. The AD7291 provides a 2-wire serial interface compatible with 3. Automatic partial power-down while not converting to 2 2 2 I C interfaces. The I C interface supports standard and fast I C maximize power efficiency. interface modes. The AD7291 normally remains in a partial 4. Channel sequencer operation. power-down state while not converting and powers up for 5. Integrated temperature sensor with 0.25°C resolution. conversions. The conversion process can be controlled by a 2 6. Out of range indicator that can be software disabled or command mode where conversions occur across I C write enabled. operations or an autocycle mode selected through software control. Table 1. AD7291 and Related Products Device Resolution Interface Features The AD7291 includes a high accuracy band gap temperature 2 2 12-bit IC 8-channel, I C, 12-bit SAR AD7291 sensor, which is monitored and digitized by the 12-bit ADC to ADC with temperature sensor give a resolution of 0.25°C. AD7298 12-bit SPI 8-channel, 1 MSPS, 12-bit SAR The AD7291 offers a programmable sequencer, which enables ADC with temperature sensor the selection of a preprogrammable sequence of channels for conversion. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 08711-001 AD7291 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Address Pointer Register ........................................................... 15 Functional Block Diagram .............................................................. 1 Command Register (0x00)........................................................ 17 General Description ......................................................................... 1 Voltage Conversion Result Register (0x01) ............................ 18 Product Highlights ........................................................................... 1 TSENSE Conversion Result Register (0x02)................................ 18 Revision History ............................................................................... 2 TSENSE Average Result Register (0x03)...................................... 19 Specifications..................................................................................... 3 Limit Registers (0x04 to 0x1E) ................................................. 19 2 I C Timing Specifications............................................................ 5 Hysteresis Register ..................................................................... 20 Absolute Maximum Ratings............................................................ 6 Alert Status Register A and Alert Status Register B (0x1F and 0x20)............................................................................................. 20 Thermal Resistance ...................................................................... 6 2 I C Interface .................................................................................... 21 ESD Caution.................................................................................. 6 Serial Bus Address Byte ............................................................. 21 Pin Configuration and Function Descriptions............................. 7 2 General I C Timing.................................................................... 21 Typical Performance Characteristics ............................................. 8 Writing to the AD7291 .................................................................. 22 Terminology .................................................................................... 11 Writing Two Bytes of Data to a 16-Bit Register ..................... 22 Circuit Information........................................................................ 12 Writing to Multiple Registers.................................................... 22 Converter Operation.................................................................. 12 Reading Data From the AD7291.................................................. 23 Analog Input ............................................................................... 12 Reading Two Bytes of Data from a 16-Bit Register ............... 23 ADC Transfer Function............................................................. 13 Modes of Operation ....................................................................... 24 Temperature Sensor Operation ................................................ 13 Command Mode ........................................................................ 24 Temperature Sensor Averaging................................................. 13 Autocycle Mode.......................................................................... 26 VDRIVE ............................................................................................ 14 Outline Dimensions....................................................................... 27 The Internal or External Reference.......................................... 14 Ordering Guide .......................................................................... 27 Reset ............................................................................................. 14 Internal Register Structure ............................................................ 15 REVISION HISTORY 10/11—Rev. A to Rev. B Changes to Table 9.......................................................................... 16 8/11—Rev. 0 to Rev. A Changes to Temperature Sensor—Internal, Accuracy Parameter, Table 2 ................................................................................................ 3 1/11—Revision 0: Initial Version Rev. B | Page 2 of 28 Data Sheet AD7291 SPECIFICATIONS VDD = 2.8 V to 3.6 V; VDRIVE = 1.65 V to 3.6 V; fSCL = 400 kHz, fast SCLK mode; VREF = 2.5 V internal/external; TA = −40°C to +125°C, unless otherwise noted. Table 2. 1 Parameter Min Typ Max Unit Test Conditions/Comments DYNAMIC PERFORMANCE f = 1 kHz sine wave IN 2 Signal-to-Noise Ratio (SNR) 70 71 dB 2 Signal-to-Noise (+ Distortion) Ratio (SINAD) 70 71 dB 2 Total Harmonic Distortion (THD) −84 −78 dB Spurious-Free Dynamic Range (SFDR) −85 −80 dB Intermodulation Distortion (IMD) f = 5.4 kHz, f = 4.6 kHz A B Second-Order Terms −88 dB Third-Order Terms −88 dB Channel-to-Channel Isolation −100 dB fIN = 10 kHz 3 Full Power Bandwidth 30 MHz At 3 dB 10 MHz At 0.1 dB DC ACCURACY Resolution 12 Bits 2 Integral Nonlinearity (INL) ±0.5 ±1 LSB 2 Differential Nonlinearity (DNL) ±0.5 ±0.99 LSB Guaranteed no missed codes to 12 bits 2 Offset Error ±2 ±4.5 LSB 2 Offset Error Matching ±2.5 ±4.5 LSB Offset Temperature Drift 4 ppm/°C 2 Gain Error ±1 ±4 LSB 2 Gain Error Matching ±1 ±2.5 LSB Gain Temperature Drift 0.5 ppm/°C ANALOG INPUT Input Voltage Ranges 0 V V REF DC Leakage Current ±0.01 ±1 μA 3 Input Capacitance 34 pF When in track 8 pF When in hold REFERENCE INPUT/OUTPUT 4 Reference Output Voltage 2.4925 2.5 2.5075 V ±0.3% maximum at 25°C Long-Term Stability 150 ppm For 1000 hours Output Voltage Hysteresis 50 ppm 5 Reference Input Voltage Range 1 2.5 V DC Leakage Current ±0.01 ±1 μA External reference applied to Pin V REF VREF Output Impedance 1 Ω Reference Temperature Coefficient 12 35 ppm/°C 3 VREF Noise 60 μV rms Bandwidth = 10 MHz LOGIC INPUTS (SDA, SCL) Input High Voltage, VINH 0.7 × VDRIVE V Input Low Voltage, VINL 0.3 × VDRIVE V Input Current, I ±0.01 ±1 μA V = 0 V or V IN IN DRIVE 3 Input Capacitance, C 6 pF IN Input Hysteresis, VHYST 0.1 × VDRIVE V Rev. B | Page 3 of 28 AD7291 Data Sheet 1 Parameter Min Typ Max Unit Test Conditions/Comments LOGIC OUTPUTS Output High Voltage, VOH VDRIVE − 0.3 V VDRIVE < 1.8 VDRIVE − 0.2 V VDRIVE ≥ 1.8 Output Low Voltage, V 0.4 V I = 3 mA OL SINK 0.6 V I = 6 mA SINK Floating State Leakage Current ±0.01 ±1 μA 3 Floating State Output Capacitance 8 pF TEMPERATURE SENSOR—INTERNAL Operating Range −40 +125 °C Accuracy ±1 ±2 °C TA = −40°C to +85°C ±1 ±3 °C TA = 85°C to 125°C Resolution 0.25 °C LSB size CONVERSION RATE Conversion Time 3.2 μs 6 Autocycle Update Rate 50 μs Throughput Rate 22.22 kSPS f = 400 kHz SCL POWER REQUIREMENTS Digital inputs = 0 V or VDRIVE V 2.8 3 3.6 V DD V 1.65 3 3.6 V DRIVE 7, 8 ITOTAL Normal Mode (Operational) 2.9 3.5 mA Normal Mode (Static) 2.9 3.3 mA Full Power-Down Mode 0.3 1.6 μA TA = −40°C to +25°C 1.6 4.5 μA T = >25°C to 85°C A 4.9 12 μA T = >85°C to 125°C A 8 Power Dissipation Normal Mode (Operational) 8.7 10.5 mW VDD = 3 V, VDRIVE = 3 V 10.4 12.6 mW Normal Mode (Static) 10.4 11.9 mW Full Power-Down Mode 1.1 5.8 μW T = −40°C to +25°C A 5.8 16.2 μW T = >25°C to 85°C A 17.6 43.2 μW TA = >85°C to 125°C 1 All specifications expressed in decibels are referred to full-scale input, FSR, and tested with an input signal at 0.5 dB below full scale, unless otherwise specified. 2 See the Terminology section. 3 Sample tested during initial release to ensure compliance. 4 o Refers to Pin V specified for 25 C. REF 5 A correction factor may be required on the temperature sensor results when using an external V (see the Temperature Sensor Averaging section). REF 6 Sampled during initial release to ensure compliance; not subject to production testing. 7 I is the total current flowing in V and V . TOTAL DD DRIVE 8 ITOTAL and power dissipation are specified with VDD = VDRIVE = 3.6 V, unless otherwise noted. Rev. B | Page 4 of 28 Data Sheet AD7291 2 I C TIMING SPECIFICATIONS Guaranteed by initial characterization. All values were measured with the input filtering enabled. CB refers to the capacitive load on the bus line, with tR and tF measured between 0.3 × VDRIVE and 0.7 × VDRIVE (see Figure 2). VDD = 2.8 V to 3.6 V; VDRIVE = 1.65 V to 3.6 V; VREF = 2.5 V internal/external; TA = −40°C to +125°C, unless otherwise noted. Table 3. Limit at T , T MIN MAX Parameter Conditions Min Typ Max Unit Description f Standard mode 100 kHz Serial clock frequency SCL Fast mode 400 kHz t Standard mode 4 μs t , SCL high time 1 HIGH Fast mode 0.6 μs t2 Standard mode 4.7 μs tLOW, SCL low time Fast mode 1.3 μs t Standard mode 250 ns t , data setup time 3 SU;DAT Fast mode 100 ns 1 t Standard mode 0 3.45 μs t , data hold time 4 HD;DAT Fast mode 0 0.9 μs t5 Standard mode 4.7 μs tSU;STA, setup time for a repeated start condition Fast mode 0.6 μs t Standard mode 4 μs t , hold time for a repeated start condition 6 HD;STA Fast mode 0.6 μs t7 Standard mode 4.7 μs tBUF, bus-free time between a stop and a start condition Fast mode 1.3 μs t8 Standard mode 4 μs tSU;STO, setup time for a stop condition Fast mode 0.6 μs t Standard mode 1000 ns t , rise time of the SDA signal 9 RDA Fast mode 20 + 0.1 C 300 ns B t10 Standard mode 300 ns tFDA, fall time of the SDA signal Fast mode 20 + 0.1 CB 300 ns t11 Standard mode 1000 ns tRCL, rise time of the SCL signal Fast mode 20 + 0.1 C 300 ns B t Standard mode 1000 ns t , rise time of the SCL signal after a repeated 11A RCL1 Fast mode 20 + 0.1 CB 300 ns start condition and after an acknowledge bit t12 Standard mode 300 ns tFCL, fall time of the SCL signal Fast mode 20 + 0.1 CB 300 ns t Fast mode 0 50 ns Pulse width of the suppressed spike SP t 6 ms Power-up and acquisition time POWER-UP 1 A device must provide a data hold time for SDA to bridge the undefined region of the SCL falling edge. t t 11 12 t t 6 2 SCL t 6 t t t t 4 3 5 8 t 1 t t 10 9 SDA t 7 S P S P S = START CONDITION P = STOP CONDITION Figure 2. 2-Wire Serial Interface Timing Diagram Rev. B | Page 5 of 28 08711-002 AD7291 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 4. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any V to GND1, GND −0.3 V to +5 V DD other conditions above those indicated in the operational V to GND1, GND −0.3 V to +5 V DRIVE section of this specification is not implied. Exposure to absolute Analog Input Voltage to GND1 −0.3 V to +3 V maximum rating conditions for extended periods may affect −0.3 V to V + 0.3 V Digital Input Voltage to GND1 DRIVE device reliability. Digital Output Voltage to GND1 −0.3 V to VDRIVE + 0.3 V V to GND1 −0.3 V to +3 V REF THERMAL RESISTANCE GND to GND1 −0.3 V to +0.3 V 1 Input Current to Any Pin Except Supplies ±10 mA Table 5. Thermal Resistance Operating Temperature Range −40°C to +125°C Package Type θJA θJC Unit Storage Temperature Range −65°C to +150°C 20-Lead LFCSP 52 6.5 °C/W Junction Temperature 150°C Pb-free Temperature, Soldering ESD CAUTION Reflow 260(+0)°C ESD 2 kV 1 Transient currents of up to 100 mA do not cause latch-up. Rev. B | Page 6 of 28 Data Sheet AD7291 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 15 SCL V 1 IN3 14 SDA V 2 IN4 AD7291 V 3 13 AS1 IN5 TOP VIEW (Not to Scale) ALERT V 4 12 IN6 11 AS0 V 5 IN7 NOTES 1. THE EXPOSED METAL PADDLE ON THE BOTTOM OF THE LFCSP PACKAGE SHOULD BE SOLDERED TO PCB GROUND FOR PROPER HEAT DISSIPATION AND PERFORMANCE. Figure 3. Pin Configuration Table 6. Pin Function Descriptions Pin No. Mnemonic Description 1 to 5, V , V , Analog Inputs. The AD7291 has eight single-ended analog inputs that are multiplexed into the on-chip track-and- IN3 IN4 18 to 20 VIN5, VIN6, hold amplifier. Each input channel can accept analog inputs from 0 V to 2.5 V. Any unused input channels should VIN7, VIN0, be connected to GND1 to avoid noise pickup. VIN1, VIN2 6 GND1 Ground. Ground reference point for the internal reference circuitry on the AD7291. All analog input signals and the external reference signals should be referred to this GND1 voltage. The GND1 pin should be connected to the ground plane of a system. All ground pins should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. The VREF pin should be decoupled to this ground pin via a 10 μF decoupling capacitor. 7 VREF Internal Reference/External Reference Supply. The nominal internal reference voltage of 2.5 V appears at this pin. Provided the output is buffered, the on-chip reference can be taken from this pin and applied externally to the rest of a system. Decoupling capacitors should be connected to this pin to decouple the reference buffer. For best performance, it is recommended to use a 10 μF decoupling capacitor on this pin to GND1. The internal reference can be disabled and an external reference supplied to this pin if required. The input voltage range for the external reference is 2.0 V to 2.5 V. 8 D Decoupling Capacitor Pin. Decoupling capacitors (1 μF recommended) are connected to this pin to decouple the CAP internal LDO. 9 GND Ground. Ground reference point for all analog and digital circuitry on the AD7291. The GND pin should be con- nected to the ground plane of the system. All ground pins should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. Both DCAP and VDD pins should be decoupled to this GND pin. 10 VDD Supply Voltage, 2.8 V to 3.6 V. This supply should be decoupled to GND with 10 μF and 100 nF decoupling capacitors. 2 11, 13 AS0, AS1 Logic Input. Together, the logic state of these two inputs selects a unique I C address for the AD7291. See Table 31 for details. The device address depends on the voltage applied to these pins. 12 ALERT Digital Output. This pin acts as an out-of-range indicator and, if enabled, becomes active when the conversion result violates the DATAHIGH or DATALOW register values. See the Limit Registers (0x04 to 0x1E) section. 14 SDA Digital Input/Output. Serial bus bidirectional data. This open-drain output requires a pull-up resistor. The output coding is straight binary for the voltage channels and twos complement for the temperature sensor result. 2 2 15 SCL Digital Input. Serial I C Bus Clock. This input requires a pull-up resistor. The data transfer rate in I C mode is compatible with both 100 kHz and 400 kHz operating modes. 16 VDRIVE Logic Power Supply Input. The voltage supplied at this pin determines the voltage at which the interface operates. This pin should be decoupled to GND. The voltage range on this pin is 1.65 V to 3.6 V and may be less than the voltage at VDD but should never exceed it by more than 0.3 V. 17 PD/RST Power-Down Pin. This pin places the part into a full power-down mode and enables power conservation when operation is not required. This pin can be used to reset the device by toggling the pin low for a minimum of 1 ns and a maximum of 100 ns. If the maximum time is exceeded, the part enters power-down mode. When placing the device in full power-down mode, the analog inputs must be returned to 0 V. EPAD EPAD Exposed Paddle. The exposed metal paddle on the bottom of the LFCSP package should be soldered to PCB ground for proper functionality and heat dissipation. Rev. B | Page 7 of 28 08711-003 GND1 6 20 V IN2 V 19 V REF 7 IN1 D 8 18 V CAP IN0 GND 9 17 PD/RST V 10 16 V DD DRIVE AD7291 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 1.0 0 V = V = 3V DD DRIVE 0.8 f = 22.22ksps S f = 400kHz –20 SCL 0.6 f = 10kHz IN SNR = 71.209 0.4 THD = –81.66 –40 T = 25°C A 0.2 V = 3V DRIVE V = 3V DD 0 –60 f = 22.22ksps S f = 400kHz SCL –0.2 –80 –0.4 –0.6 –100 INL (POSITIVE) –0.8 INL (NEGATIVE) –1.0 –120 0 0.5 1.0 1.5 2.0 2.5 3.0 02k 4k 6k 8k 10k V (V) FREQUENCY (Hz) REF Figure 4. Typical FFT Figure 7. INL vs. External V REF 1.0 1.0 T = 25°C A V = 3V 0.8 0.8 DRIVE V = 2.5V REF 0.6 V = 3V 0.6 DD f = 22.22ksps S 0.4 0.4 f = 400kHz SCL T = 25°C A 0.2 0.2 V = 3V DRIVE V = 3V 0 0 DD f = 22.22ksps S –0.2 –0.2 f = 400kHz SCL –0.4 –0.4 –0.6 –0.6 DNL (POSITIVE) –0.8 –0.8 DNL (NEGATIVE) –1.0 –1.0 0 500 1000 1500 2000 2500 3000 3500 4096 0 0.5 1.0 1.5 2.0 2.5 3.0 ADC CODE V (V) REF Figure 5. Typical ADC INL Figure 8. DNL vs. External V REF 1.0 11.7 0.8 0.6 11.6 0.4 0.2 11.5 0 –0.2 11.4 T = 25°C A –0.4 V = 3V DRIVE V = 2.5V –0.6 REF 11.3 V = 3V DD –0.8 f = 22.22ksps S f = 400kHz SCL –1.0 11.2 0 500 1000 1500 2000 2500 3000 3500 4096 0 0.5 1.0 1.5 2.0 2.5 ADC CODE EXTERNAL REFERENCE (V) Figure 6. Typical ADC DNL Figure 9. Effective Number of Bits vs. V , f = 400 kHz REF SCL Rev. B | Page 8 of 28 DNL (LSB) INL (LSB) AMPLITUDE (dB) 08711-009 08711-011 08711-010 EFFECTIVE NUMBER OF BITS DNL (LSB) INL (LSB) 08711-013 08711-012 08711-035 Data Sheet AD7291 125 3.0 V = V = 3V DD DRIVE V = V = 3V DD DRIVE 120 f = 400kHz SCL 2.5 115 110 2.0 105 1.5 100 95 1.0 90 85 0.5 80 0 75 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 1 10 100 1k f (kHz) CURRENT LOAD (mA) NOISE Figure 10. V vs. Reference Output Drive REF Figure 13. Channel-to-Channel Isolation, f = 10 kHz IN 55 72 V = 3V DRIVE V = 3V DD 50 45 71 40 35 70 30 25 20 69 0 20406080 100 02 0.5 1.0 1.5 2.0.5 TIME (Seconds) EXTERNAL REFERENCE (V) Figure 11. Response to Thermal Shock from Room Temperature into 50°C Figure 14. SINAD vs. Reference Voltage, f = 400 kHz, f = 22.22 kSPS SCL s Stirred Oil –90 1.5 V = 3V DD V = 3V DRIVE –92 1.0 –94 0.5 –96 –98 0 –100 –0.5 –102 –104 –1.0 –106 –1.5 –108 –110 –2.0 1k 10k 100k 1M 10M 100M –40 –25 –10 5 20 35 50 65 80 95 110 125 RIPPLE FREQUENCY (Hz) TEMPERATURE (°C) Figure 12. PSRR vs. Supply Ripple Frequency Without Supply Decoupling Figure 15. Temperature Accuracy at 3 V Rev. B | Page 9 of 28 PSRR (dB) TEMPERATURE READING (°C) V (V) REF 08711-021 08711-014 08711-061 SINAD (dB) TEMPERATURE ERROR (°C) CHANNEL-TO-CHANNEL ISOLATION (dB) 08711-018 08711-017 08711-036 AD7291 Data Sheet 9.0 2.5 V = 3V V = 3V DRIVE DRIVE 8.9 V = 3V DD 2.0 8.8 8.7 –40°C 1.5 8.6 +25°C +85°C 8.5 +125°C 1.0 8.4 8.3 8.2 0.5 8.1 0 8.0 0 60 120 180 240 300 360 420 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 SCL FREQUENCY (kHz) V DD Figure 16. Power vs. Throughput in Normal Mode Figure 17. Full Shutdown Current vs. Supply Voltage for Various Temperatures Rev. B | Page 10 of 28 POWER (mW) 08711-062 TOTAL CURRENT (µA) 08711-037 Data Sheet AD7291 TERMINOLOGY Aperture Delay Signal-to-Noise and Distortion Ratio (SINAD) The measured ratio of signal-to-noise and distortion at the The measured interval between the sampling clock’s leading output of the ADC. The signal is the rms amplitude of the edge and the point at which the ADC takes the sample. fundamental. Noise is the sum of all nonfundamental signals Aperture Jitter up to half the sampling frequency (f /2), excluding dc. The S This is the sample-to-sample variation in the effective point in ratio is dependent on the number of quantization levels in the time at which the sample is taken. digitization process; the more levels, the smaller the quantization Full-Power Bandwidth noise. The theoretical signal-to-noise and distortion ratio for The input frequency at which the amplitude of the recon- an ideal N-bit converter with a sine wave input is given by structed fundamental is reduced by 0.1 dB or 3 dB for a Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB full-scale input. Thus, the SINAD is 74 dB for an ideal 12-bit converter. Power Supply Rejection Ratio (PSRR) Total Harmonic Distortion (THD) PSRR is defined as the ratio of the power in the ADC output at The ratio of the rms sum of harmonics to the fundamental. For full-scale frequency, f, to the power of a 100 mV p-p sine wave the AD7291, it is defined as applied to the ADC V supply of frequency, f . The frequency DD S of the input varies from 5 kHz to 25 MHz. 2 2 2 2 2 V +V +V +V +V 2 3 4 5 6 THD (dB)= 20 log PSRR (dB) = 10 log(Pf/Pf ) S V 1 where: where: Pf is the power at frequency, f, in the ADC output. V1 is the rms amplitude of the fundamental. PfS is the power at frequency, fS, in the ADC output. V2, V3, V4, V5, and V6 are the rms amplitudes of the second Integral Nonlinearity through sixth harmonics. The maximum deviation from a straight line passing through Peak Harmonic or Spurious Noise the endpoints of the ADC transfer function. The endpoints are The ratio of the rms value of the next largest component in the zero scale, a point 1 LSB below the first code transition, and full ADC output spectrum (up to fS/2 and excluding dc) to the rms scale, a point 1 LSB above the last code transition. value of the fundamental. Typically, the value of this specification Differential Nonlinearity is determined by the largest harmonic in the spectrum, but for The difference between the measured and the ideal 1 LSB ADCs where the harmonics are buried in the noise floor, it is a change between any two adjacent codes in the ADC. noise peak. Offset Error Intermodulation Distortion The deviation of the first code transition (00…000) to With inputs consisting of sine waves at two frequencies, fa and (00…001) from the ideal—that is, GND1 + 1 LSB. fb, any active device with nonlinearities creates distortion products at sum and difference frequencies of mfa ± nfb, where Offset Error Match m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms The difference in offset error between any two channels. are those for which neither m nor n equals zero. For example, Gain Error second-order terms include (fa + fb) and (fa − fb), while third- The deviation of the last code transition (111…110) to order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb). (111…111) from the ideal (that is, V − 1 LSB) after the offset REF The AD7291 is tested using the CCIF standard where two input error has been adjusted out. frequencies near the top end of the input bandwidth are used. Gain Error Match In this case, the second-order terms are usually distanced in The difference in gain error between any two channels. frequency from the original sine waves while the third-order Track-and-Hold Acquisition Time terms are usually at a frequency close to the input frequencies. The track-and-hold amplifier returns to track mode at the end As a result, the second- and third-order terms are specified of conversion. Track-and-hold acquisition time is the time separately. The calculation of intermodulation distortion is, required for the output of the track-and-hold amplifier to reach like the THD specification, the ratio of the rms sum of the its final value, within ±1 LSB, after the end of conversion. individual distortion products to the rms amplitude of the sum of the fundamentals, expressed in dB. Rev. B | Page 11 of 28 AD7291 Data Sheet CIRCUIT INFORMATION When the ADC starts a conversion (see Figure 19), SW2 The AD7291 includes an 8-channel multiplexer, an on-chip opens and SW1 moves to Position B, causing the comparator track-and-hold amplifier, an analog-to-digital converter (ADC), to become unbalanced. The control logic and the capacitive an on-chip oscillator, internal data registers, an internal tempera- 2 DAC are used to add and subtract fixed amounts of charge to ture sensor, and an I C-compatible serial interface, all housed in bring the comparator back into a balanced condition. When the a 20-lead LFCSP. This package offers considerable space-saving comparator is rebalanced, the conversion is complete. The advantages over alternative solutions. The part can be operated control logic generates the ADC output code. Figure 21 shows from a single supply from 2.8 V to 3.6 V and offers 12 bits of the transfer functions of the ADC. resolution. The AD7291 has eight single-ended input channels and an on-chip ±12 ppm reference. The analog input range for CAPACITIVE DACE the AD7921 is 0 V to VREF. The AD7291 includes a high accuracy band gap temperature sensor, which is monitored and A V IN digitized by the 12-bit ADC to give a resolution of 0.25°C. CONTROL SW1 B LOGIC SW2 The AD7291 typically remains in a partial power-down state COMPARATOR GND1 while not converting. When supplies are first applied, the part Figure 19. ADC Conversion Phase powers up in a partial power-down state. Power-up is initiated prior to a conversion, and the device returns to partial power- ANALOG INPUT down mode when the conversion is complete. Conversions can Figure 20 shows an equivalent circuit of the analog input struc- be initiated by using the autocycle mode or command mode ture of the AD7291. The two diodes, D1 and D2, provide ESD where wake-up and a conversion occur during a write address protection for the analog inputs. Care must be taken to ensure function. When the conversion is complete, the AD7291 again that the analog input signal never exceeds the internally generated enters partial power-down mode. LDO voltage of 2.5 V (DCAP) by more than 300 mV. This causes the diodes to become forward biased and start conducting In command mode at the beginning of a read, the AD7291 current into the substrate. The maximum current these diodes wakes up completely, that is, becomes fully functional and can conduct without causing irreversible damage to the part is completes the conversion while the address is being read out. In 10 mA. Capacitor C1, in Figure 20, is typically about 8 pF and autocylce mode, conversions occur at 50 μs intervals; that is, the can primarily be attributed to pin capacitance. Resistor R1 is a AD7291 exits partial power-down mode and powers up fully at lumped component made up of the on resistance of a switch 50 μs intervals. This automatic partial power-down feature (track-and-hold switch) and the on resistance of the input allows power saving between conversions. Any read or write 2 multiplexer. The total resistance is typically about 155 Ω. operation across the I C interface can occur while the device is Capacitor C2 is the ADC sampling capacitor and has a in partial power-down mode. capacitance of 34 pF typically. CONVERTER OPERATION D (2.5V) CAP The AD7291 is a 12-bit successive approximation ADC based around a capacitive DAC. Figure 18 and Figure 19 show simpli- C2 D1 34pF fied schematics of the ADC during the acquisition and conversion R1 V IN phase, respectively. The ADC comprises control logic, SAR, D2 CONVERSION PHASE: SWITCH OPEN C1 TRACK PHASE: SWITCH CLOSED and a capacitive DAC that are used to add and subtract fixed 8pF amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. Figure 18 shows the acquisition phase. SW2 is closed and SW1 is in Position A, the Figure 20. Equivalent Analog Input Circuit comparator is held in a balanced condition, and the sampling For ac applications, removing high frequency components capacitor acquires the signal on the selected V channel. IN from the analog input signal is recommended by using an RC low-pass filter on the relevant analog input pin. In applications CAPACITIVE DAC where harmonic distortion and signal-to-noise ratios are critical, the analog input should be driven from a low imped- A V IN SW1 CONTROL ance source. Large source impedances significantly affect the B LOGIC SW2 ac performance of the ADC. This may necessitate the use of COMPARATOR GND1 an input buffer amplifier. The choice of the op amp is a function Figure 18. ADC Acquisition Phase of the particular application performance criteria. Rev. B | Page 12 of 28 08711-004 08711-006 08711-005 Data Sheet AD7291 Each input integrates, in turn, over a period of several hundred ADC TRANSFER FUNCTION microseconds. This takes place continuously in the background, The output coding of the AD7291 is straight binary for the leaving the user free to perform conversions on the other analog input channel conversion results and twos complement channels. When integration is complete, a signal passes to the for the temperature conversion result. The designed code tran- control logic to initiate a conversion automatically. sitions occur at successive LSB values (that is, 1 LSB, 2 LSBs, and so forth). The LSB size is V /4096 for the AD7291. The If the ADC is in command mode and performing a voltage REF ideal transfer characteristic for the AD7291 for straight binary conversion, the AD7291 waits for it to complete and then coding is shown in Figure 21. initiates a temperature sensor conversion. If the ADC is not performing voltage conversions, temperature conversions occur at 5 ms intervals. 111...111 In autocycle mode, the conversion is inserted into an 111...110 appropriate place in the current sequence. If the ADC is idle, the conversion takes place immediately. The TSENSE conversion 111...000 result register stores the result of the last conversion on the temperature channel; this can be read at any time. 011...111 1LSB = V /4096 REF Theoretically, the temperature measuring circuit can measure temperatures from −512°C to +511°C with a resolution of 000...010 0.25°C. However, temperatures outside T (the specified tem- A 000...001 000...000 perature range for the AD7291) are outside the guaranteed 0V 1LSB +V – 1LSB REF operating temperature range of the device. The temperature ANALOG INPUT sensor is enabled by setting the TSENSE bit in the command NOTES 1. V IS 2.5V. REF register. Figure 21. Straight Binary Transfer Characteristic TEMPERATURE SENSOR AVERAGING TEMPERATURE SENSOR OPERATION The AD7291 incorporates a temperature sensor averaging The AD7291 contains one local temperature sensor. The on-chip, feature to enhance the accuracy of the temperature measure- band gap temperature sensor measures the temperature of the ments. The temperature averaging feature is performed AD7291 die. continuously in the background provided the TSENSE bit in the command register is enabled. The temperature is The temperature sensor module on the AD7291 is based on the measured each time a T conversion is performed and a SENSE three current principle (see Figure 22), where three currents are moving average method is used to determine the result in the passed through a diode and the forward voltage drop is TSENSE average result register. The average result is given by the measured, allowing the temperature to be calculated free of following equation: errors caused by series resistance. V 7 1 DD T AVG=() Previous _ Average _ Result +() Current _ Result I4 × I 8 × I I BIAS SENSE 8 8 The average result is then available in the TSENSE average result register whose content is updated after every TSENSE conversion. V OUT+ The first TSENSE conversion result given by the AD7291 after the temperature sensor has been selected in the command register TO ADC (Bit D7) is the actual first T conversion result, and this SENSE V result remains valid until the next T conversion is INTERNAL OUT– SENSE SENSE completed and the result register is updated. TRANSISTOR BIAS DIODE Figure 22. Top Level Structure of Internal Temperature Sensor Rev. B | Page 13 of 28 ADC CODE 08711-007 08711-008 AD7291 Data Sheet Temperature Value Format V DRIVE One LSB of the ADC corresponds to 0.25°C. The temperature VDRIVE controls the voltage at which the serial interface operates. reading from the ADC is stored in a 12-bit twos complement VDRIVE allows the ADC to easily interface to both 1.8 V and 3 V format, to accommodate both positive and negative tempera- processors. For example, if the AD7291 is operated with a VDD ture measurements. Sample temperature values are listed in of 3.3 V, the V pin can be powered from a 1.8 V supply. DRIVE Table 7. The temperature conversion formulas are as follows: This enables the AD7291 to operate with a larger dynamic range with a V of 3.3 V while still being able to interface to DD Positive Temperature = ADC Code/4 1.8 V processors. Take care to ensure that VDRIVE does not Negative Temperature = (4096 − ADC Code)/4 exceed VDD by more than 0.3 V (see the Absolute Maximum The previous formulae are for a V of 2.5 V only. If an REF Ratings section). external reference is used, the temperature sensor requires an THE INTERNAL OR EXTERNAL REFERENCE external reference of between 2 V and 2.5 V for correct The AD7291 can operate with either the internal 2.5 V on-chip operation. The temperature results (in Celsius) are calculated reference or an externally applied reference. The EXT_REF bit using the following formula, where VEXT_REF is the value of the in the command register is used to determine whether the external reference voltage. internal reference is used. If the EXT_REF bit is selected in the ADCCode ⎛ ⎞ command register, an external reference can be supplied Temperature= V + 109.3 − 273.15 ⎜ ⎟ EXT _ REF ⎝ 10 ⎠ through the V pin. On power-up, the internal reference is REF enabled. Suitable external reference sources for the AD7291 Table 7. Temperature Data Format include AD780, AD1582, ADR431, REF193, and ADR391. Temperature (°C) Digital Output The internal reference circuitry consists of a 2.5 V band gap −40 1111 0110 0000 reference and a reference buffer. When the AD7291 operates in −25 1111 1001 1100 internal reference mode, the 2.5 V internal reference is available −10 1111 1101 1000 at the VREF pin, which should be decoupled to GND1 using a −0.25 1111 1111 1111 10 μF capacitor. It is recommended that the internal reference 0 0000 0000 0000 be buffered before applying it elsewhere in the system. +0.25 0000 0000 0001 +10 0000 0010 1000 The internal reference is capable of sourcing up to 2 mA of +25 0000 0110 0100 current when the converter is static. The reference buffer +50 0000 1100 1000 requires 5.5 ms to power up and charge the 10 μF decoupling +75 0001 0010 1100 capacitor during the power-up time. +100 0001 1001 0000 RESET +105 0001 1010 0100 The AD7291 includes a reset feature, which can be used to reset +125 0001 1111 0100 the device and the content of all internal registers including the command register to their default state. To activate the reset operation, the PD/RST pin should be brought low for a minimum of 1 ns and a maximum of 100 ns and be asynchronous PD to the clock; therefore, it can be triggered at any time. If the / RST pin is held low for greater than 100 ns, the part enters full PD RST power-down mode. It is imperative that the / pin be held at a stable logic level at all times to ensure normal operation. Rev. B | Page 14 of 28 Data Sheet AD7291 INTERNAL REGISTER STRUCTURE The AD7291 contains 34 internal registers (see Figure 23) that COMMAND REGISTER are used to store conversion results, high and low conversion VOLTAGE CONV limits, and information to configure and control the device. RESULT REGISTER There are 33 data registers and one address pointer register. T CONV SENSE RESULT REGISTER Each data register has an address that the address pointer T AVG SENSE register points to when communicating with it. Table 9 details RESULT REGISTER which registers are read, write, or read/write. CH0 DATA HIGH REGISTER ADDRESS POINTER REGISTER CH0 DATA LOW REGISTER The address pointer register is the register to which the first data byte of every write operation is written automatically; CH0 HYSTERESIS REGISTER therefore, this register does not have and does not require an ADDRESS POINTER CH1 DATA HIGH address. The address pointer register is an 8-bit register in REGISTER REGISTER which the six LSBs are used as pointer bits to store an address CH1 DATA LOW that points to one of the AD7291’s data registers. The first byte REGISTER following each write address is to the address pointer register, CH1 HYSTERESIS REGISTER containing the address of one of the data registers. The six LSBs select the data register to which subsequent data bytes are written. Only the six LSBs of this register are used to select a CH7 DATA HIGH REGISTER data register. During power-up, the address pointer register contains all 0s, pointing to the command register. CH7 DATA LOW REGISTER CH7 HYSTERESIS Table 8. Address Pointer Register REGISTER D1 D0 P5 P4 P3 P2 P1 P0 T DATA SENSE HIGH 0 0 Register select REGISTER T DATA SENSE LOW REGISTER T HYSTERESIS SENSE REGISTER SDA SCL ALERT STATUS REGISTER A ALERT STATUS REGISTER B SERIAL BUS INTERFACE Figure 23. AD7291 Register Structure Rev. B | Page 15 of 28 DATA 08711-015 AD7291 Data Sheet Table 9. AD7291 Register Addresses Hex Code P5 P4 P3 P2 P1 P0 Registers Read/Write 0x00 0 0 0 0 0 0 Command register Write. 0x01 0 0 0 0 0 1 Voltage conversion result register Read. 0x02 0 0 0 0 1 0 T conversion result register Read. SENSE 0x03 0 0 0 0 1 1 T average result register Read. SENSE 0x04 0 0 0 1 0 0 CH0 DATA register Read/write. HIGH 0x05 0 0 0 1 0 1 CH0 DATALOW register Read/write. 0x06 0 0 0 1 1 0 CH0 hysteresis register Read/write. 0x07 0 0 0 1 1 1 CH1 DATAHIGH register Read/write. 0x08 0 0 1 0 0 0 CH1DATA register Read/write. LOW 0x09 0 0 1 0 0 1 CH1 hysteresis register Read/write. 0x0A 0 0 1 0 1 0 CH2 DATAHIGH register Read/write. 0x0B 0 0 1 0 1 1 CH2 DATALOW register Read/write. 0x0C 0 0 1 1 0 0 CH2 hysteresis register Read/write. 0x0D 0 0 1 1 0 1 CH3 DATAHIGH register Read/write. 0x0E 0 0 1 1 1 0 CH3 DATA register Read/write. LOW 0x0F 0 0 1 1 1 1 CH3 hysteresis register Read/write. 0x10 0 1 0 0 0 0 CH4 DATAHIGH register Read/write. 0x11 0 1 0 0 0 1 CH4 DATALOW register Read/write. 0x12 0 1 0 0 1 0 CH4 hysteresis register Read/write. 0x13 0 1 0 0 1 1 CH5 DATA register Read/write. HIGH 0x14 0 1 0 1 0 0 CH5 DATA register Read/write. LOW 0x15 0 1 0 1 0 1 CH5 hysteresis register Read/write. 0x16 0 1 0 1 1 0 CH6 DATAHIGH register Read/write. 0x17 0 1 0 1 1 1 CH6 DATALOW register Read/write. 0x18 0 1 1 0 0 0 CH6 hysteresis register Read/write. 0x19 0 1 1 0 0 1 CH7 DATA register Read/write. HIGH 0x1A 0 1 1 0 1 0 CH7 DATA register Read/write. LOW 0x1B 0 1 1 0 1 1 CH7 hysteresis register Read/write. 0x1C 0 1 1 1 0 0 TSENSE DATAHIGH register Read/write. 0x1D 0 1 1 1 0 1 TSENSE DATALOW register Read/write. 0x1E 0 1 1 1 1 0 T hysteresis register Read/write. SENSE 0x1F 0 1 1 1 1 1 Alert Status Register A Read. 0x20 1 0 0 0 0 0 Alert Status Register B Read. 0x3F 1 1 1 1 1 1 Factory test mode The user should not access this register. Rev. B | Page 16 of 28 Data Sheet AD7291 COMMAND REGISTER (0x00) The command register is a 16-bit write-only register that is used to set the operating modes of the AD7291. The bit functions are outlined in Table 10. A two-byte write is necessary when writing to the command register. MSB denotes the first bit in the data stream. During power-up, the default content of the command register is all 0s. Table 10. Command Register Bits and Default Settings at Power-Up MSB LSB Channel Bit D15 to DB8 D7 D6 D5 D4 D3 D2 D1 D0 Function CH0 to CH7 TSENSE Don’t Noise-delayed EXT_REF Polarity of ALERT Clear alert RESET Autocycle care bit trial and pin (active high/ mode sampling active low) Setting Enable = 1 Enable = 1 0 Enable = 1 Enable = 1 Active low = 1 Enable = 1 Enable = 1 Enable = 1 Disable = 0 Disable = 0 Disable = 0 Disable = 0 Active high = 0 Disable = 0 Disable = 0 Disable = 0 Table 11. Command Register Bit Function Descriptions Bit Mnemonic Comment D15 to D8 CH0 to CH7 These 8-channel address bits select the analog input channel(s) to be converted. A 1 in any of Bit D15 to Bit D8 selects a channel for conversion. If more than one channel bit is set to 1, the AD7291 sequences through the selected channels, starting with the lowest channel. All unused channels should be set to 0. A channel or sequence of channels for conversion must be selected in the command register, prior to initiating a conversion. D7 TSENSE This bit enables temperature conversions, which occur in the background at 5 ms intervals. The results can be read from the TSENSE conversion result register (0x02) and the TSENSE average result register (0x03). For details, refer to the Temperature Sensor Operation section. D6 Don’t care D5 Noise- When this function is enabled, it delays the critical sampling intervals and bit trials when there is activity on 2 delayed bit the I C bus, thus ensuring improved dc performance of the AD7291. When this feature is enabled, the trial and conversion time may vary. This bit is disabled on power-up, and it is recommended to write a 1 to enable this sampling feature for normal operation. D4 EXT_REF Writing a Logic 1 to this bit enables the use of an external reference. The input voltage range for the external reference is 2 V to 2.5 V. The external reference should not exceed 2.5 V or the device performance will be adversely affected. During power-up, the default configuration has the internal reference enabled. D3 Polarity of This bit determines the active polarity of the ALERT pin. The ALERT pin is configured for active low operation ALERT pin if this bit is set to 1 and active high if this bit is set to 0. The default configuration on power-up is active high (0). D2 Clear alert This bit clears the content of the alert status register. Once the content of both alert status registers is cleared, this bit should be reprogrammed to a Logic 0 to ensure that future alerts are detected. D1 RESET Setting this bit resets the contents of all internal registers in the AD7291 to their default states including the command register itself. This bit is automatically returned to 0 once the reset is completed to enable the internal registers to be reprogrammed. D0 Autocycle Writing a 1 to this bit enables the autocycle mode of operation. In this mode, the channels selected in Bit D15 mode to Bit D8 are continuously converted by the AD7291. This function is used in conjunction with the limit registers, which can be programmed to issue an alert if the conversion result exceeds the preset limit for any channel selected for conversion. Rev. B | Page 17 of 28 AD7291 Data Sheet Table 12. Channel Selection Bits for Command Register D15 D14 D13 D12 D11 D10 D9 D8 Selected Analog Input Channel Comments 0 0 0 0 0 0 0 0 No channel selected If more than one channel is selected, the AD7291 converts the 0 0 0 0 0 0 0 1 Convert on Channel 7 (VIN7) selected channels starting with the 0 0 0 0 0 0 1 0 Convert on Channel 6 (V ) IN6 lowest channel in the sequence. 0 0 0 0 0 1 0 0 Convert on Channel 5 (V ) IN5 0 0 0 0 1 0 0 0 Convert on Channel 4 (V ) IN4 0 0 0 1 0 0 0 0 Convert on Channel 3 (VIN3) 0 0 1 0 0 0 0 0 Convert on Channel 2 (VIN2) 0 1 0 0 0 0 0 0 Convert on Channel 1 (VIN1) 1 0 0 0 0 0 0 0 Convert on Channel 0 (V ) IN0 Table 13. TSENSE Data Format Input D11 (MSB) D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 (LSB) Value (°C) −512 +256 +128 +64 +32 +16 +8 +4 +2 +1 +0.5 +0.25 Sample Delay and Bit Trial Delay Table 14. Conversion Value Register (First Read) 2 MSB Ideally, no I C bus activity should occur while an ADC D15 D14 D13 D12 D11 D10 D9 D8 conversion is taking place. However, this may not be possible, ADD3 ADD2 ADD1 ADD0 B11 B10 B9 B8 for example, when operating in autocycle mode. It is therefore recommended to enable the noise delayed bit trial and sampling Table 15. Conversion Value Register (Second Read) function by writing a 1 to Bit D5 in the command register. This LSB mechanism delays critical sample intervals and bit trials while 2 D7 D6 D5 D4 D3 D2 D1 D0 there is activity on the I C bus. This results in a quiet period for B7 B6 B5 B4 B3 B2 B1 B0 each bit decision, and conversion results are less susceptible to interference from external noise. Table 16. Channel Address Bits for the Result Register On power-up, the bit trial and sample interval delay mechanism ADD2 ADD2 ADD1 ADD0 Analog Input Channel is not enabled. It is recommended that this feature should be 0 0 0 0 VIN0 enabled for normal operation. When enabled, the AD7291 0 0 0 1 VIN1 delays the bit trials, mitigating against the effect of activity on 0 0 1 0 V IN2 2 the I C bus. In cases where there is excessive activity on the 0 0 1 1 V IN3 interface lines, enabling these bits may cause the overall 0 1 0 0 VIN4 conversion time to increase. 0 1 0 1 VIN5 0 1 1 0 VIN6 The AD7291 also incorporates functionality that allows it to 0 1 1 1 V reject glitches shorter than 50 ns. This feature improves the IN7 1 0 0 0 T noise susceptibility of the device. SENSE 1 0 0 1 T average result SENSE VOLTAGE CONVERSION RESULT REGISTER (0x01) The voltage conversion result register is a 16-bit read-only Temperature Value Format register that stores the conversion result from the ADC in The temperature reading from the ADC is stored in an 11-bit straight binary format. A 2-byte read is necessary to read data twos complement format, D11 to D0, to accommodate both from this register. Table 14 and Table 15 show the contents of positive and negative temperature measurements. The tem- the first and second bytes of data to be read from the AD7291. perature data format is provided in Table 13. Each AD7291 conversion result consists of four channel address T CONVERSION RESULT REGISTER (0x02) bits (see Table 14 and Table 15) and the 12-bit data result. SENSE Bit D15 to Bit D12 are the channel address bits that identify The TSENSE result register is a 16-bit read-only register used to the ADC channel that corresponds to the subsequent result. store the ADC data generated from the internal temperature Bit D11 to Bit D0 contain the most recent ADC result. sensor. This register stores the temperature readings from the ADC in a 12-bit twos complement format, D11 to D0, and uses Bit D15 to Bit D12 to store the channel address bits. Conversions take place approximately every 5 ms. Table 13 details the temperature data format that applies to the internal temperature sensor. Rev. B | Page 18 of 28 Data Sheet AD7291 Table 17. T Conversion Result Register (First Read) DATA Register SENSE HIGH MSB The DATAHIGH registers for CH0 to CH7 and the internal D15 D14 D13 D12 D11 D10 D9 D8 temperature sensor are 16-bit read/write registers; only the ADD3 ADD2 ADD1 ADD0 B11 B10 B9 B8 12 LSBs of each register are used. Bit D15 to Bit D12 are not used in the register and are set to 0s. This register stores the Table 18. TSENSE Result Register (Second Read) upper limit that activates the ALERT output. If the value in the LSB conversion result register is greater than the value in the D7 D6 D5 D4 D3 D2 D1 D0 DATA register, an ALERT occurs for that channel. When HIGH B7 B6 B5 B4 B3 B2 B1 B0 the conversion result returns to a value at least N LSBs below the DATAHIGH register value, the ALERT output pin is reset. The T AVERAGE RESULT REGISTER (0x03) SENSE value of N is taken from the hysteresis register associated with that channel. The ALERT pin can also be reset by writing to The TSENSE average result register is a 16-bit read-only register Bit D2 in the command register. used to store the average result from the internal temperature sensor. This register stores the average temperature readings Table 21. DATA Register (First Read/Write) HIGH from the ADC in an 11-bit twos complement format, D11 to MSB D0, and uses Bit D15 to Bit D12 to store the channel address D15 D14 D13 D12 D11 D10 D9 D8 bits. The T average result register is updated after every SENSE 0 0 0 0 B11 B10 B9 B8 T conversion is completed. The first T average SENSE SENSE conversion result given by the AD7291 after averaging is Table 22. DATAHIGH Register (Second Read/Write) enabled is the actual first TSENSE conversion result. Table 13 LSB details the temperature data format, which applies to the D7 D6 D5 D4 D3 D2 D1 D0 internal temperature sensor. See the Temperature Sensor B7 B6 B5 B4 B3 B2 B1 B0 Averaging section for more details. DATA Register Table 19. T Average Result Register (First Read) LOW SENSE MSB The DATALOW register for each channel is a 16-bit read/write D15 D14 D13 D12 D11 D10 D9 D8 register; only the 12 LSBs of each register are used. Bit D15 to ADD3 ADD2 ADD1 ADD0 B11 B10 B9 B8 Bit D12 are not used in the register and are set to 0s. The register stores the lower limit that activates the ALERT output. Table 20. TSENSE Average Result Register (Second Read) If the value in the T conversion result register is less than SENSE LSB the value in the DATALOW register, an ALERT occurs for that D7 D6 D5 D4 D3 D2 D1 D0 channel. When the conversion result returns to a value at least B7 B6 B5 B4 B3 B2 B1 B0 N LSBs above the DATALOW register value, the ALERT output pin is reset. The value of N is taken from the hysteresis register LIMIT REGISTERS (0x04 TO 0x1E) associated with that channel. The ALERT output pin can also be reset by writing to Bit D2 in the command register. The AD7291 has nine pairs of limit registers. Each pair stores high and low conversion limits for each analog input channel Table 23. DATA Register (First Read/Write) LOW and the internal temperature sensor. Each pair of limit registers MSB has one associated hysteresis register. All 27 registers are 16 bits D15 D14 D13 D12 D11 D10 D9 D8 wide; only the 12 LSBs of the registers are used for the AD7291. 0 0 0 0 B11 B10 B9 B8 The four MSBs, D15 and D12, in these registers should contain 0s. During power-up, the contents of the DATAHIGH register for Table 24. DATALOW Register (Second Read/Write) each analog voltage channel is full scale (0x0FFF), while the LSB default contents of the DATALOW voltage channels registers is D7 D6 D5 D4 D3 D2 D1 D0 zero scale (0x0000). The output coding of the AD7291 is twos B7 B6 B5 B4 B3 B2 B1 B0 complement for the temperature conversion result. The default content for the T DATA register is 0x07FF, while the SENSE HIGH default content of the T DATA register is 0x0800. The SENSE LOW AD7291 signals an alert in hardware if the conversion result moves outside the upper or lower limit set by the limit registers. Rev. B | Page 19 of 28 AD7291 Data Sheet ALERT STATUS REGISTER A AND ALERT STATUS HYSTERESIS REGISTER REGISTER B (0x1F AND 0x20) Each analog input channel and the internal temperature sensor The alert status registers are 16-bit, read-only registers that has its own hysteresis register, which is a 16-bit read/write provide information on an alert event. If a conversion result register. Only the 12 LSBs are used. Bit D15 to Bit D12 are not activates the ALERT pin, as described in the Limit Registers used in the register and are set to 0s. The hysteresis register (0x04 to 0x1E) section, the alert status register can be read to stores the hysteresis value, N, when using the limit registers. gain further information. There are two alert status registers in Each pair of limit registers has a dedicated hysteresis register. the AD7291; Alert Status Register A, which stores alerts for the The hysteresis value determines the reset point for the ALERT analog voltage conversion channels (see Table 27 and Table 28) pin if a violation of the limits occurs. For example, if a hysteresis and Alert Status Register B, which stores alerts for the internal value of eight LSBs is required on the upper and lower limits of temperature sensor only (see Table 29 and Table 30). Channel 0, the 16-bit word, 0000 0000 0000 1000, should be written to the hysteresis register of CH0, the address of which Both alert status registers contain two status bits per channel, is 0x06 (see Table 25 and Table 26). During power-up, the one corresponding to the DATAHIGH limit and the other to the hysteresis registers content defaults to all zeros (0x0000). If a DATALOW limit. The bit with a status of 1 shows where the hysteresis value is required, that value must be written to the violation occurred—that is, on which channel—and whether hysteresis register for the channel in question. the violation occurred on the upper or lower limit. If a second alert event occurs on the other channel between receiving the Table 25. Hysteresis Register (First Read/Write Byte) first alert and interrogating the alert status register, the corres- MSB ponding bit for that alert event is also set. The entire contents D15 D14 D13 D12 D11 D10 D9 D8 of the alert status register can be cleared by writing 1 to Bit D2 0 0 0 0 B11 B10 B9 B8 in the command register. Table 26. Hysteresis Register (Second Read/Write Byte) For example, if Bit D14 in Alert Status Register A is set to 1, the lower limit on Channel 7 (Register 0x1A) has been violated, LSB while if Bit D11 is set 1, the upper limit on Channel 5 has been D7 D6 D5 D4 D3 D2 D1 D0 violated (Register 0x13). B7 B6 B5 B4 B3 B2 B1 B0 The TSENSE and TSENSE_AVG alerts are determined HIGH HIGH by comparison with the TSENSE DATAHIGH register (Register 0x1C). Likewise, the TSENSELOW and TSENSE_AVGLOW alerts are determined by comparison with the TSENSE DATALOW register (Register 0x1D). Table 27. Alert Status Register A (First Read Byte) D15 D14 D13 D12 D11 D10 D9 D8 CH7HIGH CH7LOW CH6HIGH CH6LOW CH5HIGH CH5LOW CH4HIGH CH4LOW Table 28. Alert Status Register A (Second Read Byte) D7 D6 D5 D4 D3 D2 D1 D0 CH3HIGH CH3LOW CH2HIGH CH2LOW CH1HIGH CH1LOW CH0HIGH CH0LOW Table 29. Alert Status Register B (First Read Byte) D15 D14 D13 D12 D11 D10 D9 D8 0 0 0 0 0 0 0 0 Table 30. Alert Status Register B (Second Read Byte) D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 TSENSE_AVGHIGH TSENSE_AVGLOW TSENSEHIGH TSENSELOW Rev. B | Page 20 of 28 Data Sheet AD7291 2 I C INTERFACE 2 Control of the AD7291 is carried out via the I C compatible the serial clock line (SCL) remains high. This indicates that a serial bus. The AD7291 is connected to this bus as a slave device data stream follows. The master device is responsible for under the control of a master device such as the processor. generating the clock. Data is sent over the serial bus in groups of nine bits—eight bits SERIAL BUS ADDRESS BYTE of data from the transmitter followed by an acknowledge bit The first byte the user writes to the device is the slave address (ACK) from the receiver. Data transitions on the SDA line must 2 byte. Similar to all I C-compatible devices, the AD7291 has a occur during the low period of the clock signal and remain 7-bit serial address. The three MSBs of this address are set to stable during the high period. The receiver should pull the SDA 010. The four LSBs are user-programmable by the three-state line low during the acknowledge bit to signal that the preceding input pins, AS0 and AS1, as shown in Table 31. byte has been received correctly. If this is not the case, cancel In Table 31, H means tie the pin to V , L means tie the pin DRIVE the transaction. to GND, and NC refers to a pin left floating. Note that in this The first byte that the master sends must consist of a 7-bit slave final case, the stray capacitance on the pin must be less than address, followed by a data direction bit. Each device on the 30 pF to allow correct detection of the floating state; therefore, bus has a unique slave address; therefore, the first byte sets up any PCB trace must be kept as short as possible. communication with a single slave device for the duration of the transaction. Table 31. Slave Address Control Using Three-State Input Pins Slave Address (A6 to A0) The transaction can be used either to write to a slave device AS1 AS0 Binary Hex (data direction bit = 0) or to read data from it (data direction H H 010 0000 0x20 bit = 1). In the case of a read transaction, it is often necessary H NC 010 0010 0x22 first to write to the slave device (in a separate write transaction) H L 010 0011 0x23 to tell it from which register to read. Reading and writing NC H 010 1000 0x28 cannot be combined in one transaction. NC NC 010 1010 0x2A When the transaction is complete, the master can keep control NC L 010 1011 0x2B of the bus, initiating a new transaction by generating another L H 010 1100 0x2C start bit (high-to-low transition on SDA while SCL is high). L NC 010 1110 0x2E This is known as a repeated start (SR). Alternatively, the bus L L 010 1111 0x2F can be relinquished by releasing the SCL line followed by the SDA line. This low-to-high transition on SDA while SCL is high 2 GENERAL I C TIMING 2 is known as a stop bit (P), and it leaves the I C bus in its idle Figure 24 shows the timing diagram for general read and write state (no current is consumed by the bus). 2 operations using an I C-compliant interface. The example in Figure 24 shows a simple write transaction When no device is driving the bus, both SCL and SDA are high. with an AD7291 as the slave device. In this example, the This is known as the idle state. When the bus is idle, the master AD7291 register pointer is being set up for a future read initiates a data transfer by establishing a start condition, defined transaction. as a high-to-low transition on the serial data line (SDA) while SCL SDA R/W A6 A5 A4 A3 A2 A1 A0 P7 P6 P5 P4 P3 P2 P1 P0 START COND ACK. BY ACK. BY STOP BY SLAVE ADDRESS BYTE REGISTER ADDRESS BY MASTER AD7291 AD7291 MASTER USER PROGRAMMABLE 5 LSBs 2 Figure 24. General I C Timing Rev. B | Page 21 of 28 08711-040 AD7291 Data Sheet WRITING TO THE AD7291 WRITING TWO BYTES OF DATA TO A 16-BIT WRITING TO MULTIPLE REGISTERS REGISTER Writing to multiple address registers consists of the following steps (see Figure 26): All registers on the AD7921 are 16-bit registers; therefore, two bytes of data are required to write a value to any one of these 1. The master device asserts a start condition on SDA. registers. Writing two bytes of data to a register consists of the 2. The master sends the 7-bit slave address followed by following sequence (see Figure 25): the write bit (low). 1. The master device asserts a start condition on SDA. 3. The addressed slave device (AD7291) asserts an 2. The master sends the 7-bit slave address followed by the acknowledge on SDA. 4. The master sends a register address, for example, the CH1 write bit (low). DATA register address. 3. The addressed slave device asserts an acknowledge on SDA. HIGH 5. The slave (AD7291) asserts an acknowledge on SDA. 4. The master sends a register address. The slave asserts an 6. The master sends the first data byte. acknowledge on SDA. 5. The master sends the first data byte (most significant). 7. The slave (AD7291) asserts an acknowledge on SDA. 6. The slave asserts an acknowledge on SDA. 8. The master sends the second data byte. 7. The master sends the second data byte (least significant). 9. The slave (AD7291) asserts an acknowledge on SDA. 8. The slave asserts an acknowledge on SDA. 10. The master sends a second register address, for example, the command register. 9. The master asserts a stop condition on SDA to end the 11. The slave (AD7291) asserts an acknowledge on SDA. transaction. 12. The master sends the first data byte. 13. The slave (AD7291) asserts an acknowledge on SDA. 14. The master sends the second data byte. 15. The slave (AD7291) asserts an acknowledge on SDA. 16. The master asserts a stop condition on SDA to end the transaction. The previous example details writing to two registers only (the CH1 DATA register address and the command register). HIGH However, the AD7291 can read from multiple registers in one write operation as shown in Figure 26. S SLAVE ADDRESS 0 SA REG POINTER SA DATA[15:8] SA DATA[7:0] SA P FROM MASTER TO SLAVE S = START CONDITION SR = REPEATED START P = STOP CONDITION FROM SLAVE TO MASTER SA = SLAVE ACKNOWLEDGE A = NOT ACKNOWLEDGE Figure 25. Writing Two Bytes of Data to a 16-Bit Register ... S SLAVE ADDRESS 0 SA POINT TO CH1 DATA REG (0x04) SA DATA[15:8] SA DATA[7:0] SA HIGH ... POINT TO COMMAND REG (0x00) SA DATA[15:8] SA DATA[7:0] SA P FROM MASTER TO SLAVE S = START CONDITION SR = REPEATED START P = STOP CONDITION FROM SLAVE TO MASTER SA = SLAVE ACKNOWLEDGE A = NOT ACKNOWLEDGE Figure 26. Writing to Multiple Registers Rev. B | Page 22 of 28 08711-059 08711-019 Data Sheet AD7291 READING DATA FROM THE AD7291 Reading two bytes of data from a 16-bit register consists of the READING TWO BYTES OF DATA FROM A 16-BIT following sequence (see Figure 27): REGISTER 1. The master device asserts a start condition on SDA. Reading the contents from any of the 16-bit registers is a 2-byte 2. The master sends the 7-bit slave address followed by the read operation. In this protocol, the first part of the transaction read bit (high). writes to the register pointer. When the register address has 3. The addressed slave device asserts an acknowledge on SDA. been set up, any number of reads can be performed from that 4. The master receives a data byte. particular register without having to write to the address 5. The master asserts an acknowledge on SDA. pointer register again. When the required number of reads 6. The master receives a second data byte. is completed, the master should not acknowledge the final 7. The master asserts an acknowledge on SDA. byte. This tells the slave to stop transmitting, allowing a stop 8. The master receives a data byte. condition to be asserted by the master. Further reads from 9. The master asserts an acknowledge on SDA. this register can be performed in a future transaction without 10. The master receives a second data byte. having to rewrite to the register pointer. 11. The master asserts an acknowledge on SDA. If a read from a different address is required, the relevant 12. The master receives a data byte. register address has to be written to the address pointer register 13. The master asserts an acknowledge on SDA. and, again, any number of reads from this register can then be 14. The master receives a second data byte. performed. In the following example, the master device reads 15. The master asserts a not acknowledge on SDA to notify the three lots of 2-byte data from a slave device but as many lots slave that the data transfer is complete. consisting of two bytes can be read as required. This protocol 16. The master asserts a stop condition on SDA to end the assumes that the particular register address has been set up by transaction. a single-byte write operation to the address pointer register. ... S SLAVE ADDRESS 1 A DATA[15:8] A DATA[7:0] A DATA[15:8] A DATA[7:0] A ... DATA[15:8] DATA[7:0] A A P FROM MASTER TO SLAVE S = START CONDITION SR = REPEATED START P = STOP CONDITION FROM SLAVE TO MASTER A = ACKNOWLEDGE A = NOT ACKNOWLEDGE Figure 27. Reading Three Lots of Two Bytes of Data from the Conversion Result Register Rev. B | Page 23 of 28 08711-060 AD7291 Data Sheet MODES OF OPERATION When supplies are first applied to the AD7291, the ADC register is initiated. When operating the device in fast mode, the powers up in partial power-down mode and normally remains acquisition and conversion times combined take approximately in this partial power-down state while not converting. Once 4.45 μs (1.25 μs acquisition time plus 3.2 μs conversion time). the master addresses the AD7291, it exits partial power-down. When in command mode, the part cycles through the selected There are two methods of initiating a conversion on the channels from the lowest selected channel in the sequence to AD7291: command mode and autocycle mode. the next lowest until all the channels in the sequence are converted. COMMAND MODE To exit the command mode, the master should not acknowledge In command mode, the AD7291 converts on demand on either the final byte of data. This stops the AD7291 transmitting, a single channel or a sequence of channels. Writing in the allowing the master to assert a stop condition on the bus. On command register puts the part into command mode. This is the receipt of a stop condition, the AD7291 stops converting the default mode of operation and allows a conversion to be and enters partial power-down mode, but the content of the automatically selected any time a write operation occurs to the command register is preserved. Once the part is readdressed command register. To enter this mode, the required combina- and a read is initiated from the voltage conversion register, the tion of channels is written into the command register (Register AD7291 begins converting on the previously selected sequence 0x00). Following the write operation, the AD7291 must be of channels. The conversion sequence starts converting the addressed again to indicate that a read operation is required. first selected channel in the sequence; that is, if Channel 1, The read then takes place from the voltage or temperature Channel 2, and Channel 3 are selected and a stop condition conversion result register. For the first conversion to occur, occurs after the Channel 1 result is read, on resumption of the address pointer written to the AD7291 must point to the conversions, Channel 1 is reconverted and the conversion voltage conversion result register or TSENSE conversion result sequence continues. register. The conversion is completed while the first four channel address bits are read. The next conversion in the sequence takes place once the next read from the result Rev. B | Page 24 of 28 Data Sheet AD7291 The example in Figure 28 shows the command mode convert- 15. The master then asserts an acknowledge on SDA. ing on a sequence of channels including V , V , and V . 16. The master receives the second data byte, which contains IN0 IN1 IN2 the eight LSBs of the converted result for Channel V . The IN0 1. The master device asserts a start condition on SDA. master then asserts on acknowledge on SDA. 2. The master sends the 7-bit slave address followed by the 17. Step 11 and Step 12 repeat for Channel VIN1 and write bit (low). Channel VIN2. 3. The addressed slave device (AD7291) asserts an 18. Once the master has received the results from all the acknowledge on SDA. selected channels, the slave again converts and outputs 4. The master sends the command register address (0x00). the result for the first channel in the selected sequence. 5. The slave asserts an acknowledge on SDA. Step 12 to Step 14 are repeated. 6. The master sends the first data byte (0xE0) to the command 19. The master asserts a not acknowledge on SDA and a stop register, which selects the V , V , and V channels. IN0 IN1 IN2 condition on SDA to end the conversion and exit 7. The slave asserts an acknowledge on SDA. command mode. 8. The master sends the second data byte (0x20) to the com- mand register. To change the conversion sequence, rewrite a new sequence to 9. The slave asserts an acknowledge on SDA. the command mode. If a new write to the command register is 10. The master sends the result register address (0x01). performed while an existing conversion sequence is underway, 11. The slave asserts an acknowledge on SDA. the existing conversion sequence is terminated and the next 12. The master sends the 7-bit slave address followed by the conversion performed is the first selected channel from the new write bit (high). sequence. The maximum throughput that can be achieved using 2 13. The slave (AD7291) asserts an acknowledge on SDA. this mode with a 400 kHz I C clock is (400 kHz/18) = 22.2 kSPS. 14. The master receives a data byte, which contains the channel address bits and the four MSBs of the converted result for Channel V . IN0 S SLAVE ADDRESS 0 SA POINT TO COMMAND REG (0x00) SA COMMAND = 0xE0 SA COMMAND = 0x20 SA * ... V [11:8] ... POINT TO RESULT REG (0x01) SA SR SLAVE ADDRESS 1 SA CH AD (0000) IN0 A * ... ... V [7:0] V [11:8] V [7:0] IN0 A CH AD (0001) IN1 A IN1 A * * ... V [11:8] V [7:0] V [11:8] ... CH AD (0010) IN2 A IN2 A CH ID (0000) IN0 A FROM MASTER TO SLAVE S = START CONDITION ... ........ V [7:0] V [7:0] A IN2 A P IN0 SR = REPEATED START P = STOP CONDITION FROM SLAVE TO MASTER * = POSITION OF SAMPLING START SA = SLAVE ACKNOWLEDGE A = NOT ACKNOWLEDGE Figure 28. Command Mode Operation Rev. B | Page 25 of 28 08711-016 AD7291 Data Sheet AUTOCYCLE MODE The AD7291 can be configured to convert continuously on a automatically cycles through the channel sequence starting with programmable sequence of channels, making it the ideal mode the lowest channel and working its way up through the sequence. of operation for system monitoring. This mode is useful for Once the sequence is complete, the ADC starts converting on monitoring signals, such as battery voltage and temperature, the lowest channel again, continuing to loop through the alerting only when the limits are violated. sequence until this mode is exited. Once a conversion is completed, the conversion result is compared with the content Conversions take place in the background approximately every of the limit registers, and alert status registers are automatically 50 μs, and are transparent to the master. The acquisition and updated. If a violation of the limit registers is found, the ALERT conversion times combined for any channel take approximately pin is asserted with the polarity determined by Bit D3 in the 3.6 μs. Typically, this mode is used to automatically monitor a command register. selection of channels with either the limit registers programmed to signal an out-of-range condition via the alert function or the If a command mode conversion is required while the autocycle minimum/maximum recorders tracking the variation over time mode is active, it is necessary to disable the autocycle mode of a particular channel. Reads and writes can be performed at before proceeding to the command mode. This is achieved any time (the ADC voltage conversion result register, Register by setting Bit D0 of the command register to 1. When the 0x01, contains the most recent conversion result). command mode conversion is complete, the user can reenable autocycle mode by setting Bit D0 to 1 in the command register. During power-up, this mode is disabled. To enable this mode, In autocycle mode, the AD7291 does not enter partial power- write to Bit D0 in the command register (Register 0x00) and down on receipt of a stop condition; therefore, conversions and select the desired channels for conversion by writing to the alert monitoring continue to function. corresponding channel bits (Bit D15 to Bit D8). If more than one channel bit is set in the configuration register, the ADC Rev. B | Page 26 of 28 Data Sheet AD7291 OUTLINE DIMENSIONS 4.10 0.30 4.00 SQ 0.25 3.90 0.18 PIN 1 INDICATOR 16 20 0.50 15 1 BSC EXPOSED 2.75 PAD 2.60 SQ 2.35 11 5 10 6 0.50 0.25 MIN TOP VIEW BOTTOM VIEW 0.40 0.30 0.80 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO 0.75 0.05 MAX THE PIN CONFIGURATION AND 0.70 FUNCTION DESCRIPTIONS 0.02 NOM SECTION OF THIS DATA SHEET. COPLANARITY SEATING 0.08 PLANE 0.20 REF COMPLIANT TO JEDEC STANDARDS MO-220-WGGD. Figure 29. 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 4 mm × 4 mm Body, Very Very Thin Quad (CP-20-8) Dimensions shown in millimeters ORDERING GUIDE 1 Model Temperature Range Package Description Package Option AD7291BCPZ −40°C to +125°C 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-20-8 AD7291BCPZ-RL7 −40°C to +125°C 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-20-8 EVAL-AD7291SDZ Evaluation Board 1 Z = RoHS Compliant Part. Rev. B | Page 27 of 28 PIN 1 INDICATOR 020509-B AD7291 Data Sheet NOTES 2 I C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08711-0-10/11(B) Rev. B | Page 28 of 28