ANALOG DEVICES ADA4859-3

Single-Supply, Fixed G = 2, High Speed, Video Amplifier with Charge Pump ADA4859-3 FEATURES CONNECTION DIAGRAM ADA4859-3 Integrated charge pump Supply range: 3 V to 5.5 V Output range: −3.3 V to −1.8 V 16 15 14 13 50 mA maximum output current at −3 V for external use High speed amplifiers −3 dB bandwidth: 195 MHz 12 +IN2 +V 1 S Slew rate: 740 V/μs 0.1 dB gain flatness: 60 MHz 11 –IN2 C1_a 2 CHARGE 0.1% settling time: 20 ns PUMP C1_b 3 10 OUT2 Low power CPO 4 Total quiescent current: 38 mA 9 PD Power-down feature High input common-mode voltage range 56 7 8 −1.8 V to +3.8 V at +5 V supply Current feedback architecture Differential gain error: 0.01% NOTES 1. NC = NO CONNECT. Differential phase error: 0.02° 2. EXPOSED PAD, CONNECT TO GROUND. Available in 16-lead LFCSP Figure 1. APPLICATIONS Professional video Consumer video Imaging Active filters GENERAL DESCRIPTION The ADA4859-3 (triple) is a single-supply, high speed current This triple video amplifier is designed to operate on supply feedback amplifier with an integrated charge pump that eliminates voltages of 3.3 V to 5 V, using only 38 mA total quiescent the need for negative supplies in order to output negative voltages current, including the charge pump. To further reduce the or output a 0 V level for video applications. The 195 MHz, large power consumption, it is equipped with a power-down feature signal −3 dB bandwidth at a fixed gain of 2, as well as the 740 V/μs that lowers the total supply current to as low as 2 mA when the slew rate, make this amplifier ideal for high resolution professional amplifier is not being used. Even in power-down mode, the and consumer video applications. The amplifier also has a wide charge pump can be used to power external components. The input common-mode voltage range that extends from 1.8 V maximum output current for external use is 50 mA at −3 V. below ground to 1.2 V below the positive rail at 5 V supply. The ADA4858-3 is available in a 16-lead LFCSP, and it is designed to work over the industrial temperature range of −40°C to +105°C. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. OUT1 +V S –IN1 +IN3 +IN1 –IN3 NC OUT3 07715-001 ADA4859-3 TABLE OF CONTENTS Features .............................................................................................. 1  Theory of Operation ...................................................................... 12  Applications ....................................................................................... 1  Overview ..................................................................................... 12  Connection Diagram ....................................................................... 1  Charge Pump Operation ........................................................... 12  General Description ......................................................................... 1  Applications Information .............................................................. 13  Revision History ............................................................................... 2  Using the ADA4859-3 in Gains Equal to +1, −1 ........................ 13  Specif ica t ions ..................................................................................... 3  Video Line Driver ....................................................................... 14  Absolute Maximum Ratings ............................................................ 5  Power-Down ............................................................................... 14  Maximum Power Dissipation ..................................................... 5  Layout Considerations ............................................................... 14  ESD Caution .................................................................................. 5  Power Supply Bypassing ............................................................ 14  Pin Configuration and Function Descriptions ............................. 6  Outline Dimensions ....................................................................... 15  Typical Performance Characteristics ............................................. 7  Ordering Guide .......................................................................... 15  REVISION HISTORY 11/08—Revision 0: Initial Version Rev. 0 | Page 2 of 16 ADA4859-3 SPECIFICATIONS TA = 25°C, VS = 5 V, G = 2, RF = 550 Ω, RL = 150 Ω, unless otherwise noted. Table 1. Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Bandwidth V = 0.1 V p-p 265 MHz OUT VOUT = 2 V p-p 195 MHz Bandwidth for 0.1 dB Flatness VOUT = 2 V p-p, CL = 6 pF 60 MHz Slew Rate VOUT = 2 V step 740 V/μs Settling Time to 0.1% V = 2 V step 20 ns OUT NOISE/DISTORTION PERFORMANCE Harmonic Distortion (HD2/HD3) fC = 1 MHz, VO = 2 V p-p −84/−93 dBc f = 5 MHz, V = 2 V p-p −70/−83 dBc C O Crosstalk f = 5 MHz −80 dBc Total Output Noise f = 1 MHz 17 nV/√Hz Input Current Noise f = 1 MHz 2 pA/√Hz Differential Gain Error 0.01 % Differential Phase Error 0.02 Degrees DC PERFORMANCE Output Offset Voltage −25 +9 +25 mV +Input Bias Current −2 +0.7 +2 μA Closed-Loop Gain 1.9 2 2.1 V/V INPUT CHARACTERISTICS Input Resistance +IN 15 MΩ Input Capacitance +IN 1.5 pF Input Common-Mode Voltage Range −1.8 +3.8 V OUTPUT CHARACTERISTICS Output Voltage Swing −1.4 to +3.6 −1.7 to +3.8 V Output Overdrive Recovery Time Rise/fall, f = 5 MHz 15 ns Maximum Linear Output Current @ VO = 1 VPEAK fC = 1 MHz, HD2 ≤ −50 dBc 19 mA POWER-DOWN Input Voltage Enabled 1.9 V Powered down 2 V Bias Current −0.1 +0.1 μA Turn-On Time 0.5 μs Turn-Off Time 2 μs POWER SUPPLY Operating Range 3 5.5 V Total Quiescent Current Amplifier 15 17 21 mA Charge Pump 21 mA Total Quiescent Current When Powered Down Amplifier 0.15 0.25 0.3 mA Charge Pump 4 mA Positive Power Supply Rejection Ratio Referred to output −55 −50 dB Negative Power Supply Rejection Ratio Referred to output −51 −47 dB Charge Pump Output Voltage −3.2 −3 −2.5 V Charge Pump Sink Current 150 mA Rev. 0 | Page 3 of 16 ADA4859-3 T = 25°C, V = 3.3 V, G = 2, R = 550 Ω, R = 150 Ω, unless otherwise noted. A S F L Table 2. Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Bandwidth V = 0.1 V p-p 260 MHz OUT V = 2 V p-p 165 MHz OUT Bandwidth for 0.1 dB Flatness V = 2 V p-p, C = 6 pF 65 MHz OUT L Slew Rate VOUT = 2 V step, RL = 150 Ω 530 V/μs Settling Time to 0.1% VOUT = 2 V step 20 ns NOISE/DISTORTION PERFORMANCE Total Harmonic Distortion fC = 1 MHz, VO = 2 V p-p −84/−86 dBc fC = 5 MHz, VO = 2 V p-p −73/−77 dBc Crosstalk f = 5 MHz −80 dBc Total Output Noise f = 1 MHz 17 nV/√Hz Input Current Noise f = 1 MHz 2 pA/√Hz Differential Gain Error 0.02 % Differential Phase Error 0.03 Degrees DC PERFORMANCE Output Offset Voltage −25 +9 +25 mV +Input Bias Current −2 +0.7 +2 μA Closed-Loop Gain 1.9 2 2.1 V/V INPUT CHARACTERISTICS Input Resistance +IN 15 MΩ Input Capacitance +IN 1.5 pF Input Common-Mode Voltage Range −0.9 +2.2 V OUTPUT CHARACTERISTICS Output Voltage Swing −0.7 to +2.1 −1 to +2.3 V Output Overdrive Recovery Time Rise/fall, f = 5 MHz 15 ns Maximum Linear Output Current @ V = 1 V f = 1 MHz, HD2 ≤ −50 dBc 18 mA O PEAK C POWER-DOWN Input Voltage Enabled 1.25 V Powered down 1.35 V Bias Current −0.1 +0.1 μA Turn-On Time 0.5 μs Turn-Off Time 2 μs POWER SUPPLY Operating Range 3 5.5 V Total Quiescent Current Amplifier 14 17 20 mA Charge Pump 19 mA Total Quiescent Current When Powered Down Amplifier 0.15 0.25 0.3 mA Charge Pump 2 mA Positive Power Supply Rejection Ratio Referred to output −54 −50 dB Negative Power Supply Rejection Ratio Referred to output −50 −47 dB Charge Pump Output Voltage −2.1 −2 −1.8 V Charge Pump Sink Current 45 mA Rev. 0 | Page 4 of 16 ADA4859-3 ABSOLUTE MAXIMUM RATINGS MAXIMUM POWER DISSIPATION Table 3. The maximum power that can be safely dissipated by the Parameter Rating ADA4859-3 is limited by the associated rise in junction Supply Voltage 6 V temperature. The maximum safe junction temperature 1 Internal Power Dissipation for plastic encapsulated devices is determined by the glass 16-Lead LFCSP See Figure 2 transition temperature of the plastic, approximately 150°C. Input Voltage (Common-Mode) (−VS − 0.2 V) to (+VS − 1.8 V) Temporarily exceeding this limit may cause a shift in parametric Differential Input Voltage ±VS performance due to a change in the stresses exerted on the die Output Short-Circuit Duration Observe power derating curves by the package. Exceeding a junction temperature of 175°C for Storage Temperature Range −65°C to +125°C an extended period can result in device failure. Operating Temperature Range −40°C to +105°C To ensure proper operation, it is necessary to observe the Lead Temperature 300°C (Soldering, 10 sec) maximum power derating curves in Figure 2. 2.5 1 Specification is for device in free air. Stresses above those listed under Absolute Maximum Ratings 2.0 may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational 1.5 section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect 1.0 device reliability. 0.5 0 –40 –20 0 20 40 60 80 100 AMBIENT TEMPERATURE (°C) Figure 2. Maximum Power Dissipation vs. Ambient Temperature ESD CAUTION Rev. 0 | Page 5 of 16 MAXIMUM POWER DISSIPATION (W) 07715-002 ADA4859-3 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ADA4859-3 TOP VIEW (Not to Scale) 16 15 14 13 12 +IN2 +V 1 S –IN2 11 C1_a 2 CHARGE PUMP C1_b 3 10 OUT2 CPO 4 9 PD 56 7 8 NOTES 1. NC = NO CONNECT. 2. EXPOSED PAD, CONNECT TO GROUND. Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 +V Positive Supply for Charge Pump. S 2 C1_a Charge Pump Capacitor Side a. 3 C1_b Charge Pump Capacitor Side b. 4 CPO Charge Pump Output. 5 +VS Positive Supply. 6 +IN3 Noninverting Input 3. 7 −IN3 Inverting Input 3. 8 OUT3 Output 3. 9 PD Power Down. 10 OUT2 Output 2. 11 −IN2 Inverting Input 2. 12 +IN2 Noninverting Input 2. 13 NC No Connect. 14 +IN1 Noninverting Input 1. 15 −IN1 Inverting Input 1. 16 OUT1 Output 1. 17 (EPAD) Exposed Pad (EPAD) The exposed pad must be connected to the ground plane. Rev. 0 | Page 6 of 16 OUT1 +V S –IN1 +IN3 +IN1 –IN3 NC OUT3 07715-003 ADA4859-3 TYPICAL PERFORMANCE CHARACTERISTICS VS = 5 V, G = 2, RF = 550 Ω, RL = 150 Ω, large signal VOUT = 2 V p-p, small signal VOUT = 0.1 V p-p, and T = 25ºC, unless otherwise noted. 2 2 1 1 0 0 –1 –1 –2 –2 –3 –3 –4 –4 V = 5V S –5 –5 V = 5V S –6 –6 –7 –7 V = 3.3V V = 3.3V S S –8 –8 1 10 100 1000 1 10 100 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 4. Small Signal Frequency Response vs. Supply Voltage Figure 7. Large Signal Frequency Response vs. Supply Voltage 0.2 0.2 0.1 0.1 C = 10pF 0 0 L –0.1 –0.1 C = 16pF L –0.2 –0.2 C = 10pF L –0.3 –0.3 C =14pF L –0.4 –0.4 –0.5 –0.5 –0.6 –0.6 V = 5V S –0.7 –0.7 V = 3.3V S –0.8 –0.8 1 10 100 1000 1 10 100 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 5. Large Signal 0.1 dB Flatness vs. Supply Voltage Figure 8. Large Signal 0.1 dB Flatness vs. Capacitive Load 0 0 V = 3.3V S –10 –10 –20 –20 –30 –30 –40 –40 –50 –50 HD2 HD2 –60 –60 –70 –70 HD3 –80 –80 HD3 –90 –90 –100 –100 110 100 110 100 FREQUENCY (MHz) FREQUENCY (MHz) Figure 6. Harmonic Distortion vs. Frequency Figure 9. Harmonic Distortion vs. Frequency Rev. 0 | Page 7 of 16 DISTORTION (dBc) NORMALIZED CLOSED-LOOP GAIN (dB) NORMALIZED CLOSED-LOOP GAIN (dB) 07715-005 07715-004 07715-006 NORMALIZED GAIN (dB) DISTORTION (dBc) NORMALIZED CLOSED-LOOP GAIN (dB) 07715-009 07715-007 07715-008 ADA4859-3 0 0.2 0.1 –10 C = 16pF L 0 –20 –0.1 C =10pF L –0.2 C =110pF L –30 C =14pF L –0.3 –40 –0.4 –0.5 –50 –0.6 –60 –0.7 V = 3.3V S –70 –0.8 0.1 1 10 100 400 1 10 100 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 10. Power Supply Rejection Ratio (PSRR) vs. Frequency Figure 13. Large Signal 0.1 dB Flatness vs. Capacitive Load –40 –30 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 –100 0.1 1 10 100 400 0.1 1 10 100 400 FREQUENCY (MHz) FREQUENCY (MHz) Figure 11. Forward Isolation vs. Frequency Figure 14. Crosstalk vs. Frequency 250 20 18 200 16 14 150 12 10 100 8 6 50 4 2 0 0 100 1k 10k 100k 1M 100 1k 10k 100k 1M FREQUENCY (Hz) FREQUENCY (Hz) Figure 12. Total Output Voltage Noise vs. Frequency Figure 15. Noninverting Input Current Noise vs. Frequency Rev. 0 | Page 8 of 16 FORWARD ISOLATION (dB) PSRR (dB) OUTPUT VOLTAGE NOISE (nV/ Hz) 07715-011 07715-010 07715-012 NORMALIZED GAIN (dB) CROSSTALK (dB) INPUT CURRENT NOISE (pA/ Hz) 07715-015 07715-014 07715-013 ADA4859-3 0.15 1.5 V = 200mV p-p OUT C = 10pF C = 6pF L L 0.10 1.0 C = 4pF L 0.05 0.5 0 0 –0.05 –0.5 C = 4pF L –0.10 –1.0 C = 6pF L C = 10pF L –0.15 –1.5 TIME (5ns/DIV) TIME (5ns/DIV) Figure 16. Small Signal Transient Response vs. Capacitive Load Figure 19. Large Signal Transient Response vs. Capacitive Load 0.15 1.5 2.0 V = 200mV p-p OUT V = 3.3V S 0.10 1.0 1.5 V = 5V S 0.05 0.5 1.0 0 0 0.5 –0.05 –0.5 0 V = 5V S –0.10 –1.0 –0.5 V = 3.3V S –0.15 –1.5 –1.0 TIME (5ns/DIV) TIME (5ns/DIV) Figure 17. Small Signal Transient Response vs. Supply Voltage, C = 4 pF Figure 20. Large Signal Transient Response vs. Supply Voltage, C = 4 pF L L 1100 900 V = 3.3V S 1000 800 RISE 900 700 RISE 800 600 700 FALL FALL 600 500 500 400 400 300 300 200 200 100 100 00.5 1.0 1.5 2.0 2.5 00.5 1.0 1.5 2.0 2.5 OUTPUT VOLTAGE (V p-p) OUTPUT VOLTAGE (V p-p) Figure 18. Slew Rate vs. Output Voltage Figure 21. Slew Rate vs. Output Voltage Rev. 0 | Page 9 of 16 SLEW RATE (V/µs) OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 07715-017 07715-016 07715-018 OUTPUT VOLTAGE, V = 5V (V) S SLEW RATE (V/µs) OUTPUT VOLTAGE (V) OUTPUT VOLTAGE, V = 3.3V (V) 07715-019 S 07715-021 07715-020 ADA4859-3 5 2.5 3.0 1.5 V V = 3.3V V IN S IN 2.5 4 2.0 2.0 1.0 3 1.5 1.5 2 1.0 1.0 0.5 1 0.5 0.5 0 0 0 0 –0.5 –1 –0.5 –1.0 –0.5 V OUT V –2 –1.0 OUT –1.5 –3 –1.5 –2.0 –1.0 TIME (20ns/DIV) TIME (20ns/DIV) Figure 22. Output Overdrive Recovery Figure 25. Output Overdrive Recovery 2.0 0.5 2.0 0.5 1.6 0.4 1.6 0.4 OUTPUT 1.2 0.3 1.2 0.3 0.8 0.2 0.8 0.2 ERROR 0.4 0.1 0.4 0.1 INPUT 0 0 0 0 –0.4 –0.1 –0.4 –0.1 ERROR –0.8 –0.2 –0.8 –0.2 INPUT –1.2 –0.3 –1.2 –0.3 OUTPUT –1.6 –0.4 –1.6 –0.4 –2.0 –0.5 –2.0 –0.5 –5 0 5 10 15 20 25 30 35 40 –5 0 5 10 15 20 25 30 35 40 TIME (ns) TIME (ns) Figure 23. Settling Time (Rise) Figure 26. Settling Time, (Fall) 0 24 1.5 6 V –0.4 22 PD 1.0 5 CHARGE PUMP CURRENT V OUT –0.8 20 0.5 4 –1.2 18 –1.6 16 0 3 AMPLIFIER CURRENT –2.0 14 –0.5 2 –2.4 12 OUTPUT –1.0 1 –2.8 VOLTAGE 10 –3.2 8 –1.5 0 2.5 3.0 3.5 4.0 4.5 5.0 TIME (400ns/DIV) CHARGE PUMP SUPPLY VOLTAGE (V) Figure 24. Charge Pump Voltage and Current vs. Supply Voltage Figure 27. Enable/Power-Down Time Rev. 0 | Page 10 of 16 CHARGE PUMP OUTPUT VOLTAGE (V) AMPLITUDE (V) OUTPUT VOLTAGE (V) INPUT VOLTAGE (V) CURRENT (mA) ERROR (%) 07715-022 07715-024 07715-023 AMPLITUDE (V) OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) POWER-DOWN VOLTAGE (V) INPUT VOLTAGE (V) ERROR (%) 07715-027 07715-025 07715-026 ADA4859-3 –100 –100 V = 3.3V CHARGE PUMP HARMONICS CHARGE PUMP HARMONICS S –105 –105 –110 –110 –115 –115 –120 –120 –125 –125 –130 –130 –135 –135 –140 –140 –145 –145 –150 –150 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 FREQUENCY (MHz) FREQUENCY (MHz) Figure 29. Output Spectrum vs. Frequency Figure 28. Output Spectrum vs. Frequency Rev. 0 | Page 11 of 16 POWER (dBm) 07715-100 POWER (dBm) 07715-101 ADA4859-3 THEORY OF OPERATION Φ 1 a OVERVIEW +V S C1 The ADA4859-3 is a fixed gain of two, current feedback amplifier CPO designed for exceptional performance as a triple video amplifier. Its Φ b 1 C2 specifications make it especially suitable for SD and HD video applications. The ADA4859-3 provides HD video output on a Figure 30. Charging Cycle single supply as low as 3.0 V while only consuming 13 mA per Φ a 2 amplifier. It also features a power-down pin (PD) that reduces +V S C1 the quiescent current to 4 mA when activated. CPO Φ 2 b The ADA4859-3 can be used in applications that require both C2 ac- and dc-coupled inputs and outputs. The output stage on the ADA4859-3 is capable of driving 2 V p-p video signals into two Figure 31. Discharging Cycle doubly terminated video loads (150 Ω each) on a single 5 V supply. The ADA4859-3 specifications make it especially suitable for SD The input range of the ADA4859-3 includes ground, whereas and HD video applications. It also allows dc-coupled video signal the output range is limited by the output headroom set by the with its black level set to 0 V and its sync tip down to −300 mV voltage drop across two diodes from each rail, which occurs for YPbPr video. 1.2 V from the positive and negative supply rails. The charge pump is always on, even when the power-down pin CHARGE PUMP OPERATION (PD) is enabled and the amplifier is off. However, it would be in The on-board charge pump creates a negative supply for the an idle state if the negative current were not used. Each amplifier amplifier. It provides different negative voltages depending on needs −6.3 mA of current, which totals −19 mA for all three the power supply voltage. For a +5 V supply, the negative supply amplifiers. This means additional negative current may be available generated is equal to −3 V with 150 mA of output supply current, by the charge pump for external use. Pin 4 (CPO) is the charge and for a +3.3 V supply, the negative supply is equal to −2 V pump output, which provides access to the negative supply with 45 mA of output supply current. generated by the charge pump. Placing a 1 μF charge capacitor at the CPO pin is essential to hold the charge and regulate the ripple. Figure 30 shows the charging cycle when the supply voltage, +VS, charges C1 through Φ1 to ground. During this cycle, C1 If the negative supply is used to power another device in the quickly charges to reach the +VS voltage. The discharge cycle then system, it is only possible for the 5 V supply operation. In the begins with switching Φ1 off and switching Φ2 on, as shown in 3.3 V supply operation, the charge pump output current is very Figure 31. When C1 = C2, the charge in C1 is divided between limited. The capacitor at the CPO pin, which regulates the ripple the two capacitors and slowly increases the voltage in C2 until it of the negative voltage, can be used as a coupling capacitor for the reaches a predetermined voltage (−3 V for the +5 V supply and external device. However, the charge pump current should be −2 V limited to a maximum of 50 mA for external use. When powering for the +3.3 V supply). The typical charge pump charging and down the ADA4859-3, the charge pump is not affected and its discharging frequency is 550 kHz with a 150 Ω load and no input output voltage and current remain available for external use. signal. This frequency changes with the load current, and it can get much slower if the amplifier is powered down and no external current is used. Rev. 0 | Page 12 of 16 07715-137 07715-138 ADA4859-3 APPLICATIONS INFORMATION +V S USING THE ADA4859-3 IN GAINS EQUAL TO +1, −1 10µF The ADA4859-3 was designed to offer outstanding video performance, simplify applications, and minimize board area. 0.1µF R The ADA4859-3 is a triple amplifier with on-chip feedback F R G and gain set resistors. The gain is fixed internally at G = +2. The V inclusion of the on-chip resistors not only simplifies the design OUT V IN of the application but also eliminates six surface-mount resistors, R T saving valuable board space and lowering assembly costs. GAIN OF +1 Although the ADA4859-3 has a fixed gain of G = +2, it can be Figure 33. Unity Gain of Option 2 used in other gain configurations, such as G = −1 and G = +1. Inverting Unity-Gain Operation Unity-Gain Operation In this configuration, the noninverting input is tied to ground Option 1 and the input signal is applied to the inverting input. The noise There are two options for obtaining unity gain (G = +1). The gain for this configuration is +2, see Figure 34. first is shown in Figure 32. In this configuration, the −IN input +V S pin is tied to the output. (Feedback is provided through the two 10µF internal 550 Ω resistors in parallel), and the input is applied to the noninverting input. The noise gain for this configuration is 1. 0.01µF +V S 10µF V IN V R OUT T 0.1µF GAIN OF –1 Figure 34. Inverting Configuration (G = −1) V OUT V IN Figure 35 shows the small signal frequency response for both R T gain of +1 (Option 1 and Option 2) and gain of −1 configurations. GAIN OF +1 It is clear that the G = +1 Option 2 has better flatness and no Figure 32. Unity Gain of Option 1 peaking compared to Option 1. 3 Option 2 G = +1, OPTION 1 Another option exists for running the ADA4859-3 as a unity- gain amplifier. In this configuration, the noise gain is +2, see 0 Figure 33. The frequency response and transient response for G = +1, this configuration closely match the gain of +2 plots because the OPTION 2 noise gains are equal. This method does have twice the noise –3 gain of Option 1; however, in applications that do not require low G = –1 noise, Option 2 offers less peaking and ringing. By tying the inputs together, the net gain of the amplifier becomes +1. Equation 1 –6 shows the transfer characteristic for the schematic shown in V = 5V S Figure 33. V = 2V p-p OUT R = 100Ω L –9 ⎛ ⎞ ⎛R +R ⎞ −R 1 10 100 1000 F F G ⎜ ⎟ ⎜ ⎟ V =V +V (1) OUT IN IN FREQUENCY (MHz) ⎜ ⎟ ⎜ ⎟ R R G G ⎝ ⎠ ⎝ ⎠ Figure 35. Large Signal, G = +1 and G = −1 which simplifies to VOUT = VIN. Rev. 0 | Page 13 of 16 07715-130 CLOSED-LOOP GAIN (dB) 07715-131 07715-132 07715-031 ADA4859-3 VIDEO LINE DRIVER POWER-DOWN The ADA4859-3 was designed to excel in video driver applications. The ADA4859-3 is equipped with a PD (power-down) pin for Figure 36 shows a typical schematic for a video driver operating all three amplifiers. This allows the user the ability to reduce on bipolar supplies. the quiescent supply current when an amplifier is not active. The power-down threshold levels are derived from ground V (R) IN 75Ω 75Ω level. The amplifiers are powered down when the voltage V (R) OUT applied to the PD pin is greater than a certain voltage from 16 15 14 13 ground. In a 5 V supply application, the voltage is greater than 2 V, and in a 3.3 V supply application, the voltage is greater than 1.5 V. 12 1 V (G) The amplifier is enabled whenever the PD pin is left floating IN 75Ω (not connected). If the PD pin is not used, it is best to leave it 11 2 floating or connected to ground. Note that the power-down feature CHARGE 1µF 3 10 75Ω PUMP does not control the charge pump output voltage and current. V (G) OUT 4 9 Table 5. Power-Down Voltage Control PD 1µF PD Pin 5 V 3.3 V Not Active <1.5 V <1 V +V S 56 7 8 Active >2 V >1.5 V + 10µF 0.1µF 75Ω V (B) V (B) IN OUT 75Ω LAYOUT CONSIDERATIONS As is the case with all high speed applications, careful attention Figure 36. Video Driver Schematic to printed circuit board (PCB) layout details prevents associated In applications that require multiple video loads be driven board parasitics from becoming problematic. Proper RF design simultaneously, the ADA4859-3 can deliver. Figure 37 shows technique is mandatory. The PCB should have a ground plane the ADA4856-3 configured with two video loads, and Figure 38 covering all unused portions of the component side of the board to shows the large signal performance for multiple video loads. provide a low impedance return path. Removing the ground plane on all layers from the area near the input and output pins 75Ω reduces stray capacitance. Locate termination resistors and loads as +V S CABLE 10µF 75Ω close as possible to their respective inputs and outputs. Keep V 1 OUT 75Ω input and output traces as far apart as possible to minimize 0.1µF 75Ω coupling (crosstalk) through the board. Adherence to – CABLE 75Ω microstrip or stripline design techniques for long signal traces 75Ω V 2 OUT CABLE (greater than about 1 inch) is recommended. 75Ω V + IN 75Ω POWER SUPPLY BYPASSING Careful attention must be paid to bypassing the power supply Figure 37. Video Driver Schematic for Two Video Loads pins of the ADA4859-3. Use high quality capacitors with low equivalent series resistance (ESR), such as multilayer ceramic 6.5 capacitors (MLCCs), to minimize supply voltage ripple and power dissipation. A large, usually tantalum, 10 μF to 47 μF 6.0 capacitor located in proximity to the ADA4859-3 is required to 5.5 provide good decoupling for lower frequency signals. In addition, locate 0.1 μF MLCC decoupling capacitors as close to 5.0 R = 150Ω L each of the power supply pins as is physically possible, no more 4.5 than 1/8-inch away. The ground returns should terminate R = 75Ω L immediately into the ground plane. Locating the bypass capacitor 4.0 return close to the load return minimizes ground loops and 3.5 improves performance. 3.0 2.5 1 10 100 1000 FREQUENCY (MHz) Figure 38. Large Signal Frequency Response for Various Loads Rev. 0 | Page 14 of 16 CLOSED-LOOP GAIN (dB) 07715-034 07715-134 07715-135 2.25 2.10 SQ 1.95 ADA4859-3 OUTLINE DIMENSIONS 4.00 0.60 MAX BSC SQ (BOTTOM VIEW) 0.60 MAX PIN 1 INDICATOR 13 16 1 12 PIN 1 0.65 BSC INDICATOR TOP 3.75 VIEW BSC SQ 0.75 9 0.60 4 8 5 0.50 0.25 MIN 0.80 MAX 12° MAX 1.95 BSC 0.65 TYP 0.05 MAX FOR PROPER CONNECTION OF 1.00 0.02 NOM THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND 0.85 0.35 FUNCTION DESCRIPTIONS 0.80 0.20 REF 0.30 COPLANARITY SECTION OF THIS DATA SHEET. SEATING 0.08 0.25 PLANE COMPLIANT TO JEDEC STANDARDS MO-220-VGGC Figure 39.16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm × 4 mm Body, Very Thin Quad (CP-16-4) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option Ordering Quantity 1 ADA4859-3ACPZ-R2 –40°C to +105°C 16-Lead LFCSP_VQ CP-16-4 250 1 ADA4859-3ACPZ-R7 –40°C to +105°C 16-Lead LFCSP_VQ CP-16-4 1,500 1 ADA4859-3ACPZ-RL –40°C to +105°C 16-Lead LFCSP_VQ CP-16-4 5,000 1 Z = RoHS Compliant Part. Rev. 0 | Page 15 of 16 072808-A ADA4859-3 NOTES ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07715-0-11/08(0) Rev. 0 | Page 16 of 16