ANALOG DEVICES ADA4858-3

Single-Supply, High Speed, Triple Op Amp with Charge Pump ADA4858-3 FEATURES CONNECTION DIAGRAM ADA4858-3 Integrated charge pump Supply range: 3 V to 5.5 V Output range: −3.3 V to −1.8 V 16 15 14 13 50 mA maximum output current for external use at −3 V High speed amplifiers 12 +IN2 +V 1 S −3 dB bandwidth: 600 MHz 11 –IN2 C1_a 2 CHARGE Slew rate: 600 V/μs PUMP 3 C1_b 10 OUT2 0.1 dB flatness: 85 MHz CPO 4 9 PD 0.1% settling time: 18 ns Low power 56 7 8 Total quiescent current: 42 mA Power-down feature NOTES High input common-mode voltage range 1. NC = NO CONNECT. 2. EXPOSED PAD, CONNECT TO GROUND. −1.8 V to +3.8 V at +5 V supply Figure 1. Current feedback architecture Differential gain error: 0.01% Differential phase error: 0.02° Available in 16-lead LFCSP APPLICATIONS Professional video Consumer video Imaging Active filters GENERAL DESCRIPTION The ADA4858-3 (triple) is a single-supply, high speed current This triple operational amplifier is designed to operate on feedback amplifier with an integrated charge pump that eliminates supply voltages of 3.3 V to 5 V, using only 42 mA of total the need for negative supplies to output negative voltages or output quiescent current, including the charge pump. To further a 0 V level for video applications. The 600 MHz, −3 dB bandwidth reduce the power consumption, it is equipped with a power- and 600 V/μs slew rate make this amplifier well suited for many down feature that lowers the total supply current to as low as high speed applications. In addition, its 0.1 dB flatness out to 2.5 mA when the amplifier is not being used. Even in power- 85 MHz at G = 2, along with its differential gain and phase errors down mode, the charge pump can be used to power external of 0.01% and 0.02° into a 150 Ω load, make it well suited for components. The maximum output current for external use is professional and consumer video applications. 50 mA at −3 V. The amplifier also has a wide input common- mode voltage range that extends from 1.8 V below ground to 1.2 V below the positive rail at a 5 V supply. The ADA4858-3 is available in a 16-lead LFCSP, and it is designed to work over the extended industrial temperature range of −40°C to +105°C. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2008–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. OUT1 +V S +IN3 –IN1 +IN1 –IN3 NC OUT3 07714-001 ADA4858-3 TABLE OF CONTENTS Features .............................................................................................. 1  Applications Information .............................................................. 14  Applications ....................................................................................... 1  Gain Configurations .................................................................. 14  Connection Diagram ....................................................................... 1  DC-Coupled Video Signal ........................................................ 14  General Description ......................................................................... 1  Multiple Video Driver ................................................................ 14  Revision History ............................................................................... 2  DC Restore Function ................................................................. 15  Specif ica t ions ..................................................................................... 3  Clamp Amplifier ......................................................................... 15  Absolute Maximum Ratings ............................................................ 5  PD (Power-Down) Pin .............................................................. 16  Maximum Power Dissipation ..................................................... 5  Power Supply Bypassing ............................................................ 16  ESD Caution .................................................................................. 5  Layout .......................................................................................... 16  Pin Configuration and Function Descriptions ............................. 6  Outline Dimensions ....................................................................... 17  Typical Performance Characteristics ............................................. 7  Ordering Guide .......................................................................... 17  Theory of Operation ...................................................................... 13  Overview ...................................................................................... 13  Charge Pump Operation ........................................................... 13  REVISION HISTORY 5/09—Rev. 0 to Rev. A Changes to Overview Section and Charge Pump Operation Section .............................................................................................. 13 Changes to Table 5 and Figure 41 ................................................. 14 Added DC Restore Function Section, Figure 43, Clamp Amplifier Section, and Figure 44 .................................................. 15 10/08—Revision 0: Initial Version Rev. A | Page 2 of 20 ADA4858-3 SPECIFICATIONS TA = 25°C, VS = 5 V, G = 2, RF = 301 Ω, RF = 402 Ω for G = 1, RL = 150 Ω, unless otherwise noted. Table 1. Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Bandwidth V = 0.1 V p-p, G = 1 600 MHz OUT VOUT = 0.1 V p-p 350 MHz VOUT = 2 V p-p, G = 1 165 MHz VOUT = 2 V p-p 175 MHz Bandwidth for 0.1 dB Flatness V = 2 V p-p 85 MHz OUT Slew Rate V = 2 V step 600 V/μs OUT Settling Time to 0.1% V = 2 V step 18 ns OUT NOISE/DISTORTION PERFORMANCE Harmonic Distortion (HD2/HD3) f = 1 MHz, V = 2 V p-p −86/−94 dBc C OUT fC = 5 MHz, VOUT = 2 V p-p −71/−84 dBc Crosstalk f = 5 MHz −60 dB Input Voltage Noise f = 1 MHz 4 nV/√Hz Input Current Noise f = 1 MHz (+IN/−IN) 2/9 pA/√Hz Differential Gain Error 0.01 % Differential Phase Error 0.02 Degrees DC PERFORMANCE Input Offset Voltage −14 +0.5 +14 mV + Input Bias Current −2 +0.7 +2 μA − Input Bias Current −13 +8 +13 μA Open-Loop Transimpedance 300 390 kΩ INPUT CHARACTERISTICS Input Resistance +IN1/+IN2 15 MΩ −IN1/−IN2 90 Ω Input Capacitance +IN1/+IN2 1.5 pF Input Common-Mode Voltage Range Typical −1.8 +3.8 V Common-Mode Rejection Ratio −61 −54 dB OUTPUT CHARACTERISTICS Output Voltage Swing −1.4 to +3.6 −1.7 to +3.7 V Output Overdrive Recovery Time Rise/fall, f = 5 MHz 15 ns Maximum Linear Output Current @ VOUT = 1 VPEAK fC = 1 MHz, HD2 ≤ −50 dBc 21 mA POWER-DOWN Input Voltage Enabled 1.9 V Powered down 2 V Bias Current −0.1 +0.1 μA Turn-On Time 0.3 μs Turn-Off Time 1.6 μs POWER SUPPLY Operating Range 3 5.5 V Total Quiescent Current Amplifiers 15 19 21 mA Charge Pump 23 mA Total Quiescent Current When Powered Down Amplifiers 0.15 0.25 0.3 mA Charge Pump 4 mA Positive Power Supply Rejection Ratio −64 −60 dB Negative Power Supply Rejection Ratio −58 −54 dB Charge Pump Output Voltage −3.3 −3 −2.5 V Charge Pump Sink Current 150 mA Rev. A | Page 3 of 20 ADA4858-3 T = 25°C, V = 3.3 V, G = 2, R = 301 Ω, R = 402 Ω for G = 1, R = 150 Ω, unless otherwise noted. A S F F L Table 2. Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Bandwidth V = 0.1 V p-p, G = 1 540 MHz OUT V = 0.1 V p-p 340 MHz OUT V = 2 V p-p, G = 1 140 MHz OUT VOUT = 2 V p-p 145 MHz Bandwidth for 0.1 dB Flatness VOUT = 2 V p-p 70 MHz Slew Rate VOUT = 2 V step 430 V/μs Settling Time to 0.1% V = 2 V step 20 ns OUT NOISE/DISTORTION PERFORMANCE Harmonic Distortion (HD2/HD3) fC = 1 MHz, VOUT = 2 V p-p −88/−91 dBc f = 5 MHz, V = 2 V p-p −75/−78 dBc C OUT Crosstalk f = 5 MHz −60 dB Input Voltage Noise f = 1 MHz 4 nV/√Hz Input Current Noise f = 1 MHz (+IN/−IN) 2/9 pA/√Hz Differential Gain Error 0.02 % Differential Phase Error 0.03 Degrees DC PERFORMANCE Input Offset Voltage −14 +0.7 +14 mV + Input Bias Current −2 +0.6 +2 μA − Input Bias Current −13 +7 +13 μA Open-Loop Transimpedance 300 350 kΩ INPUT CHARACTERISTICS Input Resistance +IN1/+IN2 15 MΩ −IN1/−IN2 90 Ω Input Capacitance +IN1/+IN2 1.5 pF Input Common-Mode Voltage Range Typical −0.9 +2.2 V Common-Mode Rejection Ratio −60 −54 dB OUTPUT CHARACTERISTICS Output Voltage Swing −0.6 to +2.1 −0.9 to +2.2 V Output Overdrive Recovery Time Rise/fall, f = 5 MHz 15 ns Maximum Linear Output Current @ V = 1 V f = 1 MHz, HD2 ≤ −50 dBc 20 mA OUT PEAK C POWER-DOWN Input Voltage Enabled 1.25 V Powered down 1.35 V Bias Current −0.1 +0.1 μA Turn-On Time 0.3 μs Turn-Off Time 1.6 μs POWER SUPPLY Operating Range 3 5.5 V Total Quiescent Current Amplifiers 14 19 20 mA Charge Pump 21 mA Total Quiescent Current When Powered Down Amplifiers 0.15 0.25 0.3 mA Charge Pump 2 mA Positive Power Supply Rejection Ratio −63 −60 dB Negative Power Supply Rejection Ratio −57 −54 dB Charge Pump Output Voltage −2.1 −2 −1.8 V Charge Pump Sink Current 45 mA Rev. A | Page 4 of 20 ADA4858-3 ABSOLUTE MAXIMUM RATINGS MAXIMUM POWER DISSIPATION Table 3. The maximum power that can be safely dissipated by the Parameter Rating ADA4858-3 is limited by the associated rise in junction Supply Voltage 6 V temperature. The maximum safe junction temperature for 1 Internal Power Dissipation plastic encapsulated devices is determined by the glass transition 16-Lead LFCSP See Figure 2 temperature of the plastic, approximately 150°C. Temporarily Input Voltage (Common Mode) (−VS − 0.2 V) to (+VS − 1.2 V) exceeding this limit may cause a shift in parametric performance Differential Input Voltage ±VS due to a change in the stresses exerted on the die by the package. Output Short-Circuit Duration Observe power derating curves Exceeding a junction temperature of 175°C for an extended Storage Temperature Range −65°C to +125°C period can result in device failure. Operating Temperature Range −40°C to +105°C To ensure proper operation, it is necessary to observe the Lead Temperature 300°C (Soldering, 10 sec) maximum power derating curves in Figure 2. 2.5 1 Specification is for device in free air. Stresses above those listed under Absolute Maximum Ratings 2.0 may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational 1.5 section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect 1.0 device reliability. 0.5 0 –40 –20 0 20 40 60 80 100 AMBIENT TEMPERATURE (°C) Figure 2. Maximum Power Dissipation vs. Ambient Temperature ESD CAUTION Rev. A | Page 5 of 20 MAXIMUM POWER DISSIPATION (W) 07714-002 ADA4858-3 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ADA4858-3 TOP VIEW (Not to Scale) 16 15 14 13 12 +IN2 +V 1 S 11 –IN2 C1_a 2 CHARGE PUMP C1_b 3 10 OUT2 CPO 4 PD 9 56 7 8 NOTES 1. NC = NO CONNECT. 2. EXPOSED PAD, CONNECT TO GROUND. Figure 3. Pin Configuration. Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 +V Positive Supply for Charge Pump. S 2 C1_a Charge Pump Capacitor Side a. 3 C1_b Charge Pump Capacitor Side b. 4 CPO Charge Pump Output. 5 +V Positive Supply. S 6 +IN3 Noninverting Input 3. 7 −IN3 Inverting Input 3. 8 OUT3 Output 3. 9 PD Power-Down. 10 OUT2 Output 2. 11 −IN2 Inverting Input 2. 12 +IN2 Noninverting Input 2. 13 NC No Connect. 14 +IN1 Noninverting Input 1. 15 −IN1 Inverting Input 1. 16 OUT1 Output 1. EPAD Exposed Pad (EPAD) The exposed pad must be connected to ground. Rev. A | Page 6 of 20 +V OUT1 S –IN1 +IN3 –IN3 +IN1 OUT3 NC 07714-003 ADA4858-3 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VS = 5 V, G = 2, RF = 301 Ω, RF = 402 Ω for G = 1, RF = 200 Ω for G = 5, RL = 150 Ω, large signal VOUT = 2 V p-p, and small signal VOUT = 0.1 V p-p, unless otherwise noted. 2 2 G = 1 1 1 G = 1 0 0 G = 2 –1 –1 G = 2 –2 –2 G = 5 G = 5 –3 –3 –4 –4 –5 –5 –6 –6 –7 –7 –8 –8 1 10 100 1000 1 10 100 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 4. Small Signal Frequency Response vs. Gain Figure 7. Large Signal Frequency Response vs. Gain 2 2 V = 3.3V V = 3.3V S S 1 1 G = 1 G = 1 G = 2 0 0 –1 –1 G = 2 –2 –2 G = 5 G = 5 –3 –3 –4 –4 –5 –5 –6 –6 –7 –7 –8 –8 1 10 100 1000 1 10 100 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 5. Small Signal Frequency Response vs. Gain Figure 8. Large Signal Frequency Response vs. Gain 2 2 1 1 R = 301Ω R = 200Ω F R = 200Ω F F 0 0 R = 301Ω F –1 –1 R = 402Ω F R = 402Ω F –2 –2 R = 499Ω F R = 499Ω F –3 –3 –4 –4 –5 –5 –6 –6 –7 –7 –8 –8 1 10 100 1000 1 10 100 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 6. Small Signal Frequency Response vs. Feedback Resistor Figure 9. Large Signal Frequency Response vs. Feedback Resistor Rev. A | Page 7 of 20 NORMALIZED CLOSED-LOOP GAIN (dB) NORMALIZED CLOSED-LOOP GAIN (dB) NORMALIZED CLOSED-LOOP GAIN (dB) 07714-006 07714-005 07714-004 NORMALIZED CLOSED-LOOP GAIN (dB) NORMALIZED CLOSED-LOOP GAIN (dB) NORMALIZED CLOSED-LOOP GAIN (dB) 07714-009 07714-008 07714-007 ADA4858-3 0.2 0.2 R = 200Ω F 0.1 0.1 0 0 V = 5V S –0.1 –0.1 R = 301Ω F –0.2 –0.2 V = 3.3V S –0.3 –0.3 –0.4 –0.4 –0.5 –0.5 –0.6 –0.6 –0.7 –0.7 –0.8 –0.8 1 10 100 1000 1 10 100 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 10. Large Signal 0.1 dB Flatness vs. Supply Voltage Figure 13. Large Signal 0.1 dB Flatness vs. Feedback Resistor 0 0 –10 –10 –20 –20 –30 –30 –40 –40 –50 –50 –60 HD2 –60 HD2 –70 –70 HD3 HD3 –80 –80 –90 –90 –100 –100 110 100 110 100 FREQUENCY (MHz) FREQUENCY (MHz) Figure 11. Harmonic Distortion vs. Frequency Figure 14. Harmonic Distortion vs. Frequency, VS = 3.3 V 10 –10 0 –20 –10 –30 –20 –30 –40 –40 –50 –50 –60 –60 –70 –70 0.1 1 10 100 400 0.1 1 10 100 400 FREQUENCY (MHz) FREQUENCY (MHz) Figure 12. Power Supply Rejection Ratio (PSRR) vs. Frequency Figure 15. Common-Mode Rejection Ratio (CMRR) vs. Frequency Rev. A | Page 8 of 20 NORMALIZED CLOSED-LOOP GAIN (dB) PSRR (dB) DISTORTION (dBc) 07714-012 07714-011 07714-010 NORMALIZED CLOSED-LOOP GAIN (dB) CMRR (dB) DISTORTION (dBc) 07714-015 07714-014 07714-013 ADA4858-3 –30 –20 –40 –30 –50 –40 –60 –50 –70 –60 –80 –70 –90 –80 –100 –90 0.1 1 10 100 400 0.1 1 10 100 400 FREQUENCY (MHz) FREQUENCY (MHz) Figure 16. Forward Isolation vs. Frequency Figure 19. Crosstalk vs. Frequency 0.15 1.5 2.0 V = 200mV p-p OUT 1.0 1.5 0.10 0.05 0.5 1.0 0 0.5 0 –0.5 0 –0.05 V = 3.3V S V = 5V S –1.0 –0.5 –0.10 V = 5V S V = 3.3V S –1.5 –1.0 –0.15 TIME (5ns/DIV) TIME (5ns/DIV) Figure 20. Large Signal Transient Response vs. Supply Voltage Figure 17. Small Signal Transient Response vs. Supply Voltage 1.5 0.15 G = 1 C = 4pF L C = 10pF L V = 200mV p-p OUT 1.0 0.10 C = 6pF L 0.5 0.05 0 0 –0.5 –0.05 C = 4pF L –1.0 –0.10 G = 1 C = 6pF C = 10pF L L –1.5 –0.15 TIME (5ns/DIV) TIME (5ns/DIV) Figure 21. Large Signal Transient Response vs. Capacitive Load Figure 18. Small Signal Transient Response vs. Capacitive Load Rev. A | Page 9 of 20 FORWARD ISOLATION (dB) OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 07714-018 07714-017 07714-016 OUTPUT VOLTAGE, V = 5V (V) S CROSSTALK (dB) OUTPUT VOLTAGE (V) 07714-021 OUTPUT VOLTAGE, V = 3.3V (V) S 07714-019 07714-020 ADA4858-3 0.15 1.5 C = 10pF C = 10pF L L C = 16pF C = 6pF L L 0.10 1.0 C = 4pF L C = 14pF L 0.05 0.5 0 0 –0.05 –0.5 –0.10 –1.0 V = 200mV p-p OUT –0.15 –1.5 TIME (5ns/DIV) TIME (5ns/DIV) Figure 22. Small Signal Transient Response vs. Capacitive Load Figure 25. Large Signal Transient Response vs. Capacitive Load 2.0 0.5 2.0 0.5 1.6 0.4 1.6 0.4 OUTPUT 1.2 0.3 1.2 0.3 ERROR 0.8 0.2 0.8 0.2 INPUT 0.4 0.1 0.4 0.1 0 0 0 0 –0.4 –0.1 –0.4 –0.1 ERROR –0.8 –0.2 –0.8 INPUT –0.2 –1.2 –0.3 –1.2 –0.3 OUTPUT –1.6 –0.4 –1.6 –0.4 –2.0 –0.5 –2.0 –0.5 –5 0 5 10 15 20 25 30 35 40 –5 0 5 10 15 20 25 30 35 40 TIME (ns) TIME (ns) Figure 23. Settling Time (Rise) Figure 26. Settling Time (Fall) 5 2.5 3.0 1.5 V V V = 3.3V IN S IN 2.5 4 2.0 2.0 1.0 1.5 3 V V OUT OUT 1.5 2 1.0 1.0 0.5 1 0.5 0.5 0 0 0 0 –0.5 –1 –0.5 –0.5 –1.0 –2 –1.0 –1.5 –3 –1.5 –2.0 –1.0 TIME (20ns/DIV) TIME (20ns/DIV) Figure 24. Output Overdrive Recovery Figure 27. Output Overdrive Recovery, VS = 3.3 V Rev. A | Page 10 of 20 OUTPUT VOLTAGE (V) AMPLITUDE (V) OUTPUT VOLTAGE (V) 07714-022 ERROR (%) INPUT VOLTAGE (V) 07714-023 07714-024 OUTPUT VOLTAGE (V) AMPLITUDE (V) OUTPUT VOLTAGE (V) 07714-025 ERROR (%) INPUT VOLTAGE (V) 07714-026 07714-027 ADA4858-3 1000 1000 RISE, G = 2 V = 3.3V S 900 900 RISE, G = 1 800 800 RISE, G = 2 700 700 FALL, G = 2 RISE, G = 1 600 600 FALL, G = 1 500 500 FALL, G = 2 400 400 FALL, G = 1 300 300 200 200 100 100 0 0 0 0.5 1.0 1.5 2.0 2.5 0 0.5 1.0 1.5 2.0 2.5 OUTPUT VOLTAGE (V p-p) OUTPUT VOLTAGE (V p-p) Figure 28. Slew Rate vs. Output Voltage Figure 31. Slew Rate vs. Output Voltage, VS = 3.3 V 0 24 1.5 6 CHARGE PUMP CURRENT V PD –0.4 22 1.0 5 V OUT –0.8 20 0.5 4 –1.2 18 AMPLIFIER CURRENT –1.6 16 0 3 –2.0 14 –0.5 2 –2.4 12 OUTPUT –1.0 1 VOLTAGE –2.8 10 –3.2 8 –1.5 0 2.5 3.0 3.5 4.0 4.5 5.0 TIME (400ns/DIV) CHARGE PUMP SUPPLY VOLTAGE (V) Figure 29. Charge Pump Output Voltage and Current vs. Figure 32. Enable/Power-Down Time Charge Pump Supply Voltage 20 100 18 90 16 80 14 70 12 60 10 50 8 40 6 30 4 20 –IN 2 10 +IN 0 0 100 1k 10k 100k 1M 100 1k 10k 100k 1M FREQUENCY (Hz) FREQUENCY (Hz) Figure 30. Input Voltage Noise vs. Frequency Figure 33. Input Current Noise vs. Frequency Rev. A | Page 11 of 20 CHARGE PUMP OUTPUT VOLTAGE (V) INPUT VOLTAGE NOISE (nV/ Hz) SLEW RATE (V/µs) CURRENT (mA) 07714-028 07714-030 07714-029 OUTPUT VOLTAGE (V) INPUT CURRENT NOISE (pA/ Hz) SLEW RATE (V/µs) POWER-DOWN VOLTAGE (V) 07714-031 07714-033 07714-032 ADA4858-3 –100 –100 V = 3.3V CHARGE PUMP HARMONICS CHARGE PUMP HARMONICS S –105 –105 –110 –110 –115 –115 –120 –120 –125 –125 –130 –130 –135 –135 –140 –140 –145 –145 –150 –150 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 FREQUENCY (MHz) FREQUENCY (MHz) Figure 34. Output Spectrum vs. Frequency Figure 35. Output Spectrum vs. Frequency, VS = 3.3 V Rev. A | Page 12 of 20 POWER (dBm) 07714-201 POWER (dBm) 07714-202 ADA4858-3 THEORY OF OPERATION Φ a 2 OVERVIEW +V S C1 The ADA4858-3 is a current feedback amplifier designed for CPO Φ exceptional performance as a triple amplifier with a variable 2 b C2 gain capability. Its specifications make it especially suitable for SD and HD video applications. The ADA4858-3 provides Figure 37. C1 Discharging Cycle HD video output on a single supply as low as 3.0 V while only The ADA4858-3 specifications make it especially suitable for SD consuming 13 mA per amplifier. It also features a power-down and HD video applications. It also allows dc-coupled video signals pin (PD) that reduces the total quiescent current to 2 mA when with its black level set to 0 V and its sync tip at −300 mV for activated. YPbPr video. The ADA4858-3 can be used in applications that require both The charge pump is always on, even when the power-down pin ac- and dc-coupled inputs and outputs. The output stage on the (PD) is enabled and the amplifiers are off. However, if a negative ADA4858-3 is capable of driving 2 V p-p video signals into two current is not used, the charge pump is in an idle state. Each doubly terminated video loads (150 Ω each) on a single 5 V supply. amplifier needs −6.3 mA of current, which totals −19 mA for all The input range of the ADA4858-3 includes ground, and the three amplifiers. This means additional negative current may be output range is limited by the output headroom set by the voltage available by the charge pump for external use. Pin 4 (CPO) is drop across the two diodes from each rail, which occurs 1.2 V the charge pump output that provides access to the negative from the positive supply and the charge pump negative supply rails. supply generated by the charge pump. CHARGE PUMP OPERATION If the negative supply is used to power another device in the The on-board charge pump creates a negative supply for the system, it is only possible for the 5 V supply operation. In the amplifier. It provides different negative voltages depending on 3.3 V supply operation, the charge pump output current is very the power supply voltage. For a +5 V supply, the negative supply limited. The capacitor C2 placed at the CPO pin, which generated is equal to −3 V with 150 mA of output supply current, regulates the ripple of the negative voltage, can be used as a and for a +3.3 V supply, the negative supply is equal to −2 V coupling capacitor for the external device. However, the charge with 45 mA of output supply current. pump current should be limited to a maximum of 50 mA for Figure 36 shows the charging cycle when the supply voltage +VS external use. When powering down the ADA4858-3, the charge charges C1 through Φ1 to ground. During this cycle, C1 quickly pump is not affected and its output voltage and current are still charges to reach the +VS voltage. The discharge cycle then begins available for external use. with switching Φ off and switching Φ on, as shown in Figure 37. 1 2 It is recommended to use 1 μF low ESR and low ESL capacitors When C1 = C2, the charge in C1 is divided between the two for C1 and C2. These capactiors should be placed very close to capacitors and slowly increases the voltage in C2 until it reaches the part. C1 should be placed between Pin C1_a and Pin C1_b, a predetermined voltage (−3 V for +5 V supply and −2 V for and C2 should be placed between Pin CPO and ground. If the +3.3 V supply). The typical charge pump charging and discharging charge pump ripple at the CPO pin is too high, larger capacitors frequency is 550 kHz with a 150 Ω load and no input signal; (that is, 4.7 μF) can replace the 1 μF at C1 and C2. however, this frequency changes with different loads and supply conditions. Φ 1 a +V S C1 CPO Φ b 1 C2 Figure 36. C1 Charging Cycle Rev. A | Page 13 of 20 07714-137 07714-138 ADA4858-3 APPLICATIONS INFORMATION The choice of RF and RG should be carefully considered for GAIN CONFIGURATIONS maximum flatness vs. power dissipation trade-off. In this case, the The ADA4858-3 is a single-supply, high speed, voltage feedback flatness is over 90 MHz, which is more than the high definition amplifier. Table 5 provides a convenient reference for quickly video requirement. determining the feedback and gain set resistor values and band- 5V width for common gain configurations. C1 10µF C2 1 Table 5. Recommended Values and Frequency Performance 0.1µF Small Signal Large Signal 0.1 dB Gain RF (Ω) RG (Ω) −3 dB BW (MHz) Flatness (MHz) 1 402 N/A 600 88 V IN + R4 2 301 301 350 85 U1 R1 75Ω 75Ω V ADA4858-3 OUT 5 200 40 160 35 R5 75Ω – 1 Conditions: V = 5 V, T = 25°C, R = 150 Ω. S A L Figure 38 and Figure 39 show the typical noninverting and R3 R2 –V S 249Ω inverting configurations and the recommended bypass 249Ω capacitor values. Figure 40. DC-Coupled, Single-Supply Schematic 10µF +V S MULTIPLE VIDEO DRIVER In applications requiring that multiple video loads be driven 0.1µF V IN simultaneously, the ADA4858-3 can deliver 5 V supply operation. + Figure 41 shows the ADA4858-3 configured with two video V ADA4858-3 OUT loads, and Figure 42 shows the two video load performances. – R F 301Ω R F 10µF +V S R G R G Figure 38. Noninverting Gain Configuration 0.1µF 301Ω – 75Ω CABLE R 75Ω F 10µF +V S V 1 ADA4858-3 OUT 75Ω CABLE 75Ω V IN + 75Ω CABLE R 0.1µF 75Ω G V V 2 IN – OUT 75Ω 75Ω V ADA4858-3 OUT Figure 41. Video Driver Schematic for Two Video Loads + 6.5 R = 150Ω L 6.0 Figure 39. Inverting Gain Configuration 5.5 R = 75Ω L DC-COUPLED VIDEO SIGNAL 5.0 The ADA4858-3 does not have a rail-to-rail output stage. The output can be within 1 V of the rails. Having a charge pump on 4.5 board that can provide −3 V on a +5 V supply and −2 V on 4.0 +3.3 V supply makes this part excellent for video applications. In dc-coupled applications, the black color has a 0 V voltage reference. 3.5 This means that the output voltage should be able to reach 0 V, V = 5V S R = 301Ω F 3.0 which is feasible with the presence of the charge pump. Figure 40 G = 2 V = 2V p-p OUT shows the schematic of a dc-coupled, single-supply application. 2.5 1 10 100 1000 It is similar to the dual-supply application in which the input is FREQUENCY (MHz) properly terminated with a 50 Ω resistor to ground. The amplifier Figure 42. Large Signal Frequency Response for Various Loads itself is set at a gain of 2 to account for the input termination loss. Rev. A | Page 14 of 20 07714-139 07714-140 CLOSED-LOOP GAIN (dB) 07714-141 07714-142 07714-040 ADA4858-3 220µA R 220µA ADA4858-3 4.7nF G 75Ω 220µA U1 R 75Ω B 301Ω V1 301Ω 74AC86 NTA4153 4.7nF 75Ω U2 G 75Ω 301Ω V2 301Ω 74AC86 ADCMP371AKSZ NTA4153 200kΩ H 4.7nF 0.1µF 75Ω +5V U3 B 75Ω 7.15kΩ 2.8kΩ 301Ω V3 301Ω 74AC86 NTA4153 Figure 43. AC-Coupled Video Input with DC Restored Output DC RESTORE FUNCTION CLAMP AMPLIFIER Having a charge pump gives the ability to take an ac-coupled In some applications, a current output DAC driving a resistor input signal and restore its dc 0 V reference. The simplest way may not have a negative supply available. In such case, the YPbPr of accomplishing this is to use the blanking interval and the H- video signal may be shifted up by 300 mV to avoid clamping the sync signal to set the 0 V reference. Use the H-sync to sample the sync tip. These applications require a signal dc clamp on the output dc level during the blanking interval to charge a capacitor and of the video driver to restore the dc level to 0 V reference. The hold the charge during the video signal. Figure 43 shows the ADA4858-3 has a charge pump that allows the output to swing schematic of the dc restored circuit. negative; twice the sync tip (−600 mV) in G = 2 configuration. The H-sync coming out of the video source can be either positive Figure 44 shows the ADA4858-3 in a difference amplifier or negative. This is why a polarity correction circuit is used to configuration. The video signal is connected to the noninverting produce only a positive going H-sync. The H-sync is fed to a side, and a dc bias of 600 mV is injected on the inverting side. comparator that produces a high voltage if H-sync is negative and V = 5V CC a low voltage if the H-sync is positive. The H-sync is then fed to Y ADA4858-3 an XOR with the output of the comparator. If the original H-sync DAC1 R7 U1 Y was negative, the output of the XOR is positive because of the 75Ω R12 75Ω logic high coming from the comparator, causing the XOR to act as an inverter. However, if the original H-sync is positive, it stays R2 R1 301Ω 301Ω the same because the output of the comparator is low and the V = 5V CC XOR acts as a buffer. Pb DAC2 The result is a positive going H-sync triggering the MOSFET R8 U2 Pb 75Ω R13 during the blanking interval. This shorts the 4.7 nF capacitor to 75Ω ground, which causes it to charge up by the dc level of the current R4 R3 signal. When the H-sync goes low, the MOSFET opens and the 301Ω 301Ω capacitor holds the charge during the video signal, making the V = 5V CC output signal referenced to ground or 0 V level. Pr DAC3 R9 U3 Pr 75Ω R14 V = 5V CC 75Ω ADA4860-1 V = 5V CC R6 R5 R10 301Ω 301Ω 44.2kΩ V1 R11 C1 C2 6.02kΩ 0.1µF 10µF Figure 44. Clamp Amp Rev. A | Page 15 of 20 07714-100 07714-101 ADA4858-3 PD (POWER-DOWN) PIN LAYOUT The ADA4858-3 is equipped with a PD (power-down) pin for As is the case with all high speed applications, careful attention all three amplifiers. This allows the user to reduce the quiescent to printed circuit board (PCB) layout details prevents associated supply current when an amplifier is not active. The power- board parasitics from becoming problematic. The ADA4858-3 can down threshold levels are derived from ground level. The operate at up to 600 MHz; therefore, proper RF design techniques amplifiers are powered down when the voltage applied to the must be employed. The PCB should have a ground plane covering PD pin is greater than a certain voltage from ground. In a 5 V all unused portions of the component side of the board to provide a supply application, the voltage is greater than 2 V, and in a 3.3 V low impedance return path. Removing the ground plane on all supply application, the voltage is greater than 1.5 V. The amplifier layers from the area near and under the input and output pins is enabled whenever the PD pin is left floating (not connected). reduces stray capacitance. Keep signal lines connecting the If the PD pin is not used, it is best to leave it floating or connected feedback and gain resistors as short as possible to minimize the to ground. Note that the power-down feature does not control the inductance and stray capacitance associated with these traces. Place charge pump output voltage and current. termination resistors and loads as close as possible to their respective inputs and outputs. Keep input and output traces as Table 6. Power-Down Voltage Control far apart as possible to minimize coupling (crosstalk) through the PD Pin 5 V 3.3 V board. Adherence to microstrip or stripline design techniques for Not Active <1.5 V <1 V long signal traces (greater than 1 inch) is recommended. For Active >2 V >1.5 V more information on high speed board layout, see “A Practical Guide to High-Speed Printed-Circuit-Board Layout,” Analog POWER SUPPLY BYPASSING Dialogue, Volume 39, Number 3, September 2005 at www.analog.com. Careful attention must be paid to bypassing the power supply pins of the ADA4858-3. High quality capacitors with low equivalent series resistance (ESR), such as multilayer ceramic capacitors (MLCCs), should be used to minimize supply voltage ripple and power dissipation. A large, usually tantalum, capacitor between 2.2 μF to 47 μF located in proximity to the ADA4858-3 is required to provide good decoupling for lower frequency signals. The actual value is determined by the circuit transient and frequency requirements. In addition, place 0.1 μF MLCC decoupling capacitors as close to each of the power supply pins and across from both supplies as is physically possible, no more than 1/8 inch away. The ground returns should terminate immediately into the ground plane. Placing the bypass capacitor return close to the load return minimizes ground loops and improves performance. Rev. A | Page 16 of 20 2.25 2.10 SQ 1.95 ADA4858-3 OUTLINE DIMENSIONS 4.00 0.60 MAX BSC SQ (BOTTOM VIEW) 0.60 MAX PIN 1 INDICATOR 13 16 1 12 PIN 1 0.65 BSC INDICATOR TOP 3.75 VIEW BSC SQ 0.75 9 0.60 4 8 5 0.50 0.25 MIN 0.80 MAX 12° MAX 1.95 BSC 0.65 TYP 0.05 MAX FOR PROPER CONNECTION OF 1.00 0.02 NOM THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND 0.85 0.35 FUNCTION DESCRIPTIONS 0.80 0.20 REF 0.30 COPLANARITY SECTION OF THIS DATA SHEET. SEATING 0.08 0.25 PLANE COMPLIANT TO JEDEC STANDARDS MO-220-VGGC Figure 45.16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm × 4 mm Body, Very Thin Quad (CP-16-4) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option Ordering Quantity 1 ADA4858-3ACPZ-R2 –40°C to +105°C 16-Lead LFCSP_VQ CP-16-4 250 1 ADA4858-3ACPZ-R7 –40°C to +105°C 16-Lead LFCSP_VQ CP-16-4 1,500 1 ADA4858-3ACPZ-RL –40°C to +105°C 16-Lead LFCSP_VQ CP-16-4 5,000 1 Z = RoHS Compliant Part. Rev. A | Page 17 of 20 072808-A ADA4858-3 NOTES Rev. A | Page 18 of 20 ADA4858-3 NOTES Rev. A | Page 19 of 20 ADA4858-3 NOTES ©2008–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07714-0-5/09(A) Rev. A | Page 20 of 20