ANALOG DEVICES ADA4096-2

30 V, Micropower, Overvoltage Protection, Rail-to-Rail Input/Output Amplifier Data Sheet ADA4096-2 FEATURES PIN CONFIGURATIONS Input overvoltage protection, 32 V above and below OUTA 1 8 +V –INA 2 7 OUTB the supply rails ADA4096-2 TOP VIEW +INA 3 6 –INB Rail-to-rail input and output swing (Not to Scale) –V 4 5 +INB Low power: 60 μA per amplifier typical Unity-gain bandwidth Figure 1. 8-Lead, MSOP (RM-8) 800 kHz typical @ V = ±15 V SY OUTA 1 8 +V 550 kHz typical @ V = ±5 V SY ADA4096-2 –INA 2 7 OUTB 465 kHz typical @ V = ±1.5 V TOP VIEW SY +INA 3 (Not to Scale) 6 –INB Single-supply operation: 3 V to 30 V –V 4 5 +INB Low offset voltage: 300 μV maximum High open-loop gain: 120 dB typical NOTES 1. CONNECT THE EXPOSED Unity-gain stable PAD TO GROUND. No phase reversal Figure 2. 8-Lead LFCSP (CP-8-10) Qualified for automotive applications APPLICATIONS Battery monitoring Sensor conditioners Portable power supply control Portable instrumentation GENERAL DESCRIPTION The ADA4096-2 features a unique input stage that allows the The ADA4096-2 operational amplifier features micropower input voltage to exceed either supply safely without any phase operation and rail-to-rail input and output ranges. The reversal or latch-up; this is called overvoltage protection, or OVP. extremely low power requirements and guaranteed operation from 3 V to 30 V make these amplifiers perfectly suited to The dual ADA4096-2 is available in 8-lead LFCSP (2 mm × 2 mm) monitor battery usage and to control battery charging. Their and 8-lead MSOP packages. The ADA409x family is specified dynamic performance, including 27 nV/√Hz voltage noise over the extended industrial temperature range (−40°C to +125°C) density, recommends them for battery-powered audio applica- and is part of the growing selection of 30 V, low power op amps tions. Capacitive loads to 200 pF are handled without oscillation. from Analog Devices, Inc. (see Table 1). The ADA4096-2 has overvoltage protection inputs and diodes Table 1. Low Power, 30 V Operational Amplifiers that allow the voltage input to extend 32 V above and below Op Amp Rail-to-Rail I/O PJFET Low Noise the supply rails, making this device ideal for robust industrial Dual ADA4091-2 AD8682 AD8622 applications. Quad ADA4091-4 AD8684 AD8624 Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2011–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 09241-002 09241-001 ADA4096-2 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1  ±1.5 V Characteristics ..................................................................8  Applications ....................................................................................... 1  ±5 V Characteristics ................................................................... 10  Pin Configurations ........................................................................... 1  ±15 V Characteristics ................................................................ 12  General Description ......................................................................... 1  Comparative Voltage and Variable Voltage Graphs ............... 14  Revision History ............................................................................... 2  Theory of Operation ...................................................................... 15  Specif ica t ions ..................................................................................... 3  Input Stage ................................................................................... 15  Electrical Specifications, V = ±1.5 V ....................................... 3  Phase Inversion ........................................................................... 15  SY Electrical Specifications, V = ±5 V .......................................... 4  Input Overvoltage Protection ................................................... 16  SY Electrical Specifications, VSY = ±15 V ........................................ 5  Comparator Operation .............................................................. 17  Absolute Maximum Ratings ............................................................ 7  Outline Dimensions ....................................................................... 18  Thermal Resistance ...................................................................... 7  Ordering Guide .......................................................................... 19  ESD Caution .................................................................................. 7  Automotive Products ................................................................. 19  Typical Performance Characteristics ............................................. 8  REVISION HISTORY 3/12—Rev. 0 to Rev. A Changed −3 dB Closed-Loop Bandwidth from 97 kHz to 970 kHz(Table 2) ............................................................................... 3 Changed −3 dB Closed-Loop Bandwidth from 114 kHz to 1140 kHz (Table 3)............................................................................ 4 Changed to −3 dB Closed-Loop Bandwidth from 152 kHz to 1520 kHz (Table 4)............................................................................ 5 Updated Outline Dimensions ....................................................... 18 7/11—Revision 0: Initial Version Rev. A | Page 2 of 20 Data Sheet ADA4096-2 SPECIFICATIONS ELECTRICAL SPECIFICATIONS, V = ±1.5 V SY V = ±1.5 V, V = V /2, T = 25°C, unless otherwise noted. SY CM SY A Table 2. Parameter Symbol Test Conditions/Comments Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage VOS 35 300 µV 0°C ≤ TA ≤ +125°C 450 µV −40°C ≤ TA ≤ +125°C 900 µV Offset Voltage Drift ∆V /∆T −40°C ≤ T ≤ +125°C 1 µV/°C OS A Input Bias Current I ±10 ±15 nA B −40°C ≤ T ≤ +125°C ±16 nA A Input Offset Current IOS ±0.1 ±1.5 nA −40°C ≤ TA ≤ +125°C ±3 nA Input Voltage Range −1.5 +1.5 V Common-Mode Rejection Ratio CMRR V = 0 V to ±1.5 V 63 77 dB CM −40°C ≤ T ≤ +125°C 58 dB A Large Signal Voltage Gain AVO RL = 10 kΩ, VO = −1.4 V to +1.4 V 92 94 dB −40°C ≤ TA ≤ +125°C 84 dB RL = 2 kΩ, VO = −1.3 V to +1.3 V 86 92 dB −40°C ≤ T ≤ +125°C 77 dB A MATCHING CHARACTERISTICS Offset Voltage TA = 25°C 100 300 µV OUTPUT CHARACTERISTICS Output Voltage High VOH RL = 10 kΩ to GND 1.48 1.49 V −40°C ≤ TA ≤ +125°C 1.45 V RL = 2 kΩ to GND 1.45 1.46 V −40°C to +125°C 1.40 V Output Voltage Low V R = 10 kΩ to GND −1.49 −1.48 V OL L −40°C ≤ T ≤ +125°C −1.45 V A RL = 2 kΩ to GND −1.48 −1.47 V −40°C ≤ TA ≤ +125°C −1.40 V Short-Circuit Limit I Source/sink ±10 mA SC Closed-Loop Impedance Z f = 100 kHz, A = 1 102 Ω OUT V POWER SUPPLY Power Supply Rejection Ratio PSRR VSY = 3 V to 36 V 100 dB −40°C ≤ TA ≤ +125°C 90 dB Supply Current per Amplifier I V = V /2 40 µA SY O SY −40°C ≤ T ≤ +125°C 80 µA A DYNAMIC PERFORMANCE Slew Rate SR RL = 100 kΩ, CL = 30 pF 0.25 V/µs Gain Bandwidth Product GBP V = 5 mV p-p, R = 10 kΩ, A = 100 501 kHz IN L V Unity-Gain Crossover UGC V = 5 mV p-p, R = 10 kΩ, A = 1 465 kHz IN L V Phase Margin Φ 51 Degrees M −3 dB Closed-Loop Bandwidth −3 dB AV = 1, VIN = 5 mV p-p 970 kHz NOISE PERFORMANCE Voltage Noise e p-p 0.1 Hz to 10 Hz 0.7 µV p-p n Voltage Noise Density e f = 1 kHz 27 nV/√Hz n Current Noise Density in f = 1 kHz 0.2 pA/√Hz Rev. A | Page 3 of 20 ADA4096-2 Data Sheet ELECTRICAL SPECIFICATIONS, V = ±5 V SY VSY = ±5.0 V, VCM = VSY/2, TA = 25°C, unless otherwise noted. Table 3. Parameter Symbol Test Conditions/Comments Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage V 35 300 µV OS −40°C ≤ T ≤ +125°C 500 µV A Offset Voltage Drift ∆VOS/∆T 1 µV/°C Input Bias Current IB ±10 ±15 nA −40°C ≤ TA ≤ +125°C ±19 nA Input Offset Current I ±1.5 ±2 nA OS −40°C ≤ T ≤ +125°C ±3 nA A Input Voltage Range −5 +5 V Common-Mode Rejection Ratio CMRR VCM = −5 V to +5 V 73 86 dB −40°C ≤ TA ≤ +125°C 68 dB VCM = −3 V to +3 V 91 103 dB −40°C ≤ T ≤ +125°C 85 dB A Large Signal Voltage Gain A R = 10 kΩ, V = ±4.8 V 102 111 dB VO L O −40°C ≤ TA ≤ +125°C 99 dB RL = 2 kΩ, VO = ±4.7 V 94 103 dB −40°C ≤ TA ≤ +125°C 88 dB MATCHING CHARACTERISTICS Offset Voltage T = 25°C 100 300 µV A OUTPUT CHARACTERISTICS Output Voltage High V R = 10 kΩ to GND 4.96 4.97 V OH L −40°C ≤ T ≤ +125°C 4.95 V A R = 2 kΩ to GND 4.80 4.90 V L −40°C ≤ TA ≤ +125°C 4.70 V Output Voltage Low VOL RL = 10 kΩ to GND −4.98 −4.97 V −40°C ≤ T ≤ +125°C −4.95 V A R = 2 kΩ to GND −4.90 −4.80 V L −40°C ≤ T ≤ +125°C −4.75 V A Short-Circuit Limit ISC Source/sink ±10 mA Closed-Loop Impedance ZOUT f = 100 kHz, AV = 1 71 Ω POWER SUPPLY Power Supply Rejection Ratio PSRR V = 3 V to 36 V 100 dB SY −40°C ≤ T ≤ +125°C 90 dB A Supply Current per Amplifier ISY VO = VSY/2 47 55 µA −40°C ≤ TA ≤ +125°C 75 µA DYNAMIC PERFORMANCE Slew Rate SR R = 100 kΩ, C = 30 pF 0.3 V/µs L L Gain Bandwidth Product GBP VIN = 5 mV p-p, RL = 10 kΩ, AV = 100 595 kHz Unity-Gain Crossover UGC VIN = 5 mV p-p, RL = 10 kΩ, AV = 1 550 kHz Phase Margin Φ 52 Degrees M −3 dB Closed-Loop Bandwidth −3 dB A = 1, V = 5 mV p-p 1140 kHz V IN NOISE PERFORMANCE Voltage Noise en p-p 0.1 Hz to 10 Hz 0.7 µV p-p Voltage Noise Density en f = 1 kHz 27 nV/√Hz Current Noise Density i f = 1 kHz 0.2 pA/√Hz n Rev. A | Page 4 of 20 Data Sheet ADA4096-2 ELECTRICAL SPECIFICATIONS, V = ±15 V SY VSY = ±15.0 V, VCM = VSY/2, VO = 0.0 V, TA = 25°C, unless otherwise noted. Table 4. Parameter Symbol Test Conditions/Comments Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage V 35 300 µV OS −40°C ≤ TA ≤ +125°C 500 µV Offset Voltage Drift ∆VOS/∆T 1 µV/°C Input Bias Current IB ±3 ±10 nA −40°C ≤ T ≤ +125°C ±15 nA A Input Offset Current I ±0.1 ±1.5 nA OS −40°C ≤ TA ≤ +125°C ±3 nA Input Voltage Range −15 +15 V Common-Mode Rejection Ratio CMRR VCM = −15 V to +15 V 82 95 dB −40°C ≤ TA ≤ +125°C 75 dB V = −13 V to +13 V 95 107 dB CM −40°C ≤ T ≤ +125°C 89 dB A Large Signal Voltage Gain AVO RL = 10 kΩ, VO = ±14.7 V 110 120 dB −40°C ≤ TA ≤ +125°C 105 dB RL = 2 kΩ, VO = ±11 V 100 112 dB −40°C ≤ T ≤ +125°C 90 dB A Input Capacitance Differential Mode C 2.5 pF DM Common Mode CCM 7 pF MATCHING CHARACTERISTICS Offset Voltage T = 25°C 100 300 µV A OUTPUT CHARACTERISTICS Output Voltage High VOH RL = 10 kΩ to GND 14.92 14.94 V −40°C ≤ TA ≤ +125°C 14.90 V R = 2 kΩ to GND 14.0 14.3 V L −40°C ≤ T ≤ +125°C 12.0 V A Output Voltage Low VOL RL = 10 kΩ to GND −14.96 −14.80 V −40°C ≤ TA ≤ +125°C −14.75 V RL = 2 kΩ to GND −14.75 −14.65 V −40°C ≤ T ≤ +125°C −14.0 V A Short-Circuit Limit I Source/sink ±10 mA SC Closed-Loop Impedance Z f = 100 kHz, A = 1 40 Ω OUT V POWER SUPPLY Power Supply Rejection Ratio PSRR V = 3 V to 36 V 100 dB SY −40°C ≤ T ≤ +125°C 90 dB A Supply Current per Amplifier I V = V /2 60 75 µA SY O SY −40°C ≤ TA ≤ +125°C 100 µA DYNAMIC PERFORMANCE Slew Rate SR R = 100 kΩ, C = 30 pF 0.4 V/µs L L Settling Time t To 0.1%, 10 V step 23.4 µs S Gain Bandwidth Product GBP VIN = 5 mV p-p, RL = 10 kΩ, AV = 100 786 kHz Unity-Gain Crossover UGC VIN = 5 mV p-p, RL = 10 kΩ, AV = 1 800 kHz Phase Margin ΦM 60 Degrees −3 dB Closed-Loop Bandwidth −3 dB A = 1, V = 5 mV p-p 1520 kHz V IN Channel Separation CS f = 1 kHz 100 dB Rev. A | Page 5 of 20 ADA4096-2 Data Sheet Parameter Symbol Test Conditions/Comments Min Typ Max Unit NOISE PERFORMANCE Voltage Noise en p-p 0.1 Hz to 10 Hz 0.7 µV p-p Voltage Noise Density en f = 1 kHz 27 nV/√Hz Current Noise Density in f = 1 kHz 0.2 pA/√Hz Rev. A | Page 6 of 20 Data Sheet ADA4096-2 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 5. Parameter Rating θ is specified for the device soldered on a 4-layer JEDEC standard JA printed circuit board (PCB) with zero airflow. The exposed pad Supply Voltage 36 V Input Voltage is soldered to the application board. Operating Condition −V ≤ VIN ≤ +V Table 6. Thermal Resistance 1 Overvoltage Condition (−V) − 32 V ≤ V ≤ (+V) + 32 V IN 2 Package Type θJA θJC Unit Differential Input Voltage ±V SY 8-Lead MSOP (RM-8) 142 45 °C/W Input Current ±5 mA 8-Lead LFCSP (CP-8-10) 76 43 °C/W Output Short-Circuit Duration to Indefinite GND Storage Temperature Range −65°C to +150°C ESD CAUTION Operating Temperature Range −40°C to +125°C Junction Temperature Range −65°C to +150°C Lead Temperature (Soldering, 300°C 60 sec) 1 Performance not guaranteed during overvoltage conditions. 2 Limit the input current to ±5 mA. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. A | Page 7 of 20 ADA4096-2 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted. ±1.5 V CHARACTERISTICS 180 10k ADA4096-2 ADA4096-2 V = ±1.5V V = ±1.5V SY SY 160 T = 25°C T = 25°C A A 140 1k 120 100 100 80 60 SOURCING SINKING 10 40 20 0 1 0.001 0.01 0.1 1 10 100 LOAD CURRENT (mA) V (µV) OS Figure 3. Input Offset Voltage Distribution Figure 6. Dropout Voltage vs. Load Current 25 140 200 ADA4096-2 ADA4096-2 V = ±1.5V V = ±1.5V 120 SY SY T = –40°C TO +125°C T = 25°C A A 150 20 100 PHASE 80 100 15 60 40 50 GAIN 10 20 0 0 5 –20 –50 –40 0 –60 –100 100 1k 10k 100k 1M 10M –2.5 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5 FREQUENCY (Hz) TCV (µV/°C) OS Figure 4. Offset Voltage Drift Distribution Figure 7. Open-Loop Gain and Phase vs. Frequency 30 50 ADA4096-2 ADA4096-2 G = +100 V = ±1.5V V = ±1.5V 40 SY SY 20 T = 25°C A 30 G = +10 10 20 T = +25°C A T = +125°C A 10 0 G = +1 T = +85°C A 0 –10 –10 T = 0°C A –20 –20 –30 –30 –40 T = –40°C A –40 –50 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 10 100 1k 10k 100k 1M 10M V (V) FREQUENCY (Hz) CM Figure 5. Input Bias Current vs. V and Temperature Figure 8. Closed-Loop Gain vs. Frequency CM Rev. A | Page 8 of 20 I (nA) B NUMBER OF AMPLIFIERS NUMBER OF AMPLIFIERS –200 –175 –150 –125 –100 –75 –50 –25 0 25 50 75 100 125 150 175 200 MORE 09241-004 09241-003 09241-005 GAIN (dB) V TO RAIL (mV) CLOSED-LOOP GAIN (dB) OUT PHASE (Degrees) 09241-008 09241-006 09241-007 Data Sheet ADA4096-2 10k 0.08 ADA4096-2 ADA4096-2 V = ±1.5V V = ±1.5V SY SY 0.06 T = 25°C T = 25°C A A 1k R = 10kΩ L 0.04 C = 100pF L G = +1 100 0.02 G = +100 0 10 –0.02 G = +10 1 –0.04 –0.06 G = +1 0.1 –0.08 0.01 –0.10 10 100 1k 10k 100k 1M 10M 0 5 10 15 20 25 30 FREQUENCY (Hz) TIME (µs) Figure 9. Output Impedance vs. Frequency Figure 12. Small Signal Transient Response 120 1.6 ADA4096-2 ADA4096-2 V = ±1.5V V = ±1.5V SY SY 1.4 100 T = 25°C T = 25°C A A R = 10kΩ F R = 100Ω 1.2 S 80 PSRR+ 1.0 60 0.8 PSRR– 40 0.6 20 0.4 0 0.2 –20 0 10 100 1k 10k 100k 1M 10M 0 20 40 60 80 100 FREQUENCY (Hz) TIME (µs) Figure 10. PSRR vs. Frequency Figure 13. Positive Overload Recovery 2.0 0.2 ADA4096-2 ADA4096-2 V = ±1.5V V = ±1.5V SY SY 0 1.5 T = 25°C T = 25°C A A R = 10kΩ R = 10kΩ L F –0.2 C = 100pF R = 100Ω 1.0 L S G = +1 –0.4 0.5 –0.6 0 –0.8 –0.5 –1.0 –1.0 –1.2 –1.5 –1.4 –2.0 –1.6 0 20 40 60 80 100 120 0 20 40 60 80 100 TIME (µs) TIME (µs) Figure 11. Large Signal Transient Response Figure 14. Negative Overload Recovery Rev. A | Page 9 of 20 PSRR (dB) Z (Ω) V (V) OUT OUT 09241-010 09241-052 09241-009 V (V) V (V) OUT OUT V (V) OUT 09241-011 09241-056 09241-055 ADA4096-2 Data Sheet ±5 V CHARACTERISTICS 250 10k ADA4096-2 ADA4096-2 V = ±5V V = ±5V SY SY T = 25°C T = 25°C A A 200 1k 150 100 100 SOURCING SINKING 10 50 0 1 0.001 0.01 0.1 1 10 100 LOAD CURRENT (mA) V (µV) OS Figure 18. Dropout Voltage vs. Load Current Figure 15. Input Offset Voltage Distribution 40 140 200 ADA4096-2 ADA4096-2 V = ±5V V = ±5V SY 120 SY 35 T = –40°C TO +125°C T = 25°C A A 150 100 30 PHASE 80 100 25 60 20 40 50 GAIN 20 15 0 0 10 –20 –50 5 –40 0 –60 –100 100 1k 10k 100k 1M 10M –2.5 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5 FREQUENCY (Hz) TCV (µV/°C) OS Figure 16. Offset Voltage Drift Distribution Figure 19. Open-Loop Gain and Phase vs. Frequency 30 50 ADA4096-2 ADA4096-2 G = +100 V = ±5V V = ±5V 40 SY SY 20 T = 25°C A 30 10 G = +10 T = +125°C 20 A 0 T = +85°C 10 A G = +1 –10 0 –10 –20 –20 T = +25°C A –30 –30 T = 0°C A –40 –40 T = –40°C A –50 –50 –5 –4 –3 –2 –1 0 1 2 3 4 5 10 100 1k 10k 100k 1M 10M V (V) FREQUENCY (Hz) CM Figure 20. Closed-Loop Gain vs. Frequency Figure 17. Input Bias Current vs. VCM and Temperature Rev. A | Page 10 of 20 I (nA) NUMBER OF AMPLIFIERS NUMBER OF AMPLIFIERS B –200 –175 –150 –125 –100 –75 –50 –25 0 25 50 75 100 125 150 175 200 MORE 09241-016 09241-015 09241-050 GAIN (dB) V TO RAIL (mV) CLOSED-LOOP GAIN (dB) OUT PHASE (Degrees) 09241-024 09241-023 09241-020 Data Sheet ADA4096-2 10k 0.08 ADA4096-2 ADA4096-2 V = ±5V V = ±5V SY SY 0.06 T = 25°C T = 25°C A A 1k R = 10kΩ L 0.04 C = 100pF L G = +1 100 0.02 G = +100 0 10 –0.02 G = +10 1 –0.04 –0.06 G = +1 0.1 –0.08 0.01 –0.10 10 100 1k 10k 100k 1M 10M 0 5 10 15 20 25 30 FREQUENCY (Hz) TIME (µs) Figure 21. Output Impedance vs. Frequency Figure 24. Small Signal Transient Response 140 6 ADA4096-2 ADA4096-2 V = ±5V V = ±5V SY SY 120 T = 25°C T = 25°C A A 5 R = 10kΩ F R = 100Ω 100 S 4 80 PSRR+ 60 3 PSRR– 40 2 20 1 0 –20 0 10 100 1k 10k 100k 1M 10M 0 20 40 60 80 100 FREQUENCY (Hz) TIME (µs) Figure 22. PSRR vs. Frequency Figure 25. Positive Overload Recovery 6 1 ADA4096-2 ADA4096-2 V = ±5V V = ±5V SY SY T = 25°C T = 25°C A A 4 0 R = 10kΩ R = 10kΩ L F C = 100pF R = 100Ω L S G = +1 2 –1 0 –2 –2 –3 –4 –4 –6 –5 0 50 100 150 200 250 300 350 400 0 20 40 60 80 100 TIME (µs) TIME (µs) Figure 23. Large Signal Transient Response Figure 26. Negative Overload Recovery Rev. A | Page 11 of 20 PSRR (dB) Z (Ω) V (V) OUT OUT 09241-017 09241-053 09241-021 V (V) V (V) OUT OUT V (V) OUT 09241-018 09241-058 09241-057 ADA4096-2 Data Sheet ±15 V CHARACTERISTICS 250 10k ADA4096-2 ADA4096-2 V = ±15V V = ±15V SY SY T = 25°C T = 25°C A A 200 1k 150 100 100 SOURCING SINKING 10 50 0 1 0.001 0.01 0.1 1 10 100 LOAD CURRENT (mA) V (µV) OS Figure 30. Dropout Voltage vs. Load Current Figure 27. Input Offset Voltage Distribution 35 140 200 ADA4096-2 ADA4096-2 V = ±15V V = ±15V 120 SY SY T = 25°C 30 T = –40°C TO +125°C A A 150 100 25 80 PHASE 100 60 20 40 50 GAIN 15 20 0 0 10 –20 –50 5 –40 –60 –100 0 100 1k 10k 100k 1M 10M –2.5 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5 FREQUENCY (Hz) TCV (µV/°C) OS Figure 28. Offset Voltage Drift Distribution Figure 31. Open-Loop Gain and Phase vs. Frequency 40 50 ADA4096-2 ADA4096-2 G = +100 V = ±15V V = ±15V 30 SY SY 40 T = 25°C A 20 30 T = +125°C A G = +10 10 T = +85°C A 20 0 10 –10 G = +1 0 –20 T = +25°C A –10 T = 0°C –30 A –20 –40 –30 –50 T = –40°C A –40 –60 –15 –10 –5 0 5 10 15 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) V (V) CM Figure 29. Input Bias Current vs. VCM and Temperature Figure 32. Closed-Loop Gain vs. Frequency Rev. A | Page 12 of 20 I (nA) B NUMBER OF AMPLIFIERS NUMBER OF AMPLIFIERS –200 –175 –150 –125 –100 –75 –50 –25 0 25 50 75 100 125 150 175 200 MORE 09241-028 09241-027 09241-051 GAIN (dB) V TO RAIL (mV) CLOSED-LOOP GAIN (dB) OUT PHASE (Degrees) 09241-036 09241-034 09241-030 Data Sheet ADA4096-2 10k 0.08 ADA4096-2 ADA4096-2 V = ±15V V = ±15V SY SY 0.06 T = 25°C T = 25°C A A 1k R = 10kΩ L 0.04 C = 100pF L G = +1 100 0.02 0 10 G = +100 –0.02 G = +10 1 –0.04 G = +1 –0.06 0.1 –0.08 0.01 –0.10 10 100 1k 10k 100k 1M 10M 0 5 10 15 20 25 30 FREQUENCY (Hz) TIME (µs) Figure 33. Output Impedance vs. Frequency Figure 36. Small Signal Transient Response 120 16 ADA4096-2 ADA4096-2 V = ±15V V = ±15V SY SY 14 100 T = 25°C T = 25°C A A R = 10kΩ F R = 100Ω 12 S 80 PSRR+ 10 60 PSRR– 8 40 6 20 4 0 2 –20 0 0 20 40 60 80 100 10 100 1k 10k 100k 1M 10M TIME (µs) FREQUENCY (Hz) Figure 34. PSRR vs. Frequency Figure 37. Positive Overload Recovery 15 0 ADA4096-2 ADA4096-2 V = ±15V V = ±15V SY SY –2 T = 25°C T = 25°C A A 10 R = 10kΩ R = 10kΩ L F C = 100pF R = 100Ω L –4 S G = +1 5 –6 0 –8 –10 –5 –12 –10 –14 –15 –16 0 50 100 150 200 250 300 350 400 0 20 40 60 80 100 TIME (µs) TIME (µs) Figure 35. Large Signal Transient Response Figure 38. Negative Overload Recovery Rev. A | Page 13 of 20 PSRR (dB) Z (Ω) V (V) OUT OUT 09241-031 09241-054 09241-035 V (V) V (V) OUT OUT V (V) OUT 09241-032 09241-060 09241-059 ADA4096-2 Data Sheet COMPARATIVE VOLTAGE AND VARIABLE VOLTAGE GRAPHS 0.5 70 ADA4096-2 ADA4096-2 V = ±15V T = 25°C SY A 0.4 T = 25°C R = ∞ 60 A L 0.3 50 0.2 40 0.1 0 30 –0.1 20 –0.2 10 –0.3 –0.4 0 –10 –8 –6 –4 –2 0 2 4 6 8 10 0 4 8 12 16 20 24 28 32 36 TIME (s) SUPPLY VOLTAGE (V) Figure 39. Input Voltage Noise, 0.1 Hz to 10 Hz Bandwidth Figure 42. Supply Current vs. Supply Voltage –80 100 ADA4096-2 ADA4096-2 V = ±15V V = ±15V SY SY T = 25°C T = 25°C A A –90 –100 –110 10kΩ –120 1kΩ –130 2kΩ V = IN 10V p-p –140 10 20 100 1k 10k 50k 0.1 1 10 100 1k FREQUENCY (Hz) FREQUENCY (Hz) Figure 40. Channel Separation vs. Frequency Figure 43. Voltage Noise Density 120 50 ADA4096-2 ADA4096-2 T = 25°C V = ±15V 110 SY A T = 25°C A R = 2kΩ L 100 40 G = +1 V = 100mV p-p IN 90 V = ±15V SY 80 30 V = ±1.5V SY 70 V = ±5V SY 60 20 OS– 50 40 10 OS+ 30 20 0 100 1k 10k 100k 1M 10M 0.01 0.1 1 FREQUENCY (Hz) C (nF) LOAD Figure 41. CMRR vs. Frequency Figure 44. Overshoot vs. Load Capacitance Rev. A | Page 14 of 20 CMRR (dB) CHANNEL SEPARATION (dB) NOISE (µV) 09241-039 09241-040 09241-041 OVERSHOOT (%) e (nV/ Hz) SUPPLY CURRENT PER AMPLIFIER (µA) n 09241-100 09241-043 09241-044 Data Sheet ADA4096-2 THEORY OF OPERATION INPUT STAGE V CC R7 R1 R2 R5 I1 I3 D6 D10 Q20 Q5 Q6 Q11 Q12 D3 C2 D9 Q18 Q3 Q4 OUT Q13 Q14 D4 Q7 Q8 C1 Q9 D8 Q17 Q10 ×1 Q19 OVP +IN Q1 Q2 R6 D2 Q16 I2 Q15 D7 –IN OVP R3 R4 D11 D1 V EE Figure 45. Simplified Schematic Figure 45 shows a simplified schematic of the ADA4096-2. The Although phase inversion persists for only as long as the inputs are input stage comprises two differential pairs (Q1 to Q4 and Q5 saturated, it can be detrimental to applications where the amplifier to Q8) operating in parallel. When the input common-mode is part of a closed-loop system. The ADA4096-2 is free from phase voltage approaches V − 1.5 V, Q1 to Q4 shut down as I1 reaches inversion over the entire common-mode voltage range, as well as CC its minimum voltage compliance. Conversely, when the input the overvoltage protected range stated in the Absolute Maximum common-mode voltage approaches V + 1.5 V, Q5 to Q8 shut Ratings section, Table 5. Figure 46 shows the ADA4096-2 in a EE down as I2 reaches its minimum voltage compliance. This unity-gain configuration with the input signal at ±40 V and the topology allows for maximum input dynamic range because the amplifier supplies at ±10 V. amplifier can function with its inputs at 200 mV outside the rail T (at room temperature). As with any rail-to-rail input amplifier, V mismatch between OS the two input pairs determines the CMRR of the amplifier. If the input common-mode voltage range is kept within 1.5 V of each rail, transitions between the input pairs are avoided, thus 1 improving the CMRR by approximately 10 dB (see Table 3 and Table 4). PHASE INVERSION Some single-supply amplifiers exhibit phase inversion when the input signal extends beyond the common-mode voltage range of the amplifier. When the input devices become saturated, CH1 10.0V CH2 10.0V M2.00ms A CH1 –3.6V T 34.20% the inverting and noninverting inputs exchange functions, Figure 46. No Phase Reversal causing the output to move in the opposing direction. Rev. A | Page 15 of 20 09241-045 09241-046 ADA4096-2 Data Sheet Figure 47 was generated with the ADA4096-2 in a buffer configu- INPUT OVERVOLTAGE PROTECTION ration with the supplies connected to GND (or ±15 V) and the The ADA4096-2 inputs are protected from input voltage positive input swept until it exceeds the supplies by 32 V. In general, excursions up to 32 V outside each rail. This feature is of input current is limited to 1 mA during positive overvoltage con- particular importance in applications with power supply ditions and 200 μA during negative undervoltage conditions. For sequencing issues that could cause the signal source to be active example, at an overvoltage of 20 V, the ADA4096-2 input current is before the supplies to the amplifier. limited to 1 mA, providing a current limit equivalent to a series Figure 47 shows the input current limiting capability of the 20 kΩ resistor. Figure 47 also shows that the current limiting ADA4096-2 (green curves) compared to using a 5 kΩ series circuitry is active whether the amplifier is powered or not. resistor (red curves). Note that Figure 47 represents input protection under abnormal 7 conditions only. The correct amplifier operation input voltage 6 range (IVR) is specified in Table 2 to Table 4. 5 4 3 2 1 0 –1 –2 –3 –4 –5 LOW RDS SERIES FET ON –6 5kΩ SERIES RESISTOR –7 –48 –40 –32 –24 –16 –8 0 8 16 24 32 40 48 V (V) IN Figure 47. Input Current Limiting Capability Rev. A | Page 16 of 20 INPUT BIAS CURRENT (mA) V = –15V EE V = 0V EE V = +15V CC 09241-047 Data Sheet ADA4096-2 500 COMPARATOR OPERATION Although op amps are quite different from comparators, 400 occasionally an unused section of a dual or a quad op amp V = HIGH OUT may be pressed into service as a comparator; however, this is not recommended for any rail-to-rail output op amps. For rail- 300 to-rail output op amps, the output stage is generally a ratioed current mirror with bipolar or MOSFET transistors. With the part V = LOW OUT 200 operating open loop, the second stage increases the current drive to the ratioed mirror to close the loop, but it cannot, which results 100 in an increase in supply current. With the op amp configured as BUFFER a comparator, the supply current can be significantly higher (see Figure 48). 0 0 4 8 12 16 20 24 28 32 36 SUPPLY VOLTAGE (V) Figure 48. Comparator Supply Current Rev. A | Page 17 of 20 SUPPLY CURRENT PER AMPLIFIER (µA) 09241-048 ADA4096-2 Data Sheet OUTLINE DIMENSIONS 3.20 3.00 2.80 8 5 5.15 3.20 4.90 3.00 4.65 1 2.80 4 PIN 1 IDENTIFIER 0.65 BSC 0.95 15° MAX 0.85 1.10 MAX 0.75 0.80 0.15 0.23 6° 0.55 0.40 0.05 0.09 0° 0.40 0.25 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 49. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters 1.70 1.60 1.50 2.00 BSC SQ 0.50 BSC 5 8 0.175 REF PIN 1 INDEX EXPOSED 1.10 PAD AREA 1.00 0.425 0.90 0.350 0.275 4 1 TOP VIEW BOTTOM VIEW FOR PROPER CONNECTION OF 0.60 THE EXPOSED PAD, REFER TO 0.05 MAX 0.55 THE PIN CONFIGURATION AND 0.02 NOM 0.50 FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. SEATING 0.30 PLANE 0.20 REF 0.25 0.20 Figure 50. 8-Lead Lead Frame Chip Scale Package [LFCSP_UD] 2 mm × 2 mm Body, Ultra Thin, Dual Lead (CP-8-10) Dimensions shown in millimeters Rev. A | Page 18 of 20 PIN 1 IND ATOR IC (R 0.15) 10-07-2009-B 07-11-2011-B Data Sheet ADA4096-2 ORDERING GUIDE Temperature 1, 2 Model Range Package Description Package Option Branding ADA4096-2ARMZ −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 A2T ADA4096-2ARMZ-R7 −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 A2T ADA4096-2ARMZ-RL −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 A2T ADA4096-2ACPZ-R7 −40°C to +125°C 8-Lead Frame Chip Scale Package [LFCSP_UD] CP-8-10 A4 ADA4096-2ACPZ-RL −40°C to +125°C 8-Lead Frame Chip Scale Package [LFCSP_UD] CP-8-10 A4 ADA4096-2WARMZ-R7 −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 A2T ADA4096-2WARMZ-RL −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 A2T 1 Z = RoHS Compliant Part. 2 W = Qualified for Automotive Applications. AUTOMOTIVE PRODUCTS The ADA4096-2W models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models. Rev. A | Page 19 of 20 ADA4096-2 Data Sheet NOTES ©2011–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09241-0-3/12(A) Rev. A | Page 20 of 20