ANALOG DEVICES ADA4092-4

Micropower RRIO Operational Amplifier ADA4092-4 FEATURES PIN CONFIGURATION Single-supply operation: 3 V to 30 V 1 14 OUTA OUTD Wide input voltage range 2 13 –INA –IND Rail-to-rail output swing 3 12 +INA +IND ADA4092-4 Low supply current: 200 μA/amplifier 4 11 +V TOP VIEW –V (Not to Scale) Wide bandwidth: 1.4 MHz 5 10 +INB +INC High phase margin: 69° 6 9 –INB –INC Slew rate: 0.4 V/μs OUTB 7 8 OUTC Low offset voltage: 1.50 mV maximum Figure 1. 14-Lead TSSOP (RU-14) No phase reversal Overvoltage protection (OVP) 25 V above/below supply rails at ±5 V 12 V above/below supply rails at ±15 V APPLICATIONS Industrial process control Battery-powered instrumentation Power supply control and protection Telecommunications Remote sensors Low voltage strain gage amplifiers DAC output amplifiers GENERAL DESCRIPTION The ADA4092-4 quad is a micropower, single-supply, 1.4 MHz The ADA4092-4 is specified over the extended industrial bandwidth amplifier featuring rail-to-rail inputs and outputs. It temperature range of −40°C to +125°C. The ADA4092-4 is is guaranteed to operate from a +3 V to +30 V single supply as part of the growing selection of 30 V, low power op amps from well as from ±1.5 V to ±15 V dual supplies. Analog Devices, Inc., see Table 1. The ADA4092-4 features a unique input stage that allows the The ADA4092-4 is available in the 14–lead TSSOP surface-mount input voltage to exceed either supply safely without any phase package. reversal or latch-up; this is called overvoltage protection (OVP). Table 1. Low Power, 30 V Operational Amplifiers Applications for these amplifiers include portable telecom- RRIO Low munications equipment, power supply control and protection, Family Rail-to-Rail I/O Precision PJFET Noise and interface for transducers with wide output ranges. Sensors Single OP1177 requiring a rail-to-rail input amplifier include Hall effect, piezo- Dual ADA4091-2 AD8682 OP2177 electric, and resistive transducers. ADA4091-4 AD8684 OP4177 Quad ADA4092-4 The ability to swing rail-to-rail at both the input and output enables designers, for example, to build multistage filters in single-supply systems and to maintain high signal-to-noise ratios (SNR). Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2010–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 08803-001 ADA4092-4 TABLE OF CONTENTS Features .............................................................................................. 1 ESD Caution...................................................................................6 Applications ....................................................................................... 1 Typical Performance Characteristics ..............................................7 Pin Configuration ............................................................................. 1 Theory of Operation ...................................................................... 15 General Description ......................................................................... 1 Input Stage ................................................................................... 15 Revision History ............................................................................... 2 Output Stage ................................................................................ 15 Specifications ..................................................................................... 3 Input Overvoltage Protection ................................................... 16 Electrical Specifications ............................................................... 3 Comparator Operation .............................................................. 16 Absolute Maximum Ratings ............................................................ 6 Outline Dimensions ....................................................................... 17 Thermal Resistance ...................................................................... 6 Ordering Guide .......................................................................... 17 REVISION HISTORY 6/11—Rev. A to Rev. B Changes to Single-Supply Operating Range ................................. 1 5/10—Rev. 0 to Rev. A Changes to Data Sheet Title, General Description, and Table 1 ......................................................................................... 1 4/10—Revision 0: Initial Version Rev. B | Page 2 of 20 ADA4092-4 SPECIFICATIONS ELECTRICAL SPECIFICATIONS V = ±1.5 V, V = 0 V, T = 25°C, unless otherwise noted. SY CM A Table 2. Parameter Symbol Test Conditions/Comments Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage V −1.5 +0.2 +1.5 mV OS −40°C ≤ T ≤ +125°C −2.5 +2.5 mV A Offset Voltage Drift ΔV /ΔT 3 µV/°C OS Input Bias Current I −60 −45 nA B −40°C ≤ T ≤ +85°C −60 +60 nA A −40°C ≤ T ≤ +125°C −275 +275 nA A Input Offset Current I −4 +1 +4 nA OS −40°C ≤ T ≤ +85°C −5 +5 nA A −40°C ≤ T ≤ +125°C −75 +75 nA A Input Voltage Range IVR −1.5 +1.5 V Common-Mode Rejection Ratio CMRR V = −1.5 V to +1.5 V 70 85 dB CM −40°C ≤ T ≤ +125°C 68 dB A Large Signal Voltage Gain A R = 100 kΩ, V = −1.2 V to +1.2 V 106 113 dB VO L O −40°C ≤ T ≤ +125°C 101 dB A R = 10 kΩ, V = −1.2 V to +1.2 V 92 94 dB L O −40°C ≤ T ≤ +125°C 85 dB A OUTPUT CHARACTERISTICS Output Voltage High V R = 100 kΩ to GND 1.485 1.495 V OH L −40°C ≤ T ≤ +125°C 1.480 V A R = 10 kΩ to GND 1.470 1.480 V L −40°C to +125°C 1.455 V Output Voltage Low V R = 100 kΩ to GND −1.497 −1.490 V OL L −40°C ≤ T ≤ +125°C −1.480 V A R = 10 kΩ to GND −1.495 −1.485 V L −40°C ≤ T ≤ +125°C −1.475 V A Short-Circuit Limit I Source/sink ±30 mA SC Closed-Loop Impedance Z f = 1 MHz, A = +1 130 Ω OUT V POWER SUPPLY Power Supply Rejection Ratio PSRR V = 2.7 V to 36 V 98 112 dB SY −40°C ≤ T ≤ +125°C 90 dB A Supply Current per Amplifier I I = 0 mA 165 200 µA SY O −40°C ≤ T ≤ +125°C 300 µA A DYNAMIC PERFORMANCE Slew Rate SR R = 100 kΩ, C = 30 pF 0.4 V/µs L L Settling Time t To 0.01% 25 µs S Gain Bandwidth Product GBP 1.2 MHz Phase Margin Φ 66 Degrees M NOISE PERFORMANCE Voltage Noise e p-p 0.1 Hz to 10 Hz 0.8 µV p-p n Voltage Noise Density e f = 1 kHz 30 nV/√Hz n Rev. B | Page 3 of 20 ADA4092-4 V = ±5.0 V, V = 0 V, T = 25°C, unless otherwise noted. SY CM A Table 3. Parameter Symbol Test Conditions/Comments Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage V −1.5 +0.2 +1.5 mV OS −40°C ≤ T ≤ +125°C −2.5 +2.5 mV A Offset Voltage Drift ΔV /ΔT 3 µV/°C OS Input Bias Current I −60 −53 nA B −40°C ≤ T ≤ +85°C −80 +80 nA A −40°C ≤ T ≤ +125°C −350 +350 nA A Input Offset Current I −4 +1 +4 nA OS −40°C ≤ T ≤ +85°C −7 +7 nA A −40°C ≤ T ≤ +125°C −100 +100 nA A Input Voltage Range IVR −5 +5 V Common-Mode Rejection Ratio CMRR V = −5.0 V to +5.0 V 82 95 dB CM −40°C ≤ T ≤ +125°C 78 dB A Large Signal Voltage Gain A R = 100 kΩ, V = ±4.7 V 113 117 dB VO L O −40°C ≤ T ≤ +125°C 106 dB A R = 10 kΩ, V = ±4.7 V 98 100 dB L O −40°C ≤ T ≤ +125°C 90 dB A OUTPUT CHARACTERISTICS Output Voltage High V R = 100 kΩ to GND 4.980 4.990 V OH L −40°C ≤ T ≤ +125°C 4.975 V A R = 10 kΩ to GND 4.945 4.960 V L −40°C ≤ T ≤ +125°C 4.900 V A Output Voltage Low V R = 100 kΩ to GND −4.997 −4.990 V OL L −40°C ≤ T ≤ +125°C −4.980 V A R = 10 kΩ to GND −4.990 −4.980 V L −40°C ≤ T ≤ +125°C −4.975 V A Short-Circuit Limit I Source/sink ±20 mA SC Closed-Loop Impedance Z f = 1 MHz, A = +1 90 Ω OUT V POWER SUPPLY Power Supply Rejection Ratio PSRR V = 2.7 V to 36 V 98 112 dB SY −40°C ≤ T ≤ +125°C 90 dB A Supply Current per Amplifier I I = 0 mA 180 225 µA SY O −40°C ≤ T ≤ +125°C 300 µA A DYNAMIC PERFORMANCE Slew Rate SR R = 100 kΩ, C = 30 pF 0.4 V/µs L L Settling Time t To 0.01% 25 µs S Gain Bandwidth Product GBP 1.3 MHz Phase Margin Φ 67 Degrees M NOISE PERFORMANCE Voltage Noise e p-p 0.1 Hz to 10 Hz 0.8 µV p-p n Voltage Noise Density e f = 1 kHz 30 nV/√Hz n Rev. B | Page 4 of 20 ADA4092-4 V = ±15.0 V, V = 0 V, V = 0 V, T = 25°C, unless otherwise noted. SY CM O A Table 4. Parameter Symbol Test Conditions/Comments Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage V −1.5 +0.2 +1.5 mV OS −40°C ≤ T ≤ +125°C −2.5 +2.5 mV A Offset Voltage Drift ΔV /ΔT 3 µV/°C OS Input Bias Current I −60 −50 nA B −40°C ≤ T ≤ +85°C −80 +80 nA A −40°C ≤ T ≤ +125°C −500 +500 nA A Input Offset Current I −4 +1 +4 nA OS −40°C ≤ T ≤ +85°C −10 +10 nA A −40°C ≤ T ≤ +125°C −140 +140 nA A Input Voltage Range IVR −15 +15 V Common-Mode Rejection Ratio CMRR V = −15.0 V to +15.0 V 90 103 dB CM −40°C ≤ T ≤ +125°C 87 dB A Large Signal Voltage Gain A R = 100 kΩ, V = ±14.7 V 116 118 dB VO L O −40°C ≤ T ≤ +125°C 108 dB A R = 10 kΩ, V = ±14.7 V 102 104 dB L O −40°C ≤ T ≤ +125°C 93 dB A OUTPUT CHARACTERISTICS Output Voltage High V R = 100 kΩ to GND 14.970 14.980 V OH L −40°C ≤ T ≤ +125°C 14.950 V A R = 10 kΩ to GND 14.900 14.915 V L −40°C ≤ T ≤ +125°C 14.800 V A Output Voltage Low V R = 100 kΩ to GND −14.985 −14.980 V OL L −40°C ≤ T ≤ +125°C −14.965 V A R = 10 kΩ to GND −14.970 −14.950 V L −40°C ≤ T ≤ +125°C −14.940 V A Short-Circuit Limit I Source/sink ±20 mA SC Closed-Loop Impedance Z f = 1 MHz, A = +1 68 Ω OUT V POWER SUPPLY Power Supply Rejection Ratio PSRR V = 2.7 V to 36 V 98 112 dB SY −40°C ≤ T ≤ +125°C 90 dB A Supply Current per Amplifier I I = 0 mA 200 250 µA SY O −40°C ≤ T ≤ +125°C 350 µA A DYNAMIC PERFORMANCE Slew Rate SR R = 100 kΩ, C = 30 pF 0.4 V/µs L L Settling Time t To 0.01% 25 µs S Gain Bandwidth Product GBP 1.4 MHz Phase Margin Φ 69 Degrees M Channel Separation CS f = 1 kHz 100 dB NOISE PERFORMANCE Voltage Noise e p-p 0.1 Hz to 10 Hz 0.8 µV p-p n Voltage Noise Density e f = 1 kHz 30 nV/√Hz n Rev. B | Page 5 of 20 ADA4092-4 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 5. θ is specified for the device soldered on a 4-layer JEDEC standard JA Parameter Rating printed circuit board (PCB) with zero airflow. Supply Voltage 36 V Input Voltage Refer to the Input Table 6. Thermal Resistance Overvoltage Package Type θ θ Unit JA JC Protection 14-Lead TSSOP (RU-14) 112 35 °C/W section Differential Input Voltage ±V SY Input Current ±5 mA ESD CAUTION Output Short-Circuit Duration to GND Indefinite Storage Temperature Range −65°C to +150°C Operating Temperature Range −40°C to +125°C Junction Temperature Range −65°C to +150°C Lead Temperature (Soldering, 60 sec) 300°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. B | Page 6 of 20 ADA4092-4 TYPICAL PERFORMANCE CHARACTERISTICS 180 40 ADA4092-4 ADA4092-4 160 35 V = ±1.5V SY V = ±1.5V SY T = 25°C A T = 25°C A 140 30 120 25 100 20 80 15 60 10 40 5 20 0 0 –2 –1 0 1 2 3 4 5 6 7 8 TCV (μV/°C) OS OFFSET VOLTAGE (µV) Figure 2. Input Offset Voltage Distribution, 3 V Figure 5. TCV Distribution, 3 V OS 180 70 ADA4092-4 ADA4092-4 160 V = ±5V SY 60 V = ±5V SY T = 25°C A T = 25°C A 140 50 120 40 100 80 30 60 20 40 10 20 0 0 –2 –1 0 1 2 3 4 5 6 7 8 TCV (μV/°C) OS OFFSET VOLTAGE (µV) Figure 3. Input Offset Voltage Distribution, 10 V Figure 6. TCV Distribution, 10 V OS 70 180 ADA4092-4 ADA4092-4 160 V = ±15V SY 60 V = ±15V SY T = 25°C A T = 25°C A 140 50 120 40 100 80 30 60 20 40 10 20 0 –2 –1 0 1 2 3 4 5 6 7 8 TCV (μV/°C) OS OFFSET VOLTAGE (µV) Figure 7. TCV Distribution, 30 V Figure 4. Input Offset Voltage Distribution, 30 V OS Rev. B | Page 7 of 20 NUMBER OF PARTS NUMBER OF PARTS NUMBER OF PARTS –1200 –1200 –1200 –1000 –1000 –1000 –800 –800 –800 –600 –600 –600 –400 –400 –400 –200 –200 –200 0 0 0 200 200 200 400 400 400 600 600 600 800 800 800 1000 1000 1000 1200 1200 1200 08803-004 08803-003 08803-002 NUMBER OF AMPLIFIERS NUMBER OF AMPLIFIERS NUMBER OF AMPLIFIERS 08803-007 08803-006 08803-005 ADA4092-4 600 60 500 40 400 ADA4092-4 20 V = ±1.5V SY ADA4092-4 T = 25°C I OS I V = ±1.5V B– 300 SY T = 25°C A 0 200 –20 100 I B+ 0 –40 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 V (V) CM V (V) CM Figure 8. Input Offset Voltage vs. Common-Mode Voltage, 3 V Figure 11. Input Bias Current vs. Common-Mode Voltage, 3 V 600 60 500 ADA4092-4 40 V = ±5V SY T = 25°C 400 20 300 I OS 0 ADA4092-4 V = ±5V 200 SY T = 25°C A I B– –20 100 I B+ 0 –40 –5 –4 –3 –2 –1 0 1 2 3 4 5 –5 –4 –3 –2 –1 0 1 2 3 4 5 V (V) CM V (V) CM Figure 12. Input Bias Current vs. Common-Mode Voltage, 10 V Figure 9. Input Offset Voltage vs. Common-Mode Voltage, 10 V 600 60 500 40 ADA4092-4 400 I OS V = ±15V SY 20 T = 25°C ADA4092-4 V = ±15V 300 SY T = 25°C A I 0 B– 200 I B+ –20 100 –40 0 –15 –10 –5 0 5 10 15 –15 –10 –05 0 5 10 15 V (V) V (V) CM CM Figure 10. Input Offset Voltage vs. Common-Mode Voltage, 30 V Figure 13. Input Bias Current vs. Common-Mode Voltage, 30 V Rev. B | Page 8 of 20 V (µV) V (µV) V (µV) OS OS OS 08803-009 08803-010 08803-008 I (nA) I (nA) I (nA) B B B 08803-013 08803-012 08803-011 ADA4092-4 10k 120 ADA4092-4 100 V = ±1.5V SY PHASE T = 25°C A 80 1k 60 40 GAIN 100 20 0 V – V DD OH –20 V – V OL SS 10 –40 ADA4092-4 V = ±1.5V SY –60 T = 25°C A 1 –80 0.001 0.01 0.1 1 10 100 1k 10k 100k 1M 10M LOAD CURRENT (mA) FREQUENCY (Hz) Figure 14. Dropout Voltage vs. Load Current, 3 V Figure 17. Open-Loop Gain and Phase vs. Frequency, 3 V 10k 120 ADA4092-4 100 V = ±5V SY PHASE T = 25°C 80 A 1k 60 40 GAIN 20 100 0 V – V DD OH –20 V – V OL SS –40 10 ADA4092-4 –60 V = ±5V SY T = 25°C A –80 1 –100 0.001 0.01 0.1 1 10 100 1k 10k 100k 1M 10M LOAD CURRENT (mA) FREQUENCY (Hz) Figure 15. Dropout Voltage vs. Load Current, 10 V Figure 18. Open-Loop Gain and Phase vs. Frequency, 10 V 10k 140 ADA4092-4 120 V = ±15V SY T = 25°C 100 A PHASE 1k 80 60 40 GAIN 100 20 0 V – V DD OH –20 10 V – V OL SS ADA4092-4 –40 V = ±15V SY T = 25°C A –60 1 –80 0.001 0.01 0.1 1 10 100 1k 10k 100k 1M 10M LOAD CURRENT (mA) FREQUENCY (Hz) Figure 16. Dropout Voltage vs. Load Current, 30 V Figure 19. Open-Loop Gain and Phase vs. Frequency, 30 V Rev. B | Page 9 of 20 V TO RAIL (mV) V TO RAIL (mV) OUT V TO RAIL (mV) OUT OUT 08803-016 08803-015 08803-014 GAIN (dB) AND PHASE (Degrees) GAIN (dB) AND PHASE (Degrees) GAIN (dB) AND PHASE (Degrees) 08803-019 08803-017 08803-018 ADA4092-4 50 1k ADA4092-4 ADA4092-4 GAIN = +100 V = ±1.5V V = ±1.5V 40 SY SY T = 25°C T = 25°C A A 100 30 GAIN = +10 20 A = +100 V 10 10 A = +10 GAIN = +1 V 0 1 A = +1 V –10 0.1 –20 10 100 1k 10k 100k 1M 10M 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 20. Closed-Loop Gain vs. Frequency, 3 V Figure 23. Closed-Loop Output Impedance vs. Frequency, 3 V 50 1k ADA4092-4 ADA4092-4 GAIN = +100 V = ±5V V = ±5V SY 40 SY T = 25°C T = 25°C A A 30 100 GAIN = +10 20 A = +100 V 10 10 A = +10 V GAIN = +1 0 1 A = +1 V –10 0.1 –20 10 100 1k 10k 100k 1M 10M 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 21. Closed-Loop Gain vs. Frequency, 10 V Figure 24. Closed-Loop Output Impedance vs. Frequency, 10 V 50 1k ADA4092-4 GAIN = +100 ADA4092-4 V = ±15V 40 SY V = ±15V SY T = 25°C A T = 25°C A 100 30 GAIN = +10 20 A = +100 V 10 10 A = +10 V GAIN = +1 0 1 –10 A = +1 V –20 0.1 10 100 1k 10k 100k 1M 10M 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 22. Closed-Loop Gain vs. Frequency, 30 V Figure 25. Output Impedance vs. Frequency, 30 V Rev. B | Page 10 of 20 FREQUENCY (Hz) FREQUENCY (Hz) FREQUENCY (Hz) CLOSED-LOOP GAIN (dB) CLOSED-LOOP GAIN (dB) CLOSED-LOOP GAIN (dB) 08803-022 08803-021 08803-020 Z (Ω) Z (Ω) OUT Z (Ω) OUT OUT 08803-025 08803-024 08803-023 ADA4092-4 90 120 80 100 70 80 60 PSRR+ 60 50 40 ADA4092-4 40 PSRR– V = ±1.5V SY T = 25°C 30 A 20 20 ADA4092-4 V = ±1.5V SY 0 T = 25°C 10 A 0 –20 100 1k 10k 100k 1M 10M 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure 29. PSRR vs. Frequency, 3 V Figure 26. CMRR vs. Frequency, 3 V 100 120 90 100 80 80 70 PSRR+ 60 60 50 ADA4092-4 40 PSRR– 40 V = ±5V SY T = 25°C A 30 20 ADA4092-4 20 V = ±5V SY 0 T = 25°C A 10 –20 0 100 1k 10k 100k 1M 10M 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure 30. PSRR vs. Frequency, 10 V Figure 27. CMRR vs. Frequency, 10 V 120 100 90 100 80 80 70 PSRR+ 60 60 50 ADA4092-4 40 PSRR– 40 V = ±15V SY T = 25°C A 30 20 ADA4092-4 20 V = ±15V SY 0 T = 25°C A 10 –20 0 100 1k 10k 100k 1M 10M 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure 31. PSRR vs. Frequency, 30 V Figure 28. CMRR vs. Frequency, 30 V Rev. B | Page 11 of 20 CMRR (dB) CMRR (dB) CMRR (dB) 08803-028 08803-027 08803-026 PSRR (dB) PSRR (dB) PSRR (dB) 08803-031 08803-030 08803-029 ADA4092-4 2.0 0.06 1.5 0.04 1.0 0.02 0.5 0 0 ADA4092-4 –0.5 V = ±1.5V ADA4092-4 SY –0.02 T = 25°C A V = ±1.5V SY –1.0 R = 100kΩ L T = 25°C A C = 100pF L R = 100kΩ L –0.04 C = 100pF L –1.5 –2.0 –0.06 0 10 20 30 40 50 60 70 80 0 2 4 6 8 10 12 14 16 18 TIME (µs) TIME (µs) Figure 32. Large Signal Transient Response, 3 V Figure 35. Small Signal Transient Response, 3 V 6 0.06 4 0.04 2 0.02 0 0 ADA4092-4 V = ±5V SY T = 25°C ADA4092-4 –2 A –0.02 R = 100kΩ V = ±5V L SY C = 100pF T = 25°C L A R = 100kΩ L –4 –0.04 C = 100pF L –6 –0.06 0 20 40 60 80 100 120 140 160 0 2 4 6 8 10 12 14 16 18 TIME (µs) TIME (µs) Figure 33. Large Signal Transient Response, 10 V Figure 36. Small Signal Transient Response, 10 V 2.0 0.06 1.5 0.04 1.0 0.02 0.5 0 0 ADA4092-4 V = ±15V –0.5 SY ADA4092-4 T = 25°C –0.02 A V = ±15V SY R = 100kΩ L –1.0 T = 25°C A C = 100pF L R = 100kΩ L –0.04 C = 100pF –1.5 L –2.0 –0.06 40 80 120 160 200 0 0 2 4 6 8 10 12 14 16 18 TIME (µs) TIME (µs) Figure 34. Large Signal Transient Response, 30 V Figure 37. Small Signal Transient Response, 30 V Rev. B | Page 12 of 20 V (V) V (V) V (V) OUT OUT OUT 08803-034 08803-033 08803-032 V (V) V (V) V (V) OUT OUT OUT 08803-037 08803-036 08803-035 ADA4092-4 1.6 0 1.4 –0.2 1.2 –0.4 1.0 –0.6 0.8 –0.8 ADA4092-4 ADA4092-4 V = ±1.5V V = ±1.5V SY SY 0.6 T = 25°C –1.0 T = 25°C A A 0.4 –1.2 0.2 –1.4 0 –1.6 0 10 20 30 40 50 60 70 80 90 0 10 20 30 40 50 60 70 80 90 100 TIME (µs) TIME (µs) Figure 38. Positive Overload Recovery, 3 V Figure 41. Negative Overload Recovery, 3 V 6 0 5 –1 4 –2 3 –3 ADA4092-4 ADA4092-4 V = ±5V V = ±5V 2 SY SY T = 25°C T = 25°C A A –4 1 –5 0 –1 –6 0 10 20 30 40 50 60 70 90 0 10 20 30 40 50 60 70 80 90 TIME (µs) TIME (µs) Figure 39. Positive Overload Recovery, 10 V Figure 42. Negative Overload Recovery, 10 V 16 0 14 –2 12 –4 10 –6 8 –8 ADA4092-4 ADA4092-4 6 V = ±15V V = ±15V SY SY T = 25°C T = 25°C –10 A A 4 –12 2 –14 0 –16 –2 0 10 20 30 40 50 60 70 80 90 0 10 20 30 40 50 60 70 80 TIME (µs) TIME (µs) Figure 40. Positive Overload Recovery, 30 V Figure 43. Negative Overload Recovery, 30 V Rev. B | Page 13 of 20 V (V) V (V) OUT OUT V (V) OUT 08803-039 08803-040 08803-038 V (V) OUT V (V) V (V) OUT OUT 08803-043 08803-042 08803-041 ADA4092-4 0.5 1000 ADA4092-4 ADA4092-4 0.4 V = ±15V SY V = ±15V T = 25°C SY A T = 25°C 0.3 0.2 0.1 100 0 –0.1 –0.2 –0.3 –0.4 10 0 1 2 3 4 5 6 7 8 9 10 0.01 0.10 1 10 100 1000 TIME (µs) FREQUENCY (Hz) Figure 44. Peak-to-Peak Voltage Noise Figure 46. Voltage Noise Density 200 –50 180 –60 160 –70 140 –80 120 –90 100 –100 80 –110 ADA4092-4 60 T = 25°C A –120 ADA4092-4 40 V = ±1.5V, ±5V, ±15V SY T = 25°C –130 A 20 0 –140 0 4 8 12 16 20 24 28 32 36 20 100 1k 10k 50k V (V) FREQUENCY (Hz) SUPPLY Figure 47. Channel Separation vs. Frequency Figure 45. Supply Current vs. Supply Voltage Rev. B | Page 14 of 20 V (µV) OUT I (µA) SUPPLY 08803-045 08803-044 CHANNEL SEPARATION (dB) e (nV/√Hz) n 08803-047 08803-046 ADA4092-4 THEORY OF OPERATION A common practice in bipolar amplifiers to protect the input The ADA4092-4 is a single-supply, micropower amplifier transistors from large differential voltages is to include series featuring rail-to-rail inputs and outputs. To achieve wide input resistors and differential diodes. See Figure 49 for the full input and output ranges, these amplifiers employ unique input and protection circuitry. These diodes turn on whenever the differential output stages. voltage exceeds approximately 0.6 V. In this condition, current INPUT STAGE flows between the input pins, limited only by the two 5 kΩ resistors. Evaluate each application carefully to make sure that In Figure 48, the input stage comprises two differential pairs, a the increase in current does not affect performance. PNP pair (PNP input stage) and an NPN pair (NPN input stage). These input stages do not work in parallel. Instead, only one OUTPUT STAGE stage is on for any given input common-mode signal level. The The output stage in the ADA4092-4 device uses a PNP and an PNP stage (Transistor Q1 and Transistor Q2) is required to ensure NPN transistor, as do most output stages. However, Q32 and that the amplifier remains in the linear region when the input Q33, the output transistors, connect with their collectors to an voltage approaches and reaches the negative rail. Alternatively, output pin to achieve the rail-to-rail output swing. the NPN stage (Transistor Q5 and Transistor Q6) is needed for input voltages up to, and including, the positive rail. As the output voltage approaches either the positive or the negative rail, these transistors begin to saturate. Thus, the final For the majority of the input common-mode range, the PNP limit on output voltage is the saturation voltage of these transistors, stage is active, as shown in Figure 8 through Figure 13. Notice which is about 50 mV. The output stage has inherent gain arising that the V shifts and that the bias current switches direction at OS from the transistor output impedance, as well as any external load approximately 1.5 V below the positive rail. At voltages below this impedance; consequently, the open-loop gain of the op amp is level, the bias current flows out of the ADA4092-4 input, from dependent on the load resistance and decreases when the output the PNP input stage. However, above this voltage, the bias voltage is close to either rail. current enters the device due to the NPN stage. The actual mechanism within the amplifier for switching between the input stages comprises Q3, Q4, and Q7. As the input common-mode voltage increases, the emitters of Q1 and Q2 follow that voltage plus a diode drop. Eventually, the emitters of Q1 and Q2 are high enough to turn on Q3, which diverts the tail current away from the PNP input stage, turning it off. The tail current of the PNP pair is diverted to the Q4/Q7 current mirror to activate the NPN input stage, as shown in Figure 48. –IN Q32 Q3 Q16 Q5 Q6 +IN Q1 Q2 Q17 Q8 Q10 Q12 Q14 OUT Q9 Q11 Q13 Q15 Q18 Q19 Q33 Q4 Q7 Figure 48. Simplified Schematic Without Input Protection (See Figure 49) Rev. B | Page 15 of 20 08803-124 ADA4092-4 INPUT OVERVOLTAGE PROTECTION The ADA4092-4 has two different ESD circuits for enhanced Therefore, consider two conditions to determine which case is protection, as shown in Figure 49. the limiting factor. 1. Consider, for example, that when operating on ±15 V, the inputs can go +42 V above the negative supply rail. With the −V pin equal to −15 V, +42 V above this supply (the negative supply) is +27 V. 2. There is a restriction on the input current of 5 mA through +V a 5 kΩ resistor to the ESD structure to the positive rail. In the first condition, +27 V through the 5 kΩ resistor to +15 V gives a current of 2.4 mA. Thus, the DIAC is the limiting D3 D1 R1 factor. If the ADA4092-4 supply voltages are changed to ±5 V, D7 D5 D2 R2 then −5 V + 42 V = +37 V. However, +5 V + (5 kΩ × 5 mA) = D4 D8 D6 30 V. Thus, the normal resistor diode structure is the limitation when running on lower supply voltages. –V Additional resistance can be added externally in series with each input to protect against higher peak voltages; however, the additional thermal noise of the resistors must be considered. The flatband voltage noise of the ADA4092-4 is approximately 25 nV/√Hz, and a 5 kΩ resistor has a noise of 9 nV/√Hz. Adding an additional 5 kΩ resistor increases the total noise by less than Figure 49. Complete Input Protection Network 15% root sum square (rss). Therefore, maintain resistor values below this value (5 kΩ) when overall noise performance is critical. One circuit is a series resistor of 5 kΩ to the internal inputs and diodes (D1 and D2 or D5 and D6) from the internal inputs to the Note that this represents input protection under abnormal supply rails. The other protection circuit is a circuit with two conditions only. The correct amplifier operation input voltage DIACs (D3 and D4 or D7 and D8) to the supply rails. A DIAC range (IVR) is specified in Table 2, Table 3, and Table 4. can be considered a bidirectional Zener diode with a transfer COMPARATOR OPERATION characteristic, as shown in Figure 50. Although op amps are quite different from comparators, 5 occasionally an unused section of a dual or a quad op amp 4 can be pressed into service as a comparator; however, this is not recommended. For rail-to-rail output op amps, the output stage 3 is generally a ratioed current mirror with bipolar or MOSFET 2 transistors. With the part operating open loop, the second stage 1 increases the current drive to the ratioed mirror to close the loop, but it cannot, which results in an increase in supply current. With 0 three of the op amps operating normally and the fourth one in –1 comparator mode, the supply current increases by about 200 µA (see Figure 51). –2 1000 ONE COMPARATOR, V HIGH OUT –3 900 –50 –40 –30 –20 –10 0 10 20 30 40 50 VOLTAGE (V) ONE COMPARATOR, V LOW OUT 800 Figure 50. DIAC Transfer Characteristic 700 NORMAL OPERATION For a worst-case design analysis, consider two cases. The 600 ADA4092-4 has a normal ESD structure from the internal op 500 amp inputs to the supply rails. In addition, it has 42 V DIACs 400 from the external inputs to the rails, as shown in Figure 48. 300 200 100 0 0 4 8 12 16 20 24 28 32 36 V (V) SY Figure 51. Comparator Supply Current Rev. B | Page 16 of 20 CURRENT (mA) 08803-123 08803-100 I (µA) SY 08803-051 ADA4092-4 OUTLINE DIMENSIONS 5.10 5.00 4.90 14 8 4.50 6.40 4.40 BSC 4.30 1 7 PIN 1 0.65 BSC 1.05 1.20 1.00 0.20 MAX 0.80 0.09 0.75 0.15 8° 0.60 SEATING 0° 0.05 0.45 0.30 PLANE COPLANARITY 0.19 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AB-1 Figure 52. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown in millimeters ORDERING GUIDE 1 Model Temperature Range Package Description Package Option ADA4092-4ARUZ −40°C to +125°C 14-Lead Thin Shrink Small Outline Package [TSSOP] RU-14 ADA4092-4ARUZ-RL −40°C to +125°C 14-Lead Thin Shrink Small Outline Package [TSSOP] RU-14 1 Z = RoHS Compliant Part. Rev. B | Page 17 of 20 061908-A ADA4092-4 NOTES Rev. B | Page 18 of 20 ADA4092-4 NOTES Rev. B | Page 19 of 20 ADA4092-4 NOTES ©2010–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08803-0-6/11(B) Rev. B | Page 20 of 20