ANALOG DEVICES ADA4091-2

Precision Micropower, OVP, RRIO Operational Amplifier ADA4091-2/ADA4091-4 FEATURES PIN CONFIGURATIONS Single-supply operation: 3.0 V to 30 V OUTA 1 8 +V –INA 2 7 OUTB Wide input voltage range ADA4091-2 3 6 +INA TOP VIEW –INB Rail-to-rail output swing (Not to Scale) –V 4 5 +INB Low supply current: 200 μA/amplifier Wide bandwidth: 1.2 MHz Figure 1. 8-Lead, Narrow-Body SOIC (R-8) Slew rate: 0.46 V/μs OUTA 1 Low offset voltage: 250 μV maximum 8+V –INA 2 7OUTB ADA4091-2 No phase reversal +INA 3 6–INB TOP VIEW Overvoltage protection (OVP) (Not to Scale) –V 4 5+INB 25 V above/below supply rails at ±5 V 12 V above/below supply rails at ±15 V NOTES 1. IT IS RECOMMENDED TO CONNECT THE EXPOSED PAD TO V–. APPLICATIONS Figure 2. 8-Lead LFCSP (CP-8-9) Industrial process control 1 14 OUTA OUTD Battery-powered instrumentation 2 13 –INA –IND Power supply control and protection 3 12 +INA +IND ADA4091-4 Telecommunications 4 11 +V TOP VIEW –V (Not to Scale) Remote sensors +INB 5 10 +INC Low voltage strain gage amplifiers –INB 6 9 –INC DAC output amplifiers OUTB 7 8 OUTC Figure 3. 14-Lead TSSOP (RU-14) GENERAL DESCRIPTION The ADA4091-2 dual and ADA4091-4 quad are micropower, single-supply, 1.2 MHz bandwidth amplifiers featuring rail-to- rail inputs and outputs. They are guaranteed to operate from a –INA 1 12 –IND +3.0 V to +30 V single supply as well as from ±1.5 V to ±15 V +INA 2 ADA4091-4 11 +IND TOP dual supplies. V+ 3 10 V– VIEW +INB 4 9 +INC The ADA4091 family features a unique input stage that allows the input voltage to exceed either supply safely without any phase reversal or latch-up; this is called overvoltage protection, or OVP. Applications for these amplifiers include portable telecom- NOTES munications equipment, power supply control and protection, 1. NC = NO CONNECT. 2. IT IS RECOMMENDED TO CONNECT THE and interface for transducers with wide output ranges. Sensors EXPOSED PAD TO V–. requiring a rail-to-rail input amplifier include Hall effect, piezo- Figure 4. 16-Lead LFCSP (CP-16-17) electric, and resistive transducers. The ADA4091-2 is available in 8-lead, plastic SOIC and 8-lead The ability to swing rail-to-rail at both the input and output enables LFCSP packages. The ADA4091-4 is available in 14–lead TSSOP designers, for example, to build multistage filters in single-supply and 16-lead LFCSP surface-mount packages. systems and to maintain high signal-to-noise ratios (SNR). Table 1. Low Power, 36 V Operational Amplifiers The ADA4091 family is specified over the extended industrial Family Rail-to-Rail I/O PJFET Low Noise Single OP1177 temperature range of −40°C to +125°C. The ADA4091 family is Dual ADA4091-2 AD8682 OP2177 part of the growing selection of 36 V, low power op amps from Quad ADA4091-4 AD8684 OP4177 Analog Devices, Inc., (see Table 1). Rev. F Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2008–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 07671-001 07671-101 07671-103 07571-102 –INB 5 16 NC OUTB 6 15 OUTA 14 OUTD OUTC 7 8 –INC 13 NC ADA4091-2/ADA4091-4 TABLE OF CONTENTS Features .............................................................................................. 1 ESD Caution...................................................................................6 Applications ....................................................................................... 1 Typical Performance Characteristics ..............................................7 General Description ......................................................................... 1 Theory of Operation ...................................................................... 14 Pin Configurations ........................................................................... 1 Input Stage ................................................................................... 14 Revision History ............................................................................... 2 Output Stage ................................................................................ 14 Specif ica t ions ..................................................................................... 3 Input Overvoltage Protection ................................................... 15 Electrical Specifications ............................................................... 3 Outline Dimensions ....................................................................... 16 Absolute Maximum Ratings ............................................................ 6 Ordering Guide .......................................................................... 18 Thermal Resistance ...................................................................... 6 REVISION HISTORY 10/10—Rev. E. to Rev. F 7/09—Rev. A to Rev. B Changes to Features Section and General Description Section . 1 Added New Part ADA4091-4 ........................................... Universal Changes to Outline Dimensions ................................................... 17 Changes to Features Section, General Description Section, and Figure 4 ............................................................................................... 1 5/10—Rev. D. to Rev. E Added Figure 2, Renumbered Sequentially ................................... 1 Changes to Data Sheet Title ............................................................ 1 Changes to Table 1 ............................................................................. 1 Changes to Table 2, Input Characteristics, Offset Voltage .......... 3 Changes to Table 2 ............................................................................. 3 Changes to Table 3, Input Characteristics, Offset Voltage .......... 4 Changes to Table 3 ............................................................................. 4 Changes to Table 4, Input Characteristics, Offset Voltage .......... 5 Changes to Table 4 ............................................................................. 5 Changes to Table 5 ............................................................................. 6 4/10—Rev. C to Rev. D Changes to Table 6 ............................................................................. 6 Changes to Table 2, Added LFCSP to Input Characteristics ...... 3 Updated Outline Dimensions ....................................................... 16 Changes to Table 3, Added LFCSP to Input Characteristics ...... 4 Changes to Ordering Guide .......................................................... 16 Changes to Table 4, Added LFCSP to Input Characteristics ...... 5 7/09—Rev. 0 to Rev. A 10/09—Rev. B to Rev. C Changes to Data Sheet Title ............................................................. 1 Added 8-Lead LFCSP and 16-Lead LFCSP ..................... Universal Changes to Features .......................................................................... 1 Change to Features Section ............................................................. 1 Changes to Table 2 ............................................................................. 3 Updated Outline Dimensions ....................................................... 16 Changes to Table 3 ............................................................................. 4 Changes to Ordering Guide .......................................................... 18 Changes to Table 4 ............................................................................. 5 Added Input Current Parameter, Table 5 ....................................... 6 Added New Figure 12 and Figure 13, Renumbered Sequentially ........................................................................................ 8 Added New Figure 24 and Figure 25 ........................................... 10 Added New Figure 36 and Figure 37 ........................................... 12 Added New Figure 43 .................................................................... 13 Changes to Input Overvoltage Protection Section ..................... 15 Changes to Ordering Guide .......................................................... 16 10/08—Revision 0: Initial Version Rev. F | Page 2 of 20 ADA4091-2/ADA4091-4 SPECIFICATIONS ELECTRICAL SPECIFICATIONS V = ±1.5 V, V = 0.0 V, T = 25°C, unless otherwise noted. SY CM A Table 2. Parameter Symbol Test Conditions/Comments Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage VOS −250 −40 +250 μV ADA4091-4 LFCSP package −400 −40 +400 μV −40°C ≤ TA ≤ +125°C −600 +600 μV Offset Voltage Drift ∆V /∆T 2.5 μV/°C OS Input Bias Current I −55 −44 nA B −40°C ≤ T ≤ +85°C −55 +55 nA A −40°C ≤ TA ≤ +125°C −275 +275 nA Input Offset Current IOS −3 0.5 +3 nA −40°C ≤ TA ≤ +85°C −5 +5 nA −40°C ≤ T ≤ +125°C −75 +75 nA A Input Voltage Range −1.5 +1.5 V Common-Mode Rejection Ratio CMRR VCM = −1.35 V to +1.35 V 84 100 dB −40°C ≤ TA ≤ +125°C 78 dB Large Signal Voltage Gain AVO RL = 100 kΩ, VO = −1.2 V to +1.2 V 106 113 dB −40°C ≤ T ≤ +125°C 101 dB A R = 10 kΩ, V = −1.2 V to +1.2 V 92 94 dB L O −40°C ≤ T ≤ +125°C 85 dB A OUTPUT CHARACTERISTICS Output Voltage High VOH RL = 100 kΩ to GND 1.490 1.495 V −40°C ≤ T ≤ +125°C 1.490 V A R = 10 kΩ to GND 1.475 1.485 V L −40°C to +125°C 1.455 V Output Voltage Low VOL RL = 100 kΩ to GND −1.499 −1.495 V −40°C ≤ TA ≤ +125°C −1.495 V R = 10 kΩ to GND −1.495 −1.490 V L −40°C ≤ T ≤ +125°C −1.490 V A Short-Circuit Limit I Source/sink ±31 mA SC Open-Loop Impedance ZOUT f = 1 MHz, AV = 1 102 Ω POWER SUPPLY Power Supply Rejection Ratio PSRR V = 2.7 V to 36 V 108 126 dB SY −40°C ≤ T ≤ +125°C 100 dB A Supply Current per Amplifier ISY IO = 0 mA 165 200 μA −40°C ≤ TA ≤ +125°C 300 μA DYNAMIC PERFORMANCE Slew Rate SR R = 100 kΩ, C = 30 pF 0.46 V/μs L L Settling Time tS To 0.01% 22 μs Gain Bandwidth Product GBP 1.22 MHz Phase Margin ΦM 69 Degrees NOISE PERFORMANCE Voltage Noise en p-p 0.1 Hz to 10 Hz 0.8 μV p-p Voltage Noise Density en f = 1 kHz 24 nV/√Hz Rev. F | Page 3 of 20 ADA4091-2/ADA4091-4 V = ±5.0 V, V = 0.0 V, T = 25°C, unless otherwise noted. SY CM A Table 3. Parameter Symbol Test Conditions/Comments Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage VOS −250 −45 +250 μV ADA4091-4 LFCSP package −400 −40 +400 μV −40°C ≤ TA ≤ +125°C −600 +600 μV Offset Voltage Drift ∆V/∆T 2.5 μV/°C OS Input Bias Current I −60 −50 nA B −40°C ≤ T ≤ +85°C −80 +80 nA A −40°C ≤ TA ≤ +125°C −350 +350 nA Input Offset Current IOS −3 0.5 +3 nA −40°C ≤ TA ≤ +85°C −7 +7 nA −40°C ≤ T ≤ +125°C −100 +100 nA A Input Voltage Range −5 +5 V Common-Mode Rejection Ratio CMRR V = −4.85 V to +4.85 V 95 113 dB CM −40°C ≤ TA ≤ +125°C 88 dB Large Signal Voltage Gain AVO RL = 100 kΩ, VO = ±4.7 V 113 117 dB −40°C ≤ T ≤ +125°C 106 dB A R = 10 kΩ, V = ±4.7 V 98 100 dB L O −40°C ≤ T ≤ +125°C 90 dB A OUTPUT CHARACTERISTICS Output Voltage High VOH RL = 100 kΩ to GND 4.980 4.990 V −40°C ≤ T ≤ +125°C 4.980 V A R = 10 kΩ to GND 4.950 4.960 V L −40°C ≤ TA ≤ +125°C 4.900 V Output Voltage Low VOL RL = 100 kΩ to GND −4.998 −4.990 V −40°C ≤ TA ≤ +125°C −4.980 V R = 10 kΩ to GND −4.990 −4.980 V L −40°C ≤ T ≤ +125°C −4.975 V A Short-Circuit Limit I Source/sink ±20 mA SC Open-Loop Impedance ZOUT f = 1 MHz, AV = 1 77 Ω POWER SUPPLY Power Supply Rejection Ratio PSRR V = 2.7 V to 36 V 108 126 dB SY −40°C ≤ T ≤ +125°C 100 dB A Supply Current per Amplifier ISY IO = 0 mA 180 225 μA −40°C ≤ TA ≤ +125°C 300 μA DYNAMIC PERFORMANCE Slew Rate SR R = 100 kΩ, C = 30 pF 0.46 V/μs L L Settling Time tS To 0.01% 22 μs Gain Bandwidth Product GBP 1.22 MHz Phase Margin ΦM 70 Degrees NOISE PERFORMANCE Voltage Noise e p-p 0.1 Hz to 10 Hz 0.8 μV p-p n Voltage Noise Density en f = 1 kHz 24 nV/√Hz Rev. F | Page 4 of 20 ADA4091-2/ADA4091-4 V = ±15.0 V, V = 0.0 V, V = 0.0 V, T = 25°C, unless otherwise noted. SY CM O A Table 4. Parameter Symbol Test Conditions/Comments Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage VOS −250 −35 +250 μV ADA4091-4 LFCSP package −400 −40 +400 μV −40°C ≤ T ≤ +125°C −600 +600 μV A Offset Voltage Drift ∆V /∆T 3.0 μV/°C OS Input Bias Current I −60 −50 nA B −40°C ≤ TA ≤ +85°C −80 +80 nA −40°C ≤ TA ≤ +125°C −510 +510 nA Input Offset Current IOS −3 0.5 +3 nA −40°C ≤ T ≤ +85°C −10 +10 nA A −40°C ≤ T ≤ +125°C −140 +140 nA A Input Voltage Range −15 +15 V Common-Mode Rejection Ratio CMRR VCM = −14.85 V to +14.85 V 104 121 dB −40°C ≤ TA ≤ +125°C 95 dB Large Signal Voltage Gain A R = 100 kΩ, V = ±14.7 V 116 119 dB VO L O −40°C ≤ T ≤ +125°C 108 dB A R = 10 kΩ, V = ±14.7 V 102 104 dB L O −40°C ≤ TA ≤ +125°C 93 dB OUTPUT CHARACTERISTICS Output Voltage High V R = 100 kΩ to GND 14.975 14.980 V OH L −40°C ≤ T ≤ +125°C 14.950 V A RL = 10 kΩ to GND 14.900 14.920 V −40°C ≤ TA ≤ +125°C 14.800 V Output Voltage Low VOL RL = 100 kΩ to GND −14.996 −14.990 V −40°C ≤ T ≤ +125°C −14.985 V A R = 10 kΩ to GND −14.975 −14.950 V L −40°C ≤ T ≤ +125°C −14.940 V A Short-Circuit Limit ISC Source/sink ±20 mA Open-Loop Impedance ZOUT f = 1 MHz, AV = 1 71 Ω POWER SUPPLY Power Supply Rejection Ratio PSRR V = 2.7 V to 36 V 108 126 dB SY −40°C ≤ TA ≤ +125°C 100 dB Supply Current per Amplifier ISY IO = 0 mA 200 250 μA −40°C ≤ TA ≤ +125°C 350 μA DYNAMIC PERFORMANCE Slew Rate SR RL = 100 kΩ, CL = 30 pF 0.46 V/μs Settling Time tS To 0.01% 22 μs Gain Bandwidth Product GBP 1.27 MHz Phase Margin Φ 72 Degrees M Channel Separation CS f = 1 kHz 100 dB NOISE PERFORMANCE Voltage Noise en p-p 0.1 Hz to 10 Hz 0.8 μV p-p Voltage Noise Density e f = 1 kHz 25 nV/√Hz n Rev. F | Page 5 of 20 ADA4091-2/ADA4091-4 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 5. θ is specified for the device soldered on a 4-layer JEDEC standard JA Parameter Rating PCB with zero airflow. The exposed pad is soldered to the Supply Voltage 36 V application board. Input Voltage Refer to the Input Overvoltage Protection Table 6. Thermal Resistance section Package Type θ θ Unit 1 JA JC Differential Input Voltage ±V SY 8-Lead SOIC (R-8) 155 45 °C/W Input Current ±5 mA 14-Lead TSSOP (RU-14) 112 35 °C/W Output Short-Circuit Duration to GND Indefinite 8-Lead LFCSP (CP-8-9) 75 12 °C/W Storage Temperature Range −65°C to +150°C 16-Lead LFCSP (CP-16-17) 55 14 °C/W Operating Temperature Range −40°C to +125°C Junction Temperature Range −65°C to +150°C ESD CAUTION Lead Temperature (Soldering, 60 sec) 300°C 1 Input current should be limited to ±5 mA. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. F | Page 6 of 20 ADA4091-2/ADA4091-4 TYPICAL PERFORMANCE CHARACTERISTICS 200 10,000 ADA4091-2 180 T = 25°C A V = ±1.5V SY 160 1000 140 120 100 100 V – V DD OH 80 10 60 V – V OL SS 40 1 20 ADA4091-2 V = ±1.5V SY 0 0.1 –250 –200 –150 –100 –50 0 50 100 150 200 250 0.001 0.01 0.1 1 10 100 V (µV) LOAD CURRENT (mA) OS Figure 5. Input Offset Voltage Distribution Figure 8. Dropout Voltage vs. Load Current 300 100 100 ADA4091-2 PHASE –40°C ≤ T ≤ +125°C A V = ±1.5V SY 250 80 80 200 60 60 GAIN 150 40 40 100 20 20 ADA4091-2 50 0 0 V = ±1.5V SY R = 1MΩ L C = 35pF L 0 –20 –20 –1 01 23 45 678 1k 10k 100k 1M 10M TCV (µV/°C) OS FREQUENCY (Hz) Figure 6. TCVOS Distribution Figure 9. Open-Loop Gain and Phase vs. Frequency 350 50 ADA4091-2 V = ±1.5V SY 300 A = 100 V 40 250 +125°C 30 200 A = 10 V 150 20 100 10 50 +85°C A = 1 V 0 0 –50 ADA4091-2 –10 V = ±1.5V SY –100 +25°C R = 1MΩ L –40°C C = 35pF L –150 –20 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 10 100 1k 10k 100k 1M 10M V (V) FREQUENCY (Hz) CM Figure 7. Input Bias Current vs. Common-Mode Voltage Figure 10. Closed-Loop Gain vs. Frequency Rev. F | Page 7 of 20 I (nA) NUMBER OF AMPLIFIERS NUMBER OF AMPLIFIERS B 07671-033 07671-035 07671-034 OPEN-LOOP GAIN (dB) CLOSED-LOOP GAIN (dB) V TO RAIL (mV) OUT 07671-010 PHASE (Degrees) 07671-017 07671-007 ADA4091-2/ADA4091-4 3.0 1k 2.5 100 2.0 A = 100 V 10 1.5 A = 10 V 1.0 A = 1 1 V ADA4091-2 0.5 ADA4091-2 V = ±1.5V SY T = 25°C V = 2.8V p-p A IN R = 100kΩ V = ±1.5V SY L 0.1 0 10 100 1k 10k 100k 1M 10M 100 1k 10k 100k 1M FREQUENCY (Hz) FREQUENCY (Hz) Figure 11. Output Impedance vs. Frequency Figure 14. Output Swing vs. Frequency 2.0 1.6 1.4 1.5 1.2 1.0 1.0 0.5 0.8 0 ADA4091-2 0.6 V = ±1.5V SY –0.5 T = 25°C A R = 100kΩ 0.4 L C = 100pF L –1.0 A = +1 V 0.2 ADA4091-2 –1.5 0 T = 25°C A V = ±1.5V SY –2.0 –0.2 0 5 10 15 20 25 30 35 40 45 50 0 102030 40 50 60 7080 90 TIME (µs) TIME (µs) Figure 12. Large Signal Transient Response Figure 15. Positive Overload Recovery 0.06 0 –0.2 0.04 –0.4 0.02 –0.6 0 ADA4091-2 –0.8 V = ±1.5V SY T = 25°C A –0.02 R = 100kΩ L –1.0 C = 100pF L A = +1 V –0.04 –1.2 ADA4091-2 –0.06 –1.4 T = 25°C A V = ±1.5V SY –0.08 –1.6 0123456789 1011121314151617181920 0 10 203040 50 60 708090 TIME (µs) TIME (µs) Figure 16. Negative Overload Recovery Figure 13. Small Signal Transient Response Rev. F | Page 8 of 20 V (V) OUT V (V) Z (Ω) OUT OUT 07671-025 07671-013 07671-028 V SWING (V) OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) OUT 07671-045 07671-051 07671-036 ADA4091-2/ADA4091-4 225 0.06 ADA4091-2 T = 25°C A 200 V = ±5V 0.04 SY 175 0.02 150 ADA4091-2 0 125 V = ±5V SY T = 25°C A R = 100kΩ L 100 –0.02 C = 100pF L A = +1 V 75 –0.04 50 –0.06 25 0 –0.08 –250 –200 –150 –100 –50 0 50 100 150 200 250 0123456789 1011121314151617181920 V (µV) TIME (µs) OS Figure 17. Input Offset Voltage Distribution Figure 20. Small Signal Transient Response 400 500 ADA4091-2 ADA4091-2 V = ±5V –40°C ≤ T ≤ +125°C SY A 350 V = ±5V SY 400 300 300 250 200 200 +125°C 100 150 +85°C +25°C 0 100 –100 50 –40°C 0 –200 –1 01 234 56 78 –5 –4 –3 –2 –1 014 2 3 5 TCV (µV/°C) V (V) OS CM Figure 18. TCV Distribution OS Figure 21. Input Bias Current vs. Common-Mode Voltage 100 100 6 PHASE 80 80 4 60 60 2 GAIN 40 40 0 ADA4091-2 V = ±5V SY T = 25°C A R = 100kΩ L 20 20 –2 C = 100pF L A = +1 V ADA4091-2 0 0 –4 V = ±5V SY R = 1MΩ L C = 35pF L –20 –20 –6 0 5 10 15 20 25 30 35 40 45 50 1k 10k 100k 1M 10M TIME (µs) FREQUENCY (Hz) Figure 19. Large Signal Transient Response Figure 22. Open-Loop Gain and Phase vs. Frequency Rev. F | Page 9 of 20 V (V) NUMBER OF AMPLIFIERS NUMBER OF AMPLIFIERS OUT 07671-026 07671-038 07671-037 OPEN-LOOP GAIN (dB) V (V) I (nA) OUT B 07671-032 07671-029 PHASE (Degrees) 07671-005 ADA4091-2/ADA4091-4 1k 50 A = 100 V 40 100 30 A = 10 V 20 A = 100 V 10 10 A = 1 V A = 10 V 0 1 ADA4091-2 –10 ADA4091-2 V = ±5V SY A = 1 V R = 1MΩ T = 25°C L A C = 35pF V = ±5V L SY 0.1 –20 10 100 1k 10k 100k 1M 10M 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure 23. Output Impedance vs. Frequency Figure 26. Closed-Loop Gain vs. Frequency 10 6 9 5 8 7 4 6 5 3 4 2 3 2 ADA4091-2 1 ADA4091-2 V = ±5V SY 1 T = 25°C V = 9.8V p-p A IN R = 100kΩ V = ±5V L SY 0 0 100 1k 10k 100k 1M 0 102030 40 50 60 7080 90 TIME (µs) FREQUENCY (Hz) Figure 24. Output Voltage Swing vs. Frequency Figure 27. Positive Overload Recovery 10,000 1 0 1000 –1 V – V DD OH 100 –2 V – V OL SS –3 10 –4 1 ADA4091-2 –5 T = 25°C A ADA4091-2 V = ±5V SY V = ±5V SY 0.1 –6 0.001 0.01 0.1 1 10 100 0 10 20 30 40 50 60 70 80 TIME (µs) LOAD CURRENT (mA) Figure 28. Negative Overload Recovery Figure 25. Dropout Voltage vs. Load Current Rev. F | Page 10 of 20 V TO RAIL (mV) V SWING (V) Z (Ω) OUT OUT OUT 07671-018 07671-015 07671-012 CLOSED-LOOP GAIN (dB) OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 07671-046 07671-047 07671-009 ADA4091-2/ADA4091-4 250 100 100 ADA4091-2 PHASE T = 25°C A V = ±15V SY 80 80 200 60 60 150 GAIN 40 40 100 20 20 50 ADA4091-2 0 0 V = ±15V SY R = 1MΩ L C = 35pF L 0 –20 –20 –250 –200 –150 –100 –50 0 50 100 150 200 250 1k 10k 100k 1M 10M V (µV) OS FREQUENCY (Hz) Figure 29. Input Offset Voltage Distribution Figure 32. Open-Loop Gain and Phase vs. Frequency 350 20 ADA4091-2 –40°C ≤ T ≤ +125°C A 15 300 V = ±15V SY 10 250 5 200 0 ADA4091-2 V = ±15V SY 150 T = 25°C A –5 R = 100kΩ L C = 100pF L A = +1 100 V –10 50 –15 0 –20 –1 0 12345678 –25 0 25 50 75 100 125 150 175 200 TCV (µV/°C) TIME (µs) OS Figure 30. TCV Distribution OS Figure 33. Large Signal Transient Response 700 0.06 ADA4091-2 V = ±15V SY 600 0.04 500 0.02 400 +125°C 300 0 ADA4091-2 V = ±15V SY 200 T = 25°C A R = 100kΩ L –0.02 +85°C C = 100pF 100 L +25°C A = +1 V 0 –0.04 –100 –40°C –0.06 –200 –300 –0.08 –15 –10 –5 0 5 10 15 0123456789 1011121314151617181920 V (V) TIME (µs) CM Figure 31. Input Bias Current vs. Common-Mode Voltage Figure 34. Small Signal Transient Response Rev. F | Page 11 of 20 I (nA) NUMBER OF AMPLIFIERS NUMBER OF AMPLIFIERS B 07671-031 07671-042 07671-041 OPEN-LOOP GAIN (dB) V (V) OUT V (V) OUT 07671-027 07671-030 PHASE (Degrees) 07671-006 ADA4091-2/ADA4091-4 35 50 A = 100 V 40 30 30 25 A = 10 V 20 20 10 15 A = 1 V 0 10 –10 ADA4091-2 ADA4091-2 5 V = ±15V V = ±15V SY –20 SY V = 29.8V p-p R = 1MΩ IN L R = 100kΩ C = 35pF L L 0 –30 100 1k 10k 100k 1M 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure 35. Output Voltage Swing vs. Frequency Figure 38. Closed-Loop Gain vs. Frequency 10,000 16 14 1000 12 10 V – V DD OH 100 8 V – V OL SS 6 10 4 2 1 ADA4091-2 0 T = 25°C ADA4091-2 A V = ±15V V = ±15V SY SY 0.1 –2 0.001 0.01 0.1 1 10 100 0 102030 40 50 60 7080 90 LOAD CURRENT (mA) TIME (µs) Figure 36. Dropout Voltage vs. Load Current Figure 39. Positive Overload Recovery 1k 2 0 –2 100 –4 –6 A = 100 V 10 –8 –10 A = 10 V 1 –12 ADA4091-2 ADA4091-2 A = 1 V –14 T = 25°C T = 25°C A A V = ±15V V = ±15V SY SY 0.1 –16 10 100 1k 10k 100k 1M 10M 01020 30 40 50 60 70 80 TIME (µs) FREQUENCY (Hz) Figure 40. Negative Overload Recovery Figure 37. Output Impedance vs. Frequency Rev. F | Page 12 of 20 Z (Ω) V TO RAIL (mV) V SWING (V) OUT OUT OUT 07671-011 07671-019 07671-016 CLOSED-LOOP GAIN (dB) OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 07671-048 07671-049 07671-008 ADA4091-2/ADA4091-4 100 0.5 ADA4091-2 V = ±1.5V, ±5V, ±15V SY 0.4 80 0.3 0.2 60 0.1 PSRR– PSRR+ 40 0 –0.1 20 –0.2 –0.3 0 –0.4 ADA4091-2 V = ±15V SY –20 –0.5 0 1 23 45 67 8 9 10 100 1k 10k 100k 1M 10M TIME (Seconds) FREQUENCY (Hz) Figure 41.Peak-to-Peak Voltage Noise Figure 44. PSRR vs. Frequency –60 500 ADA4091-2 ADA4091-2 T = 25°C V = ±15V A SY 450 –70 400 –80 350 300 –90 250 –100 200 150 –110 100 –120 50 –130 0 10 100 1k 10k 100k 0 5 10 15 20 25 30 35 FREQUENCY (Hz) V (V) SY Figure 42. Channel Separation vs. Frequency Figure 45. Supply Current vs. Supply Voltage 110 1k ADA4091-2 V = ±5V, ±15V 100 SY 90 80 70 V = ±1.5V SY 60 100 50 40 30 20 ADA4091-2 T = 25°C 10 A V = ±5V SY 0 10 100 1k 10k 100k 1M 10M 0.01 0.1 1 10 100 1k FREQUENCY (Hz) FREQUENCY (Hz) Figure 43. CMRR vs. Frequency Figure 46. Voltage Noise Density Rev. F | Page 13 of 20 CMRR (dB) CHANNEL SEPARATION (dB) NOISE (µV p-p) 07671-002 07671-044 07671-043 I (µA) PSRR (dB) SY VOLTAGE NOISE (nV/ Hz) 07671-050 07671-004 07671-003 ADA4091-2/ADA4091-4 THEORY OF OPERATION Q1 and Q2 are high enough to turn on Q3, which diverts the The ADA4091 family is a single-supply, micropower amplifier tail current away from the PNP input stage, turning it off. The featuring rail-to-rail inputs and outputs. To achieve wide input tail current of the PNP pair is diverted to the Q4/Q7 current and output ranges, these amplifiers employ unique input and mirror to activate the NPN input stage. output stages. A common practice in bipolar amplifiers to protect the input INPUT STAGE transistors from large differential voltages is to include series In Figure 47, the input stage comprises two differential pairs, a resistors and differential diodes. See Figure 48 for the full input PNP pair (PNP input stage) and an NPN pair (NPN input protection circuitry. These diodes turn on whenever the diffe- stage). These input stages do not work in parallel. Instead, only rential voltage exceeds approximately 0.6 V. In this condition, one stage is on for any given input common-mode signal level. current flows between the input pins, limited only by the two The PNP stage (Transistor Q1 and Transistor Q2) is required to 5 kΩ resistors. Evaluate each application carefully to make sure ensure that the amplifier remains in the linear region when the that the increase in current does not affect performance. input voltage approaches and reaches the negative rail. Alter- OUTPUT STAGE natively, the NPN stage (Transistor Q5 and Transistor Q6) is needed for input voltages up to, and including, the positive rail. The output stage in the ADA4091-x device uses a PNP and an NPN transistor, as do most output stages. However, Q32 For the majority of the input common-mode range, the PNP and Q33, the output transistors, connect with their collectors stage is active, as shown in Figure 7, Figure 21, and Figure 31. to the output pin to achieve the rail-to-rail output swing. Notice that the bias current switches direction at approximately 1.5 V below the positive rail. At voltages below this level, the As the output voltage approaches either the positive or negative bias current flows out of the ADA4091-x input, from the PNP rail, these transistors begin to saturate. Thus, the final limit input stage. Above this voltage, however, the bias current enters on output voltage is the saturation voltage of these transistors, the device, due to the NPN stage. The actual mechanism within which is about 50 mV. The output stage has inherent gain arising the amplifier for switching between the input stages comprises from the transistor output impedance, as well as any external load Transistor Q3, Transistor Q4, and Transistor Q7. As the input impedance; consequently, the open-loop gain of the op amp is common-mode voltage increases, the emitters of Q1 and Q2 dependent on the load resistance and decreases when the output follow that voltage plus a diode drop. Eventually, the emitters of voltage is close to either rail. –IN Q32 Q3 Q16 +IN Q1 Q2 Q5 Q6 Q17 Q8 Q10 Q12 Q14 OUT Q9 Q11 Q13 Q15 Q18 Q19 Q33 Q4 Q7 Figure 47. Simplified Schematic Without Input Protection (see Figure 48) Rev. F | Page 14 of 20 07671-024 ADA4091-2/ADA4091-4 INPUT OVERVOLTAGE PROTECTION The ADA4091-x has two different ESD circuits for enhanced For a worst-case design analysis, consider two cases. The protection, as shown in Figure 48. ADA4091-x has a normal ESD structure from the internal op amp inputs to the supply rails. In addition, it has 42 V DIACs from the external inputs to the rails, as shown in Figure 47. Therefore, two conditions need to be considered to determine which case is the limiting factor. • Condition 1. Consider, for example, that when operating +V on ±15 V, the inputs can go +42 V above the negative supply rail. With the −V pin equal to −15 V, +42 V above D3 D1 R1 this supply (the negative supply) is +27 V. D7 D5 D2 R2 • Condition 2. There is a restriction on the input current of D4 D8 D6 5 mA through a 5 kΩ resistor to the ESD structure to the positive rail. In Condition 1, +27 V through the 5 kΩ resistor to +15 V gives a current of 2.4 mA. Thus, the –V DIAC is the limiting factor. If the ADA4091-x supply voltages are changed to ±5 V, then −5 V + 42 V = +37 V. However, +5 V + (5 kΩ × 5 mA) = 30 V. Thus, the normal resistor diode structure is the limitation when running on lower supply voltages. Additional resistance can be added externally in series with Figure 48. Complete Input Protection Network each input to protect against higher peak voltages; however, the One circuit is a series resistor of 5 kΩ to the internal inputs and additional thermal noise of the resistors must be considered. diodes (D1 and D2 or D5 and D6) from the internal inputs to The flatband voltage noise of the ADA4091-x is approximately the supply rails. The other protection circuit is a circuit with 24 nV/√Hz, and a 5 kΩ resistor has a noise of 9 nV/√Hz. Adding two DIACs (D3 and D4 or D7 and D8) to the supply rails. A an additional 5 kΩ resistor increases the total noise by less than DIAC can be considered a bidirectional Zener diode with a 15% root sum square (rss). Therefore, maintain resistor values transfer characteristic, as shown in Figure 49. below this value (5 kΩ) when overall noise performance is critical. 5 Note that this represents input protection under abnormal con- 4 ditions only. The correct amplifier operation input voltage range (IVR) is specified in Table 2, Table 3, and Table 4. 3 2 1 0 –1 –2 –3 –50 –40 –30 –20 –10 0 10 20 30 40 50 VOLTAGE (V) Figure 49. DIAC Transfer Characteristic Rev. F | Page 15 of 20 CURRENT (mA) 07671-023 07671-100 ADA4091-2/ADA4091-4 OUTLINE DIMENSIONS 5.00 (0.1968) 4.80 (0.1890) 85 6.20 (0.2441) 4.00 (0.1574) 1 5.80 (0.2284) 3.80 (0.1497) 4 1.27 (0.0500) 0.50 (0.0196) 45° BSC 1.75 (0.0688) 0.25 (0.0099) 1.35 (0.0532) 0.25 (0.0098) 8° 0.10 (0.0040) 0° 0.51 (0.0201) COPLANARITY 1.27 (0.0500) 0.10 0.31 (0.0122) 0.25 (0.0098) SEATING 0.40 (0.0157) PLANE 0.17 (0.0067) COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 50. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 3.25 0.60 MAX 3.00 SQ 0.50 2.75 BSC 0.60 MAX 5 8 2.95 EXPOSED 1.60 2.75 SQ PAD PIN 1 1.50 2.55 INDICATOR 1.40 4 1 PIN 1 0.50 TOP VIEW BOTTOM VIEW INDICATOR 2.23 0.40 2.13 0.30 12° MAX 0.70 MAX 2.03 0.90 MAX 0.65TYP 0.85 NOM 0.05 MAX FOR PROPER CONNECTION OF 0.01 NOM THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND 0.30 SEATING FUNCTION DESCRIPTIONS PLANE 0.23 SECTION OF THIS DATA SHEET. 0.20 REF 0.18 Figure 51. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD] 3 mm × 3 mm Body, Very Thin, Dual Lead (CP-8-9) Dimensions shown in millimeters Rev. F | Page 16 of 20 012407-A 051909-A ADA4091-2/ADA4091-4 5.10 5.00 4.90 14 8 4.50 6.40 4.40 BSC 4.30 1 7 PIN 1 0.65 BSC 1.05 1.20 1.00 0.20 MAX 0.80 0.09 0.75 0.15 8° 0.60 SEATING 0° 0.05 0.45 0.30 PLANE COPLANARITY 0.19 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AB-1 Figure 52. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown in millimeters 4.10 0.35 4.00 SQ 0.30 3.90 PIN 1 0.25 INDICATOR 13 16 0.65 12 BSC 1 EXPOSED 2.70 PAD 2.60 SQ 2.50 4 9 8 5 0.45 0.25 MIN TOP VIEW BOTTOM VIEW 0.40 0.35 0.80 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO 0.75 0.05 MAX THE PIN CONFIGURATION AND 0.70 FUNCTION DESCRIPTIONS 0.02 NOM SECTION OF THIS DATA SHEET. COPLANARITY SEATING 0.08 PLANE 0.20 REF COMPLIANT TO JEDEC STANDARDS MO-220-WGGC. Figure 53. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 4 mm × 4 mm Body, Very Very Thin Quad (CP-16-17) Dimensions are millimeters Rev. F | Page 17 of 20 PIN 1 INDICATOR 012909-B 061908-A ADA4091-2/ADA4091-4 ORDERING GUIDE 1 Model Temperature Range Package Description Package Option Branding ADA4091-2ARZ −40°C to +125°C 8-Lead Standard Small Outline Package (SOIC_N) R-8 ADA4091-2ARZ-R7 −40°C to +125°C 8-Lead Standard Small Outline Package (SOIC_N) R-8 ADA4091-2ARZ-RL −40°C to +125°C 8-Lead Standard Small Outline Package (SOIC_N) R-8 ADA4091-2ACPZ-R2 −40°C to +125°C 8-Lead Frame Chip Scale Package (LFCSP_VD) CP-8-9 A1Z ADA4091-2ACPZ-R7 −40°C to +125°C 8-Lead Frame Chip Scale Package (LFCSP_VD) CP-8-9 A1Z ADA4091-2ACPZ-RL −40°C to +125°C 8-Lead Frame Chip Scale Package (LFCSP_VD) CP-8-9 A1Z ADA4091-4ARUZ −40°C to +125°C 14-Lead Thin Shrink Small Outline Package (TSSOP) RU-14 ADA4091-4ARUZ-RL −40°C to +125°C 14-Lead Thin Shrink Small Outline Package (TSSOP) RU-14 ADA4091-4ACPZ-R2 −40°C to +125°C 16-Lead Lead Frame Chip Scale Package (LFCSP_WQ) CP-16-17 ADA4091-4ACPZ-R7 −40°C to +125°C 16-Lead Lead Frame Chip Scale Package (LFCSP_WQ) CP-16-17 ADA4091-4ACPZ-RL −40°C to +125°C 16-Lead Lead Frame Chip Scale Package (LFCSP_WQ) CP-16-17 1 Z = RoHS Compliant Part. Rev. F | Page 18 of 20 ADA4091-2/ADA4091-4 NOTES Rev. F | Page 19 of 20 ADA4091-2/ADA4091-4 NOTES ©2008–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07671-0-10/10(F) Rev. F | Page 20 of 20