ANALOG DEVICES ADA4084-2

30 V, Low Noise, Rail-to-Rail I/O, Low Power Operational Amplifier Data Sheet ADA4084-2 FEATURES PIN CONFIGURATIONS Rail-to-rail input/output ADA4084-2 OUT A 1 8 V+ Low power: 625 µA typical OUT B –IN A 2 7 Gain bandwidth product: 15.9 MHz at A =100 typical V +IN A 3 6 –IN B Unity-gain crossover: 9.9 MHz typical −3 dB closed-loop bandwidth: 13.9 MHz typical at ±15 V V– 4 5 +IN B TOP VIEW Low offset voltage: 100 μV maximum (SOIC) (Not to Scale) Unity-gain stable Figure 1. 8-Lead MSOP (RM) High slew rate: 4.6 V/μs typical 8-Lead SOIC (R) Low noise: 3.9 nV/√Hz typical at 1 kHz APPLICATIONS Battery-powered instrumentation Power supply control and protection Telecommunications DAC output amplifier ADC input buffer The ADA4084-2 is a member of a growing series of high voltage, GENERAL DESCRIPTION low noise op amps offered by Analog Devices, Inc., (see Table 1). The ADA4084-2 is a dual, single-supply, 10 MHz bandwidth For a more complete selection table of low input voltage noise amplifier featuring rail-to-rail inputs and outputs. It is guaran- amplifiers, see the AN-940 Application Note, Low Noise teed to operate from 3 V to 30 V (or ±1.5 V to ±15 V). Amplifier Selection Guide for Optimal Noise Performance, These amplifiers are well suited for single-supply applications available at www.analog.com. requiring both ac and precision dc performance. The combina- tion of wide bandwidth, low noise, and precision makes the Table 1. Low Noise Op Amps ADA4084-2 useful in a wide variety of applications, including Voltage Noise Single Dual Quad filters and instrumentation. 1.1 nV/Hz AD8597 AD8599 Other applications for these amplifiers include portable telecom- 1.8 nV/Hz ADA4004-1 ADA4004-2 ADA4004-4 1 munications equipment, power supply control and protection, 2.8 nV/Hz RRO AD8675 AD8676 and use as amplifiers or buffers for transducers with wide output 2.8 nV/Hz AD8671 AD8672 AD8674 ranges. Sensors requiring a rail-to-rail input amplifier include 3.2 nV/Hz OP27/OP37 2 Hall effect, piezoelectric, and resistive transducers. 3.9 nV/Hz RRIO ADA4084-2 1 The ability to swing rail-to-rail at both the input and output Rail-to-rail output. 2 Rail-to-rail input/output. enables designers to build multistage filters in single-supply systems and to maintain high signal-to-noise ratios. The ADA4084-2 is specified over the industrial temperature range of −40°C to +125°C. The dual ADA4084-2 is available in the 8-lead SOIC and MSOP surface-mount packages. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2011–2012 Analog Devices, Inc. All rights reserved. 08237-001 ADA4084-2 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 ±15 V Characteristics ................................................................ 15 Applications ....................................................................................... 1 Comparative Voltage and Variable Voltage Graphs ............... 19 General Description ......................................................................... 1 Applications Information .............................................................. 20 Pin Configurations ........................................................................... 1 Functional Description .............................................................. 20 Revision History ............................................................................... 2 Input Protection ......................................................................... 21 Specifications ..................................................................................... 3 Output Phase Reversal ............................................................... 21 Electrical Characteristics ............................................................. 3 Designing Low Noise Circuits in Single-Supply Applications ................................................................................ 21 Absolute Maximum Ratings ............................................................ 6 Comparator Operation .............................................................. 22 Thermal Resistance ...................................................................... 6 Outline Dimensions ....................................................................... 23 ESD Caution .................................................................................. 6 Ordering Guide .......................................................................... 23 Typical Performance Characteristics ............................................. 7 ±1.5 V Characteristics .................................................................. 7 ±5 V Characteristics ................................................................... 11 REVISION HISTORY 2/12—Rev. 0 to Rev. A Changes to Data Sheet Title ............................................................ 1 Changes to Voltage Range in General Description ...................... 1 Changes to Supply Current/Amplifier Parameter, Table 2.......... 3 Changes to Common-Mode Rejection Ratio Parameter, Table 3 .. 4 Changes to Common-Mode Rejection Ratio Parameter, Table 4 .. 5 Changes to Figure 2 .......................................................................... 6 Changes to Figure 24 ...................................................................... 10 Changes to Figure 32 ...................................................................... 12 Changes to Figure 47 ...................................................................... 14 Changes to Figure 55 ...................................................................... 16 Changes to Figure 62 ...................................................................... 17 Changes to Figure 73 ...................................................................... 20 10/11—Revision 0: Initial Version Rev. A | Page 2 of 24 Data Sheet ADA4084-2 SPECIFICATIONS ELECTRICAL CHARACTERISTICS V = 3 V, V =1.5 V, T = 25°C, unless otherwise noted. SY CM A Table 2. Parameter Symbol Test Conditions/Comments Min Typ Max Unit INPUT CHARACTERISTICS 1 Offset Voltage V SOIC package 100 μV OS −40°C ≤ T ≤ +125°C 200 μV A MSOP package 130 μV −40°C ≤ TA ≤ +125°C 250 μV Offset Voltage Drift ΔVOS/ΔT −40°C ≤ TA ≤ +125°C 0.5 1.75 µV/°C Offset Voltage Matching Channel A vs. Channel B, TA = 25°C 150 μV Input Bias Current I 140 300 nA B –40°C ≤ T ≤ +125°C 450 nA A Input Offset Current IOS 25 nA –40°C ≤ TA ≤ +125°C 50 nA Input Voltage Range 0 3 V Common-Mode Rejection Ratio CMRR V = 0 V to 3 V 64 80 dB CM −40°C ≤ T ≤ +125°C 60 dB A Large Signal Voltage Gain A R = 2 kΩ, 0.5 V ≤ V ≤ 2.5 V 100 104 dB VO L O RL = 2 kΩ, −40°C ≤ TA ≤ +125°C 97 dB Input Impedance, Differential 100||1.1 kΩ||pF Input Impedance, Common-Mode 80||2.9 MΩ||pF OUTPUT CHARACTERISTICS Output Voltage High VOH RL = 10 kΩ to VCM 2.85 2.95 V –40°C ≤ TA ≤ +125°C 2.8 V R = 2 kΩ to V 2.8 2.9 V L CM –40°C ≤ T ≤ +125°C 2.7 V A Output Voltage Low VOL RL = 10 kΩ to VCM 10 20 mV –40°C ≤ TA ≤ +125°C 40 mV RL = 2 kΩ to VCM 50 mV –40°C ≤ T ≤ +125°C 75 mV A Short-Circuit Current I −17/+10 mA SC POWER SUPPLY Power Supply Rejection Ratio PSRR V = ±1.25 V to ±1.75 V 100 110 dB SY –40°C ≤ T ≤ +125°C 90 dB A Supply Current/Amplifier I I = 0 mA 565 650 µA SY O –40°C ≤ TA ≤ +125°C 950 µA DYNAMIC PERFORMANCE Slew Rate SR R = 2 kΩ 2.0 2.6 V/µs L Gain Bandwidth Product GBP VIN = 5 mV p-p, RL = 10 kΩ, AV = 100 15.4 MHz Unity-Gain Crossover UGC VIN = 5 mV p-p, RL = 10 kΩ, AV = 1 8.08 MHz Phase Margin Φ 86 Degrees M −3 dB Closed-Loop Bandwidth −3 dB A = 1, V = 5 mV p-p 12.3 MHz V IN NOISE PERFORMANCE Voltage Noise e p-p 0.1 Hz to 10 Hz 0.14 μV p-p n Voltage Noise Density e f = 1 kHz 3.9 nV/√Hz n Current Noise Density i f = 1 kHz 0.55 pA/√Hz n 1 Offset voltage does not include solder heat resistance. Rev. A | Page 3 of 24 ADA4084-2 Data Sheet V = ±5.0 V, V = 0 V, T = 25°C, unless otherwise noted. SY CM A Table 3. Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS 1 Offset Voltage V SOIC package 100 μV OS −40°C ≤ T ≤ +125°C 250 μV A MSOP package 130 μV −40°C ≤ TA ≤ +125°C 250 μV Offset Voltage Drift ΔVOS/ΔT −40°C ≤ TA ≤ +125°C 0.5 1.75 μV/°C Offset Voltage Matching Channel A vs. Channel B, TA = 25°C 150 μV Input Bias Current I 140 300 nA B −40°C ≤ T ≤ +125°C 450 nA A Input Offset Current I 25 nA OS −40°C ≤ TA ≤ +125°C 50 nA Input Voltage Range −5 +5 V Common-Mode Rejection Ratio CMRR V = ±4 V 106 124 dB CM V = ±5 V, −40°C ≤ T ≤ +125°C 76 dB CM A Large Signal Voltage Gain A R = 2 kΩ, −4 V ≤ V ≤ 4 V 108 112 dB VO L O RL = 2 kΩ, −40°C ≤ TA ≤ +125°C 103 dB Input Impedance, Differential 100||1.1 kΩ||pF Input Impedance, Common-Mode 200||2.5 MΩ||pF OUTPUT CHARACTERISTICS Output Voltage High VOH RL = 10 kΩ to VCM 4.9 4.95 V −40°C ≤ TA ≤ +125°C 4.8 V R = 2 kΩ to V 4.8 4.85 V L CM −40°C ≤ T ≤ +125°C 4.7 V A Output Voltage Low V R = 10 kΩ to V −4.95 −4.9 V OL L CM −40°C ≤ TA ≤ +125°C −4.8 V RL = 2 kΩ to VCM −4.95 −4.8 V −40°C ≤ T ≤ +125°C −4.7 V A Short Circuit Current I −24/+17 mA SC POWER SUPPLY Power Supply Rejection Ratio PSRR V = ±2 V to ±18 V 110 120 dB SY −40°C ≤ T ≤ +125°C 105 dB A Supply Current/Amplifier I I = 0 mA 595 700 µA SY O −40°C ≤ TA ≤ +125°C 1000 µA DYNAMIC PERFORMANCE Slew Rate SR R = 2 kΩ to V 2.4 3.7 V/µs L CM Gain Bandwidth Product GBP VIN = 5 mV p-p, RL = 10 kΩ, AV = 100 15.9 MHz Unity-Gain Crossover UGC VIN = 5 mV p-p, RL = 10 kΩ, AV = 1 9.6 MHz Phase Margin ΦM 85 Degrees −3 dB Closed-Loop Bandwidth −3 dB A = 1, V = 5 mV p-p 13.9 MHz V IN NOISE PERFORMANCE Voltage Noise e p-p 0.1 Hz to 10 Hz 0.14 µV p-p n Voltage Noise Density e f = 1 kHz 3.9 nV/√Hz n Current Noise Density i 0.55 pA/√Hz n 1 Offset Voltage does not include solder heat resistance. Rev. A | Page 4 of 24 Data Sheet ADA4084-2 V = ±15.0 V, V = 0 V, T = 25°C, unless otherwise noted. SY CM A Table 4. Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS 1 Offset Voltage V SOIC package 100 μV OS −40°C ≤ T ≤ +125°C 200 μV A MSOP package 130 μV −40°C ≤ TA ≤ +125°C 250 μV Offset Voltage Drift ΔVOS/ΔT 0.5 1.75 μV/°C Offset Voltage Matching Channel A vs. Channel B, TA = 25°C 150 μV Input Bias Current I 140 300 nA B −40°C ≤ T ≤ +125°C 450 nA A Input Offset Current I 25 nA OS −40°C ≤ TA ≤ +125°C 50 nA Input Voltage Range −15 +15 V Common-Mode Rejection Ratio CMRR V = ±14 V 106 124 dB CM V = ±15 V, −40°C ≤ T ≤ +125°C 85 dB CM A Large Signal Voltage Gain A R = 2 kΩ, −13.5 V ≤ V ≤ +13.5 V 110 117 dB VO L O −40°C ≤ TA ≤ +125°C 105 dB Input Impedance, Differential 100||1.1 kΩ||pF Input Impedance, Common-Mode 200||2.5 MΩ||pF OUTPUT CHARACTERISTICS Output Voltage High VOH RL = 10 kΩ to VCM 14.8 14.9 V −40°C ≤ TA ≤ +125°C 14.8 V R = 2 kΩ to V 14.5 14.6 V L CM −40°C ≤ T ≤ +125°C 14.3 V A Output Voltage Low V R = 10 kΩ to V −14.95 −14.9 V OL L CM −40°C ≤ TA ≤ +125°C −14.8 V RL = 2 kΩ to VCM −14.9 −14.8 V −40°C ≤ T ≤ +125°C −14.7 V A Short Circuit Current I ±30 mA SC POWER SUPPLY Power Supply Rejection Ratio PSRR V = ±2 V to ±18 V 110 120 dB SY −40°C ≤ T ≤ +125°C 105 dB A Supply Current/Amplifier I I = 0 mA 625 750 µA SY O −40°C ≤ TA ≤ +125°C 1050 µA DYNAMIC PERFORMANCE Slew Rate SR R = 2 kΩ 2.4 4.6 V/µs L Gain Bandwidth Product GBP VIN = 5 mV p-p, RL = 10 kΩ, AV = 100 15.9 MHz Unity-Gain Crossover UGC VIN = 5 mV p-p, RL = 10 kΩ, AV = 1 9.9 MHz Phase Margin ΦM 86 Degrees −3 dB Closed-Loop Bandwidth −3 dB A = 1, V = 5 mV p-p 13.9 MHz V IN NOISE PERFORMANCE Voltage Noise e p-p 0.1 Hz to 10 Hz 0.1 µV p-p n Voltage Noise Density e f = 1 kHz 3.9 nV/√Hz n Current Noise Density i 0.55 pA/√Hz n 1 Offset Voltage does not include solder heat resistance. Rev. A | Page 5 of 24 ADA4084-2 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 5. THERMAL RESISTANCE Parameter Rating θJA is specified for the device soldered on a 4-layer JEDEC Supply Voltage ±18 V standard printed circuit board (PCB) with zero airflow. Input Voltage V− ≤ V ≤ V+ IN 1 Differential Input Voltage ±0.6 V Table 6. Thermal Resistance Output Short-Circuit Duration to GND Indefinite Package Type θ θ Unit JA JC Storage Temperature Range −65°C to +150°C 8-Lead SOIC 121 43 °C/W Operating Temperature Range −40°C to +125°C 8-Lead MSOP 142 45 °C/W Junction Temperature Range −65°C to +150°C Lead Temperature (Soldering 60 sec) 300°C ESD CAUTION 1 For input differential voltages greater than 0.6 V, the input current should be limited to less than 5 mA to prevent degradation or destruction of the input devices. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. V CC R4 R3 R6 Q24 Q23 D2 D1 Q1 Q2 MIRROR D100 FOLDED V Q4 Q3 OUT CASCADE D101 Q13 C2 R7 V D5 D4 BIAS Q18 R5 C1 Q19 R1 R2 Q21 V D20 EE Figure 2. Simplified Schematic Rev. A | Page 6 of 24 08237-002 Data Sheet ADA4084-2 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted. ±1.5 V CHARACTERISTICS 120 500 ADA4084-2 400 V = ±1.5V SY 100 T = 25°C A 300 R = ∞ L 200 80 100 0 60 –100 40 –200 –300 ADA4084-2 20 V = ±1.5V SY –400 T = 25°C A R = ∞ L –500 0 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 –100 –75 –50 –25 0 25 50 75 100 COMMON-MODE VOLTAGE (V) V (µV) OS Figure 3. Input Offset Voltage Distribution, SOIC Figure 6. Input Offset Voltage vs. Common-Mode Voltage 50 –50 ADA4084-2 45 V = ±1.5V SY T = 25°C A 40 I + R = ∞ L B –100 35 30 25 –150 I – B 20 15 –200 10 ADA4084-2 V = ±1.5V SY 5 V = 0V CM R = ∞ L 0 –250 –100 –75 –50 –25 0 25 50 75 100 –40 –25 –10 5 20 35 50 65 80 95 110 125 V (µV) TEMPERATURE (°C) OS Figure 4. Input Offset Voltage Distribution, MSOP Figure 7. Input Bias Current vs. Temperature 60 600 50 400 40 200 T = +125°C A 30 0 T = +85°C A –200 20 T = +25°C ADA4084-2 A T = –40°C A V = ±1.5V SY –400 10 T = 25°C A ADA4084-2 R = ∞ L V = ±1.5V SY –40° ≤ T ≤ +125°C A –600 0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 V (V) TCV (µV/°C) CM OS Figure 8. Input Bias Current vs. VCM and Temperature Figure 5. TCVOS Distribution, SOIC Rev. A | Page 7 of 24 NUMBER OF AMPLIFIERS NUMBER OF AMPLIFIERS NUMBER OF AMPLIFIERS 08237-004 08237-003 08237-005 INPUT BIAS (nA) INPUT BIAS (nA) INPUT OFFSET VOLTAGE (µV) 08237-008 08237-006 08237-007 ADA4084-2 Data Sheet 60 ADA4084-2 V = ±1.5V 1000 50 SY T = 25°C A A = +100 V 40 30 100 A = +10 V 20 10 (V+) –V OH 10 A = +1 V 0 ADA4084-2 V = ±1.5V SY –10 T = 25°C A 1 –20 0.001 0.01 0.1 1 10 10 100 1k 10k 100k 1M 10M 100M LOAD CURRENT (mA) FREQUENCY (Hz) Figure 12. Closed-Loop Gain vs. Frequency Figure 9. Dropout Voltage vs. Source Current 1000 1000 A = +10 V 100 10 100 A = +100 V A = +1 V 1 10 V – (V–) OL 0.10 ADA4084-2 ADA4084-2 V = ±1.5V SY V = ±1.5V SY T = 25°C A T = 25°C A 1 0.01 0.001 0.01 0.1 1 10 10 100 1k 10k 100k 1M 10M 100M LOAD CURRENT (mA) FREQUENCY (Hz) Figure 13. Output Impedance vs. Frequency Figure 10. Dropout Voltage vs. Sink Current 140 120 270 ADA4084-2 ADA4084-2 V = ±1.5V V = ±1.5V 120 SY 100 SY 225 T = 25°C T = 25°C A A R = 10kΩ L 100 80 180 80 60 135 60 40 90 PSRR– 40 20 45 20 PSRR+ 0 0 0 –20 –45 –20 –40 –90 10 100 1k 10k 100k 1M 10M 100M 0.1 1 10 100 1k 10k 100k FREQUENCY (Hz) FREQUENCY (kHz) Figure 14. PSRR vs. Frequency Figure 11. Open-Loop Gain and Phase vs. Frequency Rev. A | Page 8 of 24 GAIN (dB) V (mV) V (mV) DO DO PHASE (Degrees) 08237-010 08237-009 08237-011 PSRR (dB) Z (Ω) GAIN (dB) OUT 08237-014 08237-013 08237-012 Data Sheet ADA4084-2 120 2 0.08 ADA4084-2 110 V = ±1.5V SY INPUT T = 25°C 0 0.06 A 100 90 0.04 –2 80 –4 0.02 70 OUTPUT 60 –6 0 50 ADA4084-2 40 V = ±1.5V –8 SY –0.02 T = 25°C A 30 –10 –0.04 20 –1 0 1 2 3 4 5 6 7 8 9 10 100 1k 10k 100k 1M 10M 100M TIME (µs) FREQUENCY (Hz) Figure 15. CMRR vs. Frequency Figure 18. Settling Time 1.5 10 1.0 0.5 4 0 –0.5 ADA4084-2 V = ±1.5V SY –1.0 T = 25°C A ADA4084-2 R = 2kΩ L V = ±1.5V SY C = 100pF L T = 25°C A –1.5 1 0 2 4 6 8 10 12 14 16 18 1 10 100 1k 10k 100k TIME (µs) FREQUENCY (Hz) Figure 19. Voltage Noise Density Figure 16. Large Signal Transient Response 60 80 ADA4084-2 V = ±1.5V 60 SY 50 V = 100mV p-p IN OS+ R = 2kΩ L 40 T = 25°C A 40 20 30 0 –20 20 OS– ADA4084-2 –40 V = ±1.5V SY T = 25°C A 10 R = 2kΩ –60 L C = 100pF L –80 0 0 2 4 6 8 10 12 14 16 18 1 10 100 1000 TIME (µs) CAPACITANCE (pF) Figure 17. Small Signal Transient Response Figure 20. Overshoot vs. Capacitance Rev. A | Page 9 of 24 CMRR (dB) VOLTAGE (V) VOLTAGE (mV) 08237-017 08237-016 08237-015 VOLTAGE (V) VOLTAGE NOISE DENSITY (nV/√Hz) OVERSHOOT (%) VOLTAGE (V) 08237-020 08237-019 08237-018 ADA4084-2 Data Sheet 80 0.01 60 40 20 0 0.001 –20 ADA4084-2 –40 R = 2kΩ L V = 0.4V IN RMS ADA4084-2 V = ±1.5V SY –60 V = ±1.5V T = 25°C SY A T = 25°C 500kHz FILTER A –80 0.0001 0 1 2 3 4 5 6 7 8 9 10 10 100 1k 10k 100k TIME (Seconds) FREQUENCY (Hz) Figure 21. Voltage Noise 0.1 Hz to 10 Hz Figure 24. THD + N vs. Frequency 0 2.0 ADA4084-2 ADA4084-2 V = ±1.5V –20 V = ±1.5V 1.5 SY SY T = 25°C T = 25°C A A V = 1V p-p IN –40 1.0 –60 0.5 OUTPUT –80 0 –100 –0.5 INPUT –120 –1.0 –140 –1.5 –160 –2.0 100 1k 10k 100k 0 100 200 300 400 500 600 700 800 900 1000 TIME (µs) FREQUENCY (Hz) Figure 22. Channel Separation Figure 25. No Phase Reversal 1 0.1 0.01 ADA4084-2 V = ±1.5V SY T = 25°C A f = 1kHz 0.001 0.001 0.01 0.1 1 AMPLITUDE (V ) RMS Figure 23. THD + N vs. Amplitude Rev. A | Page 10 of 24 CHANNEL SEPARATION (dB) THD + N (%) VOLTAGE NOISE (nV) 08237-021 08237-023 08237-022 VOLTAGE (V) THD + N (%) 08237-025 08237-024 Data Sheet ADA4084-2 ±5 V CHARACTERISTICS 120 600 ADA4084-2 500 V = ±5V SY 100 400 T = 25°C A R = ∞ L 300 200 80 100 0 60 –100 –200 40 –300 ADA4084-2 V = ±5V –400 SY 20 T = 25°C A –500 R = ∞ L –600 0 –5 –4 –3 –2 –1 0 1 2 3 4 5 –100 –75 –50 –25 0 25 50 75 100 COMMON-MODE VOLTAGE (V) V (µV) OS Figure 26. Input Offset Voltage Distribution SOIC Figure 29. Input Offset Voltage vs. Common-Mode Voltage –50 60 ADA4084-2 V = ±5V SY 50 T = 25°C A R = ∞ L –100 40 I + B –150 30 I – B 20 –200 ADA4084-2 V = ±5V 10 SY V = 0V CM R = ∞ L 0 –250 –100 –75 –50 –25 0 25 50 75 100 –40 –25 –10 5 20 35 50 65 80 95 110 125 V (µV) TEMPERATURE (°C) OS Figure 27. Input Offset Voltage Distribution MSOP Figure 30. Input Bias Current vs. Temperature 800 50 45 600 40 400 35 200 T = +125°C 30 A T = +85°C A 0 25 20 –200 T = +25°C 15 A T = –40°C A –400 ADA4084-2 10 V = ±5V SY ADA4084-2 R = ∞ –600 L 5 –40° ≤ T ≤ +125°C V = ±5V A SY –800 0 –5 –4 –3 –2 –1 0 1234 5 02 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8.0 V (V) TCV (µV/°C) CM OS Figure 31. Input Bias Current vs. V and Temperature Figure 28. TCVOS Distribution CM Rev. A | Page 11 of 24 NUMBER OF AMPLIFIERS NUMBER OF AMPLIFIERS NUMBER OF AMPLIFIERS 08237-028 08237-027 08237-026 INPUT BIAS (nA) INPUT BIAS (nA) INPUT OFFSET VOLTAGE (µV) 08237-031 08237-029 08237-030 ADA4084-2 Data Sheet 60 ADA4084-2 1000 V = ±5V 50 SY T = 25°C A A = +100 V 40 100 30 A = +10 V 20 10 (V+) –V 10 OH A = +1 V 0 ADA4084-2 V = ±5V SY –10 T = 25°C A 1 –20 0.001 0.01 0.1 1 10 10 100 1k 10k 100k 1M 10M 100M LOAD CURRENT (mA) FREQUENCY (Hz) Figure 32. Dropout Voltage vs. Source Current Figure 35. Closed-Loop Gain vs. Frequency 1000 1000 100 A = +10 V 100 10 A = +1 V A = +100 V 1 V – (V–) 10 OL ADA4084-2 0.10 ADA4084-2 V = ±5V SY V = ±5V SY T = 25°C A T = 25°C A 1 0.01 0.001 0.01 0.1 1 10 10 100 1k 10k 100k 1M 10M 100M LOAD CURRENT (mA) FREQUENCY (Hz) Figure 33. Dropout Voltage vs. Sink Current Figure 36. Output Impedance vs. Frequency 140 120 270 ADA4084-2 ADA4084-2 V = ±5V V = ±5V 100 SY 225 120 SY T = 25°C T = 25°C A A R = 10kΩ L 80 180 100 60 135 80 40 90 60 PSRR– 20 45 40 0 0 20 PSRR+ –20 –45 0 –40 –90 –20 0.1 1 10 100 1k 10k 100k 10 100 1k 10k 100k 1M 10M 100M FREQUENCY (kHz) FREQUENCY (Hz) Figure 34. Open-Loop Gain and Phase vs. Frequency Figure 37. PSRR vs. Frequency Rev. A | Page 12 of 24 GAIN (dB) V (mV) V (mV) DO DO PHASE (Degrees) 08237-033 08237-032 08237-034 PSRR (dB) Z (Ω) GAIN (dB) OUT 08237-037 08237-036 08237-035 Data Sheet ADA4084-2 120 10 0.16 ADA4084-2 110 V = ±5V SY 5 0.12 T = 25°C A 100 INPUT 0.08 0 90 80 –5 0.04 70 OUTPUT –10 0 60 50 –15 –0.04 ADA4084-2 40 V = ±5V SY –20 –0.08 T = 25°C A 30 –25 –0.12 20 –2 0 2 4 6 8 10 12 14 16 18 10 100 1k 10k 100k 1M 10M 100M TIME (µs) FREQUENCY (Hz) Figure 38. CMRR vs. Frequency Figure 41. Settling Time 5 10 4 3 2 1 4 0 –1 –2 ADA4084-2 V = ±5V SY –3 T = 25°C A ADA4084-2 R = 2kΩ L V = ±5V –4 SY C = 100pF L T = 25°C A –5 1 0 2 4 6 8 10 12 14 16 18 1 10 100 1k 10k 100k TIME (µs) FREQUENCY (Hz) Figure 39. Large Signal Transient Response Figure 42. Voltage Noise Density 80 60 ADA4084-2 60 V = ±5V SY 50 OS+ V = 100mV p-p IN R = 2kΩ L 40 T = 25°C A 40 20 0 30 –20 20 OS– ADA4084-2 –40 V = ±5V SY T = 25°C A 10 –60 R = 2kΩ L C = 100pF L –80 0 0 1 2 3 4 5 6 7 8 9 10 1 10 100 1000 TIME (µs) CAPACITANCE (pF) Figure 40. Small Signal Transient Response Figure 43. Overshoot vs. Load Capacitance Rev. A | Page 13 of 24 CMRR (dB) VOLTAGE (V) VOLTAGE (mV) 08237-040 08237-039 08237-038 VOLTAGE (V) VOLTAGE NOISE DENSITY (nV/√Hz) OVERSHOOT (%) VOLTAGE (V) 08237-043 08237-042 08237-041 ADA4084-2 Data Sheet 80 1 ADA4084-2 R = 2kΩ L 60 V = 2.0V IN RMS V = ±5V SY 40 0.1 T = 25°C A 500kHz FILTER 20 0 0.01 –20 –40 0.001 ADA4084-2 –60 V = ±5V SY T = 25°C A –80 0.0001 0 1 23 45 67 89 10 10 100 1k 10k 100k TIME (Seconds) FREQUENCY (Hz) Figure 44. Volage Noise 0.1 Hz to 10 Hz Figure 47. THD + N vs. Frequency 0 6 ADA4084-2 ADA4084-2 V = ±5V –20 V = ±5V SY SY 4 T = 25°C T = 25°C A A V = 5V p-p IN –40 2 –60 –80 0 OUTPUT –100 –2 INPUT –120 –4 –140 –160 –6 01 100 200 300 400 500 600 700 800 900000 100 1k 10k 100k FREQUENCY (Hz) TIME (µs) Figure 45. Channel Separation Figure 48. No Phase Reversal 1 0.1 0.01 0.001 ADA4084-2 V = ±5V SY T = 25°C A f = 1kHz 0.0001 0.001 0.01 0.1 1 AMPLITUDE (V ) RMS Figure 46. THD + N vs. Amplitude Rev. A | Page 14 of 24 CHANNEL SEPARATION (dB) THD + N (%) VOLTAGE NOISE (nV) 08237-044 08237-046 08237-045 VOLTAGE (V) THD + N (%) 08237-047 08237-048 Data Sheet ADA4084-2 ±15 V CHARACTERISTICS 100 600 ADA4084-2 500 90 V = ±15V SY 400 T = 25°C A 80 R = ∞ L 300 70 200 60 100 50 0 –100 40 –200 30 –300 ADA4084-2 20 V = ±15V SY –400 T = 25°C A 10 –500 R = ∞ L –600 0 –100 –75 –50 –25 0 25 50 75 100 –15 –10 –5 0 5 10 15 COMMON-MODE VOLTAGE (V) V (µV) OS Figure 49. Input Offset Voltage Distribution, SOIC Figure 52. Input Offset Voltage vs. Common-Mode Voltage –50 60 ADA4084-2 V = ±15V SY 50 T = 25°C A I + R = ∞ B L –100 40 –150 30 I – B 20 –200 ADA4084-2 V = ±15V SY 10 V = 0V CM R = ∞ L 0 –250 –100 –75 –50 –25 0 25 50 75 100 –40 –25 –10 5 20 35 50 65 80 95 110 125 V (µV) TEMPERATURE (°C) OS Figure 50. Input Offset Voltage Distribution, MSOP Figure 53. Input Bias Current vs. Temperature 1200 60 800 50 400 40 T = +125°C A T = +85°C A 30 0 –400 T = +25°C 20 T = –40°C A A ADA4084-2 V = ±15V SY 10 –800 ADA4084-2 R = ∞ L V = ±15V –40° ≤ T ≤ +125°C SY A 0 –1200 02 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8.0 –15 –10 –5 0 5 10 15 TCV (µV/°C) V (V) OS CM Figure 51. TCVOS Distribution Figure 54. Input Bias Current vs. VCM and Temperature Rev. A | Page 15 of 24 NUMBER OF AMPLIFIERS NUMBER OF AMPLIFIERS NUMBER OF AMPLIFIERS 08237-051 08237-050 08237-049 INPUT BIAS (nA) INPUT BIAS (nA) INPUT OFFSET VOLTAGE (µV) 08237-054 08237-052 08237-053 ADA4084-2 Data Sheet 60 10000 ADA4084-2 V = ±15V 50 SY T = 25°C A A = +100 V 40 1000 30 A = +10 V 20 100 10 (V+) –V OH A = +1 V 10 ADA4084-2 0 V = ±15V SY T = 25°C A –10 1 –20 0.001 0.01 0.1 1 10 10 100 1k 10k 100k 1M 10M 100M LOAD CURRENT (mA) FREQUENCY (Hz) Figure 55. Dropout Voltage vs. Source Current Figure 58. Closed-Loop Gain vs. Frequency 1000 10000 100 A = +10 V 1000 10 A = +100 V 100 1 A = +1 V V – (V–) OL 10 ADA4084-2 0.1 V = ±15V SY ADA4084-2 T = 25°C A V = ±15V SY T = 25°C A 1 0.01 0.001 0.01 0.1 1 10 10 100 1k 10k 100k 1M 10M 100M LOAD CURRENT (mA) FREQUENCY (Hz) Figure 56. Dropout Voltage vs. Sink Current Figure 59. Output Impedance vs. Frequency 120 270 140 ADA4084-2 ADA4084-2 V = ±15V V = ±15V 225 100 SY 120 SY T = 25°C T = 25°C A A R = 10kΩ L 180 80 100 135 60 80 90 40 60 PSRR– 45 20 40 0 0 20 PSRR+ –20 –45 0 –40 –90 –20 100 1k 10k 100k 1M 10M 100M 10 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) Figure 57. Open-Loop Gain and Phase vs. Frequency Figure 60. PSRR vs. Frequency Rev. A | Page 16 of 24 GAIN (dB) V (mV) V (mV) DO DO PHASE (Degrees) 08237-056 08237-055 08237-057 PSRR (dB) Z (Ω) GAIN (dB) OUT 08237-060 08237-059 08237-058 Data Sheet ADA4084-2 120 10 0.20 ADA4084-2 110 V = ±15V SY 5 0.15 T = 25°C A 100 INPUT 0.10 0 90 80 –5 0.05 70 OUTPUT –10 0 60 50 –15 –0.05 40 ADA4084-2 –20 –0.10 V = ±15V SY 30 T = 25°C A –25 –0.15 20 –2 0 2 4 6 8 10 12 14 16 18 10 100 1k 10k 100k 1M 10M 100M TIME (µs) FREQUENCY (Hz) Figure 61. CMRR vs. Frequency Figure 64. Settling Time 15 10 10 5 4 0 –5 ADA4084-2 V = ±15V SY T = 25°C –10 A ADA4084-2 R = 2kΩ L V = ±15V SY C = 100pF L T = 25°C A –15 1 0 4 8 12 16 20 24 28 32 36 1 10 100 1k 10k 100k TIME (µs) FREQUENCY (Hz) Figure 62. Large Signal Transient Response Figure 65. Voltage Noise Density 70 80 ADA4084-2 60 V = ±15V 60 SY V = 100mV p-p OS+ IN R = 2kΩ L 40 T = 25°C 50 A 20 40 0 30 –20 ADA4084-2 20 OS– –40 V = ±15V SY T = 25°C A 10 R = 2kΩ –60 L C = 100pF L –80 0 0 1 2 3 4 5 6 7 8 9 10 1 10 100 1000 TIME (µs) CAPACITANCE (pF) Figure 63. Small Signal Transient Response Figure 66. Overshoot vs. Load Capacitance Rev. A | Page 17 of 24 CMRR (dB) VOLTAGE (mV) VOLTAGE (V) 08237-062 08237-063 08237-061 VOLTAGE (V) VOLTAGE NOISE DENSITY (nV/√Hz) OVERSHOOT (%) VOLTAGE (V) 08237-066 08237-065 08237-064 ADA4084-2 Data Sheet 60 1 ADA4084-2 V = ±15V SY T = 25°C A 40 500kHz FILTER 0.1 20 0.01 0 –20 0.001 –40 ADA4084-2 V = ±15V SY T = 25°C A 0.0001 –60 10 100 1k 10k 100k 0 2 4 6 8 10 FREQUENCY (Hz) TIME (Seconds) Figure 70. THD + N vs. Frequency Figure 67. Voltage Noise 0.1 Hz to 10 Hz 0 20 ADA4084-2 ADA4084-2 –20 15 V = ±15V V = ±15V SY SY T = 25°C T = 25°C A A –40 V = 10V p-p IN 10 –60 5 –80 0 OUTPUT –100 –5 INPUT –120 –10 –140 –15 –160 –20 –180 0 100 200 300 400 500 600 700 800 900 1000 100 1k 10k 100k TIME (µs) FREQUENCY (Hz) Figure 71. No Phase Reversal Figure 68. Channel Sepatation 1 0.1 0.01 0.001 ADA4084-2 V = ±15V SY T = 25°C A f = 1kHz 0.0001 0.001 0.01 0.1 1 10 AMPLITUDE (V ) RMS Figure 69. THD + N vs. Amplitude Rev. A | Page 18 of 24 CHANNEL SEPARATION (dB) THD + N (%) VOLTAGE NOISE (nV) 08237-067 08237-069 08237-068 VOLTAGE (V) THD + N (%) 08237-070 08237-071 Data Sheet ADA4084-2 COMPARATIVE VOLTAGE AND VARIABLE VOLTAGE GRAPH 1000 900 +125°C 800 +85°C 700 +25°C 600 –40°C 500 400 300 200 ADA4084-2 T = 25°C A 100 R = ∞ L 0 0 4 8 12 16 20 24 28 32 36 V (V) SY Figure 72. Supply Current vs. Supply Voltage Rev. A | Page 19 of 24 I /AMPLIFIER (µA) SY 08237-072 ADA4084-2 Data Sheet APPLICATIONS INFORMATION important that the effective source impedances connected to FUNCTIONAL DESCRIPTION the ADA4084-2 inputs be balanced for optimum dc and ac The ADA4084-2 is a precision single-supply, rail-to-rail opera- performance. tional amplifier. Intended for portable instrumentation, the To achieve rail-to-rail output, the ADA4084-2 output stage ADA4084-2 combines the attributes of precision, wide band- design employs a unique topology for both sourcing and sinking width, and low noise to make it an ideal choice in single-supply current. This circuit topology is illustrated in Figure 74. The applications that require both ac and precision dc performance. output stage is voltage-driven from the second gain stage. The Other low supply voltage applications for which the ADA4084-2 signal path through the output stage is inverting; that is, for is well suited are active filters, audio microphone preamplifiers, power supply control, and telecommunications. To combine all positive input signals, Q13 provides the base current drive to Q19 of these attributes with rail-to-rail input/output operation, novel so that it conducts (sinks) current. For negative input signals, the circuit design techniques are used. signal path via Q18 → mirror → Q24 provides the base current drive for Q23 to conduct (source) current. Both transistors R4 R3 provide output current until they are forced into saturation. V CC R6 D1 D2 Q24 Q23 Q1 Q2 D100 Q4 Q3 D101 MIRROR V OUT D5 D4 C2 Q13 R7 V BIAS Q18 R1 R2 R5 C1 Q19 Figure 73. ADA4084-2 Equivalent Input Circuit Q21 V For example, Figure 73 illustrates a simplified equivalent circuit D20 EE for the input stage of the ADA4084-2. It comprises a PNP Figure 74. ADA4084-2 Equivalent Output Circuit differential pair, Q1 and Q2, and an NPN differential pair, Q3 Thus, the saturation voltage of the output transistors sets the and Q4, operating concurrently. Diode D100 and Diode D101 limit on the ADA4084-2 maximum output voltage swing. Output serve to clamp the applied differential input voltage to the short-circuit current limiting is determined by the maximum ADA4084-2, thereby protecting the input transistors against signal current into the base of Q13 from the second gain stage. Zener breakdown of the emitter-base junctions. Input stage The output stage also exhibits voltage gain. This is accomplished voltage gains are kept low for input rail-to-rail operation. The by the use of common-emitter amplifiers, and, as a result, the two pairs of differential output voltages are connected to the voltage gain of the output stage (thus, the open-loop gain of the second stage of the ADA4084-2, which is a modified compound device) exhibits a dependence on the total load resistance at the folded cascade gain stage. It is also in the second gain stage, output of the ADA4084-2. where the two pairs of differential output voltages are combined into a single-ended output signal voltage used to drive the output stage. A key issue in the input stage is the behavior of the input bias currents over the input common-mode voltage range. Input bias currents in the ADA4084-2 are the arithmetic sum of the base currents in Q1 and Q4 and in Q2 and Q3. As a result of this design approach, the input bias currents in the ADA4084-2 not only exhibit different amplitudes; they also exhibit different polarities. This effect is best illustrated by Figure 7, Figure 8, Figure 30, Figure 31, Figure 53, and Figure 54. It is therefore Rev. A | Page 20 of 24 08237-073 08237-074 Data Sheet ADA4084-2 INPUT PROTECTION OUTPUT PHASE REVERSAL As with any semiconductor device, if conditions exist where the Some operational amplifiers designed for single-supply operation applied input voltages to the device exceed either supply voltage, exhibit an output voltage phase reversal when their inputs are the input overvoltage I-to-V characteristic of the device must be driven beyond their useful common-mode range. Typically, for considered. When an overvoltage occurs, the amplifier may be single-supply bipolar op amps, the negative supply determines damaged, depending on the magnitude of the applied voltage the lower limit of their common-mode range. With these devices, and the magnitude of the fault current. external clamping diodes, with the anode connected to ground and the cathode to the inputs, prevent input signal excursions The D1, D2, D4, and D5 diodes conduct when the input common- from exceeding the negative supply of the device (that is, GND), mode voltage exceeds either supply pin by a diode drop. This preventing a condition that causes the output voltage to change varies with temperature and is in the range of 0.3 V to 0.8 V. As phase. JFET input amplifiers can also exhibit phase reversal, illustrated in the simplified equivalent circuit shown in Figure 73, and, if so, a series input resistor is usually required to prevent it. the ADA4084-2 does not have any internal current limiting resis- tors; thus, fault currents can quickly rise to damaging levels. The ADA4084-2 is free from reasonable input voltage range restrictions, provided that input voltages no greater than the This input current is not inherently damaging to the device, supply voltages are applied. Although device output does not provided that it is limited to 5 mA or less. If a fault condition change phase, large currents can flow through the input causes more than 5 mA to flow, an external series resistor protection diodes. Therefore, the technique recommended in the should be added at the expense of additional thermal noise. Input Protection section should be applied to those applications Figure 75 illustrates a typical noninverting configuration for an where the likelihood of input voltages exceeding the supply overvoltage-protected amplifier where the series resistance, R , S voltages is high. is chosen, such that DESIGNING LOW NOISE CIRCUITS IN SINGLE- V −V IN SUPPLY (MAX) R = SUPPLY APPLICATIONS S 5 mA In single-supply applications, devices like the ADA4084-2 For example, a 1 kΩ resistor protects the ADA4084-2 against extend the dynamic range of the application through the use of input signals up to 5 V above and below the supplies. Note that rail-to-rail operation. Referring to the op amp noise model the thermal noise of a 1 kΩ resistor at room temperature is circuit configuration illustrated in Figure 76, the expression for 4 nV/√Hz, which exceeds the voltage noise of the ADA4084-2. an amplifier’s total equivalent input noise voltage for a source For other configurations where both inputs are used, each input resistance level, R , is given by S should be protected against abuse with a series resistor. Again, V 2 2 2 to ensure optimum dc and ac performance, it is recommended e = 2[(e ) + ( × ) ]+ (e ) , units in i R nT nR nOA S nOA Hz that source impedance levels be balanced. where: R2 R = 2R, the effective, or equivalent, circuit source resistance. S 2 (enR) is the source resistance thermal noise voltage power (4kTR). –23 1/2 k is the Boltzmann’s constant, 1.38 × 10 J/K. V ADA4084-2 OUT T is the ambient temperature in Kelvin of the circuit, 273.15 + R1 V IN T (°C). A 2 (i ) is the op amp equivalent input noise current spectral nOA Figure 75. Resistance in Series with Input power (1 Hz bandwidth). Limits Overvoltage Currents to Safe Values 2 (e ) is the op amp equivalent input noise voltage spectral nOA To protect Q1-Q2 and Q3-Q4 from large differential voltages power (1 Hz bandwidth). that may result in Zener breakdown of the emitter-base junction, e e nR nOA R D100 and D101 are connected between the two inputs. This NOISELESS precludes operation as a comparator. For a more complete i nOA description, see the MT-035 Tutorial, Op Amp Inputs, Outputs, Single-Supply, and Rail-to-Rail Issues; the MT-083 Tutorial, e IDEAL nR R NOISELESS Comparators, the MT-084 Tutorial, Using Op Amps As OP AMP NOISELESS R = 2R Comparators; and the AN-849 Application Note, Using Op i S nOA Amps as Comparators, at www.analog.com. Figure 76. Op Amp Noise Circuit Model Used to Determine Total Circuit Equivalent Input Noise Voltage and Noise Figure Rev. A | Page 21 of 24 08237-075 08237-076 ADA4084-2 Data Sheet As a design aid, Figure 77 shows the total equivalent input noise with source resistance levels that are consistent with maintaining of the ADA4084-2 and the total thermal noise of a resistor for low total circuit noise. comparison. Note that for source resistance less than 1 kΩ, the COMPARATOR OPERATION equivalent input noise voltage of the ADA4084-2 is dominant. Although op amps are quite different from comparators, 100 FREQUENCY = 1kHz occasionally an unused section of a dual or a quad op amp T = 25°C A can be used as a comparator; however, this is not recommended for any rail-to-rail output op amps. For rail-to-rail output op amps, the output stage is generally a ratioed current mirror with bipolar or MOSFET transistors. With the part operating open ADA4084-2 TOTAL EQUIVALENT NOISE loop, the second stage increases the current drive to the ratioed 10 mirror to close the loop. However, it cannot, which results in an increase in supply current. With the op amp configured as a RESISTOR THERMAL NOISE ONLY comparator, the supply current can be significantly higher (see Figure 76). An unused section should be configured as a voltage follower with the noninverting input connected to a voltage 1 within the input voltage range. The ADA4084-2 has unique 100 1k 10k 100k second stage and output stage designs that greatly reduce the TOTAL SOURCE RESISTANCE, R (Ω) S excess supply current when the op amp is operating open loop. Figure 77. ADA4084-2 Equivalent Thermal Noise vs. Total Source Resistance 800 COMPARATOR Because circuit SNR is the critical parameter in the final analysis, OUTPUT LOW 700 the noise behavior of a circuit is sometimes expressed in terms of its noise figure, NF. The noise figure is defined as the ratio of 600 BUFFER a circuit’s output signal-to-noise to its input signal-to-noise. 500 COMPARATOR OUTPUT HIGH Noise figure is generally used for RF and microwave circuit 400 analysis in a 50 Ω system. This is not very useful for op amp circuits where the input and output impedances can vary 300 greatly. For a more complete description of noise figure, see the 200 MT-052 Tutorial, Op Amp Noise Figure: Don’t be Mislead, ADA4084-2 available at www.analog.com. 100 T = 25°C A R = ∞ L Signal levels in the application invariably increase to maximize 0 0 4 8 12 16 20 24 28 32 36 circuit SNR, which is not an option in low voltage, single-supply V (V) SY applications. Figure 78. Supply Current vs. Supply Voltage Therefore, to achieve optimum circuit SNR in single-supply applications, it is recommended that an operational amplifier with the lowest equivalent input noise voltage be chosen, along Rev. A | Page 22 of 24 EQUIVALENT THERMAL NOISE (nV/ Hz) 08237-077 SUPPLY CURRENT (µA) 08237-078 Data Sheet ADA4084-2 OUTLINE DIMENSIONS 3.20 3.00 2.80 8 5 5.15 3.20 4.90 3.00 4.65 1 2.80 4 PIN1 IDENTIFIER 0.65BSC 0.95 15°MAX 0.85 1.10MAX 0.75 0.80 0.15 0.23 6° 0.55 0.40 0.05 0.09 0° 0.40 0.25 COPLANARITY 0.10 COMPLIANTTOJEDECSTANDARDSMO-187-AA Figure 79. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters 5.00(0.1968) 4.80(0.1890) 85 6.20(0.2441) 4.00(0.1574) 1 5.80(0.2284) 3.80(0.1497) 4 1.27(0.0500) 0.50(0.0196) 45° BSC 1.75(0.0688) 0.25(0.0099) 1.35(0.0532) 0.25(0.0098) 8° 0.10(0.0040) 0° COPLANARITY 0.51(0.0201) 1.27(0.0500) 0.10 0.31(0.0122) 0.25(0.0098) SEATING 0.40(0.0157) 0.17(0.0067) PLANE COMPLIANTTOJEDECSTANDARDSMS-012-AA CONTROLLINGDIMENSIONSAREINMILLIMETERS;INCHDIMENSIONS (INPARENTHESES)AREROUNDED-OFFMILLIMETEREQUIVALENTSFOR REFERENCEONLYANDARENOTAPPROPRIATEFORUSEINDESIGN. Figure 80. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) ORDERING GUIDE 1 Model Temperature Range Package Description Package Option Branding ADA4084-2ARMZ −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 A2Q ADA4084-2ARMZ-R7 −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 A2Q ADA4084-2ARMZ-RL −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 A2Q ADA4084-2ARZ −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 ADA4084-2ARZ-R7 −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 ADA4084-2ARZ-RL −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 1 Z = RoHS Compliant Part. Rev. A | Page 23 of 24 10-07-2009-B 012407-A ADA4084-2 Data Sheet NOTES ©2011–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08237-0-2/12(A) Rev. A | Page 24 of 24