ANALOG DEVICES ADA4075-2

Ultralow Noise Amplifier at Lower Power Data Sheet ADA4075-2 FEATURES PIN CONFIGURATIONS Ultralow noise: 2.8 nV/√Hz at 1 kHz typical Ultralow distortion: 0.0002% typical OUTA 1 8 V+ Low supply current: 1.8 mA per amplifier typical ADA4075-2 –INA 2 7 OUTB Offset voltage: 1 mV maximum TOP VIEW +INA 3 6 –INB (Not to Scale) Bandwidth: 6.5 MHz typical V– 4 5 +INB Slew rate: 12 V/μs typical Figure 1. 8-Lead SOIC Dual-supply operation: ±4.5 V to ±18 V Unity-gain stable Extended industrial temperature range OUTA 1 8V+ 8-lead SOIC and 2 mm × 2 mm LFCSP packages ADA4075-2 –INA 2 7OUTB TOP VIEW +INA 3 6–INB (Not to Scale) APPLICATIONS V– 4 5+INB Precision instrumentation Figure 2. 8-Lead, 2 mm × 2 mm LFCSP Professional audio Active filters Low noise amplifier front end Integrators GENERAL DESCRIPTION Table 1. Low Noise Precision Op Amps The ADA4075-2 is a dual, high performance, low noise operational Supply 44 V 36 V 12 V to 16 V 5 V amplifier combining excellent dc and ac characteristics on the Single OP27 AD8671 AD8665 AD8605 Analog Devices, Inc., iPolar® process. The iPolar process is an AD8675 OP162 AD8655 advanced bipolar technology implementing vertical junction AD8597 AD8691 isolation with lateral trench isolation. This allows for low noise ADA4004-1 performance amplifiers in smaller die size at faster speed and AD797 lower power. Its high slew rate, low distortion, and ultralow Dual OP275 AD8672 AD8666 AD8606 noise make the ADA4075-2 ideal for high fidelity audio and AD8676 OP262 AD8656 high performance instrumentation applications. It is also AD8599 AD8692 especially useful for lower power demands, small enclosures, ADA4004-2 and high density applications. The ADA4075-2 is specified for Quad AD8674 AD8668 AD8608 the −40°C to +125°C temperature range and is available in a ADA4004-4 OP462 AD8694 standard SOIC package and a 2 mm × 2 mm LFCSP package. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2008–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 07642-001 07642-002 ADA4075-2 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1  Applications Information .............................................................. 16  Applications....................................................................................... 1  Input Protection ......................................................................... 16  Pin Configurations ........................................................................... 1  Total Harmonic Distortion ....................................................... 16  General Description ......................................................................... 1  Phase Reversal ............................................................................ 16  Revision History ............................................................................... 2  DAC Output Filter...................................................................... 17  Specifications..................................................................................... 3  Balanced Line Driver ................................................................. 18  Absolute Maximum Ratings............................................................ 5  Balanced Line Receiver.............................................................. 19  Thermal Resistance ...................................................................... 5  Low Noise Parametric Equalizer.............................................. 20  Power Sequencing ........................................................................ 5  Schematic......................................................................................... 21  ESD Caution.................................................................................. 5  Outline Dimensions....................................................................... 22  Typical Performance Characteristics ............................................. 6  Ordering Guide .......................................................................... 22  REVISION HISTORY 12/11—Rev. A to Rev. B Changes to Features Section............................................................ 1 8/09—Rev. 0 to Rev. A Added 8-Lead LFCSP_WD ...............................................Universal Changes to Table 1............................................................................ 1 Changes to Table 2............................................................................ 3 Changes to Table 3............................................................................ 4 Changes to Table 4 and Table 5....................................................... 5 Changes to Figure 3, Figure 5, Figure 6, and Figure 8 ................. 6 Added Figure 4 and Figure 7; Renumbered Sequentially ........... 6 Added Figure 9 and Figure 12......................................................... 7 Changes to Figure 10, Figure 11, Figure 13, and Figure 14......... 7 Changes to Figure 16, Figure 17, Figure 19, and Figure 20......... 8 Changes to Figure 22 and Figure 25............................................... 9 Changes to Figure 36...................................................................... 11 Changes to Figure 54...................................................................... 14 Changes to and Moved Figure 57 and Figure 60 to ................... 15 Changes to Figure 59 and Figure 62............................................. 15 Changes to Input Protection Section and Phase Reversal Section.............................................................................. 16 Changes to DAC Output Filter Section ....................................... 17 Changes to Figure 67...................................................................... 18 Updated Outline Dimensions ....................................................... 22 Changes to Ordering Guide .......................................................... 22 10/08—Revision 0: Initial Version Rev. B | Page 2 of 24 Data Sheet ADA4075-2 SPECIFICATIONS VSY = ±15 V, VCM = 0 V, TA = 25°C, SOIC package, unless otherwise noted. Table 2. Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage VOS 0.2 1 mV −40°C ≤ T ≤ +125°C 1.2 mV A Input Bias Current I 30 100 nA B −40°C ≤ TA ≤ +125°C 150 nA Input Offset Current IOS 5 50 nA −40°C ≤ T ≤ +125°C 75 nA A Input Voltage Range −40°C ≤ T ≤ +125°C −12.5 +12.5 V A Common-Mode Rejection Ratio CMRR V = −12.5 V to +12.5 V 110 118 dB CM −40°C ≤ TA ≤ +125°C 106 dB Large Signal Voltage Gain AVO RL = 2 kΩ, VO = −11 V to +11 V 114 117 dB −40°C ≤ T ≤ +125°C 108 dB A R = 600 Ω, V = −10 V to +10 V 112 117 dB L O −40°C ≤ TA ≤ +125°C 106 dB Offset Voltage Drift ∆VOS/∆T −40°C ≤ TA ≤ +125°C 0.3 μV/°C Input Resistance, Differential Mode RINDM 1.5 MΩ Input Resistance, Common Mode R 500 MΩ INCM Input Capacitance, Differential Mode C 2.4 pF INDM Input Capacitance, Common Mode CINCM 2.1 pF OUTPUT CHARACTERISTICS Output Voltage High VOH RL = 2 kΩ to GND 12.8 13 V −40°C ≤ TA ≤ +125°C 12.5 V RL = 600 Ω to GND 12.4 12.8 V −40°C ≤ T ≤ +125°C 12 V A V = ±18 V, R = 600 Ω to GND 15 15.8 V SY L −40°C ≤ TA ≤ +125°C 14 V Output Voltage Low VOL RL = 2 kΩ to GND −14 −13.6 V −40°C ≤ TA ≤ +125°C −13 V R = 600 Ω to GND −13.6 −13 V L −40°C ≤ T ≤ +125°C −12.5 V A VSY = ±18 V, RL = 600 Ω to GND −16.6 −16 V −40°C ≤ TA ≤ +125°C −15 V Short-Circuit Current I 40 mA SC Closed-Loop Output Impedance Z f = 1 kHz, A = 1 0.1 Ω OUT V POWER SUPPLY Power Supply Rejection Ratio PSRR V = ±4.5 V to ±18 V 106 110 dB SY −40°C ≤ T ≤ +125°C 100 dB A Supply Current per Amplifier ISY VSY = ±4.5 V to ±18 V, IO = 0 mA 1.8 2.25 mA −40°C ≤ TA ≤ +125°C 3.35 mA DYNAMIC PERFORMANCE Slew Rate SR RL = 2 kΩ, AV = 1 12 V/μs Settling Time tS To 0.01%, VIN = 10 V step, RL = 1 kΩ 3 μs Gain Bandwidth Product GBP R = 1 MΩ, C = 35 pF, A = 1 6.5 MHz L L V Phase Margin Φ R = 1 MΩ, C = 35 pF, A = 1 60 Degrees M L L V THD + NOISE Total Harmonic Distortion and Noise THD + N R = 2 kΩ, A = 1, V = 3 V rms, f = 1 kHz 0.0002 % L V IN NOISE PERFORMANCE Voltage Noise e p-p f = 0.1 Hz to 10 Hz 60 nV p-p n Voltage Noise Density e f = 1 kHz 2.8 nV/√Hz n Current Noise Density in f = 1 kHz 1.2 pA/√Hz Rev. B | Page 3 of 24 ADA4075-2 Data Sheet V = ±15 V, V = 0 V, T = 25°C, LFCSP package, unless otherwise noted. SY CM A Table 3. Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage VOS 0.3 1 mV −40°C ≤ T ≤ +125°C 1.5 mV A Input Bias Current IB 30 100 nA −40°C ≤ T ≤ +125°C 150 nA A Input Offset Current IOS 5 50 nA −40°C ≤ TA ≤ +125°C 75 nA Input Voltage Range −40°C ≤ T ≤ +125°C −12.5 +12.5 V A Common-Mode Rejection Ratio CMRR VCM = −12.5 V to +12.5 V 110 116 dB −40°C ≤ T ≤ +125°C 106 dB A Large Signal Voltage Gain A R = 2 kΩ, V = −11 V to +11 V 110 117 dB VO L O −40°C ≤ TA ≤ +125°C 102 dB R = 600 Ω, V = −10 V to +10 V 108 117 dB L O −40°C ≤ TA ≤ +125°C 100 dB Offset Voltage Drift ∆V/∆T −40°C ≤ T ≤ +125°C 3 μV/°C OS A Input Resistance, Differential Mode R 1.5 MΩ INDM Input Resistance, Common Mode RINCM 500 MΩ Input Capacitance, Differential Mode C 2.4 pF INDM Input Capacitance, Common Mode CINCM 2.1 pF OUTPUT CHARACTERISTICS Output Voltage High VOH RL = 2 kΩ to GND 12.8 13 V −40°C ≤ T ≤ +125°C 12.5 V A RL = 600 Ω to GND 12.4 12.8 V −40°C ≤ TA ≤ +125°C 12 V V = ±18 V, R = 600 Ω to GND 15 15.8 V SY L −40°C ≤ TA ≤ +125°C 14 V Output Voltage Low V R = 2 kΩ to GND −14 −13.6 V OL L −40°C ≤ TA ≤ +125°C −13 V RL = 600 Ω to GND −13.6 −13 V −40°C ≤ T ≤ +125°C −12.5 V A VSY = ±18 V, RL = 600 Ω to GND −16.6 −16 V −40°C ≤ T ≤ +125°C −15 V A Short-Circuit Current I 40 mA SC Closed-Loop Output Impedance ZOUT f = 1 kHz, AV = 1 0.1 Ω POWER SUPPLY Power Supply Rejection Ratio PSRR V = ±4.5 V to ±18 V 100 104 dB SY −40°C ≤ TA ≤ +125°C 95 dB Supply Current per Amplifier ISY VSY = ±4.5 V to ±18 V, IO = 0 mA 1.8 2.25 mA −40°C ≤ T ≤ +125°C 3.35 mA A DYNAMIC PERFORMANCE Slew Rate SR RL = 2 kΩ, AV = 1 12 V/μs Settling Time tS To 0.01%, VIN = 10 V step, RL = 1 kΩ 3 μs Gain Bandwidth Product GBP R = 1 MΩ, C = 35 pF, A = 1 6.5 MHz L L V Phase Margin ΦM RL = 1 MΩ, CL = 35 pF, AV = 1 60 Degrees THD + NOISE Total Harmonic Distortion and Noise THD + N RL = 2 kΩ, AV = 1, VIN = 3 V rms, f = 1 kHz 0.0002 % NOISE PERFORMANCE Voltage Noise e p-p f = 0.1 Hz to 10 Hz 60 nV p-p n Voltage Noise Density en f = 1 kHz 2.8 nV/√Hz Current Noise Density i f = 1 kHz 1.2 pA/√Hz n Rev. B | Page 4 of 24 Data Sheet ADA4075-2 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 4. θ is specified for the worst-case conditions, that is, a device JA Parameter Rating soldered in a circuit board for surface-mount packages. This Supply Voltage ±20 V was measured using a standard 4-layer board. Input Voltage ±V SY 1 Input Current ±10 mA Table 5. Thermal Resistance Differential Input Voltage ±1.2 V Package Type θ θ Unit JA JC Output Short-Circuit Duration to GND Indefinite 8-Lead SOIC 158 43 °C/W Storage Temperature Range −65°C to +150°C 8-Lead LFCSP 115 40 °C/W Operating Temperature Range −40°C to +125°C Junction Temperature Range −65°C to +150°C POWER SEQUENCING Lead Temperature (Soldering, 60 sec) 300°C The op amp supplies must be established simultaneously with, 1 or before, any input signals that are applied. If this is not possible, The input pins have clamp diodes to the power supply pins. limit the input current to 10 mA. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any ESD CAUTION other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. B | Page 5 of 24 ADA4075-2 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted. 250 250 V = ±15V V = ±5V SY SY V = 0V V = 0V CM CM BASED ON 600 OP AMPS BASED ON 600 OP AMPS SOIC PACKAGE SOIC PACKAGE 200 200 150 150 100 100 50 50 0 0 –1.0 –0.5 0 0.5 1.0 –1.0 –0.5 0 0.5 1.0 V (mV) V (mV) OS OS Figure 3. Input Offset Voltage Distribution Figure 6. Input Offset Voltage Distribution 100 100 V = ±15V V = ±5V SY SY V = 0V V = 0V CM CM BASED ON 300 OP AMPS BASED ON 300 OP AMPS LFCSP PACKAGE LFCSP PACKAGE 80 80 60 60 40 40 20 20 0 0 –1.0 –0.5 0 0.5 1.0 –1.0 –0.5 0 0.5 1.0 V (mV) V (mV) OS OS Figure 4. Input Offset Voltage Distribution Figure 7. Input Offset Voltage Distribution 70 80 V = ±15V V = ±5V SY SY –40°C ≤ T ≤ +125°C –40°C ≤ T ≤ +125°C A A 70 60 BASED ON 200 OP AMPS BASED ON 200 OP AMPS SOIC PACKAGE SOIC PACKAGE 60 50 50 40 40 30 30 20 20 10 10 0 0 –2.0 –1.6 –1.2 –0.8 –0.4 0 0.4 0.8 1.2 1.6 2.0 –2.0 –1.6 –1.2 –0.8 –0.4 0 0.4 0.8 1.2 1.6 2.0 TCV (μV/°C) TCV (μV/°C) OS OS Figure 5. Input Offset Voltage Drift Distribution Figure 8. Input Offset Voltage Drift Distribution Rev. B | Page 6 of 24 NUMBER OF AMPLIFIERS NUMBER OF AMPLIFIERS NUMBER OF AMPLIFIERS 07642-004 07642-040 07642-003 NUMBER OF AMPLIFIERS NUMBER OF AMPLIFIERS NUMBER OF AMPLIFIERS 07642-007 07642-042 07642-006 Data Sheet ADA4075-2 40 40 V = ±15V V = ±5V SY SY V = 0V V = 0V CM CM 35 35 BASED ON 300 OP AMPS BASED ON 300 OP AMPS LFCSP PACKAGE LFCSP PACKAGE 30 30 25 25 20 20 15 15 10 10 5 5 0 0 01 23456 7 8 0 1 234 5 678 TCV (µV/°C) TCV (µV/°C) OS OS Figure 9. Input Offset Voltage Drift Distribution Figure 12. Input Offset Voltage Drift Distribution 300 300 V = ±15V SY V = ±5V SY BASED ON 60 OP AMPS BASED ON 60 OP AMPS 200 200 100 100 0 0 –100 –100 –200 –200 –300 –300 –15 –10 –5 0 5 10 15 –5 –4 –3 –2 –1 0 1 2 3 4 5 V (V) CM V (V) CM Figure 10. Input Offset Voltage vs. Common-Mode Voltage Figure 13. Input Offset Voltage vs. Common-Mode Voltage 80 100 V = ±15V SY V = ±5V SY 80 60 60 40 40 20 20 0 0 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 11. Input Bias Current vs. Temperature Figure 14. Input Bias Current vs. Temperature Rev. B | Page 7 of 24 I (nA) V (μV) B OS NUMBER OF AMPLIFIERS 07642-043 07642-009 07642-005 I (nA) V (μV) B OS NUMBER OF AMPLIFIERS 07642-052 07642-012 07642-008 ADA4075-2 Data Sheet 60 60 V = ±15V V = ±5V SY SY 50 50 40 40 30 30 20 20 10 10 0 0 –15 –10 –5 0 5 10 15 –4 –3 –2 –1 01234 V (V) V (V) CM CM Figure 15. Input Bias Current vs. Input Common-Mode Voltage Figure 18. Input Bias Current vs. Input Common-Mode Voltage 10 10 V = ±15V SY V = ±5V SY V+ – V V+ – V OH OH 1 1 V – V– V – V– OL OL 0.1 0.1 0.001 0.01 0.1 1 10 100 0.001 0.01 0.1 1 10 100 LOAD CURRENT (mA) LOAD CURRENT (mA) Figure 16. Output Voltage to Supply Rail vs. Load Current Figure 19. Output Voltage to Supply Rail vs. Load Current 2.5 2.0 V = ±15V SY V = ±5V SY R = 2kΩ L V+ – V R = 2kΩ L OH 2.0 V+ – V OH 1.5 1.5 1.0 V – V– OL 1.0 V – V– OL 0.5 0.5 0 0 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 17. Output Voltage to Supply Rail vs. Temperature Figure 20. Output Voltage to Supply Rail vs. Temperature Rev. B | Page 8 of 24 OUTPUT VOLTAGE TO SUPPLY RAIL (V) OUTPUT VOLTAGE TO SUPPLY RAIL (V) I (nA) B 07642-011 07642-010 07642-047 OUTPUT VOLTAGE TO SUPPLY RAIL (V) OUTPUT VOLTAGE TO SUPPLY RAIL (V) I (nA) B 07642-014 07642-013 07642-049 Data Sheet ADA4075-2 140 140 140 140 V = ±15V V = ±5V SY SY 120 120 120 120 100 100 100 100 PHASE PHASE 80 80 80 80 60 60 60 60 GAIN 40 40 40 40 20 GAIN 20 20 20 0 0 0 0 –20 –20 –20 –20 –40 –40 –40 –40 –60 –60 –60 –60 –80 –80 –80 –80 –100 –100 –100 –100 1k 10k 100k 1M 10M 100M 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) Figure 21. Open-Loop Gain and Phase vs. Frequency Figure 24. Open-Loop Gain and Phase vs. Frequency 50 50 V = ±15V V = ±5V SY SY A = +100 A = +100 V V 40 40 30 30 A = +10 A = +10 V V 20 20 10 10 A = +1 A = +1 V V 0 0 –10 –10 –20 –20 10 100 1k 10k 100k 1M 10M 100M 10 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) Figure 22. Closed-Loop Gain vs. Frequency Figure 25. Closed-Loop Gain vs. Frequency 1k 1k V = ±15V V = ±5V SY SY A = +10 100 V 100 A = +10 V 10 10 A = +100 A = +100 V V A = +1 V A = +1 V 1 1 0.1 0.1 0.01 0.01 0.001 0.001 10 100 1k 10k 100k 1M 10M 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure 26. Output Impedance vs. Frequency Figure 23. Output Impedance vs. Frequency Rev. B | Page 9 of 24 GAIN (dB) GAIN (dB) Z (Ω) OUT 07642-017 07642-117 PHASE (Degrees) 07642-015 GAIN (dB) GAIN (dB) Z (Ω) OUT 07642-020 07642-120 PHASE (Degrees) 07642-018 ADA4075-2 Data Sheet 140 140 V = ±15V V = ±5V SY SY 120 120 100 100 80 80 60 60 40 40 20 20 0 0 100 1k 10k 100k 1M 10M 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure 27. CMRR vs. Frequency Figure 30. CMRR vs. Frequency 120 120 V = ±15V V = ±5V SY SY 100 100 80 80 60 60 PSRR– PSRR– PSRR+ PSRR+ 40 40 20 20 0 0 –20 –20 10 100 1k 10k 100k 1M 10M 100M 10 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) Figure 28. PSRR vs. Frequency Figure 31. PSRR vs. Frequency 40 40 V = ±5V V = ±15V SY SY A = +1 A = +1 V V 35 35 R = 2kΩ R = 2kΩ L L 30 30 25 25 20 20 15 15 10 10 5 5 0 0 10 100 1000 10 100 1000 CAPACITANCE (pF) CAPACITANCE (pF) Figure 32. Small Signal Overshoot vs. Load Capacitance Figure 29. Small Signal Overshoot vs. Load Capacitance Rev. B | Page 10 of 24 PSRR (dB) CMRR (dB) OVERSHOOT (%) 07642-023 07642-022 07642-021 PSRR (dB) OVERSHOOT (%) CMRR (dB) 07642-024 07642-026 07642-025 Data Sheet ADA4075-2 V = ±15V V = ±5V SY SY V = 20V p-p V = 7V p-p IN IN A = +1 A = +1 V V R = 2kΩ R = 2kΩ L L C = 100pF C = 100pF L L 0V 0V TIME (4µs/DIV) TIME (4µs/DIV) Figure 33. Large Signal Transient Response Figure 36. Large Signal Transient Response V = ±15V SY V = 100mV p-p IN V = ±5V SY A = +1 V V = 100mV p-p IN R = 2kΩ L A = +1 V C = 100pF L R = 2kΩ 0V L 0V C = 100pF L TIME (10µs/DIV) TIME (10µs/DIV) Figure 34. Small Signal Transient Response Figure 37. Small Signal Transient Response 4 4 V = ±15V V = ±5V SY SY 2 2 INPUT INPUT 0 0 OUTPUT OUTPUT 0 0 –5 –2 –10 –4 –15 –6 –20 –8 TIME (1µs/DIV) TIME (1µs/DIV) Figure 35. Negative Overload Recovery Figure 38. Negative Overload Recovery Rev. B | Page 11 of 24 INPUT VOLTAGE (V) VOLTAGE (20mV/DIV) VOLTAGE (5V/DIV) 07642-028 07642-027 OUTPUT VOLTAGE (V) 07642-029 INPUT VOLTAGE (V) VOLTAGE (2V/DIV) VOLTAGE (20mV/DIV) 07642-031 07642-030 OUTPUT VOLTAGE (V) 07642-032 ADA4075-2 Data Sheet 4 4 V = ±15V V = ±5V SY SY 2 2 INPUT INPUT 0 0 –2 –2 15 4 10 2 5 OUTPUT OUTPUT 0 0 –5 –2 –10 –4 TIME (1µs/DIV) TIME (1µs/DIV) Figure 42. Positive Overload Recovery Figure 39. Positive Overload Recovery V = ±5V V = ±15V SY SY INPUT INPUT +6mV +10mV OUTPUT OUTPUT 0V 0V ERROR BAND ERROR BAND –10mV –6mV TIME (2µs/DIV) TIME (2µs/DIV) Figure 40. Positive Settling Time to 0.01% Figure 43. Positive Settling Time to 0.01% V = ±5V V = ±15V SY SY INPUT INPUT +6mV +10mV ERROR BAND OUTPUT OUTPUT 0V 0V ERROR BAND –10mV –6mV TIME (2µs/DIV) TIME (2µs/DIV) Figure 41. Negative Settling Time to 0.01% Figure 44. Negative Settling Time to 0.01% Rev. B | Page 12 of 24 INPUT VOLTAGE (V) VOLTAGE (5V/DIV) VOLTAGE (5V/DIV) 07642-064 07642-061 OUTPUT VOLTAGE (V) 07642-033 INPUT VOLTAGE (V) VOLTAGE (5V/DIV) VOLTAGE (5V/DIV) 07642-062 07642-063 OUTPUT VOLTAGE (V) 07642-034 Data Sheet ADA4075-2 10 10 V = ±5V V = ±15V SY SY 1 1 1 10 100 1k 10k 100k 1 10 100 1k 10k 100k FREQUENCY (Hz) FREQUENCY (Hz) Figure 45. Voltage Noise Density Figure 48. Voltage Noise Density 10 10 V = ±15V R V = ±5V SY R SY S1 S1 R R S2 S2 UNCORRELATED UNCORRELATED R = 0Ω R = 0Ω S1 S1 1 1 CORRELATED CORRELATED R = R R = R S1 S2 S1 S2 0.1 0.1 1 10 100 1k 10k 100k 1 10 100 1k 10k 100k FREQUENCY (Hz) FREQUENCY (Hz) Figure 49. Current Noise Density Figure 46. Current Noise Density V = ±5V V = ±15V SY SY TIME (1s/DIV) TIME (1s/DIV) Figure 47. 0.1 Hz to 10 Hz Noise Figure 50. 0.1 Hz to 10 Hz Noise Rev. B | Page 13 of 24 CURRENT NOISE DENSITY (pA/ Hz) VOLTAGE NOISE DENSITY (nV/√Hz) INPUT NOISE VOLTAGE (10nV/DIV) 07642-036 07642-045 07642-035 CURRENT NOISE DENSITY (pA/ Hz) VOLTAGE NOISE DENSITY (nV/√Hz) INPUT NOISE VOLTAGE (10nV/DIV) 07642-039 07642-046 07642-038 ADA4075-2 Data Sheet 8 6 5 6 V = ±15V SY +125°C 4 +85°C V = ±5V SY 4 3 +25°C 2 –40°C 2 1 0 0 4 6 8 101214 1618 –50 –25 0 25 50 75 100 125 SUPPLY VOLTAGE (±V) TEMPERATURE (°C) Figure 54. Supply Current vs. Temperature Figure 51. Supply Current vs. Supply Voltage 10 10 V = ±5V V = ±15V SY SY f = 1kHz f = 1kHz 1 1 0.1 0.1 0.01 0.01 0.001 600Ω 0.001 600Ω 0.0001 0.0001 2kΩ 2kΩ 0.00001 0.00001 0.0001 0.001 0.01 0.1 1 10 0.0001 0.001 0.01 0.1 1 10 AMPLITUDE (V rms) AMPLITUDE (V rms) Figure 52. THD + Noise vs. Amplitude Figure 55. THD + Noise vs. Amplitude 1 1 V = ±15V V = ±5V SY SY V = 3V rms IN V = 1.5V rms IN 0.1 0.1 0.01 0.01 600Ω 0.001 0.001 600Ω 2kΩ 2kΩ 0.0001 0.0001 10 100 1k 10k 100k 10 100 1k 10k 100k FREQUENCY (Hz) FREQUENCY (Hz) Figure 53. THD + Noise vs. Frequency Figure 56. THD + Noise vs. Frequency Rev. B | Page 14 of 24 THD + NOISE (%) THD + NOISE (%) SUPPLY CURRENT (mA) 07642-048 07642-060 07642-058 THD + NOISE (%) THD + NOISE (%) SUPPLY CURRENT (mA) 07642-067 07642-057 07642-065 Data Sheet ADA4075-2 0 0 V = ±15V V = ±5V SY 100kΩ SY 100kΩ V = 10V p-p V = 5V p-p IN IN 1kΩ 1kΩ –20 R = 2kΩ –20 R = 2kΩ L L –40 –40 R R L L –60 –60 –80 –80 –100 –100 –120 –120 –140 –140 100 1k 10k 100k 100 1k 10k 100k FREQUENCY (Hz) FREQUENCY (Hz) Figure 57. Channel Separation vs. Frequency Figure 60. Channel Separation vs. Frequency 10 1 V = ±18V V = ±18V SY SY V = 8V rms f = 1kHz IN 1 0.1 0.1 0.01 0.01 0.001 0.001 600Ω 600Ω 2kΩ 0.0001 0.0001 2kΩ 0.00001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 10 100 1k 10k 100k AMPLITUDE (V rms) FREQUENCY (Hz) Figure 61. THD + Noise vs. Frequency Figure 58. THD + Noise vs. Amplitude 10 2.5 V = ±18V V = ±18V SY SY R = 2kΩ L 2.0 V+ – V OH V+ – V OH 1.5 1 V – V– OL V – V– OL 1.0 0.5 0.1 0 0.001 0.01 0.1 1 10 100 –50 –25 0 25 50 75 100 125 LOAD CURRENT (mA) TEMPERATURE (°C) Figure 59. Output Voltage to Supply Rail vs. Temperature Figure 62. Output Voltage to Supply Rail vs. Load Current Rev. B | Page 15 of 24 THD + NOISE (%) OUTPUT VOLTAGE TO SUPPLY RAIL (V) CHANNEL SEPARATION (dB) 07642-066 07642-041 07642-056 THD + NOISE (%) OUTPUT VOLTAGE TO SUPPLY RAIL (V) CHANNEL SEPARATION (dB) 07642-068 07642-044 07642-059 ADA4075-2 Data Sheet APPLICATIONS INFORMATION 1 INPUT PROTECTION To prevent base-emitter junction breakdown from occurring in the input stage of the ADA4075-2 when a very large differential 0.1 voltage is applied, the inputs are clamped by the internal diodes to ±1.2 V. To preserve the ultralow voltage noise feature of the V = ±4V SY ADA4075-2, the commonly used internal current-limiting 0.01 R = 2kΩ L V = 1.5V rms IN resistors in series with the inputs are not used. V = ±15V SY In small signal applications, current limiting is not required; R = 2kΩ L 0.001 V = 3V rms however, in applications where the differential voltage of the IN ADA4075-2 exceeds ±1.2 V, large currents may flow through these diodes. Employ external current-limiting resistors as 0.0001 shown in Figure 63 to reduce the input currents to less than 10 100 1k 10k 100k FREQUENCY (Hz) ±10 mA. Note that depending on the value of these resistors, the total voltage noise will most likely be degraded. For example, Figure 64. THD + Noise vs. Frequency a 1 kΩ resistor at room temperature has a thermal noise of PHASE REVERSAL 4 nV/√Hz, whereas the ADA4075-2 has an ultralow voltage An undesired phenomenon, phase reversal (also known as phase noise of only 2.8 nV/√Hz typical. inversion) occurs in many op amps when one or both of the ADA4075-2 inputs are driven beyond the specified input common-mode R1 2 voltage (VICM) range, in effect reversing the polarity of the output. 1 In some cases, phase reversal can induce lockups and cause R2 3 equipment damage as well as self destruction. The ADA4075-2 incorporates phase reversal prevention circuitry that clamps the output to 2 V typical from the supply rails when Figure 63. Input Protection one or both inputs exceed the V range. Figure 65 shows the ICM TOTAL HARMONIC DISTORTION input/output waveforms of the ADA4075-2 configured as a unity- The total harmonic distortion + noise (THD + N) of the gain buffer for a supply voltage of ±15 V. ADA4075-2 is 0.0002% typical with a load resistance of 2 kΩ. V = ±15V SY V Figure 64 shows the performance of the ADA4075-2 driving a IN 2 kΩ load with supply voltages of ±4 V and ±15 V. Notice that there is more distortion for the supply voltage of ±4 V than for a V OUT supply voltage of ±15 V. Therefore, it is important to operate the ADA4075-2 at a supply voltage greater than ±5 V for optimum distortion. The THD + noise graphs for supply voltages of ±5 V and ±18 V are available in Figure 56 and Figure 61. TIME (40µs/DIV) Figure 65. No Phase Reversal Rev. B | Page 16 of 24 07642-050 THD + NOISE (%) VOLTAGE (5V/DIV) 07642-053 07642-069 Data Sheet ADA4075-2 For a DAC output filter, an op amp with reasonable slew rate and DAC OUTPUT FILTER bandwidth is required. The ADA4075-2 has a high slew rate of the The ultralow voltage noise, low distortion, and high slew rate of 12 V/μs and a relatively wide bandwidth of 6.5 MHz. The cutoff the ADA4075-2 make it an ideal choice for professional audio frequency of the low-pass filter is approximately 167 kHz. In signal processing. Figure 66 shows the ADA4075-2 used in a addition, the 100 kΩ − 47 μF RC network provides ac coupling typical audio DAC output filter configuration. The differential to block out the dc components at the output. outputs of the DAC are fed into the ADA4075-2. The ADA4075-2 is configured as a differential Sallen-Key filter. It operates as an external low-pass filter to remove high frequency noise present on the output pins of the DAC. It also provides differential-to- single-ended conversion from the differential outputs of the DAC. 11kΩ 68pF 11kΩ 3.01kΩ 47µF DAC OUTN 100Ω 1/2 OUTPUT 5.62kΩ 1.5kΩ DAC OUTP 2.2nF 100kΩ ADA4075-2 560pF 5.62kΩ 270pF 150pF Figure 66. Typical DAC Output Filter Circuit (Differential) Rev. B | Page 17 of 24 + 07642-054 ADA4075-2 Data Sheet Finally, even with these precautions, it is vital that the positive BALANCED LINE DRIVER feedback be accurately controlled. This is partly achieved by The circuit of Figure 67 shows a balanced line driver designed using 1% resistors. In addition, the following setup procedure for audio use. Such drivers are intended to mimic an output ensures that the positive feedback does not become excessive: transformer in operation, whereby the common-mode voltage can be impressed by the load. Furthermore, either output can be 1. Set R11 to its midposition (or short the ends together, shorted to ground in single-ended applications without affecting whichever is easier) and temporarily short the negative the overall operation. output to ground. 2. Apply a 10 V p-p sine wave at approximately 1 kHz to the Circuits of this type use positive and negative feedback to obtain a input and adjust R7 to provide 930 mV p-p at TEST (see high common-mode output impedance, and they are somewhat Figure 67). notorious for component sensitivity and susceptibility to latch-up. 3. Remove the short from the negative output (and across This circuit uses several techniques to avoid spurious behavior. R11, if used) and adjust R11 until the output waveforms First, the 4-op-amp arrangement ensures that the input impedance are symmetric. is load independent (the input impedance can become negative The overall gain of the driver is equal to 2, which provides an with some configurations). Note that the output op amps are extra 6 dB of headroom in balanced differential mode. The packaged with the input op amps to maximize drive capability. output noise is about −109 dBV in a 20 kHz bandwidth. Second, the positive feedback is ac-coupled by C2 and C3, which eliminates the need for offset trim. Because the circuit is ac-coupled at the input, these capacitors do not have significant dc voltage across them, thus tantalum types of capacitors can be used. C5 IN 50pF C1 R4 R5 10µF A1 4.7kΩ 4.7kΩ A2 1/2 R1 R13 10kΩ 1/2 OUT+ 100Ω ADA4075-2 ADA4075-2 R18 4.7kΩ R7 250Ω R6 R8 R9 R2 4.7kΩ 4.7kΩ 100Ω 4.7kΩ FEEDBACK TRIM C4 50pF SYMMETRY TEST C3 C2 TRIM R3 R10 R12 10µF 10µF 4.7kΩ 4.7kΩ 4.7kΩ R11 250Ω A3 C6 1/2 50pF A4 R14 ADA4075-2 OUT– 1/2 R15 100Ω 4.7kΩ ADA4075-2 R16 R17 100Ω 4.7kΩ NOTES 1. ALL RESISTORS SHOULD HAVE 1% TOLERANCE. 2. A1/A2 IN SAME PACKAGE; A3/A4 IN SAME PACKAGE. Figure 67. Balanced Line Driver Rev. B | Page 18 of 24 07642-073 Data Sheet ADA4075-2 Note that A3 is not in the signal path, and almost any op amp BALANCED LINE RECEIVER works well here. Although it may seem as though the inverting Figure 68 depicts a unity-gain balanced line receiver capable of output should be noisier than the noninverting one, they are in a high degree of hum rejection. The CMRR is approximately fact symmetric at about −111 dBV (20 kHz bandwidth). given by Sometimes an overall gain of ½ is desired to provide an extra   R1R4 6 dB of differential input headroom. This can be attained by   20 log 10   R2R3 reducing R3 and R4 to 5 kΩ and increasing R9 to 22 kΩ.   Therefore, R1 to R4 should be close tolerance components to obtain the best possible CMRR without adjustment. The presence of A2 ensures that the impedances are symmetric at the two inputs (unlike many other designs), and, as a bonus, A2 also provides a complementary output. A3 raises the common-mode input impedance from approximately 7.5 kΩ to approximately 70 kΩ, reducing the degradation of CMRR due to mismatches in source impedance. C2 50pF R3 OUT+ C3 10kΩ 50pF R6 R1 5kΩ A1 IN– R5 A2 5kΩ 1/2 R2 5kΩ IN+ 1/2 OUT– 5kΩ ADA4075-2 ADA4075-2 R7 R8 5.6kΩ 5.6kΩ R4 10kΩ C1 A3* 22µF (NON-POLAR) R9 R10 11kΩ 11kΩ *A3 REDUCES THE DEGRADATION OF CMRR (SEE THE BALANCED LINE RECEIVER SECTION FOR MORE DETAILS). Figure 68. Balanced Line Receiver Rev. B | Page 19 of 24 07642-071 ADA4075-2 Data Sheet The bandwidth control adjusts the Q from 0.9 to about 11. The LOW NOISE PARAMETRIC EQUALIZER overall noise is setting dependent, but with all controls centered, The circuit in Figure 69 is a reciprocal parametric equalizer it is about −104 dBV in a 20 kHz bandwidth. Such a low noise yielding ±20 dB of cut or boost with variable bandwidth and level can obviate the need for a bypass switch in many applications. frequency. The frequency control range is 6.9:1, with the geometric mean center frequency conveniently occurring at the midpoint of the potentiometer setting. The center frequency is equal to 48 Hz/Ct, where Ct is the value of C1 and C2 in microfarads. 47µF 6.2kΩ 6.2kΩ IN OUT 620Ω ADA4075-2 1/2 100Ω BOOST CUT BANDWIDTH 1kΩ 5kΩ 2.7kΩ 1.5kΩ ADA4075-2 C1* C2* 1.5kΩ 1/2 1.3kΩ 1.3kΩ 2.5kΩ 2.5kΩ 2.5kΩ 2.5kΩ 1/2 1/2 ADA4075-2 ADA4075-2 620Ω 620Ω FREQUENCY (GANGED POTENTIOMETER) *THE CENTER FREQUENCY IS AFFECTED BY THE VALUE OF C1 AND C2 (SEE THE LOW NOISE PARAMETRIC EQUALIZER SECTION FOR MORE DETAILS). Figure 69. Low Noise Parametric Equalizer Rev. B | Page 20 of 24 07642-074 Data Sheet ADA4075-2 SCHEMATIC V+ OUTA/ OUTB –INA/ +INA/ –INB +INB V– Figure 70. Simplified Schematic Rev. B | Page 21 of 24 07642-072 ADA4075-2 Data Sheet OUTLINE DIMENSIONS 5.00 (0.1968) 4.80 (0.1890) 85 6.20 (0.2441) 4.00 (0.1574) 1 5.80 (0.2284) 3.80 (0.1497) 4 0.50 (0.0196) 1.27 (0.0500) 45° BSC 1.75 (0.0688) 0.25 (0.0099) 1.35 (0.0532) 0.25 (0.0098) 8° 0.10 (0.0040) 0° 0.51 (0.0201) COPLANARITY 1.27 (0.0500) 0.10 0.31 (0.0122) 0.25 (0.0098) SEATING 0.40 (0.0157) PLANE 0.17 (0.0067) COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 71. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 0.30 2.00 0.25 0.50 BSC BSC SQ 0.18 8 5 0.65 0.60 4 1 PIN 1 INDEX 0.55 AREA TOP VIEW BOTTOM VIEW 0.60 0.05 MAX 0.55 0.02 NOM 0.50 SEATING PLANE 0.20 REF Figure 72. 8-Lead Lead Frame Chip Scale Package [LFCSP_WD] 2 mm × 2 mm Body, Very Very Thin, Dual Lead (CP-8-6) Dimensions shown in millimeters ORDERING GUIDE 1 Model Temperature Range Package Description Package Option Branding ADA4075-2ARZ −40°C to +125°C 8-Lead SOIC_N R-8 ADA4075-2ARZ-R7 −40°C to +125°C 8-Lead SOIC_N R-8 ADA4075-2ARZ-RL −40°C to +125°C 8-Lead SOIC_N R-8 ADA4075-2ACPZ-R7 −40°C to +125°C 8-Lead LFCSP_WD CP-8-6 A0 ADA4075-2ACPZ-RL −40°C to +125°C 8-Lead LFCSP_WD CP-8-6 A0 1 Z = RoHS Compliant Part. Rev. B | Page 22 of 24 PIN 1 INDICATOR 012407-A 051608-A Data Sheet ADA4075-2 NOTES Rev. B | Page 23 of 24 ADA4075-2 Data Sheet NOTES ©2008–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07642-0-12/11(B) Rev. B | Page 24 of 24