ANALOG DEVICES ADA4062-2

Low Power JFET-Input Op Amps ADA4062-2/ADA4062-4 FEATURES PIN CONFIGURATIONS Low input bias current: 50 pA maximum OUT A 1 8 V+ ADA4062-2 Offset voltage –IN A 2 7 OUT B TOP VIEW 1.5 mV maximum for B grade (ADA4062-2 SOIC package) +IN A 3 6 –IN B (Not to Scale) V– 4 5 +IN B 2.5 mV maximum for A grade Offset voltage drift: 5 μV/°C typical Figure 1. 8-Lead Narrow-Body SOIC and 8-Lead MSOP Slew rate: 3.3 V/μs typical CMRR: 90 dB typical Low supply current: 165 μA typical High input impedance Unity-gain stable N A 8 OUT B –I 2 ±5 V to ±15 V dual-supply operation ADA4062-2 +IN A 3 7 –IN B TOP VIEW Packaging (Not to Scale) 8-lead SOIC, 8-lead MSOP, 10-lead LFCSP, 14-lead TSSOP, and 16-lead LFCSP packages NC = NO CONNECT APPLICATIONS Figure 2. 10-Lead LFCSP Power controls and monitoring 1 Active filters OUT A 14 OUT D 2 Industrial/process controls –IN A 13 –IN D 3 Body probe electronics +IN A ADA4062-4 12 +IN D TOP VIEW 4 11 Data acquisition V+ V– (Not to Scale) 5 10 Integrators +IN B +IN C 6 9 Input buffering –IN B –IN C 7 8 OUT B OUT C GENERAL DESCRIPTION Figure 3. 14-Lead TSSOP The ADA4062-2 and ADA4062-4 are dual and quad JFET-input amplifiers with industry-leading performance. They offer lower power, offset voltage, drift, and ultralow bias current. The ADA4062-2 B grade (SOIC package) features a typical low offset voltage of 0.5 mV, an offset drift of 5 μV/°C, and a bias current –IN A 1 12 –IN D of 2 pA. ADA4062-4 +IN A 2 11 +IN D TOP VIEW The ADA4062 family is ideal for various applications, including V+ 3 10 V– (Not to Scale) +IN B 4 9 +IN C process controls, industrial and instrumentation equipment, active filtering, data conversion, buffering, and power control and monitoring. With a low supply current of 165 μA per amplifier, they are well suited for lower power applications. NOTES 1. NC = NO CONNECT. The ADA4062 family is also specified for the extended industrial 2. IT IS RECOMMENDED TO CONNECT THE EXPOSED PAD TO V–. temperature range of −40°C to +125°C. The ADA4062-2 is Figure 4. 16-Lead LFCSP available in lead-free, 8-lead SOIC, 8-lead MSOP, and 10-lead Table 1. Low Power Op Amps LFCSP (1.6 mm × 1.3 mm × 0.55 mm) packages, while the Precision Precision High ADA4062-4 is available in lead-free, 14-lead TSSOP and CMOS High Bandwidth Bandwidth 16-lead LFCSP packages. Single AD8663 AD8641 Dual AD8667 AD8642 AD8682 Quad AD8669 AD8643 AD8684 Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2008–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. –IN B NC OUT A OUT B OUT D OUT C –IN C NC 07670-064 07670-001 07670-065 07670-068 5 16 6 15 V– 4 1 OUT A 7 14 NC 5 10 NC 8 13 +IN B 6 9 V+ ADA4062-2/ADA4062-4 TABLE OF CONTENTS Features .............................................................................................. 1  ESD Caution...................................................................................5  Applications ....................................................................................... 1  Typical Performance Characteristics ..............................................6  General Description ......................................................................... 1  Applications Information .............................................................. 15  Pin Configurations ........................................................................... 1  Notch Filter ................................................................................. 15  Revision History ............................................................................... 2  High-Side Signal Conditioning ................................................ 15  Specif ica t ions ..................................................................................... 3  Micropower Instrumentation Amplifier ................................. 15  Electrical Characteristics ............................................................. 3  Phase Reversal ............................................................................ 16  Absolute Maximum Ratings ............................................................ 5  Schematic ......................................................................................... 17  Thermal Resistance ...................................................................... 5  Outline Dimensions ....................................................................... 18  Power Sequencing ........................................................................ 5  Ordering Guide .......................................................................... 20  REVISION HISTORY 2/10—Rev. A to Rev. B 7/09—Rev. 0 to Rev. A Added 16-Lead LFCSP Package........................................ Universal Added ADA4062-4 ............................................................. Universal Changes to Features Section, General Description Section, and Added 14-Lead TSSOP Package ....................................... Universal Table 1 ................................................................................................ 1 Added 10-Lead LFCSP Package ....................................... Universal Changes to Offset Voltage Drift Parameter, Table 2 .................... 3 Changes to Features Section and Table 1 ....................................... 1 Changes to Table 4 ............................................................................ 5 Changes to Table 2 ............................................................................. 3 Changes to Typical Performance Characteristics Layout ............ 6 Changes to Thermal Resistance Section ........................................ 5 Changes to Figure 5, Figure 6, Figure 8, and Figure 9 .................. 6 Added Figure 6 and Figure 9; Renumbered Sequentially ........... 6 Changes to Figure 7, Figure 8, and Figure 10 ............................... 6 Changes to Figure 37 and Figure 40............................................. 11 Changes to Figure 25 and Figure 28 ............................................... 9 Changes to Figure 41 and Figure 44............................................. 12 Changes to Figure 37 and Figure 40 ............................................. 11 Changes to Figure 47, Figure 48, Figure 50, and Figure 51....... 13 Changes to Figure 41 to Figure 46 ................................................ 12 Added Figure 49 and Figure 52; Renumbered Sequentially ..... 13 Changes to Figure 47 and Figure 50 ............................................. 13 Changes to Figure 57 and Figure 59............................................. 15 Changes to Figure 53 to Figure 58 ................................................ 14 Changes to Phase Reversal Section and Figure 61 ..................... 16 Changes to Notch Filter Section and Micropower Instrumentation Changes to Figure 63 ...................................................................... 17 Updated Outline Dimensions ....................................................... 18 Amplifier Section ............................................................................ 15 Updated Outline Dimensions ....................................................... 18 Changes to Ordering Guide .......................................................... 19 Changes to Ordering Guide .......................................................... 20 10/08—Revision 0: Initial Version Rev. B | Page 2 of 20 ADA4062-2/ADA4062-4 SPECIFICATIONS ELECTRICAL CHARACTERISTICS V = ±15 V, V = 0 V, T = 25°C, unless otherwise noted. SY CM A Table 2. Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage VOS B Grade (ADA4062-2, 8-Lead SOIC Only) 0.5 1.5 mV −40°C ≤ T ≤ +125°C 3 mV A A Grade 0.75 2.5 mV −40°C ≤ TA ≤ +125°C 5 mV Offset Voltage Drift ∆VOS/∆T −40°C ≤ TA ≤ +125°C 5 μV/°C Input Bias Current I 2 50 pA B −40°C ≤ T ≤ +125°C 5 nA A Input Offset Current I 0.5 25 pA OS −40°C ≤ TA ≤ +125°C 2.5 nA Input Voltage Range −40°C ≤ TA ≤ +125°C −11.5 +15 V Common-Mode Rejection Ratio CMRR B Grade (ADA4062-2, 8-Lead SOIC Only) V = −11.5 V to +11.5 V 80 90 dB CM −40°C ≤ T ≤ +125°C 80 dB A A Grade VCM = −11.5 V to +11.5 V 73 90 dB −40°C ≤ TA ≤ +125°C 70 dB Large-Signal Voltage Gain AVO RL = 10 kΩ, VO = −10 V to +10 V 76 83 dB −40°C ≤ T ≤ +125°C 72 dB A Input Resistance R 10 TΩ IN Input Capacitance, Differential Mode C 1.5 pF INDM Input Capacitance, Common Mode CINCM 4.8 pF OUTPUT CHARACTERISTICS Output Voltage High V R = 10 kΩ to V 13 13.5 V OH L CM −40°C ≤ TA ≤ +125°C 12.5 V Output Voltage Low VOL RL = 10 kΩ to VCM −13.8 −13 V −40°C ≤ TA ≤ +125°C −12.5 V Short-Circuit Current I 20 mA SC Closed-Loop Output Impedance Z f = 1 kHz, A = 1 1 Ω OUT V POWER SUPPLY Power Supply Rejection Ratio PSRR B Grade (ADA4062-2, 8-Lead SOIC Only) V = ±4 V to ±18 V 80 90 dB SY −40°C ≤ TA ≤ +125°C 80 dB A Grade VSY = ±4 V to ±18 V 74 90 dB −40°C ≤ TA ≤ +125°C 70 dB Supply Current per Amplifier I I = 0 mA 165 220 μA SY O −40°C ≤ T ≤ +125°C 260 μA A DYNAMIC PERFORMANCE Slew Rate SR R = 10 kΩ, C = 100 pF, A = 1 3.3 V/μs L L V Settling Time t To 0.1%, V = 10 V step, C = 100 pF, 3.5 μs S IN L RL = 10 kΩ, AV = 1 Gain Bandwidth Product GBP RL = 10 kΩ, AV = 1 1.4 MHz Phase Margin ΦM RL = 10 kΩ, AV = 1 78 Degrees Channel Separation (ADA4062-2 Only) CS f = 1 kHz 135 dB Channel Separation (ADA4062-4 Only) CS f = 1 kHz 130 dB Rev. B | Page 3 of 20 ADA4062-2/ADA4062-4 Parameter Symbol Conditions Min Typ Max Unit NOISE PERFORMANCE Voltage Noise en p-p f = 0.1 Hz to 10 Hz 1.5 μV p-p Voltage Noise Density en f = 1 kHz 36 nV/√Hz Current Noise Density i f = 1 kHz 5 fA/√Hz n Rev. B | Page 4 of 20 ADA4062-2/ADA4062-4 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 3. Parameter Rating θ is specified for the worst-case conditions, that is, a device JA soldered in a circuit board for surface-mount packages. It was Supply Voltage ±18 V measured using a standard 4-layer board. Input Voltage ±V SY Differential Input Voltage ±V SY Table 4. Thermal Resistance Input Current ±10 mA Package Type θ θ Unit JA JC Output Short-Circuit Duration to GND Indefinite 8-Lead SOIC 120 45 °C/W Storage Temperature Range −65°C to +150°C 8-Lead MSOP 142 45 °C/W Operating Temperature Range −40°C to +125°C 10-Lead LFCSP 132 46 °C/W Junction Temperature Range −65°C to +150°C 14-Lead TSSOP 112 35 °C/W Lead Temperature (Soldering, 60 sec) 300°C 16-Lead LFCSP 75 12 °C/W Stresses above those listed under Absolute Maximum Ratings POWER SEQUENCING may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any The supply voltages of the op amps must be established other conditions above those indicated in the operational simultaneously with, or before, any input signals are applied. If section of this specification is not implied. Exposure to absolute this is not possible, the input current must be limited to 10 mA. maximum rating conditions for extended periods may affect device reliability. ESD CAUTION Rev. B | Page 5 of 20 ADA4062-2/ADA4062-4 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted. 70 280 V = ±5V V = ±15V SY SY V = 0V V = 0V CM CM BASED ON 600 OP AMPS 60 240 BASED ON 600 OP AMPS 50 200 40 160 30 120 20 80 10 40 0 0 –4 –3 –2 –1 0 1 2 3 4 –4 –3 –2 –1 0 1 2 3 4 V (mV) V (mV) OS OS Figure 5. Input Offset Voltage Distribution Figure 8. Input Offset Voltage Distribution 40 40 ADA4062-2 ONLY ADA4062-2 ONLY V = ±5V V = ±15V SY SY –40°C ≤ T ≤ +125°C –40°C ≤ T ≤ +125°C A A BASED ON 200 OP AMPS BASED ON 200 OP AMPS 30 30 20 20 10 10 0 0 –2 02468 10 –2 0 2 4 6 8 10 TCV (µV/°C) TCV (µV/°C) OS OS Figure 6. Input Offset Voltage Drift Distribution Figure 9. Input Offset Voltage Drift Distribution 25 25 ADA4062-4 ONLY ADA4062-4 ONLY V = ±5V V = ±15V SY SY –40°C ≤ T≤ 125°C –40°C ≤ T≤ 125°C 20 20 BASED ON 200 OP AMPS BASED ON 200 OP AMPS 15 15 10 10 5 5 0 0 0 2 4 6 8 10 12 14 16 18 0 2 4 6 8 10 12141618 TCV (µV/°C) TCV (µV/°C) OS OS Figure 10. Input Offset Voltage Drift Distribution Figure 7. Input Offset Voltage Drift Distribution Rev. B | Page 6 of 20 NUMBER OF AMPLIFIERS NUMBER OF AMPLIFERS NUMBER OF AMPLIFERS 07670-070 07670-055 07670-054 NUMBER OF AMPLIFIERS NUMBER OF AMPLIFERS NUMBER OF AMPLIFERS 07670-069 07670-005 07670-003 ADA4062-2/ADA4062-4 5 5 V = ±5V V = ±15V SY SY 4 4 3 3 2 2 1 1 0 0 –1 –1 –2 –2 –3 –3 –4 –4 –5 –5 –4 –3 –2 –1 0 1 2 3 4 5 –15 –12 –9 –6 –3 0 3 6 9 12 15 V (V) V (V) CM CM Figure 11. Input Offset Voltage vs. Common-Mode Voltage Figure 14. Input Offset Voltage vs. Common-Mode Voltage 10000 10000 V = ±15V V = ±5V SY SY 1000 1000 100 100 10 10 1 1 0.1 0.1 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 12. Input Bias Current vs. Temperature Figure 15. Input Bias Current vs. Temperature 3 5 V = ±5V V = ±15V SY SY 4 2 3 1 2 0 1 –1 0 –2 –3 –2 –1 0 1 2345 –12–10 –8–6–4 –2 0 2 4 6 8 1012 1416 V (V) V (V) CM CM Figure 13. Input Bias Current vs. Common-Mode Voltage Figure 16. Input Bias Current vs. Common-Mode Voltage Rev. B | Page 7 of 20 I (pA) I (pA) V (mV) B B OS 07670-013 07670-012 07670-056 I (pA) I (pA) V (mV) OS B B 07670-010 07670-009 07670-006 ADA4062-2/ADA4062-4 10 10 V = ±15V V = ±5V SY SY V+ – V V+ – V OH OH 1 1 V – V– V – V– OL OL 0.1 0.1 0.01 0.1 1 10 100 0.01 0.1 1 10 100 LOAD CURRENT (mA) LOAD CURRENT (mA) Figure 17. Output Voltage to Supply Rail vs. Load Current Figure 20. Output Voltage to Supply Rail vs. Load Current 220 200 +125°C 200 190 +85°C 180 180 160 170 V = ±15V 140 SY 160 +25°C 120 –40°C 150 100 V = ±5V SY 140 80 130 60 120 40 110 20 0 100 0 2 4 6 8 1012 1416 18 –50 –25 0 25 50 75 100 125 150 SUPPLY VOLTAGE (±V) TEMPERATURE (°C) Figure 18. Supply Current/Amp vs. Supply Voltage Figure 21. Supply Current/Amp vs. Temperature 2.0 2.0 V = ±5V V = ±15V SY SY R = 10kΩ R = 10kΩ L L V+ – V OH 1.5 1.5 V+ – V OH V – V– OL V – V– OL 1.0 1.0 0.5 0.5 0 0 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 19. Output Voltage to Supply Rail vs. Temperature Figure 22. Output Voltage to Supply Rail vs. Temperature Rev. B | Page 8 of 20 SUPPLY CURRENT/AMP (µA) OUTPUT VOTLAGE TO SUPPLY RAIL (V) OUTPUT VOLTAGE TO SUPPLY RAIL (V) 07670-018 07670-014 07670-146 SUPPLY CURRENT/AMP (µA) OUTPUT VOTLAGE TO SUPPLY RAIL (V) OUTPUT VOLTAGE TO SUPPLY RAIL (V) 07670-015 07670-011 07670-149 ADA4062-2/ADA4062-4 120 120 120 120 V = ±5V V = ±15V SY SY 100 PHASE 100 100 100 PHASE 80 80 80 80 60 60 60 60 40 40 40 40 GAIN GAIN 20 20 20 20 0 0 0 0 –20 –20 –20 –20 –40 –40 –40 –40 –60 –60 –60 –60 1k 10k 100k 1M 10M 100M 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) Figure 23. Open-Loop Gain and Phase vs. Frequency Figure 26. Open-Loop Gain and Phase vs. Frequency 50 50 V = ±5V SY V = ±15V SY A = +100 A = +100 V V 40 40 30 30 A = +10 A = +10 V V 20 20 10 10 A = +1 V A = +1 V 0 0 –10 –10 –20 –20 10 100 1k 10k 100k 1M 10M 100M 10 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) Figure 24. Closed-Loop Gain vs. Frequency Figure 27. Closed-Loop Gain vs. Frequency 1000 1000 V = ±5V V = ±15V SY SY 100 100 A = +100 V A = +100 V 10 10 A = +10 V A = +10 V 1 1 A = +1 V A = +1 V 0.1 0.1 100 1k 10k 100k 1M 10M 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure 25. Output Impedance vs. Frequency Figure 28. Output Impedance vs. Frequency Rev. B | Page 9 of 20 GAIN (dB) GAIN (dB) Z (Ω) OUT 07670-021 07670-020 PHASE (Degrees) 07670-019 GAIN (dB) GAIN (dB) Z (Ω) OUT 07670-018 07670-017 PHASE (Degrees) 07670-016 ADA4062-2/ADA4062-4 100 100 V = ±5V V = ±15V SY SY 90 90 80 80 70 70 60 60 50 50 40 40 30 30 20 20 10 10 0 0 100 1k 10k 100k 1M 10M 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure 29. CMRR vs. Frequency Figure 32. CMRR vs. Frequency 120 140 V = ±5V SY V = ±15V SY 120 100 100 80 80 60 PSRR+ 60 PSRR+ 40 40 PSRR– 20 PSRR– 20 0 0 –20 –20 10 100 1k 10k 100k 1M 10M 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure 30. PSRR vs. Frequency Figure 33. PSRR vs. Frequency 60 60 V = ±5V V = ±15V SY SY A = +1 A = +1 V V R = 10kΩ R = 10kΩ L L 50 50 40 40 30 30 20 20 10 10 0 0 10 100 1000 10000 10 100 1000 10000 C (pF) C (pF) L L Figure 31. Small-Signal Overshoot vs. Load Capacitance Figure 34. Small-Signal Overshoot vs. Load Capacitance Rev. B | Page 10 of 20 OVERSHOOT (%) CMRR (dB) PSRR (dB) 07670-026 07670-025 07670-030 OVERSHOOT (%) CMRR (dB) PSRR (dB) 07670-023 07670-027 07670-022 ADA4062-2/ADA4062-4 V = ±5V V = ±15V SY SY V = 4V p-p V = 20V p-p IN IN A = +1 A = +1 V V R = 10kΩ R = 10kΩ L L C = 100pF C = 100pF L L TIME (4µs/DIV) TIME (10µs/DIV) Figure 35. Large-Signal Transient Response Figure 38. Large-Signal Transient Response V = ±5V V = ±15V SY SY V = 100mV p-p V = 100mV p-p IN IN A = +1 A = +1 V V R = 10kΩ R = 10kΩ L L C = 100pF C = 100pF L L TIME (10µs/DIV) TIME (10µs/DIV) Figure 36. Small-Signal Transient Response Figure 39. Small-Signal Transient Response 4 4 V = ±15V SY V = ±5V SY A =–10 V A =–10 2 2 V INPUT INPUT 0 0 OUTPUT 0 OUTPUT 0 –5 –2 –10 –4 –15 –6 –20 TIME (2µs/DIV) TIME (2µs/DIV) Figure 37. Negative Overload Recovery Figure 40. Negative Overload Recovery Rev. B | Page 11 of 20 INPUT VOLTAGE (V) VOLTAGE (20mV/DIV) VOLTAGE (1V/DIV) 07670-032 07670-031 OUTPUT VOLTAGE (V) 07670-036 INPUT VOLTAGE (V) VOLTAGE (20mV/DIV) VOLTAGE (5V/DIV) 07670-029 07670-028 OUTPUT VOLTAGE (V) 07670-033 ADA4062-2/ADA4062-4 2 2 V = ±5V V = ±15V SY SY A =–10 A =–10 V INPUT INPUT V 0 0 –2 –2 15 4 10 2 5 OUTPUT OUTPUT 0 0 –2 –5 TIME (2µs/DIV) TIME (2µs/DIV) Figure 41. Positive Overload Recovery Figure 44. Positive Overload Recovery INPUT INPUT +20mV +100mV OUTPUT OUTPUT 0V 0V –20mV –100mV ERROR BAND ERROR BAND V = ±5V V = ±15V SY SY C = 100pF C = 100pF L L R = 10kΩ R = 10kΩ L L TIME (2µs/DIV) TIME (2µs/DIV) Figure 42. Positive Settling Time to 0.1% Figure 45. Positive Settling Time to 0.1% V = ±5V V = ±15V SY SY C = 100pF C = 100pF INPUT L L INPUT R = 10kΩ R = 10kΩ L L +20mV +100mV OUTPUT OUTPUT 0V 0V –20mV –100mV ERROR BAND ERROR BAND TIME (2µs/DIV) TIME (2µs/DIV) Figure 43. Negative Settling Time to 0.1% Figure 46. Negative Settling Time to 0.1% Rev. B | Page 12 of 20 INPUT VOLTAGE (V) VOLTAGE (1V/DIV) VOLTAGE (1V/DIV) 07670-076 07670-075 OUTPUT VOLTAGE (V) 07670-037 INPUT VOLTAGE (V) VOLTAGE (5V/DIV) VOLTAGE (5V/DIV) 07670-078 07670-077 OUTPUT VOLTAGE (V) 07670-034 ADA4062-2/ADA4062-4 1000 1000 V = ±5V V = ±15V SY SY 100 100 10 10 110 100 1k 110 100 1k FREQUENCY (Hz) FREQUENCY (Hz) Figure 47. Voltage Noise Density Figure 50. Voltage Noise Density V = ±5V V = ±15V SY SY TIME (1s/DIV) TIME (1s/DIV) Figure 48. 0.1 Hz to 10 Hz Noise Figure 51. 0.1 Hz to 10 Hz Noise 0 0 V = ±5V SY V = ±15V 100kΩ 100kΩ SY V = 5V p-p IN V = 10V p-p IN 1kΩ –20 –20 1kΩ R = 10kΩ L R = 10kΩ L ADA4062-2 ONLY ADA4062-2 ONLY –40 –40 R R L L –60 –60 –80 –80 –100 –100 –120 –120 –140 –140 –160 –160 100 1k 10k 100k 100 1k 10k 100k FREQUENCY (Hz) FREQUENCY (Hz) Figure 49. Channel Separation vs. Frequency (ADA4062-2 Only) Figure 52. Channel Separation vs. Frequency (ADA4062-2 Only) Rev. B | Page 13 of 20 CHANNEL SEPARATION (dB) VOLTAGE NOISE DENSITY (nV/√Hz) INPUT NOISE VOLTAGE (0.5µV/DIV) 07670-044 07670-049 07670-043 CHANNEL SEPARATION (dB) VOLTAGE NOISE DENSITY (nV/√Hz) INPUT NOISE VOLTAGE (0.5µV/DIV) 07670-041 07670-046 07670-040 ADA4062-2/ADA4062-4 0 0 V = ±5V V = ±15V SY 100kΩ 100kΩ SY V = 5V p-p V = 10V p-p IN IN 1kΩ –20 1kΩ –20 R = 10kΩ R = 10kΩ L L ADA4062-4 ONLY ADA4062-4 ONLY –40 –40 R R L L –60 –60 –80 –80 –100 –100 –120 –120 –140 –140 –160 –160 100 1k 10k 100k 100 1k 10k 100k FREQUENCY (Hz) FREQUENCY (Hz) Figure 53. Channel Separation vs. Frequency (ADA4062-4 Only) Figure 56. Channel Separation vs. Frequency (ADA4062-4 Only) 100 10 V = ±5V S f = 1kHz R = 10kΩ L 10 1 1 0.1 0.1 0.01 0.01 V = ±15V S f = 1kHz R = 10kΩ L 0.001 0.001 0.001 0.01 0.1 1 10 0.001 0.01 0.1 1 10 AMPLITUDE (V rms) AMPLITUDE (V rms) Figure 57 THD + N vs. Amplitude Figure 54. THD + N vs. Amplitude 1 1 V = ±5V V = ±15V SY S V = 0.5V rms V = 2V rms IN IN R = 10kΩ L R = 10kΩ L 0.1 0.1 0.01 0.01 0.001 0.001 10 100 1k 10k 100k 100 1k 10k 100k 1M FREQUENCY (Hz) FREQUENCY (Hz) Figure 55. THD + N vs. Frequency Figure 58. THD + N vs. Frequency Rev. B | Page 14 of 20 THD + N (%) CHANNEL SEPARATION (dB) THD + N (%) 07670-071 07670-073 07670-067 CHANNEL SEPARATION (dB) THD + N (%) THD + N (%) 07670-072 07670-074 07670-066 ADA4062-2/ADA4062-4 APPLICATIONS INFORMATION HIGH-SIDE SIGNAL CONDITIONING NOTCH FILTER Many applications require the sensing of signals near the positive A notch filter rejects a specific interfering frequency and can be rail. The ADA4062-x can be used in high-side current sensing implemented using a single op amp. Figure 59 shows a 60 Hz applications. Figure 61 shows a high-side signal conditioning notch filter that uses the twin-T network with the ADA4062-x circuit using the ADA4062-x. The ADA4062-x has an input configured as a voltage follower. The ADA4062-x works as a buffer common-mode range that includes the positive supply (−11.5 V ≤ that provides high input resistance and low output impedance. VCM ≤ +15 V). In the circuit, the voltage drop across a low value The low bias current (2 pA typical) and high input resistance resistor, such as the 0.1 Ω shown in Figure 61, is amplified by a (10 TΩ typical) of the ADA4062-x enable large resistors and small factor of 5 using the ADA4062-x. capacitors to be used. 0.1Ω Alternatively, different combinations of resistor and capacitor +15V 500kΩ R L values can be used to achieve the desired notch frequency. 100kΩ +15V However, the major drawback to this circuit topology is the 100kΩ V O need to ensure that all the resistors and capacitors be closely ADA4062-x matched. If they are not closely matched, the notch frequency 500kΩ –15V offset and drift cause the circuit to attenuate at a frequency Figure 61. High-Side Signal Conditioning other than the ideal notch frequency. Therefore, to achieve the desired performance, 1% or better MICROPOWER INSTRUMENTATION AMPLIFIER component tolerances are usually required. In addition, a notch The ADA4062-2 is a dual amplifier and is perfectly suited for filter requires an op amp with a bandwidth of at least 100× to applications that require lower supply currents. For supply 200× the center frequency. Hence, using the ADA4062-x with voltages of ±15 V, the supply current per amplifier is 165 μA a bandwidth of 1.4 MHz is excellent for a 60 Hz notch filter. typical. The ADA4062-2 also offers a typical low offset voltage Figure 60 shows the frequency response of the notch filter. At drift of 5 μV/°C and a very low bias current of 2 pA, which 60 Hz, the notch filter has about 50 dB attenuation of signal. make it well suited for instrumentation amplifiers. +V SY Figure 62 shows the classic 2-op-amp instrumentation amplifier with four resistors using the ADA4062-2. The key to high CMRR R1 R2 V 804kΩ 804kΩ O for this instrumentation amplifier are resistors that are well IN ADA4062-x C3 matched to both the resistive ratio and relative drift. For true 6.6nF –V difference amplification, matching of the resistor ratio is very R3 SY 402kΩ important, where R3/R4 = R1/R2. Assuming perfectly matched resistors, the gain of the circuit is 1 + R2/R1, which is approximately C1 C2 3.3nF 3.3nF 100. Tighter matching of two op amps in one package, as is the 1 f = O case with the ADA4062-2, offers a significant boost in performance 2π R C 1 1 R1 = R2 = 2R3 over the classical 3-op-amp configuration. Overall, the circuit only C3 requires about 330 μA of supply current. C1 = C2 = 2 R3 Figure 59. Notch Filter Circuit 10.1kΩ R2 1MΩ 20 +15V R4 +15V 1MΩ R1 10 10.1kΩ 1/2 0 1/2 V O ADA4062-2 –10 ADA4062-2 –15V V1 –20 –15V V2 –30 V = 100(V2 – V1) O TYPICAL: 0.5mV < │V2 – V1│< 135mV –40 TYPICAL: –13.8V < V < +13.5V O USE MATCHED RESISTORS –50 Figure 62. Micropower Instrumentation Amplifier –60 –70 –80 10 100 1k FREQUENCY (Hz) Figure 60. Frequency Response of the Notch Filter Rev. B | Page 15 of 20 GAIN (dB) 07670-060 07670-057 07670-058 07670-059 ADA4062-2/ADA4062-4 PHASE REVERSAL V IN V = ±15V SY Phase reversal occurs in some amplifiers when the input common- mode voltage range is exceeded. When the voltage driving the V OUT input to these amplifiers exceeds the maximum input common- mode voltage range, the output of the amplifiers changes polarity. Most JFET input amplifiers have phase reversal if either input exceeds the input common-mode range. For the ADA4062-x, the output does not phase reverse if one or both of the inputs exceeds the input voltage range but remains within the positive supply rail and 0.5 V above the negative supply rail. In other words, for an application with a supply voltage of ±15 V, the input voltage can be as high as +15 V TIME (40µs/DIV) without any output phase reversal. However, when the voltage Figure 64. No Phase Reversal of the inputs is driven beyond −14.5 V, phase reversal occurs due to saturation of the input stage leading to forward biasing of the gate-drain diode. Phase reversal in ADA4062-x can be prevented by using a Schottky diode to clamp the input terminals to each other. In the simple buffer circuit in Figure 63, D1 protects the op amp against phase reversal, and R limits the input current that flows into the op amp. +V SY R D1 V 10kΩ O IN5711 ADA4062-x –V SY Figure 63. Phase Reversal Solution Circuit Rev. B | Page 16 of 20 07670-053 VOLTAGE (5V/DIV) 07670-063 ADA4062-2/ADA4062-4 SCHEMATIC V+ OUT –IN +IN V– Figure 65. Simplified Schematic of the ADA4062-x Rev. B | Page 17 of 20 07670-062 ADA4062-2/ADA4062-4 OUTLINE DIMENSIONS 3.20 3.00 2.80 8 5 5.15 3.20 4.90 3.00 4.65 1 2.80 4 PIN 1 IDENTIFIER 0.65 BSC 0.95 15° MAX 0.85 1.10 MAX 0.75 0.80 0.15 0.23 6° 0.55 0.40 0.05 0.09 0° 0.40 0.25 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 66. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters 5.00 (0.1968) 4.80 (0.1890) 85 6.20 (0.2441) 4.00 (0.1574) 1 5.80 (0.2284) 3.80 (0.1497) 4 0.50 (0.0196) 1.27 (0.0500) 45° BSC 1.75 (0.0688) 0.25 (0.0099) 1.35 (0.0532) 0.25 (0.0098) 8° 0.10 (0.0040) 0° 0.51 (0.0201) COPLANARITY 1.27 (0.0500) 0.10 0.31 (0.0122) 0.25 (0.0098) SEATING 0.40 (0.0157) PLANE 0.17 (0.0067) COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 67. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 0.55 0.20 DIA 1.30 0.40 TYP 0.30 9 1 1.60 0.35 0.30 0.40 0.25 BSC 6 4 TOP VIEW BOTTOM VIEW 0.60 0.55 0.50 0.05 MAX 0.02 NOM 0.20 BSC SEATING PLANE Figure 68. 10-Lead Lead Frame Chip Scale Package [LFCSP_UQ] 1.30 mm × 1.60 mm, Body, Ultra Thin Quad (CP-10-10) Dimensions shown in millimeters Rev. B | Page 18 of 20 PIN 1 IDENTIFIER 100709-B 012407-A 033007-A ADA4062-2/ADA4062-4 5.10 5.00 4.90 14 8 4.50 6.40 4.40 BSC 4.30 1 7 PIN 1 0.65 BSC 1.05 1.20 1.00 0.20 MAX 0.80 0.09 0.75 0.15 8° 0.60 SEATING 0° 0.05 0.45 0.30 PLANE COPLANARITY 0.19 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AB-1 Figure 69. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown in millimeters 3.10 0.30 3.00 SQ 0.23 2.90 PIN 1 0.18 INDICATOR 13 16 0.50 12 1 BSC EXPOSED 1.75 PAD 1.60 SQ 1.45 9 4 8 5 0.50 0.20 MIN TOP VIEW BOTTOM VIEW 0.40 0.30 FORPROPERCONNECTIONOF 0.80 THE EXPOSED PAD, REFER TO 0.75 0.05 MAX THE PIN CONFIGURATION AND 0.70 FUNCTION DESCRIPTIONS 0.02 NOM SECTION OF THIS DATA SHEET. COPLANARITY SEATING 0.08 PLANE 0.20 REF COMPLIANT TO JEDEC STANDARDS MO-220-WEED-6. Figure 70. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 3 mm × 3 mm Body, Very Very Thin Quad (CP-16-22) Dimensions shown in millimeters Rev. B | Page 19 of 20 PIN 1 INDICATOR 061908-A 01-13-2010-D ADA4062-2/ADA4062-4 ORDERING GUIDE 1 Model Temperature Range Package Description Package Option Branding ADA4062-2ARMZ −40°C to +125°C 8-Lead MSOP RM-8 A25 ADA4062-2ARMZ-RL −40°C to +125°C 8-Lead MSOP RM-8 A25 ADA4062-2ARMZ-RL7 −40°C to +125°C 8-Lead MSOP RM-8 A25 ADA4062-2ARZ −40°C to +125°C 8-Lead SOIC_N R-8 ADA4062-2ARZ-R7 −40°C to +125°C 8-Lead SOIC_N R-8 ADA4062-2ARZ-RL −40°C to +125°C 8-Lead SOIC_N R-8 ADA4062-2BRZ −40°C to +125°C 8-Lead SOIC_N R-8 ADA4062-2BRZ-R7 −40°C to +125°C 8-Lead SOIC_N R-8 ADA4062-2BRZ-RL −40°C to +125°C 8-Lead SOIC_N R-8 ADA4062-2ACPZ-R2 −40°C to +125°C 10-Lead LFCSP_UQ CP-10-10 J ADA4062-2ACPZ-RL −40°C to +125°C 10-Lead LFCSP_UQ CP-10-10 J ADA4062-2ACPZ-R7 −40°C to +125°C 10-Lead LFCSP_UQ CP-10-10 J ADA4062-4ARUZ −40°C to +125°C 14-Lead TSSOP RU-14 ADA4062-4ARUZ-RL −40°C to +125°C 14-Lead TSSOP RU-14 ADA4062-4ACPZ-R2 −40°C to +125°C 16-Lead LFCSP_WQ CP-16-22 A2K ADA4062-4ACPZ-R7 −40°C to +125°C 16-Lead LFCSP_WQ CP-16-22 A2K ADA4062-4ACPZ-RL −40°C to +125°C 16-Lead LFCSP_WQ CP-16-22 A2K 1 Z = RoHS Compliant Part. ©2008–2010 Analog Devices, Inc. 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