ANALOG DEVICES AD9957

1 GSPS Quadrature Digital Upconverter with 18-Bit I/Q Data Path and 14-Bit DAC Data Sheet AD9957 FEATURES GENERAL DESCRIPTION 1 GSPS internal clock speed (up to 400 MHz analog output) The AD9957 functions as a universal I/Q modulator and agile Integrated 1 GSPS 14-bit DAC upconverter for communications systems where cost, size, power 250 MSPS input data rate consumption, and dynamic performance are critical. The AD9957 Phase noise ≤ −125 dBc/Hz (400 MHz carrier @ 1 kHz offset) integrates a high speed, direct digital synthesizer (DDS), a high Excellent dynamic performance >80 dB narrow-band SFDR performance, high speed, 14-bit digital-to-analog converter (DAC), 8 programmable profiles for shift keying clock multiplier circuitry, digital filters, and other DSP functions Sin(x)/(x) correction (inverse sinc filter) onto a single chip. It provides baseband upconversion for data Reference clock multiplier transmission in a wired or wireless communications system. Internal oscillator for a single crystal operation Software and hardware controlled power-down The AD9957 is the third offering in a family of quadrature Integrated RAM digital upconverters (QDUCs) that includes the AD9857 and Phase modulation capability AD9856. It offers performance gains in operating speed, power Multichip synchronization consumption, and spectral performance. Unlike its predecessors, Easy interface to Blackfin SPORT it supports a 16-bit serial input mode for I/Q baseband data. Interpolation factors from 4× to 252× The device can alternatively be programmed to operate either as Interpolation DAC mode a single tone, sinusoidal source or as an interpolating DAC. Gain control DAC The reference clock input circuitry includes a crystal oscillator, Internal divider allows references up to 2 GHz a high speed, divide-by-two input, and a low noise PLL for 1.8 V and 3.3 V power supplies multiplication of the reference clock frequency. 100-lead TQFP_EP package The user interface to the control functions includes a serial port APPLICATIONS easily configured to interface to the SPORT of the Blackfin® HFC data, telephony, and video modems DSP and profile pins to enable fast and easy shift keying of any Wireless base station transmissions signal parameter (phase, frequency, or amplitude). Broadband communications transmissions Internet telephony FUNCTIONAL BLOCK DIAGRAM I DATA FORMAT AND FOR 14-BIT DAC I/Q DATA INTERPOLATE XMIT Q NCO AD9957 TIMING AND REFERENCE CLOCK CONTROL INPUT CIRCUITRY USER INTERFACE REFERENCE CLOCK INPUT Figure 1. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2007–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 06384-001 AD9957 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 RAM Control .................................................................................. 27 Applications ....................................................................................... 1 RAM Overview ........................................................................... 27 General Description ......................................................................... 1 RAM Segment Registers ............................................................ 27 Functional Block Diagram .............................................................. 1 RAM State Machine ................................................................... 27 Revision History ............................................................................... 4 RAM Trigger (RT) Pin ............................................................... 27 Specifications ..................................................................................... 5 Load/Retrieve RAM Operation ................................................ 28 Electrical Specifications ............................................................... 5 RAM Playback Operation ......................................................... 28 Absolute Maximum Ratings ............................................................ 8 Overview of RAM Playback Modes ......................................... 29 ESD Caution .................................................................................. 8 RAM Ramp-Up Mode ........................................................... 29 Pin Configuration and Function Descriptions ............................. 9 RAM Bidirectional Ramp Mode .......................................... 30 Typical Performance Characteristics ........................................... 12 RAM Continuous Bidirectional Ramp Mode .................... 32 Modes of Operation ....................................................................... 16 RAM Continuous Recirculate Mode ................................... 33 Overview ...................................................................................... 16 Clock Input (REF_CLK) ................................................................ 34 Quadrature Modulation Mode ................................................. 17 REFCLK Overview ..................................................................... 34 BlackFin Interface (BFI) Mode ................................................. 18 Crystal Driven REF_CLK ......................................................... 34 Interpolating DAC Mode .......................................................... 19 Direct Driven REF_CLK ........................................................... 34 Single Tone Mode ....................................................................... 20 Phase-Locked Loop (PLL) Multiplier ...................................... 35 Signal Processing ............................................................................ 21 PLL Charge Pump ...................................................................... 36 Parallel Data Clock (PDCLK) ................................................... 21 External PLL Loop Filter Components ................................... 36 Transmit Enable Pin (TxEnable) .............................................. 21 PLL Lock Indication .................................................................. 36 Input Data Assembler ................................................................ 22 Additional Features ........................................................................ 37 Inverse CCI Filter ....................................................................... 23 Output Shift Keying (OSK) ....................................................... 37 Fixed Interpolator (4×) .............................................................. 23 Manual OSK ............................................................................ 37 Programmable Interpolating Filter .......................................... 24 Automatic OSK ....................................................................... 37 QDUC Mode ........................................................................... 24 Profiles ......................................................................................... 38 BFI Mode ................................................................................. 24 I/O_UPDATE Pin ...................................................................... 38 Quadrature Modulator .............................................................. 25 Automatic I/O Update ............................................................... 38 DDS Core ..................................................................................... 25 Power-Down Control ................................................................ 39 Inverse Sinc Filter ....................................................................... 25 General-Purpose I/O (GPIO) Port .......................................... 39 Output Scale Factor (OSF) ........................................................ 26 Synchronization of Multiple Devices ........................................... 40 14-Bit DAC .................................................................................. 26 Overview ..................................................................................... 40 Auxiliary DAC ........................................................................ 26 Clock Generator ......................................................................... 40 Rev. C | Page 2 of 64 Data Sheet AD9957 Sync Generator ............................................................................ 40 I/O_RESET—Input/Output Reset ........................................ 48 Sync Receiver ............................................................................... 41 I/O_UPDATE—Input/Output Update ................................ 48 Setup/Hold Validation ................................................................ 42 Serial I/O Timing Diagrams ...................................................... 48 Synchronization Example .......................................................... 44 MSB/LSB Transfers ..................................................................... 48 I/Q Path Latency ......................................................................... 45 I/O_UPDATE, SYNC_CLK, and System Clock Relationships ................................................................................ 49 Example ....................................................................................45 Register Map and Bit Descriptions ............................................... 50 Power Supply Partitioning ............................................................. 46 Register Map ................................................................................ 50 3.3 V Supplies .............................................................................. 46 Register Bit Descriptions............................................................ 55 DVDD_I/O (Pin 11, Pin 15, Pin 21, Pin 28, Pin 45, Pin 56, Pin 66) ......................................................................................46 Control Function Register 1 (CFR1) .................................... 55 AVDD (Pin 74 to Pin 77 and Pin 83) ................................... 46 Control Function Register 2 (CFR2) .................................... 56 1.8 V Supplies .............................................................................. 46 Control Function Register 3 (CFR3) .................................... 58 DVDD (Pin 17, Pin 23, Pin 30, Pin 47, Pin 57, Pin 64) ..... 46 Auxiliary DAC Control Register ........................................... 58 AVDD (Pin 3) .......................................................................... 46 I/O Update Rate Register ....................................................... 58 AVDD (Pin 6) .......................................................................... 46 RAM Segment Register 0 ....................................................... 58 AVDD (Pin 89 and Pin 92) .................................................... 46 RAM Segment Register 1 ....................................................... 59 Serial Programming ........................................................................ 47 Amplitude Scale Factor (ASF) Register ............................... 59 Control Interface—Serial I/O .................................................... 47 Multichip Sync Register ......................................................... 59 General Serial I/O Operation .................................................... 47 Profile Registers ........................................................................... 60 Instruction Byte ........................................................................... 47 Profile<7:0> Register—Single Tone ...................................... 60 Instruction Byte Information Bit Map ................................. 47 Profile<7:0> Register—QDUC ............................................. 60 Serial I/O Port Pin Descriptions ............................................... 47 RAM Register .......................................................................... 60 SCLK—Serial Clock................................................................ 47 GPIO Configuration Register ............................................... 60 CS GPIO Data Register ................................................................ 60 —Chip Select Bar ............................................................... 47 Outline Dimensions ........................................................................ 61 SDIO—Serial Data Input/Output ......................................... 47 Ordering Guide ........................................................................... 61 SDO—Serial Data Out ........................................................... 48 Rev. C | Page 3 of 64 AD9957 Data Sheet REVISION HISTORY 4/12—Rev. B to Rev. C 1/08—Rev. 0 to Rev. A Changes to Table 1 ............................................................................ 7 Changes to REFCLK Multiplier Specification ............................... 3 Changes to Table 3 .......................................................................... 11 Changes to I/O_Update/Profile<2:0>/RT Timing Change to Sync Generator Section ............................................... 41 Characteristics and I/Q Input Timing Characteristics ................. 5 Changes to Sync Receiver Section and Setup/Hold Validation Replaced Pin Configuration and Function Descriptions Section .............................................................................................. 42 Section .................................................................................................8 Changes to Figure 25 Through Figure 29.................................... 15 Changes to Table 13 ........................................................................ 50 Changes to Table 19 ........................................................................ 57 Deleted Table 4, Renumbered Sequentially ................................ 20 Changes to Table 26 ........................................................................ 59 Changes to DDS Core Section ...................................................... 24 Changes to Figure 47 and Table 6................................................. 33 10/10—Rev. A to Rev. B Replaced Synchronization of Multiple Devices Section ............ 39 Changes to Data Rate in Features Section ..................................... 1 Added I/Q Path Latency Section .................................................. 44 Changes to Specifications Section .................................................. 6 Added Power Supply Partitioning Section .................................. 45 Added EPAD Notation to Figure 4 and Table 3 ........................... 9 Changes to General Serial I/O Operation Section ..................... 46 Changes to Table 13 ....................................................................... 48 Changes to XTAL_SEL Pin Description ...................................... 11 Changes to BlackFin Interface (BFI) Mode Section .................. 18 Changes to Table 14 ....................................................................... 49 Changes to Figure 30 and Figure 31 ............................................. 22 Changes to Table 19 ....................................................................... 54 Changes to Programmable Interpolating Filter Section ............ 24 Changes to Table 20 ....................................................................... 56 Changes to Fifth Paragraph of Quadrature Modulator Section...... 25 Changes to GPIO Configuration Register and Changes to RAM Segment Registers Section ............................. 27 GPIO Data Register Sections ........................................................ 58 Changes to RAM Playback Operation Section ........................... 28 Changes to Control Interface—Serial I/O Section ..................... 47 5/07—Revision 0: Initial Version Added to I/O_UPDATE, SYNC_CLK, and System Clock Relationships Section and Figure 64 ............................................ 49 Changes to Default Values of Profile 0 Register—Single Tone (0x0E) and Profile 0 Register—QDUC (0x0E) in Table 14 ....... 51 Changes to Default Values in Table 15 ......................................... 52 Changes to Default Values in Table 16 ......................................... 53 Changes to Default Values in Table 17 ......................................... 54 Updated Outline Dimensions ....................................................... 61 Rev. C | Page 4 of 64 Data Sheet AD9957 SPECIFICATIONS ELECTRICAL SPECIFICATIONS AVDD (1.8V) and DVDD (1.8V) = 1.8 V ± 5%, AVDD (3.3V) = 3.3 V ± 5%, DVDD_I/O (3.3V) = 3.3 V ± 5%, T = 25°C, R = 10 kΩ, SET I = 20 mA, external reference clock frequency = 1000 MHz with REFCLK multiplier disabled, unless otherwise noted. OUT Table 1. Parameter Test Conditions/Comments Min Typ Max Unit REF_CLK INPUT CHARACTERISTICS Frequency Range 1 REFCLK Multiplier Disabled 60 1000 MHz Enabled 3.2 60 MHz Maximum REFCLK Input Divider Frequency Full temperature range 1500 1900 MHz Minimum REFCLK Input Divider Frequency Full temperature range 25 35 MHz External Crystal 25 MHz Input Capacitance 3 pF Input Impedance (Differential) 2.8 kΩ Input Impedance (Single-Ended) 1.4 kΩ Duty Cycle REFCLK multiplier disabled 45 55 % REFCLK multiplier enabled 40 60 % REF_CLK Input Level Single-ended 50 1000 mV p-p Differential 100 2000 mV p-p REFCLK MULTIPLIER VCO GAIN CHARACTERISTICS VCO Gain (K ) @ Center Frequency VCO0 range setting 429 MHz/V V VCO1 range setting 500 MHz/V VCO2 range setting 555 MHz/V VCO3 range setting 750 MHz/V VCO4 range setting 789 MHz/V 2 VCO5 range setting 850 MHz/V REFCLK_OUT CHARACTERISTICS Maximum Capacitive Load 20 pF Maximum Frequency 25 MHz DAC OUTPUT CHARACTERISTICS Full-Scale Output Current 8.6 20 31.6 mA Gain Error −10 +10 %FS Output Offset 2.3 µA Differential Nonlinearity 0.8 LSB Integral Nonlinearity 1.5 LSB Output Capacitance 5 pF Residual Phase Noise @ 1 kHz Offset, 20 MHz A OUT REFCLK Multiplier Disabled −152 dBc/Hz Enabled @ 20× −140 dBc/Hz Enabled @ 100× −140 dBc/Hz AC Voltage Compliance Range −0.5 +0.5 V SPURIOUS-FREE DYNAMIC RANGE (SFDR SINGLE TONE) fOUT = 20.1 MHz −70 dBc fOUT = 98.6 MHz −69 dBc fOUT = 201.1 MHz −61 dBc f = 397.8 MHz −54 dBc OUT Rev. C | Page 5 of 64 AD9957 Data Sheet Parameter Test Conditions/Comments Min Typ Max Unit NOISE SPECTRAL DENSITY (NSD) Single Tone fOUT = 20.1 MHz −167 dBm/Hz f = 98.6 MHz −162 dBm/Hz OUT f = 201.1 MHz −157 dBm/Hz OUT f = 397.8 MHz −151 dBm/Hz OUT TWO-TONE INTERMODULATION DISTORTION (IMD) I/Q rate = 62.5 MSPS; 16× interpolation f = 25 MHz −82 dBc OUT fOUT = 50 MHz −78 dBc fOUT = 100 MHz −73 dBc MODULATOR CHARACTERISTICS Input Data Error Vector Magnitude 2.5 Msymbols/s, QPSK, 4× oversampled 0.53 % 270.8333 ksymbols/s, GMSK, 32× 0.77 % oversampled 2.5 Msymbols/s, 256-QAM, 4× 0.35 % oversampled WCDMA—FDD (TM1), 3.84 MHz Bandwidth, 5 MHz Channel Spacing Adjacent Channel Leakage Ratio (ACLR) IF = 143.88 MHz −78 dBc Carrier Feedthrough −78 dBc SERIAL PORT TIMING CHARACTERISTICS Maximum SCLK Frequency 70 Mbps Minimum SCLK Pulse Width Low 4 ns High 4 ns Maximum SCLK Rise/Fall Time 2 ns Minimum Data Setup Time to SCLK 5 ns Minimum Data Hold Time to SCLK 0 ns Maximum Data Valid Time in Read Mode 11 ns I/O_UPDATE/PROFILE<2:0>/RT TIMING CHARACTERISTICS Minimum Pulse Width High 1 SYNC_CLK cycle Minimum Setup Time to SYNC_CLK 1.75 ns Minimum Hold Time to SYNC_CLK 0 ns I/Q INPUT TIMING CHARACTERISTICS Maximum PDCLK Frequency 250 MHz Minimum I/Q Data Setup Time to PDCLK 1.75 ns Minimum I/Q Data Hold Time to PDCLK 0 ns Minimum TxEnable Setup Time to PDCLK 1.75 ns Minimum TxEnable Hold Time to PDCLK 0 ns MISCELLANEOUS TIMING CHARACTERISTICS 3 Wake-Up Time 1 4 Fast Recovery Mode 8 SYSCLK cycles Full Sleep Mode 150 μs 4 Minimum Reset Pulse Width High 5 SYSCLK cycles DATA LATENCY (PIPELINE DELAY) Data Latency Single Tone Mode 4 Frequency, Phase-to-DAC Output 79 SYSCLK cycles Rev. C | Page 6 of 64 Data Sheet AD9957 Parameter Test Conditions/Comments Min Typ Max Unit CMOS LOGIC INPUTS Voltage Logic 1 2.0 V Logic 0 0.8 V Current Logic 1 90 150 µA Logic 0 90 150 µA Input Capacitance 2 pF XTAL_SEL INPUT Logic 1 Voltage 1.25 V Logic 0 Voltage 0.6 V Input Capacitance 2 pF CMOS LOGIC OUTPUTS 1 mA load Voltage Logic 1 2.8 V Logic 0 0.4 V POWER SUPPLY CURRENT DVDD_I/O (3.3V) Pin Current Consumption QDUC mode 16 mA DVDD (1.8V) Pin Current Consumption QDUC mode 610 mA AVDD (3.3V) Pin Current Consumption QDUC mode 28 mA AVDD (1.8V) Pin Current Consumption QDUC mode 105 mA POWER CONSUMPTION Single Tone Mode 800 mW Continuous Modulation 8× interpolation 1400 1800 mW Inverse Sinc Filter Power Consumption 150 200 mW Full Sleep Mode 12 40 mW 1 The system clock is limited to 750 MHz maximum in BFI mode. 2 The gain value for VCO range Setting 5 is measured at 1000 MHz. 3 Wake-up time refers to the recovery from analog power-down modes. The longest time required is for the Reference Clock Multiplier PLL to relock to the reference. 4 SYSCLK cycle refers to the actual clock frequency used on-chip by the DDS. If the reference clock multiplier is used to multiply the external reference clock frequency, the SYSCLK frequency is the external frequency multiplied by the reference clock multiplication factor. If the reference clock multiplier and divider are not used, the SYSCLK frequency is the same as the external reference clock frequency. Rev. C | Page 7 of 64 AD9957 Data Sheet ABSOLUTE MAXIMUM RATINGS DIGITAL INPUTS Table 2. DVDD_I/O Parameter Rating AVDD (1.8V), DVDD (1.8V) Supplies 2 V AVDD (3.3V), DVDD_I/O (3.3V) Supplies 4 V INPUT Digital Input Voltage −0.7 V to +4 V XTAL_SEL −0.7 V to +2.2 V Digital Output Current 5 mA Storage Temperature Range −65°C to +150°C AVOID OVERDRIVING DIGITAL INPUTS. Operating Temperature Range −40°C to +85°C FORWARD BIASING ESD DIODES MAY COUPLE DIGITAL NOISE ONTO POWER θ 22°C/W PINS. JA θ 2.8°C/W JC Figure 2. Equivalent Input Circuit Maximum Junction Temperature 150°C DAC OUTPUTS Lead Temperature, Soldering (10 sec) 300°C AVDD Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute IOUT IOUT maximum rating conditions for extended periods may affect device reliability. MUST TERMINATE OUTPUTS TO AGND FOR CURRENT FLOW. DO NOT EXCEED THE OUTPUT VOLTAGE COMPLIANCE RATING. Figure 3. Equivalent Output Circuit ESD CAUTION Rev. C | Page 8 of 64 06384-055 06384-003 Data Sheet AD9957 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS NC 1 75 AVDD (3.3V) PIN 1 74 PLL_LOOP_FILTER 2 INDICATOR AVDD (3.3V) AVDD (1.8V) 3 73 AGND 72 AGND 4 NC AGND 71 5 I/O_RESET AVDD (1.8V) 6 70 CS 69 SYNC_IN+ 7 SCLK SYNC_IN– 8 68 SDO SYNC_OUT+ 9 67 SDIO SYNC_OUT– 66 10 DVDD_I/O (3.3V) DVDD_I/O (3.3V) 11 65 DGND AD9957 64 SYNC_SMP_ERR 12 DVDD (1.8V) TQFP-100 (E_PAD) DGND 13 63 DGND TOP VIEW MASTER_RESET (Not to Scale) 14 62 DGND DVDD_I/O (3.3V) 61 15 NC DGND 16 60 OSK DVDD (1.8V) 59 17 I/O_UPDATE EXT_PWR_DWN 18 58 DGND PLL_LOCK 57 19 DVDD (1.8V) CCI_OVFL 20 56 DVDD_I/O (3.3V) 55 SYNC_CLK DVDD_I/O (3.3V) 21 DGND 22 54 PROFILE0 DVDD (1.8V) 23 53 PROFILE1 NC 52 PROFILE2 24 D17 25 51 RT NOTES 1. NC = NO CONNECT. 2. EXPOSED PAD SHOULD BE SOLDERED TO GROUND. Figure 4. Pin Configuration Rev. C | Page 9 of 64 D16 26 100 NC D15 27 99 NC DVDD_I/O (3.3V) 28 98 NC DGND 29 97 NC DVDD (1.8V) 30 96 AGND D14 31 95 XTAL_SEL D13 32 94 REFCLK_OUT D12 33 93 NC D11 34 92 AVDD (1.8V) D10 35 91 REF_CLK D9 REF_CLK 36 90 D8 37 89 AVDD (1.8V) D7 AGND 38 88 D6 39 87 NC PDCLK 40 86 NC TxENABLE/FS 41 85 AGND D5/SPORT I-DATA 42 84 DAC_RSET D4/SPORT Q-DATA 83 AVDD (3.3V) 43 D3 44 82 AGND DVDD_I/O (3.3V) 45 81 IOUT 46 DGND 80 IOUT DVDD (1.8V) 47 79 AGND D2 48 78 AGND D1 49 AVDD (3.3V) 77 D0 50 76 AVDD (3.3V) 06384-004 AD9957 Data Sheet Table 3. Pin Function Descriptions 1 Pin No. Mnemonic I/O Description 1, 24, 61, 72, 86, NC Not Connected. Allow device pin to float. 87, 93, 97 to 100 2 PLL_LOOP_FILTER I PLL-Loop Filter Compensation. See External PLL Loop Filter Components section. 3, 6, 89, 92 AVDD (1.8V) I Analog Core VDD. 1.8 V analog supplies. 74 to 77, 83 AVDD (3.3V) I Analog DAC VDD. 3.3 V analog supplies. 17, 23, 30, 47, 57, DVDD (1.8V) I Digital Core VDD. 1.8 V digital supplies. 64 11, 15, 21, 28, 45, DVDD_I/O (3.3V) I Digital Input/Output VDD. 3.3 V digital supplies. 56, 66 4, 5, 73, 78, 79, AGND I Analog Ground. 82, 85, 88, 96 13, 16, 22, 29, 46, DGND I Digital Ground. 58, 62, 63, 65 7 SYNC_IN+ I Synchronization Signal, Digital Input (Rising Edge Active). Synchronization signal from external master to synchronize internal subclocks. See the Synchronization of Multiple Devices section. 8 SYNC_IN− I Synchronization Signal, Digital Input (Falling Edge Active). Synchronization signal from external master to synchronize internal subclocks. See the Synchronization of Multiple Devices section. 9 SYNC_OUT+ O Synchronization Signal, Digital Output (Rising Edge Active). Synchronization signal from internal device subclocks to synchronize external slave devices. See the Synchronization of Multiple Devices section. 10 SYNC_OUT− O Synchronization Signal, Digital Output (Falling Edge Active). Synchronization signal from internal device subclocks to synchronize external slave devices. See the Synchronization of Multiple Devices section. 12 SYNC_SMP_ERR O Synchronization Sample Error, Digital Output (Active High). A high on this pin indicates that the AD9957 did not receive a valid sync signal on SYNC_IN+/SYNC_IN−. See the Synchronization of Multiple Devices section. 14 MASTER_RESET I Master Reset, Digital Input (Active High). This pin clears all memory elements and sets registers to default values. 18 EXT_PWR_DWN I External Power-Down, Digital Input (Active High). A high level on this pin initiates the currently programmed power-down mode. See the Power-Down Control section for further details. If unused, tie to ground. 19 PLL_LOCK O PLL Lock, Digital Output (Active High). A high on this pin indicates that the clock multiplier PLL has acquired lock to the reference clock input. 20 CCI_OVFL O CCI Overflow Digital Output, Active High. A high on this pin indicates a CCI filter overflow. This pin remains high until the CCI overflow condition is cleared. 25 to 27, 31 to D<17:0> I/O Parallel Data Input Bus (Active High). These pins provide the interleaved, 18-bit, digital, I 39, 42 to 44, 48 and Q vectors for the modulator to upconvert. Also used for a GPIO port in Blackfin to 50 interface mode. 42 SPORT I-DATA I In Blackfin interface mode, this pin serves as the I-data serial input. 43 SPORT Q-DATA I In Blackfin interface mode, this pin serves as the Q-data serial input. 40 PDCLK O Parallel Data Clock, Digital Output (Clock). See the Signal Processing section for details. 41 TxENABLE/FS I Transmit Enable, Digital Input (Active High). See the Signal Processing section for details. In Blackfin interface mode, this pin serves as the FS input to receive the RFS output signal from the Blackfin. 51 RT I RAM Trigger, Digital Input (Active High). This pin provides control for the RAM amplitude scaling function. When this function is engaged, a high sweeps the amplitude from the beginning RAM address to the end. A low sweeps the amplitude from the end RAM address to the beginning. If unused, connect to ground or supply. 52 to 54 PROFILE<2:0> I Profile Select Pins, Digital Inputs (Active High). These pins select one of eight phase/frequency profiles for the DDS core (single tone or carrier tone). Changing the state of one of these pins transfers the current contents of all I/O buffers to the corresponding registers. State changes should be set up to the SYNC_CLK pin. 55 SYNC_CLK O Output System Clock/4, Digital Output (Clock). The I/O_UPDATE and PROFILE<2:0> pins should be set up to the rising edge of this signal. Rev. C | Page 10 of 64 Data Sheet AD9957 1 Pin No. Mnemonic I/O Description 59 I/O_UPDATE I/O Input/Output Update; Digital Input Or Output (Active High) Depending on the Internal I/O Update Active Bit. A high on this pin indicates a transfer of the contents of the I/O buffers to the corresponding internal registers. 60 OSK I Output Shift Keying, Digital Input (Active High). When using OSK (manual or automatic), this pin controls the OSK function. See the Output Shift Keying (OSK) section of the data sheet for details. When not using OSK, tie this pin high. 67 SDIO I/O Serial Data Input/Output, Digital Input/Output (Active High). This pin can be either unidirectional or bidirectional (default), depending on configuration settings. In bidirectional serial port mode, this pin acts as the serial data input and output. In unidirectional, it is an input only. 68 SDO O Serial Data Output, Digital Output (Active High). This pin is only active in unidirectional serial data mode. In this mode, it functions as the output. In bidirectional mode, this pin is not operational and should be left floating. 69 SCLK I Serial Data Clock. Digital clock (rising edge on write, falling edge on read). This pin provides the serial data clock for the control data path. Write operations to the AD9957 use the rising edge. Readback operations from the AD9957 use the falling edge. 70 I CS Chip Select, Digital Input (Active Low). Bringing this pin low enables the AD9957 to detect serial clock rising/falling edges. Bringing this pin high causes the AD9957 to ignore input on the serial data pins. 71 I/O_RESET I Input/Output Reset, Digital Input (Active High). Rather than resetting the entire device during a failed communication cycle, when brought high, this pin resets the state machine of the serial port controller and clears any I/O buffers that have been written since the last I/O update. When unused, tie this pin to ground to avoid accidental resets. 80 IOUT O Open-Source DAC Complementary Output Source. Analog output, current mode. Connect through 50 Ω to AGND. 81 IOUT O Open-Source DAC Output Source. Analog output, current mode. Connect through 50 Ω to AGND. 84 DAC_RSET O Analog Reference Pin. This pin programs the DAC output full-scale reference current. Attach a 10 kΩ resistor to AGND. 90 REF_CLK I Reference Clock Input. Analog input. See the REFCLK Overview section for more details. 91 REF_CLK I Complementary Reference Clock Input. Analog input. See the REFCLK Overview section for more details. 94 REFCLK_OUT O Reference Clock Output. Analog output. See the REFCLK Overview section for more details. 95 XTAL_SEL I Crystal Select (1.8 V Logic). Analog input (active high). Driving the XTAL_SEL pin high enables the internal oscillator to be used with a crystal resonator. If unused, connect it to AGND. (EPAD) Exposed Pad The EPAD should be soldered to ground. (EPAD) 1 I = input, O = output. Rev. C | Page 11 of 64 AD9957 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 1 1 0 0 –10 –10 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 1 –70 –70 1 –80 –80 –90 –90 –100 –100 CENTER 102MHz 5kHz/DIV SPAN 50kHz START 0Hz 50MHz/DIV STOP 500MHz Figure 5. 15.625 kHz Quadrature Tone, Carrier = 102 MHz, Figure 8. Narrow-Band View of Figure 5 CCI = 16, f = 1 GHz (with Carrier and Lower Sideband Suppression) S 1 1 0 0 –10 –10 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 1 –70 –70 1 –80 –80 –90 –90 –100 –100 CENTER 222MHz 5kHz/DIV SPAN 50kHz START 0MHz 50MHz/DIV STOP 500MHz Figure 9. Narrow-Band View of Figure 6 Figure 6. 15.625 kHz Quadrature Tone, Carrier = 222 MHz, (with Carrier And Lower Sideband Suppression) CCI = 16, fS = 1 GHz 1 1 0 0 –10 –10 –20 –20 –30 –30 –40 –40 –50 –50 1 –60 –60 –70 –70 1 –80 –80 –90 –90 –100 –100 START 0Hz 50MHz/DIV STOP 500MHz CENTER 372MHz 5kHz/DIV SPAN 50kHz Figure 7. 15.625 kHz Quadrature Tone, Carrier = 372 MHz, Figure 10. Narrow-Band View of Figure 7 CCI = 16, f = 1 GHz (with Carrier and Lower Sideband Suppression) S Rev. C | Page 12 of 64 06384-052 06384-050 06384-048 06384-049 06384-053 06384-051 Data Sheet AD9957 0 0 –10 –10 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 –100 START 0Hz 50MHz/DIV STOP 500MHz CENTER 102MHz 2MHz/DIV SPAN 20MHz Figure 11. QPSK, 7.8125 Msymbols/s, 4x Oversampled Raised Cosine, Figure 14. Narrow-Band View of Figure 11 α = 0.25, CCI = 8, Carrier = 102 MHz, f = 1 GHz S 0 0 –10 –10 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 –100 CENTER 222MHz 2MHz/DIV SPAN 20MHz START 0MHz 50MHz/DIV STOP 500MHz Figure 12. QPSK, 7.8125 Msymbols/s, 4x Oversampled Raised Cosine, Figure 15. Narrow-Band View of Figure 12 α = 0.25, CCI = 8, Carrier = 222 MHz, f = 1 GHz S 0 0 –10 –10 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 –100 START 0Hz 50MHz/DIV STOP 500MHz CENTER 372MHz 2MHz/DIV SPAN 20MHz Figure 13. QPSK, 7.8125 Msymbols/s, 4x Oversampled Raised Cosine, Figure 16. Narrow-Band View of Figure 13 α = 0.25, CCI = 8, Carrier = 372 MHz, f = 1 GHz S Rev. C | Page 13 of 64 06384-046 06384-045 06384-044 06384-041 06384-043 06384-042 AD9957 Data Sheet –50 –90 f = 397.8MHz OUT –100 –55 –110 SFDR WITHOUT PLL f = 201.1MHz OUT –120 f = 98.6MHz OUT –60 –130 SFDR WITH PLL –65 –140 –150 –70 –160 f = 20.1MHz OUT –75 –170 0 50 100 150 200 250 300 350 400 10 100 1k 10k 100k 1M 10M 100M FREQUENCY OUT (MHz) FREQUENCY OFFSET (Hz) Figure 17. Wideband SFDR vs. Output Frequency in Single Tone Mode, Figure 20. Residual Phase Noise, System Clock = 1 GHz PLL with REFCLK = 15.625 MHz × 64 –90 –45 f = 397.8MHz OUT LOW SUPPLY –100 –50 HIGH SUPPLY f = 201.1MHz –110 OUT –55 –120 –60 –130 –65 –140 f = 20.1MHz OUT –70 –150 f = 98.6MHz OUT –160 –75 0 50 100 150 200 250 300 350 400 450 10 100 1k 10k 100k 1M 10M 100M FREQUENCY OFFSET (Hz) FREQUENCY OUT (MHz) Figure 21. Residual Phase Noise Using the REFCLK Multiplier, Figure 18. SFDR vs. Output Frequency and Supply (±5%) in Single Tone REFCLK = 50 MHz with 20x Multiplication, System Clock = 1 GHz Mode, REFCLK = 1 GHz 1200 –50 DVDD 1.8V –40°C 1000 +85°C –55 800 –60 600 –65 400 AVDD 1.8V AVDD 3.3V DVDD 3.3V –70 200 0 –75 100 200 300 400 500 600 700 800 900 1000 0 50 100 150 200 250 300 350 400 450 SYSTEM CLOCK FREQUENCY (MHz) FREQUENCY OUT (MHz) Figure 22. Power Dissipation vs. System Clock (PLL Disabled) Figure 19. SFDR vs. Frequency and Temperature in Single Tone Mode, REFCLK = 1 GHz Rev. C | Page 14 of 64 SFDR (dBc) SFDR (dBc) SFDR (dBc) 06384-060 06384-059 06384-058 POWER DISSIPATION (mW) MAGNITUDE (dBc/ Hz) MAGNITUDE (dBc/Hz) 06384-062 06384-054 06384-061 Data Sheet AD9957 1200 –20 –30 1000 DVDD 1.8V –40 800 –50 –60 600 –70 –80 400 –90 AVDD 1.8V AVDD 3.3V DVDD 3.3V 200 –100 –110 0 CENTER 143.86MHz 2.55MHz/DIV SPAN 25.5MHz 400 500 600 700 800 900 1000 SYSTEM CLOCK FREQUENCY (MHz) Tx CHANNEL W-CDMA SGFF FWD BANDWIDTH: 3.84MHz POWER: –11.88dBm Figure 23. Power Dissipation vs. System Clock (PLL Enabled) ADJACENT CHANNEL BANDWIDTH: 3.84MHz LOWER: –78.27dB SPACING: 3MHz UPPER: –78.50dB ADJACENT CHANNEL BANDWIDTH: 3.84MHz LOWER: –81.42dB SPACING: 10MHz UPPER: –81.87dB Figure 24. Typical ACLR for Wideband CDMA Rev. C | Page 15 of 64 POWER DISSIPATION (mW) 06384-063 06384-064 AD9957 Data Sheet MODES OF OPERATION than that of the DAC. An internal chain of rate interpolation OVERVIEW filters the user data and upsamples to the DAC sample rate. The AD9957 has three basic operating modes. Combined, the filters provide for programmable rate interpola- tion while suppressing spectral images and retaining the original • Quadrature modulation (QDUC) mode (default) baseband spectrum. • Interpolating DAC mode • Single tone mode QDUC mode employs both the DDS and the rate interpolation filters. In this case, two parallel banks of rate interpolation The active mode is selected via the operating mode bits in filters allow baseband processing of in-phase and quadrature Control Function Register 1 (CFR1). Single tone mode allows (I/Q) signals with the DDS providing the carrier signal to be the device to operate as a sinusoidal generator with the DDS modulated by the baseband signals. A detailed block diagram of driving the DAC directly. the AD9957 is shown in Figure 25. Interpolating DAC mode bypasses the DDS, allowing the user The inverse sinc filter is available in all three modes. to deliver baseband data to the device at a sample rate lower AD9957 18 I 16 8 AUX DAC GAIN DAC DDS IS DAC_RSET 8-BIT 18 I/Q IN θ QS cos (ωt+θ) IOUT DAC ω 16 14-BIT IOUT sin (ωt+θ) 18 CLOCK OUTPUT Q SCALE FACTOR REFCLK_OUT OSK ÷2 SYSCLK PDCLK REF_CLK PARALLEL DATA INTERNAL CLOCK TIMING AND CONTROL PLL TIMING AND CONTROL REF_CLK TxENABLE XTAL_SEL FTW POWER SERIAL I/O PROGRAMMING RAM DOWN PORT PW REGISTERS CONTROL 2 2 3 I Q IS QS Figure 25. Detailed Block Diagram Rev. C | Page 16 of 64 DATA ASSEMBLER AND FORMATTER BLACKFIN INTERFACE PROFILE I/O_UPDATE SDIO SDO INVERSE INVERSE SCLK CCI CCI I/O_RESET CS HALF-BAND HALF-BAND FILTERS (4×) FILTERS (4×) CCI CCI RT (1× TO 63×) (1× TO 63×) FTW PW CCI_OVFL OSK EXT_PWR_DWN SYNC_OUT SYNC_IN INVERSE SINC FILTER PLL_LOCK PLL_LOOP_FILTER MASTER_RESET CLOCK MODE 06384-005 Data Sheet AD9957 The PROFILE and I/O_UPDATE pins are also synchronous to QUADRATURE MODULATION MODE the PDCLK. A block diagram of the AD9957 operating in QDUC mode is shown in Figure 26; grayed items are inactive. The parallel input The DDS core provides a quadrature (sine and cosine) local accepts 18-bit I- and Q-words in time-interleaved fashion. That oscillator signal to the quadrature modulator, where the is, an 18-bit I-word is followed by an 18-bit Q-word, then the interpolated I and Q samples are multiplied by the respective next 18-bit I-word, and so on. One 18-bit I-word and one 18-bit phase of the carrier and summed together, producing a Q-word together comprise one internal sample. The data assem- quadrature modulated data stream. This data stream is routed bler and formatter de-interleave the I- and Q-words so that each through the inverse sinc filter (optionally), and the output sample propagates along the internal data pathway in parallel scaling multiplier. Then it is applied to the 14-bit DAC to fashion. Both I and Q data paths are active; the parallel data produce the quadrature modulated analog output signal. clock (PDCLK) serves to synchronize the input of I/Q data to the AD9957. AD9957 18 I 16 8 AUX DAC GAIN DAC IS DDS DAC_RSET 8-BIT 18 I/Q IN θ QS cos (ωt+θ) IOUT DAC ω 16 14-BIT IOUT sin (ωt+θ) 18 CLOCK OUTPUT Q SCALE FACTOR REFCLK_OUT OSK ÷2 SYSCLK PDCLK REF_CLK PARALLEL DATA INTERNAL CLOCK TIMING AND CONTROL PLL TIMING AND CONTROL REF_CLK TxENABLE XTAL_SEL FTW POWER PROGRAMMING SERIAL I/O RAM DOWN REGISTERS PORT PW CONTROL 2 2 3 I Q IS QS Figure 26. Quadrature Modulation Mode Rev. C | Page 17 of 64 DATA ASSEMBLER AND FORMATTER BLACKFIN INTERFACE PROFILE I/O_UPDATE SDIO SDO INVERSE INVERSE SCLK CCI CCI I/O_RESET CS HALF-BAND HALF-BAND FILTERS (4×) FILTERS (4×) CCI CCI RT (1× TO 63×) (1× TO 63×) FTW PW CCI_OVFL OSK EXT_PWR_DWN SYNC_OUT SYNC_IN INVERSE SINC FILTER PLL_LOCK PLL_LOOP_FILTER MASTER_RESET CLOCK MODE 06384-006 AD9957 Data Sheet The Blackfin interface includes an additional pair of half-band BLACKFIN INTERFACE (BFI) MODE filters in both I and Q signal paths (not shown explicitly in the A subset of the QDUC mode is the Blackfin interface (BFI) diagram). The two half-band filters increase the interpolation mode, shown in Figure 27; grayed items are inactive. In this of the baseband data by a factor of four, relative to the normal mode, a separate I and Q serial bit stream is applied to the QDUC mode. baseband data port instead of parallel data-words. The two serial inputs provide for 16-bit I- and Q-words (unlike the The synchronization of the serial data occurs through the 18-bit words in normal QDUC mode). The serial bit streams PDCLK signal. In BFI mode, the PDCLK signal is effectively are delivered to the Blackfin interface. The Blackfin interface the bit clock for the serial data. converts the 16-bit serial data into 16-bit parallel data to Note that the system clock is limited to 750 MHz in BFI mode. propagate down the signal processing chain. AD9957 I 18 16 8 AUX DAC GAIN DAC IS DDS 8-BIT DAC_RSET 2 I/Q IN θ QS cos (ωt+θ) IOUT DAC ω 16 14-BIT IOUT sin (ωt+θ) 18 CLOCK Q OUTPUT SCALE FACTOR REFCLK_OUT OSK ÷2 SYSCLK PDCLK REF_CLK PARALLEL DATA INTERNAL CLOCK TIMING AND CONTROL PLL TIMING AND CONTROL REF_CLK TxENABLE XTAL_SEL POWER FTW SERIAL I/O PROGRAMMING RAM DOWN PORT PW REGISTERS CONTROL 2 2 3 I Q IS QS Figure 27. Quadrature Modulation Mode, Blackfin Interface Rev. C | Page 18 of 64 DATA ASSEMBLER AND FORMATTER BLACKFIN INTERFACE PROFILE I/O_UPDATE SDIO SDO INVERSE INVERSE SCLK CCI CCI I/O_RESET CS HALF-BAND HALF-BAND FILTERS (4×) FILTERS (4×) CCI CCI RT (1× TO 63×) (1× TO 63×) FTW PW CCI_OVFL O OSK SK EXT_PWR_DWN SYNC_OUT SYNC_IN INVERSE SINC FILTER PLL_LOCK PLL_LOOP_FILTER MASTER_RESET CLOCK MODE 06384-007 Data Sheet AD9957 INTERPOLATING DAC MODE No modulation takes place in the interpolating DAC mode; therefore, the spectrum of the data supplied at the parallel port A block diagram of the AD9957 operating in interpolating DAC remains at baseband. However, a sample rate conversion takes mode is shown in Figure 28; grayed items are inactive. In this place based on the programmed interpolation rate. The inter- mode, the Q data path, DDS, and modulator are all disabled; only polation hardware processes the signal, effectively performing the I data path is active. an oversample with a zero-stuffing operation. The original As in quadrature modulation mode, the PDCLK pin functions input spectrum remains intact and the images that otherwise as a clock, synchronizing the input of data to the AD9957. would occur from the sample rate conversion process are suppressed by the interpolation signal chain. AD9957 18 I 16 8 AUX DAC GAIN DAC DDS IS DAC_RSET 8-BIT 18 I/Q IN θ QS cos (ωt+θ) IOUT DAC ω 16 14-BIT IOUT sin (ωt+θ) 18 CLOCK Q OUTPUT SCALE FACTOR REFCLK_OUT OSK ÷2 SYSCLK PDCLK REF_CLK PARALLEL DATA INTERNAL CLOCK TIMING AND CONTROL PLL TIMING AND CONTROL REF_CLK TxENABLE XTAL_SEL FTW POWER SERIAL I/O PROGRAMMING RAM DOWN PORT PW REGISTERS CONTROL 2 2 3 I Q IS QS Figure 28. Interpolating DAC Mode Rev. C | Page 19 of 64 DATA ASSEMBLER AND FORMATTER BLACKFIN INTERFACE PROFILE I/O_UPDATE SDIO SDO SCLK INVERSE INVERSE CCI CCI I/O_RESET CS HALF-BAND HALF-BAND FILTERS (4×) FILTERS (4×) CCI CCI RT (1× TO 63×) (1× TO 63×) FTW PW CCI_OVFL OSK EXT_PWR_DWN SYNC_OUT SYNC_IN INVERSE SINC FILTER PLL_LOCK PLL_LOOP_FILTER MASTER_RESET CLOCK MODE 06384-008 AD9957 Data Sheet SINGLE TONE MODE cosine or sine output of the DDS. The sinusoid at the DDS output can be scaled using a 14-bit amplitude scale factor (ASF) A block diagram of the AD9957 operating in single tone mode and optionally routed through the inverse sinc filter. is shown in Figure 29; grayed items are inactive. In this mode, both I and Q data paths are disabled from the 18-bit parallel Single tone mode offers the output shift keying (OSK) function. data port up to, and including, the modulator. The internal It provides the ability to ramp the amplitude scale factor between DDS core produces a single frequency signal based on the zero and an arbitrary preset value over a programmable time programmed tuning word. The user may select either the interval. AD9957 18 I 16 8 AUX DAC GAIN DAC IS DDS 8-BIT DAC_RSET 10 I/Q IN θ QS cos (ωt+θ) IOUT DAC ω 16 14-BIT IOUT sin (ωt+θ) 18 CLOCK OUTPUT Q SCALE FACTOR REFCLK_OUT OSK ÷2 SYSCLK PDCLK REF_CLK PARALLEL DATA INTERNAL CLOCK TIMING AND CONTROL PLL TIMING AND CONTROL REF_CLK TxENABLE XTAL_SEL POWER FTW SERIAL I/O PROGRAMMING RAM DOWN PORT REGISTERS PW CONTROL 2 2 3 I Q IS QS Figure 29. Single Tone Mode Rev. C | Page 20 of 64 DATA ASSEMBLER AND FORMATTER BLACKFIN INTERFACE PROFILE I/O_UPDATE SDIO SDO SCLK INVERSE INVERSE CCI CCI I/O_RESET CS HALF-BAND HALF-BAND FILTERS (4×) FILTERS (4×) CCI CCI RT (1× TO 63×) (1× TO 63×) FTW PW CCI_OVFL OSK EXT_PWR_DWN SYNC_OUT SYNC_IN INVERSE SINC FILTER PLL_LOCK PLL_LOOP_FILTER MASTER_RESET CLOCK MODE 06384-009 Data Sheet AD9957 SIGNAL PROCESSING For a better understanding of the operation of the AD9957, it TRANSMIT ENABLE PIN (TxENABLE) is helpful to follow the signal path in quadrature modulation The AD9957 accepts a user-generated signal applied to the mode from the parallel data port to the output of the DAC, TxENABLE pin that gates the user supplied data. Polarity of examining the function of each block (see Figure 26). the TxENABLE pin is set using the TxENABLE invert bit (see the Register Map section for details). When TxENABLE is true, The internal system clock (SYSCLK) signal that generates from the device latches data into the device on the expected edge of the timing source provided to the REF_CLK pins provides all PDCLK (based on the PDCLK invert bit). When TxENABLE timing within the AD9957. is false, the device ignores the data supplied to the port, even though the PDCLK may continue to operate. Furthermore, PARALLEL DATA CLOCK (PDCLK) when the TxENABLE pin is held false, then the device either The AD9957 generates a signal on the PDCLK pin, which is a forces the 18-bit data-words to Logic 0s, or it retains the last clock signal that runs at the sample rate of the parallel data port. value present on the data port prior to TxENABLE switching PDCLK serves as a data clock for the parallel port in QDUC to the false state (see the data assembler hold last value bit in and interpolating DAC modes; in BFI mode, it is a bit clock. the Register Map section). Normally, the device uses the rising edges on PDCLK to latch the user-supplied data into the data port. Alternatively, the Alternatively, rather than operating the TxENABLE pin as a PDCLK Invert bit selects the falling edges as the active edges. gate for framing bursts of data, it can be driven with a clock Furthermore, the PDCLK enable bit is used to switch off the signal operating at the parallel port data rate. When driven by PDCLK signal. Even when the output signal is turned off via the a clock signal, the transition from the false to true state must PDCLK enable bit, PDCLK continues to operate internally. The meet the required setup and hold times on each cycle to ensure device uses PDCLK internally to capture parallel data. Note that proper operation. PDCLK is Logic 0 when disabled. In QDUC mode, on the false-to-true edge of TxENABLE, the In QDUC mode, the AD9957 expects alternating I- and Q- device is ready to receive the first I-word. The first I-word is data-words at the parallel port (see Figure 31). Each active edge latched into the device coincident with the active edge of PDCLK. of PDCLK captures one 18-bit word; therefore, there are two The next active edge of PDCLK latches in a Q-word, and so on, PDCLK cycles per I/Q pair. In BFI mode, the AD9957 expects until TxENABLE is returned to a static false state. The user may two serial bit streams, each segmented into 16-bit words with reverse the ordering of the I- and Q-words via the Q-First Data PDCLK indicating each new bit. In either case, the output clock Pairing bit. Furthermore, the user must ensure that an even rate is f as explained in the Input Data Assembler section. PDCLK number of data words are delivered to the device as it must capture both an I- and a Q-word before the data is processed In QDUC applications that require a consistent timing relation- along the signal chain. ship between the internal SYSCLK signal and the PDCLK signal, the PDCLK rate control bit is used to slightly alter the operation In interpolating DAC mode, TxENABLE operation is similar to of PDCLK. When this bit is set, the PDCLK rate is reduced by QDUC mode, but without the need for I/Q data pairing; the a factor of two. This causes rising edges on PDCLK to latch even-number-of-PDCLK-cycles rule does not apply. incoming I-words and falling edges to latch incoming Q-words. Again, the edge polarity assignment is reversible via the PDCLK In BFI mode, operation of the TxENABLE pin is similar except Invert bit. that instead of the false-to-true edge marking the first I-word, it marks the first I and Q bits in a serial frame. The user must ensure that all 16-bits of a serial frame are delivered because the device must capture a full 16-bit I- and Q-word before the data is processed along the signal chain. The timing relationships between TxENABLE, PDCLK, and DATA are shown in Figure 30, Figure 31, and Figure 32. Rev. C | Page 21 of 64 AD9957 Data Sheet TxENABLE t DS t DH PDCLK t DS I I I I D<17:0> I I 0 1 2 3 K – 1 K t DH Figure 30. 18-Bit Parallel Port Timing Diagram—Interpolating DAC Mode TxENABLE t DS t DH PDCLK t DS I Q I Q I Q D<17:0> 0 0 1 1 N N t DH Figure 31. 18-Bit Parallel Port Timing Diagram—Quadrature Modulation Mode TxENABLE PDCLK I DATA I I I I I I I I I I I I I I I I 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 I 16n – 1 Q DATA Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Q 16n – 1 Figure 32. Dual Serial I/Q Bit Stream Timing Diagram, BFI Mode INPUT DATA ASSEMBLER When the PDCLK rate control bit is active in QDUC mode, however, the frequency of PDCLK becomes The input to the AD9957 is an 18-bit parallel data port in QDUC mode or interpolating DAC mode. In BFI mode, it f SYSCLK with PDCLK rate control active f = PDCLK operates as a dual serial data port. 4R In QDUC mode, it is assumed that two consecutive 18-bit In the interpolating DAC mode, the rate of PDCLK is the same words represent the real (I) and imaginary (Q) parts of a as QDUC mode with the PDCLK rate control bit active, that is, complex number of the form, I + jQ. The 18-bit words are f SYSCLK supplied to the input of the AD9957 at a rate of f = for interpolating DAC mode PDCLK 4R f SYSCLK f = for QDUC mode In BFI mode, the 18-bit parallel input converts to a dual serial PDCLK 2R input that is, one pin is assigned as the serial input for the I-words where: and one pin is assigned as the serial input for the Q-words. The fSYSCLK (for all of the PDCLK equations in this section) is the other 16 pins are not used. Furthermore, each I- and Q-word sample rate of the DAC. has a 16-bit resolution. fPDCLK is the bit rate of the I- and Q-data R (for all of the PDCLK equations in this section) is the streams and is given by interpolation factor of the programmable interpolation filter. f SYSCLK f = for BFI mode PDCLK R Rev. C | Page 22 of 64 06384-012 06384-011 06384-010 Data Sheet AD9957 Encoding and pulse shaping of symbols must be implemented FIXED INTERPOLATOR (4×) before the data is presented to the input of the AD9957. Data This block is a fixed 4× rate interpolator, implemented as a delivered to the input of the AD9957 may be formatted as either cascade of two half-band filters. Together, the sampling rate twos complement or offset binary (see the Data Format bit in of these two filters increases by a factor of four while preserving Table 13). In BFI mode, the bit sequence order can be set to the spectrum of the baseband signal applied at the input. Both either MSB-first or LSB-first (via the Blackfin Bit Order bit). are linear phase filters; virtually no phase distortion is intro- duced within their pass bands. Their combined insertion loss INVERSE CCI FILTER is 0.01 dB, preserving the relative amplitude of the input signal. The inverse cascaded comb integrator (CCI) filter predistorts the data, compensating for the slight attenuation gradient imposed The filters are designed to deliver a composite performance that by the CCI filter (see the Programmable Interpolating Filter yields a usable pass band of 40% of the input sample rate. Within section). Data entering the first half-band filter occupies a maxi- that pass band, ripple does not exceed 0.002 dB peak-to-peak. mum bandwidth of ½ f as defined by Nyquist (where f is the IQ IQ The stop band extends from 60% to 340% of the input sample sample rate at the input of the first half-band filter); see Figure 33. rate and offers a minimum of 85 dB attenuation. Figure 34 and Figure 35 show the composite response of the two half-band filters. If the CCI filter is used, the inband attenuation gradient can pose a 10 problem for applications requiring an extremely flat pass band. 0 For example, if the spectrum of the data supplied to the AD9957 –10 occupies a significant portion of the ½ fDATA region, the higher –20 frequencies of the data spectrum are slightly more attenuated –30 than the lower frequencies (the worst-case overall droop from –40 f = 0 to ½ f is <0.8 dB). The inverse CCI filter has a response DATA –50 –60 characteristic that is the inverse of the CCI filter response over –70 the ½ f region. IQ –80 –90 INBAND ATTENUATION –100 GRADIENT –110 –120 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 f I CCI FILTER RESPONSE Figure 34. Half-Band 1 and Half-Band 2 Composite Response (Frequency Scaled to Input Sample Rate of Half-Band 1) 0.010 0.008 0.006 f 0.004 f 4f IQ IQ ½f 0.002 IQ 0 Figure 33. CCI Filter Response –0.002 The product of the two responses yields an extremely flat –0.004 pass band (±0.05 dB over the baseband Nyquist bandwidth) –0.006 eliminating the inband attenuation gradient introduced by the –0.008 CCI filter. The cost is a slight attenuation of the input signal (approximately 0.5 dB for a CCI interpolation rate of 2, and –0.010 0 0.1 0.2 0.3 0.4 0.5 0.8 dB for higher interpolation rates). f I The inverse CCI filter can be bypassed using the appropriate bit Figure 35. Composite Pass-Band Detail (Frequency Scaled to Input Sample Rate of Half-Band 1) in the register map; it is automatically bypassed if the CCI inter- polation rate is 1×. When bypassed, power to the stage turns off In BFI mode, there are two additional half-band filters resident, to reduce power consumption. yielding a total fixed interpolation factor of 16×. The extra BFI filters use the same filter tap coefficient values as the QDUC half-band filters, but their data pathway is 16 bits (instead of 18 bits as with the QDUC half-band filters). As such, baseband quantization noise is higher in BFI mode. Rev. C | Page 23 of 64 06384-013 (dB) (dB) 06384-015 06384-014 AD9957 Data Sheet Knowledge of the frequency response of the half-band filters is response portion of the diagram to the right, as it must remain essential to understanding their impact on the spectral properties aligned with the corresponding Mf point on the frequency SYMBOL of the input signal. This is especially true when using the quad- axis of the raised cosine spectral diagram. However, if f shifts IQ rature modulator to upconvert a baseband signal containing to the right, so does the half-band response, proportionally. complex data symbols that have been pulse shaped. The result is that the raised cosine spectral mask always lies within the flat portion (dc to 0.4 fIQ) of the pass band response Consider that a complex symbol is represented by a real (I) and of the first half-band filter, regardless of the choice of α so long an imaginary (Q) component, thus requiring two digital words as M > 2. Therefore, for M > 2, the first half-band filter has to represent a single complex sample of the form I + jQ. The absolutely no negative impact on the spectrum of the baseband sample rate associated with a sequence of complex symbols is signal when raised cosine pulse shaping is employed. For the referred to as f . If pulse shaping is applied to the symbols, SYMBOL case of M = 2, a problem can arise. This is highlighted by the the sample rate must be increased by some integer factor, M shaded area in the tail of the α = 1 trace on the raised cosine (a consequence of the pulse shaping process). This new sample spectral mask diagram. Notice that this portion of the raised rate (fIQ) is related to the symbol rate by cosine spectral mask extends beyond the flat portion of the fIQ = MfSYMBOL half-band response and causes unwanted amplitude and phase where f is the rate at which complex samples must be supplied distortion as the signal passes through the first half-band filter. IQ to the input of the first half-band filter in both (I and Q) signal To avoid this, simply ensure that α ≤ 0.6 when M = 2. paths. This rate should not be confused with the rate at which PROGRAMMABLE INTERPOLATING FILTER data is supplied to the AD9957. The programmable interpolator is implemented as a low-pass Typically, pulse shaping is applied to the baseband symbols via CCI filter. It is programmable by a 6-bit control word, giving a a filter having a raised cosine response. In such cases, an excess range of 2× to 63× interpolation. bandwidth factor (α, 0 ≤ α ≤ 1) is used to modify the bandwidth The programmable interpolator is bypassed when programmed of the data. For α = 0, the data bandwidth corresponds to fSYMBOL/2; for an interpolation factor of 1. When bypassed, power to the for α = 1, the data bandwidth extends to f . Figure 36 shows SYMBOL the relationship between α, the bandwidth of the raised cosine stage is removed and the inverse CCI filter is also bypassed, response, and the response of the first half-band filter. because its compensation is not needed. The output of the programmable interpolator is the data from TYPICAL SPECTRUM OF A RANDOM SYMBOL SEQUENCE the 4× interpolator further upsampled by the CCI filter, accord- ing to the rate chosen by the user. This results in the upsampling of NYQUIST BAND the input data by a factor of 8× to 252× in steps of four. WIDTH The transfer function of the CCI interpolating filter is f 5 ½f f 2f 3f SYMBOL SYMBOL SYMBOL SYMBOL R− 1   ( ) −j 2π fk   H( f)= (1) ∑ e   k= 0   RAISED COSINE SPECTRAL MASK where R is the programmed interpolation factor, and f is the frequency normalized to fSYSCLK. SAMPLE RATE FOR α = 1 α = 0.5 2× OVERSAMPLED α = 0 PULSE SHAPING Note that minimum R requirements exist depending on the mode and frequency of fSYSCLK. The minimum R setting is f ½f f 2f 4f SYMBOL SYMBOL SYMBOL SYMBOL defined under the follo wing conditions. QDUC Mode HALF-BAND FILTER RESPONSE If fSYSCLK is between 500 MSPS to 1 GSPS, then the minimum R is 2. INPUT SAMPLE INPUT SAMPLE RATE OF FIRST RATE OF FIRST If fSYSCLK is less than 500 MSPS, then the minimum R is 1. HALF-BAND HALF-BAND FILTER FILTER BFI Mode f 0.4f ½f f 2f If f is between 500 MSPS to 750 MSPS, then the minimum IQ IQ IQ IQ SYSCLK R is 3. Figure 36. Effect of the Excess Bandwidth Factor (α) The responses in Figure 36 reflect the specific case of M = 2 (the If fSYSCLK is between 250 MSPS to 500 MSPS, then the minimum interpolation factor for the pulse shaping operation). Increasing R is 2. Factor M shifts the location of the f point on the half-band IQ If fSYSCLK is less than 250 MSPS, then the minimum R is 1. Rev. C | Page 24 of 64 06384-016 Data Sheet AD9957 where the round() function means to round the result to the QUADRATURE MODULATOR nearest integer. For example, for f = 41 MHz and f = OUT SYSCLK The digital quadrature modulator stage shifts the frequency of 122.88 MHz, then FTW = 1,433,053,867 (0x556AAAAB). the baseband spectrum of the incoming data stream up to the desired carrier frequency (a process known as upconversion). In single tone mode, the DDS frequency, phase, and amplitude are all programmable via the serial I/O port. The amplitude At this point, the baseband data, which was delivered to the is controlled by means of a digital multiplier using a 14-bit device at an I/Q sample rate of f , has been upsampled to a rate IQ fractional scale value called the amplitude scale factor (ASF). equal to the frequency of SYSCLK, making the data sampling −14 The LSB weight is 2 , yielding a multiplier range of 0 to rate equal to the sampling rate of the carrier signal. −14 0.99993896484375 (1 − 2 ). To bypass the ASF multiplier, program the appropriate control register bit (see the details of The frequency of the carrier signal is controlled by a direct CFR2<24> in the Register Bit Descriptions section). When digital synthesizer (DDS). The DDS very precisely generates the desired carrier frequency from the internal reference clock bypassed, the ASF multiplier clocks are disabled to conserve (SYSCLK). The carrier is applied to the I and Q multipliers in power. The phase offset is controlled by means of a digital adder quadrature fashion (90° phase offset) and summed, yielding a that uses a 14-bit offset value called the phase offset word (POW). data stream that represents the quadrature modulated carrier. The adder is situated between the phase accumulator and the angle-to-amplitude conversion logic in the DDS core. The adder The modulation is performed digitally, avoiding the phase applies the POW to the instantaneous phase values produced by offset, gain imbalance, and crosstalk issues commonly associated the DDS phase accumulator. The adder is MSB aligned with the with analog modulators. Note that the modulated, so-called −14 phase accumulator yielding an LSB weight of 2 (which equates to signal is a number stream sampled at the rate of SYSCLK, the a resolution of ~0.022° or ~0.000383 radians). Both the ASF and same rate at which the DAC is clocked. the POW are available for each of the eight profiles. The orientation of the modulated signal with respect to the INVERSE SINC FILTER carrier is controlled by a spectral invert bit. This bit resides in The sampled carrier data stream is the input to the digital-to- each of the eight profile registers. By default, the time domain analog converter. The DAC output spectrum is shaped by the output of the quadrature modulator takes the form characteristic sin(x)/x (or sinc) envelope, due to the intrinsic I(t) × cos(ωt) − Q(t) × sin(ωt) (2) zero-order hold effect associated with DAC-generated signals. The shape of the sinc envelope is well known and can be When the spectral invert bit is asserted, it becomes compensated for. This compensation is provided by the inverse I(t) × cos(ωt) + Q(t) × sin(ωt) (3) sinc filter preceding the DAC. DDS CORE The inverse sinc filter is implemented as a digital FIR filter. Its The direct digital synthesizer (DDS) block generates sine response characteristic very nearly matches the inverse of the and/or cosine signals. In single tone mode, the DDS generates sinc envelope, as shown in Figure 37 (along with the sinc either a digital sine or cosine waveform based on the select DDS envelope for comparison). sine output bit. In QDUC mode, the DDS generates the quadra- The inverse sinc filter is enabled through a bit in the register ture carrier reference signal that digitally modulates the I/Q map. The filter tap coefficients are listed in Table 4. The filter baseband signal. predistorts the data prior to its arrival at the DAC to compensate The DDS output frequency is tuned using registers accessed via for the sinc envelope that otherwise distorts the spectrum. the serial I/O port. This allows for both precise tuning and When the inverse sinc filter is enabled, it introduces a ~3.0 dB instantaneous changing of the carrier frequency. insertion loss. The inverse sinc compensation is effective for The equation relating output frequency (fOUT) of the DDS to the output frequencies up to 40% (nominally) of the DAC sample rate. frequency tuning word (FTW) and the system clock (fSYSCLK) is Table 4. Inverse Sinc Filter Tap Coefficients FTW   Tap No. Tap Value Tap No. f = f (4)   OUT SYSCLK 32  2  1 −35 7 2 +134 6 31 where FTW is a decimal number from 0 to 2,147,483,647 (2 − 1). 3 −562 5 4 +6729 4 Solving for FTW yields    f  32 OUT     FTW= round 2 (5)     f  SYSCLK   Rev. C | Page 25 of 64 AD9957 Data Sheet 14-BIT DAC In Figure 37, it can be seen that the sinc envelope introduces a The AD9957 incorporates an integrated 14-bit current-output frequency dependent attenuation that can be as much as 4 dB at DAC. The output current is delivered as a balanced signal using the Nyquist frequency (half of the DAC sample rate). Without two outputs. The use of balanced outputs reduces the amount of the inverse sinc filter, the DAC output also suffers from the common-mode noise at the DAC output, increasing signal-to- frequency dependent droop of the sinc envelope. The inverse noise ratio. An external resistor (R ) connected between the SET sinc filter effectively flattens the droop to within ±0.05 dB as DAC_RSET pin and AGND establishes a reference current. The shown in Figure 38, which shows the corrected sinc response full-scale output current of the DAC (IOUT) is a scaled version of with the inverse sinc filter enabled. the reference current (see the Auxiliary DAC section that 1 follows). SINC Proper attention should be paid to the load termination to keep 0 the output voltage within the specified compliance range, as voltages developed beyond this range cause excessive distortion –1 and can damage the DAC output circuitry. Auxiliary DAC –2 The full-scale output current of the main DAC (IOUT) is con- INVERSE SINC trolled by an 8-bit auxiliary DAC. An 8-bit code word stored in –3 the appropriate register map location sets I according to the OUT following equation: –4 0 0.1 0.2 0.3 0.4 0.5 86.4 CODE   FREQUENCY RELATIVE TO DAC SAMPLE RATE I = 1+ (6)   OUT R 96   SET Figure 37. Sinc and Inverse Sinc Responses –2.8 where: RSET is the value of the RSET resistor (in ohms). CODE is the 8-bit value supplied to the auxiliary DAC (default is 127). –2.9 For example, with RSET = 10,000 and CODE = 127, IOUT = 20.07 mA. COMPENSATED RESPONSE –3.0 –3.1 0 0.1 0.2 0.3 0.4 0.5 FREQUENCY RELATIVE TO DAC SAMPLE RATE Figure 38. DAC Response with Inverse Sinc Compensation OUTPUT SCALE FACTOR (OSF) In QDUC and interpolating DAC modes, the output amplitude is controlled using an 8-bit digital multiplier. The 8-bit multiplier value is called the output scale factor (OSF) and is programmed via the appropriate control registers. It is available for each of −7 the eight profiles. The LSB weight is 2 , which yields a multiplier −7 range of 0 to 1.9921875 (2 − 2 ). The gain extends to nearly a factor of 2 to provide a means to overcome the intrinsic loss through the modulator when operating in the quadrature modulation mode. In interpolating DAC mode, the OSF should not be programmed to exceed unity, as clipping can result. Programming the 8-bit multiplier to unity gain (0x80) bypasses the stage and reduces power consumption. Rev. C | Page 26 of 64 (dB) (dB) 06384-018 06384-017 Data Sheet AD9957 RAM CONTROL Q-channel bits. In playback mode, when driving data directly RAM OVERVIEW into the baseband signal chain, the 16-bit data-words are The AD9957 has an integrated 1024 × 32-bit RAM. This RAM considered to be signed (that is, twos complement) values. The is only accessible when the AD9957 is operating in QDUC or 16-bit I-and Q-words are MSB aligned with the 18-bit I and Q interpolating DAC mode. The RAM has two fundamental baseband data path. The two remaining LSBs of each 18-bit modes of operation: data entry/retrieve mode and playback baseband channel are driven by the MSB of the respective mode. The mode is selected by programming the RAM Enable channel. This ensures correct polarity coding when the 16-bit I bit in CFR1 via the serial I/O port. and Q data from the RAM translates into 18-bit words for the baseband signal chain. Alternatively, when the RAM is driving Data entry/retrieve mode is used to load or read back the RAM the baseband scaling multipliers in playback mode, the RAM contents via the serial I/O port. Playback mode is used to deliver data is considered to represent unsigned, fractional values with a RAM data to one of two internal destinations: the baseband −16 range of 0 to 1 − 2 . scaling multipliers (see Figure 25, the IS and QS labels) or the baseband signal chain (see Figure 25, the I and Q labels). In RAM SEGMENT REGISTERS both cases, the RAM can be used to apply an arbitrary, time- Two dedicated registers (RAM Segment Register 0 and RAM varying waveform to the selected destination. A block diagram Segment Register 1) control the operation of the RAM. Each of the RAM and its control elements is shown in Figure 39. contains the following: The external parallel data port is disabled when the baseband • 10-bit start address word signal chain serves as the RAM playback destination. • 10-bit end address word RT • 16-bit address step rate word 3 RAM MODE 16 ADDRESS STEP RATE RAM • 3-bit RAM playback mode word SEGMENT 10 START ADDRESS REGISTERS 10 END ADDRESS When programming these registers, the user must ensure that DDS CLOCK BASEBAND DATA CLOCK the end address is greater than the start address. With the RAM segment registers, the user can arbitrarily partition CLK SDIO U/D 32 32 10 SDO STATE the RAM into two independent memory segments. The segment Q RAM MACHINE SCLK boundaries are specified with the start and end address words I/O_RESET CS UP/DOWN COUNTER in each RAM segment register. The playback rate is controlled I 16 I CHANNEL IS by the address step rate word (only meaningful when the base- (MSBs) band scaling multipliers serve as the playback destination). If the Q Q CHANNEL 16 baseband signal chain serves as the RAM playback destination, QS (LSBs) the 16-bit address step rate words must be set to 1. The playback mode of the RAM is controlled via the RAM playback mode word. Figure 39. RAM Block Diagram RAM STATE MACHINE In Figure 39, the serial I/O port is used to program the contents The state machine acts as an address generator for the RAM. It of the two RAM segment registers as well as to load and retrieve is clocked by either the serial I/O port (when the RAM is operating the RAM contents. The state machine takes care of incrementing in the load/retrieve mode) or the baseband data clock (when or decrementing the RAM address locations and controlling the the RAM is in playback mode). The state machine uses the timing of the RAM address and data for proper operation. The RAM mode bits of the active RAM segment register to establish I-channel and Q-channel multiplexers route RAM data to base- the proper sequence through the specified address range. band scaling multipliers (IS/QS) or directly to the baseband RAM TRIGGER (RT) PIN signal chain (I/Q) when the RAM is used in playback mode. The state of the RAM playback destination bit determines the The RAM state machine monitors the RT pin for logic state tran- destination of the RAM data during playback. sitions. Any state transition triggers the state machine into action. An I/O update (or a profile change) is necessary to enact a state The direction of the logic state transition on the RT pin deter- change of the RAM enable or RAM playback destination bits, or mines which RAM segment register the state machine uses for any of the RAM segment register bits. playback instructions. RAM Segment Register 0 is used if the state machine detects a 0-to-1 transition; RAM Segment Register 1 The 32-bit RAM data bus is partitioned so that the 16 MSBs are is used if a 1-to-0 transition is detected. designated as I-channel bits and the 16 LSBs are designated as Rev. C | Page 27 of 64 ADDRESS DATA SERIAL I/O PORT 06384-019 AD9957 Data Sheet rate when the playback destination is the baseband scaling LOAD/RETRIEVE RAM OPERATION multipliers. Loading or retrieving the RAM contents is a three-step process. Although RAM load/retrieve operations via the serial I/O port 1. Program the RAM segment registers with start and end take precedence over playback, it is recommended that the user addresses defining the boundaries of each independent not attempt RAM access via the serial I/O port when the RAM RAM segment. enable bit is set. 2. Toggle the RT pin with the appropriate transition to select Figure 41 is a block diagram showing the functional compo- the desired RAM segment register. nents used for RAM playback operation when the internal destination is the baseband scaling multipliers. 3. Using the serial I/O port, write (or read) the address range specified by the selected RAM segment register. RT 3 RAM MODE Figure 40 shows the RAM block diagram when used for loading 16 ADDRESS STEP RATE RAM SEGMENT 10 START ADDRESS or retrieve operations. REGISTERS 10 END ADDRESS DDS CLOCK RT 3 BASEBAND DATA CLOCK RAM MODE 16 ADDRESS STEP RATE RAM SEGMENT 10 START ADDRESS REGISTERS CLK SDIO 10 END ADDRESS U/D 32 32 10 SDO STATE Q RAM DDS CLOCK MACHINE SCLK BASEBAND DATA CLOCK I/O_RESET CS UP/DOWN COUNTER I 16 SDIO CLK I CHANNEL IS U/D 32 32 10 SDO STATE (MSBs) Q RAM MACHINE SCLK Q Q CHANNEL 16 I/O_RESET QS CS UP/DOWN COUNTER I (LSBs) 16 NOTES I CHANNEL IS 1. NONESSENTIAL FUNCTIONAL COMPONENTS ARE RENDERED IN GRAY. (MSBs) Q Figure 41. RAM Playback to Baseband Scaling Multipliers Q CHANNEL 16 QS (LSBs) During playback to the baseband scaling multipliers, the NOTES 1. NONESSENTIAL FUNCTIONAL COMPONENTS ARE RENDERED IN GRAY. address step rate word in the active RAM segment register sets Figure 40. RAM Load/Retrieve Operation the rate at which RAM data samples are delivered to the multipliers. The following equations define the RAM sample During a load or retrieve operation, the state machine controls rate and sample interval (Δt): an up/down counter to step through the required RAM locations. f SYSCLK The counter is synchronized with the serial I/O port so that the RAM Sample Rate= 4RM serial/parallel conversion of the 32-bit words is correctly timed with the generation of the appropriate RAM address to properly 4RM ∆t= execute the desired read or write operation. The up/down f SYSCLK counter always increments through the address range during serial I/O port operations. where: R is the rate interpolation factor for the CCI filter. Because the RAM segment registers are completely independent, M is the 16-bit value of the address step rate word stored in the it is possible to define overlapping address ranges. However, active RAM segment register. doing so causes the overlapping address locations to be over- written by the most recent write operation. It is recommended If the RAM enable bit is set and the baseband scaling multi- that the user avoid defining overlapping address ranges. pliers are selected as the playback destination, then assertion of an I/O update or profile change causes the multipliers to be RAM PLAYBACK OPERATION driven with a static value of zero. A subsequent state change on When the RAM has been loaded, it can be used for playback the RT pin causes the multipliers to be driven by the data played operation. The destination of the playback data is selected via back from the RAM instead of the static zero value. the RAM playback destination bit. The active RAM segment Figure 42 is a block diagram showing RAM playback operation register is selected by the appropriate transition of the RT pin. when the internal destination is the baseband data path. During The active RAM segment register directs the internal state playback to the baseband data path, the state machine increments/ machine by defining the RAM address range occupied by the decrements the RAM address at the baseband data rate (the data and the RAM playback mode. It also defines the playback address step rate must be set to 1). Rev. C | Page 28 of 64 ADDRESS DATA SERIAL I/O PORT 06384-020 ADDRESS DATA SERIAL I/O PORT 06384-021 Data Sheet AD9957 RT RAM Ramp-Up Mode 3 RAM MODE 16 ADDRESS STEP RATE RAM In ramp-up mode, upon assertion of an I/O update or a state SEGMENT 10 START ADDRESS REGISTERS change on the RT pin, the RAM begins playback operation 10 END ADDRESS using the parameters programmed into the selected RAM seg- DDS CLOCK BASEBAND DATA CLOCK ment register. Data is extracted from RAM over the specified address range contained in the start address and end address of CLK SDIO U/D the active RAM segment register. The data is delivered at the 32 32 10 SDO STATE Q RAM MACHINE SCLK appropriate rate and to the destination as specified by the RAM I/O_RESET playback destination bit. UP/DOWN COUNTER CS I 16 I CHANNEL IS The playback rate is governed by the timer internal to the RAM (MSBs) state machine and its period (Δt) is determined by the state of the Q Q CHANNEL 16 QS RAM playback destination bit as detailed in the RAM playback (LSBs) operation section. NOTES 1. NONESSENTIAL FUNCTIONAL COMPONENTS ARE RENDERED IN GRAY. The internal state machine begins extracting data from the Figure 42. RAM Playback to Baseband Data Path RAM at the start address and continues to extract data until it OVERVIEW OF RAM PLAYBACK MODES reaches the end address. Upon reaching this address, the state machine halts. The RAM is operational in any one of four different playback modes. A graphic representation of the ramp-up mode appears in • Ramp-up Figure 43. The upper trace shows the progression of the RAM address from the start address to the end address for the active • Bidirectional ramp RAM segment register. The address value advances by one with • Continuous bidirectional ramp each timeout of the timer internal to the state machine. The circled • Continuous recirculate numbers indicate specific events, explained as follows: RAM playback is only functional when the AD9957 is pro- grammed for either the QDUC or interpolating DAC mode. Event 1—an I/O update or state transition on the RT pin. This event initializes the state machine to the start address of the active The RAM playback mode is selected via the 3-bit RAM play- RAM segment register. back mode word located in each of the RAM segment registers. Thus, the RAM playback mode is segment dependent. The Event 2—the state machine reaches the end address of the active RAM playback mode bits are detailed in Table 5. RAM segment register and halts. Table 5. RAM Playback Modes 1 PDCLK CYCLE OR RAM Playback Mode M DDS CLOCK CYCLES Bits<2:0> RAM Playback Mode 001 Ramp-up 010 Bidirectional ramp Δt 011 Continuous bidirectional END ADDRESS ramp RAM 100 Continuous recirculate ADDRESS 1 000, 101, 110, 111 Not Valid START ADDRESS The continuous bidirectional ramp and continuous recirculate I/O_UPDATE OR RT TRANSITION modes are not available when the baseband scaling multipliers 1 2 serve as the destination of RAM playback. Figure 43. Ramp-Up Timing Diagram Rev. C | Page 29 of 64 ADDRESS DATA SERIAL I/O PORT 06384-022 06384-023 AD9957 Data Sheet A Logic 1 to Logic 0 transition on the RT pin instructs the state RAM Bidirectional Ramp Mode machine to switch to RAM Segment Register 1 and to decrement This mode is unique in that the RAM segment playback mode through the address range starting with the end address. As word of both RAM segment registers must be programmed for long as the RT pin remains Logic 0, the state machine continues RAM bidirectional ramp mode. to play back the RAM data until it reaches the start address, at which point the state machine halts. In bidirectional ramp mode, upon assertion of an I/O update, the RAM readies for playback operation using the parameters It is important to note that RAM Segment Register 1 is played programmed into RAM Segment Register 0. The data is deliv- back in reverse order for bidirectional ramp mode. This must ered at the appropriate rate and to the destination as specified be kept in mind when the RAM contents are loaded via the by the RAM playback destination bit. serial I/O port when bidirectional ramp mode is the intended playback mode. The playback rate is governed by the timer that is internal to the RAM state machine, and its period (Δt) is determined by the A graphic representation of the bidirectional ramp mode state of the RAM playback destination bit as detailed in the appears in Figure 44. It demonstrates the action of the state RAM Playback Operation section. machine in response to the RT pin. If the RT pin changes states before the state machine reaches the programmed start or end Playback begins upon a 0 to 1 logic transition on the RT pin. address, the internal timer is restarted and the direction of the This instructs the state machine to increment through the address counter reversed. address range specified in RAM Segment Register 0 starting with the start address. As long as the RT pin remains Logic 1, the state machine continues to play back the RAM data until it reaches the end address, at which point the state machine halts. 0 1 0 1 0 RAM SEGMENT 1 PDCLK CYCLE OR M DDS CLOCK CYCLES END ADDRESS Δt NUMBER 0 RAM ADDRESS 1 Δt Δt START ADDRESS NUMBER 0 END ADDRESS NUMBER 1 RAM ADDRESS Δt Δt START ADDRESS NUMBER 1 RT PIN I/O_UPDATE 1 2 3 4 5 6 7 8 Figure 44. Bidirectional Ramp Timing Diagram Rev. C | Page 30 of 64 06384-024 Data Sheet AD9957 The circled numbers in Figure 44 indicate specific events, Event 5—the RT pin switches to Logic 1. The state machine explained as follows: initializes to the start address of RAM Segment Register 0, resets the internal timer, and begins incrementing the RAM Event 1—an I/O update or profile change activates the RAM address counter. bidirectional ramp mode. Event 6—the RT pin switches to Logic 0. The state machine Event 2—the RT pin switches to Logic 1. The state machine initializes to the end address of RAM Segment Register 1, resets initializes to the start address of RAM Segment Register 0 and the internal timer, and begins decrementing the RAM address begins incrementing the RAM address counter. counter. Event 3—the RT pin remained at Logic 1 long enough for the Event 7—the RT pin remained at Logic 0 long enough for the state machine to reach the end address of RAM Segment state machine to reach the start address of RAM Segment Register 0, at which point the address counter is halted. Register 1, at which point the address counter is halted. Event 4—the RT pin switches to Logic 0. The state machine Event 8—the RT pin switches to Logic 1. The state machine initializes to the end address of RAM Segment Register 1, resets initializes to the start address of RAM Segment Register 0, the internal timer, and begins decrementing the RAM address resets the internal timer, and begins incrementing the RAM counter. address counter. Rev. C | Page 31 of 64 AD9957 Data Sheet 1 PDCLK CYCLE OR M DDS CLOCK CYCLES Δt END ADDRESS RAM ADDRESS 1 Δt START ADDRESS I/O_UPDATE OR RT TRANSITION 1 2 3 Figure 45. Continuous Bidirectional Ramp Timing Diagram RAM Continuous Bidirectional Ramp Mode Note that a change in state of the RT pin aborts the current waveform and the newly selected RAM segment register is used In continuous bidirectional ramp mode, upon assertion of an to initiate a new waveform. I/O update or a state change on the RT pin, the RAM begins playback operation using the parameters programmed into the A graphic representation of the continuous bidirectional ramp selected RAM segment register. Data is extracted from RAM mode is shown in Figure 45. The circled numbers in Figure 45 over the specified address range contained in the start address indicate specific events, explained as follows: and end address. The data is delivered at the appropriate rate and to the destination as specified by the RAM playback Event 1—an I/O update or state change on the RT pin has destination bit. activated the RAM continuous bidirectional ramp mode. The state machine initializes to the start address of the active RAM The playback rate is governed by the timer internal to the RAM segment register. The state machine begins incrementing state machine and its period (Δt) is determined by the state of through the specified address range. the RAM playback destination bit as detailed in the RAM Playback Operation section. Event 2—the state machine reaches the end address of the active RAM segment register. After initialization, the internal state machine begins extracting data from the RAM at the start address of the active RAM segment Event 3—the state machine reaches the start address of the register and increments the address counter until it reaches the active RAM segment register. end address, at which point the state machine reverses the direc- The continuous bidirectional ramp continues indefinitely until tion of the address counter and begins decrementing through the next I/O update or state change on the RT pin. the address range. Whenever one of the terminal addresses is reached, the state machine reverses the address counter; the process continues indefinitely. Rev. C | Page 32 of 64 06384-025 Data Sheet AD9957 1 PDCLK CYCLE OR M DDS CLOCK CYCLES Δt END ADDRESS RAM ADRESS 1 START ADDRESS I/O_UPDATE OR RT TRANSITION 1 2 3 4 5 Figure 46. Continuous Recirculate Timing Diagram active RAM segment register and causes the state machine to RAM Continuous Recirculate Mode begin incrementing the address counter at the appropriate rate. The continuous recirculate mode mimics ramp-up mode, except that when the state machine reaches the end address of Event 2—the state machine reaches the end address of the active the active RAM segment register, it does not halt. Instead, the RAM segment register. next timeout of the internal timer causes the state machine to Event 3—the state machine switches to the start address of the jump to the start address of the active RAM segment register. active RAM segment register. The state machine continues to This process continues indefinitely until an I/O update or state increment the address counter. change on the RT pin. A state change on the RT pin aborts the current waveform and the newly selected RAM segment register Event 4—the state machine again reaches the end address of the initiates a new waveform. active RAM segment register. A graphic representation of the continuous recirculate mode is Event 5—the state machine switches to the start address of the shown in Figure 46. active RAM segment register. The state machine continues to increment the address counter. The circled numbers in Figure 46 indicate specific events, which are explained as follows: Event 4 and Event 5 repeat until an I/O update or state change occurs on the RT pin. Event 1—an I/O update or state change on the RT pin occurs. This initializes the state machine to the start address of the Rev. C | Page 33 of 64 06384-026 AD9957 Data Sheet CLOCK INPUT (REF_CLK) REFCLK OVERVIEW Table 6. REFCLK_OUT Buffer Control The AD9957 supports a number of options for producing the CFR3<29:28> REFCLK_OUT Buffer internal SYSCLK signal (that is, the DAC sample clock) via the 00 Disabled REF_CLK REF_CLK/ input pins. The REF_CLK input can be 01 Low output current driven directly from a differential or single-ended source, or it 10 Medium output current can accept a crystal connected across the two input pins. There 11 High output current is also an internal phase-locked loop (PLL) multiplier that can be independently enabled. A block diagram of the REF_CLK CRYSTAL DRIVEN REF_CLK functionality is shown in Figure 47. The various input configu- When using a crystal at the REF_CLK input, the resonant rations are controlled by means of the XTAL_SEL pin and frequency should be approximately 25 MHz. Figure 48 shows control bits in the CFR3 register. Figure 47 also shows how the the recommended circuit configuration. CFR3 control bits are associated with specific functional blocks. XTAL_SEL PLL_LOOP_FILTER 90 REF_CLK 95 2 DRV0 CFR3 XTAL <29:28> 2 91 PLL ENABLE REF_CLK 94 REFCLK_OUT CFR3 39pF 39pF REFCLK <8> INPUT SELECT LOGIC Figure 48. Crystal Connection Diagram ENABLE PLL_LOOP_FILTER 1 IN OUT 1 PLL 0 DIRECT DRIVEN REF_CLK 0 CHARGE VCO SYSCLK 90 REF_CLK PUMP DIVIDE SELECT REF_CLK When driving the REF_CLK/ inputs directly from a 2 7 3 91 signal source, either single-ended or differential signals can be REF_CLK I N VCO SEL CP used. With a differential signal source, the REF_CLK/REF_CLK CFR3 CFR3 CFR3 <7:1> <26:24> <21:19> 1 pins are driven with complementary signals and ac-coupled 0 ÷2 with 0.1 µF capacitors. With a single-ended signal source, either a single-ended-to-differential conversion can be employed or the REFCLK INPUT REFCLK INPUT REF_CLK input can be driven single-ended directly. In either case, DIVIDER RESETB DIVIDER BYPASS CFR3<14> CFR3<15> REF_CLK 0.1 µF capacitors are used to ac couple both REF_CLK/ Figure 47. REF_CLK Block Diagram pins to avoid disturbing the internal dc bias voltage of ~1.35 V. See Figure 49 for more details. The PLL enable bit is used to choose between the PLL path or the direct input path. When the direct input path is selected, the The REF_CLK/REF_CLK input resistance is ~2.5 kΩ differential REF_CLK/REF_CLK pins must be driven by an external signal (~1.2 kΩ single-ended). Most signal sources have relatively low source. Input frequencies up to 2 GHz are supported. For input output impedances. The REF_CLK/REF_CLK input resistance is frequencies greater than 1 GHz, the input divider must be relatively high; therefore, its effect on the termination impedance enabled for proper operation of the device. is negligible and can usually be chosen to be the same as the output impedance of the signal source. The bottom two examples in When the PLL is enabled, a buffered clock signal is available at Figure 49 assume a signal source with a 50 Ω output impedance. the REFCLK_OUT pin. This clock signal is the same frequency as the REF_CLK input. This is especially useful when a crystal is connected, because it gives the user a replica of the crystal clock for driving other external devices. The REFCLK_OUT buffer is controlled by two bits as listed in Table 6. Rev. C | Page 34 of 64 06384-028 06384-027 Data Sheet AD9957 0.1µF Figure 51 shows the boundaries of the VCO frequency ranges 90 REF_CLK PECL, over the full range of temperature and supply voltage variation LVPECL, DIFFERENTIAL SOURCE, OR TERMINATION DIFFERENTIAL INPUT. for an individual device selected from the population. Figure 51 LVDS DRIVER shows that the VCO frequency ranges for a single device always 91 REF_CLK 0.1µF overlap when operated over the full range of conditions. In conclusion, if a user wants to retain a single default value for 0.1µF BALUN (1:1) 90 CFR3<26:24>, a frequency that falls into one of the ranges REF_CLK found in Figure 50 should be selected. Additionally, for any SINGLE-ENDED SOURCE, 50Ω DIFFERENTIAL INPUT. given individual device, the VCO frequency ranges overlap, 91 REF_CLK meaning that any given device exhibits no gaps in its frequency 0.1µF coverage across VCO ranges over the full range of conditions. 0.1µF 90 FLOW = 920 REF_CLK VCO5 FHIGH = 1030 SINGLE-ENDED SOURCE, 50Ω SINGLE-ENDED INPUT. FLOW = 760 VCO4 FHIGH = 875 91 REF_CLK 0.1µF FLOW = 650 VCO3 FHIGH = 790 Figure 49. Direct Connection Diagram FLOW = 530 VCO2 FHIGH = 615 PHASE-LOCKED LOOP (PLL) MULTIPLIER FLOW = 455 VCO1 FHIGH = 530 An internal phase-locked loop (PLL) provides users of the AD9957 the option to use a reference clock frequency that is FLOW = 400 VCO0 FHIGH = 460 significantly lower than the system clock frequency. The PLL supports a wide range of programmable frequency multiplica- 395 495 595 695 795 895 995 (MHz) tion factors (12× to 127×) as well as a programmable charge Figure 50. VCO Ranges Including Atypical Wafer Process Skew pump current and external loop filter components (connected via the PLL_LOOP_FILTER pin). These features add an extra FLOW = 810 layer of flexibility to the PLL, allowing optimization of phase VCO5 FHIGH = 1180 noise performance and flexibility in frequency plan develop- FLOW = 646 ment. The PLL is also equipped with a PLL_LOCK pin. VCO4 FHIGH = 966 FLOW = 574 The PLL output frequency range (fSYSCLK) is constrained to the VCO3 FHIGH = 904 range of 420 MHz ≤ f ≤ 1 GHz by the internal VCO. In SYSCLK FLOW = 469 addition, the user must program the VCO to one of six operating VCO2 FHIGH = 709 ranges such that f falls within the specified range. Figure 50 SYSCLK FLOW = 402 and Figure 51 summarize these VCO ranges. FHIGH = 602 VCO1 Figure 50 shows the boundaries of the VCO frequency ranges FLOW = 342 VCO0 FHIGH = 522 over the full range of temperature and supply voltage variation 335 435 535 635 735 835 935 1035 1135 for all devices from the available population. The implication is (MHz) that multiple devices chosen at random from the population and Figure 51. Typical VCO Ranges operated under widely varying conditions may require different values to be programmed into CFR3<26:24> to operate at the Table 7. VCO Range Bit Settings same frequency. For example, Part A chosen randomly from the VCO SEL Bits population, operating in an ambient temperature of −10°C with (CFR3<26:24>) VCO Range a system clock frequency of 900 MHz may require CFR3<26:24> 000 VCO0 to be set to 100b. Whereas Part B chosen randomly from the 001 VCO1 population, operating in an ambient temperature of 90°C with a 010 VCO2 system clock frequency of 900 MHz may require CFR3<26:24> 011 VCO3 to be set to 101b. If a frequency plan is chosen such that the 100 VCO4 system clock frequency operates within one set of boundaries 101 VCO5 (as shown in Figure 51), the required value in CFR3<26:24> is 110 PLL Bypassed consistent from part to part. 111 PLL Bypassed Rev. C | Page 35 of 64 06384-029 06384-056 06384-057 AD9957 Data Sheet PLL CHARGE PUMP In the prevailing literature, this configuration yields a third- order, Type II PLL. To calculate the loop filter component The charge pump current (ICP) is programmable to provide the values, begin with the feedback divider value (N), the gain of user with additional flexibility to optimize the PLL performance. Table 8 lists the bit settings vs. the nominal charge pump the phase detector (KD), and the gain of the VCO (KV) based on current. the programmed VCO SEL bit settings (see Table 1 for KV). The loop filter component values depend on the desired open-loop Table 8. PLL Charge Pump Current bandwidth (fOL) and phase margin (φ), as follows: I (CFR3<21:19>) Charge Pump Current, I (μA) CP CP   πNf 1 OL R1= 1+  (7) 000 212   K K sin(φ) D V  001 237 010 262 K K tan(φ) D V C1= (8) 011 287 2 2N(πf ) OL 100 312   101 337 K K 1− sin(φ) D V C2=   (9) 2   110 363 N(2πf ) cos(φ) OL   111 387 where: K equals the programmed value of I . D CP EXTERNAL PLL LOOP FILTER COMPONENTS K is taken from Table 1. V The PLL_LOOP_FILTER pin provides a connection interface to attach the external loop filter components. The ability to use Ensure that proper units are used for the variables in Equation 7 custom loop filter components gives the user more flexibility to through Equation 9. ICP must be in amps, not μA as appears in optimize the PLL performance. The PLL and external loop filter Table 8; KV must be in Hz/V, not MHz/V as listed in Table 1; the components are shown in Figure 52. loop bandwidth (fOL) must be in Hz; the phase margin (φ) must AVDD be in radians. For example, suppose the PLL is programmed such that C1 I = 287 μA, K = 625 MHz/V, and N = 25. If the desired loop CP V C2 R1 bandwidth and phase margin are 50 kHz and 45°, respectively, the loop filter component values are R1 = 52.85 Ω, C1 = 145.4 nF, and C2 = 30.11 nF. PLL_LOOP_FILTER 2 PLL LOCK INDICATION REFCLK PLL When the PLL is in use, the PLL_LOCK pin provides an active PLL IN PFD CP VCO PLL OUT high indication that the PLL has locked to the REFCLK input signal. When the PLL is bypassed, the PLL_LOCK pin defaults ÷N to Logic 0. Figure 52. REFCLK PLL External Loop Filter Rev. C | Page 36 of 64 06384-030 Data Sheet AD9957 ADDITIONAL FEATURES OUTPUT SHIFT KEYING (OSK) • The maximum amplitude scale factor • The amplitude step size The OSK function (Figure 53) is only available in single tone mode. It allows the user to control the output signal amplitude • The time interval between steps of the DDS. Both manual and automatic modes are available. The amplitude ramp parameters reside in the 32-bit ASF OSK register and are programmed via the serial I/O port. The 60 amplitude step interval is set using the 16-bit amplitude ramp rate portion of the ASF register (Bits<31:16>). The maximum OSK ENABLE amplitude scale factor is set using the 14-bit amplitude scale AUTO OSK ENABLE factor in the ASF register (Bits<15:2>). The amplitude step size MANUAL OSK EXTERNAL is set using the 2-bit amplitude step size portion of the ASF LOAD ARR AT I/O_UPDATE 14 TO DDS register (Bits<1:0>). The direction of the ramp (positive or OSK 16 AMPLITUDE AMPLITUDE RAMP RATE CONTROLLER CONTROL (ASF<31:16>) negative slope) is controlled by the external OSK pin. When PARAMETER the OSK pin is a Logic 1, the slope is positive; otherwise, it is 14 AMPLITUDE SCALE FACTOR (ASF<15:2>) negative. 2 AMPLITUDE STEP SIZE The step interval is controlled by a 16-bit programmable timer (ASF<1:0>) that is clocked at a rate of ¼ f SYSCLK. The timer period sets the interval between amplitude steps. The step time interval (Δt) DDS CLOCK is given by Figure 53. OSK Block Diagram 4M ∆t= The operation of the OSK function is governed by four control f SYSCLK register bits, the external OSK pin, and the entire 32 bits of the where M is the 16-bit number stored in the amplitude ramp rate ASF register. The primary control for the OSK block is the OSK portion of the ASF register. For example, if f = 750 MHz SYSCLK enable bit. When this bit is set, the OSK function is enabled; and M = 23,218 (0x5AB2), then Δt ≈ 123.8293 μs. otherwise, the OSK function is disabled. When disabled, the other OSK input controls are ignored and the internal clocks are The output of the OSK function is a 14-bit unsigned data bus shut down to conserve power. that controls the amplitude of the DDS output (as long as the OSK enable bit is Logic 1). When the OSK pin is Logic 1, the When the OSK function is enabled, automatic and manual OSK output value starts at 0 and increments by the programmed operation is selected via the Select Auto-OSK bit. When this bit amplitude step size until it reaches the programmed maximum is set, the automatic mode is active; otherwise, the manual amplitude value. When the OSK pin is Logic 0, the OSK output mode is active. starts at its present value and decrements by the programmed Manual OSK amplitude step size until it reaches 0. In manual mode, output amplitude is varied by successive write The OSK output does not necessarily attain the maximum operations to the amplitude scale factor portion of the ASF amplitude—the OSK pin may switch to Logic 0 before attaining register. The rate at which amplitude changes can be applied to the maximum value. the output signal is limited by the speed of the serial I/O port. In manual mode, the OSK pin functionality depends on the The OSK output does not necessarily reach a value of zero—the state of the manual OSK external control bit. It is either inoperative OSK pin may switch to Logic 1 before attaining the zero value. or used to switch the output amplitude between the programmed amplitude scale factor value and zero. When operational, a Logic 0 The OSK output is initialized to 0 at power-up. It is also set to 0 on the OSK pin forces the output amplitude to zero whereas a when the OSK enable bit is Logic 0 or when the OSK enable bit is Logic 1, but the Select Auto-OSK bit is Logic 0. Logic 1 on the OSK pin causes the output amplitude to be scaled by the amplitude scale factor value. The amplitude step size of the OSK output is set by the ampli- Automatic OSK tude step size bits in the ASF register according to the values listed in Table 9. The step size refers to the LSB weight of the In automatic mode, the OSK function automatically generates 14-bit OSK output. a linear amplitude vs. time profile (or amplitude ramp). The amplitude ramp is controlled via three parameters, as follows: The OSK output cannot exceed the maximum amplitude value programmed into the ASF register. Rev. C | Page 37 of 64 06384-031 AD9957 Data Sheet Table 9. OSK Amplitude Step Size I/O_UPDATE PIN ASF<1:0> Amplitude Step Size By default, the I/O_UPDATE pin is an input that serves as a 00 1 strobe signal to allow synchronous update of the device operating 01 2 parameters. For example, frequency, phase, and amplitude con- 10 4 trol words for the DDS can be programmed using the serial I/O 11 8 port. However, the serial I/O port is an asynchronous interface; consequently, programming of the device operating parameters As mentioned earlier, the step interval is controlled by a 16-bit using the I/O port is not synchronized with the internal timing. programmable timer. Normally, this timer is loaded with the Using the pin, I/O_UPDATE, the user can synchronize the programmed timing value whenever the timer expires, thus application of certain programmed operating parameters with initiating a new timing cycle. However, three events cause the external circuitry when new parameters are programmed into timer to have its timing value reloaded prior to the timer expiring. the I/O registers. A rising edge on I/O_UPDATE initiates transfer One such event is when the Select Auto-OSK bit is transitioned of the register contents to the internal workings of the device. from a Logic 0 state to a Logic 1 state followed by an I/O update. A The transfer of programmed data from the programming second such event is a change of state in the OSK pin. The third registers to the internal hardware is also accomplished by event is dependent on the status of the Load ARR @ I/O Update changing the state of the profile pins. bit. If this bit is Logic 0, no action occurs; otherwise, when the I/O_UPDATE pin is asserted (or a profile change occurs), the AUTOMATIC I/O UPDATE timer resets to its initial starting point. The AD9957 offers an option whereby the I/O update function PROFILES is asserted automatically rather than relying on an external signal supplied by the user. This feature is enabled by setting the Each of the three operating modes of the AD9957 support the Internal I/O Update Active bit in CFR2. use of profiles, which consist of a group of registers containing pertinent operating parameters for a particular operating mode. When this feature is active, the I/O_UPDATE pin becomes an Profiles enable rapid switching between parameter sets. Profile output pin. It generates an active high pulse each time an inter- parameters are programmed via the serial I/O port. Once pro- nal I/O update occurs. The duration of the pulse is approximately grammed, a specific profile is activated by means of three 12 cycles of SYSCLK. This I/O update strobe can be used to external pins (PROFILE<2:0>). A particular profile is activated notify an external controller that the device has generated an by providing the appropriate logic levels to the profile control I/O update internally. pins per the settings listed in Table 10. The repetition rate of the internal I/O update is programmed Table 10. Profile Control Pins via the serial I/O port. Two parameters control the repetition PROFILE<2:0> Active Profile rate. The first parameter consists of the two I/O update rate 000 0 control bits in CFR2. The second parameter is the 32-bit word 001 1 in the I/O update rate register that sets the range of an internal 010 2 counter. 011 3 The I/O update rate control bits establish a divide by 1, 2, 4, or 8 100 4 of a clock signal that runs at ¼ fSYSCLK. The output of the divider 101 5 clocks the aforementioned 32-bit internal counter. The repetition 110 6 rate of the I/O update is given by 111 7 f SYSCLK f  Consider an application of basic two-tone frequency shift I /O _UPDATE A 2 B keying (FSK) where binary data is transmitted by selecting between two different frequencies: a mark frequency (Logic 1) where: and a space frequency (Logic 0). To accommodate FSK, the A is the value of the 2-bit word comprising the I/O update rate Profile 0 register is programmed with the appropriate frequency control bits. tuning word for a space, and the Profile 1 register is programmed B is the value of the 32-bit word stored in the I/O update rate with the appropriate frequency tuning word for a mark. Then, register. with the PROFILE1 and PROFILE2 pins tied to Logic 0, the If B is programmed to 0x0003 or less, the I/O_UPDATE pin no PROFILE0 pin is used to transmit the data bits. The logic state longer pulses, but assumes a static Logic 1 state. of the PROFILE0 pin causes the appropriate mark and space frequencies to be generated. Rev. C | Page 38 of 64 Data Sheet AD9957 POWER-DOWN CONTROL Each of these 16 pins is assigned a unique bit in both the 16-bit The AD9957 offers the ability to independently power down four GPIO configuration register and the 16-bit GPIO data register. specific sections of the device. Power-down functionality applies The status of each bit in the GPIO configuration register assigns to the digital core, DAC, auxiliary DAC, and REFCLK input. the associated pin as either a GPIO input or output (0 = input, A power-down of the digital core disables the ability to update 1 = output) based on the data listed in Table 11. the serial I/O port. However, the digital power-down bit can When a GPIO pin is programmed as an output, the logic state still be cleared via the serial port to prevent the possibility of a written to the associated bit of the GPIO data register (via the nonrecoverable state. serial I/O port) appears at the GPIO pin. When a GPIO pin is programmed as an input, the logic state of the GPIO pin can be Software power-down is controlled through four independent read (via the serial I/O port) in the associated bit position in the power-down bits in CFR1. Software control requires forcing the GPIO data register. Note that the GPIO data register does not EXT_PWR_DWN pin to a Logic 0 state. In this case, setting the desired power-down bits (via the serial I/O port) powers down require an I/O update. the associated functional block; clearing the bits restores the function. Table 11. GPIO Pins vs. Configuration and Data Register Bits Pin Label Configuration Bit Data Bit Alternatively, all four functions can be simultaneously powered D17 15 15 down via external hardware control through the EXT_PWR_DWN D16 14 14 pin. Forcing this pin to Logic 1 powers down all four circuit D15 13 13 blocks, regardless of the state of the power-down bits. That is, D14 12 12 the independent power-down bits in CFR1 are ignored and D13 11 11 overridden when EXT_PWR_DWN is Logic 1. D12 10 10 D11 9 9 Based on the state of the external power-down control bit, the D10 8 8 EXT_PWR_DWN pin produces either a full power-down or a D9 7 7 fast recovery power-down. The fast recovery power-down mode D8 6 6 maintains power to the DAC bias circuitry and the PLL, VCO, D7 5 5 and input section of the REFCLK circuitry. Although the fast D6 4 4 recovery power-down does not conserve as much power as the D3 3 3 full power-down, it allows the device to very quickly awaken D2 2 2 from the power-down state. D1 1 1 GENERAL-PURPOSE I/O (GPIO) PORT D0 0 0 The GPIO function is only available when the AD9957 is pro- grammed for QDUC mode and the Blackfin interface mode is active. Because the Blackfin serial interface uses only two of the 18 parallel data port pins (D<5:4>), the remaining 16 pins (D<17:6> and D<3:0>) are available as a GPIO port. Rev. C | Page 39 of 64 AD9957 Data Sheet SYNCHRONIZATION OF MULTIPLE DEVICES OVERVIEW The synchronization mechanism relies on the premise that the The internal clocks of the AD9957 provide the timing for the REFCLK signal appearing at each device is edge aligned with all propagation of data along the baseband signal processing path. others resulting from the external REFCLK distribution system These internal clocks are derived from the internal system clock (see Figure 59). (SYSCLK) and are all submultiples of the SYSCLK frequency. CLOCK GENERATOR The logic state of all of these clocks in aggregate during any given SYSCLK cycle defines a unique clock state. The clock state The clock generator provides the necessary timing for the inter- advances with each cycle of SYSCLK, but the sequence of clock nal workings of the AD9957. The goal of the synchronization states is periodic. By definition, multiple devices are synchro- mechanism is to force the clock generator to a known state nized when their clock states match and they transition between coincident with an external synchronization signal. The clock states simultaneously. Clock synchronization allows the user to generator consists of three separate clock trees (see Figure 55). asynchronously program multiple devices, but synchronously The first is a common clock generator that is active for all programmed modes of operation (single tone, QDUC, or activate the programming by applying a coincident I/O update to all devices. It also allows multiple devices to operate in unison interpolating DAC). The common clock generates the when the parallel port is in use with either the QDUC or inter- SYNC_CLK signal that appears at Pin 55. The second clock polating DAC mode (see Figure 59) or when the dual serial port generator is active when the device is programmed for the (BlackFin interface) is in use. interpolating DAC mode or quadrature modulation mode using the parallel data port. It uses the SYSCLK/2 output of the common The function of the synchronization logic in the AD9957 is to clock as its primary timing source. The third clock generator is force the internal clock generator to a predefined state coincident active when the device is programmed for quadrature modulation with an external synchronization signal applied to the SYNC_IN mode using the BlackFin interface. pins. Forcing multiple devices to the same clock state coincident COMMON CLOCK with the same external signal is, by definition, synchronization. GENERATOR Figure 54 is a block diagram of the synchronization function. SYNC PULSE The synchronization logic consists of two independent blocks, a SYSCLK ÷2 ÷2 SYNC_CLK sync generator and a sync receiver, both of which use the local CLOCK GENERATOR FOR INTERPOLATING SYSCLK signal for internal timing. DAC MODE OR QUADRATURE MODULATION MODE WITH THE PARALLEL DATA PORT REF_CLK 90 ÷R ÷2 PDCLK INPUT SYSCLK REF_CLK CIRCUITRY 91 6 CLOCK GENERATOR FOR QUADRATURE MODULATION MODE WITH THE BLACKFIN INTERFACE 5 ÷R ÷2 ÷2 ÷2 ÷2 9 SYNC SYNC_OUT GENERATOR 10 SYNC STATE 6 PRESET VALUE SYNC SYNC Figure 55. Clock Generator RECEIVER RECEIVER DELAY ENABLE 5 SYNC GENERATOR The sync generator block is shown in Figure 56. It is activated 7 INPUT DELAY SYNC_IN AND EDGE via the Sync Generator Enable bit. It allows for one AD9957 in a 8 DETECTION INTERNAL SYNC group to function as a master timing source with the remaining CLOCKS RECEIVER devices slaved to the master. 12 SETUP AND SYNC_SMP_ERR HOLD VALIDATION 6 4 SYNC STATE SYNC SYNC PRESET VALUE VALIDATION TIMING DELAY VALIDATION DISABLE Figure 54. Synchronization Circuit Block Diagram Rev. C | Page 40 of 64 CLOCK GENERATOR SYNC GENERATOR ENABLE SYNC POLARITY SYNC GENERATOR DELAY 06384-032 06384-065 Data Sheet AD9957 SYNC RECEIVER 9 PROGAMMABLE D Q SYNC_OUT SYSCLK DELAY ÷16 ÷2R 10 The sync receiver block (shown in Figure 57) is activated via the LVDS 5 DRIVER Sync Receiver Enable bit. The sync receiver consists of three 0 R SYNC 1 subsections: the input delay and edge detection block, the GENERATOR DELAY internal clock generator block, and the setup-and-hold valida- SYNC POLARITY SYNC tion block. GENERATOR ENABLE The clock generator block remains operational even when the sync receiver is not enabled. Figure 56. Sync Generator The sync receiver accepts an LVDS-compatible signal at the The sync generator produces an LVDS-compatible clock signal SYNC_IN pins. Typically, the signal applied to the SYNC_IN with a 50% duty cycle that appears at the SYNC_OUT pins. The pins originates from the SYNC_OUT of another AD9957 frequency of the SYNC_OUT signal can be one of two possible functioning as a master timing unit. The sync receiver expects a rates. With the AD9957 programmed for any of the following periodic synchronization pulse that meets certain frequency modes: requirements based on the operating mode of the AD9957. • Single tone mode When programmed for single tone mode, the frequency of • Quadrature modulation mode with the CCI filter bypassed SYNC_IN must satisfy (that is, interpolation factor is 1) f SYSCLK f = • Interpolating DAC mode with the CCI filter bypassed (that SYNC _ IN 4M is, interpolation factor is 1) where M is any integer greater than zero. When programmed The frequency of SYNC_OUT is given by: for quadrature modulation mode (using the parallel data port) or interpolating DAC mode, the frequency of SYNC_IN must f SYSCLK f = SYNC _ OUT satisfy 16 f SYSCLK With the AD9957 programmed for the QDUC or interpolating f = SYNC _ IN 16(R+ M) DAC mode and with the CCI filter not bypassed (that is, R>1) the frequency of SYNC_OUT is given by where R is the programmed CCI interpolation factor and M is f any integer greater than or equal to zero. When programmed SYSCLK f = SYNC _ OUT for quadrature modulation mode using the BlackFin interface, 32R the frequency of SYNC_IN must satisfy where R is the programmed interpolation factor of the CCI filter. f SYSCLK f = SYNC _ IN The signal at the SYNC_OUT pins is edge aligned with either 32(R+ M) the rising or falling edge of the internal SYSCLK signal as deter- mined by the Sync Polarity bit. Because the SYNC_OUT signal is where R is the programmed CCI interpolation factor and M is any integer greater than or equal to zero. synchronized with the internal SYSCLK of the master device, the master device SYSCLK serves as the reference timing source for all slave devices. The user can adjust the output delay of the SYNC_OUT signal in steps of ~75 ps by programming the 5-bit sync generator delay word via the serial I/O port. The programmable output delay facilitates added edge timing flexibility to the overall synchronization mechanism. Rev. C | Page 41 of 64 06384-033 AD9957 Data Sheet CLOCK SYNC STATE STATE PRESET VALUE SYNC DELAYED SYNC-IN SIGNAL RECEIVER 6 ENABLE SYNC P Q 0 RECEIVER R . . DELAY E INTERNAL . . S CLOCKS LVDS 5 . . E RECEIVER RISING EDGE T Q N DETECTOR SYNC_IN+ 7 PROGAMMABLE AND LOAD DELAY SYNC_IN– 8 STROBE GENERATOR CLOCK GENERATOR SETUP AND HOLD SYNC_SMP_ERR 12 VALIDATION SYSCLK 4 SYNC SYNC SYNC PULSE TIMING VALIDATION VALIDATION DELAY DISABLE Figure 57. Sync Receiver to each device in a group. This flexibility is limited, however, When a device other than another AD9957 provides the because the sync state preset value must adhere to certain SYNC_IN signal it must be LVDS compatible. Furthermore, bounds to satisfy internal timing requirements. Regardless of although SYNC_IN is typically considered to be a periodic the programmed sync state preset value, the preset value is clock signal, it is not an absolute requirement. It is feasible to internally constrained to the range, 2 to R, where R is the CCI drive the SYNC_IN pins with a single synchronization pulse as filter interpolation factor. A programmed value of 0 or 1 is forced long as its edge transition meets the setup/hold timing required to 2, whereas a programmed value greater than R is forced to R. for the internally generated sync pulse (as detailed later in this section). However, using a periodic SYNC_IN signal has the SETUP/HOLD VALIDATION distinct advantage that should any of the devices arbitrarily lose Synchronization of the AD9957 internal clock generator with synchronization it automatically resynchronizes with the arrival other external devices relies on the ability of the sync receiver’s of the next SYNC_IN edge. edge detection circuit to generate a valid sync pulse. This requires proper sampling of the rising edge of the delayed The 5-bit sync receiver delay word in the multichip sync register SYNC_IN signal with the rising edge of the local SYSCLK. If the delays the SYNC_IN signal in steps of ~75 ps. This provides the edge timing of these signals fails to meet the setup or hold time ability to time align the arrival of the SYNC_IN signal to requirements of the internal latches in the edge detection multiple devices by compensating for unequal propagation times. circuitry, the proper generation of a sync pulse is in jeopardy. The edge detection logic in the sync receiver generates a The setup-and-hold validation block (see Figure 58) gives the synchronization pulse (sync pulse) having a duration of one user a means to validate that proper edge timing exists between SYSCLK cycle with a repetition rate equal to that of the signal the two signals. The Sync Timing Validation Disable bit in applied to the SYNC_IN pins. To produce the sync pulse, the Control Function Register 2 controls whether or not the setup- strobe generator samples the delayed rising edge of the SYNC_IN and-hold validation block is active. signal with the rising edge of the local SYSCLK. The generation The validation block makes use of a specified time window of this sync pulse is crucial to the operation of the synchroniza- (programmable in increments of ~75 ps via the 4-bit sync tion mechanism, because it performs the task of placing the clock generator into a known state. The sync pulse presets the validation delay word in the multichip sync register). The setup R-divider stage of the internal clock generator, which behaves as validation and hold validation circuits use latches identical to a presettable downcounter (see Figure 55). The programmable those in both the rising edge detector and strobe generator. The programmable time window skews the timing between the local 6-bit sync state preset value word in the multichip sync register SYSCLK signal and the delayed sync-in signal. If the hold valida- establishes the preset state. The preset state is only active for a tion and setup validation circuits fail to produce the same logic single SYSCLK period, after which the clock generator is free to states, it is an indication of a possible setup or hold violation. cycle through its state sequence until the next sync pulse arrives (see Figure 55). In addition to presetting the R-divider, the sync The check logic of Figure 58 monitors the state of the setup and pulse also synchronously presets the other dividers to a proper hold validation latches. If they are not equal (that is, a potential state in order to preserve the cadence of the clock tree. setup/hold violation exists), a Logic 1 is stored in an internal validation result latch; otherwise, a Logic 0 is stored. The state The ability to program the clock state preset value provides the of validation result latch appears at the SYNC_SMP_ERR pin. flexibility to synchronize devices, but with specific relative clock state offsets by assigning a different sync state preset value word Rev. C | Page 42 of 64 06384-034 Data Sheet AD9957 The validation result latch is in a reset state whenever the sync Because the programmed value of the sync validation delay receiver is disabled, which forces the SYNC_SMP_ERR pin to a establishes the time window for a setup/hold measurement, Logic 0 state. To reset the validation result latch when the sync the amount of delay is an important consideration for proper operation of the validation block. The value chosen should receiver is active, however, requires the use of the Sync Timing Validation Disable bit in the multichip sync register. To make a represent a small fraction of the SYSCLK period. For example, setup/hold validation measurement is a two-step process. First, if the SYSCLK frequency is 1 GHz (1000 ps period), then a write a Logic 1 to the sync timing validation disable bit. Then, reasonable sync validation delay value is 4 (~300 ps). This to make a measurement, write a Logic 0. The first action resets allows the validation block to ensure that the local SYSCLK the validation result latch and holds it in a reset state; the and the delayed SYNC_IN edges exhibit at least 300 ps of second action releases the reset state and enables the validation timing separation. Choosing too large a value can cause the result latch to capture a setup/hold validation measurement. validation block to indicate a setup/hold violation when one Each time a new setup/hold validation check is desired, this does not exist. Choosing too small a value can cause the two-step procedure must be performed. validation block to miss a setup/hold violation when one actually exists. SYNC RECEIVER RISING EDGE FROM DETECTOR SYNC AND STROBE RECEIVER GENERATOR DELAY TO LOGIC CLOCK GENERATION SYNC D Q LOGIC PULSE SETUP AND HOLD VALIDATION SETUP VALIDATION DELAY D Q 4 12 SYNC_SMP_ERR 4 SYNC VALIDATION DELAY 4 D Q SYSCLK DELAY HOLD VALIDATION SYNC TIMING VALIDATION DISABLE Figure 58. Sync Timing Validation Block Rev. C | Page 43 of 64 CHECK LOGIC 06384-036 AD9957 Data Sheet generator is coordinated with the others. This is the role of the SYNCHRONIZATION EXAMPLE synchronization and delay equalization block. This block accepts To accomplish the synchronization of multiple devices provide the SYNC_OUT signal generated by the master device and each AD9957 with a SYNC_IN signal that is edge aligned across redistributes it to the SYNC_IN input of the slave units (as well all the devices. If the SYNC_IN signal is edge aligned at all devices, as feeding it back to the master). The goal of the redistributed and all devices have the same sync receiver delay and sync state SYNC_OUT signal from the master device is to deliver an edge- preset value, then they all have matching clock states (that is, aligned SYNC_IN signal to all of the sync receivers. they are synchronized). Figure 59 shows this concept with three AD9957s in synchronization. One device operates as a master Assuming that all devices share the same REFCLK edge timing timing unit with the others synchronized to the master. (due to the clock distribution and delay equalization block) and that all devices share the same SYNC_IN edge timing (due to The master device must have its SYNC_IN pins included as part the synchronization and delay equalization block), then all of the synchronization distribution and delay equalization mecha- devices should be generating an internal sync pulse in unison nism. This ensures that the master maintains synchronous timing (assuming all have the same value for the sync receiver delay). with the other units. With the further stipulation that all devices have the same sync state preset value, then the synchronized sync pulses cause all of The synchronization mechanism begins with the clock distribu- the devices to assume the same predefined clock state simultane- tion and delay equalization block, which ensures that all devices ously. That is, all devices have their internal clocks fully receive an edge-aligned REFCLK signal. However, even though synchronized. the REFCLK signal is edge aligned among all devices, this alone does not guarantee that the clock state of each internal clock CLOCK DISTRIBUTION AND CLOCK DELAY EQUALIZATION SOURCE EDGE (FOR EXAMPLE, AD951x) ALIGNED AT REF_CLK INPUTS REF_CLK DATA AD9957 FPGA MASTER DEVICE NUMBER 1 SYNC SYNC IN OUT EDGE ALIGNED AT SYNC_IN REF_CLK DATA INPUTS. AD9957 FPGA NUMBER 2 SYNC SYNC IN OUT SYNCHRONIZATION DISTRIBUTION AND DELAY EQUALIZATION (FOR EXAMPLE AD951x) REF_CLK DATA AD9957 FPGA NUMBER 3 SYNC SYNC IN OUT Figure 59. Multichip Synchronization Example Rev. C | Page 44 of 64 PDCLK PDCLK PDCLK 06384-035 Data Sheet AD9957 signal process path by updating a parallel register at the proper I/Q PATH LATENCY time. The data is transferred from the parallel register to the The I/Q latency through the AD9957 is easiest to describe in signal processing chain and all timing has been verified regard- terms of system clock (SYSCLK) cycles and is a function of the less of the phase relationship between the updating of the parallel AD9957 configuration (that is, which mode and which optional register and the signal processing clock. features are engaged). The I/Q latency is primarily affected by the programmable CCI rate. Example Quadrature modulation mode = 18-bit parallel data The values in Table 12 should be considered estimates because Reference clock multiplier = bypassed observed latency may be data dependent. The latency was Input scale multiplier = off calculated using the linear delay model for FIR filters. N = CCI Inverse CCI = off rate (programmable interpolation rate, 2 to 63, 1 if bypassed). CCI rate = 20 Inverse SINC = on In BFI mode, the latency through the AD9957 may not be con- Output scale = off stant for multiple transmissions. This is due to the relationship between the phase of the clock that drives the first half-band Latency = (16 × 20) + (4 × 20) + (4 × 20) + (69 × 20) + filter and the frame sync signal coming from the Blackfin, (4 × 20 + 8) + 22 + 8 + 2 + 8 = 1988 SYSCLKs which is unknown and denoted as x in Table 12. The design successfully transfers data from the data assembler logic to the Table 12. Stage Quadrature Modulation Mode—Parallel Quadrature Modulation Mode—BFI Interpolation DAC Mode Input Demuxplexer 16N (16 + x)N 28N where x = 0 to 15 Input Scale Multiplier Active: 8N Not available in BFI mode Active: 8N Bypassed: 4N Bypassed: 4N Inverse CCI Filter Active: 8N Active: 8N Active: 8N Bypassed: 4N Bypassed: 4N Bypassed: 4N Half-Band Filters 69N 345N 69N CCI Filter Active: 4N + 8 Active: 4N + 8 Active: 4N + 8 Bypass: 2N + 4 Bypass: 2N + 4 Bypass: 2N + 4 Modulator 22 22 0 Inverse Sinc Filter Active: 8 Active: 8 Active: 8 Bypass: 2 Bypass: 2 Bypass: 2 Output Scale Multiplier Active: 12 Active: 12 Active: 12 Bypass: 2 Bypass: 2 Bypass: 2 DAC Interface 8 8 8 Rev. C | Page 45 of 64 AD9957 Data Sheet POWER SUPPLY PARTITIONING The AD9957 features multiple power supplies, and their power 1.8 V SUPPLIES consumption varies with its configuration. This section covers DVDD (Pin 17, Pin 23, Pin 30, Pin 47, Pin 57, Pin 64) which power supplies can be grouped together and how the These pins can be grouped together. Their current consumption power consumption of each block varies with frequency. increases linearly with the system clock frequency. A system clock of 1 GHz produces a typically current consumption of The values quoted in this section are for comparison only. Refer 610 mA in QDUC mode. There is also a slight (~5%) increase to Table 1 for exact values. With each group, bypass capacitors of as fOUT increases from 50 MHz to 400 MHz. 1 μF in parallel with a 10 μF capacitor should be used. AVDD (Pin 3) The recommendations here are for typical applications, for which there are four groups of power supplies: 3.3 V digital, This 1.8 V supply powers the REFCLK multiplier (PLL) and 3.3 V analog, 1.8 V digital, and 1.8 V analog. consumes about 7 mA. For applications demanding the highest performance with the PLL enabled, this supply should be Applications demanding the highest performance may require isolated from other 1.8 V AVDD supplies with a separate additional power supply isolation. regulator. For less demanding applications this supply can be run off the same regulator as Pin 89, Pin 92 with a ferrite bead 3.3 V SUPPLIES to isolate Pin 3 from Pin 89, and Pin 89. DVDD_I/O (Pin 11, Pin 15, Pin 21, Pin 28, Pin 45, Pin 56, Pin 66) The loop filter for the PLL should directly connect to Pin 3. If These 3.3 V supplies can be grouped together. The power the PLL is bypassed, pin 3 should still be powered, but isolation is not critical. consumption on these pins varies dynamically with serial port activity. AVDD (Pin 6) AVDD (Pin 74 to Pin 77 and Pin 83) This pin can be grouped together with the DVDD 1.8V supply pins. For the highest performance, a ferrite bead should be used These are 3.3 V DAC power supplies that typically consume for isolation, with a separate regulator being ideal. about 28 mA. At a minimum, a ferrite bead should be used to isolate these from other 3.3 V supplies, with a separate regulator AVDD (Pin 89 and Pin 92) being ideal. The current consumption of these supplies consist This 1.8 V supply for the REFCLK input consumes about mainly of biasing current and do not vary with frequency. 15 mA. The supply can be run off the same as Pin 3 with a ferrite bead to isolate Pin 3 from Pin 89 and Pin 92. At a minimum, a ferrite bead should be used to isolate these from other 1.8 V supplies. However, for applications demanding the highest performance, a separate regulator is recommended. Rev. C | Page 46 of 64 Data Sheet AD9957 SERIAL PROGRAMMING For a read cycle, Phase 2 is the same as the write cycle with the CONTROL INTERFACE—SERIAL I/O following differences: Data is read from the active registers, not The AD9957 serial port is a flexible, synchronous serial commu- the serial port buffer, and data is driven out on the falling edge nications port allowing easy interface to many industry-standard of SCLK. microcontrollers and microprocessors. Note that to read back any profile register (0x0E to 0x15), the The interface allows read/write access to all registers that configure three external profile pins must be used. For example, if the the AD9957. MSB-first or LSB-first transfer formats are sup- profile register is Profile 5 (0x13) then PROFILE<0:2> pins ported. In addition, the serial interface port can be configured must equal 101.This is not required to write to profile registers. as a single pin input/output (SDIO) allowing a two-wire interface, or it can be configured as two unidirectional pins for input/output INSTRUCTION BYTE (SDIO/SDO), enabling a 3-wire interface. Two optional pins The instruction byte contains the following information as CS (I/O_RESET and ) enable greater flexibility for designing shown in the instruction byte bit map. systems with the AD9957. Instruction Byte Information Bit Map GENERAL SERIAL I/O OPERATION MSB LSB There are two phases to a serial communications cycle. The first D7 D6 D5 D4 D3 D2 D1 D0 is the instruction phase to write the instruction byte into the R/W X X A4 A3 A2 A1 A0 AD9957. The instruction byte contains the address of the regis- W ter to be accessed (see the Register Map and Bit Descriptions R/ —Bit 7 of the instruction byte determines whether a read section) and defines whether the upcoming data transfer is a or write data transfer occurs after the instruction byte write. write or read operation. Logic 1 indicates a read operation. Cleared indicates a write operation. For a write cycle, Phase 2 represents the data transfer between the serial port controller to the serial port buffer. The number X, X—Bit 6 and Bit 5 of the instruction byte are don’t cares. of bytes transferred is a function of the register being accessed. A4, A3, A2, A1, A0—Bit 4, Bit 3, Bit 2, Bit 1, and Bit 0 of the For example, when accessing the Control Function Register 2 instruction byte determine which register is accessed during the (Address 0x01), Phase 2 requires that four bytes be transferred. data transfer portion of the communications cycle. Each bit of data is registered on each corresponding rising edge of SCLK. The serial port controller expects that all bytes of the SERIAL I/O PORT PIN DESCRIPTIONS register be accessed; otherwise, the serial port controller is put SCLK—Serial Clock out of sequence for the next communication cycle. However, The serial clock pin is used to synchronize data to and from the one way to write fewer bytes than required is to use the I/O_RESET AD9957 and to run the internal state machines. pin feature. The I/O_RESET pin function can be used to abort an I/O operation and reset the pointer of the serial port con- CS—Chip Select Bar troller. After an I/O reset, the next byte is the instruction byte. An active low input that allows more than one device on the Note that every completed byte written prior to an I/O reset is same serial communications line. The SDO and SDIO pins go preserved in the serial port buffer. Partial bytes written are not to a high impedance state when this input is high. If driven high preserved. At the completion of any communication cycle, the during any communications cycle, that cycle is suspended until AD9957 serial port controller expects the next eight rising CS CS is reactivated low. Chip select ( ) can be tied low in SCLK edges to be the instruction byte for the next communi- systems that maintain control of SCLK. cation cycle. SDIO—Serial Data Input/Output After a write cycle, the programmed data resides in the serial port buffer and is inactive. I/O_UPDATE transfers data from Data is always written into the AD9957 on this pin. However, the serial port buffer to active registers. The I/O update can this pin can be used as a bidirectional data line. Bit 1 of CFR1, either be sent after each communication cycle or when all serial Register Address 0x00, controls the configuration of this pin. operations are complete. In addition, a change in profile pins The default is cleared, which configures the SDIO pin as can initiate an I/O update. bidirectional. Rev. C | Page 47 of 64 AD9957 Data Sheet SDO—Serial Data Out SERIAL I/O TIMING DIAGRAMS Data is read from this pin for protocols that use separate lines Figure 60 through Figure 63 provide basic examples of the tim- for transmitting and receiving data. In the case where the ing relationships between the various control signals of the serial AD9957 operates in a single bidirectional I/O mode, this pin I/O port. Most of the bits in the register map are not transferred does not output data and is set to a high impedance state. to their internal destinations until assertion of an I/O update, which is not included in the timing diagrams that follow. I/O_RESET—Input/Output Reset I/O_RESET synchronizes the I/O port state machines without MSB/LSB TRANSFERS affecting the addressable registers contents. An active high The AD9957 serial port can support both most significant bit input on the I/O_RESET pin causes the current communication (MSB) first or least significant bit (LSB) first data formats. This cycle to abort. After I/O_RESET returns low (Logic 0), another functionality is controlled by Bit 0 in Control Function Register 1 communication cycle can begin, starting with the instruction (0x00). The default format is MSB first. If LSB first is active, byte write. all data, including the instruction byte, must follow LSB-first convention. Note that the highest number found in the bit range I/O_UPDATE—Input/Output Update column for each register is the MSB and the lowest number is The I/O_UPDATE initiates the transfer of written data from the LSB for that register (see the Register Map and Bit the I/O port buffer to active registers. I/O_UPDATE is active Descriptions section and Table 13). on the rising edge and its pulse width must be greater than one SYNC_CLK period. It is either an input or output pin depending on the programming of the Internal I/O Update Active bit. INSTRUCTION CYCLE DATA TRANSFER CYCLE CS SCLK I I I I I I I I D D D D D D D D SDIO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Figure 60. Serial Port Write Timing—Clock Stall Low INSTRUCTION CYCLE DATA TRANSFER CYCLE CS SCLK SDIO I I I I I I I I DON'T CARE 7 6 5 4 3 2 1 0 D D D D D D D D SDO O7 O6 O5 O4 O3 O2 O1 O0 Figure 61. 3-Wire Serial Port Read Timing—Clock Stall Low INSTRUCTION CYCLE DATA TRANSFER CYCLE CS SCLK SDIO I I I I I I I I D D D D D D D D 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Figure 62. Serial Port Write Timing—Clock Stall High INSTRUCTION CYCLE DATA TRANSFER CYCLE CS SCLK SDIO I I I I I I I I D D D D D D D D 7 6 5 4 3 2 1 0 O7 O6 O5 O4 O3 O2 O1 O0 Figure 63. 2-Wire Serial Port Read Timing—Clock Stall High Rev. C | Page 48 of 64 06384-039 06384-040 06384-037 06384-038 Data Sheet AD9957 For example, if repetitive changes to phase offset via the SPI I/O_UPDATE, SYNC_CLK, AND SYSTEM CLOCK port is desired, the latency of those changes to the DAC output RELATIONSHIPS is constant; otherwise, a time uncertainty of one SYNC_CLK The I/O_UPDATE pin is used to transfer data from the serial period is present. I/O buffer to the active registers in the device. Data in the buffer is inactive. By default, the I/O_UPDATE pin is an input that serves as a strobe signal to allow synchronous update of the device oper- SYNC_CLK is a rising edge active signal. It is derived from the ating parameters. A rising edge on I/O_UPDATE initiates system clock and a divide-by-4 frequency divider. SYNC_CLK, transfer of the register contents to the internal workings of which is externally provided, can be used to synchronize the device. Alternatively, the transfer of programmed data from external hardware to the AD9957 internal clocks. the programming registers to the internal hardware can be accomplished by changing the state of the PROFILE[2:0] pins. I/O_UPDATE initiates the start of a buffer transfer. It can be sent synchronously or asynchronously relative to the The timing diagram shown in Figure 64 depicts when the data SYNC_CLK. If the setup time between these signals is met, in the buffer is transferred to the active registers. then constant latency (pipeline) to the DAC output exists. SYSCLK A B SYNC_CLK I/O_UPDATE DATA IN N – 1 N N + 1 REGISTERS DATA IN N N + 1 N + 2 I/O BUFFERS THE DEVICE REGISTERS AN I/O UPDATE AT POINT A. THE DATA IS TRANSFERRED FROM THE ASYNCHRONOUSLY LOADED I/O BUFFERS AT POINT B. Figure 64. I/O_UPDATE Transferring Data from I/O Buffer to Active Registers Rev. C | Page 49 of 64 06384-161 AD9957 Data Sheet REGISTER MAP AND BIT DESCRIPTIONS REGISTER MAP Note that the highest number found in the Bit Range column for each register in the following tables is the MSB and the lowest number is the LSB for that register. Table 13. Control Registers Register Bit Name Range (Serial (Internal Bit 7 Bit 0 Default Address) Address) (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) Value Control <31:24> RAM Open RAM Open Operating Mode 0x00 Function Enable Playback Register 1 Destination CFR1 <23:16> Manual Inverse Clear CCI Open Select 0x00 (0x00) OSK Sinc Filter DDS External Enable Sine Control Output <15:8> Open Autoclear Open Clear Phase Load ARR @ OSK Select 0x00 Phase Accumulator I/O Update Enable Auto- Accumulator OSK <7:0> Digital DAC Power- REFCLK Input Aux DAC External Auto SDIO LSB First 0x00 Power- Down Power-Down Power-Down Power-Down Power-Down Input Down Control Enable Only Control <31:24> Blackfin Blackfin Bit Blackfin Open Enable 0x00 Function Interface Order Early Frame Profile Register 2 Mode Sync Enable Registers CFR2 Active as ASF (0x01) Source <23:16> Internal SYNC_CLK Open Read 0x40 Enable I/O Effective Update FTW Active <15:8> I/O Update Rate Control PDCLK Rate Data Format PDCLK PDCLK TxEnable Q-First 0x08 Control Enable Invert Invert Data Pairing <7:0> Open Data Sync Timing Open 0x20 Assembler Validation Hold Last Disable Value Control <31:24> Open DRV0<1:0> Open VCO SEL<2:0> 0x1F Function <23:16> Open I <2:0> Open 0x3F CP Register 3 <15:8> REFCLK REFCLK Open PLL 0x40 CFR3 Input Input Enable (0x02) Divider Divider Bypass ResetB <7:0> N<6:0> Open 0x00 Auxiliary <31:24> Open 0x00 DAC <23:16> Open 0x00 Control <15:8> Open 0x7F Register <7:0> FSC<7:0> 0x7F (0x03) I/O Update <31:24> I/O Update Rate<31:24> 0xFF Rate <23:16> I/O Update Rate<23:16> 0xFF Register <15:8> I/O Update Rate<15:8> 0xFF (0x04) <7:0> I/O Update Rate<7:0> 0xFF Rev. C | Page 50 of 64 Data Sheet AD9957 Table 14. RAM, ASF, Multichip Sync, and Profile 0 Registers Bit Range Register Name (Internal Bit 7 Bit Bit 0 Default (Serial Address) Address) (MSB) Bit 6 Bit5 4 Bit 3 Bit 2 Bit 1 (LSB) Value RAM Segment <47:40> RAM Address Step Rate 0<15:8> Register 0 (0x05) <39:32> RAM Address Step Rate 0<7:0> <31:24> RAM End Address 0<9:2> <23:16> RAM End Open Address 0<1:0> <15:8> RAM Start Address 0<9:2> <7:0> RAM Start Open RAM Playback Mode 0<2:0> Address 0<1:0> RAM Segment <47:40> RAM Address Step Rate 1<15:8> Register 1 (0x06) <39:32> RAM Address Step Rate 1<7:0> <31:24> RAM End Address 1<9:2> <23:16> RAM End Open Address 1<1:0> <15:8> RAM Start Address 1<9:2> <7:0> RAM Start Open RAM Playback Mode 1<2:0> Address 1<1:0> Amplitude Scale <31:24> Amplitude Ramp Rate<15:8> 0x00 Factor (ASF) <23:16> Amplitude Ramp Rate<7:0> 0x00 Register <15:8> Amplitude Scale Factor<13:6> 0x00 (0x09) <7:0> Amplitude Scale Factor<5:0> Amplitude Step Size<1:0> 0x00 Multichip Sync <31:24> Sync Validation Delay<3:0> Sync Sync Sync Open 0x00 Register (0x0A) Receiver Generator Generator Enable Enable Polarity <23:16> Sync State Preset Value<5:0> Open 0x00 <15:8> Sync Generator Delay<4:0> Open 0x00 <7:0> Sync Receiver Delay<4:0> Open 0x00 Profile 0 <63:56> Open Amplitude Scale Factor<13:8> 0x08 Register—Single <55:48> Amplitude Scale Factor<7:0> 0xB5 Tone (0x0E) <47:40> Phase Offset Word<15:8> 0x00 <39:32> Phase Offset Word<7:0> 0x00 <31:24> Frequency Tuning Word<31:24> 0x00 <23:16> Frequency Tuning Word<23:16> 0x00 <15:8> Frequency Tuning Word<15:8> 0x00 <7:0> Frequency Tuning Word<7:0> 0x00 Profile 0 <63:56> CCI Interpolation Rate<7:2> Spectral Invert Inverse 0x00 Register—QDUC CCI Bypass (0x0E) <55:48> Output Scale Factor 0x00 <47:40> Phase Offset Word<15:8> 0x00 <39:32> Phase Offset Word<7:0> 0x00 <31:24> Frequency Tuning Word<31:24> 0x00 <23:16> Frequency Tuning Word<23:16> 0x00 <15:8> Frequency Tuning Word<15:8> 0x00 <7:0> Frequency Tuning Word<7:0> 0x00 Rev. C | Page 51 of 64 AD9957 Data Sheet Table 15. Profile 1, Profile 2, and Profile 3 Registers Register Name Bit Range Bit 7 Bit 0 (Serial (Internal Default Address) Address) (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) Value Profile 1 <63:56> Open Amplitude Scale Factor<13:8> 0x00 Register— <55:48> Amplitude Scale Factor<7:0> 0x00 Single Tone <47:40> Phase Offset Word<15:8> 0x00 (0x0F) <39:32> Phase Offset Word<7:0> 0x00 <31:24> Frequency Tuning Word<31:24> 0x00 <23:16> Frequency Tuning Word<23:16> 0x00 <15:8> Frequency Tuning Word<15:8> 0x00 <7:0> Frequency Tuning Word<7:0> 0x00 Profile 1 <63:56> CCI Interpolation Rate<7:2> Spectral Inverse CCI 0x00 Register— Invert Bypass QDUC (0x0F) <55:48> Output Scale Factor<7:0> 0x00 <47:40> Phase Offset Word<15:8> 0x00 <39:32> Phase Offset Word<7:0> 0x00 <31:24> Frequency Tuning Word<31:24> 0x00 <23:16> Frequency Tuning Word<23:16> 0x00 <15:8> Frequency Tuning Word<15:8> 0x00 <7:0> Frequency Tuning Word<7:0> 0x00 Profile 2 <63:56> Open Amplitude Scale Factor<13:8> 0x00 Register— <55:48> Amplitude Scale Factor<7:0> 0x00 Single Tone <47:40> Phase Offset Word<15:8> 0x00 (0x10) <39:32> Phase Offset Word<7:0> 0x00 <31:24> Frequency Tuning Word<31:24> 0x00 <23:16> Frequency Tuning Word<23:16> 0x00 <15:8> Frequency Tuning Word<15:8> 0x00 <7:0> Frequency Tuning Word<7:0> 0x00 Profile 2 <63:56> CCI Interpolation Rate<7:2> Spectral Inverse CCI 0x00 Register— Invert Bypass QDUC (0x10) <55:48> Output Scale Factor<7:0> 0x00 <47:40> Phase Offset Word<15:8> 0x00 <39:32> Phase Offset Word<7:0> 0x00 <31:24> Frequency Tuning Word<31:24> 0x00 <23:16> Frequency Tuning Word<23:16> 0x00 <15:8> Frequency Tuning Word<15:8> 0x00 <7:0> Frequency Tuning Word<7:0> 0x00 Profile 3 <63:56> Open Amplitude Scale Factor<13:8> 0x00 Register— <55:48> Amplitude Scale Factor<7:0> 0x00 Single Tone <47:40> Phase Offset Word<15:8> 0x00 (0x11) <39:32> Phase Offset Word<7:0> 0x00 <31:24> Frequency Tuning Word<31:24> 0x00 <23:16> Frequency Tuning Word<23:16> 0x00 <15:8> Frequency Tuning Word<15:8> 0x00 <7:0> Frequency Tuning Word<7:0> 0x00 Profile 3 <63:56> CCI Interpolation Rate<7:2> Spectral Inverse CCI 0x00 Register— Invert Bypass QDUC <55:48> Output Scale Factor<7:0> 0x00 (0x11) <47:40> Phase Offset Word<15:8> 0x00 <39:32> Phase Offset Word<7:0> 0x00 <31:24> Frequency Tuning Word<31:24> 0x00 <23:16> Frequency Tuning Word<23:16> 0x00 <15:8> Frequency Tuning Word<15:8> 0x00 <7:0> Frequency Tuning Word<7:0> 0x00 Rev. C | Page 52 of 64 Data Sheet AD9957 Table 16. Profile 4, Profile 5, and Profile 6 Registers Register Bit Name Range (Serial (Internal Default Address) Address) Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Value Profile 4 <63:56> Open Amplitude Scale Factor<13:8> 0x00 Register— <55:48> Amplitude Scale Factor<7:0> 0x00 Single Tone <47:40> Phase Offset Word<15:8> 0x00 (0x12) <39:32> Phase Offset Word<7:0> 0x00 <31:24> Frequency Tuning Word<31:24> 0x00 <23:16> Frequency Tuning Word<23:16> 0x00 <15:8> Frequency Tuning Word<15:8> 0x00 <7:0> Frequency Tuning Word<7:0> 0x00 Profile 4 <63:56> CCI Interpolation Rate<7:2> Spectral Invert Inverse CCI Bypass 0x00 Register— <55:48> Output Scale Factor<7:0> 0x00 QDUC <47:40> Phase Offset Word<15:8> 0x00 (0x12) <39:32> Phase Offset Word<7:0> 0x00 <31:24> Frequency Tuning Word<31:24> 0x00 <23:16> Frequency Tuning Word<23:16> 0x00 <15:8> Frequency Tuning Word<15:8> 0x00 <7:0> Frequency Tuning Word<7:0> 0x00 Profile 5 <63:56> Open Amplitude Scale Factor<13:8> 0x00 Register— <55:48> Amplitude Scale Factor<7:0> 0x00 Single Tone <47:40> Phase Offset Word<15:8> 0x00 (0x13) <39:32> Phase Offset Word<7:0> 0x00 <31:24> Frequency Tuning Word<31:24> 0x00 <23:16> Frequency Tuning Word<23:16> 0x00 <15:8> Frequency Tuning Word<15:8> 0x00 <7:0> Frequency Tuning Word<7:0> 0x00 Profile 5 <63:56> CCI Interpolation Rate<7:2> Spectral Invert Inverse CCI Bypass 0x00 Register— <55:48> Output Scale Factor<7:0> 0x00 QDUC <47:40> Phase Offset Word<15:8> 0x00 (0x13) <39:32> Phase Offset Word<7:0> 0x00 <31:24> Frequency Tuning Word<31:24> 0x00 <23:16> Frequency Tuning Word<23:16> 0x00 <15:8> Frequency Tuning Word<15:8> 0x00 <7:0> Frequency Tuning Word<7:0> 0x00 Profile 6 <63:56> Open Amplitude Scale Factor<13:8> 0x00 Register— <55:48> Amplitude Scale Factor<7:0> 0x00 Single Tone <47:40> Phase Offset Word<15:8> 0x00 (0x14) <39:32> Phase Offset Word<7:0> 0x00 <31:24> Frequency Tuning Word<31:24> 0x00 <23:16> Frequency Tuning Word<23:16> 0x00 <15:8> Frequency Tuning Word<15:8> 0x00 <7:0> Frequency Tuning Word<7:0> 0x00 Profile 6 <63:56> CCI Interpolation Rate<7:2> Spectral Invert Inverse CCI Bypass 0x00 Register— <55:48> Output Scale Factor<7:0> 0x00 QDUC <47:40> Phase Offset Word<15:8> 0x00 (0x14) <39:32> Phase Offset Word<7:0> 0x00 <31:24> Frequency Tuning Word<31:24> 0x00 <23:16> Frequency Tuning Word<23:16> 0x00 <15:8> Frequency Tuning Word<15:8> 0x00 <7:0> Frequency Tuning Word<7:0> 0x00 Rev. C | Page 53 of 64 AD9957 Data Sheet Table 17. Profile 7, RAM, GPIO Configuration, and GPIO Data Registers Bit Range Register Name (Internal Bit 7 Bit 0 Default (Serial Address) Address) (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) Value Profile 7 <63:56> Open Amplitude Scale Factor<13:8> 0x00 Register— <55:48> Amplitude Scale Factor<7:0> 0x00 Single Tone <47:40> Phase Offset Word<15:8> 0x00 (0x15) <39:32> Phase Offset Word<7:0> 0x00 <31:24> Frequency Tuning Word<31:24> 0x00 <23:16> Frequency Tuning Word<23:16> 0x00 <15:8> Frequency Tuning Word<15:8> 0x00 <7:0> Frequency Tuning Word<7:0> 0x00 Profile 7 <63:56> CCI Interpolation Rate<7:2> Spectral Inverse CCI 0x00 Register— Invert Bypass QDUC (0x15) <55:48> Output Scale Factor<7:0> 0x00 <47:40> Phase Offset Word<15:8> 0x00 <39:32> Phase Offset Word<7:0> 0x00 <31:24> Frequency Tuning Word<31:24> 0x00 <23:16> Frequency Tuning Word<23:16> 0x00 <15:8> Frequency Tuning Word<15:8> 0x00 <7:0> Frequency Tuning Word<7:0> 0x00 RAM Register <31:0> RAM Word<31:0> (0x16) GPIO <15:0> GPIO Configuration<15:0> 0x00 Configuration Register (0x18) GPIO Data <15:0> GPIO Data<15:0> 0x00 Register (0x19) Rev. C | Page 54 of 64 Data Sheet AD9957 The following section provides a detailed description of each bit REGISTER BIT DESCRIPTIONS in the AD9957 register map. For cases in which a group of bits The serial I/O port registers span an address range of 0 to 25 serve a specific function, the entire group is considered as a (0x00 to 0x19 in hexadecimal notation). This represents a total binary word and described in aggregate. of 26 registers. However, six of these registers are unused, yielding a total of 20 available registers. The unused registers are 7, 8, 11 This section is organized in sequential order of the serial to 13, and 23 (0x07 to 0x08, 0x0B to 0x0D, and 0x17). addresses of the registers. Following each subheading are the individual bit descriptions for that particular register. The The number of bytes assigned to the registers varies. That is, the location of the bit(s) in the register are indicated by or registers are not of uniform depth; each contains the number , where A and B are bit numbers. The notation, , of bytes necessary for its particular function. Additionally, the specifies a range of bits from most significant to least significant registers are assigned names according to their functionality. bit position. For example, <5:2> means bit positions 5 down to In some cases, a register is given a mnemonic descriptor. For 2, inclusive, with Bit 0 identifying the LSB of the register. example, the register at Serial Address 0x00 is named Control Function Register 1 and is assigned the mnemonic CFR1. Unless otherwise stated, programmed bits are not transferred to their internal destinations until the assertion of an I/O update or profile change. Control Function Register 1 (CFR1) Address 0x00, four bytes are assigned to this register. Table 18. Bit Descriptions for CFR1 Register Bit (s) Mnemonic Description 31 RAM Enable 0: disables RAM playback functionality (default). 1: enables RAM playback functionality. 30:29 Open 28 RAM Playback Ineffective unless CFR1<31> = 1. Destination 0: RAM playback data routed to baseband scaling multipliers (default). 1: RAM playback data routed to baseband I/Q data path. 27:26 Open 25:24 Operating Mode 00: quadrature modulation mode (default). 01: single tone mode. 1x: interpolating DAC mode. 23 Manual OSK Ineffective unless CFR1<9:8> = 10b. External Control 0: OSK pin inoperative (default). 1: OSK pin enabled for manual OSK control (see the Output Shift Keying (OSK) section). 22 Inverse Sinc Filter 0: inverse sinc filter bypassed (default). Enable 1: inverse sinc filter active. 21 Clear CCI This bit is automatically cleared by the serial I/O port controller. This operation requires several internal clock cycles to complete, during which time the data supplied to the CCI input by the baseband signal chain is ignored. The inputs are forced to all zeros to flush the CCI data path, after which the CCI accumulators are reset. 0: normal operation of the CCI filter (default). 1: initiates an asynchronous reset of the accumulators in the CCI filter. 20:17 Open 16 Select DDS Sine Ineffective unless CFR1<25:24> = 01b. Output 0: cosine output of the DDS is selected (default). 1: sine output of the DDS is selected. 15:14 Open 13 Autoclear Phase 0: normal operation of the DDS phase accumulator (default). Accumulator 1: synchronously resets the DDS phase accumulator any time I/O_UPDATE is asserted or a profile change occurs. 12 Open 11 Clear Phase 0: normal operation of the DDS phase accumulator (default). Accumulator 1: asynchronous, static reset of the DDS phase accumulator. 10 Load ARR @ I/O 0: normal operation of the OSK amplitude ramp rate timer (default). Update 1: OSK amplitude ramp rate timer reloaded any time I/O_UPDATE is asserted or a profile change occurs. Rev. C | Page 55 of 64 AD9957 Data Sheet Bit (s) Mnemonic Description 9 OSK (Output Shift 0: OSK disabled (default). Keying) Enable 1: OSK enabled. 8 Select Auto-OSK Ineffective unless CFR1<9> = 1. 0: manual OSK enabled (default). 1: automatic OSK enabled. 7 Digital Power- This bit is effective without the need for an I/O update. Down 0: clock signals to the digital core are active (default). 1: clock signals to the digital core are disabled. 6 DAC Power-Down 0: DAC clock signals and bias circuits are active (default). 1: DAC clock signals and bias circuits are disabled. 5 REFCLK Input This bit is effective without the need for an I/O update. Power-Down 0: REFCLK input circuits and PLL are active (default). 1: REFCLK input circuits and PLL are disabled. 4 Auxiliary DAC 0: auxiliary DAC clock signals and bias circuits are active (default). Power-Down 1: auxiliary DAC clock signals and bias circuits are disabled. 3 External Power- 0: assertion of the EXT_PWR_DWN pin affects full power-down (default). Down Control 1: assertion of the EXT_PWR_DWN pin affects fast recovery power-down. 2 Auto Power-Down Ineffective when CFR1<25:24> = 01b. Enable 0: disable power-down (default). 1: when the TxEnable pin is Logic 0, the baseband signal processing chain is flushed of residual data and the clocks are automatically stopped. Clocks restart when the TxENABLE pin is a Logic 1. 1 SDIO Input Only 0: configures the SDIO pin for bidirectional operation; 2-wire serial programming mode (default). 1: configures the serial data I/O pin (SDIO) as an input only pin; 3-wire serial programming mode. 0 LSB First 0: configures the serial I/O port for MSB first format (default). 1: configures the serial I/O port for LSB first format. Control Function Register 2 (CFR2) Address 0x01, four bytes are assigned to this register. Table 19. Bit Descriptions for CFR2 Register Bit (s) Mnemonic Description 31 Blackfin Interface Valid only when CFR1<25:24> = 00b (quadrature modulation mode). Mode Active 0: Pin D<17:0> configured as an 18-bit parallel port (default). 1: Pin D<5:4> configured as a dual serial port compatible with the Blackfin serial interface. Pin D<17:6> and Pin D<3:0> become available as a 16-bit GPIO port. 30 Blackfin Bit Order Valid only when CFR2<31> = 1. 0: the dual serial port (BFI) configured for MSB first operation (default). 1: the dual serial port (BFI) configured for LSB first operation. 29 Blackfin Early Valid only when CFR2<31> = 1. Frame Sync 0: the dual serial port (BFI) configured to be compatible with Blackfin late frame sync operation (default). Enable 1: the dual serial port (BFI) configured to be compatible with Blackfin early frame sync operation. 28:25 Open 24 Enable Profile Valid only when CFR1<25:24> = 01b (single tone mode) and CFR1<9>=0 (OSK disabled). Registers as ASF 0: amplitude scale factor bypassed (unity gain). Source 1: the active profile register determines the amplitude scale factor. 23 Internal I/O This bit is effective without the need for an I/O update. Update Active 0: serial I/O programming is synchronized with external assertion of the I/O_UPDATE pin, which is configured as an input pin (default). 1: serial I/O programming is synchronized with an internally generated I/O update signal (the internally generated signal appears at the I/O_UPDATE pin, which is configured as an output pin). 22 SYNC_CLK Enable 0: the SYNC_CLK pin is disabled; static Logic 0 output. 1: the SYNC_CLK pin generates a clock signal at ¼ fSYSCLK; use of synchronization of the serial I/O port (default). Rev. C | Page 56 of 64 Data Sheet AD9957 Bit (s) Mnemonic Description 21:17 Open 16 Read Effective 0: a serial I/O port read operation of the FTW register reports the contents of the FTW register (default). FTW 1: a serial I/O port read operation of the FTW register reports the actual 32-bit word appearing at the input to the DDS phase accumulator. 15:14 I/O Update Rate Ineffective unless CFR2<23> = 1. Sets the prescale ratio of the divider that clocks the I/O update timer as Control follows: 00: divide-by-1 (default). 01: divide-by-2. 10: divide-by-4. 11: divide-by-8. 13 PDCLK Rate Ineffective unless CFR2<31> = 0 and CFR1<25:24> = 00b. Control 0: PDCLK operates at the input data rate (default). 1: PDCLK operates at ½ the input data rate; useful for maintaining a consistent relationship between I/Q words at the parallel data port and the internal clocks of the baseband signal processing chain. 12 Data Format 0: the data-words applied to Pin D<17:0> are expected to be coded as twos complement (default). 1: the data-words applied to Pin D<17:0> are expected to be coded as offset binary. 11 PDCLK Enable 0: the PDCLK pin is disabled and forced to a static Logic 0 state; the internal clock signal continues to operate and provide timing to the data assembler. 1: the internal PDCLK signal appears at the PDCLK pin (default). 10 PDCLK Invert 0: normal PDCLK polarity; Q-data associated with Logic 1, I-data with Logic 0 (default). 1: inverted PDCLK polarity. 9 TxEnable Invert 0: normal TxENABLE polarity; Logic 0 is standby, Logic 1 is transmit (default). 1: inverted TxENABLE polarity; Logic 0 is transmit, Logic 1 is standby. 8 Q-First Data 0: an I/Q data pair is delivered as I-data first, followed by Q-data (default). Pairing 1: an I/Q data pair is delivered as Q-data first, followed by I-data. 7 Open 6 Data Assembler Ineffective when CFR1<25:24> = 01b. Hold Last Value 0: when the TxENABLE pin is false, the data assembler ignores the input data and internally forces zeros on the baseband signal path (default). 1: when the TxENABLE pin is false, the data assembler ignores the input data and internally forces the last value received on the baseband signal path. 5 Sync Timing 0: enables the setup and hold validation circuit to take a measurement; the measurement result appears at Validation Disable the SYNC_SMP_ERR pin; a Logic 1 at this pin indicates a potential setup/hold violation whereas a Logic 0 indicates that a setup/hold violation has not been detected; the measurement result is latched and held until this bit is set to a Logic 1. 1: resets the setup and hold validation measurement circuit forcing the SYNC_SMP_ERR pin to a static Logic 0 condition (default); the measurement circuit is effectively disabled until this bit is restored to a Logic 0 state. 4:0 Open Rev. C | Page 57 of 64 AD9957 Data Sheet Control Function Register 3 (CFR3) Address 0x02, four bytes are assigned to this register. Table 20. Bit Descriptions for CFR3 Register Bit (s) Mnemonic Description 31:30 Open 29:28 DRV0 Controls REFCLK_OUT pin (see Table 6 for details); default is 01b. 27 Open 26:24 VCO SEL Selects frequency band of the VCO in the REFCLK PLL (see Table 7 for details); default is 111b. 23:22 Open 21:19 I Selects the charge pump current in the REFCLK PLL (see Table 8 for details); default is 111b. CP 18:16 Open 15 0: input divider is selected (default). REFCLK Input Divider Bypass 1: input divider is bypassed. 14 REFCLK Input Divider 0: input divider is reset. ResetB 1: input divider operates normally (default). 13:9 Open 8 PLL Enable 0: REFCLK PLL bypassed (default). 1: REFCLK PLL enabled. 7:1 N This 7-bit number is divide modulus of the REFCLK PLL feedback divider; default is 0000000b. 0 Open Auxiliary DAC Control Register Address 0x03, four bytes are assigned to this register. Table 21. Bit Descriptions for Auxiliary DAC Control Register Bit(s) Mnemonic Description 31:8 Open 7:0 FSC This 8-bit number controls the full-scale output current of the main DAC (see the Auxiliary DAC section); default is 0xFF. I/O Update Rate Register Address 0x04, four bytes are assigned to this register. This register is effective without the need for an I/O update. Table 22. Bit Descriptions for I/O Update Rate Register5 Bit(s) Mnemonic Description 31:0 I/O Update Rate Ineffective unless CFR2<23> = 1. This 32-bit number controls the automatic I/O update rate (see the Automatic I/O Update section); default is 0xFFFFFFFF. RAM Segment Register 0 Address 0x05, six bytes are assigned to this register. This register is effective without the need for an I/O update. This register is only active if CFR1<31> = 1 and there is a Logic 0-to-Logic 1 transition on the RT pin. Table 23. Bit Descriptions for RAM Segment Register 0 Bit(s) Mnemonic Description 47:32 RAM Address Step This 16-bit number controls the rate at which the RAM state machine steps through the specified RAM Rate 0 address range. 31:22 RAM End Address 0 This 10-bit number identifies the ending address for the RAM state machine. 21:16 Open 15:6 RAM Start Address 0 This 10-bit number identifies the starting address for the RAM state machine. 5:3 Open 2:0 RAM Playback Mode 0 This 3-bit number identifies the playback mode for the RAM state machine (see Table 5). Rev. C | Page 58 of 64 Data Sheet AD9957 RAM Segment Register 1 Address 0x06, six bytes are assigned to this register. This register is only active if CFR1<31> = 1 and there is a Logic 1 to Logic 0 transition on the RT pin. Table 24. Bit Descriptions for RAM Segment Register 1 Bit(s) Mnemonic Description 47:32 RAM Address Step This 16-bit number controls the rate at which the RAM state machine steps through the specified RAM Rate 1 address range. 31:22 RAM End Address 1 This 10-bit number identifies the ending address for the RAM state machine. 21:16 Open 15:6 RAM Start Address 1 This 10-bit number identifies the starting address for the RAM state machine. 5:3 Open 2:0 RAM Playback Mode 1 This 3-bit number identifies the playback mode for the RAM state machine (see Table 5). Amplitude Scale Factor (ASF) Register Address 0x09, four bytes are assigned to this register. This register is only active if CFR1<9> = 1. Table 25. Bit Descriptions for ASF Register Bit(s) Mnemonic Description 31:16 Amplitude Ramp Rate Ineffective unless CFR1<8> = 1. This 16-bit number controls the rate at which the OSK controller updates amplitude changes to the DDS. 15:2 Amplitude Scale Factor If CFR1<8> = 0 and CFR1<23> = 0, then this 14-bit number is the amplitude scale factor for the DDS. If CFR1<8> = 0 and CFR1<23> = 1, then this 14-bit number is the amplitude scale factor for the DDS when the OSK pin is Logic 1. If CFR1<8> = 1, then this 14-bit number sets a ceiling on the maximum allowable amplitude scale factor for the DDS. 1:0 Amplitude Step Size Ineffective unless CFR1<8> = 1. This 2-bit number controls the step size for amplitude changes to the DDS (see Table 9). Multichip Sync Register Address 0x0A, four bytes are assigned to this register. Table 26. Bit Descriptions for the Multichip Sync Register Bit(s) Mnemonic Description 31:28 Sync Validation Delay Default is 0000b. This 4-bit number sets the timing skew (in ~75 ps increments) between SYSCLK and the delayed sync-in signal for the synchronization validation block in the synchronization receiver. 27 Sync Receiver Enable 0: synchronization clock receiver disabled (default). 1: synchronization clock receiver enabled. 26 Sync Generator Enable 0: synchronization clock generator disabled (default). 1: synchronization clock generator enabled. 25 Sync Generator Polarity 0: synchronization clock generator coincident with the rising edge of the system clock (default). 1: synchronization clock generator coincident with the falling edge of the system clock. 24 Open 23:18 Sync State Preset Value Default is 000000b. This 6-bit number is the state that the internal clock generator assumes when it receives a sync pulse. 17:16 Open 15:11 Sync Generator Delay Default is 00000b. This 5-bit number sets the output delay (in ~75 ps increments) of the synchronization generator. 10:8 Open 7:3 Sync Receiver Delay Default is 00000b. This 5-bit number sets the delay input delay (in ~75 ps increments) of the synchronization receiver. 2:0 Open Rev. C | Page 59 of 64 AD9957 Data Sheet QDUC profiles control: DDS frequency (32 bits), DDS phase PROFILE REGISTERS offset (16 bits), output amplitude scaling (8 bits), CCI filter There are eight consecutive serial I/O addresses (0x0E to 0x15) interpolation factor, inverse CCI bypass, and spectral invert. dedicated to device profiles. All eight profile registers are either The QDUC profiles also selectively apply to the interpolating single tone profiles or QDUC profiles depending on the device operating mode specified by CFR1<25:24>. During operation, DAC operating mode: only output scaling, CCI filter interpola- the active profile register is determined via the external tion factor, and inverse CCI bypass apply; all others (DDS PROFILE<2:0> pins. frequency, output amplitude scaling, and spectral invert) are ignored. Single tone profiles control: DDS frequency (32 bits), DDS phase offset (16 bits), and DDS amplitude scaling (14 bits). Profile<7:0> Register—Single Tone Address 0x0E to 0x15, eight bytes are assigned to this register. Table 27. Bit Descriptions for Profile<7:0> Registers—Single Tone Bit(s) Mnemonic Description 63:62 Open 61:48 Amplitude Scale Factor This 14-bit number controls the DDS output amplitude. 47:32 Phase Offset Word This 16-bit number controls the DDS phase offset. 31:0 Frequency Tuning Word This 32-bit number controls the DDS frequency. Profile<7:0> Register—QDUC Address 0x0E to 0x15, eight bytes are assigned to this register. Table 28. Bit Descriptions for Profile<7:0> Registers—QDUC Bit(s) Mnemonic Description 63:58 CC Interpolation Rate This 6-bit number is the rate interpolation factor for the CCI filter. 57 Spectral Invert 0: the modulator output takes the form: I(t) × cos(ct) – Q(t) × sin(ct). 1: the modulator output takes the form: I(t) × cos(ct) + Q(t) × sin(ct). 56 Inverse CCI Bypass 0: the inverse CCI filter is enabled. 1: the inverse CCI filter is bypassed. 55:48 Output Scale Factor This 8-bit number controls the output amplitude. 47:32 Phase Offset Word This 16-bit number controls the DDS phase offset. 31:0 Frequency Tuning Word This 32-bit number controls the DDS frequency. RAM Register Address 0x16, four bytes are assigned to this register. Table 29. Bit Descriptions for RAM Register Bit(s) Mnemonic Description 31:0 RAM Word The number of 32-bit words written to RAM is defined by the start and end address in RAM Segment Register 0 or RAM Segment Register 1. GPIO Configuration Register Address 0x18, two bytes are assigned to this register. Table 30. Bit Descriptions for GPIO Configuration Register Bit(s) Mnemonic Description 15:0 GPIO Configuration See the General-Purpose I/O (GPIO) Port section for details. GPIO Data Register Address 0x19, two bytes are assigned to this register. Table 31. Bit Descriptions for GPIO Data Register Bits Mnemonic Description 15:0 GPIO Data Read or write based on the contents of the GPIO Configuration register. See the General-Purpose I/O (GPIO) Port section for details. Rev. C | Page 60 of 64 Data Sheet AD9957 OUTLINE DIMENSIONS 16.00 BSC SQ 1.20 0.75 MAX 0.60 14.00 BSC SQ 0.45 76 76 100 100 1 75 75 1 PIN 1 EXPOSED 5.00 SQ TOP VIEW PAD (PINS DOWN) 0° MIN 1.05 0.20 BOTTOM VIEW 1.00 (PINS UP) 0.09 51 51 25 25 0.95 7° 26 50 50 26 3.5° VIEW A 0.50 BSC 0.27 0.15 0° SEATING LEAD PITCH 0.22 0.05 0.08 MAX PLANE COPLANARITY 0.17 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO VIEW A THE PIN CONFIGURATION AND ROTATED 90° CCW FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MS-026-AED-HD Figure 65. 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] (SV-100-4) Dimensions shown in millimeters ORDERING GUIDE 1 Model Temperature Range Package Description Package Option AD9957BSVZ −40°C to +85°C 100-Lead Thin Quad Flat Package Exposed Pad [TQFP_EP] SV-100-4 AD9957BSVZ-REEL −40°C to +85°C 100-Lead Thin Quad Flat Package Exposed Pad [TQFP_EP] SV-100-4 AD9957/PCBZ Evaluation Board 1 Z = RoHS Compliant Part. Rev. C | Page 61 of 64 042209-A AD9957 Data Sheet NOTES Rev. C | Page 62 of 64 Data Sheet AD9957 NOTES Rev. C | Page 63 of 64 AD9957 Data Sheet NOTES ©2007–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06384-0-4/12(C) Rev. C | Page 64 of 64