ANALOG DEVICES AD9879

Mixed-Signal Front End Set-Top Box, Cable Modem AD9879 FUNCTIONAL BLOCK DIAGRAM FEATURES Low cost 3.3 V MxFE™ for I DOCSIS-, EURO-DOCSIS-, DVB-, DAVIC-compliant 12 –1 TX set-top box and cable modem applications TX DATA ⇑16 SINC DAC TX Q 232 MHz quadrature digital upconverter DDS 12-bit direct IF DAC (TxDAC+™) Σ-∆ Σ-∆_OUT Up to 65 MHz carrier frequency DDS CA_PORT Programmable sampling clock rates 4 16× upsampling interpolation LPF SPORT MCLK CONTROL REGISTERS PLL XM/N Single-tone frequency synthesis Analog Tx output level adjust 2 Direct cable amp interface RXI 8 RXIQ[3:0] ADC MUX MUX 2 12-bit, 33 MSPS direct IF ADC RXQ with optional video clamping input 10-bit, 33 MSPS direct IF ADC 10 ADC RX10 Dual 7-bit, 16.5 MSPS sampling I/Q ADC 12-bit Σ-∆ auxiliary DAC MUX RXIF[11:0] 12 APPLICATIONS ADC RX12 MUX Cable modem and satellite systems CLAMP VIDEO Set-top boxes AD9879 Power line modem PC multimedia Figure 1. Digital communications Data and video modems QAM, OFDM, FSK modulation GENERAL DESCRIPTION The AD9879 is a single-supply set-top box and cable modem The 12-bit and 10-bit IF ADCs can convert direct IF inputs up mixed-signal front end. The device contains a transmit path to 70 MHz and run at sample rates up to 33 MSPS. A video interpolation filter, complete quadrature digital upconverter, input with an adjustable signal clamping level, along with the and transmit DAC. The receive path contains a 12-bit ADC, a 10-bit ADC, allow the AD9879 to process an NTSC and a QAM 10-bit ADC, and dual 7-bit ADCs. All internally required clocks channel simultaneously. and an output system clock are generated by the phase-locked The programmable Σ-Δ DAC can be used to control external loop (PLL) from a single crystal or clock input. components, such as variable gain amplifiers (VGAs) or voltage The transmit path interpolation filter provides an upsampling controlled tuners. The CA port provides an interface to the factor of 16× with an output signal bandwidth as high as AD8321/AD8323 or AD8322/AD8327 programmable gain 8.3 MHz. Carrier frequencies up to 65 MHz with 26 bits of amplifier (PGA) cable drivers, enabling host processor control frequency tuning resolution can be generated by the direct via the MxFE SPORT. digital synthesizer (DDS). The transmit DAC resolution is The AD9879 is available in a 100-lead MQFP. It offers enhanced 12 bits and can run at sampling rates as high as 232 MSPS. receive path undersampling performance and lower cost when Analog output scaling from 0.0 dB to 7.5 dB in 0.5 dB steps is compared with the pin-compatible AD9873. The AD9879 is available to preserve SNR when reduced output levels are specified over the commercial (−40°C to +85°C) temperature required. range. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 www.analog.com or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved. 02773-001 AD9879 TABLE OF CONTENTS Specifications..................................................................................... 4 Serial Interface for Register Control ............................................ 20 Absolute Maximum Ratings............................................................ 7 General Operation of the Serial Interface............................... 20 Explanation of Test Levels........................................................... 7 Instruction Byte.......................................................................... 20 Thermal Characteristics .............................................................. 7 Serial Interface Port Pin Description....................................... 20 ESD Caution.................................................................................. 7 MSB/LSB Transfers .................................................................... 20 Pin Configuration and Function Descriptions............................. 8 Notes on Serial Port Operation ................................................ 21 Terminology .................................................................................... 10 Transmit Path (Tx) ......................................................................... 22 Theory of Operation ...................................................................... 11 Transmit Timing......................................................................... 22 Transmit Path.............................................................................. 11 Data Assembler........................................................................... 22 Data Assembler........................................................................... 11 Half-Band Filters (HBFs) .......................................................... 22 Interpolation Filter ..................................................................... 12 Cascaded Integrator-Comb (CIC) Filter................................. 22 Digital Upconverter.................................................................... 12 Combined Filter Response........................................................ 22 DPLL-A Clock Distribution...................................................... 12 Tx Signal Level Considerations................................................ 24 Clock and Oscillator Circuitry ................................................. 12 Tx Throughput and Latency..................................................... 24 Programmable Clock Output REFCLK................................... 13 Digital-to-Analog Converter .................................................... 25 Reset and Transmit Power-Down ............................................ 14 Programming the AD8321/AD8323 or AD8322/AD8327 Cable Driver Amplifier Gain Control..................................................... 26 Σ-Δ Outputs ................................................................................ 15 Receive Path (Rx) ........................................................................... 27 Register Map and Bit Definitions ................................................. 16 IF10 and IF12 ADC Operation ................................................ 27 Register 0x00—Initialization .................................................... 17 Input Signal Range and Digital Output Codes....................... 27 Register 0x01—Clock Configuration....................................... 17 Driving the Inputs ...................................................................... 27 Register 0x02—Power-Down.................................................... 17 PCB Design Considerations.......................................................... 28 Registers 0x03–0x04—Σ-Δ and Flag Control......................... 17 Component Placement .............................................................. 28 Register 0x07—Video Input Configuration............................ 17 Power Planes and Decoupling .................................................. 28 Register 0x08—ADC Clock Configuration ............................ 18 Ground Planes ............................................................................ 29 Register 0x0C—Die Revision.................................................... 18 Signal Routing............................................................................. 29 Register 0x0D—Tx Frequency Tuning Words LSBs.............. 18 Outline Dimensions ....................................................................... 30 Register 0x0E—DAC Gain Control ......................................... 18 Ordering Guide .......................................................................... 30 Register 0x0F—Tx Path Configuration................................... 18 Registers 0x10–0x17—Carrier Frequency Tuning................. 19 Rev. A | Page 2 of 32 AD9879 REVISION HISTORY 6/05—Rev. 0 to Rev. A Updated Format.................................................................. Universal Changed OSCOUT to REFCLK....................................... Universal Changed REF CLK to REFCLK........................................ Universal Changes to Specifications Section................................................... 4 Changes to Figure 13 ......................................................................21 Changes to Equation 18..................................................................24 Changes to Equation 21..................................................................24 Changes to Outline Dimensions ...................................................30 Changes to Ordering Guide...........................................................30 8/02—Revision 0: Initial Version Rev. A | Page 3 of 32 AD9879 SPECIFICATIONS VAS = 3.3 V ± 5%, VDS = 3.3 V ± 10%, fOSCIN = 27 MHz, fSYSCLK = 216 MHz, fMCLK = 54 MHz (M = 8), ADC clock from OSCIN, RSET = 4.02 kΩ, 75 Ω DAC load, unless otherwise noted. Table 1. Parameter Temp Test Level Min Typ Max Unit OSCIN AND XTAL CHARACTERISTICS Frequency Range Full II 3 29 MHz Duty Cycle Full II 35 50 65 % Input Impedance 25°C III 100||3 MΩ||pF MCLK Cycle to Cycle Jitter 25°C III 6 ps rms Tx DAC CHARACTERISTICS Resolution N/A N/A 12 Bits Maximum Sample Rate Full II 232 MHz Full-Scale Output Current Full II 4 10 20 mA Gain Error (Using Internal Reference) 25°C I −2.0 −1.0 +2.0 % FS Offset Error 25°C I ±1.0 % FS Reference Voltage (REFIO Level) 25°C I 1.18 1.23 1.28 V Differential Nonlinearity (DNL) 25°C III ±2.5 LSB Integral Nonlinearity (INL) 25°C III ±8 LSB Output Capacitance 25°C III 5 pF Phase Noise @ 1 kHz Offset, 42 MHz Crystal and OSCIN Multiplier Enabled at 16× 25°C III −110 dBc/Hz Output Voltage Compliance Range Full II −0.5 +1.5 V Wideband SFDR 5 MHz Analog Out, I = 10 mA Full III 60.8 66.9 dBc OUT 65 MHz Analog Out, I = 10 mA Full III 44.0 46.2 dBc OUT Narrow-band SFDR (±1 MHz Window) 5 MHz Analog Out, IOUT = 10 mA Full III 65.4 72.3 dBc Tx MODULATOR CHARACTERISTICS I/Q Offset Full II 50 55 dB Pass-Band Amplitude Ripple (f < fIQCLK/8) Full II ±0.1 dB Pass-Band Amplitude Ripple (f < f /4) Full II ±0.5 dB IQCLK Stop-Band Response (f > f × 3/4) Full II −63 dB IQCLK Tx GAIN CONTROL Gain Step Size 25°C III 0.5 dB Gain Step Error 25°C III <0.05 dB Settling Time to 1% (Full-Scale Step) 25°C III 1.8 µs IQ ADC CHARACTERISTICS 1 Resolution N/A N/A 6 Bits Maximum Conversion Rate Full II 14.5 MHz Pipeline Delay N/A N/A 3.5 ADC cycles Offset Matching Between I and Q ADCs Full III ±4.0 LSBs Gain Matching Between I and Q ADCs Full III ±2.0 LSBs Analog Input 1 Input Voltage Range Full III 1 Vppd Input Capacitance 25°C III 2.0 pF Differential Input Resistance 25°C III 4 kΩ AC Performance (AIN = 0.5 dBFS, fIN = 5 MHz) Effective Number of Bits (ENOB) 25°C I 5.00 5.8 Bits Signal-to-Noise Ratio (SNR) 25°C I 34.7 36.5 dB Total Harmonic Distortion (THD) 25°C I −50 −36.2 dB Spurious-Free Dynamic Range (SFDR) 25°C I 41.3 51 dB Rev. A | Page 4 of 32 AD9879 Parameter Temp Test Level Min Typ Max Unit 10-BIT ADC CHARACTERISTICS Resolution N/A N/A 10 Bits Maximum Conversion Rate Full II 29 MHz Pipeline Delay N/A N/A 4.5 ADC cycles Analog Input Input Voltage Range Full III 2.0 Vppd Input Capacitance 25°C III 2 pF Differential Input Resistance 25°C II 4 kΩ Reference Voltage Error (REFT10–REFB10) –1 V Full I ±4 ±200 mV AC Performance (A = –0.5 dBFS, f = 5 MHz) IN IN ADC Sample Clock Source = OSCIN Signal-to-Noise and Distortion (SINAD) Full II 58.3 59.9 dB Effective Number of Bits (ENOB) Full II 9.4 9.65 Bits Signal-to-Noise Ratio (SNR) Full II 58.6 60 dB Total Harmonic Distortion (THD) Full II −73 −62 dB Spurious-Free Dynamic Range (SFDR) Full II 65.7 76 dB AC Performance (AIN = −0.5 dBFS, fIN = 50 MHz) ADC Sample Clock Source = OSCIN Signal-to-Noise and Distortion (SINAD) Full II 57.7 59.0 dB Effective Number of Bits (ENOB) Full II 9.29 9.51 Bits Signal-to-Noise Ratio (SNR) Full II 57.8 59.1 dB Total Harmonic Distortion (THD) Full II −61.4 −75 dB Spurious-Free Dynamic Range (SFDR) Full II 64 78 dB 12-BIT ADC CHARACTERISTICS Resolution N/A N/A 12 Bits Maximum Conversion Rate Full II 29 MHz Pipeline Delay N/A N/A 5.5 ADC cycles Analog Input Input Voltage Range Full III 2 Vppd Input Capacitance 25°C III 2 pF Differential Input Resistance 25°C III 4 kΩ Reference Voltage Error (REFT12–REFB12) −1 V Full I ±16 ±200 mV AC Performance (A = −0.5 dBFS, f = 5 MHz) IN IN ADC Sample Clock Source = OSCIN Signal-to-Noise and Distortion (SINAD) Full II 60.0 65.2 dB Effective Number of Bits (ENOB) Full II 9.67 10.53 Bits Signal-to-Noise Ratio (SNR) Full II 60.3 65.6 dB Total Harmonic Distortion (THD) Full II −76.6 −58.7 dB Spurious-Free Dynamic Range (SFDR) Full II 64.7 79 dB AC Performance (A = −0.5 dBFS, f = 50 MHz) IN IN ADC Sample Clock Source = OSCIN Signal-to-Noise and Distortion (SINAD) Full II 59.5 62.7 dB Effective Number of Bits (ENOB) Full II 9.59 10.1 Bits Signal-to-Noise Ratio (SNR) Full II 59.7 63.0 dB Total Harmonic Distortion (THD) Full II −75.5 −60.5 dB Spurious-Free Dynamic Range (SFDR) Full II 63.8 79 dB VIDEO CLAMP PERFORMANCE (A = −0.5 dBFS, f = 5 MHz) IN ADC Sample Clock = OSCIN Signal-to-Noise and Distortion (SINAD) Full II 43.9 50.6 dB Effective Number of Bits (ENOB) Full II 7.0 8.1 Bits Rev. A | Page 5 of 32 AD9879 Parameter Temp Test Level Min Typ Max Unit Signal-to-Noise Ratio (SNR) Full II 46.2 57.2 Bits Total Harmonic Distortion (THD) Full II −50.1 −44.5 dB Spurious-Free Dynamic Range (SFDR) Full II 44.9 53.4 dB CHANNEL-TO-CHANNEL ISOLATION Tx DAC-to-ADC Isolation (AOUT = 5 MHz) Isolation Between Tx and IQ ADCs 25°C III >60 dB Isolation Between Tx and 10-Bit ADC 25°C III >80 dB Isolation Between Tx and 12-Bit ADC 25°C III >80 dB ADC-to-ADC (AIN = –0.5 dBFS, f = 5 MHz) Isolation Between IF10 and IF12 ADCs 25°C III >85 dB Isolation Between Q and I Inputs 25°C III >50 dB TIMING CHARACTERISTICS (10 pF Load) Minimum RESET Pulse Width Low (tRL) N/A N/A 5 tMCLK cycles Digital Output Rise/Fall Time Full II 2.8 4 ns Tx/Rx Interface MCLK Frequency (f ) Full II 66 MHz MCLK TxSYNC/TxIQ Setup Time (t ) Full II 3 ns SU TxSYNC/TxIQ Hold Time (tHD) Full II 3 ns MCLK Rising Edge to RxSYNC/RxIQ/IF Valid Delay (tMD) Full II 0 1.0 ns REFCLK Rising or Falling Edge to RxSYNC/RxIQ/IF Valid Delay (t ) Full II T /4 – 2.0 T /4 + 3.0 ns OD OSC OSC REFCLK Edge to MCLK Falling Edge (tEE) Full II −1.0 +1.0 ns Serial Control Bus Maximum SCLK Frequency (fSCLK) Full II 15 MHz Minimum Clock Pulse Width High (t ) Full II 30 ns PWH Minimum Clock Pulse Width Low (t ) Full II 30 ns PWL Maximum Clock Rise/Fall Time Full II 1 ms Minimum Data/Chip-Select Setup Time (tDS) Full II 25 ns Minimum Data Hold Time (tDH) Full II 0 ns Maximum Data Valid Time (tDV) Full II 30 ns CMOS LOGIC INPUTS Logic 1 Voltage 25°C II VDRVDD – 0.7 V Logic 0 Voltage 25°C II 0.4 V Logic 1 Current 25°C II 12 µA Logic 0 Current 25°C II 12 µA Input Capacitance 25°C II 3 pF CMOS LOGIC OUTPUTS (1 mA Load) Logic 1 Voltage 25°C II V – 0.6 V DRVDD Logic 0 Voltage 25°C II 0.4 V POWER SUPPLY Supply Current, I (Full Operation) 25°C II 163 184 mA S Analog Supply Current, IAS 25°C III 95 mA Digital Supply Current, IDS 25°C III 68 mA Supply Current, IS Standby (PWRDN Pin Active) 25°C II 119 126 mA Full Power-Down (Register 0x02 = 0xF9) 25°C III 16 mA Power-Down Tx Path (Register 0x02 = 0x60) 25°C III 113 mA Power-Down Rx Path (Register 0x02 = 0x19) 25°C III 110 mA 1 IQ ADC in default mode. ADC Clock Select Register 8, Bit 3 set to 0. Rev. A | Page 6 of 32 AD9879 ABSOLUTE MAXIMUM RATINGS Table 2. EXPLANATION OF TEST LEVELS Parameter Rating I Devices are 100% production tested at +25°C and Power Supply (V ,V ,V ) 3.9 V AVDD DVDD DRVDD guaranteed by design and characterization testing for Digital Output Current 5 mA commercial operating temperature range (−40ºC to Digital Inputs −0.3 V to V + 0.3 V DRVDD +85°C). Analog Inputs −0.3 V to VAVDD + 0.3 V Operating Temperature −40°C to +85°C II Parameter is guaranteed by design and/or Maximum Junction Temperature 150°C characterization testing. Storage Temperature −65°C to +150°C III Parameter is a typical value only. Lead Temperature (Soldering, 10 sec) 300°C Stresses above those listed under Absolute Maximum Ratings N/A Test level definition is not applicable. may cause permanent damage to the device. This is a stress THERMAL CHARACTERISTICS rating only and functional operation of the device at these or any other conditions above those indicated in the operational Thermal Resistance section of this specification is not implied. Exposure to absolute 100-Lead MQFP maximum rating conditions for extended periods may affect θ = 40.5°C/W JA device reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. A | Page 7 of 32 AD9879 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 80 DNC DNC PIN 1 DRGND 2 79 I+ DRVDD 3 78 I– IF(11) 4 77 DNC IF(10) 5 76 DNC 6 75 IF(9) DNC 7 74 IF(8) AGNDIQ IF(7) 8 73 AVDDIQ 9 72 IF(6) DRVDD 10 71 IF(5) REFCLK 11 70 IF(4) DRGND AD9879 12 69 IF(3) DGND Σ-∆ TOP VIEW 13 68 IF(2) (Pins Down) Σ-∆_OUT 14 67 IF(1) FLAG1 15 66 IF(0) DVDD Σ-∆ 16 65 RXIQ(3) CA_EN 17 64 RXIQ(2) CA_DATA RXIQ(1) 18 63 CA_CLK RXIQ(0) 19 62 DVDDOSC RXSYNC 20 61 OSCIN DRGND 21 60 XTAL DRVDD 22 59 DGNDOSC 23 58 MCLK AGNDPLL 24 57 DVDD PLLFILT 25 56 DGND AVDDPLL TXSYNC 26 55 DVDDPLL 27 54 TXIQ(5) DGNDPLL 28 53 TXIQ(4) AVDDTX 29 52 TXIQ(3) TX+ 30 51 TXIQ(2) TX– Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No. Mnemonic Description 1, 35, 75 to 77, 80 DNC Do Not Connect. Pins are not bonded to die. 2, 21, 70 DRGND Pin Driver Digital Ground. 3, 22, 72 DRVDD Pin Driver Digital 3.3 V Supply. 4 to 15 IF[11:0] 12-Bit ADC Digital Output. 16 to 19 RXIQ[3:0] Muxed I and Q ADCs Output. 20 RXSYNC Sync Output, IF, I and Q ADCs. 23 MCLK Master Clock Output. 24, 33, 38 DVDD Digital 3.3 V Supply. 25, 34, 39, 40 DGND Digital Ground. 26 TXSYNC Sync Input for Transmit Port. 27 to 32 TXIQ[5:0] Digital Input for Transmit Port. 36 PROFILE Profile Selection Inputs. 37 RESET Chip Reset Input (Active Low). Rev. A | Page 8 of 32 TXIQ(1) 31 100 VIDEO IN TXIQ(0) 32 99 AGND DVDD 33 98 IF12+ DGND 34 97 IF12– 96 DNC 35 AGND 95 PROFILE 36 AVDD RESET 37 94 REFT12 38 93 DVDD REFB12 92 DGND 39 AVDD 40 DGND 91 AGND 41 90 SCLK IF10+ 42 CS 89 IF10– 43 SDIO 88 AGND 44 87 SDO AVDD DGNDTX 45 86 REFT10 46 85 DVDDTX REFB10 47 84 PWRDN AVDD 48 83 REFIO AGND 49 82 FSADJ Q+ 50 81 AGNDTX Q– 02773-002 AD9879 Pin No. Mnemonic Description 41 SCLK SPORT Clock. 42 CS SPORT Chip Select. 43 SDIO SPORT Data I/O. 44 SDO SPORT Data Output. 45 DGNDTX Tx Path Digital Ground. 46 DVDDTX Tx Path Digital 3.3 V Supply. 47 PWRDN Power-Down Transmit Path. 48 REFIO TxDAC Decoupling (to AGND). 49 FSADJ DAC Output Adjust (External Resistor). 50 AGNDTX Tx Path Analog Ground. 51, 52 TX−, TX+ Tx Path Complementary Outputs. 53 AVDDTX Tx Path Analog 3.3 V Supply. 54 DGNDPLL PLL Digital Ground. 55 DVDDPLL PLL Digital 3.3 V Supply. 56 AVDDPLL PLL Analog 3.3 V Supply. 57 PLLFILT PLL Loop Filter Connection. 58 AGNDPLL PLL Analog Ground. 59 DGNDOSC Oscillator Digital Ground. 60 XTAL Crystal Oscillator Inverted Output. 61 OSCIN Oscillator Clock Input. 62 DVDDOSC Oscillator Digital 3.3 V Supply. 63 CA_CLK Serial Clock to Cable Driver. 64 CA_DATA Serial Data to Cable Driver. 65 CA_EN Serial Enable to Cable Drive. 66 DVDD Σ-∆ Σ-∆ Digital 3.3 V Supply. 67 FLAG1 Digital Output Flag 1. 68 Σ-∆_OUT Σ-∆ DAC Output. 69 DGND Σ-∆ Σ-∆ Digital Ground. 71 REFCLK Programmable Reference Clock Output. 73 AVDDIQ 7-Bit ADCs Analog 3.3 V Supply. 74 AGNDIQ 7-Bit ADCs Analog Ground. 78, 79 I−, I+ Differential Input to I ADC. 81, 82 Q−, Q+ Differential Input to Q ADC. 83, 88, 91, 96, 99 AGND 12-Bit ADC Analog Ground. 84, 87, 92, 95 AVDD 12-Bit ADC Analog 3.3 V Supply. 85 REFB10 10-Bit ADC Decoupling Node. 86 REFT10 10-Bit ADC Decoupling Node. 89, 90 IF10−, IF10+ Differential Input to 10-Bit ADC. 93 REFB12 12-Bit ADC Decoupling Node. 94 REFT12 12-Bit ADC Decoupling Node. 97, 98 IF12−, IF12+ Differential Input to IF ADC. 100 VIDEO IN Video Clamp Input, 12-Bit ADC. Rev. A | Page 9 of 32 AD9879 TERMINOLOGY Aperture Delay Offset Error The aperture delay is a measure of the sample-and-hold First transition should occur for an analog value 1/2 LSB amplifier (SHA) performance. It specifies the time delay above −FS. Offset error is defined as the deviation of the actual between the rising edge of the sampling clock input and when transition from that point. the input signal is held for conversion. Output Compliance Range Aperture Uncertainty (Jitter) The range of allowable voltage at the output of a current-output Aperture jitter is the variation in aperture delay for successive DAC. Operation beyond the maximum compliance limits can samples. It is manifested as noise on the input to the ADC. cause either output stage saturation or break down, resulting in nonlinear performance. Channel-to-Channel Isolation (Crosstalk) In an ideal multichannel system, the signal in one channel does Phase Noise not influence the signal level of another channel. The channel- Single-sideband phase noise power is specified relative to the to-channel isolation specification is a measure of the change carrier (dBc/Hz) at a given frequency offset (1 kHz) from the that occurs to a grounded channel as a full-scale signal is carrier. Phase noise can be measured directly in single-tone applied to another channel. transmit mode with a spectrum analyzer that supports noise marker measurements. It detects the relative power between the Differential Nonlinearity Error (DNL, No Missing Codes) carrier and the offset (1 kHz) sideband noise and takes the An ideal converter exhibits code transitions that are exactly 1 LSB resolution bandwidth (RBW) into account by subtracting apart. DNL is the deviation from this ideal value. Guaranteed 10 log(RBW). It also adds a correction factor that compensates no missing codes to 10-bit resolution indicates that all 1,024 for the implementation of the resolution bandwidth, log display, codes, respectively, must be present over all operating ranges. and detector characteristic. Effective Number of Bits (ENOB) Pipeline Delay (Latency) For a sine wave, SINAD can be expressed in terms of the Pipeline delay is the number of clock cycles between conversion number of bits. Using the formula initiation and the availability of the associated output data. N = (SINAD − 1.76 dB∕6.02) Power Supply Rejection it is possible to determine a measure of performance expressed Power supply rejection specifies the converter’s maximum full- as N, the effective number of bits. Thus, the effective number of scale change when the supplies are varied from nominal to bits for a device’s sine wave inputs at a given input frequency minimum and maximum specified voltages. can be calculated directly from its measured SINAD. Signal-to-Noise and Distortion (SINAD) Ratio Gain Error SINAD is the ratio of the rms value of the measured input The first code transition should occur at an analog value signal to the rms sum of all other spectral components below 1/2 LSB above full scale. The last transition should occur for an the Nyquist frequency, including harmonics but excluding dc. analog value 1 1/2 LSB below the nominal full scale. Gain error The value for SINAD is expressed in decibels. is the deviation of the actual difference between the first and Signal-to-Noise Ratio (SNR) last code transitions and the ideal difference between the first SNR is the ratio of the rms value of the measured input signal to and last code transitions. the rms sum of all other spectral components below the Nyquist Input Referred Noise frequency, excluding harmonics and dc. The value for SNR is The rms output noise is measured using histogram techniques. expressed in decibels. The standard deviation of the ADC output code is calculated in Spurious-Free Dynamic Range (SFDR) LSB and converted to an equivalent voltage. This results in a SFDR is the difference, in dB, between the rms amplitude of the noise figure that can be directly referred to the input of the MxFE. DAC output signal (or the ADC input signal) and the peak Integral Nonlinearity Error (INL) spurious signal over the specified bandwidth (Nyquist Linearity error refers to the deviation of each individual code bandwidth, unless otherwise noted). from a line drawn from negative full scale through the positive Total Harmonic Distortion (THD) full scale. The point used as the negative full scale occurs THD is the ratio of the rms sum of the first six harmonic 1/2 LSB before the first code transition. Positive full scale is components to the rms value of the measured input signal, and defined as a level 1 1/2 LSB beyond the last code transition. The is expressed as a percentage or in decibels. deviation is measured from the middle of each code to the true straight line. Rev. A | Page 10 of 32 — AD9879 THEORY OF OPERATION To gain a general understanding of the AD9879, refer to the The transmit DAC resolution is 12 bits and can run at sampling block diagram of the device architecture in Figure 3. The rates as high as 232 MSPS. Analog output scaling from 0.0 dB device consists of a transmit path, receive path, and auxiliary to 7.5 dB in 0.5 dB steps is available to preserve SNR when functions, such as a DPLL, a Σ-Δ DAC, a serial control port, reduced output levels are required. and a cable amplifier interface. DATA ASSEMBLER TRANSMIT PATH The AD9879 data path operates on two 12-bit words, the I and The transmit path contains an interpolation filter, a complete Q components, which compose a complex symbol. The data quadrature digital upconverter, an inverse sinc filter, and a assembler builds the 24-bit complex symbols from four 12-bit current output DAC. The maximum output current of consecutive 6-bit nibbles read over the TxIQ[5:0] bus. The the DAC is set by an external resistor. The Tx output PGA nibbles are strobed synchronous to the master clock, MCLK, provides additional transmit signal level control. into the data assembler. A high level on TxSYNC signals the start of a transmit symbol. The first two nibbles of the symbol The transmit path interpolation filter provides an upsampling form the I component, and the second two nibbles form the Q factor of 16 with an output signal bandwidth as high as component. Symbol components are assumed to be in twos 5.8 MHz. Carrier frequencies up to 65 MHz with 26 bits of complement format. The timing of the interface is fully frequency tuning resolution can be generated by the direct described in the Transmit Timing section of this data sheet. digital synthesizer (DDS). AD9879 QUADRATURE MODULATOR DAC GAIN CONTROL FSADJ DATA FIR LPF CIC LPF ASSEMBLER –1 SINC COS 6 12 12 BYPASS TXIQ I 4 4 12 TX MUX DAC –1 — SINC 12 12 TXSYNC Q 4 4 (f ) SYSCLK SIN (f ) OSCIN DDS (f ) IQCLK PLL ÷4 XTAL OSCIN × M MCLK (f ) MCLK REFCLK ÷R ÷4 OSCIN 12 Σ-∆ INPUT REGISTER Σ-∆ Σ-∆_OUT 3 CA CA_PORT INTERFACE ÷8 PROFILE PROFILE SELECT FLAG1 4 SERIAL ÷2 ÷2 SPORT INTERFACE (f ) OSCIN 7 ADC I INPUT 4 RXIQ[3:0] IQ MUX 7 Q INPUT ADC RXPORT RXSYNC ÷2 (f ) OSCIN 10 IF10 INPUT ADC 12 IF[11:0] MUX IF IF12 INPUT 12 ADC MUX VIDEO INPUT + – CLAMP LEVEL DAC Figure 3. Block Diagram Rev. A | Page 11 of 32 02773-003 AD9879 External loop filter components consisting of a series resistor INTERPOLATION FILTER (1.3 kΩ) and capacitor (0.01 µF) provide the compensation zero Once through the data assembler, the IQ data streams are fed for the OSCIN multiplier PLL loop. The overall loop through a 4× FIR low-pass filter and a 4× cascaded integrator- performance has been optimized for these component values. comb (CIC) low-pass filter. The combination of these two filters results in the sample rate increasing by a factor of 16. DPLL-A CLOCK DISTRIBUTION In addition to the sample rate increase, the half-band filters Figure 3 shows the clock signals used in the transmit path. The provide the low-pass filtering characteristic necessary to DAC sampling clock, f , is generated by DPLL-A. F has a DAC DAC suppress the spectral images between the original sampling frequency equal to L × fOSCIN, where fOSCIN is the internal signal frequency and the new (16× higher) sampling frequency. generated by either the crystal oscillator when a crystal is connected between the OSCIN and XTAL pins or the clock that DIGITAL UPCONVERTER is fed into the OSCIN pin, and L is the multiplier programmed The digital quadrature modulator stage following the CIC filters through the serial port. L can have the values of 1, 2, 3, or 8. is used to frequency shift (upconvert) the baseband spectrum of The transmit path expects a new half word of data at the rate of the incoming data stream up to the desired carrier frequency. f . When the Tx multiplexer is enabled, the frequency of The carrier frequency is controlled numerically by a direct CLK-A Tx Port is digital synthesizer (DDS). The DDS uses the internal system clock (f ) to generate the desired carrier frequency with a SYSCLK fCLK−A = 2 × fDA/K = 2 × L × fOSCIN/K (1) high degree of precision. The carrier is applied to the I and Q multipliers in quadrature fashion (90° phase offset) and where K is the interpolation factor. summed to yield a data stream that is the modulated carrier. The interpolation factor can be programmed to be 1, 2, or 4. The modulated carrier becomes the 12-bit sample sent to the DAC. When the Tx multiplexer is disabled, the frequency of the The receive path contains a 12-bit ADC, a 10-bit ADC, and a Tx Port is dual 7-bit ADC. All internally required clocks and an output f = f /K = L × f /K (2) system clock are generated by the PLL from a single crystal or CLK−A DAC OSCIN clock input. Receive Section The 12-bit and 10-bit IF ADCs can convert direct IF inputs up The AD9879 includes two high speed, high performance ADCs. to 70 MHz and run at sample rates up to 33 MSPS. A video The 10-bit and 12-bit direct IF ADCs deliver excellent under- input with an adjustable signal clamping level along with the sampling performance with input frequencies as high as 70 MHz. 10-bit ADC allow the AD9879 to process an NTSC and a QAM The sampling rate can be as high as 33 MSPS. channel simultaneously. The ADC sampling frequency can be derived directly from the The programmable Σ-Δ DAC can be used to control external OSCIN signal or from the on-chip OSCIN multiplier. For components, such as variable gain amplifiers (VGAs) or voltage highest dynamic performance, it is advisable to choose an controlled tuners. The CA_PORT provides an interface to the OSCIN frequency that can be directly used as the ADC AD8321/AD8323 or AD8322/AD8327 programmable gain sampling clock. Digital IQ ADC outputs are multiplexed to one amplifier (PGA) cable drivers, enabling host processor control 4-bit bus, clocked by a frequency (fMCLK) of four times the via the MxFE SPORT. sampling rate. The IF ADCs use a multiplexed 12-bit interface with an output word rate of f . MCLK OSCIN Clock Multiplier The AD9879 can accept either an input clock into the OSCIN CLOCK AND OSCILLATOR CIRCUITRY pin or a fundamental mode XTAL across the OSCIN pin and The internal oscillator of the AD9879 generates all sampling XTAL pins as the device’s main clock source. The internal PLL clocks from a simple, low cost, parallel resonance, fundamental then generates the f signal from which all other internal SYSCLK frequency quartz crystal. Figure 4 shows how the quartz crystal signals are derived. is connected between OSCIN (Pin 61) and XTAL (Pin 60) with parallel resonant load capacitors as specified by the crystal The DAC uses fSYSCLK as its sampling clock. For DDS manufacturer. The internal oscillator circuitry can also be applications, the carrier is typically limited to about 30% of overdriven by a TTL-level clock applied to OSCIN with XTAL fSYSCLK. For a 65 MHz carrier, the system clock required is above left unconnected. 216 MHz. fOSCIN = fMCLK × M (3) The OSCIN multiplier function maintains clock integrity, as evidenced by the excellent phase noise characteristics and low clock-related spur in the output spectrum of the AD9879’s systems. Rev. A | Page 12 of 32 AD9879 An internal PLL generates the DAC sampling frequency, f , Figure 3 shows that ADCs are either sampled directly by a low SYSCLK by multiplying OSCIN frequency M times. The MCLK signal jitter clock at OSCIN or by a clock that is derived from the PLL (Pin 23), f , is derived by dividing f by 4. output. Operating modes can be selected in Register 0x08. MCLK SYSCLK Sampling the ADCs directly with the OSCIN clock requires fSYSCLK = fOSCIN × M (4) MCLK to be programmed to be twice the OSCIN frequency. fMCLK = fOSCIN × M/4 (5) PROGRAMMABLE CLOCK OUTPUT REFCLK An external PLL loop filter (Pin 57) consisting of a series The AD9879 provides an auxiliary output clock on Pin 71, resistor and ceramic capacitor (Figure 18, R1 = 1.3 kΩ, REFCLK. The value of the MCLK divider bit field, R, C12 = 0.01 µF) is required for stability of the PLL. Also, a shield determines its output frequency as shown: surrounding these components is recommended to minimize fREFCLK = fMCLK/R, for R = 2 − 3 (6) external noise coupling into the PLL’s voltage controlled oscillator input (guard trace connected to AVDDPLL). fREFCLK = fOSCIN/R, for R = 0 (7) In its default setting (0x00 in Register 0x01), the REFCLK pin provides a buffered output of f . OSCIN CP1 CP2 10µF 10µF C1 C3 C4 C5 C6 C2 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 1 80 DNC DNC PIN 1 DRGND 2 79 I+ 3 78 DRVDD I– 4 77 (MSB) IF(11) DNC IF(10) 5 76 DNC 6 75 IF(9) DNC 7 74 IF(8) AGNDIQ IF(7) 8 73 AVDDIQ 9 72 IF(6) DRVDD IF(5) 10 71 REFCLK IF(4) 11 70 DRGND AD9879 12 69 IF(3) DGND Σ-∆ TOP VIEW IF(2) 13 68  (Pins Down) Σ-∆_OUT IF(1) 14 67 FLAG1 15 66 IF(0) DVDD Σ-∆ (MSB) RXIQ(3) 16 65 CA_EN 17 RXIQ(2) 64 CA_DATA C10 20pF 18 63 RXIQ(1) CA_CLK RXIQ(0) 19 62 DVDDOSC C11 20 61 RXSYNC OSCIN 20pF 21 60 DRGND XTAL DRVDD 22 59 DGNDOSC GUARD TRACE 23 58 MCLK AGNDPLL R1 C12 24 57 DVDD PLLFILT 1.3kΩ 0.01µF DGND 25 56 AVDDPLL 26 55 TXSYNC DVDDPLL 27 54 (MSB) TXIQ(5) DGNDPLL TXIQ(4) 28 53 AVDDTX 29 52 TXIQ(3) TX+ 30 51 TXIQ(2) TX– C13 R 0.1µF SET 4.02kΩ Figure 4. Basic Connection Diagram Rev. A | Page 13 of 32 31 100 TXIQ(1) VIDEO IN TXIQ(0) 32 99 AGND DVDD 33 98 IF12+ 34 97 DGND IF12– 35 96 DNC AGND PROFILE 36 95 AVDD RESET 37 94 REFT12 38 93 REFB12 DVDD 39 92 AVDD DGND DGND 40 91 AGND 41 90 SCLK IF10+ 42 89 IF10– CS SDIO 43 88 AGND 44 SDO 87 AVDD 45 86 DGNDTX REFT10 DVDDTX 46 85 REFB10 PWRDN 47 84 AVDD 48 83 REFIO AGND FSADJ 49 82 Q+ AGNDTX 50 81 Q– 02773-004 AD9879 A software reset (writing a 1 into Bit 5 of Register 0x00) is RESET AND TRANSMIT POWER-DOWN functionally equivalent to the hardware reset but does not force Power-Up Sequence Register 0x00 to its default value. On initial power-up, the pin should be held low until RESET V S the power supply is stable. Once RESET is deasserted, the AD9879 can be programmed RESET over the serial port. The on-chip PLL requires a maximum of 1ms MIN 1 millisecond after the rising edge of or a change of the RESET 5 MCLK PWRDN MIN multiplier factor (M) to completely settle. It is recommended Figure 5. Power-Up Sequence for Tx Data Path that the PWRDN pin be held low during the reset and PLL settling time. Changes to ADC Clock Select (Register 0x08) or Transmit Power-Down SYS Clock Divider N (Register 0x01) should be programmed before the rising edge of PWRDN. A low level on the PWRDN pin stops all clocks linked to the digital transmit data path and resets the CIC filter. Deasserting Once the PLL is frequency locked and after the pin is PWRDN PWRDN reactivates all clocks. The CIC filter is held in a reset brought high, transmit data can be sent reliably. state for 80 MCLK cycles after the rising edge of PWRDN to allow for flushing of the half-band filters with new input data. If the PWRDN pin cannot be held low throughout the reset and PLL settling time period, the power-down digital Tx bit or the Transmit data bursts should be padded with at least 20 symbols pin should be pulsed after the PLL has settled. This PWRDN of null data directly before the PWRDN pin is deasserted. will ensure correct transmit filter initialization. Immediately after the pin is deasserted, the transmit PWRDN burst should start with a minimum of 20 null data symbols. RESET This avoids unintended DAC output samples caused by the To initiate a hardware reset, the pin should be held low RESET transmit path latency and filter settling time. for at least 100 nanoseconds. All internally generated clocks stop during reset. The rising edge of RESET resets the PLL clock Software Power-Down Digital Tx (Bit 5 in Register 02x00) is functionally equivalent to the hardware pin and takes multiplier and reinitializes the programmable registers to their PWRDN default values. The same sequence as described in the Power-Up effect immediately after the last register bit has been written Sequence section should be followed after a reset or change in M. over the serial port. PWRDN 5MCLK MIN DATA SYMBOLS 20 NULL SYMBOLS 20 NULL SYMBOLS TXIQ 00 0 0 0 0 0 0 TXSYNC Figure 6. Timing Sequence to Flush Tx Data Path Rev. A | Page 14 of 32 02773-006 02773-005 AD9879 Σ-∆ OUTPUTS The AD9879 contains an on-chip Σ-Δ output that provides a In set-top box and cable modem applications, the output can be digital logic bit stream with an average duty cycle that varies used to control external variable gain amplifiers or RF tuners. A between 0% and (4095/4096)%, depending on the programmed simple single-pole RC low-pass filter provides sufficient code, as shown in Figure 7. filtering (see Figure 8). This bit stream can be low-pass filtered to generate a In more demanding applications where additional gain, level programmable dc voltage of shift, or drive capability is required, a first or second order active filter might be considered for each Σ-Δ output (see Figure 9). VDC = (Σ-Δ Code/4096)(VH) + VL (8) where: VH = VDRVDD − 0.6 V VL = 0.4 V 8 t 4096 × 8 t MCLK MCLK 0x000 0x001 DAC AD9879 12 R CONTROL Σ-∆ DC (V TO V ) L H 0x002 WORD C 0x800 MCLK ÷8 0xFFF TYPICAL: R = 50kΩ C = 0.1µF 8 t 4096 × 8 t MCLK MCLK f = 1/(2πRC) = 318Hz –3dB Figure 7. Σ-∆ Output Signals Figure 8. Σ-∆ RC Filter C R1 R AD9879 V OUT R Σ-∆ OP250 V SD C R SIGMA-DELTA V = (V + V ) (1 + R/R1)/2 OUT SD OFFSET V OFFSET TYPICAL: R = 50kΩ C = 0.1µF f = 1/(2πRC) = 318Hz –3dB Figure 9. Σ-∆ Active Filter with Gain and Offset Rev. A | Page 15 of 32 02773-007 02773-009 02773-008 AD9879 REGISTER MAP AND BIT DEFINITIONS 1 Table 4. Register Map Address Default (hex) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (hex) Type 0x00 RESET OSCIN Multiplier M[4:0] 0x08 Read/Write SDIO SPI Bytes Bidirectional LSB First 0x01 PLL Lock MCLK/REFCLK Ratio R[5:0] 0x00 Read/Write Detect 0x02 Power- Power- Power- Power- Power-Down Power- Power- Power- 0x00 Read/Write Down PLL Down Down Down Reference Down Down Down IQ DAC Tx Digital IF12 IF12 ADC IF10 ADC Reference ADC Tx ADC IQ and IF10 ADC 0x03 Σ-∆ Output Control Word [3:0] Flag 1 Flag 0 0x00 Read/Write Enable 0x04 Flag 0 Σ-∆ Output Control Word [11:4] 0x00 Read/Write 0x05 0 0 0 0 0 0 0 0 0x00 Read/Write 0x06 0 0 0 0 0 0 0 0 0x00 Read Only 0x07 Clamp Level for Video Input [6:0] 0x00 Read/Write Video Input Enable 0x08 ADCs 0 Rx Port Power- Enable 7-Bits 0 Send Send 0x80 Read/Write Clocked Fast Down IQ ADC 12-Bit 10-Bit Direct from Edge RxSYNC ADC Data ADC OSCIN Rate and IQ Only Data ADC Only Clocks 0x09 0 0 0 0 0 0 0 0 0x00 Read/Write 0x0A 0 0 0 0 0 0 0 0 0x00 Read/Write 0x0B 0 0 0 0 0 0 0 0 0x00 Read/Write 0x0C 0 0 0 0 Version [3:0] 0x05 Read/Write 0x0D 0 0 0 0 Tx Frequency Tuning Word Tx Frequency Tuning 0x00 Read/Write Profile 1 LSBs [1:0] Word Profile 0 LSBs [1:0] 0x0E 0 0 0 0 DAC Fine Gain Control [3:0] 0x00 Read/Write 0x0F 0 0 Tx Path 0 Tx Path Tx Path Tx Path Tx Path 0x00 Read/Write Select AD8322/ Bypass Spectral Transmit -1 Profile 1 AD8327 Gain Sinc Inversion Single Control Mode Filter Tone 0x10 Tx Path Frequency Tuning Word Profile 0 [9:2] 0x00 Read/Write 0x11 Tx Path Frequency Tuning Word Profile 0 [17:10] 0x00 Read/Write 0x12 Tx Path Frequency Tuning Word Profile 0 [25:18] 0x00 Read/Write 0x13 Cable Driver Amplifier Coarse Gain Control Profile 0 [7:4] Fine Gain Control Profile 0 [3:0] 0x00 Read/Write 0x14 Tx Path Frequency Tuning Word Profile 1 [9:2] 0x00 Read/Write 0x15 Tx Path Frequency Tuning Word Profile 1 [17:10] 0x00 Read/Write 0x16 Tx Path Frequency Tuning Word Profile 1 [25:18] 0x00 Read/Write 0x17 Cable Driver Amplifier Coarse Gain Control Profile 1 [7:4] Fine Gain Control Profile 1 [3:0] 0x00 Read/Write 1 Register bits denoted with 0 must be programmed with a 0 each time that register is written. Rev. A | Page 16 of 32 AD9879 REGISTER 0x02—POWER-DOWN REGISTER 0x00—INITIALIZATION Sections of the chip that are not used can be powered down Bits 0–4: OSCIN Multiplier when the corresponding bits are set high. This register has a This register field is used to program the on-chip multiplier default value of 0x00, with all sections active. (PLL) that generates the chip’s high frequency system clock f . The value of M depends on the ADC clocking mode SYSCLK Bit 0: Power-Down IQ ADC selected, as shown in Table 5. Active high powers down the IQ ADC. Table 5. Bit 1: Power-Down IQ and IF10 ADC Reference ADC Clock Select M Active high powers down the IQ and IF10 ADC reference. 1, f 8 OSCIN 0, fMCLK (PLL Derived) 16 Bit 2: Power-Down IF10 ADC When using the AD9879 in systems where the Tx path and Rx Active high powers down the IF10 ADC. path do not operate simultaneously, the value of M can be programmed from 1 to 31. The maximum fSYSCLK rate of Bit 3: Power-Down IF12 ADC Reference 236 MHz must be observed, whatever value is chosen for M. Active high powers down the 12-bit ADC reference. When M is set to 1, the internal PLL is disabled and all internal Bit 4: Power-Down IF12 ADC clocks are derived directly from OSCIN. Active high powers down the IF12 ADC. RESET Bit 5: Bit 5: Power-Down Digital TX Writing a 1 to this bit resets the registers to their default values and restarts the chip. The RESET bit always reads back 0. The Active high powers down the digital transmit section of the bits in Register 0x00 are not affected by this software reset. A PWRDN chip, similar to the function of the pin. RESET low level at the pin, however, would force all registers, Bit 6: Power-Down DAC TX including all bits in Register 0x00, to their default state. Active high powers down the DAC. Bit 6: SPI Bytes LSB First Bit 7: Power-Down PLL Active high indicates SPI serial port access of instruction byte Active high powers down the OSCIN multiplier. and data registers are least significant bit (LSB) first. Default low indicates most significant bit (MSB) first format. REGISTERS 0x03–0x04—Σ-∆ AND FLAG CONTROL Bit 7: SDIO Bidirectional The Σ-Δ control word is 12 bits wide and split into MSB bits Active high configures the serial port as a three-signal port with [11:4] and LSB bits [3:0]. Changes to the Σ-Δ control words take the SDIO pin used as a bidirectional input/output pin. Default effect immediately for every MSB or LSB register write. Σ-Δ low indicates the serial port uses four signals with SDIO output control words have a default value of 0. The control configured as an input and SDO configured as an output. words are in straight binary format with 0x000 corresponding to the bottom of the scale and 0xFFF corresponding to the top REGISTER 0x01—CLOCK CONFIGURATION of the scale. See Figure 8 for details. Bits 0–5: MCLK/REFCLK Ratio If the flag enable (Register 0x03, Bit 0) is set high, the This bit field defines R, the ratio between the auxiliary clock Σ-Δ_OUT pin maintains a fixed logic level determined output, REFCLK and MCLK. R can be any integer number directly by the MSB of the Σ-Δ control word. between 2 and 63. At default zero (R = 0), REFCLK provides a buffered version of the OSCIN clock signal. The FLAG1 pin assumes the logic level programmed into the FLAG1 bit (Register 0x03, Bit 1). Bit 7: PLL Lock Detect REGISTER 0x07—VIDEO INPUT CONFIGURATION When this bit is set low, the REFCLK pin functions in its default mode and provides an output clock with frequency f /R, as MCLK Bits 0–6: Clamp Level Control Value described above. The 7-bit clamp level control value is used to set an offset to the automatic clamp level control loop. The actual ADC output has If this bit is set to 1, the REFCLK pin is configured to indicate a clamp level offset equal to 16 times the clamp level control whether the PLL is locked to f . In this mode, the REFCLK OSCIN value as shown: pin should be low-pass filtered with an RC filter of 1.0 kΩ and 0.1 µF. A low output on REFCLK indicates the PLL has achieved Clamp Level Offset = Clamp Level Control Value × 16 (9) lock with fOSCIN. Rev. A | Page 17 of 32 AD9879 The default value for the clamp level control value is 0x20. This REGISTER 0x0E—DAC GAIN CONTROL results in an ADC output clamp level offset of 512 LSBs. The Bits 0–3: DAC Fine Gain Control valid programming range for the clamp level control value is This bit field sets the DAC gain if the Tx Path AD8321/AD8323 from 0x16 to 0x127. gain control select bit (Register F, Bit 3) is set to 0. The DAC gain can be set from 0.0 dB to 7.5 dB in increments of 0.5 dB. REGISTER 0x08—ADC CLOCK CONFIGURATION Table 6 details the programming. Bit 0: Send 10-Bit ADC Data Only Table 6. DAC Gain Control When this bit is set high, the device enters a nonmultiplexed Bits [3:0] DAC Gain mode and only the data from the 10-bit ADC is sent to the IF 0000 0.0 dB (default) [11:0] digital output port. 0001 0.5 dB Bit 1: Send 12-Bit ADC Data Only 0010 1.0 dB 0011 1.5 dB When this bit is set high, the device enters a nonmultiplexed .... .... mode and only data from the 12-bit ADC is sent to the IF [11:0] 1110 7.0 dB digital output port. 1111 7.5 dB Bit 3: Enable 7-Bits, IQ ADC REGISTER 0x0F—Tx PATH CONFIGURATION When this bit is active, the IQ ADC is put into 7-bit mode. In Bit 0: Single-Tone Tx Mode this mode, the full-scale input range is 2 Vppd. When this bit is Active high configures the AD9879 for single-tone applications set inactive, the IQ ADC is put into 6-bit mode and the full- such as FSK. The AD9879 supplies a single frequency output as scale input voltage range is 1 Vppd. determined by the frequency tuning word selected by the active Bit 4: Power-Down RXSYNC and IQ ADC Clocks profile. In this mode, the TXIQ input data pins are ignored but Setting this bit to 1 powers down the IQ ADC’s sampling clock should be tied to a valid logic voltage level. The default value is and stops the RXSYNC output pin. It can be used for additional 0 (inactive). power saving on top of the power-down selections in Register 0x02. Bit 1: Spectral Inversion Tx Bit 5: Rx Port Fast Edge Rate When set to 1, inverted modulation is performed. Setting this bit to 1 increases the output drive strength of all MODULATOR_OUT = [I cos(ωt) + Q sin(ωt)] (10) digital output pins, except MCLK, REFCLK, Σ-Δ_OUT, and FLAG1. These pins always have high output drive capability. The default is logic low, noninverted modulation. Bit 7: ADC Clocked Direct from OSCIN MODULATOR_OUT = [I cos(ωt) + Q sin(ωt)] (11) When set high, the input clock at OSCIN is used directly as the –1 Bit 2: Tx Path Bypass Sinc Filter ADC sampling clock. When set low, the internally generated master clock, MCLK, is divided by two and used as the ADC Setting this bit high bypasses the digital inverse sinc filter of the sampling clock. Best ADC performance is achieved when the Tx path. ADCs are sampled directly from f using an external crystal OSCIN Bit 3: Tx Path AD8322/AD8327 Gain Control Mode or low jitter crystal oscillator. This bit changes the manner in which transmit gain control is REGISTER 0x0C—DIE REVISION performed. Typically either AD8321/AD8323 (default 0) or AD8222/AD8327 (default 1) variable gain cable drivers are Bits 0–3: Version programmed over the chip’s 3-wire CA interface. The Tx gain The die version of the chip can be read from this register. control select changes the interpretation of the bits in Registers 0x13 and 0x17. See the Cable Driver Gain Control REGISTER 0x0D—Tx FREQUENCY TUNING WORDS section. LSBs This register accommodates two LSBs for both frequency tuning words. For more information, see the description in the Registers 0X10–0X17—Carrier Frequency Tuning section. Rev. A | Page 18 of 32 AD9879 Table 7. Cable Driver Gain Control Bit 5: Tx Path Select Profile 1 Bits [7:4] CA Interface Transmit Word The AD9879 quadrature digital upconverter is capable of 0000 0000 0000 (default) storing two preconfigured modulation modes called profiles. 0001 0000 0001 Each profile defines a transmit frequency tuning word and cable ... ... driver amplifier gain (DAC gain) setting. The profile select bit 0111 0100 0000 or PROFILE pin programs the current register profile to be 1000 1000 0000 used. The profile select bit should always be 0 if the PROFILE In this mode, the lower bits determine the fine gain setting of pin is to be used to switch between profiles. Using the profile the DAC output. select bit as a means of switching between different profiles requires the PROFILE pin to be tied low. Table 8. DAC Output Fine Gain Setting Bits [3:0] DAC Fine Gain REGISTERS 0x10–0x17—CARRIER FREQUENCY 0000 0.0 dB (default) TUNING 0001 0.5 dB Tx Path Frequency Tuning Words ... ... The frequency tuning word (FTW) determines the DDS- 1110 7.0 dB generated carrier frequency (f ) and is formed via a C 1111 7.5 dB concatenation of register addresses. New data is automatically sent over the 3-wire CA interface (and DAC gain adjust) whenever the value of the active gain The 26-bit FTW is spread over four register addresses. Bit 25 is control register changes or a new profile is selected. The default the MSB and Bit 0 is the LSB. value is 0x00 (lowest gain). The carrier frequency equation is given as The formula for the combined output level calculation of the 26 fc = [FTW × f ]/2 (12) SYSCLK AD9879 fine gain and AD8327 or AD8322 coarse gain is where: V8327 = V9879(0) + (fine)/2 + 6(coarse) − 19 (13) f = M × f . SYSCLK OSCIN V8322 = V9879(0) + (fine)/2 + 6(coarse) − 14 (14) FTW < 0 × 2000000. where: Changes to FTW bytes take effect immediately. fine is the decimal value of Bits [3:0]. Cable Driver Gain Control coarse is the decimal value of Bits [7:8]. V9879(0) is level at AD9879 output in dBmV for fine = 0. The AD9879 has a 3-pin interface to the AD832x family of V8327 is level at output of AD8327 in dBmV. programmable gain cable driver amplifiers. This allows direct V8322 is level at output of AD8322 in dBmV. control of the cable driver’s gain through the AD9879. In its default mode, the complete 8-bit register value is transmitted over the 3-wire cable amplifier (CA) interface. If Bit 3 of Register 0x0F is set high, Bits [7:4] determine the 8-bit word sent over the CA interface according to Table 7. Rev. A | Page 19 of 32 AD9879 SERIAL INTERFACE FOR REGISTER CONTROL Table 10. Bit Decodes The AD9879 serial port is a flexible, synchronous serial N1 N0 Description communication port that allows easy interface to many 0 0 Transfer 1 byte industry-standard microcontrollers and microprocessors. The 0 1 Transfer 2 bytes interface allows read/write access to all registers that configure 1 0 Transfer 3 bytes the AD9879. Single or multiple byte transfers are supported. 1 1 Transfer 4 bytes Also, the interface can be programmed to read words either MSB first or LSB first. The serial interface port of the AD9879 The Bits A4:A0 determine which register is accessed during the I/O can be configured to have one bidirectional I/O (SDIO) pin data transfer portion of the communication cycle. For multibyte or two unidirectional I/O (SDIO/SDO) pins. transfers, this address is the starting byte address. The remaining register addresses are generated by the AD9879. GENERAL OPERATION OF THE SERIAL INTERFACE SERIAL INTERFACE PORT PIN DESCRIPTION There are two phases to a communication cycle with the AD9879. Phase 1 is the instruction cycle, which is the writing of SCLK—Serial Clock an instruction byte into the AD9879 that is coincident with the The serial clock pin is used to synchronize data transfers from first eight SCLK rising edges. The instruction byte provides the the AD9879 and to run the serial port state machine. The AD9879 serial port controller with information regarding the maximum SCLK frequency is 15 MHz. Input data to the data transfer cycle, which is Phase 2 of the communication AD9879 is sampled upon the rising edge of SCLK. Output data cycle. The Phase 1 instruction byte defines whether the changes upon the falling edge of SCLK. upcoming data transfer is a read or write, the number of bytes in the data transfer, and the starting register address for the first CS—Chip Select byte of the data transfer. The first eight SCLK rising edges of Active low input starts and gates a communication cycle. It each communication cycle are used to write the instruction byte allows multiple devices to share a common serial port bus. The into the AD9879. SDO and SDIO pins go to a high impedance state when CS is high. Chip select should stay low during the entire communica- The eight remaining SCLK edges are for Phase 2 of the tion cycle. communication cycle. Phase 2 is the actual data transfer between the AD9879 and the system controller. Phase 2 of the SDIO—Serial Data I/O communication cycle is a transfer of 1 to 4 data bytes as deter- Data is always written into the AD9879 on this pin. However, mined by the instruction byte. Normally, using one multibyte this pin can be used as a bidirectional data line. The configura- transfer is the preferred method. However, single byte data tion of this pin is controlled by Bit 7 of Register 0x00. The transfers are useful to reduce CPU overhead when register default is Logic 0, which configures the SDIO pin as uni- access requires one byte only. Registers change immediately directional. upon writing to the last bit of each transfer byte. SDO—Serial Data Out INSTRUCTION BYTE Data is read from this pin for protocols that use separate lines Table 9 illustrates the information contained in the instruction byte. for transmitting and receiving data. When the AD9879 operates Table 9. Instruction Byte Information in a single bidirectional I/O mode, this pin does not output data MSB LSB and is set to a high impedance state. I7 I6 I5 I4 I3 I2 I1 I0 MSB/LSB TRANSFERS R/W N1 N0 A4 A3 A2 A1 A0 The AD9879 serial port can support both MSB first or LSB first The R/W bit of the instruction byte determines whether a read data formats. This functionality is controlled by the LSB-first bit or a write data transfer will occur after the instruction byte in Register 0x00. The default is MSB first. write. Logic high indicates a read operation. Logic low indicates a write operation. The N1:N0 bits determine the number of When this bit is set active high, the AD9879 serial port is in bytes to be transferred during the data transfer cycle. The bit LSB-first format. In LSB-first mode, the instruction byte and decodes are shown in Table 10. data bytes must be written from the LSB to the MSB. In LSB- first mode, the serial port internal byte address generator increments for each byte of the multibyte communication cycle. Rev. A | Page 20 of 32 AD9879 The same considerations apply to setting the reset bit in When this bit is set default low, the AD9879 serial port is in Register 0x00. All other registers are set to their default values, MSB-first format. In MSB-first mode, the instruction byte and but the software reset does not affect the bits in Register 0x00. data bytes must be written from the MSB to the LSB. In MSB- first mode, the serial port internal byte address generator It is recommended to use only single-byte transfers when decrements for each byte of the multibyte communication cycle. changing serial port configurations or initiating a software reset. When incrementing from 0x1F, the address generator changes to 0x00. When decrementing from 0x00, the address generator A write to Bits 1, 2, and 3 of Register 0x00 with the same logic changes to 0x1F. levels as Bits 7, 6, and 5 (bit pattern: XY1001YX binary) allows the user to reprogram a lost serial port configuration and to NOTES ON SERIAL PORT OPERATION reset the registers to their default values. The AD9879 serial port configuration bits reside in Bits 6 and 7 A second write to Register 0x00 with the reset bit low and the of Register 0x00. It is important to note that the configuration changes immediately upon writing to the last bit of the register. serial port configuration as specified above (XY) reprograms the OSCIN multiplier setting. A changed fSYSCLK frequency is For multibyte transfers, writing to this register may occur stable after a maximum of 200 fMCLK cycles (wake-up time). during the middle of the communication cycle. Care must be taken to compensate for this new configuration for the remaining bytes of the current communication cycle. t DS t SCLK INSTRUCTION CYCLE DATA TRANSFER CYCLE CS CS t PWH t PWL SCLK SCLK SDIO R/W N1 N0 A4 A3 A2 A1 A0 D7 D6 D2 D1 D0 t n n 0 0 0 DH t DS D7 D6 D2 D1 D0 SDO n n 0 0 0 SDIO INSTRUCTION BIT 7 INSTRUCTION BIT 6 Figure 10. Serial Register Interface Timing MSB First Figure 12. Timing Diagram for Register Write to AD9879 INSTRUCTION CYCLE DATA TRANSFER CYCLE CS CS SCLK SCLK SDIO A0 A1 A2 A3 A4 N0 N1 R/W D0 D1 D2 D6 D7 0 0 0 n n t DV SDIO D0 D1 D2 D6 D7 DATA BIT N DATA BIT N – 1 SDO 0 0 0 n n SDO Figure 11. Serial Register Interface Timing LSB First Figure 13. Timing Diagram for Register Read Rev. A | Page 21 of 32 02773-011 02773-010 02773-012 02773-013 AD9879 TRANSMIT PATH (TX) t SU MCLK t HD TXSYNC TXI[11:6] TXI[5:0] TXQ[11:6] TXQ[5:0] TXI[11:6] TXI[5:0] TXQ[11:6] TXQ[5:0] TXI[11:6] TXI[5:0] TXIQ Figure 14. Transmit Path Timing TRANSMIT TIMING CASCADED INTEGRATOR-COMB (CIC) FILTER The AD9879 provides a master clock, MCLK, and expects 6-bit The CIC filter is configured as a programmable interpolator multiplexed TxIQ data upon each rising edge. Transmit and provides a sample rate increase by a factor of 4. The symbols are framed with the TxSYNC input. TxSYNC high frequency response of the CIC filter is given by indicates the start of a transmit symbol. Four consecutive 6-bit 3 3 − j() 2πf() 4 data packages form a symbol (I MSB, I LSB, Q MSB, and Q LSB). ⎡ 1 1− e ⎤ ⎡ 1 sin() 4πf ⎤ ⎛ ⎞ ⎛ ⎞ H(f) = = (15) ⎜ ⎟ ⎜ ⎟ ⎢ ⎥ ⎢ ⎥ j( 2πf) ⎝ 4⎠ 1− e ⎝ 4⎠ sin() πf ⎣ ⎦ ⎣ ⎦ DATA ASSEMBLER The input data stream is representative complex data. Two 6-bit The frequency response in this form has f scaled to the output words form a 12-bit symbol component (in twos complement sample rate of the CIC filter. That is, f = 1 corresponds to the format). Four input samples are required to produce one I/Q frequency of the output sample rate of the CIC filter. H(f/R) data pair. The I/Q sample rate, f , at the input to the first IQCLK yields the frequency response with respect to the input sample half-band filter is a quarter of the input data rate, fMCLK. of the CIC filter. The I/Q sample rate, fIQCLK, puts a bandwidth limit on the COMBINED FILTER RESPONSE maximum transmit spectrum. This is the familiar Nyquist limit The combined frequency response of HBF 1, HBF 2, and and is equal to one-half fIQCLK, hereafter referred to as fNYQ. CIC puts a limit on the input signal bandwidth that can be propagated through the AD9879. HALF-BAND FILTERS (HBFs) HBF 1 and HBF 2 are both interpolating filters, each of which The usable bandwidth of the filter chain puts a limit on the doubles the sampling rate. Together, HBF 1 and HBF 2 have maximum data rate that can be propagated through the 26 taps and provide a factor-of-four increase in the sampling AD9879. A look at the pass-band detail of the combined filter rate (4 × f or 8 × f ). response (Figure 15 and Figure 16) indicates that to maintain an IQCLK NYQ amplitude error of no more than 1 dB, signals are restricted to a In relation to phase response, both HBFs are linear phase filters. bandwidth of no more than approximately 60% of f . NYQ As such, virtually no phase distortion is introduced within the pass band of the filters. This is an important feature, because phase distortion is generally intolerable in a data transmission system. Rev. A | Page 22 of 32 02773-014 AD9879 1 1 0 0 –1 –1 –2 –2 –3 –3 –4 –4 –5 –5 –6 –6 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 FREQUENCY RELATIVE TO I/Q NYQUIST BW FREQUENCY RELATIVE TO I/Q NYQUIST BW Figure 15. Cascaded Filter Pass-Band Detail (N = 4) Figure 16. Cascaded Filter Pass-Band Detail (N = 3) To keep the bandwidth of the data in the flat portion of the filter Thus, with 2× oversampling of the baseband data and α =1, pass band, the user must oversample the baseband data by at the Nyquist bandwidth of the data corresponds with the I/Q least a factor of two prior to representing it to the AD9879. Nyquist bandwidth. Without oversampling, the Nyquist bandwidth of the baseband As stated earlier, this results in problems near the upper edge of data corresponds to the f . Consequently, the upper end of the NYQ the data bandwidth due to the frequency response of the filters. data bandwidth suffers 6 dB or more of attenuation due to the The maximum value of α that can be implemented is 0.45. This frequency response of the digital filters. is because the data bandwidth becomes: There is an additional concern if the baseband data applied to 1 the AD9879 has been pulse shaped. Typically, pulse shaping is () 1 + α f = 0.725 f (16) NYQ NYQ 2 applied to the baseband data via a filter having a raised cosine response. In such cases, an α value is used to modify the which puts the data bandwidth at the extreme edge of the flat bandwidth of the data where the value of α is such that 0 < α < portion of the filter response. 1. A value of 0 causes the data bandwidth to correspond to the Nyquist bandwidth. A value of 1 causes the data bandwidth to If a particular application requires an α value between 0.45 and be extended to twice the Nyquist bandwidth. 1, then the user must oversample the baseband data by at least a factor of four. The combined HBF1, HBF2, and CIC filter introduces a worst-case droop of less than 0.2 dB over the frequency range of the data to be transmitted. Rev. A | Page 23 of 32 MAGNITUDE (dB) 02773-015 MAGNITUDE (dB) 02773-016 AD9879 The following example assumes a PK/rms level of 10 dB: Tx SIGNAL LEVEL CONSIDERATIONS The quadrature modulator introduces a maximum gain of 3 dB Maximum Symbol Component Input Value = (20) in signal level. To visualize this, assume that both the I data and ±(2,047 LSBs − 0.2 dB) = ±2,000 LSBs Q data are fixed at the maximum possible digital value, x. The output of the modulator, z is then: Maximum Complex Input RMS Value = (21) 2,000 LSBs + 6 dB − Pk/rms (dB) = 1,265 LSBs rms z = [x cos(ωt) – x sin(ωt)] (17) The maximum complex input rms value calculation uses both I and Q symbol components that add a factor of 2 (6 dB) to the formula. O Table 11 shows typical I-Q input test signals with amplitude XZ levels related to 12-bit full scale (FS). I X Tx THROUGHPUT AND LATENCY Data inputs impact the output fairly quickly but remain Figure 17. 16-Quadrature Modulation effective due to the filter characteristics of the AD9879. Data It can be shown that |z| assumes a maximum value of transmit latency through the AD9879 is easiest to describe in terms of fSYSCLK clock cycles (4 fMCLK). The numbers quoted are 2 2 z =() x + x = x 2(a gain of + 3 dB) (18) when an effect is first seen after an input value changes. Latency of I/Q data entering the data assembler (AD9879 input) However, if the same number of bits are used to represent the |z| to the DAC output is 119 fSYSCLK clock cycles (29.75 fMCLK cycles). values, as is used to represent the x values, an overflow occurs. DC values applied to the data assembler input takes up to 176 To prevent this possibility, an effective −3 dB attenuation is f clock cycles (44 f cycles) to propagate and settle at the SYSCLK MCLK internally implemented on the I and Q data path. DAC output. ( z =(1/2 +1/2) = x) (19) Frequency hopping is accomplished via changing the PROFILE input pin. The time required to switch from one frequency to another is less than 232 fSYSCLK cycles (58.5 fMCLK cycles). AD9879 AD832x LOW-PASS DAC TX FILTER 75Ω CA 3 CA_EN VARIABLE GAIN CA_DATA CABLE DRIVER CA_CLK AMPLIFIER Figure 18. 16-Quadrature Modulation Table 11. I–Q Input Test Signals Analog Output Digital Input Input Level Modulator Output Level Single Tone (fC – f) I = cos(f) FS – 0.2 dB FS – 3.0 dB Q = cos(f + 90°) = −sin(f) FS – 0.2 dB Single Tone (f + f) I = cos(f) FS – 0.2 dB FS – 3.0 dB C Q = cos(f + 270°) = +sin(f) FS – 0.2 dB Dual Tone (fC ± f) I = cos(f) FS – 0.2 dB FS Q = cos(f + 180°) = −cos(f) or Q = +cos(f) FS – 0.2 dB Rev. A | Page 24 of 32 02773-017 02773-018 AD9879 The load can be a simple resistor to ground, an op amp current- DIGITAL-TO-ANALOG CONVERTER to-voltage converter, or a transformer-coupled circuit. It is best A 12-bit digital-to-analog converter (DAC) is used to convert not to attempt to directly drive highly reactive loads (such as an the digitally processed waveform into an analog signal. The LC filter). worst-case spurious signals due to the DAC are the harmonics of the fundamental signal and their aliases. The conversion Driving an LC filter without a transformer requires the filter to process produces aliased components of the fundamental signal be doubly terminated for best performance. The filter input and at n × f ± f (n = 1, 2, 3). These are typically filtered output should both be resistively terminated with the appro- SYSCLK CARRIER priate values. The parallel combination of the two terminations with an external RLC filter at the DAC output. It is important determines the load the AD9879 sees for signals within the for this analog filter to have a sufficiently flat gain and linear filter pass band. For example, a 50 Ω terminated input/output phase response across the bandwidth of interest to avoid low-pass filter looks like a 25 Ω load to the AD9879. The modulation impairments. A relatively inexpensive seventh- order elliptical low-pass filter is sufficient to suppress the output compliance voltage of the AD9879 is −0.5 V to +1.5 V. aliased components for HFC network applications. To avoid signal distortion, any signal developed at the DAC output should not exceed +1.5 V. Furthermore, the signal may The AD9879 provides true and complement current outputs. extend below ground as much as 0.5 V without damage or The full-scale output current is set by the RSET resistor at Pin 49 signal distortion. and the DAC gain register. Assuming maximum DAC gain, the The AD9879 true and complement outputs can be differentially value of RSET for a particular full-scale IOUT is determined using combined for common-mode rejection using a broadband 1:1 the following equation: transformer. Using a grounded center tap results in signals at RSET = 32 VDACRSET/IOUT = 39.4/IOUT (22) the AD9879 DAC output pins that are symmetrical about ground. As previously mentioned, by differentially combining For example, if a full-scale output current of 20 mA is desired, the two signals, the user can provide some degree of common- then R = (39.4/0.02) Ω, or approximately 2 kΩ. SET mode signal rejection. A differential combiner might consist of The following equation calculates the full-scale output current a transformer or an operational amplifier. The object is to including the programmable DAC gain control. combine or amplify only the difference between two signals and to reject any common, usually undesirable, characteristic, such (−7.5 + 0.5 NGAIN)/20 IOUT = [39.4/RSET] × 10 (23) as 60 Hz hum or clock feedthrough that is equally present on both individual signals. where NGAIN is the value of DAC fine gain control [3:0]. Connecting the AD9879 true and complement outputs to the The full-scale output current range of the AD9879 is 4 mA to differential inputs of the gain programmable cable drivers 20 mA. Full-scale output currents outside of this range degrade AD8321/AD8323 or AD8322/AD8327 provides an optimized SFDR performance. SFDR is also slightly affected by output solution for the standard compliant cable modem upstream matching; the two outputs should be terminated equally for best channel. The cable driver’s gain can be programmed through a SFDR performance. The output load should be located as close direct 3-wire interface using the profile registers of the AD9879. as possible to the AD9879 package to minimize stray capaci- tance and inductance. AD9879 AD832x 8 t 8 t MCLK LOW-PASS MCLK 4 t MCLK TX DAC FILTER 75Ω 4 t MCLK 8 t MCLK CA_EN CA 3 CA_EN CA_CLK VARIABLE GAIN CA_DATA CABLE DRIVER CA_CLK CA_DATA AMPLIFIER MSB LSB Figure 19. Cable Amplifier Connection Figure 20. Cable Amplifier Interface Timing Rev. A | Page 25 of 32 02773-019 02773-020 AD9879 PROGRAMMING THE AD8321/AD8323 OR AD8322/AD8327 CABLE DRIVER AMPLIFIER GAIN CONTROL 3. Change in Profile Selection—The AD9879 samples the Programming the gain of the AD832x family of cable driver PROFILE input pin together with the two profile select bits amplifiers can be accomplished via the AD9879 cable amplifier and writes to the AD832x gain control registers when a control interface. Four 8-bit registers within the AD9879 (one change in profile and gain is determined. The data written per profile) store the gain value to be written to the serial 3-wire to the cable driver amplifier comes from the AD9879 gain port. Typically, either the AD8321/AD8323 or AD8322/AD8327 control register associated with the current profile. variable gain cable amplifiers are connected to the chip’s 3-wire cable amplifier interface. The Tx gain control select bit in 4. Write to AD9879 Cable Driver Amplifier Control Register 0x0F changes the interpretation of the bits in Registers Registers—The AD9879 writes gain control data associated 0x13, 0x17, 0x1B, and 0x1F. See the Cable Driver Gain Control with the current profile to the AD832x whenever the section register description. selected AD9879 cable driver amplifier gain setting is changed. Data transfers to the gain programmable cable driver amplifier are initiated by the following four conditions. Once a new stable gain value is detected (48 MCLK to 64 MCLK cycles after initiation), a data write starts with 1. Power-Up and Hardware Reset—Upon initial power-up CA_EN going low. The AD9879 always finishes a write and every hardware reset, the AD9879 clears the contents sequence to the cable driver amplifier once it is started. The of the gain control registers to 0, which defines the lowest logic controlling data transfers to the cable driver amplifier uses gain setting of the AD832x. Thus, the AD9879 writes all 0s up to 200 MCLK cycles and is designed to prevent erroneous out of the 3-wire cable amplifier control interface. write cycles from occurring. 2. Software Reset—Writing a 1 to Bit 5 of Address 0x00 initiates a software reset. Upon a software reset, the AD9879 clears the contents of the gain control registers to 0 for the lowest gain and sets the profile select to 0. The AD9879 writes all 0s out of the 3-wire cable amplifier control interface if the gain was previously on a different setting (other than 0). Rev. A | Page 26 of 32 AD9879 RECEIVE PATH (Rx) signal should be biased to a dc level equal to the midpoint of the IF10 AND IF12 ADC OPERATION ADC reference voltages, REFT12 and REFB12. Nominally, this The IF10 and IF12 ADCs have a common architecture and level is 1.2 V. When ac-coupled, the ADC inputs self bias to this share many of the same characteristics from an applications voltage and require no additional input circuitry. standpoint. Most of the information in this section is applicable to both IF ADCs. Differences, where they exist, are highlighted. Figure 23 illustrates a recommended circuit that eases the burden on the signal source by isolating its output from the INPUT SIGNAL RANGE AND DIGITAL OUTPUT ADC input. The 33 Ω series termination resistors isolate the CODES amplifier outputs from any capacitive load, which typically improves settling time. The series capacitors provide ac signal The IF ADCs have differential analog inputs labeled IF+ and coupling which ensures the ADC inputs operate at the optimal IF−. The signal input, V , is the voltage difference between the AIN dc bias voltage. The shunt capacitor sources the dynamic two input pins, V = V – V . The full-scale input voltage AIN IF+ IF− currents required to charge the SHA input capacitors, removing range is determined by the internal reference voltages, REFT this requirement from the ADC buffer. The values of CC and and REFB, which define the top and bottom of the scale. The CS should be calculated to get the correct HPF and LPF corner peak input voltage to the ADC is the difference between REFT frequencies. and REFB, which is 1 Vppd. This results in the ADC full-scale input voltage range of 2 Vppd. The digital output code is t EE straight binary and is illustrated in Table 12. M = 8 REFCLK Table 12. Digital Output Codes t OD IF[11:0] Input Signal Voltage t MD MCLK 111...111 VAIN ≥ +1.0 V 111...111 VAIN = +1.0 – 1 LSB V 111...110 VAIN = +1.0 – 2 LSB V RXIQ I[7:4] I[3:0] Q[7:4] Q[3:0] I[7:4] I[3:0] DATA ... 100...001 VAIN = +1 LSB V RXSYNC 100...000 VAIN = 0.0 V 011...111 VAIN = −1 LSB V IF10 IF12 IF10 IF12 IF10 IF12 IF DATA ... 000...001 V = −1.0 + 2 LSB V AIN Figure 21. Rx Port Timing (Default Mode: Multiplexed IF ADC Data) 000...000 VAIN = −1.0 V t EE 000...000 VAIN < −1.0 V M = 8 The IF10 ADC digital output code occupies the 10 MSBs of the REFCLK t OD Rx digital output port (IF[11:2]). The output codes clamp to the t MD top or the bottom of the scale when the inputs are overdriven. MCLK DRIVING THE INPUTS RXIQ I[7:4] I[3:0] Q[7:4] Q[3:0] I[7:4] I[3:0] DATA The IF ADCs have differential switched capacitor sample-and- hold amplifier (SHA) inputs. The nominal differential input impedance is 4.0 kΩ||3 pF. This impedance can be used as the RXSYNC effective termination impedance when calculating filter transfer characteristics and voltage signal attenuation from non-zero IF DATA IF10 OR IF12 IF10 OR IF12 IF10 OR IF12 source impedances. It should be noted, however, that for best Figure 22. Rx Port Timing (Nonmultiplexed Data) performance, additional requirements must be met by the signal source. The SHA has input capacitors that must be C C 33Ω recharged each time the input is sampled. This results in a AINP C dynamic input current at the device input. This demands that V S S C C 33Ω the source has low (<50 V) output impedance at frequencies up AINN to the ADC sampling frequency. Also, the source must have settling to better than 0.1% in <1/2 ADC CLK period. Figure 23. Simple ADC Drive Configuration Another consideration for getting the best performance from the ADC inputs is the dc biasing of the input signal. Ideally, the Rev. A | Page 27 of 32 02773-023 02773-022 02773-021 AD9879 PCB DESIGN CONSIDERATIONS Although the AD9879 is a mixed-signal device, the part should POWER PLANES AND DECOUPLING be treated as an analog component. The on-chip digital The AD9879 evaluation board demonstrates a good power circuitry is specially designed to minimize the impact the digital supply distribution and decoupling strategy. The board has four switching noise has on the operation of the analog circuits. The layers: two signal layers, one ground plane, and one power power, grounding, and layout recommendations in this section plane. will help provide the best performance from the MxFE. The power plane is split into a 3 VDD section which is used for COMPONENT PLACEMENT the 3 V digital logic circuits, a DVDD section that is used to Chances for obtaining the best performance from the MxFE are supply the digital supply pins of the AD9879, an AVDD section greatly increased if the three following guidelines of component that is used to supply the analog supply pins of the AD9879, and placement are followed. a VANLG section that supplies the higher voltage analog components on the board. The 3 VDD section typically has the • Manage the path of return currents flowing into the highest frequency currents on the power plane and should be ground plane so that high frequency switching currents kept the furthest from the MxFE and analog sections of the from the digital circuits do not flow onto the ground plane board. under the MxFE or analog circuits. The DVDD portion of the plane brings the current used to • Keep noisy digital signal paths and sensitive receive signal power the digital portion of the MxFE to the device. This paths as short as possible. should be treated similarly to the 3VDD power plane and be • Keep digital (noise generating) and analog (noise kept from going underneath the MxFE or analog components. susceptible) circuits as far away from each other as The MxFE should sit above the AVDD portion of the power possible. plane. To best manage the return currents, pure digital circuits that The AVDD and DVDD power planes can be fed from the same generate high switching currents should be closest to the power low noise voltage source. They should be decoupled from each supply entry. This keeps the highest frequency return current other, however, to prevent the noise generated in the DVDD paths short and prevents them from traveling over the sensitive portion of the MxFE from corrupting the AVDD supply. This MxFE and analog portions of the ground plane. Also, these can be done by using ferrite beads between the voltage source circuits should be generously bypassed at each device, further and DVDD and between the source and AVDD. Both DVDD reducing the high frequency ground currents. The MxFE and AVDD should have a low ESR, bulk decoupling capacitor should be placed adjacent to the digital circuits, such that the on the MxFE side of the ferrite as well as low ESR, low ESL de- ground return currents from the digital sections do not flow coupling capacitors on each supply pin (for example, the into the ground plane under the MxFE. The analog circuits AD9879 requires 17 power supply decoupling caps). The should be placed furthest from the power supply. decoupling caps should be placed as close as possible to the MxFE supply pins. An example of the proper decoupling is The AD9879 has several pins which are used to decouple shown in the AD9875 evaluation board schematic. sensitive internal nodes. These pins are REFIO, REFB10, REFT10, REFB12, and REFT12. The decoupling capacitors connected to these points should have low ESR and ESL. These capacitors should be placed as close as possible to the MxFE and be connected directly to the analog ground plane. The resistor connected to the FSADJ pin and the RC network connected to the PLLFILT pin should also be placed close to the device and connected directly to the analog ground plane. Rev. A | Page 28 of 32 AD9879 GROUND PLANES SIGNAL ROUTING In general, if the component placing guidelines discussed in the The digital Rx and Tx signal paths should be kept as short as Component Placement section can be implemented, it is best to possible. Also, these traces should have a controlled impedance have at least one continuous ground plane for the entire board. of about 50 Ω. This prevents poor signal integrity and the high All ground connections should be made as short as possible. currents that can occur during undershoot or overshoot caused This results in the lowest impedance return paths and the by ringing. If the signal traces cannot be kept shorter than quietest ground connections. approximately 1.5 inches, then series termination resistors (33 Ω to 47 Ω) should be placed close to all signal sources. It is If the components cannot be placed in a manner that keeps the advisable to series terminate all clock signals at their source high frequency ground currents from traversing under the regardless of trace length. MxFE and analog components, it may be necessary to put current steering channels into the ground plane to route the The receive (I IN, Q IN, and RF IN) signals are the most high frequency currents around these sensitive areas. These sensitive signals on the entire board. Careful routing of these current steering channels should be made only when and where signals is essential for good receive path performance. The Rx± necessary. signals form a differential pair and should be routed together as a pair. By keeping the traces adjacent to each other, noise coupled onto the signals appears as common-mode and is largely rejected by the MxFE receive input. Keeping the driving point impedance of the receive signal low and placing any low- pass filtering of the signals close to the MxFE further reduces the possibility of noise corrupting these signals. Rev. A | Page 29 of 32 AD9879 OUTLINE DIMENSIONS 23.20 BSC 20.00 BSC 3.40 1.03 MAX 18.85 REF 0.88 0.73 80 51 81 50 SEATING PLANE 14.00 BSC TOP VIEW (PINS DOWN) 12.35 REF 17.20 VIEW A BSC PIN 1 2.90 0.23 100 31 2.70 1 30 0.11 2.50 7° 0.40 0.65 BSC 0.50 0° 0.22 LEAD PITCH 0.25 LEAD WIDTH 0.10 COPLANARITY VIEW A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-022-GC-1 Figure 24. 100-Lead Metric Quad Flat Package [MQFP] (S-100-3) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option AD9879BS −40°C to +85°C 100-Lead MQFP S-100-3 1 AD9879BSZ −40°C to +85°C 100-Lead MQFP S-100-3 AD9879-EB Evaluation Board 1 Z = Pb-free part. Rev. A | Page 30 of 32 AD9879 NOTES Rev. A | Page 31 of 32 AD9879 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C02773-0-6/05(A) Rev. A | Page 32 of 32