ANALOG DEVICES AD9878

Mixed-Signal Front End for Broadband Applications AD9878 FUNCTIONAL BLOCK DIAGRAM FEATURES Low cost 3.3 V CMOS MxFE™ for broadband applications I 12 –1 DOCSIS, EURO-DOCSIS, DVB, DAVIC compliant 16 SINC Tx DAC TxID[5:0] Q Tx 232 MHz quadrature digital upconverter DDS 12-bit direct IF DAC (TxDAC+®) Σ-∆ Σ-∆ OUTPUT Up to 65 MHz carrier frequency DDS 3 4 SDIO CONTROL REGISTERS CA PORT Programmable sampling clock rates MCLK Analog Tx output level adjust PLL OSCIN Dual 12-bit, 29 MSPS direct IF ADCs with video clamp input 10 IF10[4:0] IF10 INPUT 10-bit, 29 MSPS sampling ADC MUX ADC 8-bit ∑-∆ auxiliary DAC 12 IF12B INPUT ADC MUX Direct interface to AD832x family of PGA cable drivers Σ VIDEO IN APPLICATIONS – IF12[11:0] MUX CLAMP LEVEL Cable set-top boxes MUX 12 Cable and wireless modems IF12A INPUT ADC FLAG[2:1] Figure 1. GENERAL DESCRIPTION The AD9878 is a single-supply, cable modem/set-top box, The 12-bit ADCs provide excellent undersampling performance, mixed-signal front end. The device contains a transmit path allowing this device to typically deliver better than 10 ENOBs interpolation filter, a complete quadrature digital upconverter, with IF inputs up to 70 MHz. The 12-bit IF ADCs can sample at and a transmit DAC. The receive path contains dual 12-bit rates up to 29 MHz, allowing them to process wideband signals. ADCs and a 10-bit ADC. All internally required clocks and an The AD9878 includes a programmable ∑-∆ DAC, which can be output system clock are generated by the phase-locked loop used to control an external component such as a variable gain (PLL) from a single crystal oscillator or clock input. amplifier (VGA) or a voltage controlled tuner. The transmit path interpolation filter provides an upsampling The AD9878 also integrates a CA port that enables a host factor of 16× with an output signal bandwidth up to 4.35 MHz. processor to interface with the AD832x family of programmable Carrier frequencies up to 65 MHz with 26 bits of frequency tuning gain amplifier (PGA) cable drivers or industry equivalent via resolution can be generated by the direct digital synthesizer the MxFE serial port (SPORT). (DDS). The transmit DAC resolution is 12 bits and can run at sampling rates as high as 232 MSPS. Analog output scaling from The AD9878 is available in a 100-lead, LQFP package. The 0 dB to 7.5 dB in 0.5 dB steps is available to preserve SNR when AD9878 is specified over the extended industrial (−40°C to reduced output levels are required. +85°C) temperature range. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 www.analog.com or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.326.8703 © 2005 Analog Devices, Inc. All rights reserved. 03277-001 AD9878 TABLE OF CONTENTS Electrical Characteristics ................................................................. 4 Transmit Timing......................................................................... 21 Absolute Maximum Ratings............................................................ 7 Interpolation Filter..................................................................... 21 Explanation of Test Levels........................................................... 7 Half-Band Filters (HBFs) .......................................................... 21 Thermal Characteristics .............................................................. 7 Cascade Integrator Comb (CIC) Filter.................................... 21 ESD Caution.................................................................................. 7 Combined Filter Response........................................................ 21 Pin Configuration and Function Descriptions............................. 8 Digital Upconverter ................................................................... 22 Typical Performance Characteristics ........................................... 10 Tx Signal Level Considerations................................................ 22 Terminology .................................................................................... 13 Tx Throughput and Latency..................................................... 23 Register Bit Definitions.................................................................. 14 DAC.............................................................................................. 23 Register 0x00—Initialization .................................................... 15 Programming the AD8321/AD8323 or AD8322/AD8327/AD8238 Cable-Driver Amplifiers............ 23 Register 0x01—Clock Configuration....................................... 15 OSCIN Clock Multiplier ........................................................... 24 Register 0x02—Power-Down.................................................... 15 Clock and Oscillator Circuitry ................................................. 24 Register 0x03—Flag Control..................................................... 15 Programmable Clock Output REFCLK .................................. 24 Register 0x04—∑-∆ Control Word........................................... 15 Power-Up Sequence ................................................................... 26 Register 0x07—Video Input Configuration............................ 16 Reset ............................................................................................. 26 Register 0x08—ADC Clock Configuration ............................ 16 Transmit Power-Down .............................................................. 26 Register 0x0C—Die Revision.................................................... 16 ∑-∆ Outputs ................................................................................ 27 Register 0x0D—Tx Frequency Tuning Words LSBs.............. 16 Receive Path (Rx) ....................................................................... 27 Register 0x0E—DAC Gain Control ......................................... 16 IF10 and IF12 ADC Operation ................................................ 27 Register 0x0F—Tx Path Configuration................................... 16 ADC Voltage References ........................................................... 29 Registers 0x10 Through 0x17—Burst Parameter................... 17 Video Input ................................................................................. 29 Serial Interface for Register Control ............................................ 18 PCB Design Considerations.......................................................... 30 General Operation of the Serial Interface ............................... 18 Component Placement .............................................................. 30 Instruction Byte .......................................................................... 18 Power Planes and Decoupling .................................................. 30 Serial Interface Port Pin Descriptions ..................................... 18 Ground Planes ............................................................................ 30 MSB/LSB Transfers..................................................................... 19 Signal Routing............................................................................. 30 Notes on Serial Port Operation ................................................ 19 Outline Dimensions....................................................................... 36 Theory of Operation ...................................................................... 20 Ordering Guide .......................................................................... 36 Transmit Path.............................................................................. 21 Data Assembler........................................................................... 21 Rev. A | Page 2 of 36 AD9878 REVISION HISTORY 3/05—Rev. 0 to Rev. A Changed OSCOUT to REFCLK.................................................. Universal Changes to Electrical Characteristics ........................................................4 Changes to Pin Configuration and Function Descriptions....................8 Changes to ∑-∆ Output Signals (Figure 32)............................................27 Change to ∑-∆ RC Filter (Figure 33) .......................................................27 Changes to Evaluation PCB Schematic (Figure 38 and Figure 39)......31 Updated Outline Dimensions...................................................................36 Changes to Ordering Guide......................................................................36 5/03—Revision 0: Initial Version Rev. A | Page 3 of 36 AD9878 ELECTRICAL CHARACTERISTICS VAS = 3.3 V ± 5%, VDS = 3.3 V ± 10%, fOSCIN = 27 MHz, fSYSCLK = 216 MHz, fMCLK = 54 MHz (M = 8), ADC clock derived from OSCIN, RSET = 4.02 kΩ, maximum. Fine gain, 75 Ω DAC load. Table 1. PARAMETER Temp Test Level Min Typ Max Unit OSCIN and XTAL CHARACTERISTICS Frequency Range Full II 3 29 MHz Duty Cycle 25°C II 35 50 65 % Input Impedance 25°C III 100||3 MΩ||pF MCLK Cycle-to-Cycle Jitter (f derived from PLL) 25°C III 6 ps rms MCLK Tx DAC CHARACTERISTICS Maximum Sample Rate Full II 232 MHz Resolution N/A N/A 12 Bits Full-Scale Output Current Full II 4 10 20 mA Gain Error (Using Internal Reference) 25°C I −2.0 −1 +2.0 % FS Offset Error 25°C I ±1.0 % FS Reference Voltage (REFIO Level) 25°C I 1.18 1.23 1.28 V Differential Nonlinearity (DNL) 25°C III ±2.5 LSB Integral Nonlinearity (INL) 25°C III ±8 LSB Output Capacitance 25°C III 5 pF Phase Noise @ 1 kHz Offset, 42 MHz Carrier 25°C III −110 dBc/Hz Output Voltage Compliance Range Full II −0.5 +1.5 V Wideband SFDR 5 MHz Analog Output, I = 10 mA Full II 62.4 68 dB OUT 65 MHz Analog Output, I = 10 mA Full II 50.3 53.5 dB OUT Narrow-Band SFDR (±1 MHz Window) 5 MHz Analog Output, IOUT = 10 mA Full II 71 74 dB 65 MHz Analog Output, IOUT = 10 mA Full II 61 64 dB Tx MODULATOR CHARACTERISTICS I/Q Offset Full II 50 55 dB Pass-Band Amplitude Ripple (f < fIQCLK/8) Full II ±0.1 dB Pass-Band Amplitude Ripple (f < f/4) Full II ±0.5 dB IQCLK Stop-Band Response (f > f × 3/4) Full II −63 dB IQCLK Tx GAIN CONTROL Gain Step Size 25°C III 0.5 dB Gain Step Error 25°C III <0.05 dB Settling Time, 1% (Full-Scale Step) 25°C III 1.8 µs 10-BIT ADC CHARACTERISTICS Resolution N/A N/A 10 Bits Maximum Conversion Rate Full II 29 MHz Pipeline Delay N/A N/A 4.5 ADC cycles Analog Input Input Voltage Range Full II 2 VPPD Differential Input Impedance 25°C III 4||2 kΩ||pF Full Power Bandwidth 25°C III 90 MHz Dynamic Performance (AIN = −0.5 dBFS, f = 5 MHz) Signal-to-Noise and Distortion (SINAD) Full II 57.6 59.7 dB Effective Number of Bits (ENOB) Full II 9.3 9.6 Bits Total Harmonic Distortion (THD) Full II −71.1 −63.6 dB Spurious-Free Dynamic Range (SFDR) Full II 65.7 72.4 dB Reference Voltage Error, REFT10 to REFB10 (1.0 V) Full I ±4 ±100 mV Rev. A | Page 4 of 36 AD9878 PARAMETER Temp Test Level Min Typ Max Unit Dynamic Performance (AIN = −0.5 dBFS, f = 50 MHz) Signal-to-Noise and Distortion (SINAD) Full II 54.8 57.8 dB Effective Number of Bits (ENOB) Full II 8.8 9.3 Bits Total Harmonic Distortion (THD) Full II −63.3 −56.9 dB Spurious-Free Dynamic Range (SFDR) Full II 56.9 63.7 dB 12-BIT ADC CHARACTERISTICS Resolution N/A N/A 12 Bits Maximum Conversion Rate Full II 29 MHz Pipeline Delay N/A N/A 5.5 ADC cycles Analog Input Input Voltage Range Full III 2 VPPD Differential Input Impedance 25°C III 4||2 kΩ||pF Aperture Delay 25°C III 2.0 ns Aperture Jitter 25°C III 1.2 ps rms Full Power Bandwidth 25°C III 85 MHz Input Referred Noise 25°C III 75 µV Reference Voltage Error, REFT12 to REFB12 (1 V) Full I −100 ±16 +100 mV Dynamic Performance (A = −0.5 dBFS, f = 5 MHz) IN ADC Sample Clock = OSCIN Signal-to-Noise and Distortion (SINAD) Full II 61.0 67 dB Effective Number of Bits (ENOBs) Full II 9.8 10.8 Bits Signal-to-Noise Ratio (SNR) Full II 64.2 66 dB Total Harmonic Distortion (THD) Full II −72.7 −61.7 dB Spurious-Free Dynamic Range (SFDR) Full II 62.8 74.6 dB ADC Sample Clock = PLL Signal-to-Noise and Distortion (SINAD) Full II 60.4 64.4 dB Effective Number of Bits (ENOB) Full II 9.74 10.4 Bits Signal-to-Noise Ratio (SNR) Full II 62.4 65.1 dB Total Harmonic Distortion (THD) Full II −72.7 −61.8 dB Spurious-Free Dynamic Range (SFDR) Full II 62.7 74.6 dB Dynamic Performance (A = −0.5 dBFS, f = 50 MHz) IN ADC Sample Clock = OSCIN Signal-to-Noise and Distortion (SINAD) Full II 61.0 65.2 dB Effective Number of Bits (ENOB) Full II 9.8 10.5 Bits Signal-to-Noise Ratio (SNR) Full II 64.2 67.4 dB Total Harmonic Distortion (THD) Full II −72.8 −61.8 dB Spurious-Free Dynamic Range (SFDR) Full II 62.8 74.6 dB Differential Phase 25°C III <0.1 Degrees Differential Gain 25°C III <1 LSB VIDEO ADC PERFORMANCE (AIN = −0.5 dBFS, f = 5 MHz) ADC Sample Clock = OSCIN Signal-to-Noise and Distortion (SINAD) Full II 46.7 53 dB Signal-to-Noise Ratio (SNR) Full II 54.3 63.2 Bits Total Harmonic Distortion (THD) Full II −50.2 −45.9 dB Spurious-Free Dynamic Range (SFDR) Full II 45.9 50 dB CHANNEL-TO-CHANNEL ISOLATION Tx DAC-to-ADC Isolation (5 MHz Analog Output) Isolation Between Tx and 10-Bit ADC 25°C III >60 dB Isolation Between Tx and 12-Bit ADCs 25°C III >80 dB ADC-to-ADC Isolation (AIN = –0.5 dBFS, f = 5 MHz) Isolation Between IF10 and IF12A/B 25°C III >85 dB Isolation Between IF12A and IF12B 25°C III >85 dB Rev. A | Page 5 of 36 AD9878 PARAMETER Temp Test Level Min Typ Max Unit TIMING CHARACTERISTICS (10 pF Load) Wake-Up Time N/A N/A 200 tMCLK cycles Minimum RESET Pulse Width Low, tRL N/A N/A 5 tMCLK cycles Digital Output Rise/Fall Time Full II 2.8 4 ns Tx/Rx Interface MCLK Frequency, f Full II 58 MHz MCLK TxSYNC/TxIQ Setup Time, tSU Full II 3 ns TxSYNC/TxIQ Hold Time, tHU Full II 3 ns MCLK Rising Edge to RxSYNC Valid Delay, tMD Full II 0 1.0 ns REFCLK Rising or Falling Edge to Full II t / t / ns OSCIN OSCIN RxSYNC Valid Delay, t 4 − 2.0 4 + 3.0 OD REFCLK Edge to MCLK Falling Edge, tEE Full II −1.0 +1.0 ns SERIAL CONTROL BUS Maximum SCLK Frequency, f Full II 15 MHz SCLK Minimum Clock Pulse Width High, tPWH Full II 30 ns Minimum Clock Pulse Width Low, tPWL Full II 30 ns Maximum Clock Rise/Fall Time Full II 1 µs Minimum Data/Chip-Select Setup Time, t Full II 25 ns DS Minimum Data Hold Time, t Full II 0 ns DH Maximum Data Valid Time, t Full II 30 ns DV CMOS LOGIC INPUTS Logic 1 Voltage 25°C II V − 0.7 V DRVDD Logic 0 Voltage 25°C II 0.4 V Logic 1 Current 25°C II 12 µA Logic 0 Current 25°C II 12 µA Input Capacitance 25°C III 3 pF CMOS LOGIC OUTPUTS (1 mA Load) Logic 1 Voltage 25°C II VDRVDD − 0.6 V Logic 0 Voltage 25°C II 0.4 V POWER SUPPLY Supply Current, IS (Full Operation) 25°C II 184 204 mA Analog Supply Current, I 25°C III 105 115 mA AS Digital Supply Current, I 25°C III 79 89 mA DS Supply Current, I S Standby (PWRDN Pin Active, IAS + IDS ) 25°C II 124 137 mA Full Power-Down (Register 0x02 = 0xFF) 25°C II 46 52 mA Power-Down Tx Path (Register 0x02 = 0x60) 25°C III 124 mA Power-Down IF12 Rx Path (Register 0x02 = 0x1B) 25°C III 131 159 mA Power Supply Rejection (Differential Signal) Tx DAC 25°C III <0.25 % FS 10-Bit ADC 25°C III <0.0001 % FS 12-Bit ADC 25°C III <0.0004 % FS Rev. A | Page 6 of 36 AD9878 ABSOLUTE MAXIMUM RATINGS Table 2. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress Power Supply (V , V , V ) 3.9 V AVDD DVDD DRVDD rating only; functional operation of the device at these or any Digital Output Current 5 mA other condition s above those indicated in the operational Digital Inputs −0.3 V to V + 0.3 V DRVDD section of this specification is not implied. Exposure to absolute Analog Inputs −0.3 V to VAVDD + 0.3 V maximum rating conditions for extended periods may affect Operating Temperature −40°C to +85°C device reliability. Maximum Junction Temperature 150°C Storage Temperature −65°C to +150°C Lead Temperature (Soldering, 10 sec) 300°C EXPLANATION OF TEST LEVELS I. Devices are 100% production tested at 25°C and guaranteed by design and characterization testing for extended industrial operating temperature range (−40°C to +85°C). II. Parameter is guaranteed by design and/or characterization testing. III. Parameter is a typical value only. N/A. Test level definition is not applicable. THERMAL CHARACTERISTICS Thermal resistance of 100-lead LQFP: θ = 40.5°C/W JA ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. A | Page 7 of 36 AD9878 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 DRGND 1 75 REFT10 DRVDD 2 74 REFB10 (MSB) IF12(11) 3 73 AGND10 IF12(10) 4 72 AVDD10 IF12(9) 5 71 DRVDD IF12(8) 6 70 DRGND IF12(7) 7 69 REFCLK IF12(6) 8 68 SIGDELT IF12(5) 9 67 FLAG1 IF12(4) 10 66 FLAG2 IF12(3) 11 65 CA_EN AD9878 IF12(2) 12 64 CA_DATA IF12(1) 13 TOP VIEW 63 CA_CLK (Not to Scale) IF12(0) 14 62 DVDDOSC (MSB) IF10(4) 15 61 OSCIN IF10(3) 16 60 XTAL IF10(2) 17 59 DGNDOSC IF10(1) 18 58 AGNDPLL IF10(0) 19 57 PLLFILT RxSYNC 20 56 AVDDPLL DRGND 21 55 DVDDPLL DRVDD 22 54 DGNDPLL MCLK 23 53 AVDDTx DVDD 24 52 Tx+ DGND 25 51 Tx– 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No. Mnemonic Descriptions 1, 21, 70 DRGND Pin Driver Digital Ground 2, 22, 71 DRVDD Pin Driver Digital 3.3 V Supply 3 (MSB) IF12(11) 12-Bit ADC Digital Ouput 4 to 14 IF12[10:0] 12-Bit ADC Digital Ouput 15 (MSB) IF10(4) 10-Bit ADC Digital Ouput 16 to 19 IF10[3:0] 10-Bit ADC Digital Ouput 20 RxSYNC Sync Output, 10-Bit and 12-Bit ADCs 23 MCLK Master Clock Output 24, 33, 35, 39 DVDD Digital 3.3 V Supply 25, 34, 36, 40 DGND Digital Ground 26 TxSYNC Sync Input for Transmit Port 27 (MSB) TxIQ(5) Digital Input for Transmit Port 28 to 32 TxIQ[4:0] Digital Input for Transmit Port 37 PROFILE Profile Selection Input 38 RESET Chip Reset Input 41 SCLK SPORT Clock 42 SPORT Chip Select CS 43 SDIO SPORT Data I/O Rev. A | Page 8 of 36 TxSYNC AVDD (MSB) TxIQ(5) AGND TxIQ(4) VIDEO IN TxIQ(3) AGND TxIQ(2) IF12A+ TxIQ(1) IF12A– TxIQ(0) AGND DVDD AVDD DGND REFT12A DVDD REFB12A DGND AVDD PROFILE AGND RESET IF12B+ DVDD IF12B– DGND AGND SCLK AVDD CS REFT12B SDIO REFB12B SDO AVDD DGNDTx AGND DVDDTx AVDD10 PWRDN AGND10 REFIO IF10+ FSADJ IF10– AGNDTx AGND 03277-002 AD9878 Pin No. Mnemonic Descriptions 44 SDO SPORT Data Output 45 DGNDTx Tx Path Digital Ground 46 DVDDTx Tx Path Digital 3.3 V Supply 47 PWRDN Power-Down Transmit Path 48 REFIO TxDAC Decoupling (to AGND) 49 FSADJ DAC Output Adjust (External Resistor) 50 AGNDTx Tx Path Analog Ground 51, 52 Tx−, Tx+ Tx Path Complementary Outputs 53 AVDDTx Tx Path Analog 3.3 V Supply 54 DGNDPLL PLL Digital Ground 55 DVDDPLL PLL Digital 3.3 V Supply 56 AVDDPLL PLL Analog 3.3 V Supply 57 PLLFILT PLL Loop Filter Connection 58 AGNDPLL PLL Analog Ground 59 DGNDOSC Oscillator Digital Ground 60 XTAL Crystal Oscillator Inverted Output 61 OSCIN Oscillator Clock Input 62 DVDDOSC Oscillator Digital 3.3 V Supply 63 CA_CLK Serial Clock-to-Cable Driver 64 CA_DATA Serial Data-to-Cable Driver 65 CA_EN Serial Enable-to-Cable Driver 66, 67 FLAG[2:1] Programmable Flag Outputs 68 SIGDELT ∑-∆ DAC Output 69 REFCLK Reference Clock Output 72, 80 AVDD10 10-Bit ADC Analog 3.3 V Supply 73, 79 AGND10 10-Bit ADC Analog Ground 74 REFB10 10-Bit ADC Reference Decoupling Node 75 REFT10 10-Bit ADC Reference Decoupling Node 76, 81, 86, 89, 94, AGND 12-Bit ADC Analog Ground 97, 99 77, 78 IF10−, IF10+ Differential Input to 10-bit ADC 82, 85, 90, 93, 100 AVDD 12-Bit ADC Analog 3.3 V Supply 83 REFB12B ADC12B Reference Decoupling Node 84 REFT12B ADC12B Reference Decoupling Node 87, 88 IF12B−, IF12B+ Differential Input to ADC12B 91 REFB12A ADC12A Reference Decoupling Node 92 REFT12A ADC12A Reference Decoupling Node 95, 96 IF12A−, IF12A+ Differential Input to ADC12A 98 VIDEO IN Video Clamp Input Rev. A | Page 9 of 36 AD9878 TYPICAL PERFORMANCE CHARACTERISTICS 0 0 –10 –10 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 –100 02 46 8 10 12 14 16 18 20 55 57 59 61 63 65 67 69 71 73 75 FREQUENCY (MHz) FREQUENCY (MHz) Figure 3. Dual-Sideband Spectral Plot, f = 5 MHz, f = 1 MHz, Figure 6. Dual-Sideband Spectral Plot, f = 65 MHz, f = 1 MHz, C C R = 10 kΩ (I = 4 mA), RBW = 1 kHz R = 4 kΩ (I = 10 mA), RBW = 1 kHz SET OUT SET OUT 0 0 –10 –10 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 –100 02 46 8 10 12 14 16 18 20 0 20406080 100 120 FREQUENCY (MHz) FREQUENCY (MHz) Figure 4. Dual-Sideband Spectral Plot, fC = 5 MHz, f = 1 MHz, Figure 7. Single Sideband @ 65 MHz, f = 66 MHz, C RSET = 4 kΩ (IOUT = 10 mA), RBW = 1 kHz f = 1 MHz, R = 10 kΩ (I = 4 mA), RBW = 2 kHz SET OUT 0 0 –10 –10 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 –100 55 57 59 61 63 65 67 69 70 73 75 0 20406080 100 120 FREQUENCY (MHz) FREQUENCY (MHz) Figure 5. Dual-Sideband Spectral Plot, f = 65 MHz, C Figure 8. Single Sideband @ 65 MHz, fC = 66 MHz, f = 1 MHz, R = 10 kΩ (I = 4 mA), RBW = 1 kHz SET OUT f = 1 MHz, RSET = 4 kΩ (IOUT = 10 mA), RBW = 2 kHz Rev. A | Page 10 of 36 MAGNITUDE (dB) MAGNITUDE (dB) MAGNITUDE (dB) 03277-024 03277-023 03277-022 MAGNITUDE (dB) MAGNITUDE (dB) MAGNITUDE (dB) 03277-027 03277-026 03277-025 AD9878 0 0 –10 –10 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –100 –90 0 20 406080 100 120 0 20406080 100 120 FREQUENCY (MHz) FREQUENCY (MHz) Figure 9. Single Sideband @ 42 MHz, fC = 43 MHz, Figure 12. Single Sideband @ 5 MHz, fC = 6 MHz, f = 1 MHz, RSET = 10 kΩ (IOUT = 4 mA), RBW = 2 kHz f = 1 MHz, RSET = 4 kΩ (IOUT = 10 mA), RBW = 2 kHz 0 0 –10 –10 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –2.5 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5 0 20 406080 100 120 FREQUENCY (MHz) FREQUENCY (MHz) Figure 13. Single Sideband @ 65 MHz, f = 66 MHz, Figure 10. Single Sideband @ 42 MHz, fC = 43 MHz, C f = 1 MHz, R = 10 kΩ (I = 4 mA), RBW = 500 Hz f = 1 MHz, RSET = 4 kΩ (IOUT = 10 mA), RBW = 2 kHz SET OUT 0 0 –10 –10 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –100 –90 0 20 406080 100 120 –2.5 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5 FREQUENCY (MHz) FREQUENCY (MHz) Figure 11. Single Sideband @ 5 MHz, fC = 6 MHz, Figure 14. Single Sideband @ 65 MHz, f = 66 MHz, C f = 1 MHz, RSET = 10 kΩ (IOUT = 4 mA), RBW = 2 kHz f = 1 MHz, R = 4 kΩ (I = 10 mA), RBW = 500 Hz SET OUT Rev. A | Page 11 of 36 MAGNITUDE (dB) MAGNITUDE (dB) MAGNITUDE (dB) 03277-030 03277-029 03277-028 MAGNITUDE (dB) MAGNITUDE (dB) MAGNITUDE (dB) 03277-033 03277-031 03277-032 AD9878 0 0 –10 –10 –20 –20 –30 –30 –40 –50 –40 –60 –50 –70 –60 –80 –70 –90 –100 –80 –50 –40 –30 –20 –10 0 10 20 30 40 50 0 5 10 15 20 25 30 35 40 45 50 FREQUENCY (MHz) FREQUENCY (MHz) Figure 15. Single Sideband @ 65 MHz, fC = 66 MHz, Figure 17. 16-QAM @ 42 MHz Spectral Plot, RBW = 1 kHz f = 1 MHz, RSET = 10 kΩ (IOUT = 4 mA), RBW = 50 Hz 0 0 –10 –10 –20 –20 –30 –30 –40 –50 –40 –60 –50 –70 –60 –80 –70 –90 –100 –80 –2.5 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5 0 5 10 15 20 25 30 35 40 45 50 FREQUENCY (MHz) FREQUENCY (MHz) Figure 16. Single Sideband @ 65 MHz, fC = 66 MHz, Figure 18. 16-QAM @ 5 MHz Spectral Plot, RBW = 1 kHz f = 1 MHz, RSET = 10 kΩ (IOUT = 4 mA), RBW = 10 Hz Rev. A | Page 12 of 36 MAGNITUDE (dB) MAGNITUDE (dB) 03277-035 03277-034 MAGNITUDE (dB) MAGNITUDE (dB) 03277-037 03277-036 AD9878 TERMINOLOGY Differential Nonlinearity Error (DNL, No Missing Codes) Aperture Delay An ideal converter exhibits code transitions that are exactly 1 LSB The aperture delay is a measure of the sample-and-hold amplifier apart. DNL is the deviation from this ideal value. No missing (SHA) performance that specifies the time delay between the codes indicates that all of the ADC codes must be present over rising edge of the sampling clock input and when the input all operating ranges. signal is held for conversion. Integral Nonlinearity Error (INL) Aperture Jitter Linearity error refers to the deviation of each individual code from Aperture jitter is the variation in aperture delay for successive a line drawn from negative full scale through positive full scale. samples and is manifested as noise on the input to the ADC. The point used as negative full scale occurs ½ LSB before the first Input Referred Noise code transition. Positive full scale is defined as a level 1½ LSB The rms output noise is measured using histogram techniques. beyond the last code transition. The deviation is measured from The standard deviation of the ADC output codes is calculated the middle of each code to the true straight line. in LSB, and converted to an equivalent voltage. This results in a Phase Noise noise figure that can be directly referred to the input of the MxFE. Single-sideband, phase-noise power is specified relative to the Signal-to-Noise and Distortion (SINAD) Ratio carrier (dBc/Hz) at a given frequency offset (1 kHz) from the SINAD is the ratio of the rms value of the measured input signal carrier. Phase noise can be measured directly in single-tone to the rms sum of other spectral components below the Nyquist transmit mode with a spectrum analyzer that supports noise frequency, including harmonics, but excluding dc. The value for marker measurements. It detects the relative power between SINAD is expressed in decibels. the carrier and the offset (1 kHz) sideband noise and takes the resolution bandwidth (RBW) into account by subtracting Effective Number of Bits (ENOB) 10 × log(RBW). It also adds a correction factor that compensates For a sine wave, SINAD can be expressed in terms of the number for the implementation of the resolution bandwidth, log display, of bits. Using the following formula, it is possible to get a measure and detector characteristic. of performance expressed as N, the effective number of bits: Output Compliance Range N=(SINAD− 1.76) dB 6.02 The range of allowable voltage at the output of a current-output DAC. Operation beyond the maximum compliance limits can Thus, the effective number of bits for a device for sine wave cause either output stage saturation or breakdown, resulting in inputs at a given input frequency can be calculated directly nonlinear performance. from its measured SINAD. Spurious-Free Dynamic Range (SFDR) Signal-to-Noise Ratio (SNR) The difference, in dB, between the rms amplitude of the DAC SNR is the ratio of the rms value of the measured input signal output signal (or ADC input signal) and the peak spurious signal to the rms sum of other spectral components below the Nyquist over the specified bandwidth (Nyquist bandwidth, unless frequency, excluding harmonics and dc. The value for SNR is otherwise noted). expressed in decibels. Pipeline Delay (Latency) Total Harmonic Distortion (THD) The number of clock cycles between conversion initiation and THD is the ratio of the rms sum of the first six harmonic the associated output data being made available. components to the rms value of the measured input signal. It is expressed as a percentage, or in decibels. Offset Error The first code transition should occur at an analog value ½ LSB Power Supply Rejection above negative full scale. Offset error is defined as the deviation Power supply rejection specifies the converter’s maximum full- of the actual transition from that point. scale change when the supplies are varied from nominal to minimum or maximum specified voltages. Gain Error The first code transition should occur at an analog value ½ LSB Channel-to-Channel Isolation (Crosstalk) above negative full scale. The last transition should occur for an In an ideal multichannel system, the signal in one channel does analog value 1½ LSB below the nominal full scale. Gain error not influence the signal level of another channel. The channel- is the deviation of the actual difference between first and last to-channel isolation specification is a measure of the change code transitions and the ideal difference between first and last that occurs in a grounded channel as a full-scale signal is code transitions. applied to another channel. Rev. A | Page 13 of 36 AD9878 REGISTER BIT DEFINITIONS Table 4. Register Map Address Default (Hex) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (Hex) Type 0x00 Reset OSCIN multiplier M[4:0] 0x08 Read/write SDIO LSB bidirectional first 0x01 PLL lock MCLK divider R[5:0] 0x00 Read/write detect 0x02 Power down Power Power Power Power down Power Power Power 0x00 Read/write PLL down down down ADC12B down down down DAC digital ADC12A ADC10 reference reference Tx Tx ADC12A ADC12B 0x03 Video Flag 2 Flag 1 Flag 0 0x00 Read/write input enable into ADC12B 0x04 MSB/Flag 0 ∑-∆ output control word [7:0] 0x00 Read/write 0x05 0x00 Read/write 0x06 0x00 Read only 0x07 Video input Clamp level for video input [6:0] 0x00 Read/write enable 0x08 ADC clocked Rx port Power Power down Send Send 0x80 Read/write directly from fast down reference ADC12A ADC12B OSCIN edge RxSYNC ADC10 data only data only rate generator 0x09 0x00 Read/write 0x0A 0x00 Read/write 0x0B 0x00 Read/write 0x0C Version [3:0] 0x00 Read/write 0x0D Tx frequency tuning word Tx frequency tuning 0x00 Read/write profile 1 LSB [1:0] word profile 0 LSBs [1:0] 0x0E DAC fine gain control [3:0] 0x00 Read/write 0x0F Tx path Tx path Tx Tx path Tx path 0x00 Read/write select path spectral transmit AD8321/AD8323 Profile 1 bypass inversion single gain control –1 sinc tone mode filter 0x10 Tx Path Frequency Tuning Word Profile 0 [9:2] 0x00 Read/write 0x11 Tx Path Frequency Tuning Word Profile 0 [17:10] 0x00 Read/write 0x12 Tx Path Frequency Tuning Word Profile 0 [25:18] 0x00 Read/write 0x13 Cable-driver amplifier, Cable-driver amplifier, 0x00 Read/write Coarse Gain Control Profile 0 [7:4] Fine Gain Control Profile 0 [3:0] 0x14 Tx Path Frequency Tuning Word Profile 1 [9:2] 0x00 Read/write 0x15 Tx Path Frequency Tuning Word Profile 1 [17:10] 0x00 Read/write 0x16 Tx Path Frequency Tuning Word Profile 1 [25:18] 0x00 Read/write 0x17 0x00 Read/write Cable-driver amplifier, Cable-driver amplifier, Coarse Gain Control Profile 1 [7:4] Fine Gain Control Profile 1 [3:0] Rev. A | Page 14 of 36 AD9878 Bit 1: Power Down ADC12A Voltage Reference REGISTER 0x00—INITIALIZATION Bits 0 to 4: OSCIN Multiplier Active high powers down the voltage reference circuit for the ADC12A. This register field is used to program the on-chip clock multiplier that generates the chip’s high frequency system clock, Bit 2: Power Down ADC10 f . For example, to multiply the external crystal clock f SYSCLK OSCIN Active high powers down the 10-bit ADC. by 16, program Register 0x00, Bits 4:0, to 0x10. The default Bit 3: Power Down ADC12B clock multiplier value, M, is 0x08. Valid entries range from 1 to Active high powers down the ADC12B. 31. When M is set to 1, the PLL is disabled and internal clocks are derived directly from OSCIN. The PLL requires 200 MCLK Bit 4: Power Down ADC12A cycles to regain frequency lock after a change in M. After the Active high powers down the ADC12A. recapture time of the PLL, the frequency of f is stable. SYSCLK Bit 5: Power Down Tx Bit 5: Reset Active high powers down the digital transmit section of the Writing 1 to this bit resets the registers to their default values chip, similar to the function of the PWRDN pin. and restarts the chip. The reset bit always reads back 0. The bits in Register 0x00 are not affected by this software reset. However, Bit 6: Power Down DAC Tx a low level at the RESET pin forces all registers, including all Active high powers down the DAC. bits in Register 0x00, to their default states. Bit 7: Power Down PLL Bit 6: LSB First Active high powers down the OSCIN multiplier. Active high indicates SPI serial port access of instruction byte and REGISTER 0x03—FLAG CONTROL data registers is LSB first. Default low indicates MSB-first format. Bit 0: Flag 0 Enable Bit 7: SDIO Bidirectional When this bit is active high, the SIGDELT pin maintains a fixed Active high configures the serial port as a 3-signal port with logic level determined directly by the MSB of the ∑-∆ control the SDIO pin used as a bidirectional input/output pin. Default word of Register 0x04. low indicates that the serial port uses four signals with SDIO Bit 1: Flag 1 configured as an input and SDO configured as an output. The logic level of this bit is applied at the FLAG1 pin. REGISTER 0x01—CLOCK CONFIGURATION Bit 4: Flag 2 Bits [5:0]: MCLK Divider The logic level of this bit is applied at the FLAG2 pin. This register determines the output clock on the REFCLK pin. At default 0 (R = 0), REFCLK provides a buffered version of the Bit 5: Video Input into ADC12B OSCIN clock signal for other chips. The register can also be used If the video input is enabled, setting this bit high sends the to divide the chip’s master clock fMCLK by R, where R is an integer signal applied to the VIDEO IN pin to the ADC12B. Otherwise, between 2 and 63. The generated reference clock on REFCLK pin the signal applied to the VIDEO IN pin is sent to the ADC12A. can be used for external frequency controlled devices. REGISTER 0x04—∑-∆ CONTROL WORD Bit 7: PLL Lock Detect Bits [7:0]: ∑-∆ Control Word When this bit is set low, the REFCLK pin functions in its The ∑-∆ control word is 8 bits wide and controls the duty cycle default mode and provides an output clock with frequency of the digital output on the SIGDELT pin. Changes to the ∑-∆ fMCKL/R, as described above. If this bit is set to 1, the REFCLK pin control word take effect immediately for every register write. is configured to indicate whether the PLL is locked to fOSCIN. In ∑-∆ output control words have a default value of 0. The control this mode, the REFCLK pin should be low-pass filtered with an words are in straight binary format, with 0x00 corresponding to RC filter of 1.0 kΩ and 0.1 µF. A low output on REFCLK indicates the bottom of scale or 0% duty cycle, and 0xFF corresponding that the PLL has achieved lock with f . OSCIN to the top of scale or near 100% duty cycle. REGISTER 0x02—POWER-DOWN Bit 7: Flag 0 (∑-∆ Control Word MSB) Unused sections of the chip can be powered down when the When the Flag 0 enable bit (Register 0x03, Bit 0) is set, the logic corresponding bits are set high. This register has a default value level of this bit appears on the output of the SIGDELT pin. of 0x00, all sections active. Bit 0: Power Down ADC12B Voltage Reference Active high powers down the voltage reference circuit for ADC12B. Rev. A | Page 15 of 36 AD9878 REGISTER 0x0C—DIE REVISION REGISTER 0x07—VIDEO INPUT CONFIGURATION Bits [3:0]: Version Bits [6:0]: Clamp Level Control Value The die version of the chip can be read from this register. The 7-bit clamp-level control value is used to set an offset to the automatic clamp-level control loop. The actual ADC output has a REGISTER 0x0D—Tx FREQUENCY TUNING WORDS clamp-level offset equal to 16 times the clamp level control value. LSBs Clamp -LevelOffsetClamp -LevelControlValue=(x) 16 This register accommodates the 2 LSBs for each frequency tuning word (FTW). See the Registers 0x10 Through 0x17— The default value for the clamp-level control value is 0x20. This Burst Parameter section. results in an ADC output clamp-level offset of 512 LSBs. The REGISTER 0x0E—DAC GAIN CONTROL valid programming range for the clamp-level control value is 0x16 to 0x127. This register allows the user to program the DAC gain if the Tx Gain Control Select Bit 3 in Register 0x0F is set to 0. Bit 7: Video Input Enable This bit enables the video input. In default with Bit 7 = 0, both IF12 ADCs are connected to IF inputs. If the video input is Table 5. DAC Gain Control enabled by setting bit 7 = 1, the video input will be connected to Bits [3:0] DAC Gain (dB) the IF12 ADC selected by REG 0x03, Bit 6. 0000 0.0 (default) REGISTER 0x08—ADC CLOCK CONFIGURATION 0001 0.5 Bit 0: Send ADC12B Data Only 0010 1.0 0011 1.5 When this bit is set high, the device enters a nonmultiplexed … … mode, and only the data from the ADC12B is sent to the 1110 7.0 IF[11:0] digital output port. 1111 7.5 Bit 1: Send ADC12A Data Only When this bit is set high, the device enters a nonmultiplexed mode, and only the data from the ADC12A is sent to the REGISTER 0x0F—Tx PATH CONFIGURATION IF[11:0] digital output port. Bit 0: Single Tone Tx Mode Active high configures the AD9878 for single-tone applications If both the send ADC12B data only and send ADC12A data (e.g., FSK). The AD9878 supplies a single frequency output, as only register bits are set high, the device sends both ADC12A determined by the FTW selected by the active profile. In this and ADC12B data in the default multiplexed mode. mode, the TxIQ input data pins are ignored, but should be tied Bit 3: Power Down ADC10 Voltage Reference to a valid logic voltage level. Default value is 0x00 (inactive). Active high powers down the voltage reference circuit for Bit 1: Spectral Inversion Tx the ADC10. When set to 1, inverted modulation is performed: Bit 4: Power Down RxSYNC Generator MODULATOR _OUT=[I cos(ωt)+Q sin(ωt)]. Setting this bit to 1 powers down the 10-bit ADC’s sampling clock and makes the RxSYNC output pin stay low. It can be Default is Logic 0, noninverted modulation: used for additional power saving on top of the power-down selections in Register 0x02. MODULATOR _OUT=[I cos() ωt −Q sin(ωt)]. Bit 5: Rx PORT Fast Edge Rate Bit 2: Bypass Inv Sinc Tx Filter Setting this bit to 1 increases the output drive strength of all digital Active high configures the AD9878 to bypass the sin(x)/x com- output pins, except MCLK, REFCLK, SIGDELT, and pensation filter. Default value is 0x00 (inverse sinc filter enabled). FLAG[2:1]. These pins always have high output drive capability. Bit 3: CA Interface Mode Select Bit 7: ADC Clocked Directly from OSCIN This bit changes the format of the AD9878 3-wire CA interface to When set high, the ADC sampling clock is derived directly from a format in which the AD9878 digitally interfaces to external the input clock at OSCIN. In this mode, the clock supplied to the variable gain amplifiers. This is accomplished by changing OSCIN pin should originate from an external crystal or low jitter the interpretation of the bits in Register 0x13, Register 0x17, crystal oscillator. When this bit is low, the ADC sampling clock Register 0x1B, and Register 0x1F. See the Cable-Driver Gain is derived from the internal PLL and the frequency of the clock Control section for more detail. is equal to fOSCIN × M/8. Rev. A | Page 16 of 36 AD9878 Setting this bit to 0 (default) configures the serial interface to be Table 6. Cable-Driver Gain Control compatible with AD8321/AD8323/AD8328 variable cable gain Bits [7:4] CA Interface Transmit Word amplifiers. Setting this bit to 1 configures the serial interface to be 0000 0000 0000 (default) compatible with AD8322/AD8327 variable cable gain amplifiers. 0001 0000 0001 0010 0000 0010 Bit 5: Profile Select 0011 0000 0100 The AD9878 quadrature digital upconverter can store two 0100 0000 1000 preconfigured modulation modes, called profiles. Each profile 0101 0001 0000 defines a transmit FTW, cable-driver amplifier gain setting, and 0110 0010 0000 DAC gain setting. The profile select bit or PROFILE pin programs 0111 0100 0000 the current register profile to be used. If the PROFILE pin is used 1000 1000 0000 to switch between profiles, the profile select bit should be set to 0 and tied low. Table 7. DAC Output Fine Gain Setting REGISTERS 0x10 THROUGH 0x17— Bits [3:0] DAC Fine Gain (dB) BURST PARAMETER 0000 0.0 (default) Tx Frequency Tuning Words 0001 0.5 The FTW determines the DDS-generated carrier frequency (fC) 0010 1.0 and is formed via a concatenation of register addresses. 0011 1.5 … … The 26-bit FTW is spread over four register addresses. Bit 25 is 1110 7.0 the MSB, and Bit 0 is the LSB. The carrier frequency equation is 1111 7.5 as follows: 26 () f = FTW× f 2 C SYSCLK New data is automatically sent over the 3-wire CA interface (and DAC gain adjust) whenever the value of the active gain . Where 2000 f = M× f , andFTW< 0x SYSCLK OSCIN control register changes or a new profile is selected. The default value is 0x00 (lowest gain). Changes to FTW bytes take effect immediately. Cable-Driver Gain Control The formula for the combined output-level calculation of AD9878 fine gain and AD8327 or AD8322 coarse gain is: The AD9878 has a 3-pin interface to the AD832x family of programmable gain cable-driver amplifiers. This allows direct V =V +(fine) 2+() coarse − 19 8327 9878() 0 control of the cable driver’s gain through the AD9878. In its default mode, the complete 8-bit register value is transmitted V =V +(fine) 2+(coarse)− 14 8322 9878() 0 over the 3-wire cable amplifier (CA) interface. where: If Bit 3 of Register 0x0F is set high, Bits [7:4] of Register 0x13 fine is the decimal value of Bits [3:0]. and Register 0x17 determine the 8-bit word sent over the CA coarse is the decimal value of Bits [7:4]. interface, according to the specifications in Table 6. Bits [3:0] of V is the level at AD9878 output in dBmV for fine = 0. 9878(0) Register 0x13 and Register 0x17 determine the fine gain setting V is the level at output of AD8327 in dBmV. 8327 of the DAC output, according to specifications in Table 7. V8322 is the level at output of AD8322 in dBmV. Rev. A | Page 17 of 36 AD9878 SERIAL INTERFACE FOR REGISTER CONTROL Table 9. Bit Decodes The AD9878 serial port is a flexible, synchronous, serial N1 N0 Description communications port that allows easy interface to many 0 0 Transfer 1 byte industry-standard microcontrollers and microprocessors. 0 1 Transfer 2 bytes The interface allows read/write access to all registers that 1 0 Transfer 3 bytes configure the AD9878. Single or multiple byte transfers are 1 1 Transfer 4 bytes supported. Also, the interface can be programmed to read words either MSB first or LSB first. The AD9878 serial interface port Bits [A4:A0] determine which register is accessed during the I/O can be configured to have one bidirectional I/O (SDIO) data transfer portion of the communication cycle. For multi- pin, or two unidirectional I/O (SDIO/SDO) pins. byte transfers, this address is the starting byte address. The remaining register addresses are generated by the AD9878. GENERAL OPERATION OF THE SERIAL INTERFACE t DS There are two phases of a communication cycle with the AD9878. t SCLK CS Phase 1 is the instruction cycle, which is the writing of an in- t PWH t PWL struction byte into the AD9878, coincident with the first eight SCLK SCLK rising edges. The instruction byte provides the AD9878 t DH t DS serial port controller with information regarding the data transfer SDIO INSTRUCTION BIT 7 INSTRUCTION BIT 6 cycle, which is Phase 2 of the communication cycle. Figure 19. Timing Diagram for Register Write The Phase 1 instruction byte defines whether the upcoming data transfer is a read or write, the number of bytes in the data transfer, and the starting register address for the first byte of the data CS transfer. The first eight SCLK rising edges of each communication SCLK cycle are used to write the instruction byte into the AD9878. t DV SDIO The eight remaining SCLK edges are for Phase 2 of the commu- DATA BIT N DATA BIT N SDO nication cycle. Phase 2 is the actual data transfer between the Figure 20. Timing Diagram for Register Read AD9878 and the system controller. Phase 2 of the communication cycle is a transfer of one to four data bytes, as determined by the SERIAL INTERFACE PORT PIN DESCRIPTIONS instruction byte. Normally, using one multibyte transfer is the SCLK—Serial Clock. The serial clock pin is used to synchronize preferred method. However, single-byte data transfers are useful data transfers from the AD9878 and to run the serial port state to reduce CPU overhead when register access requires only one machine. The maximum SCLK frequency is 15 MHz. Input data byte. Registers change immediately upon writing to the last bit to the AD9878 is sampled up on the rising edge of SCLK. Output of each transfer byte. data changes upon the falling edge of SCLK. INSTRUCTION BYTE CS—Chip Select. Active low input starts and gates a commu- The R/W bit of the instruction byte determines whether a read nication cycle. It allows multiple devices to share a common or a write data transfer occurs after the instruction byte write. serial port bus. The SDO and SDIO pins go into a high impedance Logic high indicates a read operation; logic low indicates a write state when CS is high. Chip select should stay low during the operation. The [N1:N0] bits determine the number of bytes to entire communication cycle. be transferred during the data transfer cycle. The bit decodes are shown in Table 9. The timing diagrams are shown in Figure 19 SDIO—Serial Data I/O. Data is always written into the AD9878 and Figure 20. on this pin. However, this pin can be used as a bidirectional data line. The configuration of this pin is controlled by Bit 7 of Register 0x00. The default is Logic 0, which configures the SDIO Table 8. Instruction Byte Information pin as unidirectional. MSB 17 16 15 14 13 12 11 LSB 10 SDO—Serial Data Out. Data is read from this pin for protocols R/W N1 N0 A4 A3 A2 A1 A0 that use separate lines for transmitting and receiving data. In the case where the AD9878 operates in a single bidirectional I/O mode, this pin does not output data and is set to a high impedance state. Rev. A | Page 18 of 36 03277-005 03277-006 AD9878 MSB/LSB TRANSFERS NOTES ON SERIAL PORT OPERATION The AD9878 serial port can support either MSB-first or LSB-first The AD9878 serial port configuration bits reside in Bit 6 and data formats. This functionality is controlled by the LSB-first bit Bit 7 of Register Address 0x00. Note that the configuration in Register 0x00. changes immediately upon writing to the last bit of the register. For multibyte transfers, writing to this register might occur The AD9878 default serial port mode is MSB-first (see Figure 21), during a communication cycle. Measures must be taken to which is programmed by setting Register 0x00 low. In MSB-first compensate for this new configuration for the remaining bytes of mode, the instruction byte and data bytes must be written from the current communication cycle. the MSB to the LSB. In MSB-first mode, the serial port internal byte address generator decrements for each byte of the multibyte The same considerations apply when setting the reset bit in communication cycle. When decrementing from 0x00, the Register Address 0x00. All other registers are set to their default address generator changes to 0x1F. values, but the software reset does not affect the bits in Register Address 0x00. It is recommended to use only single-byte transfers When the LSB-first bit in Register 0x00 is set active high, the when changing serial port configurations or initiating a software AD9878 serial port is in LSB-first format (Figure 22). In LSB- reset. A write to Bit 1, Bit 2, and Bit 3 of Address 0x00 with the first mode, the instruction byte and data bytes must be written same logic levels as Bit 7, Bit 6, and Bit 5 (bit pattern: XY1001YX from the LSB to the MSB. In LSB-first mode, the serial port binary) allows the user to reprogram a lost serial port config- internal byte address generator increments for each byte of the uration and to reset the registers to their default values. A multibyte communication cycle. When incrementing from second write to Address 0x00, with the reset bit low and the 0x1F, the address generator changes to 0x00. serial port configuration as specified above (XY), reprograms the OSCIN multiplier setting. A changed f frequency is SYSCLK stable after a maximum of 200 f cycles (wake-up time). MCLK INSTRUCTION CYCLE DATA TRANSFER CYCLE CS SCLK SDIO R/W N1 N0 A4 A3 A2 A1 A0 D7 D6 D2 D1 D0 n n 0 0 0 D7 D6 D2 D1 D0 SDO n n 0 0 0 Figure 21. Serial Register Interface Timing, MSB-First Mode INSTRUCTION CYCLE DATA TRANSFER CYCLE CS SCLK A0 A1 A2 A3 A4 N0 N1 R/W D0 D1 D2 D6 D7 SDIO 0 0 0 n n D0 D1 D2 D6 D7 SDO 0 0 0 n n Figure 22. Serial Register Interface Timing, LSB-First Mode Rev. A | Page 19 of 36 03277-004 03277-003 AD9878 THEORY OF OPERATION For a general understanding of the AD9878, refer to Figure 23, a The 12-bit and 10-bit IF ADCs can convert direct IF inputs of block diagram of the device architecture. The device consists of a up to 70 MHz and run at sample rates of up to 29 MSPS. A video transmit path, receive path, and auxiliary functions, such as a PLL, input with an adjustable signal clamping level, along with the a ∑-∆ DAC, a serial control port, and a cable amplifier interface. 10-bit ADC, allow the AD9878 to process an NTSC and a QAM channel simultaneously. The transmit path contains an interpolation filter, a complete quadrature digital upconverter, an inverse sinc filter, and a 12-bit The programmable ∑-∆ DAC can be used to control external current output DAC. components, such as variable gain amplifiers (VGAs) or voltage- controlled tuners. The CA port provides an interface to the The receive path contains a 10-bit ADC and dual 12-bit ADCs. AD832x family of programmable gain amplifier (PGA) cable All internally required clocks and an output system clock are drivers, enabling host processor control via the MxFE serial generated by the PLL from a single crystal or clock input. port (SPORT). QUADRATURE MODULATOR DAC GAIN CONTROL FSADJ DATA CIC LPF FIR LPF ASSEMBLER –1 SINC COS 6 12 12 BYPASS TxIQ[5:0] I 4 4 12 Tx OUTPUT MUX DAC –1 SINC 12 12 TxSYNC Q 4 4 (f ) SYSCLK SIN (f ) OSCIN DDS (f ) IQCLK PLL ÷4 ÷4 XTAL OSCIN× M MCLK (f ) MCLK ÷R REFCLK OSCIN FLAG0 8 Σ-∆ INPUT Σ-∆ Σ-∆ OUTPUT 3 CA CA PORT INTERFACE ÷8 PROFILE PROFILE SELECT FLAG[2:1] 4 SERIAL ÷2 SDIO INTERFACE f ) ( 10 OSCIN ADC IF10 INPUT 5 5 IF10[4:0] MUX IF10 ÷2 RxSYNC Rx PORT (f ) OSCIN 12 IF12B INPUT ADC MUX 12 12 VIDEO IN MUX IF12[11:0] IF12 12 ADC MUX IF12A INPUT – + AD9878 CLAMP LEVEL DAC Figure 23. AD9878 Block Diagram Rev. A | Page 20 of 36 03277-007 AD9878 t SU MCLK t HU TxSYNC TxI[11:6] TxI[5:0] TxQ[11:6] TxQ[5:0] TxI[11:6] TxI[5:0] TxQ[11:6] TxQ[5:0] TxI[11:6] TxI[5:0] TxIQ Figure 24. Tx Timing Diagram to the sample rate increase, the half-band filters provide the TRANSMIT PATH low-pass filtering characteristics necessary to suppress the spectral The transmit path contains an interpolation filter, a complete images between the original sampling frequency and the new quadrature digital upconverter, an inverse sinc filter, and a 12-bit (16× higher) sampling frequency. current output DAC. The maximum output current of the DAC is set by an external resistor. The Tx output PGA provides additional HALF-BAND FILTERS (HBFs) transmit signal level control. The transmit path interpolation HBF 1 and HBF 2 are both interpolating filters, each of which filter provides an upsampling factor of 16 with an output signal doubles the sampling rate. Together, HBF 1 and HBF 2 have bandwidth as high as 4.35 MHz for <1 dB droop. Carrier 26 taps and increase the sampling rate by a factor of 4 frequencies up to 65 MHz with 26 bits of frequency tuning (4 × f or 8 × f ). IQCLK NYQ resolution can be generated by the direct digital synthesizer (DDS). The transmit DAC resolution is 12 bits, and it can run at In relation to phase response, both HBFs are linear phase filters. sampling rates of up to 232 MSPS. Analog output scaling from As such, virtually no phase distortion is introduced within the pass 0 dB to 7.5 dB in 0.5 dB steps is available to preserve SNR when band of the filters. This is an important feature, because phase dis- reduced output levels are required. tortion is generally intolerable in a data transmission system. DATA ASSEMBLER CASCADE INTEGRATOR COMB (CIC) FILTER The AD9878 data path operates on two 12-bit words, the I and Q The CIC filter is configured as a programmable interpolator components, that form a complex symbol. The data assembler and provides a sample rate increase by a factor of 4. The builds the 24-bit complex symbol from four consecutive 6-bit frequency response of the CIC filter is given by: words read over the TxIQ [5:0] bus. These words are strobed 3 3 −j() 2πf() 4 into the data assembler synchronous to the master clock (MCLK). ⎡ ⎤ 1−e ⎡ sin() 4πf ⎤ 1 1 ⎛ ⎞ ⎛ ⎞ H() f −⎢ ⎥ = ⎜ ⎟ ⎢⎜ ⎟ ⎥ j2πf A high level on TxSYNC signals the start of a transmit symbol. ⎝ 4⎠ 1−e ⎝ 4⎠ sin() πf ⎢ ⎥ ⎢ ⎥ ⎣ ⎦ ⎣ ⎦ The first two 6-bit words of the symbol form the I component; the second two 6-bit words form the Q component. Symbol COMBINED FILTER RESPONSE components are assumed to be in twos complement format. The The combined frequency response of the HBF and CIC filters timing of the interface is fully described in the Transmit Timing limits the input signal bandwidth that can be propagated through section. The I/Q sample rate f puts a bandwidth limit on the IQCLK the AD9878.The usable bandwidth of the filter chain limits the maximum transmit spectrum. This is the familiar Nyquist limit maximum data rate that can be propagated through the AD9878. (hereafter referred to as f ) and is equal to half f . NYQ IQCLK A look at the pass-band detail of the combined filter response (Figure 25) indicates that to maintain an amplitude error of TRANSMIT TIMING 1 dB or less, signal bandwidth is restricted to about 60% or less The AD9878 has a master clock and expects 6-bit, multiplexed of fNYQ. TxIQ data upon each rising edge (see Figure 24). Transmit symbols are framed with the TxSYNC input. TxSYNC high Max BW (1dB droop) = 0.60 * fMCLK/8 indicates the start of a transmit symbol. Four consecutive 6-bit Thus, in order to keep the bandwidth of the data in the flat data packages form a symbol (I MSB, I LSB, Q MSB, and Q LSB). portion of the filter pass band, the user must oversample the INTERPOLATION FILTER baseband data by at least a factor of two prior to presenting it to the AD9878. Note that without oversampling, the Nyquist Once through the data assembler, the IQ data streams are fed through a 4× FIR low-pass filter and a 4× cascaded integrator bandwidth of the baseband data corresponds to fNYQ. As such, comb (CIC) low-pass filter. The combination of these two filters the upper end of the data bandwidth suffers 6 dB or more of results in the sample rate increasing by a factor of 16. In addition attenuation due to the frequency response of the digital filters. Furthermore, if the baseband data applied to the AD9878 has Rev. A | Page 21 of 36 03277-008 AD9878 been pulse shaped, there is an additional concern. Typically, Tx SIGNAL LEVEL CONSIDERATIONS pulse shaping is applied to the baseband data via a filter with a The quadrature modulator itself introduces a maximum gain of raised cosine response. In such cases, an α value is used to modify 3 dB in signal level. To visualize this, assume that both the I and the bandwidth of the data, where the value of α is such that Q data are fixed at the maximum possible digital value, x. Then, the output of the modulator, z, is 0<α< 1. [ ( ) ( )] z= x cos ωt −x sin ωt A value of 0 causes the data bandwidth to correspond to the Nyquist bandwidth. A value of 1 causes the data bandwidth to Q be extended to twice the Nyquist bandwidth. Thus, with 2× over- XZ sampling of the baseband data and α = 1, the Nyquist bandwidth I of the data corresponds with the I/Q Nyquist bandwidth. As stated X earlier, this results in problems near the upper edge of the data bandwidth due to the frequency response of the filters. The maximum value of α that can be implemented is 0.45, because the Figure 26. 16-Quadrature Modulation data bandwidth becomes It can be shown that |z| assumes a maximum value of 2 2 1 2(1+α) f = 0.725f z= x +x =x 2 (a gain of +3 dB). However, if the NYQ NYQ same number of bits represent |z| and x, an overflow occurs. which puts the data bandwidth at the extreme edge of the flat To prevent this, an effective −3 dB attenuation is internally portion of the filter response. implemented on the I and Q data path: If a particular application requires an α value between 0.45 and 1, z= 1 2+ 1 2=x the user must oversample the baseband data by at least a factor of 4. Over the frequency range of the data to be transmitted, the The following example assumes a peak rms level of 10 dB: combined HBF 1, HBF 2, and CIC filters introduce a worst-case droop of less than 0.2 dB. MaximumSymbolComponent InputValue= 1 ± 2047 LSBs− 0.2 dB=± 2000 LSBs 0 MaximumComplex Input RMSValue= –1 2000 LSBs± 6 dB−Peakrms() dB = 1265 LSBs rms –2 The maximum complex input rms value calculation uses both I and Q symbol components that add a factor of two (6 dB) –3 to the formula. Table 10 shows typical I-Q input test signals with amplitude levels related to 12-bit full scale (FS). –4 –5 Table 10. I-Q Input Test Signals –6 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Analog Modulator FREQUENCY RELATIVE TO I/Q NYQ BW Output Digital Input Input Level Output Level Single Tone I = cos(f) FS − 0.2 dB FS − 3.0 dB Figure 25. Cascaded Filter Pass Band (fC − f) Q = cos(f + 90°) FS − 0.2 dB DIGITAL UPCONVERTER = −sin(f) The digital quadrature modulator stage following the CIC filters Single Tone I = cos(f) FS − 0.2 dB FS − 3.0 dB is used to frequency shift (upconvert) the baseband spectrum of (fC + f) Q = cos(f + 270°) FS − 0.2 dB = +sin(f) the incoming data stream to the desired carrier frequency. The Dual Tone I = cos(f) FS − 0.2 dB FS carrier frequency is controlled numerically by a direct digital FS − 0.2 dBFS synthesizer (DDS). The DDS uses the internal system clock (f ± f) Q = cos(f + 180°) FS − 0.2 dB C (f ) to generate the desired carrier frequency with a high SYSCLK = −cos(f) or degree of precision. The carrier is applied to the I and Q Q = +cos(f) multipliers in a quadrature fashion (90° phase offset) and summed to yield a data stream that is the modulated carrier. The modulated carrier becomes the 12-bit sample sent to the DAC. Rev. A | Page 22 of 36 MAGNITUDE (dB) 03277-009 03277-010 AD9878 capacitance and inductance. The load can be a simple resistor to Tx THROUGHPUT AND LATENCY ground, an op amp current-to-voltage converter, or a transformer- Data inputs affect the output fairly quickly, but remain effective coupled circuit. It is best not to directly drive a highly reactive due to the AD9878 filter characteristics. Data transmit latency load, such as an LC filter. Driving an LC filter without a through the AD9878 is easiest to describe in terms of fSYSCLK clock transformer requires that the filter be doubly terminated for cycles (4 × f ). The numbers provided indicate the number of MCLK best performance—that is, both the filter input and output should f cycles before the AD9878 output responds to a change in SYSCLK be resistively terminated with the appropriate values. The parallel the input. combination of the two terminations determines the load that the AD9878 sees for signals within the filter pass band. For Latency of I/Q data from the time it enters the data assembler example, a 50 Ω terminated input/output low-pass filter looks (AD9878 input) to the time of DAC output is 119 fSYSCLK clock like a 25 Ω load to the AD9878. The output compliance voltage cycles (29.75 fMCLK cycles). DC values applied to the data assembler input take up to 176 fSYSCLK clock cycles (44 fMCLK cycles) to of the AD9878 is −0.5 V to +1.5 V. Any signal developed at the propagate and settle at the DAC output. DAC output should not exceed 1.5 V; otherwise, signal distortion results. Furthermore, the signal can extend below ground as much Frequency hopping is accomplished via changing the PROFILE as 0.5 V without damage or signal distortion. The AD9878 true input pin. The time required to switch from one frequency to and complement outputs can be differentially combined for another is less than 232 f cycles (58.5 f cycles). SYSCLK MCLK common-mode rejection using a broadband 1:1 transformer. DAC Using a grounded center tap results in signals at the AD9878 DAC A 12-bit digital-to-analog converter (DAC) is used to convert the output pins that are symmetrical about ground. As previously digitally processed waveform into an analog signal. The worst- mentioned, by differentially combining the two signals, the user case spurious signals due to the DAC are the harmonics of the can provide some degree of common-mode signal rejection. fundamental signal and their aliases (see the Analog Devices A differential combiner can consist of a transformer or an DDS tutorial at www.analog.com/dds). The conversion process op amp. The object is to combine or amplify the difference produces aliased components of the fundamental signal at between only two signals and to reject any common—usually n× f ± f (n= 1, 2, 3). These are typically filtered SYSCLK CARRIER undesirable—characteristics, such as 60 Hz hum or clock with an external RLC filter at the DAC output. It is important feedthrough, that is equally present on both signals. for this analog filter to have a sufficiently flat gain and linear phase response across the bandwidth of interest to avoid AD9878 AD832x modulation impairments. A relatively inexpensive seventh- LOW-PASS order, elliptical, low-pass filter is sufficient to suppress the DAC Tx FILTER 75Ω aliased components for HFC network applications. 3 CA The AD9878 provides true and complement current outputs. The CA_EN VARIABLE GAIN CA_DATA full-scale output current is set by the RSET resistor at Pin 49 and CA_CLK CABLE DRIVER the DAC gain register. Assuming maximum DAC gain, the value AMPLIFIER of R for a full-scale I is determined using the equation: SET OUT Figure 27. Cable Amplifier Connection R = 32V I = 39.4 I Connecting the AD9878 true and complement outputs to the SET DACRSET OUT OUT differential inputs of the programmable gain cable drivers For example, if a full-scale output current of 20 mA is desired, AD8321/AD8323 or AD8322/AD8327 (see Figure 27) then R = (39.4/0.02), or approximately 2 kΩ. SET provides an optimized solution for the standard compliant cable modem upstream channel. The cable driver’s gain The following equation calculates the full-scale output current, can be programmed through a direct 3-wire interface including the programmable DAC gain control: using the AD9878 profile registers. () −7.5+ 0.5N 20 GAIN I = 39.4 R × 10 OUT SET PROGRAMMING THE AD8321/AD8323 OR AD8322/AD8327/AD8238 CABLE-DRIVER where NGAIN is the value of DAC fine gain control [3:0]. AMPLIFIERS The full-scale output current range of the AD9878 is 4 to Users can program the gain of the AD832x family of cable-driver 20 mA. Full-scale output currents outside this range degrade amplifiers via the AD9878 cable amplifier control interface. Two SFDR performance. SFDR is also slightly affected by output (one per profile) 8-bit registers within the AD9878 store the gain matching—that is, the two outputs should be terminated equally value to be written to the serial 3-wire port. Typically, either the for best SFDR performance. The output load should be located AD8321/AD8323 or AD8322/AD8327 variable gain cable as close as possible to the AD9878 package to minimize stray amplifiers are connected to the chip’s 3-wire cable amplifier Rev. A | Page 23 of 36 03277-011 AD9878 interface. The Tx gain control select bit in Register 0x0F changes 30% of f . For a 65 MHz carrier, the system clock required is SYSCLK the interpretation of the bits in Register 0x13, Register 0x17, above 216 MHz. The OSCIN multiplier function maintains Register 0x1B, and Register 0x1F. See Figure 28 and the clock integrity, as evidenced by the part’s excellent phase noise Cable-Driver Gain Control section. characteristics and low clock-related spur in the output spectrum. 8 t 8 t MCLK MCLK 4 t External loop filter components, consisting of a series resistor MCLK 4 t MCLK 8 t (1.3 kΩ) and capacitor (0.01 µF), provide the compensation MCLK CA_EN zero for the OSCIN multiplier PLL loop. The overall loop performance is optimized for these component values. CA_CLK CLOCK AND OSCILLATOR CIRCUITRY CA_DATA MSB LSB The AD9878’s internal oscillator generates all sampling clocks Figure 28. Cable Amplifier Interface Timing from a simple, low cost, parallel resonance, fundamental fre- Data transfers to the programmable gain cable-driver amplifier quency quartz crystal. Figure 29 shows how the quartz crystal is are initiated by the following conditions: connected between OSCIN (Pin 61) and XTAL (Pin 60) with parallel resonant load capacitors, as specified by the crystal • Power-Up and Hardware Reset: Upon initial power-up and manufacturer. The internal oscillator circuitry can also be every hardware reset, the AD9878 clears the contents of the overdriven by a TTL-level clock applied to OSCIN with gain control registers to 0, which defines the lowest gain XTAL left unconnected. setting of the AD832x. Thus, the AD9878 writes all 0s out of the 3-wire cable amplifier control interface. f = f ×M OSCIN MCLK • Software Reset: Writing a 1 to Bit 5 of Address 0x00 initiates An internal PLL generates the DAC sampling frequency, fSYSCLK, a software reset. Upon a software reset, the AD9878 clears by multiplying the OSCIN frequency by M. The MCLK signal the contents of the gain control registers to 0 for the lowest (Pin 23), f , is derived by dividing f by 4. MCLK SYSCLK gain and sets the profile select to 0. The AD9878 writes all 0s out of the 3-wire cable amplifier control interface if the f = f ×M SYSCLK OSCIN gain is previously on a different setting (different from 0). f = f ×M 4 MCLK OSCIN • Change in Profile Selection: The AD9878 samples the PROFILE input pin together with the two profile select bits An external PLL loop filter (Pin 57), consisting of a series resistor and writes to the AD832x gain control registers when a and ceramic capacitor (Figure 29: R1 = 1.3 kΩ, C12 = 0.01 µF), change in profile and gain is determined. The data written is required for stability of the PLL. Also, a shield surrounding to the cable-driver amplifier comes from the AD9878 gain these components is recommended to minimize external noise control register associated with the current profile. coupling into the PLL’s voltage-controlled oscillator input (guard trace connected to AVDDPLL). • Write to the AD9878 Cable-Driver Amplifier Control Registers: The AD9878 writes gain control data associated Figure 23 shows that ADCs are either sampled directly by a with the current profile to the AD832x when the selected low jitter clock at OSCIN or by a clock that is derived from the AD9878 cable-driver amplifier gain setting is changed. Once PLL output. Operating modes can be selected in Register 0x08. a new, stable gain value is detected (48 to 64 MCLK cycles Sampling the ADCs directly with the OSCIN clock requires that after initiation) a data write starts with going low. CA_EN MCLK is programmed to be twice the OSCIN frequency. The AD9878 always finishes a write sequence to the cable- PROGRAMMABLE CLOCK OUTPUT REFCLK driver amplifier once it is started. The logic controlling data The AD9878 provides an auxiliary output clock on Pin 69, transfers to the cable-driver amplifier uses up to REFCLK. The value of the MCLK divider bit field, R, determines 200 MCLK cycles and is designed to prevent erroneous its output frequency, as shown in the following equations: write cycles from occurring. f = f R , for R= 2 to 63 OSCIN CLOCK MULTIPLIER REFCLK MCLK The AD9878 can accept either an input clock into the OSCIN f = f , for R= 0 REFCLK OSCIN pin or a fundamental-mode crystal across the OSCIN and XTAL pins as the device’s main clock source. The internal PLL In its default setting (0x00 in Register 0x01), the REFCLK pin then generates the fSYSCLK signal from which all other internal provides a buffered output of fOSCIN. signals are derived. The DAC uses fSYSCLK as its sampling clock. For DDS applications, the carrier is typically limited to about Rev. A | Page 24 of 36 03277-012 AD9878 CP2 CP1 10µF 10µF C4 C5 C6 C1 C2 C3 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF CP1 10µF C1 C2 C3 0.1µF 0.1µF 0.1µF 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 DRGND 1 75 REFT10 DRVDD 2 74 REFB10 (MSB) IF12(11) 3 73 AGND10 IF12(10) 4 72 AVDD10 IF12(9) 5 71 DRVDD IF12(8) 6 70 DRGND IF12(7) 7 69 REFCLK IF12(6) 8 68 SIGDELT IF12(5) 9 67 FLAG1 IF12(4) 10 66 FLAG2 IF12(3) 11 65 CA_EN C10 AD9878 IF12(2) 12 64 CA_DATA 20pF TOP VIEW IF12(1) 13 63 CA_CLK (Not to Scale) IF12(0) 14 62 DVDDOSC C11 20pF (MSB) IF10(4) 15 61 OSCIN IF10(3) 16 60 XTAL IF10(2) 17 59 DGNDOSC GUARD TRACE IF10(1) 18 58 AGNDPLL IF10(0) 19 57 PLLFILT R1 C12 RxSYNC 20 56 AVDDPLL 1.3kΩ 0.01µF DRGND 21 55 DVDDPLL DRVDD 22 54 DGNDPLL MCLK 23 53 AVDDTx DVDD 24 52 Tx+ 25 51 DGND Tx– 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 C13 R SET 0.1µF 4.02Ω Figure 29. Basic Connection Diagram Rev. A | Page 25 of 36 TxSYNC AVDD (MSB) TxIQ(5) AGND TxIQ(4) VIDEO IN TxIQ(3) AGND TxIQ(2) IF12A+ TxIQ(1) IF12A– TxIQ(0) AGND DVDD AVDD DGND REFT12A DVDD REFB12A DGND AVDD PROFILE AGND RESET IF12B+ DVDD IF12B– DGND AGND SCLK AVDD CS REFT12B SDIO REFB12B SDO AVDD DGNDTx AGND DVDDTx AVDD10 PWRDN AGND10 REFIO IF10+ FSADJ IF10– AGNDTx AGND 03277-013 AD9878 POWER-UP SEQUENCE RESET Upon initial power-up, the RESET pin should be held low until the To initiate a hardware reset, the RESET pin should be held low power supply is stable (see Figure 30). Once is deasserted, for at least 100 ns. All internally generated clocks, except REFCLK, RESET stop during reset. The rising edge of resets the PLL clock RESET the AD9878 can be programmed over the serial port. The on- chip PLL requires a maximum of 1 ms after the rising edge of multiplier and reinitializes the programmable registers to their RESET or a change of the multiplier factor (M) to completely default values. The same sequence as described in the Power-Up Sequence section should be followed after a reset or change in M. settle. It is recommended that the pin is held low during PWRDN the reset and PLL settling time. Changes to ADC clock select A software reset (writing 1 into Bit 5 of Register 0x00) is func- (Register 0x08) or System Clock Divider N (Register 0x01) should tionally equivalent to a hardware reset, but does not force be programmed before the rising edge of . Once the PLL PWRDN Register 0x00 to its default value. is frequency locked and after the PWRDN pin is brought high, TRANSMIT POWER-DOWN transmit data can be sent reliably. If the pin cannot be PWRDN held low throughout the reset and PLL settling time period, A low level on the pin stops all clocks linked to the PWRDN the power-down digital Tx bit, or the PWRDN pin, should be digital transmit data path and resets the CIC filter. Deasserting pulsed after the PLL has settled. This ensures correct transmit PWRDN reactivates all clocks. The CIC filter is held in a reset filter initialization. state for 80 MCLK cycles after the rising edge of to PWRDN allow for flushing of the half-band filters with new input data. V S Transmit data bursts should be padded with at least 20 symbols of null data directly before the pin is deasserted. PWRDN RESET Immediately after the PWRDN pin is deasserted, the transmit 1ms MIN. burst should start with a minimum of 20 null data symbols (see 5MCLK MIN. PWRDN Figure 31). This avoids unintended DAC output samples caused by the transmit path latency and filter settling time. Figure 30. Power-Up Sequence for Tx Data Path Software power-down digital Tx (Bit 5 in Register 0x02) is func- tionally equivalent to the hardware PWRDN pin and takes effect immediately after the last register bit is written over the serial port. PWRDN 5MCLK MIN. 20 NULL SYMBOLS DATA SYMBOLS 20 NULL SYMBOLS TxIQ 0 0 0 0 00 00 TxSYNC Figure 31. Timing Sequence to Flush Tx Data Path Rev. A | Page 26 of 36 03277-014 03277-015 AD9878 RECEIVE PATH (Rx) ∑-∆ OUTPUTS The AD9878 includes three high speed, high performance ADCs. An on-chip ∑-∆ output provides a digital logic bit stream with The 10-bit and dual 12-bit direct-IF ADCs deliver excellent under- an average duty cycle that varies between 0% and (255/256)%, sampling performance with input frequencies as high as 70 MHz. depending on the programmed code, as shown in Figure 32. The sampling rate can be as high as 29 MSPS. The ADC sampling 8 t MCLK frequency can be derived directly from the OSCIN signal, or from 256× 8 t MCLK the on-chip OSCIN multiplier. For highest dynamic performance, 00h choose an OSCIN frequency that can be directly used as the 01h ADC sampling clock. Digital 12-bit ADC outputs are multiplexed 02h to one 12-bit bus, clocked by a frequency (fMCLK) four times the sampling rate. The IF ADCs use a multiplexer to a 12-bit interface 80h with an output word rate of f . MCLK FFh IF10 AND IF12 ADC OPERATION 256× 8 t MCLK 8 t MCLK The IF10 and IF12 ADCs have a common architecture and share several characteristics from an applications standpoint. Figure 32. ∑-∆ Output Signals Most of the information in the following section is applicable to This bit stream can be low-pass filtered to generate a both IF ADCs; differences, where they exist, are highlighted. programmable dc voltage of Input Signal Range and Digital Output Codes V =[(∑- ∆Code 256)×V ]+V DC H L The IF ADCs have differential analog inputs labeled IF+ and IF−. The signal input, VAIN, is the voltage difference between the two where: input pins, VAIN = VIF+ − VIF−. The full-scale input voltage range is V =V − 0.6 V H DRVDD determined by the internal reference voltages, REFT and REFB, V = 0.4 V which define the top and bottom of the scale. The peak input L voltage to the ADC is the difference between REFT and REFB, In cable set-top box applications, the output can be used to which is 1 V p-p. This results in an ADC full-scale input voltage control external variable gain amplifiers or RF tuners. A of 2 VPPD. The digital output codes are straight binary and are single-pole, RC, low-pass filter provides sufficient filtering shown in Table 11. (see Figure 33). In more demanding applications, where additional gain, level-shift, or drive capability is required, consider using a first- or second-order filter (see Figure 34). Table 11. Digital Output Codes IF12[11:0] Input Signal Voltage AD9878 DAC 111…111 VAIN ≥ +1.0 V 8 R CONTROL Σ-∆ DC (V TO V ) L H 111…111 VAIN = +1.0 V − 1 LSB WORD C 111…110 VAIN = +1.0 V − 2 LSB MCLK ÷8 … … 100…001 V = 0 V + 1 LSB AIN TYPICAL: R = 50kΩ 100…000 V = 0.0 V AIN C = 0.01µF 011…111 VAIN = 0 V − 1 LSB f = 1/(2πRC) = 318Hz –3dB … … Figure 33. ∑-∆ RC Filter 000…001 V = −1.0 V + 2 LSB AIN C 000…000 V = −1.0 V AIN R1 R 000…000 V < −1.0 V AIN AD9878 SIGMA-DELTA V R OUT Σ-∆ OP250 V SD C R V OFFSET V = (V + V ) (1 + R/R1)/2 OUT SD OFFSET TYPICAL: R = 50kΩ C = 0.01µF f = 1/(2πRC) = 318Hz –3dB Figure 34. ∑-∆ Active Filter with Gain and Offset Rev. A | Page 27 of 36 03277-016 03277-018 03277-017 AD9878 Driving the Input Receive Timing The IF ADCs have differential switched capacitor sample-and- The AD9878 sends multiplexed data to the IF10 and IF12 outputs hold amplifier (SHA) inputs. The nominal differential input upon every rising edge of MCLK. RxSYNC frames the start of impedance is 4.0 kΩ||3 pF. This impedance can be used as the each IF10 data symbol. The 10-bit and 12-bit ADCs are read effective termination impedance when calculating filter transfer completely upon every second MCLK cycle. RxSYNC is high characteristics and voltage signal attenuation from nonzero source for every second 10-bit ADC data if the 10-bit ADC is not in impedances. For best performance, additional requirements must power-down mode. The Rx timing diagram is shown in Figure 36. be met by the signal source. The SHA has input capacitors that t EE must be recharged each time the input is sampled. This results in a dynamic input current at the device input, and demands that M/N = 2 REFCLK t MD t OD the source has low (<50 Ω) output impedance at frequencies up to the ADC sampling frequency. Also, the source must have MCLK settling of better than 0.1% in less than half the ADC clock period. IF10 DATA IF10[9:5] IF10[4:0] IF10[9:5] IF10[4:0] IF10[9:5] IF10[4:0] Another consideration for getting the best performance from the ADC inputs is the dc biasing of the input signal. Ideally, the signal RxSYNC should be biased to a dc level equal to the midpoint of the ADC IF12 DATA IF12A IF12B IF12B IF12B IF12A IF12B reference voltages, REFT12 and REFB12. Nominally, this level is 1.2 V. When ac-coupled, the ADC inputs self-bias to this voltage Rx PORT TIMING (DEFAULT MODE: MUXED IF12 ADC DATA) and require no additional input circuitry. Figure 35 illustrates a t EE recommended circuit that eases the burden on the signal source M/N = 2 by isolating its output from the ADC input. The 33 Ω series REFCLK t t MD OD termination resistors isolate the amplifier outputs from any capacitive load, which typically improves settling time. The series MCLK capacitors provide ac signal coupling, which ensures that the IF10[9:5] IF10[4:0] IF10[9:5] IF10[4:0] IF10[9:5] IF10[4:0] IF10 DATA ADC inputs operate at the optimal dc-bias voltage. The shunt capacitor sources the dynamic currents required to charge the RxSYNC SHA input capacitors, removing this requirement from the ADC buffer. The values of CC and CS should be calculated to IF DATA IF12A OR IF12B IF12A OR IF12B IF12A OR IF12B determine the correct HPF and LPF corner frequencies. Rx PORT TIMING (OUTPUT DATA FROM ONLY ONE IF12 ADC) C C 33Ω Figure 36. Rx Port Timing AIN+ V C S S C C 33Ω AIN– Figure 35. Simple ADC Drive Configuration Rev. A | Page 28 of 36 03277-019 03277-020 AD9878 ADC VOLTAGE REFERENCES VIDEO INPUT The AD9878 has three independent internal references for its For sampling video-type waveforms, such as NTSC and PAL 10-bit and 12-bit ADCs. Both 12-bit and 10-bit ADCs are signals, the video input channel provides black-level clamping. designed for 2 V p-p input voltages and have their own internal Figure 37 shows the circuit configuration for using the video reference. Figure 29 shows the proper connections of the REFT channel input (Pin 98). An external blocking capacitor is used and REFB reference pins. External references might be necessary with the on-chip video clamp circuit to level-shift the input signal for systems that require high accuracy gain matching between to a desired reference point. The clamp circuit automatically ADCs, or for improvements in temperature drift and noise senses the most negative portion of the input signal and adjusts characteristics. External references REFT and REFB must be the voltage across the input capacitor. This forces the black level centered at AVDD/2, with offset voltages as specified by the of the input signal to be equal to the value programmed in the following equations: clamp level register (Register Address 0x07). REFT−10,−12 :AVDD 2+ 0.5 V By default, the video input is disabled and disconnected from both ADCs. By setting Register 0x07, Bit 7 = 1, the video input REFT−10,−12 :AVDD 2− 0.5 V is enabled and connected to the ADC input as determined by the state of Reg 0x03, Bit 6 ( 0= ADC12A connected, 1 = A differential level of 1 V between the reference pins results in a ADC12B connected.) 2 V p-p ADC input level AIN. Internal reference sources can be powered down when external references are used (Address 0x02). CLAMP LEVEL + FS/2 CLAMP LEVEL AD9878 VIDEO INPUT BUFFER 0.1µF 12 ADC 2mA – + CLAMP DAC LEVEL LPF OFFSET Figure 37. Video Clamp Circuit Input Rev. A | Page 29 of 36 03277-021 AD9878 PCB DESIGN CONSIDERATIONS Although the AD9878 is a mixed-signal device, the part should be The DVDD portion of the plane carries the current used to power treated as an analog component. The on-chip digital circuitry is the digital portion of the MxFE to the device. This should be designed to minimize the impact of digital switching noise on the treated similarly to the 3-VDD power plane and be kept from going operation of the analog circuits. Following the recommendations underneath the MxFE or analog components. The MxFE should in this section helps achieve the best performance from the MxFE. largely sit above the AVDD portion of the power plane. The AVDD and DVDD power planes can be fed from the same low COMPONENT PLACEMENT noise voltage source; however, they should be decoupled from The following guidelines for component placement are each other to prevent the noise generated in the DVDD portion recommended to achieve optimal performance: of the MxFE from corrupting the AVDD supply. This can be done by using ferrite beads between the voltage source and DVDD, and • Manage the path of return currents to ensure that high between the source and AVDD. Both DVDD and AVDD should frequency switching currents from the digital circuits do not have a low ESR, bulk-decoupling capacitor on the MxFE side of flow into the ground plane under the MxFE or analog circuits. the ferrite as well as low ESR- and ESL-decoupling capacitors on each supply pin (for example, the AD9878 requires 17 power • Keep noisy digital signal paths and sensitive receive signal supply decoupling capacitors). The decoupling capacitors should paths as short as possible. be placed as close as possible to the MxFE supply pins. An example of proper decoupling is shown in the AD9878 evaluation • Keep digital (noise-generating) and analog (noise-susceptible) board’s two-page schematic (Figure 38 and Figure 39). circuits as far apart as possible. GROUND PLANES To best manage the return currents, pure digital circuits that generate high switching currents should be closest to the power In general, if the component placing guidelines discussed earlier supply entry. This keeps the highest frequency return current can be implemented, it is best to have at least one continuous paths short and prevents them from traveling over the sensitive ground plane for the entire board. All ground connections should MxFE and analog portions of the ground plane. Also, these be as short as possible. This results in the lowest impedance return circuits should be generously bypassed at each device to further paths and the quietest ground connections. If the components reduce high frequency ground currents. The MxFE should be cannot be placed in a manner that keeps the high frequency placed adjacent to the digital circuits, such that the ground return ground currents from traversing under the MxFE and analog currents from the digital sections do not flow into the ground components, it might be necessary to put current-steering plane under the MxFE. The analog circuits should be placed channels into the ground plane to route the high frequency furthest from the power supply. The AD9878 has several pins that currents around these sensitive areas. These current-steering are used to decouple sensitive internal nodes: REFIO, REFB12A, channels should be used only when and where necessary. REFT12A, REFB12B, REFT12B, REFB10, and REFT10. The SIGNAL ROUTING decoupling capacitors connected to these points should have low ESR and ESL, be placed as close as possible to the MxFE, and be The digital Rx and Tx signal paths should be as short as possible. connected directly to the analog ground plane. The resistor Also, these traces should have a controlled impedance of about connected to the FSADJ pin and the RC network connected to 50 Ω. This prevents poor signal integrity and the high currents the PLLFILT pin should also be placed close to the device and that can occur during undershoot or overshoot caused by ringing. connected directly to the analog ground plane. If the signal traces cannot be kept shorter than about 1.5 inches, then series termination resistors (33 Ω to 47 Ω) should be placed POWER PLANES AND DECOUPLING close to all signal sources. It is a good idea to series terminate all The AD9878 evaluation board (Figure 38 and Figure 39) clock signals at their source, regardless of trace length. The receive demonstrates a good power supply distribution and decoupling signals are the most sensitive signals on the evaluation board. strategy. The board has four layers: two signal layers, one ground Careful routing of these signals is essential for good receive path plane, and one power plane. The power plane is split into a 3-V DD performance. The IF+/IF− signals form a differential pair and section that is used for the 3 V digital logic circuits, a DVDD should be routed together. By keeping the traces adjacent to each section that is used to supply the digital supply pins of the other, noise coupled onto the signals appears as common mode AD9878, an AVDD section that is used to supply the analog and is largely rejected by the MxFE receive input. Keeping the supply pins of the AD9878, and a VANLG section that supplies driving point impedance of the receive signal low and placing the higher voltage analog components on the board. The 3-VDD any low-pass filtering of the signals close to the MxFE further section typically has the highest frequency currents on the power reduces the possibility of noise corrupting these signals. plane and should be kept the furthest from the MxFE and analog sections of the board. Rev. A | Page 30 of 36 AD9878 XTAL OSCIN Figure 38. Evaluation PCB Schematic Rev. A | Page 31 of 36 5V AD8328 U4 5V AD8328 R28 1kΩ AD8328 20 1 C117 GND5 GND Tx_OUT 0.1µF 19 2 V 1 V AD8328 CC0603 CC CC 18 3 C115 AGND; 3, 4, 5 TxEN GND1 R39 0.1µF 17 4 SMAEDGE T6 RAMP GND2 43.3Ω CC0603 1 4 3 16 5 J8 V + V + OUT IN 15 6 DUTY RC0605 2 V – V – 2 OUT IN 14 7 CYCLE RC0805 R40 BYP GND3 5 1 CC0603 86.6Ω C116 13 8 V_CLK CA_EN NC DATAEN SP 0.1µF 12 9 R6 C83 + C84 C110 SLEEP SDATA CA_DATA 500Ω 10µF TOKOB5F C72 11 10 0.1µF 0.1µF CA_CLK GND4 CLK 16V CC0805 CC0805 0.1µF BCASE CA_SLEEP OSCIN_CLK Tx_OUT Tx+ AGND; 3, 4, 5 POT1 AGND; 3 C19 R5 AGND; 3, 4, 5 R38 SMA200UP 10kΩ V_CLK; 5 0.1µF 33Ω R11 L16 L15 C114 SMAEDGE T1 2 CW RC0805 75Ω 37.5Ω TRANSF 1 AD8328 220 220 0.01µF CC0603 1 1 6 AB J3 J4 3 24 CC0603 C23 RC0605 LC1210 LC1210 RC0805 CC0805 EXT_CLK C18 2 5 JP8 U13 0.1µF R9 2 JP1 C20 C57 C58 18pF RC0605 R7 NC7SZ04 R37 49.9Ω 3 4 18pF 33pF 18pF 500Ω 59Ω CC0603 SP C24 Tx– OSCIN R12 CC0805 0.1µF R36 1 L13 L14 DIP06RCUP 37.5Ω C113 3 Y1 2 75Ω TRANSF 1 AD8328 220 220 0.01µF CC0603 VAL AB 2 3 CC0805 LC1210 LC1210 RC0805 XTAL JP7 2 DRVDD VCC C17 DVDDPLL/ RC0805 RESET 1 18pF R31 U2 RESET C69 C66 DVDDOSC C16 3 R4 IF10+ R10 33Ω 0.1µF 0.1µF GND CC0603 0.01µF SW1 C1 AD9878LQFP 1.3kΩ CC0603 CC0603 10kΩ 2 4 0.1µF C111 RC0805 AVDDTx ADM1818-10ART Tx– AGNDTx C21 C22 RC0805 51 50 2 0.1µF 1 3 CC0603 U1 AD8138 3 Tx+ FSADJ 0.1µF 0.1µF BA 49 8138+ 52 1 AVDDTx REFIO JP31 TRANSF 53 48 AGND; 5 IF10 DGNDPLL PWRDN PWRDN 54 47 AGND; 3, 4, 5 DVDDTx RESET DVDDPLL DVDDTx SMAEDGE T5 TP4 55 46 SDO, SDIO, CS, SCLK AVDDPLL DGNDTx 1 WHT 56 45 J13 R3 PLLFILT SDO SDO 1 6 JP30 C15 57 44 R33 100kΩ 2 VCML 0.01µF AGNDPLL SDIO SDIO 49.9Ω 2 5 58 43 CC0603 DGNDOSC CS CS RC0805 59 42 C108 RC0805 3 4 XTAL SCLK SCLK DRVDD PWRDN 20pF TP3 TP15 TP6 TP5 TP1 TP2 60 41 J2 OSCIN DGND4 DIP06RCUP WHT WHT WHT WHT WHT WHT 61 40 DVDDOSC DVDD4 DVDD RIBBON JP32 62 39 TRANSF AD8138 1 CA_CLK CA_CLK RESET AB R29 8138– 63 38 25 26 3 R32 CA_DATA CA_DATA PROFILE 10kΩ 64 37 23 24 2 33Ω CC0603 CA_EN CA_EN DGND3 65 36 21 22 RC0805 JP9 C112 FLAG2 FLAG2 DVDD3 IF10– 66 35 19 20 0.1µF FLAG1 FLAG1 DGND2 67 34 17 18 PROFILE1 R26 SIGDELT0 SIGDELT DVDD2 IF12B+ 68 33 15 16 33Ω TxIQ0 CC0603 REFCLK REFCLK TxIQ0 69 32 13 14 TxIQ1 C101 RC0805 DRGND TxIQ1 70 31 11 12 2 TxIQ2 0.1µF AD8138 DRVDD 3 DRVDD TxIQ2 8138+ BA 71 30 9 10 TxIQ3 1 AVDD10 TxIQ3 JP25 72 29 7 8 TRANSF TxIQ4 IF12B TxIQ4 AGND10 73 28 5 6 TxIQ5 AGND; 3, 4, 5 REFB10 TxIQ5 SMAEDGE 74 27 3 4 T3 TxSYNC + REFT10 TxSYNC 1 C14 75 26 1 2 J13 C11 C13 C12 1 6 JP24 10µF AGND1 DGND1 25 0.1µF 0.1µF 0.1µF 76 R27 2 VCML 16V IF10B– DVDD1 2 5 77 24 49.9Ω IF10B+ MCLK MCLK 78 23 C98 RC0805 3 4 DRVDD AGND10-A DRVDD2 20pF 79 22 AVDD10-A DRGND2 DIP06RCUP 80 21 RxSYNC AGND2 RxSYNC 81 20 JP26 TRANSF AD8138 1 AVDD1 IFB0 IFB0 AB 8138– 82 19 JP4 3 R25 REFB12B IFB1 IFB1 83 18 2 33Ω CC0603 + REFT12B IFB2 IFB2 C8 84 17 C6 C7 C9 C102 RC0805 AVDD2 IFB3 IFB3 10µF IF12B– 0.1µF 0.1µF 0.1µF 85 16 C91 0.1µF 10V AGND3 IFB4 IFB4 C90 86 15 10µF 0.1µF R15 C87 R16 IF12B– IF0 IF0 16V + 87 14 10kΩ 0.1µF 5.11kΩ IF12B+ IF1 IF1 88 13 A_BUFF+ AD8138 AGND4 IF2 IF2 VCML 89 12 AGND; 3, 4, 5 AVDD3 IF3 IF3 R18 R17 R14 90 11 SMAEDGE REFB12A IF4 IF4 499Ω 499Ω 33Ω 91 10 1 R13 + J12 8138+ IF12A+ REFT12A IF5 IF5 33Ω C4 CC0603 92 9 RC0805 RC0805 RC0805 C2 C3 C5 AVDD4 IF6 IF6 10µF 0.1µF 0.1µF 0.1µF 93 8 2 C86 RC0805 6 U9 10V AGND5 IF7 IF7 2 0.1µF 94 7 AD8138 3 5 BA IF12A– IF8 IF8 VEE 95 6 8 1 IF12A+ IF9 IF9 +IN JP21 TRANSF 96 5 R24 VO– IF12A 2 AGND6 IF10 IF10 97 4 IFB[0:4] 49.9Ω AGND; 3, 4, 5 AD8138 T2 VOC VIDEO IN IF11 IF11 SMAEDGE DIP06RCUP 98 3 1 VO+ 1 AGND7 DRVDD1 IF[0:11] –IN 99 2 J11 C88 1 6 JP22 VCC AVDD5 DRGND1 4 R20 100 1 47pF 2 VCML AVDD 49.9Ω 2 5 3 R23 R22 C92 RC0805 3 4 523Ω 499Ω 20pF VIDEO IN RC0805 RC0805 C95 AGND; 3, 4, 5 A_BUFF– 47pF C10 SMAEDGE R2 C96 0.1µF R21 C97 33Ω 10µF 1 JP23 0.1µF 33Ω TRANSF J1 AD8138 1 + 16V AB RC0805 CC0603 3 R19 RC0805 2 2 R1 33Ω CC0603 75Ω C94 RC0805 IF12A– 8138– 0.1µF RC0805 BCASE BCASE CC0805 CC0805 RC0805 RC0805 CC1206 CC1206 RC0805 CC0805 RC0805 CC0805 CC0805 CC0805 CC0603 CC0603 CC0603 CC0603 CC0603 CC0603 BCASE BCASE BCASE CC0603 CC0603 CC0603 RC07CUP RC0605 CC0603 CC0603 1 RCOM CC0603 22 2 R1 RC0603 3 R2 4 R3 5 R4 6 R5 7 R6 CC0805 8 R7 9 R8 10 R9 RP1 CC0805 RC0805 CC0805 RC0805 HEADER RA RIBBON CC0603 DIGITAL TRANSMIT 03277-038 + AD9878 Figure 39. Evaluation PCB Schematic (Continued) Rev. A | Page 32 of 36 TP20 CLR L17 VAL V_CLK LC1210 C89 + C93 10µF 0.1µF 16V CC0805 BCASE TP18 CLR L7 VAL AVDD LC1210 C59 + C62 C85 C76 C74 C71 C68 C65 10µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 16V CC0805 CC0603 CC0603 CC0603 CC0603 CC0603 CC0603 P1 BCASE RJ45 TP17 1 CLR SCS L9 VAL AVDDTx 2 LC1210 SSCLK 3 C61 + SSDIO 4 C64 C67 C70 C73 C75 10µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 16V SDOPC 5 CC0805 CC0603 CC0603 CC0603 CC0805 BCASE 6 J5 7 TP16 RIBBON CLR 8 3.3V_ANA L8 VAL HDR040RA AVDDPLL LC1210 C60 + C63 12 910 11 12 10µF 0.1µF 16V 34 CC0805 BCASE 56 TP14 78 CLR ABUFF– L11 VAL 910 A_BUFF– LC1210 C78 11 12 J6 C81 10µF 13 14 DCN2 5 RPT 0.1µF R34 16V 15 16 CC0805 MCLK BCASE 1kΩ 1 17 18 AGND; 3, 4, 5 14 TP12 R35 SMAEDGE 2 RC0603 CLR 19 20 33Ω ABUFF+ L10 VAL 15 A_BUFF+ J7 3 21 22 R8 JP3 16 LC1210 1 RC0603 100Ω C77 23 24 2 4 + C80 17 10µF 25 26 RC0603 JP2 5 0.1µF 16V 18 27 28 AD8328 BCASE CC0805 6 TP13 29 30 19 3.3V_ANA TB1 1 CLR 7 L12 VAL 31 32 20 5V_AD8328 33 34 8 GND TB1 2 LC1210 21 C79 35 36 9 + C82 10µF –5V_ANA TB1 3 22 37 38 0.1µF 10 16V CC0805 BCASE 39 40 23 GND TB1 4 11 NC7SZ04 24 +5V_ANA TB1 5 12 TP19 AGND; 3 25 CLR 5V_BUFF; 5 13 L1 VAL DVDD GND TB1 6 5V LC1210 24 C25 5V_DIG TB1 7 + 3.3V_DIG C28 C31 C34 C37 5V_BUFF U3 10µF SDO 3.3V_DIG TB1 8 0.1µF 0.1µF 0.1µF 0.1µF 16V CC0805 CC0603 CC0603 CC0603 BCASE TP7 CLR L2 VAL DRVDD LC1210 C26 + C29 C32 C35 C38 C39 10µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 16V CC0805 CC0603 CC0603 CC0603 CC0603 BCASE TP8 DVDDPLL/ CLR L4 VAL DVDDOSC LC1210 C40 + C43 C52 C49 C46 10µF 3.3V_BUFF 0.1µF 0.1µF 0.1µF 0.1µF 16V CC0805 CC0603 CC0603 CC0605 BCASE TP9 CLR L3 VAL DVDDTx LC1210 C27 + C30 C33 C36 10µF 0.1µF 0.1µF 0.1µF 16V CC0805 CC0603 CC0603 BCASE 2 AB IF[0:11] IFB4 13 TP10 CLR IF0 L6 VAL 3.3V_BUFF JP13 LC1210 C42 IFB[0:4] + C45 C56 C54 C51 C48 10µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 16V CC0805 CC0603 CC0605 CC0805 CC0605 BCASE TP11 CLR L5 VAL 5V_BUFF LC1210 C41 + C44 C47 C50 C55 C53 C100 10µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 16V BCASE CC0805 CC0603 CC0603 CC0603 CC0603 CC0603 POWER DIGITAL RECEIVE 124 VCCA VCCB 2 23 RP6 22 T/R NC IF11 8 9 10 22 A7 OE RP3 22 IF10 7 10 9 14 8 9 A6 B7 IF9 6 11 8 15 7 10 A5 B6 IF8 5 12 7 16 6 11 U5 A4 B5 IF7 74LVXC3245 4 13 6 17 5 12 A3 B4 TSSOP24 IF6 3 14 5 18 4 13 A2 B3 IF5 2 15 4 19 3 14 A1 B2 IF4 1 16 3 20 2 15 A0 B1 11 21 1 16 GND1 B0 12 13 GND2 GND3 1 24 VCCA VCCB 2 23 RP5 22 T/R NC IF3 8 9 10 22 A7 OE RP2 22 IF2 7 10 9 14 8 9 A6 B7 IF1 6 11 8 15 7 10 A5 B6 5 12 7 U6 16 6 11 A4 B5 74LVXC3245 4 13 6 17 5 12 A3 TSSOP24 B4 3 14 5 18 4 13 A2 B3 2 15 4 19 3 14 A1 B2 1 16 3 20 2 15 A0 B1 11 21 1 16 GND1 B0 12 13 GND2 GND3 1 24 VCCA VCCB 2 23 RP7 22 T/R NC 1 8 3 22 MCLK A0 OE RP4 22 2 7 4 21 1 16 RxSYNC A1 B0 3 6 5 20 2 15 A2 B1 4 5 6 19 3 14 13 U7 A3 B2 A B 7 74LVXC3245 18 4 13 JP5 2 DEL_CLK A4 B3 INVERT CLK TSSOP24 5 1231 8 17 A5 B4 A B 6 11 9 16 JP6 2 A6 B5 7 10 DEL_CLK 10 15 DEL_CLK A7 B6 8 9 11 14 GND1 B7 12 13 GND2 GND3 CA_SLEEP DVDD 1 24 VCCA VCCB 2 23 T/R NC 3 22 A0 OE 4 21 SDOPC A1 B0 5 20 SDIO A2 B1 6 19 CS A3 B2 U8 7 18 SCLK A4 B3 74LVXC3245 8 17 TSSOP24 A5 B4 9 16 A6 B5 10 15 A7 B6 11 14 GND1 B7 12 13 GND2 GND3 PC PARALLEL PORT 03277-039 AD9878 Figure 40. Evaluation PCB—Top Assembly Figure 41. Evaluation PCB—Bottom Assembly Rev. A | Page 33 of 36 03277-041 03277-040 AD9878 Figure 42. Evaluation PCB Layout—Top Layer Figure 43. Evaluation PCB Layout—Bottom Layer Rev. A | Page 34 of 36 03277-043 03277-042 AD9878 Figure 44. Evaluation PCB—Power Plane Figure 45. Evaluation PCB—Ground Plane Rev. A | Page 35 of 36 03277-045 03277-044 AD9878 OUTLINE DIMENSIONS 16.00 BSC SQ 1.60 MAX 14.00 BSC SQ 0.75 100 76 1 75 0.60 0.45 PIN 1 12.00 TOP VIEW REF (PINS DOWN) 1.45 0.20 1.40 0.09 1.35 7° 3.5° 25 51 0.15 0° 26 50 SEATING 0.05 0.08 MAX PLANE 0.27 COPLANARITY VIEW A 0.22 0.50 BSC VIEW A 0.17 LEAD PITCH ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026BED Figure 46. 100-Lead Low Profile Quad Flat Package [LQFP] (ST-100) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option AD9878BST −40°C to +85°C 100-LQFP ST-100 1 AD9878BSTZ −40°C to +85°C 100-LQFP ST-100 AD9878-EB Evaluation Board 1 Z = Pb-free part. © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C03277–0–3/05(A) Rev. A | Page 36 of 36