ANALOG DEVICES AD9868

Broadband Modem Mixed-Signal Front End AD9868 FEATURES FUNCTIONAL BLOCK DIAGRAM Low cost 3.3 V CMOS MxFE for broadband modems 10-bit DAC converter 2×/4× interpolation filter AD9868 200 MSPS DAC update rate IOUTN+ 2-4X PWRDWN IAMP TxDAC Integrated 17 dBm line driver with 19.5 dB gain control IOUTN– MODE 10 10-bit, 80 MSPS, ADC converter TXEN/TXSYNC 0 TO –12dB 0 TO –7.5dB TXCLK/TXQUIET −12 dB to +48 dB low noise RxPGA (<3 nV/√Hz) CLK CLKOUT1 Third-order, programmable low-pass filter ADIO[9:4]/ SYNC. CLKOUT2 Tx[5:0] Flexible digital data path interface M 2 CLK OSCIN MULTIPLIER XTAL Half- and full-duplex operation ADIO[3:0]/ Pin compatible with the AD9865 Rx[5:0] Various power-down/reduction modes Internal clock multiplier (PLL) 10 2 auxiliary programmable clock outputs Available in a 64-lead LFCSP_VQ RX+ RXEN/RXSYNC ADC 2-POLE 1-POLE LPF LPF RXCLK 80MSPS RX– 6 APPLICATIONS AGC[5:0] 0 TO 6dB –6 TO +18dB –6 TO +24dB PORT Δ = 1dB Δ = 6dB Δ = 6dB 4 REGISTER Broadband wireline networking SPI CONTROL PORT Figure 1. GENERAL DESCRIPTION of 80 MSPS. The TxDAC provides differential current outputs The AD9868 is a mixed-signal front-end (MxFE®) IC for that can be steered directly to an external load or to an internal transceiver applications requiring Tx path and Rx path low distortion current amplifier (IAMP) capable of delivering functionality with data rates up to 80 MSPS. A lower cost, pin- 17 dBm peak signal power. Tx power can be digitally controlled compatible version of the AD9865, the AD9868 removes the over a 19.5 dB range in 0.5 dB steps. current amplifier (IAMP) IOUTP functionality and limits the PLL VCO operating range of 80 MHz to 200 MHz. The receive path consists of a programmable amplifier (RxPGA), a tunable low-pass filter (LPF), and a 10-bit ADC. The part is well-suited for half- and full-duplex applications. The low noise RxPGA has a programmable gain range of The digital interface is extremely flexible, allowing simple −12 dB to +48 dB in 1 dB steps. Its input referred noise is less interfacing to digital back ends that support half- or full-duplex than 3 nV/√Hz for gain settings beyond 36 dB. The receive path data transfers, often allowing the AD9868 to replace discrete LPF cutoff frequency can be set over a 15 MHz to 35 MHz ADC and DAC solutions. Power-saving modes include the range or it can be simply bypassed. The 10-bit ADC achieves ability to reduce power consumption of individual functional excellent dynamic performance up to an 80 MSPS span. Both blocks or power down unused blocks in half-duplex applications. the RxPGA and the ADC offer scalable power consumption A serial port interface (SPI) allows software programming of allowing power/performance optimization. the various functional blocks. An on-chip PLL clock multiplier and synthesizer provide all the required internal clocks, as well The AD9868 provides a highly integrated solution for many as two external clocks, from a single crystal or clock source. broadband modems. It is available in a space-saving package, a 16-lead LFCSP, and is specified over the commercial temperature The Tx signal path consists of a 2×/4× low-pass interpolation range (−40°C to +85°C). filter, a 10-bit TxDAC, and a line driver. The transmit path signal bandwidth can be as high as 34 MHz at an input data rate Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. IOUTP+ IOUTP– 06733-001 AD9868 TABLE OF CONTENTS Features .............................................................................................. 1 Full-Duplex Mode...................................................................... 17 Applications....................................................................................... 1 RxPGA Control .......................................................................... 19 Functional Block Diagram .............................................................. 1 TxPGA Control .......................................................................... 20 General Description ......................................................................... 1 Transmit Path.................................................................................. 21 Revision History ............................................................................... 2 Digital Interpolation Filters ...................................................... 21 Specifications..................................................................................... 3 TxDAC and IAMP Architecture .............................................. 22 Tx Path Specifications.................................................................. 3 Tx Programmable Gain Control .............................................. 23 Rx Path Specifications.................................................................. 4 TxDAC Output Operation........................................................ 23 Power Supply Specifications........................................................ 6 IAMP Current-Mode Operation.............................................. 23 Digital Specifications ................................................................... 7 Receive Path .................................................................................... 24 Serial Port Timing Specifications............................................... 7 Rx Programmable Gain Amplifier........................................... 24 Half-Duplex Data Interface (ADIO Port) Timing Low-Pass Filter............................................................................ 25 Specifications ................................................................................ 8 Analog-to-Digital Converter (ADC)....................................... 26 Full-Duplex Data Interface (Tx and Rx Port) Timing AGC Timing Considerations.................................................... 27 Specifications ................................................................................ 8 Clock Synthesizer ........................................................................... 28 Absolute Maximum Ratings............................................................ 9 Power Control and Dissipation .................................................... 30 Thermal Characteristics .............................................................. 9 Power-Down ............................................................................... 30 Explanation of Test Levels........................................................... 9 Half-Duplex Power Savings ...................................................... 30 ESD Caution.................................................................................. 9 Power Reduction Options ......................................................... 31 Pin Configuration and Function Descriptions........................... 10 Power Dissipation....................................................................... 33 Serial Port ........................................................................................ 12 Mode Select upon Power-Up and Reset.................................. 33 Register Map Description.......................................................... 14 Analog and Digital Loopback Test Modes.............................. 34 Serial Port Interface (SPI).......................................................... 14 Outline Dimensions....................................................................... 35 Digital Interface .............................................................................. 16 Ordering Guide .......................................................................... 35 Half-Duplex Mode ..................................................................... 16 REVISION HISTORY 5/07—Revision 0: Initial Version Rev. 0 | Page 2 of 36 AD9868 SPECIFICATIONS Tx PATH SPECIFICATIONS AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%, f = 50 MHz, f = 200 MHz, R = 2.0 kΩ, unless otherwise noted. OSCIN DAC SET Table 1. 1 Parameter Temp Test Level Min Typ Max Unit TxDAC DC CHARACTERISTICS Resolution Full 10 Bits Update Rate Full II 200 MSPS Full-Scale Output Current (IOUTP_FS) Full IV 2 25 mA 2 Gain Error 25°C I ±2 % FS Offset Error 25°C V 2 μA Voltage Compliance Range Full −1 +1.5 V TxDAC GAIN CONTROL CHARACTERISTICS Minimum Gain 25°C V −7.5 dB Maximum Gain 25°C V 0 dB Gain Step Size 25°C V 0.5 dB Gain Step Accuracy 25°C IV Monotonic dB Gain Range Error 25°C V ±2 dB 3 TxDAC AC CHARACTERISTICS Fundamental 0.5 dBm Signal-to-Noise and Distortion (SINAD) Full IV 62.0 63.1 dBc Signal-to-Noise Ratio (SNR) Full IV 62.5 63.2 dBc Total Harmonic Distortion (THD) Full IV −77.7 −67.0 dBc Spurious-Free Dynamic Range (SFDR) Full IV 67.1 79.3 dBc IAMP DC CHARACTERISTICS IOUTN Full-Scale Current = IOUTN+ + IOUTN− Full IV 2 105 mA AC Voltage Compliance Range Full IV 1 3.9 V 4 IAMPN AC CHARACTERISTICS Fundamental 25°C 13 dBm IOUTN SFDR (Third Harmonic) Full IV 43.3 45.2 dBc REFERENCE 5 Internal Reference Voltage 25°C I 1.23 V Reference Error Full V 0.7 3.4 % o Reference Drift Full V 30 ppm/ C Tx DIGITAL FILTER CHARACTERISTICS (2× Interpolation) Latency (Relative to 1/f) Full V 43 Cycles DAC −0.2 dB Bandwidth Full V 0.2187 f /f OUT DAC −3 dB Bandwidth Full V 0.2405 fOUT/fDAC Stop-Band Rejection (0.289 fDAC to 0.711 fDAC) Full V 50 dB Tx DIGITAL FILTER CHARACTERISTICS (4× Interpolation) Latency (Relative to 1/fDAC) Full V 96 Cycles −0.2 dB Bandwidth Full V 0.1095 fOUT/fDAC −3 dB Bandwidth Full V 0.1202 fOUT/fDAC Stop Band Rejection (0.289 f to 0.711 f) Full V 50 dB OSCIN OSCIN PLL CLK MULTIPLIER OSCIN Frequency Range PLL M Factor Set to 2 Full IV 40 80 MHz PLL M Factor Set to 4 Full IV 20 50 MHz PLL M Factor Set to 8 Full IV 10 25 MHz Internal VCO Frequency Range Full IV 80 200 MHz Duty Cycle Full II 40 60 % Rev. 0 | Page 3 of 36 AD9868 1 Parameter Temp Test Level Min Typ Max Unit OSCIN Impedance 25°C V 10||03 ΜΩ||pF 6 CLKOUT1 Jitter 25°C III 12 ps rms 7 CLKOUT2 Jitter 25°C III 6 ps rms 8 CLKOUT1 and CLKOUT2 Duty Cycle Full III 45 55 % 1 See the Explanation of Test Levels section. 2 Gain error and gain temperature coefficients are based on the ADC only (with a fixed 1.23 V external reference and a 1 V p-p differential analog input). 3 TxDAC IOUTP_FS = 20 mA, differential output with 1:1 transformer with source and load termination of 50 Ω, fOUT = 5 MHz, 4x interpolation. 4 IOUTN full-scale current = 80 mA, fOSCIN = 80 MHz, fDAC =160 MHz, 2x interpolation. 5 Use external amplifier to drive additional load. 6 Internal VCO operates at 200 MHz; set to divide-by-1. 7 Because CLKOUT2 is a divided-down version of OSCIN, its jitter is typically equal to OSCIN. 8 CLKOUT2 is an inverted replica of OSCIN, if set to divide-by-1. Rx PATH SPECIFICATIONS AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%, half- or full-duplex operation with CONFIG = 0 default power bias settings, unless otherwise noted. Table 2. 1 Parameter Temp Test Level Min Typ Max Unit Rx INPUT CHARACTERISTICS Input Voltage Span RxPGA Gain = −10 dB Full III 6.33 V p-p RxPGA Gain = +48 dB Full III 8 mV p-p Input Common-Mode Voltage 25°C III 1.3 V Differential Input Impedance 25°C III 400||4.0 Ω||pF Input Bandwidth with RxLPF Disabled, RxPGA = 0 dB 25°C III 53 MHz Input Voltage Noise Density RxPGA Gain = 36 dB, f−3 dBF = 26 MHz 25°C III 3.0 nV/√Hz RxPGA Gain = 48 dB, f = 26 MHz 25°C III 2.4 nV/√Hz −3 dBF RxPGA CHARACTERISTICS Minimum Gain 25°C III −12 dB Maximum Gain 25°C III 48 dB Gain Step Size 25°C III 1 dB Gain Step Accuracy 25°C III Monotonic dB Gain Range Error 25°C III 0.5 dB RxLPF CHARACTERISTICS Cutoff Frequency (f−3 dBF ) Range Full III 15 35 MHz Attenuation at 55.2 MHz with f−3 dBF = 21 MHz 25°C III 20 dB Pass-Band Ripple 25°C III ±1 dB Settling Time 5 dB RxPGA Gain Step @ f = 50 MSPS 25°C III 20 ns ADC 60 dB RxPGA Gain Step @ fADC = 50 MSPS 25°C III 100 ns ADC DC CHARACTERISTICS Resolution N/A N/A 10 Bits Conversion Rate Full II 20 80 MSPS 2 Rx PATH LATENCY Full-Duplex Interface Full V 10.5 Cycles Half-Duplex Interface Full V 10.0 Cycles 3 Rx PATH COMPOSITE AC PERFORMANCE @ f = 50 MSPS ADC RxPGA Gain = 48 dB (Full-Scale = 8.0 mV p-p) Signal-to-Noise and Distortion (SINAD) 25°C III 43.7 dBc Total Harmonic Distortion (THD) 25°C III −71 dBc Rev. 0 | Page 4 of 36 AD9868 1 Parameter Temp Test Level Min Typ Max Unit RxPGA Gain = 24 dB (Full-Scale = 126 mV p-p) Signal-to-Noise Ratio (SNR) 25°C III 59 dBc Total Harmonic Distortion (THD) 25°C III −67.2 dBc RxPGA Gain = 0 dB (Full-Scale = 2.0 V p-p) Signal-to-Noise and Distortion (SINAD) Full IV 58 59 dBc Total Harmonic Distortion (THD) Full IV −66 −62.9 dBc 4 Rx PATH COMPOSITE AC PERFORMANCE @ f = 80 MSPS ADC RxPGA Gain = 48 dB (Full-Scale = 8.0 mV p-p) Signal-to-Noise Ratio (SNR) 25°C III 41.8 dBc Total Harmonic Distortion (THD) 25°C III −67 dBc RxPGA Gain = 24 dB (Full-Scale = 126 mV p-p) Signal-to-Noise Ratio (SNR) 25°C III 58.6 dBc Total Harmonic Distortion (THD) 25°C III −62.9 dBc RxPGA Gain = 0 dB (Full-Scale = 2.0 V p-p) Signal-to-Noise Ratio (SNR) 25°C II 58.9 59.6 dBc Total Harmonic Distortion (THD) 25°C II −69.7 −59.8 dBc Rx-to-Tx PATH FULL-DUPLEX ISOLATION (1 V p-p, 10 MHz Sine Wave Tx Output) RxPGA Gain = 40 dB IOUTP± Pins to RX± Pins 25°C III 83 dBc RxPGA Gain = 0 dB IOUTP± Pins to RX± Pins 25°C III 123 dBc 1 See the Explanation of Test Levels section. 2 Includes RxPGA, ADC pipeline, and ADIO bus delay relative to fADC. 3 f = 5 MHz, AIN = −1.0 dBFS, LPF cutoff frequency set to 15.5 MHz with Register 0x08 = 0x80. IN 4 fIN = 5 MHz, AIN = −1.0 dBFS, LPF cutoff frequency set to 26 MHz with Register 0x08 = 0x80. Rev. 0 | Page 5 of 36 AD9868 POWER SUPPLY SPECIFICATIONS 1 AVDD = 3.3 V, DVDD = CLKVDD = DRVDD = 3.3 V, RSET = 2 kΩ, full-duplex operation with fDATA = 80 MSPS , unless otherwise noted. Table 3. 2 Parameter Temp Test Level Min Typ Max Unit SUPPLY VOLTAGES AVDD Full V 3.135 3.3 3.465 V CLKVDD Full V 3.0 3.3 3.6 V DVDD Full V 3.0 3.3 3.6 V DRVDD Full V 3.0 3.3 3.6 V IS_TOTAL (Total Supply Current) Full II 406 475 mA POWER CONSUMPTION I + I (Analog Supply Current) Full IV 311 342 mA AVDD CLKVDD I + I (Digital Supply Current) Full IV 95 133 mA DVDD DRVDD 3 POWER CONSUMPTION (Half-Duplex Operation with f = 50 MSPS) DATA Tx Mode I + I 25°C IV 112 130 mA AVDD CLKVDD IDVDD + IDRVDD 25°C IV 46 49.5 mA Rx Mode IAVDD + ICLKVDD 25°C IV 225 253 mA I + I 25°C IV 36.5 39 mA DVDD DRVDD 1 POWER CONSUMPTION OF FUNCTIONAL BLOCKS (IAVDD + ICLKVDD) RxPGA and LPF 25°C III 87 mA ADC 25°C III 108 mA TxDAC 25°C III 38 mA IAMP (Programmable) 25°C III 10 100 mA Reference 25°C III 170 mA CLK PLL and Synthesizer 25°C III 107 mA MAXIMUM ALLOWABLE POWER DISSIPATION Full IV 1.66 W STANDBY POWER CONSUMPTION IS_TOTAL (Total Supply Current) Full 13 mA POWER-DOWN DELAY (Using PWRDWN Pin) RxPGA and LPF 25°C III 440 ns ADC 25°C III 12 ns TxDAC 25°C III 20 ns IAMP 25°C III 20 ns CLK PLL and Synthesizer 25°C III 27 ns POWER-UP DELAY (Using PWRDWN Pin) RxPGA and LPF 25°C III 7.8 μs ADC 25°C III 88 ns TxDAC 25°C III 13 μs IAMP 25°C III 20 ns CLK PLL and Synthesizer 25°C III 20 μs 1 Default power-up settings for MODE = high and CONFIG = low, IOUTP_FS = 20 mA, does not include IAMP current consumption, which is application dependent. 2 See the Explanation of Test Levels section. 3 Default power-up settings for MODE = low and CONFIG = low. Rev. 0 | Page 6 of 36 AD9868 DIGITAL SPECIFICATIONS AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%, RSET = 2 kΩ, unless otherwise noted. Table 4. 1 Parameter Temp Test LevelMin Typ Max Unit CMOS LOGIC INPUTS High Level Input Voltage Full VI DRVDD − 0.7 V Low Level Input Voltage Full VI 0.4 V Input Leakage Current 12 μA Input Capacitance Full VI 3 pF CMOS LOGIC OUTPUTS (CLOAD = 5 pF) High Level Output Voltage (IOH = 1 mA) Full VI DRVDD − 0.7 V Low Level Output Voltage (I = 1 mA) Full VI 0.4 V OH Output Rise/Fall Time High Strength Mode and CLOAD = 15 pF Full VI 1.5/2.3 ns Low Strength Mode and CLOAD = 15 pF Full VI 1.9/2.7 ns High Strength Mode and CLOAD = 5 pF Full VI 0.7/0.7 ns Low Strength Mode and C = 5 pF Full VI 1.0/1.0 ns LOAD RESET Minimum Low Pulse Width (Relative to fADC) 1 Clock cycles 1 See the Explanation of Test Levels section. SERIAL PORT TIMING SPECIFICATIONS AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%, unless otherwise noted. Table 5. 1 Parameter Temp Test Level Min Typ Max Unit WRITE OPERATION (See Figure 5) SCLK Clock Rate (f ) Full IV 32 MHz SCLK SCLK Clock High (t ) Full IV 14 ns HI SCLK Clock Low (tLOW) Full IV 14 ns SDIO to SCLK Setup Time (tDS) Full IV 14 ns SCLK to SDIO Hold Time (tDH) Full IV 0 ns SEN to SCLK Setup Time (t ) Full IV 14 ns S SCLK to SEN Hold Time (t ) Full IV 0 ns H READ OPERATION (See Figure 6 and Figure 7) SCLK Clock Rate (f ) Full IV 32 MHz SCLK SCLK Clock High (t ) Full IV 14 ns HI SCLK Clock Low (t ) Full IV 14 ns LOW SDIO to SCLK Setup Time (tDS) Full IV 14 ns SCLK to SDIO Hold Time (tDH) Full IV 0 ns SCLK to SDIO (or SDO) Data Valid Time (tDV) Full IV 14 ns SEN to SDIO Output Valid to High-Z (t ) Full IV 2 ns EZ 1 See the Explanation of Test Levels section. Rev. 0 | Page 7 of 36 AD9868 HALF-DUPLEX DATA INTERFACE (ADIO PORT) TIMING SPECIFICATIONS AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%, unless otherwise noted. Table 6. 1 Parameter Temp Test Level Min Typ Max Unit 2 READ OPERATION (See Figure 9) Output Data Rate Full II 20 80 MSPS Three-State Output Enable Time (tPZL) Full II 3 ns Three-State Output Disable Time (t ) Full II 3 PLZ ns Rx Data Valid Time (t ) Full II 1.5 ns VT Rx Data Output Delay (tOD) Full II 4 ns WRITE OPERATION (See Figure 8) Input Data Rate (2× Interpolation) Full II 40 80 MSPS Input Data Rate (4× Interpolation) Full II 20 50 MSPS Tx Data Setup Time (tDS) Full II 1 ns Tx Data Hold Time (t ) Full II 2.5 ns DH Latch Enable Time (t ) Full II 3 ns EN Latch Disable Time (t ) Full II 3 ns DIS 1 See the Explanation of Test Levels section. 2 CLOAD = 5 pF for digital data outputs. FULL-DUPLEX DATA INTERFACE (Tx AND Rx PORT) TIMING SPECIFICATIONS AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%, unless otherwise noted. Table 7. 1 Parameter Temp Test Level Min Typ Max Unit Tx PATH INTERFACE (See Figure 12) Input Nibble Rate (2× Interpolation) Full II 80 160 MSPS Input Nibble Rate (4× Interpolation) Full II 40 100 MSPS Tx Data Setup Time (t ) Full II 2.5 ns DS Tx Data Hold Time (tDH) Full II 1.5 ns 2 Rx PATH INTERFACE (See Figure 13) Output Nibble Rate Full II 40 160 MSPS Rx Data Valid Time (tDV) Full II 3 ns Rx Data Hold Time (tDH) Full II 0 ns 1 See the Explanation of Test Levels section. 2 C = 5 pF for digital data outputs. LOAD Rev. 0 | Page 8 of 36 AD9868 ABSOLUTE MAXIMUM RATINGS Table 8. Parameter Rating THERMAL CHARACTERISTICS ELECTRICAL Thermal Resistance: 64-lead LFCSP (4-layer board). AVDD, CLKVDD Voltage 3.9 V maximum DVDD, DRVDD Voltage 3.9 V maximum θ = 24°C/W (paddle soldered to ground plane, 0 LPM air). JA RX+, RX−, REFT, REFB −0.3 V to AVDD + 0.3 V θJA = 30.8°C/W (paddle not soldered to ground plane, 0 LPM air). IOUTP+, IOUTP− −1.5 V to AVDD + 0.3 V IOUTN+, IOUTN− −0.3 V to +3.9 V OSCIN, XTAL −0.3 V to CLVDD + 0.3 V EXPLANATION OF TEST LEVELS REFIO, REFADJ −0.3 V to AVDD + 0.3 V I. 100% production tested. Digital Input and Output Voltage −0.3 V to DRVDD + 0.3 V Digital Output Current 5 mA maximum II. 100% production tested at 25°C and guaranteed by design ENVIRONMENTAL and characterization at specified temperatures. Operating Temperature Range −40°C to +85°C (Ambient) III. Sample tested only. Maximum Junction Temperature 125°C IV. Parameter is guaranteed by design and characterization Lead Temperature (Soldering, 10 sec) 150°C testing. Storage Temperature Range (Ambient) −65°C to +150°C V. Parameter is a typical value only. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress VI. 100% production tested at 25°C and guaranteed by design rating only; functional operation of the device at these or any and characterization for industrial temperature range. other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect ESD CAUTION device reliability. Rev. 0 | Page 9 of 36 AD9868 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 64 63 62 61 60 59 58 57 56 55 54 53 51 50 49 52 48 AVSS ADIO9/Tx[5] 1 AVSS 47 ADIO8/Tx[4] 2 PIN 1 46 IOUTN– ADIO7/Tx[3] 3 IDENTIFIER 45 4 NC ADIO6/Tx[2] 44 AVSS ADIO5/Tx[1] 5 43 AVDD 6 ADIO4/Tx[0] AD9868 42 REFIO ADIO3/Rx[5] 7 TOP VIEW 41 REFADJ 8 ADIO2/Rx[4] (Not to Scale) 40 AVDD ADIO1/Rx[3] 9 39 AVSS ADIO0/Rx[2] 10 38 11 RX+ NC/Rx[1] 37 RX– NC/Rx[0] 12 36 AVSS RXEN/RXSYNC 13 35 AVDD TXEN/TXSYNC 14 34 15 AVSS TXCLK/TXQUIET 33 REFT RXCLK 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Figure 2. Pin Configuration Table 9. Pin Function Descriptions 1 Pin No. Mnemonic Mode Description 1 ADIO9 HD MSB of ADIO Buffer. Tx[5] FD MSB of Tx Nibble Input. 2 to 5 ADIO8 to ADIO5 HD Bit 8 to Bit 5 of ADIO Buffer. Tx[4:1] FD Bit 4 to Bit 1 of Tx Nibble Input. 6 ADIO4 HD Bit 4 of ADIO Buffer. Tx[0] FD LSB of Tx Nibble Input. 7 ADIO3 HD Bit 3 of ADIO Buffer. Rx[5] FD MSB of Rx Nibble Output. 8, 9 ADIO2, ADIO1 HD Bit 2 to Bit 1 of ADIO Buffer. Rx[4:3] FD Bit 4 to Bit 3 of Rx Nibble Output. 10 ADIO0 HD LSB of ADIO Buffer. Rx[2] FD Bit 2 of Rx Nibble Output. 11 NC HD No Connect. Rx[1] FD Bit 1 of Rx Nibble Output. 12 NC HD No Connect. Rx[0] FD LSB of Rx Nibble Output. 13 RXEN HD ADIO Buffer Control Input. RXSYNC FD Rx Data Synchronization Output. 14 TXEN HD Tx Path Enable Input. TXSYNC FD Tx Data Synchronization Input. 15 TXCLK HD ADIO Sample Clock Input. TXQUIET FD Fast TxDAC/IAMP Power-Down. 16 RXCLK HD ADIO Request Clock Input. FD Rx and Tx Clock Output at 2 x f . ADC Rev. 0 | Page 10 of 36 DRVDD DRVDD DRVSS DRVSS CLKOUT1 PWRDWN SDIO CLKOUT2 SDO DVDD SCLK DVSS SEN CLKVDD GAIN/PGA[5] OSCIN PGA[4] XTAL PGA[3] CLKVSS PGA[2] CONFIG PGA[1] MODE PGA[0] IOUTP+ RESET IOUTP– AVSS IOUTN+ REFB NC 06733-002 AD9868 1 Pin No. Mnemonic Mode Description 17, 64 DRVDD Digital Output Driver Supply Input. 18, 63 DRVSS Digital Output Driver Supply Return. 19 CLKOUT1 fADC/N Clock Output (R = 1, 2, or 3). 20 SDIO Serial Port Data Input/Output. 21 SDO Serial Port Data Output. 22 SCLK Serial Port Clock Input. 23 SEN Serial Port Enable Input. 24 GAIN FD Tx Data Port (Tx[5:0]) Mode Select. PGA[5] HD or FD MSB of PGA Input Data Port. 25 to 29 PGA[4:0] HD or FD Bit 4 to Bit 0 of PGA Input Data Port. 30 RESET Reset Input (Active Low). 31, 34, 36, 39, 44, 47, 48 AVSS Analog Supply Return. 32, 33 REFB, REFT ADC Reference Decoupling Nodes. 35, 40, 43 AVDD Analog Power Supply Input. 37, 38 RX−, RX+ Receive Path − and + Analog Inputs. 41 REFADJ TxDAC Full-Scale Current Adjust. 42 REFIO TxDAC Reference Input/Output. 45, 49 NC Do Not Connect; Leave Open. 46 IOUTN− −Tx Mirror Current Output Sink. 50 IOUTN+ +Tx Mirror Current Output Sink. 51 IOUTP− −TxDAC Current Output Source. 52 IOUTP+ +TxDAC Current Output Source. 53 MODE Digital Interface Mode Select Input, Low = HD, High = FD. 54 CONFIG Power-Up SPI Register Default Setting Input. 55 CLKVSS Clock Oscillator/Synthesizer Supply Return. 56 XTAL Crystal Oscillator Inverter Output. 57 OSCIN Crystal Oscillator Inverter Input. 58 CLKVDD Clock Oscillator/Synthesizer Supply. 59 DVSS Digital Supply Return. 60 DVDD Digital Supply Input. 61 CLKOUT2 fOSCIN/L Clock Output (L = 1, 2, or 4). 62 PWRDWN Power-Down Input. 1 HD = half-duplex mode; FD = full-duplex mode. Rev. 0 | Page 11 of 36 AD9868 SERIAL PORT Table 10. SPI Register Mapping Power-Up Default Value MODE = 0 MODE = 1 (Half-Duplex) (Full-Duplex) Address 1 (Hex) Bit Description Width CONFIG = 0 CONFIG = 1 CONFIG = 0 Comments SPI PORT CONFIGURATION AND SOFTWARE RESET 0x00 7 4-Wire SPI 1 0 0 0 Default SPI configuration is 3-wire, MSB first. 6 SPI LSB First 1 0 0 0 5 Software Reset 1 0 0 0 POWER CONTROL REGISTERS (Via PWRDWN Pin) 0x01 7 CLK Synthesizer 1 0 0 0 PWRDWN = 0. Default setting is for all blocks powered on. 6 TxDAC/IAMP 1 0 0 0 5 Tx Digital 1 0 0 0 4 REF 1 0 0 0 3 ADC CML 1 0 0 0 2 ADC 1 0 0 0 1 PGA Bias 1 0 0 0 0 RxPGA 1 0 0 0 0x02 7 CLK Synthesizer 1 0 0 0 PWRDWN = 1. Default setting is for all functional blocks 6 TxDAC/IAMP 1 1 1 1 powered down except PLL. 5 Tx Digital 1 1 1 1 4 REF 1 1 1 1 3 ADC CML 1 1 1 1 2 ADC 1 1 1 1 1 PGA Bias 1 1 1 1 0 RxPGA 1 1 1 1 HALF-DUPLEX POWER CONTROL 0x03 7:3 Tx OFF Delay 5 0xFF 0xFF N/A Default setting is for TXEN input to control power-on/power-off of 2 Rx_TXEN 1 0xFF 0xFF N/A Tx/Rx path. Tx driver delayed by 1 Tx PWRDN 1 0xFF 0xFF N/A 31 1/fDATA clock cycles. 0 Rx PWRDN 1 0xFF 0xFF N/A PLL CLOCK MULTIPLIER/SYNTHESIZER CONTROL 0x04 4 fADC from PLL 1 0 0 0 3:2 PLL Divide-N 2 00 00 00 1:0 PLL Multiplier-M 2 01 10 01 0x05 2 OSCIN to RXCLK 1 0 0 0 Full-duplex RXCLK normally at nibble rate. 1 Invert RXCLK 1 0 0 0 0 Disable RXCLK 1 0 0 0 0x06 7:6 CLKOUT2 Divide 2 01 01 01 Default setting is CLKOUT2 and CLKOUT1 enabled with divide-by-2. 5 CLKOUT2 Invert 1 0 0 0 4 CLKOUT2 Disable 1 0 0 0 3:2 CLKOUT1 Divide 2 01 01 01 1 CLKOUT1 Invert 1 0 0 0 0 CLKOUT1 Disable 1 0 0 0 Rx PATH CONTROL 0x07 5 Initiate Offset Cal. 1 0 0 0 Default setting has LPF on. Rx path at nominal power bias setting for 4 Rx Low Power 1 0 1 0 CONFIG = 0 and low power for CONFIG = 1. 0 Enable Rx LPF 1 1 1 1 0x08 7:0 Rx Filter Target 8 0x80 0x61 0x80 Refer to the Low-Pass Filter section. Cutoff Frequency Rev. 0 | Page 12 of 36 AD9868 Power-Up Default Value MODE = 0 MODE = 1 (Half-Duplex) (Full-Duplex) Address 1 (Hex) Bit Description Width Comments CONFIG = 0 CONFIG = 1 CONFIG = 0 Tx/Rx PATH GAIN CONTROL 0x09 6 Enable SPI Rx Gain 1 0x00 0x00 0x00 Default setting is for hardware Rx gain code via PGA or Tx data port. 5:0 Rx Gain Code 6 0x00 0x00 0x00 0x0A 6 Enable SPI Tx Gain 1 0x7F 0x7F 0x7F Default setting is for Tx gain code via SPI control. 5:0 Tx Gain Code 6 0x7F 0x7F 0x7F TxPGA AND RxPGA CONTROL 0x0B 6 PGA Code for Tx 1 0 0 0 Default setting is RxPGA control active via PGA port. 5 PGA Code for Rx 1 1 1 1 3 Force Gain Strobe 1 0 0 0 2 Rx Gain on Tx Port 1 0 0 1 1 3-Bit RxPGA Port 1 0 1 0 Tx DIGITAL FILTER AND INTERFACE 0x0C 7:6 Interpolation 2 01 00 01 Default setting is 2× interpolation with Factor LPF response. Data format is straight binary for half-duplex and twos 4 Invert 1 0 0 0 complement for full-duplex interface. TXEN/TXSYNC 2 3 Tx 5/5 Nibble 1 N/A N/A 0 2 2 LS Nibble First 1 N/A N/A 0 1 TXCLK Neg. Edge 1 0 0 0 0 Twos Complement 1 0 0 1 Rx INTERFACE AND ANALOG/DIGITAL LOOPBACK 0x0D 7 Analog Loopback 1 0 0 0 Data format is straight binary for 2 half-duplex and twos complement for 6 Digital Loopback1 0 0 0 full-duplex interface. Analog loopback: 5 Rx Port Three-State 1 N/A N/A 0 ADC Rx data fed back to TxDAC. Digital 4 Invert 1 0 0 0 loopback: Tx input data to Rx output port. RXEN/RXSYNC 3 Rx 5/5 Nibble 1 N/A N/A 0 2 LS Nibble First 1 N/A N/A 0 1 RXCLK Neg. Edge 1 0 0 0 0 Twos Complement 1 0 0 1 DIGITAL OUTPUT DRIVE STRENGTH, TxDAC OUTPUT, AND REV ID 0x0E 7 Low Digital Drive 1 0 0 0 Default setting is for high drive strength Strength and IAMP enabled. 0 TxDAC Output 1 0 0 0 0x0F 3:0 REV ID Number 4 0x00 0x00 0x00 Tx IAMP GAIN AND BIAS CONTROL 0x10 7 Select Tx Gain 1 0x04 0x04 0x04 N = 0, 1, 2, 3, 4. 2:0 N 3 0x04 0x04 0x04 0x12 6:4 Standing Current 3 0x01 0x01 0x01 Standing current. 2:0 IOFF1 Standing 3 0x01 0x01 0x01 Current 0x13 7:5 CPGA Bias Adjust 3 0x00 0x00 0x00 Current bias setting for Rx path’s functional blocks. Refer to the Power 4:3 SPGA Bias Adjust 2 Reduction Options section. 2:0 ADC Bias Adjust 4 1 Bits that are undefined should always be assigned a 0. 2 Full-duplex only. Rev. 0 | Page 13 of 36 AD9868 REGISTER MAP DESCRIPTION An 8-bit instruction header must accompany each read and write operation. The instruction header is shown in Table 12. The AD9868 contains a set of programmable registers (see W The MSB is an R/ indicator bit with logic high indicating a Table 10) that are used to optimize its numerous features, read operation. The next two bits, N1 and N0, specify the interface options, and performance parameters from its default number of bytes (one to four bytes) to be transferred during the register settings. Registers pertaining to similar functions have data transfer cycle. The remaining five bits specify the address been grouped together and assigned adjacent addresses to bits to be accessed during the data transfer portion. The data minimize the update time when using the multibyte serial port bits immediately follow the instruction header for both read interface (SPI) read/write feature. Bits that are undefined within and write operations. a register should be assigned a 0 when writing to that register. The default register settings are intended to allow some applica- Table 12. Instruction Header Information tions to operate without using an SPI. The AD9868 can be MSB LSB configured to support a half- or full-duplex digital interface via 17 16 15 14 13 12 11 10 the MODE pin, with each interface having two possible default R/W N1 N0 A4 A3 A2 A1 A0 register settings determined by the setting of the CONFIG pin. The AD9868 serial port can support both MSB (most significant For instance, applications that need to use only the Tx or Rx path bit) first and LSB (least significant bit) first data formats. Figure 3 functionality can configure the AD9868 for a half-duplex interface illustrates how the serial port words are built for the MSB first (MODE = 0), and use the TXEN pin to select between the Tx or and Figure 4 illustrates LSB first modes. The bit order is Rx signal path with the unused path remaining in a reduced controlled by the SPI LSB first bit (Register 0x00, Bit 6). The power state. The CONFIG pin can be used to select the default default value is 0, MSB first. Multibyte data transfers in MSB interpolation ratio of the Tx path and RxPGA gain mapping. format can be completed by writing an instruction byte that includes the register address of the last address to be accessed. SERIAL PORT INTERFACE (SPI) The AD9868 automatically decrements the address for each The serial port of the AD9868 has 3-wire or 4-wire SPI capability successive byte required for the multibyte communication cycle. allowing read/write access to all registers that configure the device’s INSTRUCTION CYCLE DATA TRANSFER CYCLE internal parameters. Registers pertaining to the SPI are listed in SEN Table 11. The default 3-wire serial communication port consists SCLK SEN of a clock (SCLK), serial port enable ( ), and a bidirectional SDATA R/W N1 N2 A4 A3 A2 A1 A0 D7 D6 D1 D0 1 1 N N data (SDIO) signal. SEN is an active low, control gating, read and write cycle. When SEN is high, SDO and SDIO are three- stated. The inputs to SCLK, SEN, and SDIO contain a Schmitt Figure 3. SPI Timing, MSB First trigger with a nominal hysteresis of 0.4 V centered about DRVDD/2. The SDO pin remains three-stated in a 3-wire SPI INSTRUCTION CYCLE DATA TRANSFER CYCLE SEN interface. SCLK Table 11. SPI Registers Pertaining to SPI Options SDATA A0 A1 A2 A3 A4 N2 N1 R/W D0 D1 D6 D7 1 1 N N Address (Hex) Bit Description 0x00 7 Enable 4-wire SPI. Figure 4. SPI Timing, LSB First 6 Enable SPI LSB first. A 4-wire SPI can be enabled by setting the 4-wire SPI bit high, When the SPI LSB first bit is set high, the serial port interprets causing the output data to appear on the SDO pin instead of on the both instruction and data bytes LSB first. Multibyte data transfers SDIO pin. The SDIO pin serves as an input-only throughout the in LSB format can be completed by writing an instruction byte read operation. Note that the SDO pin is active only during the that includes the register address of the first address to be accessed. transmission of data and remains three-stated at any other time. The AD9868 automatically increments the address for each successive byte required for the multibyte communication cycle. Rev. 0 | Page 14 of 36 06733-003 06733-004 AD9868 Figure 5 illustrates the timing requirements for a write opera- Figure 6 illustrates the timing for a 3-wire read operation to the SEN SEN tion to the SPI port. After the serial port enable ( ) signal SPI port. After goes low, data (SDIO) pertaining to the goes low, data (SDIO) pertaining to the instruction header is instruction header is read on the rising edges of SCLK. A read read on the rising edges of the clock (SCLK). To initiate a write operation occurs if the read/not-write indicator is set high. operation, the read/not-write bit is set low. After the instruction After the address bits of the instruction header are read, the header is read, the eight data bits pertaining to the specified eight data bits pertaining to the specified register are shifted out register are shifted into the SDIO pin on the rising edge of the of the SDIO pin on the falling edges of the next eight clock next eight clock cycles. If a multibyte communication cycle is cycles. If a multibyte communication cycle is specified in the specified, the destination address is decremented (MSB first) instruction header, a similar process as previously described for and shifts in another eight bits of data. This process repeats until a multibyte SPI write operation applies. The SDO pin remains all the bytes specified in the instruction header (N1 bit, N0 bit) three-stated in a 3-wire read operation. are shifted into the SDIO pin. SEN must remain low during the Figure 7 illustrates the timing for a 4-wire read operation to the data transfer operation, only going high after the last bit is SPI port. The timing is similar to the 3-wire read operation with shifted into the SDIO pin. the exception of the data appearing at the SDO pin, while the SDIO pin remains at high impedance throughout the operation. The SDO pin is an active output only during the data transfer phase and remains three-stated at all other times. t 1/f S SCLK t H SEN t t LOW HI SCLK t DS t DH SDIO N1 N0 A0 D7 D6 D1 D0 R/W Figure 5. SPI Write Operation Timing t 1/f S SCLK SEN t t LOW HI SCLK t DV t DS t t DH EZ N1 A2 A1 A0 D7 D6 D1 D0 SDIO R/W Figure 6. SPI 3-Wire Read Operation Timing t 1/f S SCLK SEN t t LOW HI SCLK t DS t t DH EZ N1 A2 A1 A0 SDIO R/W t EZ t DV SDO D7 D6 D1 D0 Figure 7. SPI 4-Wire Read Operation Timing Rev. 0 | Page 15 of 36 06733-006 06733-007 06733-005 AD9868 DIGITAL INTERFACE The digital interface port is configurable for half-duplex or full- The output from the receive path is driven onto the ADIO bus duplex operation by pin strapping the MODE pin low or high, when the RXEN pin is high and when a clock is present on the respectively. In half-duplex mode, the digital interface port RXCLK pin. While the output latch is enabled by RXEN, valid becomes a 10-bit bidirectional bus called the ADIO port. In data appears on the bus after a 6-clock-cycle delay due to the full-duplex mode, the digital interface port is divided into two internal FIFO delay. Note that Rx data is not latched back into 6-bit ports called Tx[5:0] and Rx[5:0] for simultaneous Tx and the Tx path if TXEN is high during this interval with TXCLK Rx operations. In this mode, data is transferred between the present. The ADIO bus becomes three-stated once the RXEN ASIC and AD9868 in 6-bit (or 5-bit) nibbles. The AD9868 also pin returns low. Figure 9 shows the receive path output timing. features a flexible digital interface for updating the RxPGA and TxPGA gain registers via a 6-bit PGA port or Tx[5:0] port for RXCLK fast updates, or via the SPI port for slower updates. See the t RXEN OD t t t PZL VT PLZ RxPGA Control section for more information. RX0 RX1 RX2 RX3 ADIO[9:0] HALF-DUPLEX MODE Figure 9. Receive Data Output Timing Diagram The half-duplex mode is selected when the MODE pin is tied low. In this mode, the bidirectional ADIO port is typically To add flexibility to the digital interface port, several program- shared in burst fashion between the transmit path and receive ming options are available in the SPI registers. These options path. Two control signals, TXEN and RXEN, from a DSP (or are listed in Table 13. The default Tx and Rx data input formats digital ASIC) control the bus direction by enabling the ADIO are straight binary, but can be changed to twos complement. port’s input latch and output driver, respectively. Two clock The default TXEN and RXEN settings are active high, but can signals are also used, TXCLK to latch the Tx input data, and be set to opposite polarities, thus allowing them to share the RXCLK to clock the Rx output data. The ADIO port can be same control. In this case, the ADIO port can still be placed disabled by setting TXEN and RXEN low (default setting), thus onto a shared bus by disabling its input latch via the control allowing it to be connected to a shared bus. signal, and disabling the output driver via the SPI register. The clock timing can be independently changed on the transmit and Internally, the ADIO port consists of an input latch for the Tx receive paths by selecting either the rising or falling clock edge path in parallel with an output latch with three-state outputs for as the validating/sampling edge of the clock. Lastly, the output the Rx path. TXEN is used to enable the input latch; RXEN is driver strength can be reduced for lower data rate applications. used to three-state the output latch. A five-sample-deep FIFO is used on the Tx and Rx paths to absorb any phase difference Table 13. SPI Registers for Half-Duplex Interface between the AD9868 internal clocks and the externally supplied Address (Hex) Bit Description clocks (TXCLK, RXCLK). The ADIO bus accepts input data- 0x0C 4 Invert TXEN. words into the transmit path when the TXEN pin is high, the 1 TXCLK negative edge. RXEN pin is low, and a clock is present on the TXCLK pin, as shown in Figure 8. 0 Twos complement. 0x0D 5 Rx port three-state. 4 Invert RXEN. t DS 1 RXCLK negative edge. TXCLK 0 Twos complement. TXEN t t 0x0E 7 Low digital drive strength. DIS EN t DH TX2 ADIO[9:0] TX0 TX1 TX3 TX4 The half-duplex interface can be configured to act as a slave or a master to the digital ASIC. An example of a slave configuration is shown in Figure 10. In this example, the AD9868 accepts all RXEN the clock and control signals from the digital ASIC. Because the Figure 8. Transmit Data Input Timing Diagram sampling clocks for the DAC and ADC are derived internally from the OSCIN signal, the TXCLK and RXCLK signals must The Tx interpolation filter(s) following the ADIO port can be be at exactly the same frequency as the OSCIN signal. The flushed with zeros if the clock signal into the TXCLK pin is phase relationships among the TXCLK, RXCLK, and OSCIN present for 33 clock cycles after TXEN goes low. Note that the signals can be arbitrary. If the digital ASIC cannot provide a low data on the ADIO bus is irrelevant over this interval. jitter clock source to OSCIN, use the AD9868 to generate the clock for its DAC and ADC and to pass the desired clock signal to the digital ASIC via CLKOUT1 or CLKOUT2. Rev. 0 | Page 16 of 36 06733-008 06733-009 AD9868 DIGITAL ASIC AD9868 In either application, Tx data and Rx data are transferred between the ASIC and AD9868 in 6-bit (or 5-bit) nibbles at 10 ADIO TO twice the internal input/output word rates of the Tx interpolation [9:0] Tx DIGITAL Tx/Rx FILTER filter and ADC. Note that the TxDAC update rate must not be DATA[9:0] 10 FROM less than the nibble rate. Therefore, the 2× or 4× interpolation Rx ADC filter must be used with a full-duplex interface. RXEN RXEN The AD9868 acts as the master, providing RXCLK as an output TXEN TXEN TXCLK DACCLK clock that is used for the timing of both the Tx[5:0] and Rx[5:0] ADCCLK RXCLK ports. RXCLK always runs at the nibble rate and can be inverted CLKOUT OSCIN or disabled via an SPI register. Because RXCLK is derived from the clock synthesizer, it remains active provided that this Figure 10. Example of a Half-Duplex Digital Interface functional block remains powered on. A buffered version of the with AD9868 Serving as the Slave signal appearing at OSCIN can also be directed to RXCLK by setting Bit 2 of Register 0x05. This feature allows the AD9868 to Figure 11 shows a half-duplex interface with the AD9868 acting be completely powered down (including the clock synthesizer) as the master, generating all the required clocks. CLKOUT1 while serving as the master. provides a clock equal to the bus data rate that is fed to the ASIC as well as back to the TXCLK and RXCLK inputs. This The Tx[5:0] port operates in the following manner with the SPI interface has the advantage of reducing the digital ASIC pin register default settings: count by three. The ASIC needs only to generate a bus control 1. Two consecutive nibbles of the Tx data are multiplexed signal that controls the data flow on the bidirectional bus. together to form a 10-bit data-word in twos complement DIGITAL ASIC AD9868 format. 2. The clock appearing on the RXCLK pin is a buffered 10 ADIO TO version of the internal clock used by the Tx[5:0] port’s [9:0] Tx DIGITAL Tx/Rx FILTER input latch with a frequency that is always twice the ADC DATA[9:0] 10 FROM sample rate (2 × f ). ADC Rx ADC 3. Data from the Tx[5:0] port is read on the rising edge of this RXEN sampling clock, as illustrated in the timing diagram shown TXEN BUS_CTR in Figure 12. Note that TXQUIET must remain high for the TXCLK reconstructed Tx data to appear as an analog signal at the RXCLK output of the TxDAC or IAMP. CLKIN CLKOUT1 4. The TXSYNC signal is used to indicate which word OSCIN belongs to which nibble. While TXSYNC is low, the first FROM nibble of every word is read as the most significant nibble. CRYSTAL OR MASTER CLK The second nibble of that same word is read on the Figure 11. Example of a Half-Duplex Digital Interface following TXSYNC high level as the least significant with AD9868 Serving as the Master nibble. If TXSYNC is low for more than one clock cycle, the last transmit data is read continuously until TXSYNC is FULL-DUPLEX MODE brought high for the second nibble of a new transmit word. The full-duplex mode interface is selected when the MODE pin This feature can be used to flush the interpolator filters is tied high. It can be used for full- or half-duplex applications. with zeros. Note that the GAIN signal must be kept low The digital interface port is divided into two 6-bit ports called during a Tx operation. Tx[5:0] and Rx[5:0], allowing simultaneous Tx and Rx operations t DS for full-duplex applications. In half-duplex applications, the Tx[5:0] t SU port can also be used to provide a fast update of the RxPGA RXCLK during an Rx operation. This feature is enabled by default and t t HD DH can be used to reduce the required pin count of the ASIC (refer TXSYNC to RxPGA Control section for details). Tx[5:0] Tx0LSB Tx1MSB Tx1LSB Tx2MSB Tx Tx3L 2 L S S B B Tx3MSB Figure 12. Tx[5:0] Port Full-Duplex Timing Diagram Rev. 0 | Page 17 of 36 06733-010 06733-011 06733-012 AD9868 The Rx[5:0] port operates in the following manner with the SPI The default Tx and Rx data input formats are twos complement, register default settings: but can be changed to straight binary. The default TXSYNC and RXSYNC settings can be changed such that the first nibble of the 1. Two consecutive nibbles of the Rx data are multiplexed word appears while either TXSYNC, RXSYNC, or both are high. together to form a 10-bit data-word in twos complement In addition, the least significant nibble can be selected as the format. first nibble of the word (least significant nibble first). The output 2. The Rx data is valid on the rising edge of RXCLK, as driver strength can also be reduced for lower data rate applications. illustrated in the timing diagram shown in Figure 13. 3. The RXSYNC signal is used to indicate which word belongs For the AD9868, the most significant nibble defaults to 6 bits, to which nibble. While RXSYNC is low, the first nibble of and the least significant nibble defaults to 4 bits. This can be every word is transmitted as the most significant nibble. changed so that the least significant nibble and most significant The second nibble of that same word is transmitted on the nibble have 5 bits each. To accomplish this, set the 5/5 nibble bit following RXSYNC high level as the least significant nibble. (Bit 3 in Register 0x0C and Bit 3 in Register 0x0D), and use the Tx[5:1] and Rx[5:1] data pins. t DH RXCLK Figure 14 shows a possible digital interface between an ASIC and the AD9868. The AD9868 serves as the master generating t DV RXSYNC the required clocks for the ASIC. This interface requires that the ASIC reserve 16 pins for the interface, assuming a 6-bit nibble Rx2MSB Rx3MSB Rx[5:0] Rx0LSB Rx1MSB Rx1LSB Rx3LSB width and the use of the Tx port for RxPGA gain control. Note that the ASIC pin allocation can be reduced by 3 if a 5-bit nibble Figure 13. Full-Duplex Rx Port Timing width is used and the gain (or gain strobe) of the RxPGA is To add flexibility to the full-duplex digital interface port, several controlled via the SPI port. programming options are available in the SPI registers. These AD9868/AD9869 DIGITAL ASIC options are listed in Table 14. The timing for the Tx[5:0] and/or 6 TO OPTIONAL Rx[5:0] ports can be independently changed by selecting either GAIN RxPGA the rising or falling clock edge as the sampling/validating edge Tx[5:0] 10/12 of the clock. Inverting RXCLK (via Bit 1 of Register 0x05) affects TO Tx DATA[5:0] Tx DIGITAL both the Rx and Tx interface because they both use RXCLK. FILTER Table 14. SPI Registers for Full-Duplex Interface Rx[5:0] 10/12 FROM Rx DATA[5:0] Address (Hex) Bit Description RxADC 0x05 2 OSCIN to RXCLK. 1 Invert RXCLK. RX_SYNC RXSYNC 0 Disable RXCLK. TXSYNC TX_SYNC 0x0B 2 Rx gain on Tx port. RXCLK CLKIN 0x0C 4 Invert TXSYNC. CLKOUT1 3 Tx 5/5 nibble. CLKOUT2 2 LS nibble first. 1 TXCLK negative edge. OSCIN 0 Twos complement. FROM CRYSTAL 0x0D 5 Rx port three-state. OR MASTER CLK 4 Invert RXSYNC. Figure 14. Example of a Full-Duplex Digital Interface 3 Rx 5/5 nibble. with Optional RxPGA Gain Control via Tx[5:0] 2 LS nibble first. 1 RXCLK negative edge. 0 Twos complement. 0x0E 7 Low digital drive strength. Rev. 0 | Page 18 of 36 06733-013 DEMUX MUX 06733-014 AD9868 RxPGA CONTROL Updating the RxPGA via the Tx[5:0] port is an option only in 1 2 full-duplex mode . In this case, a high level on the GAIN pin The AD9868 contains a digital PGA in the Rx path that is used with TXSYNC low programs the PGA setting on either the to extend the dynamic range. The RxPGA can be programmed rising edge or falling edge of RXCLK, as shown in Figure 16. over −12 dB to +48 dB with 1 dB resolution using a 6-bit word, The GAIN pin must be held high, TXSYNC must be held low, and with a 0 dB setting corresponding to a 2 V p-p input signal. and gain data must be stable for one or more clock cycles to The 6-bit word is fed into a look-up table (LUT) that is used to update the RxPGA gain setting. distribute the desired gain over three amplification stages within the Rx path. Upon power-up, the RxPGA gain register is set A low level on the GAIN pin enables data to be fed to the digital to its minimum gain of −12 dB. The RxPGA gain mapping is interpolation filter. This interface should be considered when shown in Figure 15. upgrading existing designs from the AD9875/AD9876 MxFE 48 products or from half-duplex applications trying to minimize 42 an ASIC pin count. 36 t SU 30 RXCLK 24 t HD TXSYNC 18 12 Tx[5:0] GAIN 6 0 GAIN –6 Figure 16. Updating RxPGA via Tx[5:0] in Full-Duplex Mode –12 0 612 18 24 30 36 42 48 54 60 66 Updating the RxPGA (or TxPGA) via the PGA[5:0] port is 6-BIT DIGITAL WORD-DECIMAL EQUIVALENT 3 an option for both the half-duplex and full-duplex interface. Figure 15. Digital Gain Mapping of RxPGA The PGA port consists of an input buffer that passes the 6-bit data appearing at its input directly to the RxPGA (or TxPGA) Table 15 lists the SPI registers pertaining to the RxPGA. gain register with no gating signal required. Bit 5 or Bit 6 of Register 0x0B is used to select whether the data updates the Table 15. SPI Registers for RxPGA Control RxPGA or TxPGA gain register. In applications that switch Address between RxPGA and TxPGA gain control via PGA[5:0], be (Hex) Bit Description sure that the RxPGA (or TxPGA) is not inadvertently loaded 0x09 6 Enable RxPGA update via SPI. with the wrong data during a transition. In the case of an 5:0 RxPGA gain code. RxPGA-to-TxPGA transition, first deselect the RxPGA gain 0x0B 6 Select TxPGA via PGA[5:0]. register, update the PGA[5:0] port with the desired TxPGA gain 5 Select RxPGA via PGA[5:0]. setting, and then select the TxPGA gain register. 3 Enable software gain strobe, full-duplex. 2 Enable RxPGA update via Tx[5:0], full-duplex. Note that a silicon bug exists with the full-duplex interface 1 3-Bit RxPGA gain mapping, half-duplex. (MODE = 1), which requires that the GAIN/PGA[5] pin remains low for the digital Tx path to remain enabled. Full- The RxPGA gain register can be updated via the Tx[5:0] port, duplex protocol applications must use the SPI port to control the PGA[5:0] port, or the SPI port. The first two methods allow the Tx and Rx gain. Half-duplex protocol applications using the fast updates of the RxPGA gain register and should be considered function can use an AND gate with TXQUIET and the PGA5 for digital AGC functions requiring a fast closed-loop response. bit serving as inputs to ensure that the GAIN/PGA[5] pin The SPI port allows direct update and readback of the RxPGA remains low during a Tx operation. gain register via Register 0x09 with an update rate limited to 1.6 MSPS (with SCLK = 32 MHz). Note that Bit 6 of Register 0x09 must be set for a read or write operation. 1 Default setting for full-duplex mode (MODE = 1). 2 The gain strobe can also be set in software via Register 0x0B, Bit 3 for continuous updating. This eliminates the requirement for the external gain signal, reducing the ASIC pin count by 1. 3 Default setting for half-duplex mode (MODE = 0). Rev. 0 | Page 19 of 36 GAIN (dB) 06733-015 06733-016 AD9868 The TxPGA register can be updated via the PGA[5:0] port or TxPGA CONTROL SPI port. The first method should be considered for fast updates The AD9868 also contains a digital PGA in the Tx path distri- of the TxPGA register. Its operation is similar to the description buted between the TxDAC and IAMP. The TxPGA is used to in the RxPGA Control section. The SPI port allows direct control the peak current from the TxDAC and IAMP over a update and readback of the TxPGA register via Register 0x0A 7.5 dB and 19.5 dB span, respectively, with 0.5 dB resolution. with an update rate limited to 1.6 MSPS (SCLK = 32 MHz). A 6-bit word is used to set the TxPGA attenuation according to Bit 6 of Register 0x0A must be set for a read or write operation. the mapping shown in Figure 17. The TxDAC gain mapping is applicable only when Bit 0 of Register 0x0E is set, and only Table 16 lists the SPI registers pertaining to the TxPGA. The when the 4 LSBs of the 6-bit gain word are relevant. TxPGA control register default setting is for minimum attenua- tion (0 dBFS) with the PGA[5:0] port disabled for Tx gain control. 0 –1 –2 Table 16. SPI Registers TxPGA Control –3 –4 Address (Hex) Bit Description –5 –6 0x0A 6 Enable TxPGA update via SPI. –7 –8 5:0 TxPGA gain code. –9 TxDACs IOUTP OUTPUT –10 HAS 7.5dB RANGE 0x0B 6 Select TxPGA via PGA[5:0]. –11 5 Select RxPGA via PGA[5:0]. –12 –13 0x0E 0 TxDAC output (IAMP disabled). –14 –15 –16 IAMPs IOUTN OUTPUT HAS 19.5dB RANGE –17 –18 –19 –20 0 8 16 24 32 40 48 56 64 6-BIT DIGITAL CODE (Decimal Equivalent) Figure 17. Digital Gain Mapping of TxPGA Rev. 0 | Page 20 of 36 Tx ATTENUATION (dBFS) 06733-017 AD9868 TRANSMIT PATH The transmit path of the AD9868 (or its related part, the AD9869) These responses also include the inherent sinc(x) from the of a selectable digital 2×/4× interpolation filter, a 10-bit (or12-bit) TxDAC reconstruction process and can be used to estimate any TxDAC, and a current-output amplifier, IAMP (see Figure 18). post analog filtering requirements. Note that the additional two bits of resolution offered by the The pipeline delays of the 2× and 4× filter responses are AD9869 result in a 10 dB to 12 dB reduction in the pass-band 21.5 clock cycles and 24 clock cycles, respectively, relative to noise floor. The digital interpolation filter relaxes the Tx analog f . The filter delay is also taken into consideration for DATA filtering requirements by simultaneously reducing the images applications configured for a half-duplex interface with the half- from the DAC reconstruction process while increasing the analog duplex power-down mode enabled. This feature allows the user filter’s transition band. The digital interpolation filter can also to set a programmable delay that powers down the TxDAC and be bypassed, resulting in lower digital current consumption. IAMP only after the last Tx input sample has propagated through the digital filter. See the Power Control and Dissipation section for more details. 10 2.5 ADIO[9:4]/ WIDE BAND 2-4× IOUTN+ 10 TxDAC Tx[5:0] IAMP 0 2.0 IOUTN– 1.5 –10 0 TO –12dB 0 TO –7.5dB ADIO[3:0]/ 1.0 –20 Rx[5:2] AD9868 –30 0.5 TXEN/SYNC PASS BAND 0 –40 TXCLK –0.5 –50 –1.0dB @ 0.441 f DATA Figure 18. Functional Block Diagram of Tx Path –60 –1.0 –70 –1.5 DIGITAL INTERPOLATION FILTERS –2.0 –80 The input data from the Tx port can be fed into a selectable –90 –2.5 2×/4× interpolation filter. The interpolation factor for the 0 0.25 0.50 0.75 1.00 1.25 1.75 2.00 1.50 digital filter is set via SPI Register 0x0C with the settings shown NORMALIZED FREQUENCY (Relative to f ) DATA in Table 17. The maximum input word rate, f , into the DATA Figure 19. Frequency Response of 2× Interpolation Filter interpolation filter is 80 MSPS; the maximum DAC update rate (Normalized to f ) DATA is 200 MSPS. Therefore, applications with input word rates at or 2.5 10 below 50 MSPS can benefit from 4× interpolation, whereas WIDE BAND 0 2.0 applications with input word rates between 50 MSPS and –10 1.5 80 MSPS can benefit from 2× interpolation. 1.0 –20 Table 17. Interpolation Factor Set via SPI Register 0x0C –30 0.5 PASS BAND Bits 7:6] Interpolation Factor –40 0 00 4 –1.0dB @ 0.45 f DATA –0.5 –50 01 2 –1.0 –60 10 Do not use –70 –1.5 11 Do not use –2.0 –80 The interpolation filter consists of two cascaded half-band filter –2.5 –90 stages with each stage providing 2× interpolation. The first 0 0.5 1.0 1.5 2.0 2.5 3.5 4.0 3.0 NORMALIZED FREQUENCY (Relative to f ) stage filter consists of 43 taps. The second stage filter, operating DATA at the higher data rate, consists of 11 taps. The normalized Figure 20. Frequency Response of 4× Interpolation Filter (Normalized to fDATA) wideband and pass-band filter responses (relative f ) for the DATA 2× low-pass interpolation filter and 4× low-pass interpolation filter are shown in Figure 19 and Figure 20, respectively. Rev. 0 | Page 21 of 36 IOUTP+ IOUTP– 06733-018 WIDEBAND RESPONSE (dB) WIDEBAND RESPONSE (dB) PASS-BAND RESPONSE (dB) PASS-BAND RESPONSE (dB) 06733-020 06733-019 AD9868 TxDAC AND IAMP ARCHITECTURE The value of I is determined by the R value at the REFADJ SET pin along with the Tx path’s digital attenuation setting. With The Tx path contains a TxDAC with a current amplifier, IAMP. 0 dB attenuation, the value of I is The TxDAC reconstructs the output of the interpolation filter and sources a differential current output that can be directed to I = 16 × (1.23/RSET) (1) an external load or fed into the IAMP for further amplification. For example, an RSET value of 1.96 kΩ results in I equal to 10.0 mA The TxDAC and IAMP peak current outputs are digitally with IOUTP_FS equal to 20.0 mA. Note that the REFIO pin programmable over a 0 dB to −7.5 dB and 0 dB to −19.5 dB provides a nominal band gap reference voltage of 1.23 V and range, respectively, in 0.5 dB increments. Note that this assumes should be decoupled to analog ground via a 0.1 μF capacitor. default register settings for Register 0x10 and Register 0x11. The differential current output of the TxDAC is always Applications demanding the highest spectral performance connected to the IOUTP pins, but it can be directed to the and/or lowest power consumption can use the TxDAC output IAMP by clearing Bit 0 of Register 0x0E. As a result, the directly. The TxDAC is capable of delivering a peak signal IOUTP pins must remain completely open if the IAMP is to power-up to 10 dBm while maintaining respectable linearity be used. The IAMP consists of programmable current mirrors performance. For power-sensitive applications requiring the providing a gain factor of N that is programmable from 0 to 4 in highest Tx power efficiency, the TxDAC full-scale current steps of 1 (via Bits[2:0] of Register 0x10 with a default setting of output can be reduced to as low as 2 mA, and its load resistors N = 4). Bit 7 of this register must be set to overwrite the default sized to provide a suitable voltage swing that can be amplified settings of this register. The maximum peak current per output by a low power, op amp-based driver. is 100 mA and occurs when the TxDAC standing current, I, is Most applications requiring higher peak signal powers (up to set for 12.5 mA (IOUTP_FS = 25 mA). 17 dBm) should use the IAMP. The IAMP can be configured Because the current mirrors consist of NMOS devices, they sink as a current source for loads having a well-defined impedance current. Therefore, each output pin requires a dc current path to (50 Ω or 75 Ω systems). a positive supply. The voltage output of each output pin is Figure 21 shows the equivalent schematic of the TxDAC and allowed to swing between 0.5 V and 3.9 V. Lastly, both the IAMP. The TxDAC provides a differential current output standing current, I, and the ac current, ΔI , from the TxDAC are S appearing at IOUTP+ and IOUTP−. The TxDAC can also be amplified by the gain factor (N) with the total standing current modeled as a differential current source generating a signal- drawn from the positive supply being equal to dependent ac current, when ΔIS has a peak current of I along 2 × (N) × I (2) with two dc current sources, sourcing a standing current equal to I. The full-scale output current, IOUTP_FS, is equal to the Programmable current sources, IOFF1 via Register 0x12, can be sum of these standing current sources (IOUTP_FS = 2 × I). used to improve the linearity performance under certain conditions by increasing their signal-to-standing current ratios. This feature provides a marginal improvement in distortion performance under large signal conditions when the peak ac current of the reconstructed waveform frequently approaches TxDAC the dc standing current within the TxDAC (0 dBFS to −1 dBFS I I sine wave) causing the internal mirrors to turn off. However, the ±ΔI S REFADJ improvement in distortion performance diminishes as the crest REFIO factor (peak-to-rms ratio) of the ac signal increases. Most R 0.1µF SET applications can disable these current sources (set to 0 mA via I I OFF1 OFF1 I +ΔI IOUTP+ Register 0x12) to reduce the IAMP current consumption. I –ΔI IOUTP– Table 18. SPI Registers for TxDAC and IAMP xN xN Address (Hex) Bit Description 0x0E 0 TxDAC output. IAMP 0x10 7 Enable current mirror gain settings. Figure 21. Equivalent Schematic of TxDAC and IAMP 2:0 Primary path NMOS gain of 0 to 4 with ∆ = 1. 0x12 2:0 I standing current. OFF1 Rev. 0 | Page 22 of 36 N × (I +ΔI) IOUTN+ N × (I –ΔI) IOUTN– 06733-021 AD9868 Optimum distortion performance can typically be achieved by Tx PROGRAMMABLE GAIN CONTROL performing both of the following: TxPGA functionality is also available to set the peak output current from the TxDAC or IAMP. The TxDAC and IAMP are • Limiting the peak positive V and V to 0.8 V to IOUTP+ IOUTP − digitally programmable via the PGA[5:0] port or SPI over a 0 dB avoid onset of TxDAC output compression (TxDAC to −7.5 dB range and 0 dB to −19.5 dB range, respectively, in voltage compliance is around 1.2 V). 0.5 dB increments. • Limiting V p-p seen at IOUTP+ and IOUTP− to less than 1.6 V. The TxPGA can be considered as two cascaded attenuators with the TxDAC providing a 7.5 dB range in 0.5 dB increments, and Applications demanding higher output voltage swings and the IAMP providing a 12 dB range in 6 dB increments. As a result, power drive capabilities can benefit from using the IAMP. the IAMP composite 19.5 dB span is valid only if Register 0x10 remains at its default setting of 0x04. Modifying this register IAMP CURRENT-MODE OPERATION setting corrupts the LUT and results in an invalid gain mapping. The IAMP can be configured for the current-mode operation (see Figure 23) for loads remaining relatively constant. In this TxDAC OUTPUT OPERATION mode, the IAMP delivers the signal-dependent current to the The differential current output of the TxDAC is available at the load via a center-tap transformer. Because the mirrors exhibit a IOUTP+ and IOUTP− pins, and the IAMP should be disabled high output impedance, they can be easily back-terminated (if by setting Bit 0 of Register 0x0E. Any load connected to these required). pins must be ground referenced to provide a dc path for the AVDD current sources. Figure 22 shows the outputs of the TxDAC 0.1µF driving a doubly terminated 1:1 transformer with its center tap R SET R CM tied to ground. The peak-to-peak voltage, V p-p, across RL (and 0.1µF I = 2 × N × I BIAS IOUTP+ to IOUTP−) is equal to 2 × I × (RL||RS). With I = 10 mA and RL = RS = 50 Ω, V p-p is equal to 0.5 V with 1 dBm of peak IOUTN+ T:1 power being delivered to RL and 1 dBm being dissipated in RS. IOUT PK R 1:1 IAMP TxDAC L R R S L IOUTN– 0 TO –7.5dB 0 TO –12dB 0.1µF R SET IOUT = N × I PK 2 2 POUT = (IOUT ) × T × R PK PK L Figure 23. Current-Mode Operation IOUTN+ TxDAC IAMP The IAMP gain, N, can be set between 0 and 4, while the TxDAC standing current, I, can be set between 2 mA and 0TO –7.5dB 0 TO –12dB IOUTN– 12.5 mA (with the IOUTP outputs left open). The IOUTN outputs should be connected to the transformer, which needs to be specified to handle the dc standing current, I , that is BIAS drawn by the IAMP. In addition, because I remains signal BIAS Figure 22. TxDAC Output Directly via Center-Tap Transformer independent, a series resistor should be inserted between The TxDAC is capable of delivering up to 10 dBm peak power AVDD and the center-tap transformer to provide provisions to a load, R . To increase the peak power for a fixed standing such that the IAMP common-mode voltage, VCM, can be L reduced since its optimum linearity performance is sensitive to current, users must increase V p-p across IOUTP+ and IOUTP− both the Tx signal’s peak-to-rms characteristics as well as the by increasing one or more of the following parameters: RS, RL IAMP V . Note that the V bias should not exceed 3.3 V. The (if possible), and/or the turns ratio, N, of the transformer. For CM CM power dissipated in the IAMP alone is as follows: example, removing the RS from Figure 22 and applying a 2:1 impedance ratio transformer results in 10 dBm of peak power P = 2 × N × I × V (3) IAMP CM capabilities to the load. Note that increasing the power output capabilities of the TxDAC reduces the distortion performance due to the higher voltage swings seen at IOUTP+ and IOUTP−. Rev. 0 | Page 23 of 36 REFIO REFADJ IOUTP+ IOUTP– 06733-022 REFIO REFADJ IOUTP+ IOUTP– 06733-023 AD9868 RECEIVE PATH The PGA input is self-biased at a 1.3 V common-mode level, allow- The receive signal path for the AD9868 (or its related part, the ing maximum input voltage swings of ±1.5 V at RX+ and RX−. AD9869) consists of a 3-stage RxPGA, a 3-pole programmable LPF, and a 10-bit (or 12-bit) ADC (see Figure 24). Note that the AC-coupling the input signal to this stage via 0.1 μF coupling additional two bits of resolution offered by the AD9869 result in capacitors is recommended to ensure that any external dc offset a 3 dB to 5 dB lower noise floor, depending on the RxPGA gain does not become amplified with high RxPGA gain settings, setting and LPF cutoff frequency. Also working in conjunction with potentially exceeding the ADC input range. the receive path is an offset correction circuit. These blocks are discussed in detail in the following sections. Note that the power To limit the RxPGA self-induced input offset, an offset cancella- tion loop is included. This cancellation loop is automatically consumption of the RxPGA can be modified via Register 0x13 as discussed in the Power Control and Dissipation section. performed upon power-up and can also be initiated via the SPI. During calibration, the RxPGA first stage is internally shorted, and each gain stage set to a high gain setting. A digital servo ADIO[9:4]/ Tx[5:0] loop slaves a calibration DAC, which forces the Rx input offset CLKOUT1 CLK SYNC. CLKOUT2 to be within ±32 LSBs for this particular high gain setting. M 2 CLK OSCIN ADIO[3:0]/ Although the offset varies for other gain settings, the offset is MULTIPLIER XTAL Rx[5:2] typically limited to ±5% of the ADC 2 V input span. Note that the offset cancellation circuitry is intended to reduce the voltage 10/12 RX+ RXEN/SYNC ADC 2-POLE 1-POLE SPGA LPF LPF RXCLK 80MSPS RX– offset attributed to only the RxPGA input stage, not to any dc offsets attributed to an external source. 0TO 6dB –6 TO 18dB –6 TO 24dB Δ = 1dB Δ = 6dB Δ = 6dB The gain of the RxPGA should be set to minimize clipping of GAIN the ADC while utilizing most of its dynamic range. The maximum 6 PGA[5:0] MAPPING peak-to-peak differential voltage that does not result in ADC PORT LUT 4 REGISTER clipping is shown in Figure 25. Although the graph suggests that SPI AD9868 CONTROL PORT the maximum input signal for a gain setting of −12 dB is 8.0 V p-p, the maximum input voltage into the PGA should be limited to Figure 24. Functional Block Diagram of Rx Path less than 6 V p-p to prevent turning on ESD protection diodes. Rx PROGRAMMABLE GAIN AMPLIFIER For applications having higher maximum input signals, consider adding an external resistive attenuator network. While the input The RxPGA has a digitally programmable gain range from sensitivity of the Rx path is degraded by the amount of attenuation −12 dB to +48 dB with 1 dB resolution via a 6-bit word. Its on a dB-to-dB basis, the low noise characteristics of the RxPGA purpose is to extend the dynamic range of the Rx path such that provide some design margin such that the external line noise the input of the ADC is presented with a signal that scales remains the dominant source. within its fixed 2 V input span. There are multiple ways of setting the RxPGA gain as discussed in the RXPGA Control 8.0000 section, as well as an alternative 3-bit gain mapping having a 4.0000 range of −12 dB to +36 dB with a +8 dB resolution. 2.0000 The RxPGA is comprised of two sections: a continuous time 1.0000 PGA (CPGA) for course gain and a switched capacitor PGA 0.5000 (SPGA) for fine gain resolution. The CPGA consists of two 0.2500 cascaded gain stages providing a gain range of −12 dB to +42 dB 0.1250 with a 6 dB resolution. The first stage features a low noise preamplifier (<3.0 nV/√Hz), thereby eliminating the need for 0.0625 an external preamplifier. The SPGA provides a gain range of 0.0312 0 dB to 6 dB with a 1 dB resolution. A look-up table (LUT) is 0.0156 used to select the appropriate gain setting for each stage. 0.0100 –12 –6 0 6 12 18 24 30 36 42 48 GAIN (dB) The nominal differential input impedance of the RxPGA input Figure 25. Maximum Peak-to-Peak Input vs. RxPGA Gain Setting that appearing at the device RX+ and RX− input pins is 400 Ω||4 pF Does Not Result in ADC Clipping (±20%) and remains relatively independent of gain setting. Rev. 0 | Page 24 of 36 06733-024 FULL-SCALE PEAK-TO-PEAK INPUT SPAN (V) 06733-025 AD9868 0.25 1.30 LOW-PASS FILTER 0 1.25 NORMALIZED GAIN RESPONSE –0.25 1.20 The low-pass filter (LPF) provides a third-order response with a –0.50 1.15 cutoff frequency that is typically programmable over a 15 MHz –0.75 1.10 to 35 MHz span. The first real pole is implemented within the –1.00 1.05 first CPGA gain stage (see Figure 24), and the complex pole pair –1.25 1.00 is implemented in the second CPGA gain stage. Capacitor arrays –1.50 0.95 are used to vary the different RC time constants within these –1.75 0.90 two stages in a manner that changes the cutoff frequency while –2.00 0.85 preserving the normalized frequency response. Because absolute –2.25 0.80 NORMALIZED GROUP DELAY resistor and capacitor values are process-dependent, a calibration –2.50 0.75 routine lasting less than 100 μs automatically occurs each time –2.75 0.70 –3.00 0.65 the target cutoff frequency register (Register 0x08) is updated, 00 0.1 0.2 0.3 0.4.5 0.6 0.7 0.8 0.91.0 ensuring a repeatable cutoff frequency from device to device. NORMALIZED FREQUENCY Figure 27. LPF Normalized Pass-Band Gain and Group Delay Responses Although the default setting specifies that the LPF be active, it of 55 MHz. can also be bypassed providing a nominal f−3 dB The f−3 dB is programmable by writing an 8-bit word, referred to Table 19 shows the SPI registers pertaining to the LPF. as the target, to Register 0x08. The cutoff frequency is a function of the ADC sample rate, fADC, and to a lesser extent, the RxPGA Table 19. SPI Registers for Rx Low-Pass Filter gain setting (in dB). Figure 28 shows how f varies as a −3 dB Address (Hex) Bit Description function of the RxPGA gain setting. 0x07 0 Enable Rx LPF. 3 –6dB GAIN 0x08 7:0 Target value. 0dB GAIN 0 +6dB GAIN The normalized wideband gain response is shown in Figure 26. +18dB GAIN +30dB GAIN The normalized pass-band gain and group delay responses are –3 +42dB GAIN shown in Figure 27. The −3 dB cutoff frequency, f , results in −3 dB −3 dB attenuation. In addition, the actual group delay time –6 (GDT) response can be calculated given a programmed cutoff –9 frequency using the following equation: Actual GDT = Normalized GDT/(2.45 × f−3dB) (4) –12 5 –15 0 –18 01 50 15 20 25 30 35 40 4550 –5 INPUT FREQUENCY (MHz) –10 Figure 28. Effects of RxPGA Gain on LPF Frequency Response (f = 32 MHz @ 0 dB and f = 80 MSPS) −3 dB ADC –15 1 The following formula can be used to estimate f−3 dB for a –20 RxPGA gain setting of 0 dB: –25 f = (128/target) × (f /80) ×(f /30 + 23.83) f (5) −3dB_0dB ADC ADC –30 Figure 29 compares the measured and calculated f using this −3 dB –35 formula. 0 0.5 1.0 1.5 2.0 2.5 3.0 FREQUENCY Figure 26. LPF Normalized Wideband Gain Response 1 Empirically derived for an f range of 15 MHz to 35 MHz and an f of −3 dB ADC 40 MSPS to 80 MSPS with an RxPGA = 0 dB. Rev. 0 | Page 25 of 36 GAIN (dB) 06733-026 GAIN (dB) FUNDAMENTAL (dB) 06733-028 NORMALIZED GROUP DELAY TIME RESPONSE (GDT) 06733-027 AD9868 35 ANALOG-TO-DIGITAL CONVERTER (ADC) 33 The AD9868 features a 10-bit analog-to-digital converter 31 (ADC) capable of up to 80 MSPS. As shown in Figure 24, the 29 ADC is driven by the SPGA stage, which performs both the 27 sample-and-hold and the fine gain adjust functions. A buffer 80MSPS MEASURED 25 amplifier (not shown) isolates the last CPGA gain stage from the dynamic load presented by the SPGA stage. The full-scale 80MSPS CALCULATED 23 input span of the ADC is 2 V p-p, and depending on the PGA 21 gain setting, the full-scale input span into the SPGA is adjustable 19 from 1 V to 2 V in 1 dB increments. 50MSPS MEASURED 17 50MSPS CALCULATED A pipelined, multistage ADC architecture is used to achieve high 15 48 64 80 96 112 128 144 160 176 192 208 224 sample rates while consuming low power. The ADC distributes the TARGET-DECIMAL EQUIVALENT conversion over several smaller ADC subblocks, refining the Figure 29. Measured and Calculated f vs. Target Value for −3 dB conversion with progressively higher accuracy as it passes the f = 50 MSPS and 80 MSPS ADC results from stage to stage on each clock edge. The ADC typically The following scaling factor can be applied to the previous performs best when driven internally by a 50% duty cycle clock. formula to compensate for the RxPGA gain setting on f−3 dB: The ADC power consumption can be reduced by 25 mA with Scale Factor = 1 − (RxPGA in dB)/382 (6) minimal effect on its performance by setting Bit 4 of Register 0x07. Alternative power bias settings are also available via Register 0x13, This scaling factor reduces the calculated f as the RxPGA −3 dB as discussed in the Power Control and Dissipation section. increases. Applications that need to maintain a minimum cutoff Lastly, the ADC can be completely powered down for half-duplex frequency, f−3 dB_MIN, for all RxPGA gain settings should first operation, further reducing the peak power consumption of the determine the scaling factor for the highest RxPGA gain setting AD9868. to be used. Next, the f−3 dB_MIN should be divided by this scale factor to normalize to the 0 dB RxPGA gain setting, f−3 dB_0 dB. The ADC has an internal voltage reference and reference amplifier Equation 5 can then be used to calculate the target value. as shown in Figure 31. The internal band gap reference generates a stable 1 V reference level that is converted to a differential 1 V The LPF frequency response shows a slight sensitivity to reference centered about midsupply (AVDD/2). The outputs of temperature, as shown in Figure 30. Applications sensitive to the differential reference amplifier are available at the REFT and temperature drift can recalibrate the LPF by rewriting the target REFB pins and must be properly decoupled for optimum perform- value to Register 0x08. ance. The REFT and REFB pins are conveniently situated at the 35 corners of the LFCSP package such that C1 (0603 type) can be placed directly across its pins. C3 and C4 can be placed underneath C1, and C2 (10 μF tantalum) can be placed furthest 30 from the package. f ACTUAL 80MHz AND –40°C OUT REFT 25 f ACTUAL 80MHz AND +25°C OUT C3 TO 0.1µF C2 C1 f ACTUAL 80MHz AND +85°C OUT ADCs 10µF 0.1µF 20 C4 REFB 0.1µF 1.0V 15 96 112 128 144 160 176 192 208 240 224 TARGET-DECIMAL EQUIVALENT Figure 30. f−3 dB Temperature Drift for fADC = 80 MSPS and RxPGA = 0 dB TOP VIEW C3 C1 C4 C2 Figure 31. ADC Reference and Decoupling Rev. 0 | Page 26 of 36 FREQUENCY (MHz) FREQUENCY (MHz) 06733-030 06733-029 06733-031 AD9868 Table 20 shows the SPI registers pertaining to the ADC. AGC TIMING CONSIDERATIONS When implementing a digital AGC timing loop, it is important Table 20. SPI Registers for Rx ADC to consider the Rx path latency and settling time of the Rx path Address (Hex) Bit Description in response to a change in gain setting. While the RxPGA 0x04 4 ADC clock from PLL. settling time may also show a slight dependency on the LPF 0x07 4 ADC low power mode. cutoff frequency, the ADC pipeline delay, along with the ADIO 0x13 2:0 ADC power bias adjust. bus interface, presents a more significant delay. The amount of delay or latency is dependent on whether a half-duplex or full- duplex is selected. An impulse response at the RxPGA input can be observed after 10.0 ADC clock cycles (1/fADC) in the case of a half-duplex interface, and 10.5 ADC clock cycles in the case of a full-duplex interface. This latency, along with the RxPGA settling time, should be considered to ensure stability of the AGC loop. Rev. 0 | Page 27 of 36 AD9868 CLOCK SYNTHESIZER frequency between 100 MHz and 200 MHz. The VCO output The AD9868 generates all its internal sampling clocks, as well as drives the TxDAC directly such that its update rate, fDAC, is two user-programmable clock outputs appearing at CLKOUT1 related to fOSCIN by the following equation: and CLKOUT2, from a single reference source (see Figure 32). M The reference source can either be a fundamental frequency or fDAC = 2 × fOSCIN (7) an overtone quartz crystal connected between OSCIN and where M = 0, 1, 2, or 3. XTAL, with the parallel resonant load components specified by the crystal manufacturer. It can also be a TTL-level clock M is the PLL multiplication factor set in Register 0x04. The applied to OSCIN with XTAL left unconnected. value of M is determined by the Tx path’s word rate, f , and DATA digital interpolation factor, F, as shown in the following equation: TO ADC XTAL N ÷2 M = log2(F × fDATA/fOSCIN) (8) XTAL M OSCIN 2 CLK TO TxDAC MULTIPLIER C1 C2 Note that if the reference frequency appearing at OSCIN is chosen to be equal to the Tx path and Rx path word rates, M is equal to CLKOUT2 L ÷2 log (F). Also note that the RXCLK frequency for full-duplex 2 CLKOUT1 M mode (MODE = 1) is a function of the 2 CLK multiplier R ÷2 ÷F/2 RXCLK (FULL-DUPLEX ONLY) setting, as well as the interpolation factor, F. Full-duplex mode requires that RXCLK be equal to 2 × fDATA because data is Figure 32. Clock Oscillator and Synthesizer transferred in nibbles. Special consideration should be given to the design of crystal The clock source for the ADC can be selected in Register 0x04 oscillators using the AD9868 internal CMOS inverter. This is as a buffered version of the reference frequency appearing at especially true when designing third overtone oscillators where OSCIN (default setting) or a divided version of the VCO crystal power dissipation and negative resistance upon start-up output, f . The first option is the default setting and most DAC are a few of the issues to consider. For this reason, a 40 MHz or desirable if f is equal to f . This option typically results in OSCIN ADC lower fundamental crystal is preferred with the AD9868. the best jitter/phase noise performance for the ADC sampling The CMOS inverter device characteristics are listed in Table 21. It clock. The second option is suitable in cases where fOSCIN is a is recommended to consult with the selected crystal manufacturer factor of 2 or 4 less than the fADC. In this case, the divider ratio, to ensure that a robust design can be realized with the selected N, is chosen such that the divided down VCO output is equal to crystal and AD9868 CMOS inverter. the ADC sample rate, as shown in the following equation: N f = f /2 (9) ADC DAC Table 21. CMOS Inverter Device Characteristics Nominal where N = 0, 1, or 2. Value Parameter Tolerance % Description The CLK synthesizer also has two clock outputs appearing at RF 1.2 MΩ ±25 Feedback resistor. CLKOUT1 and CLKOUT2. They are programmable via gm 17 mA/V ±20 At midsupply. Register 0x06. Both outputs can be inverted or disabled. The ZOUT 1.6 kΩ ±50 At midsupply. voltage levels appearing at these outputs are relative to DRVDD C 2.5 pF ±25 Parasitic capacitance. IN and remain active during a hardware or software reset. Table 22 C 2.0 pF ±25 Parasitic capacitance. OUT shows the SPI registers pertaining to the CLK synthesizer. The data rate, fDATA, for the Tx and Rx data paths must always be equal. Therefore, the ADC sample rate, fADC, is always equal to Table 22. SPI Registers for CLK Synthesizer f , while the TxDAC update rate is a factor of 1, 2, or 4 of DATA Address (Hex) Bit Description f , depending on the selected interpolation factor. The data DATA 0x04 4 ADC CLK from PLL. rate refers to the word rate and should not be confused with the 3:2 PLL divide factor (N). nibble rate in full-duplex interface. 1:0 PLL multiplication factor (M). M CLK multiplier contains a PLL (with integrated loop 0x06 7:6 CLKOUT2 divide number. The 2 5 CLKOUT2 invert. filter) and a VCO capable of generating an output frequency 4 CLKOUT2 disable. that is a multiple of 1, 2, 4, or 8 of its input reference frequency, fOSCIN, appearing at OSCIN. The input frequency range of fOSCIN 3:2 CLKOUT1 divide number. is between 20 MHz and 80 MHz, and the VCO can operate over 1 CLKOUT1 invert. an 80 MHz to 200 MHz span. For the best phase noise/jitter 0 CLKOUT1 disable. characteristics, it is advisable to operate the VCO with a Rev. 0 | Page 28 of 36 06733-032 AD9868 CLKOUT1 is a divided version of the VCO output and can be CLKOUT2 is a divided version of the reference frequency, f , OSCIN R L set to be a submultiple integer of f (f /2 , where R = 0, 1, 2, and can be set to be a submultiple integer of f (f /2 , DAC DAC OSCIN OSCIN or 3). Because this clock is derived from the same set of dividers where L = 0, 1, or 2). With L set to 0, the output of CLKOUT2 is used within the PLL core, it is phase-locked to the dividers such a delayed version of the signal appearing at OSCIN, exhibiting that its phase relationship relative to the signal appearing at the same duty cycle characteristics. With L set to 1 or 2, the output OSCIN (or RXCLK) can be determined upon power-up. In of CLKOUT2 is a divided version of the OSCIN signal, exhibiting addition, this clock has a near 50% duty cycle because it is a near 50% duty cycle, but without having a deterministic phase derived from the VCO. As a result, CLKOUT1 should be relationship relative to CLKOUT1 (or RXCLK). selected before CLKOUT2 as the primary source for system clock distribution. Rev. 0 | Page 29 of 36 AD9868 POWER CONTROL AND DISSIPATION POWER-DOWN HALF-DUPLEX POWER SAVINGS The AD9868 provides the ability to control the power-on state Significant power savings can be realized in applications having of various functional blocks. The state of the PWRDWN pin, a half-duplex protocol, allowing only the Rx path or Tx path to along with the contents of Register 0x01 and Register 0x02, be operational at one time. The power-savings method depends allow two user-defined power settings that are pin-selectable. on whether the AD9868 is configured for a full-duplex or half- 1 The default settings are such that Register 0x01 has all blocks duplex interface. Functional blocks having fast power-on/power-off powered on (all bits 0), while Register 0x02 has all blocks times for the Tx path and Rx path are controlled by the powered down (excluding the PLL) such that the clock signal following bits: TxDAC/IAMP, Tx Digital, ADC, and RxPGA remains available at CLKOUT1 and CLKOUT2. When the (see Table 23). PWRDWN pin is low, the functional blocks corresponding to In the case of a full-duplex digital interface (MODE = 1), users the bits in Register 0x01 are powered down. When the PWRDWN can set Register 0x01 to Register 0x60 and Register 0x02 to is high, the functional blocks corresponding to the bits in Register 0x05 (or vice versa) such that the Tx path and Rx path are Register 0x02 are powered down. PWRDWN immediately affects never powered on simultaneously. The PWRDWN pin can then be the designated functional blocks with minimum digital delay. used to control which path is powered on, depending on the burst type. During a Tx burst, the Rx path PGA and ADC blocks can Table 23. SPI Registers Associated with Power-Down and typically be powered down within 100 ns, while the Tx path Half-Duplex Power Savings DAC, IAMP, and digital filter blocks are powered up within Address (Hex) Bit Description Comments 0.5 μs. For an Rx burst, the Tx circuitry can be powered down 0x01 7 CLK Synthesizer PWRDWN = 0. within 100 ns, while the Rx circuitry is powered up within 2 μs. Default setting is 6 TxDAC/IAMP all functional blocks 5 Tx Digital Setting the TXQUIET pin low allows it to be used with the full- powered on. 4 REF duplex interface to quickly power down the IAMP and disable 3 ADC CML the interpolation filter. This is meant to maintain backward 2 ADC compatibility with the AD9875/AD9876 MxFEs, except that the 1 PGA Bias TxDAC remains powered if its IOUTP outputs are used. In 0 RxPGA most applications, the interpolation filter needs to be flushed 0x02 7 CLK Synthesizer PWRDWN = 1. with 0s before or after being powered down. This ensures that Default setting is 6 TxDAC/IAMP upon power-up, the TxDAC (and IAMP) have a negligible all functional 5 Tx Digital differential dc offset, thus preventing spectral splatter due to an blocks powered 4 REF impulse transient. off excluding PLL. 3 ADC CML Applications using a half-duplex interface (MODE = 0) can benefit 2 ADC from an additional power-savings feature available in Register 0x03. 1 PGA Bias This register is effective only for a half-duplex interface. In addition 0 RxPGA to providing power savings for half-duplex applications, this 0x03 7:3 Tx OFF Delay Half-duplex power feature allows the AD9868 to be used in applications that need savings. 2 Rx PWRDWN via TXEN only its Rx (or Tx) path functionality through pin strapping, 1 Enable Tx PWRDWN making a serial port interface (SPI) optional. This feature also 0 Enable Rx PWRDWN allows the PWRDWN pin to retain its default function as a master power control, as defined in Table 10. The default settings for Register 0x03 provide fast power control of the functional blocks in the Tx signal path and Rx signal path (outlined previously) using the TXEN pin. The TxDAC remains powered on in this mode, while the IAMP is powered down. Significant current savings are typically realized when the IAMP is powered down. 1 With MODE = 1 and CONFIG =1, Register 0x02 default settings are with all blocks powered off, with RXCLK providing a buffered version of the signal appearing at OSCIN. This setting results in the lowest power consumption upon power- up, while still allowing AD9868 to generate the system clock via a crystal. Rev. 0 | Page 30 of 36 AD9868 55 For a Tx burst, the falling edge of TXEN is used to generate an 50 internal delayed signal for powering down the Tx circuitry. Upon receipt of this signal, power-down of the Tx circuitry occurs 45 within 100 ns. The user-programmable delay for the Tx path 40 power-down is meant to match the pipeline delay of the last Tx 35 burst sample such that power-down of the TxDAC and IAMP does not impact its transmission. A 5-bit field in Register 0x03 sets 30 the delay from 0 to 31 TXCLK clock cycles, with the default 25 being 31 (0.62 μs with f = 50 MSPS). The digital interpolation TXCLK 20 filter is automatically flushed with midscale samples prior to power-down if the clock signal into the TXCLK pin is present 15 for 33 additional clock cycles after TXEN returns low. For an Rx 10 01 23 456 78 9 10 11 12 13 burst, the rising edge of TXEN is used to generate an internal I (mA) STANDING signal (with no delay) that powers up the Tx circuitry within 0.5 μs. Figure 33. Reduction in TxDAC Supply Current vs. Standing Current The Rx path power-on/power-off can be controlled by either 65 TXEN or RXEN by setting Bit 2 of Register 0x03. In the default 60 setting, the falling edge of TXEN powers up the Rx circuitry 4× INTERPOLATION 55 within 2 μs, while the rising edge of TXEN powers down the Rx circuitry within 0.5 μs. If RXEN is selected as the control signal, 50 its rising edge powers up the Rx circuitry, and the falling edge 45 powers it down. To disable the fast power-down of the Tx 40 2× INTERPOLATION circuitry and/or Rx circuitry, set Bit 1 and/or Bit 0 to 0. 35 POWER REDUCTION OPTIONS 30 1× (HALF-DUPLEX ONLY) The power consumption of the AD9868 can be significantly 25 reduced from its default setting by optimizing the power 20 consumption vs. performance of the various functional blocks 15 20 30 40 50 60 70 80 in the Tx signal path and Rx signal path. On the Tx path, INPUT DATA RATE (MSPS) minimum power consumption is realized when the TxDAC Figure 34. Digital Supply Current Consumption vs. Input Data Rate output is used directly and its standing current is reduced to as (DVDD = DRVDD = 3.3 V and fOUT = fDATA/10) low as 1 mA. Although a slight degradation in THD performance results at reduced standing currents, it often remains adequate Power consumption on the Rx path can be achieved by reducing for most applications because the op amp driver typically limits the bias levels of the various amplifiers contained within the the overall linearity performance of the Tx path. The load RxPGA and ADC. As previously noted, the RxPGA consists of resistors used at the TxDAC outputs (IOUTP+ and IOUTP−) two CPGA amplifiers and one SPGA amplifier. The bias levels can be increased to generate an adequate differential voltage of each of these amplifiers, along with the ADC, can be controlled that can be further amplified via a power efficient op amp- via Register 0x13 as shown in Table 24. The default setting for based driver solution. Figure 33 shows how the supply current Register 0x13 is 0x00. for the TxDAC is reduced from 55 mA to 14 mA as the standing current is reduced from 12.5 mA to 1.25 mA. Further Tx power Table 24. SPI Register for RxPGA and ADC Biasing savings can be achieved by bypassing or reducing the interpola- Address (Hex) Bit Description tion factor of the digital filter as shown in Figure 34. 0x07 4 ADC low power. 0x13 7:5 CPGA bias adjust. 4:3 SPGA bias adjust. 2:0 ADC power bias adjust. Rev. 0 | Page 31 of 36 I (mA) IAVDD (mA) DVDD TxDAC 06733-034 06733-033 AD9868 Because the CPGA processes signals in the continuous time The SPGA is implemented as a switched capacitor amplifier, domain, its performance vs. bias setting remains mostly therefore, its performance vs. bias level is mostly dependent on independent of the sample rate. Table 25 shows how the typical the sample rate. Figure 36 shows how the typical current consump- current consumption seen at AVDD varies as a function of tion seen at AVDD varies as a function of Register 0x13, Bits [4:3] Register 0x13, Bits [7:5], while the remaining bits are maintained at and sample rate, while the remaining bits are maintained at the their default settings of 0. Only four of the possible settings result default setting of 0. Figure 37 shows how the SNR and THD in any reduction in current consumption relative to the default performance is affected for a 10 MHz sine wave input as the setting. Reducing the bias level typically results in degradation ADC sample rate is swept from 20 MHz to 80 MHz. The SNR in the THD vs. frequency performance as shown in Figure 35. and THD performance remains relatively stable, suggesting that This is due to a reduction of the amplifier’s unity gain bandwidth, the SPGA bias can often be reduced from its default setting while the SNR performance remains relatively unaffected. without impacting the device’s overall performance. 210 Table 25. Analog Supply Current vs. CPGA Bias Settings at 205 fADC = 65 MSPS Bit 7 Bit 6 Bit 5 ∆mA 200 01 0 0 0 0 195 0 0 1 −27 00 0 1 0 −42 190 0 1 1 −51 185 1 0 0 −55 10 180 1 0 1 +27 11 1 1 0 +69 175 1 1 1 +27 170 20 30 40 50 60 70 80 ADC SAMPLE RATE (MSPS) 65.0 –20 SNR_RxPGA = 0dB Figure 36. AVDD Current vs. SPGA Bias Setting and Sample Rate 62.5 –25 61 –54 60.0 –30 60 –56 57.5 –35 SNR_RxPGA = 36dB 59 –58 55.0 –40 SNR-00 58 –60 52.5 –45 SNR-01 SNR-10 57 –62 50.0 –50 SNR-11 THD_RxPGA = 0dB 56 –64 47.5 –55 55 –66 45.0 –60 54 –68 THD-00 42.5 –65 THD-01 THD_RxPGA = 36dB 53 –70 THD-10 40.0 –70 000 001 010 011 100 THD-11 52 –72 CPGA BIAS SETTING-BITS (7:5) 51 –74 Figure 35. THD vs. fIN Performance and CPGA Bias Settings (000, 001, 010, 100 20 30 40 50 60 70 80 with RxPGA = 0 and +36 dB, AIN = −1 dBFS, LPF set to 26 MHz, fADC = 50 MSPS) SAMPLE RATE (MSPS) Figure 37. SNR and THD Performance vs. fADC and SPGA Bias Setting with RxPGA = 0 dB, fIN = 10 MHz, LPF set to 26 MHz, AIN = −1 dBFS Rev. 0 | Page 32 of 36 SNR (dBFS) 06733-035 THD (dBc) SNR (dBc) I (mA) AVDD 06733-036 06733-037 THD (dBc) AD9868 POWER DISSIPATION The ADC is based on a pipeline architecture with each stage consisting of a switched capacitor amplifier. Therefore, its The power dissipation of the AD9868 can become quite high performance vs. bias level is mostly dependent on the sample in full-duplex applications in which the Tx path and Rx path rate. Figure 38 shows how the typical current consumption seen are simultaneously operating with nominal power bias settings. at AVDD varies as a function of Register 0x13, Bits [2:0] and In fact, some applications that use the IAMP may need to sample rate, while the remaining bits are maintained at the either reduce its peak power capabilities or reduce the power default setting of 0. Setting Bit 4 or Register 0x07 corresponds consumption of the Rx path so that the device’s maximum to the 011 setting, and the settings of 101 and 111 result in allowable power consumption, P , is not exceeded. MAX higher current consumption. Figure 39 shows how the SNR and PMAX is specified at 1.66 W to ensure that the die temperature THD performance are affected for a 10 MHz sine wave input does not exceed 125°C at an ambient temperature of 85°C. This for the lower power settings as the ADC sample rate is swept specification is based on the 64-lead LFSCP having a thermal from 20 MHz to 80 MHz. resistance, θ , of 24°C/W with its heat slug soldered. (The θ is JA JA 220 30.8°C/W if the heat slug remains unsoldered.) If a particular 101 OR 111 210 application’s maximum ambient temperature, T , falls below A 200 85°C, the maximum allowable power dissipation can be 000 determined by the following equation: 190 001 180 PMAX = 1.66 + (85 − TA)/24 (10) 010 170 Assuming the IAMP common-mode bias voltage is operating 160 off the same analog supply as the AD9868, the following equa- 011 101 100 150 tion can be used to calculate the maximum total current consumption, I , of the IC: 140 MAX 130 I = (P − P)/3.47 (11) MAX MAX IAMP 120 20 30 40 50 60 70 80 With an ambient temperature of up to 85°C, IMAX is 478 mA. SAMPLE RATE (MSPS) Figure 38. AVDD Current vs. ADC Bias Setting and Sample Rate If the IAMP is operating off a different supply or in the voltage mode configuration, first calculate the power dissipated in the 61 –54 IAMP, PIAMP, using Equation 3, and then recalculate IMAX using 60 –56 Equation 11. 59 –58 Figure 33, Figure 34, Figure 36, and Figure 38 can be used to SNR-00 58 –60 SNR-01 calculate the current consumption of the Rx and Tx paths for a SNR-10 57 –62 given setting. SNR-11 56 –64 MODE SELECT UPON POWER-UP AND RESET 55 –66 The AD9868 power-up state is determined by the logic levels 54 –68 THD-00 THD-01 appearing at the MODE and CONFIG pins. The MODE pin is 53 –70 THD-10 THD-11 used to select a half- or full-duplex interface by pin strapping it 52 –72 low or high, respectively. The CONFIG pin is used in conjunc- 51 –74 20 30 40 50 60 70 80 tion with the MODE pin to determine the default settings for SAMPLE RATE (MSPS) the SPI registers as outlined in Table 10. Figure 39. SNR and THD Performance vs. fADC and ADC Bias Setting with RxPGA = 0 dB, fIN = 10 MHz, AIN = −1 dBFS The intent of these particular default settings is to allow some applications to avoid using the SPI (disabled by pin strapping A sine wave input is a standard and convenient method of SEN high), thereby reducing implementation costs. For analyzing the performance of a system. However, the amount of example, setting MODE low and CONFIG high configures the power reduction that is possible is application dependent, based AD9868 to be backward compatible with the AD9975, while on the nature of the input waveform (such as frequency content, setting MODE high and CONFIG low makes it backward and peak-to-rms ratio), the minimum ADC sample, and the compatible with the AD9875. Other applications must use the minimum acceptable level of performance. Thus, it is advisable SPI to configure the device. that power-sensitive applications optimize the power bias setting of the Rx path using an input waveform that is representative of the application. Rev. 0 | Page 33 of 36 SNR (dBc) I (mA) AVDD 06733-038 06733-039 THD (dBc) AD9868 RESET As a result, the analog loopback feature can be used for a half- A hardware reset ( pin) or software reset (Bit 5 of duplex or full-duplex interface to allow testing of the functionality Register 0x00) can be used to place the AD9868 into a known of the entire IC (excluding the digital data interface). state of operation as determined by the state of the MODE and CONFIG pins. A dc offset calibration and filter tuning routine For example, the user can configure the AD9868 with similar is also initiated upon a hardware reset, but not with a software settings as the target system, inject an input signal (sinusoidal reset. Neither reset method flushes the digital interpolation filters waveform) into the Rx input, and monitor the quality of the in the Tx path. Refer to the Half-Duplex Mode and Full-Duplex reconstructed output from the TxDAC or IAMP to ensure a Mode sections for information on flushing the digital filters. minimum level of performance. In this test, the user can exercise the RxPGA as well as validate the attenuation characteristics of RESET A hardware reset can be triggered by pulsing the pin low the RxLPF. Note that the RxPGA gain setting should be selected for a minimum of 50 ns. The SPI registers are instantly reset to such that the input does not result in clipping of the ADC. RESET their default settings upon going low, whereas the dc offset calibration and filter-tuning routine is initiated upon RESET Digital loopback can be used to test the full-duplex digital returning high. To ensure sufficient power-on time of the various interface of the AD9868. In this test, data appearing on the functional blocks, RESET returning high should occur no less Tx[5:0] port is routed back to the Rx[5:0] port, thereby than 10 ms upon power-up. If a digital reset signal from a confirming proper bus operation. The Rx port can also be microprocessor reset circuit (such as ADM1818) is not available, three-stated for half-duplex and full-duplex interfaces. a simple R-C network referenced to DVDD can be used to hold RESET low for approximately 10 ms upon power-up. Table 26. SPI Registers for Test Modes Address (Hex) Bit Description ANALOG AND DIGITAL LOOPBACK TEST MODES 0x0D 7 Analog loopback. The AD9868 features analog and digital loopback capabilities 6 Digital loopback. that can assist in system debug and final test. Analog loopback 5 Rx port three-state. routes the digital output of the ADC back into the Tx data path prior to the interpolation filters such that the Rx input signal can be monitored at the output of the TxDAC or IAMP. Rev. 0 | Page 34 of 36 AD9868 OUTLINE DIMENSIONS 0.30 9.00 0.25 0.60 MAX BSC SQ 0.18 0.60 MAX PIN 1 INDICATOR 49 64 1 48 PIN 1 INDICATOR 7.25 8.75 TOP EXPOSED PAD 7.10 SQ BSC SQ VIEW (BOTTOM VIEW) 6.95 0.50 0.40 33 17 16 32 0.30 0.25 MIN 7.50 REF 0.80 MAX 1.00 12° MAX 0.65 TYP 0.85 0.05 MAX 0.80 0.02 NOM SEATING 0.50 BSC 0.20 REF PLANE COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4 Figure 40. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 9 mm x 9 mm Body, Very Thin Quad (CP-64-3) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option 1 AD9868BCPZ −40°C to +85°C 64-Lead LFCSP_VQ CP-64-3 1 AD9868BCPZRL −40°C to +85°C 64-Lead LFCSP_VQ CP-64-3 1 Z = RoHS Compliant Part. Rev. 0 | Page 35 of 36 063006-B AD9868 NOTES ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06733-0-5/07(0) Rev. 0 | Page 36 of 36