ANALOG DEVICES AD9865

Broadband Modem Mixed-Signal Front End AD9865 FEATURES FUNCTIONAL BLOCK DIAGRAM TM Low cost 3.3 V CMOS MxFE for broadband modems 10-bit D/A converter 2×/4× interpolation filter 200 MSPS DAC update rate IOUT_G+ AD9865 Integrated 23 dBm line driver with 19.5 dB gain control 2-4X IOUT_N+ PWR DWN IAMP TxDAC IOUT_N– MODE 10-bit, 80 MSPS A/D converter IOUT_G– TXEN/SYNC 0 TO –12dB 0 TO –7.5dB −12 dB to +48 dB low noise RxPGA (< 3.0 nV/rtHz) TXCLK 10 CLKOUT_1 CLK Third order, programmable low-pass filter ADIO[9:4]/ SYN. CLKOUT_2 Tx[5:0] Flexible digital data path interface M 2 CLK OSCIN MULTIPLIER XTAL Half- and full-duplex operation ADIO[3:0]/ Rx[5:0] Backward-compatible with AD9975 and AD9875 10 Various power-down/reduction modes RX+ RXE/SYNC ADC 2-POLE 1-POLE LPF LPF RXCLK 80MSPS RX– Internal clock multiplier (PLL) 6 AGC[5:0] 0 TO 6dB – 6 TO 18dB –6 TO 24dB 2 auxiliary programmable clock outputs ∆ = 1dB ∆ = 6dB ∆ = 6dB 4 REGISTER SPI CONTROL Available in 64-lead chip scale package or bare die APPLICATIONS Figure 1. Powerline networking VDSL and HPNA GENERAL DESCRIPTION or to an internal low distortion current amplifier. The current The AD9865 is a mixed-signal front end (MxFE) IC for amplifier (IAMP) can be configured as a current- or voltage- transceiver applications requiring Tx and Rx path functionality mode line driver (with two external npn transistors) capable of with data rates up to 80 MSPS. Its flexible digital interface, delivering in excess of 23 dBm peak signal power. Tx power can power saving modes, and high Tx-to-Rx isolation make it well be digitally controlled over a 19.5 dB range in 0.5 dB steps. suited for half- and full-duplex applications. The digital inter- face is extremely flexible allowing simple interfaces to digital The receive path consists of a programmable amplifier back ends that support half- or full-duplex data transfers, thus (RxPGA), a tunable low-pass filter (LPF), and a 10-bit ADC. often allowing the AD9865 to replace discrete ADC and DAC The low noise RxPGA has a programmable gain range of solutions. Power saving modes include the ability to reduce −12 dB to +48 dB in 1 dB steps. Its input referred noise is less power consumption of individual functional blocks, or to power than 3 nV/rtHz for gain settings beyond 36 dB. The receive path down unused blocks in half-duplex applications. A serial port LPF cutoff frequency can be set over a 15 MHz to 35 MHz interface (SPI®) allows software programming of the various range or simply bypassed. The 10-bit ADC achieves excellent functional blocks. An on-chip PLL clock multiplier and dynamic performance over a 5 MSPS to 80 MSPS span. Both synthesizer provide all the required internal clocks, as well as the RxPGA and the ADC offer scalable power consumption two external clocks from a single crystal or clock source. allowing power/performance optimization. The Tx signal path consists of a bypassable 2×/4× low-pass The AD9865 provides a highly integrated solution for many interpolation filter, a 10-bit TxDAC, and a line driver. The broadband modems. It is available in a space saving 64-pin chip transmit path signal bandwidth can be as high as 34 MHz at an scale package and is specified over the commercial (−40°C to input data rate of 80 MSPS. The TxDAC provides differential +85°C) temperature range. current outputs that can be steered directly to an external load Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 www.analog.com or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. IOUT_P+ IOUT_P– 04493-0-001 AD9865 TABLE OF CONTENTS Specifications..................................................................................... 3 TxDAC and IAMP Architecture .............................................. 28 Tx Path Specifications.................................................................. 3 Tx Programmable Gain Control .............................................. 30 Rx Path Specifications.................................................................. 4 TxDAC Output Operation........................................................ 30 Power Supply Specifications ....................................................... 5 IAMP Current-Mode Operation.............................................. 30 Digital Specifications ................................................................... 6 IAMP Voltage-Mode Operation .............................................. 31 Serial Port Timing Specifications............................................... 7 IAMP Current Consumption Considerations........................ 32 Half-Duplex Data Interface (ADIO Port) Timing Receive Path .................................................................................... 33 Specifications ................................................................................ 7 Rx Programmable Gain Amplifier........................................... 33 Full-Duplex Data Interface (Tx and Rx Port) Timing Low-Pass Filter ........................................................................... 34 Specifications ................................................................................ 8 Analog-to-Digital Converter (ADC)....................................... 35 Explanation of Test Levels........................................................... 8 AGC Timing Considerations.................................................... 36 Absolute Maximum Ratings............................................................ 9 Clock Synthesizer ........................................................................... 37 Thermal Characteristics .............................................................. 9 Power Control and Dissipation .................................................... 39 ESD Caution.................................................................................. 9 Power-Down ............................................................................... 39 Pin Configuration and Function Descriptions........................... 10 Half-Duplex Power Savings ...................................................... 39 Typical Performance Characteristics ........................................... 12 Power Reduction Options......................................................... 40 Rx Path Typical Performance Characteristics ........................ 12 Power Dissipation ...................................................................... 42 TxDAC Path Typical Performance Characteristics ............... 16 Mode Select upon Power-Up and Reset.................................. 42 IAMP Path Typical Performance Characteristics .................. 18 Analog and Digital Loop-Back Test Modes............................ 43 Serial Port ........................................................................................ 19 PCB Design Considerations.......................................................... 44 Register Map Description ......................................................... 21 Component Placement.............................................................. 44 Serial Port Interface (SPI) ......................................................... 21 Power Planes and Decoupling.................................................. 44 Digital Interface .............................................................................. 23 Ground Planes ............................................................................ 44 Half-Duplex Mode ..................................................................... 23 Signal Routing ............................................................................ 44 Full-Duplex Mode...................................................................... 24 Evaluation Board ............................................................................ 46 RxPGA Control .......................................................................... 25 Outline Dimensions ....................................................................... 47 TxPGA Control .......................................................................... 27 Ordering Guide .......................................................................... 47 Transmit Path.................................................................................. 28 Digital Interpolation Filters ...................................................... 28 REVISION HISTORY Change to TxDAC Output Operation section............................ 30 11/04—Data Sheet Changed from Rev. 0 to Rev. A Insert equation................................................................................ 37 Changes to Specifications Tables.................................................... 3 Change to Figure 84 caption ......................................................... 42 Changes to Serial Table.................................................................. 19 Changes to Full Duplex Mode section......................................... 24 11/03—Revision 0: Initial Version Change to TxDAC and IAMP Architecture section .................. 29 Rev. A | Page 2 of 48 AD9865 SPECIFICATIONS Tx PATH SPECIFICATIONS AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%; f = 50 MHz, f = 200 MHz, R = 2.0 kΩ, unless otherwise OSCIN DAC SET noted. Table 1. Parameter Temp Test Level Min Typ Max Unit TxDAC DC CHARACTERISTICS Resolution Full 10 Bits Update Rate Full II 200 MSPS Full-Scale Output Current (IOUTP_FS) Full IV 2 25 mA 1 Gain Error 25°C I ±2 % FS Offset Error 25°C V 2 µA Voltage Compliance Range Full −1 +1.5 V TxDAC GAIN CONTROL CHARACTERISTICS Minimum Gain 25°C V −7.5 dB Maximum Gain 25°C V 0 dB Gain Step Size 25°C V 0.5 dB Gain Step Accuracy 25°C IV Monotonic Gain Range Error 25°C V ±2 dB 2 TxDAC AC CHARACTERISTICS Fundamental 0.5 dBm Signal-to-Noise and Distortion (SINAD) Full IV 62.0 63.1 dBc Signal-to-Noise Ratio (SNR) Full IV 62.5 63.2 dBc Total Harmonic Distortion (THD) Full IV −77.7 −67.0 dBc Spurious-Free Dynamic Range (SFDR) Full IV 67.1 79.3 dBc IAMP DC CHARACTERISTICS IOUTN Full-Scale Current = IOUTN+ + IOUTN− Full IV 2 105 mA IOUTG Full-Scale Current = IOUTG+ + IOUTG− Full IV 2 150 mA AC Voltage Compliance Range Full IV 1 7 V 3 IAMPN AC CHARACTERISTICS Fundamental 25°C 13 dBm IOUTN SFDR (Third Harmonic) Full IV 43.3 45.2 dBc IAMP GAIN CONTROL CHARACTERISTICS Minimum Gain 25°C V −19.5 dB Maximum Gain 25°C V 0 dB Gain Step Size 25°C V 0.5 dB Gain Step Accuracy 25°C IV Monotonic dB IOUTN Gain Range Error 25°C V 0.5 dB REFERENCE 4 25°C I 1.23 V Internal Reference Voltage Reference Error Full V 0.7 3.4 % o Reference Drift Full V 30 ppm/ C Tx DIGITAL FILTER CHARACTERISTICS (2× Interpolation) Latency (Relative to 1/fDAC) Full V 43 Cycles −0.2 dB Bandwidth Full V 0.2187 fOUT/fDAC −3 dB Bandwidth Full V 0.2405 f /f OUT DAC Stop-Band Rejection (0.289 f to 0.711 f) Full V 50 dB DAC DAC Rev. A | Page 3 of 48 AD9865 Parameter Temp Test Level Min Typ Max Unit Tx DIGITAL FILTER CHARACTERISTICS (4× Interpolation) Latency (Relative to 1/ F) Full V 96 Cycles DAC −0.2 dB Bandwidth Full V 0.1095 f /f OUT DAC −3 dB Bandwidth Full V 0.1202 fOUT /fDAC Stop Band Rejection (0.289 fOSCIN to 0.711 fOSCIN) Full V 50 dB PLL CLK MULTIPLIER OSCIN Frequency Range Full IV 5 80 MHz Internal VCO Frequency Range Full IV 20 200 MHz Duty Cycle Full II 40 60 % OSCIN Impedance 25°C V 100//3 ΜΩ/pF 5 CLKOUT1 Jitter 25°C III 12 ps rms 6 CLKOUT2 Jitter 25°C III 6 ps rms 7 CLKOUT1 and CLKOUT2 Duty Cycle Full III 45 55 % 1 Gain error and gain temperature coefficients are based on the ADC only (with a fixed 1.23 V external reference and a 1 V p-p differential analog input). 2 TxDAC IOUTFS = 20 mA, differential output with 1:1 transformer with source and load termination of 50 Ω, F = 5 MHz, 4x interpolation. OUT 3 IOUN full-scale current = 80 mA, fOSCIN = 80 MHz, fDAC =160 MHz, 2x interpolation. 4 Use external amplifier to drive additional load. 5 Internal VCO operates at 200 MHz , set to divide-by-1. 6 Because CLKOUT2 is a divided down version of OSCIN, its jitter is typically equal to OSCIN. 7 CLKOUT2 is an inverted replica of OSCIN, if set to divide-by-1. Rx PATH SPECIFICATIONS AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%; half- or full-duplex operation with CONFIG = 0 default power bias settings, unless otherwise noted. Table 2. Parameter Temp Test Level Min Typ Max Unit Rx INPUT CHARACTERISTICS Input Voltage Span (RxPGA Gain = −10 dB) Full III 6.33 V p-p Input Voltage Span (RxPGA Gain = +48 dB) Full III 8 mV p-p Input Common-Mode Voltage 25°C III 1.3 V Differential Input Impedance 25°C III 400 Ω 4.0 pF Input Bandwidth (with RxLPF Disabled, RxPGA = 0 dB) 25°C III 53 MHz Input Voltage Noise Density (RxPGA Gain = 36 dB, f−3 dBF = 26 MHz) 25°C III 3.0 nV/rtHz Input Voltage Noise Density (RxPGA Gain = 48 dB, f = 26 MHz) 25°C III 2.4 nV/rtHz −3 dBF RxPGA CHARACTERISTICS Minimum Gain 25°C III −12 dB Maximum Gain 25°C III 48 dB Gain Step Size 25°C III 1 dB Gain Step Accuracy 25°C III Monotonic dB Gain Range Error 25°C III 0.5 dB RxLPF CHARACTERISTICS Cutoff Frequency (f ) Range Full III 15 35 MHz −3 dBF Attenuation at 55.2 MHz with f = 21 MHz 25°C III 20 dB −3 dBF Pass-Band Ripple 25°C III ±1 dB Settling Time to 5 dB RxPGA Gain Step @ fADC = 50 MSPS 25°C III 20 ns Settling Time to 60 dB RxPGA Gain Step @ fADC = 50 MSPS 25°C III 100 ns ADC DC CHARACTERISTICS Resolution NA NA 10 Bits Conversion Rate Full II 5 80 MSPS Rev. A | Page 4 of 48 AD9865 Parameter Temp Test Level Min Typ Max Unit 1 Rx PATH LATENCY Full-Duplex Interface Full V 10.5 Cycles Half-Duplex Interface Full V 10.0 Cycles 2 Rx PATH COMPOSITE AC PERFORMANCE @ f = 50 MSPS ADC RxPGA Gain = 48 dB (Full-Scale = 8.0 mV p-p) Signal-to-Noise and Distortion (SNR) 25°C III 43.7 dBc Total Harmonic Distortion (THD) 25°C III −71 dBc RxPGA Gain = 24 dB (Full-Scale =126 mV p-p) Signal-to-Noise (SNR) 25°C III 59 dBc Total Harmonic Distortion (THD) 25°C III −67.2 dBc RxPGA Gain = 0 dB (Full-Scale = 2.0 V p-p) Signal-to-Noise and Distortion (SINAD) Full IV 58 59 dBc Total Harmonic Distortion (THD) Full IV −66 −62.9 dBc 3 Rx PATH COMPOSITE AC PERFORMANCE @ fADC = 80 MSPS RxPGA Gain = 48 dB (Full-Scale = 8.0 mV p-p) Signal-to-Noise (SNR) 25°C III 41.8 dBc Total Harmonic Distortion (THD) 25°C III −67 dBc RxPGA Gain = 24 dB (Full-Scale = 126 mV p-p) Signal-to-Noise (SNR) 25°C III 58.6 dBc Total Harmonic Distortion (THD) 25°C III −62.9 dBc RxPGA Gain = 0 dB (Full-Scale = 2.0 V p-p) Signal-to-Noise (SNR) 25°C II 58.9 59.6 dBc Total Harmonic Distortion (THD) 25°C II −69.7 −59.8 dBc Rx-to-Tx PATH FULL-DUPLEX ISOLATION (1 V p-p, 10 MHz Sine Wave Tx Output) RxPGA Gain = 40 dB IOUTP± Pins to RX± Pins 25°C III 83 dBc IOUTG± Pins to RX± Pins 25°C III 37 dBc RxPGA Gain = 0 dB IOUTP± Pins to RX± Pins 25°C III 123 dBc IOUTG± Pins to RX± Pins 25°C III 77 dBc 1 Includes RxPGA, ADC pipeline, and ADIO bus delay relative to f . ADC 2 fIN = 5 MHz, AIN = −1.0 dBFS , LPF cutoff frequency set to 15.5 MHz with Reg. 0x08 = 0x80. 3 f = 5 MHz, AIN = −1.0 dBFS , LPF cutoff frequency set to 26 MHz with Reg. 0x08 = 0x80. IN POWER SUPPLY SPECIFICATIONS 1 AVDD = 3.3 V, DVDD = CLKVDD = DRVDD = 3.3 V; RSET = 2 kΩ, full-duplex operation with fDATA = 80 MSPS, unless otherwise noted. Table 3. Parameter Temp Test Level Min Typ Max Unit SUPPLY VOLTAGES AVDD Full V 3.135 3.3 3.465 V CLKVDD Full V 3.0 3.3 3.6 V DVDD Full V 3.0 3.3 3.6 V DRVDD Full V 3.0 3.3 3.6 V IS_TOTAL (Total Supply Current) Full II 406 475 mA POWER CONSUMPTION I + I (Analog Supply Current) IV 311 342 mA AVDD CLKVDD I + I (Digital Supply Current) Full IV 95 133 mA DVDD DRVDD Rev. A | Page 5 of 48 AD9865 Parameter Temp Test Level Min Typ Max Unit 2 POWER CONSUMPTION (Half-Duplex Operation with fDATA = 50 MSPS) Tx Mode IAVDD + ICLKVDD 25°C IV 112 130 mA I + I 25°C IV 46 49.5 mA DVDD DRVDD Rx Mode I + I 25°C IV 225 253 mA AVDD CLKVDD IDVDD + IDRVDD 25°C IV 36.5 39 mA 1 POWER CONSUMPTION OF FUNCTIONAL BLOCKS (I + I ) AVDD CLKVDD RxPGA and LPF 25°C III 87 mA ADC 25°C III 108 mA TxDAC 25°C III 38 mA IAMP (Programmable) 25°C III 10 120 mA Reference 25°C III 170 mA CLK PLL and Synthesizer 25°C III 107 mA MAXIMUM ALLOWABLE POWER DISSIPATION Full IV 1.66 W STANDBY POWER CONSUMPTION IS_TOTAL (Total Supply Current) Full 13 mA POWER DOWN DELAY (USING PWR_DWN PIN) RxPGA and LPF 25°C III 440 ns ADC 25°C III 12 ns TxDAC 25°C III 20 ns IAMP 25°C III 20 ns CLK PLL and synthesizer 25°C III 27 ns POWER UP DELAY (USING PWR_DWN PIN) RxPGA and LPF 25°C III 7.8 µs ADC 25°C III 88 ns TxDAC 25°C III 13 µs IAMP 25°C III 20 ns CLK PLL and Synthesizer 25°C III 20 µs 1 Default power-up settings for MODE = HIGH and CONFIG = LOW, IOUTP_FS = 20 mA, does not include IAMP’s current consumption, which is application dependent. 2 Default power-up settings for MODE = LOW and CONFIG = LOW. DIGITAL SPECIFICATIONS AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%; R = 2 kΩ, unless otherwise noted. SET Table 4. Parameter Temp Test Level Min Typ Max Unit CMOS LOGIC INPUTS High Level Input Voltage Full VI DRVDD – 0.7 V Low Level Input Voltage Full VI 0.4 V Input Leakage Current 12 µA Input Capacitance Full VI 3 pF CMOS LOGIC OUTPUTS (CLOAD = 5 pF) High Level Output Voltage (IOH = 1 mA) Full VI DRVDD – 0.7 V Low Level Output Voltage (IOH = 1 mA) Full VI 0.4 V Output Rise/Fall Time (High Strength Mode and C = 15 pF) Full VI 1.5/2.3 ns LOAD Output Rise/Fall Time (Low Strength Mode and C = 15 pF) Full VI 1.9/2.7 ns LOAD Output Rise/Fall Time (High Strength Mode and CLOAD = 5 pF) Full VI 0.7/0.7 ns Output Rise/Fall Time (Low Strength Mode and CLOAD = 5 pF) Full VI 1.0/1.0 ns RESET Minimum Low Pulse Width (Relative to fADC) 1 Clock cycles Rev. A | Page 6 of 48 AD9865 SERIAL PORT TIMING SPECIFICATIONS AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%, unless otherwise noted. Table 5. Parameter Temp Test Level Min Typ Max Unit WRITE OPERATION (See Figure 46) SCLK Clock Rate (fSCLK) Full IV 32 MHz SCLK Clock High (tHI) Full IV 14 ns SCLK Clock Low (tLOW) Full IV 14 ns SDIO to SCLK Setup Time (t ) Full IV 14 ns DS SCLK to SDIO Hold Time (t ) Full IV 0 ns DH SEN to SCLK Setup Time (tS) Full IV 14 ns SCLK to SEN Hold Time (tH) Full IV 0 ns READ OPERATION (See Figure 47 and Figure 48) SCLK Clock Rate (fSCLK) Full IV 32 MHz SCLK Clock High (tHI) Full IV 14 ns SCLK Clock Low (tLOW) Full IV 14 ns SDIO to SCLK Setup Time (t ) Full IV 14 ns DS SCLK to SDIO Hold Time (t ) Full IV 0 ns DH SCLK to SDIO (or SDO) Data Valid Time (t ) Full IV 14 ns DV SEN to SDIO Output Valid to Hi-Z (tEZ) Full IV 2 ns HALF-DUPLEX DATA INTERFACE (ADIO PORT) TIMING SPECIFICATIONS AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%, unless otherwise noted. Table 6. Parameter Temp Test Level Min Typ Max Unit 1 READ OPERATION (See Figure 50) Output Data Rate Full II 5 80 MSPS Three-State Output Enable Time (tPZL) Full II 3 ns Three-State Output Disable Time (tPLZ) Full II 3 ns Rx Data Valid Time (t ) Full II 1.5 ns VT Rx Data Output Delay (t ) Full II 4 ns OD WRITE OPERATION (See Figure 49) Input Data Rate (1× Interpolation) Full II 20 80 MSPS Input Data Rate (2× Interpolation) Full II 10 80 MSPS Input Data Rate (4× Interpolation) Full II 5 50 MSPS Tx Data Setup Time (tDS) Full II 1 ns Tx Data Hold Time (t ) Full II 2.5 ns DH Latch Enable Time (t ) Full II 3 ns EN Latch Disable Time (tDIS) Full II 3 ns 1 C = 5 pF for digital data outputs. LOAD Rev. A | Page 7 of 48 AD9865 FULL-DUPLEX DATA INTERFACE (Tx AND Rx PORT) TIMING SPECIFICATIONS AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%, unless otherwise noted. Table 7. Parameter Temp Test Level Min Typ Max Unit Tx PATH INTERFACE (See Figure 53) Input Nibble Rate (2× Interpolation) Full II 20 160 MSPS Input Nibble Rate (4× Interpolation) Full II 10 100 MSPS Tx Data Setup Time (tDS) Full II 2.5 ns Tx Data Hold Time (t ) Full II 1.5 ns DH 1 Rx PATH INTERFACE (See Figure 54) Output Nibble Rate Full II 10 160 MSPS Rx Data Valid Time (t ) Full II 3 ns DV Rx Data Hold Time (t ) Full II 0 ns DH 1 CLOAD =5 pF for digital data outputs. EXPLANATION OF TEST LEVELS I 100% production tested. II 100% production tested at 25°C and guaranteed by design and characterization at specified temperatures. III Sample tested only. IV Parameter is guaranteed by design and characterization testing. V Parameter is a typical value only. VI 100% production tested at 25°C and guaranteed by design and characterization for industrial temperature range. Rev. A | Page 8 of 48 AD9865 ABSOLUTE MAXIMUM RATINGS Table 8. Parameter Rating Stresses above those listed under the Absolute Maximum ELECTRICAL Ratings may cause permanent damage to the device. This is a AVDD, CLKVDD Voltage 3.9 V maximum stress rating only; functional operation of the device at these or DVDD, DRVDD Voltage 3.9 V maximum any other conditions above those indicated in the operational RX+, RX−, REFT, REFB −0.3 V to AVDD + 0.3 V section of this specification is not implied. Exposure to absolute IOUTP+, IOUTP− −1.5 V to AVDD + 0.3 V maximum rating conditions for extended periods may affect IOUTN+, IOUTN−, IOUTG+, −0.3 V to +7 V device reliability. IOUTG− OSCIN, XTAL −0.3 V to CLVDD + 0.3 V THERMAL CHARACTERISTICS REFIO, REFADJ −0.3 V to AVDD + 0.3 V Thermal Resistance: 64-lead LFCSP (4-layer board). Digital Input and Output Voltage −0.3 V to DRVDD + 0.3 V θ = 24°C/W (paddle soldered to ground plane, 0 LPM air). Digital Output Current 5 mA maximum JA ENVIRONMENTAL θJA = 30.8°C/W (paddle not soldered to ground plane, Operating Temperature Range −40°C to +85°C 0 LPM air). (Ambient) Maximum Junction Temperature 125°C Lead Temperature (Soldering, 10 s) 150°C Storage Temperature Range −65°C to +150°C (Ambient) ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. A | Page 9 of 48 AD9865 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 64 63 62 61 60 59 58 57 56 55 54 53 51 50 49 52 48 AVSS ADIO9/Tx[5] 1 47 AVSS ADIO8/Tx[4] 2 PIN 1 46 IOUT_N– ADIO7/Tx[3] 3 IDENTIFIER 45 IOUT_G– 4 ADIO6/Tx[2] 44 AVSS ADIO5/Tx[1] 5 43 AVDD 6 ADIO4/Tx[0] AD9865 42 REFIO ADIO3/Rx[5] 7 TOP VIEW 41 REFADJ 8 ADIO2/Rx[4] (Not to Scale) 40 AVDD ADIO1/Rx[3] 9 39 AVSS 10 ADIO0/Rx[2] 38 11 RX+ NC/Rx[1] 37 RX– NC/Rx[0] 12 36 AVSS RXEN/RXSYNC 13 35 AVDD TXEN/TXSYNC 14 34 15 AVSS TXCLK/TXQUIET 33 REFT RXCLK 16 17 18 19 20 21 22 23 24 25 26 27 28 30 31 32 29 Figure 2. Pin Configuration Table 9. Pin Function Descriptions 1 Pin No. Mnemonic Mode Description 1 ADIO9 HD MSB of ADIO Buffer Tx[5] FD MSB of Tx Nibble Input 2 to 5 ADIO8 to 5 HD Bits 8 to 5 of ADIO Buffer Tx[4 to 1] FD Bits 4 to 1 of Tx Nibble Input 6 ADIO4 HD Bit 4 of ADIO Buffer Tx[0] FD LSB of Tx Nibble Input 7 ADIO3 HD Bit 3 of ADIO Buffer Rx[5] FD MSB of Rx Nibble Output 8, 9 ADIO2, 1 HD Bits 2 to 1 of ADIO Buffer Rx[4, 3] FD Bits 4 to 3 of Rx Nibble Output 10 ADIO0 HD LSB of ADIO Buffer Rx[2] FD Bit 2 of Rx Nibble Output 11 NC HD No Connect Rx[1] FD Bit 1 of Rx Nibble Output 12 NC HD No Connect Rx[0] FD LSB of Rx Nibble Output 13 RXEN HD ADIO Buffer Control Input RXSYNC FD Rx Data Synchronization Output 14 TXEN HD Tx Path Enable Input TXSYNC FD Tx Data Synchronization Input Rev. A | Page 10 of 48 DRVDD DRVDD DRVSS DRVSS CLKOUT1 PWR_DWN SDIO CLKOUT2 SDO DVDD SCLK DVSS SEN CLKVDD GAIN/PGA[5] OSCIN PGA[4] XTAL PGA[3] CLKVSS PGA[2] CONFIG PGA[1] MODE PGA[0] IOUT_P+ RESET IOUT_P– AVSS IOUT_N+ REFB IOUT_G+ 4493-0-002 AD9865 1 Pin No. Mnemonic Mode Description 15 TXCLK HD ADIO Sample Clock Input TXQUIET FD Fast TxDAC/IAMP Power-Down 16 RXCLK HD ADIO Request Clock Input FD Rx and Tx Clock Output at 2 x f ADC 17, 64 DRVDD Digital Output Driver Supply Input 18, 63 DRVSS Digital Output Driver Supply Return 19 CLKOUT1 fADC/N Clock Output (L = 1, 2, 4, or 8) 20 SDIO Serial Port Data Input/Output 21 SDO Serial Port Data Output 22 SCLK Serial Port Clock Input 23 SEN Serial Port Enable Input 24 GAIN FD Tx Data Port (Tx[5:0]) Mode Select PGA[5] HD or FD MSB of PGA Input Data Port 25 to 29 PGA[4 to 0] HD or FD Bits 4 to 0 of PGA Input Data Port 30 RESET Reset Input (Active Low) 31, 34, 36, 39, 44, 47, 48 AVSS Analog Ground 32, 33 REFB, REFT ADC Reference Decoupling Nodes 35, 40, 43 AVDD Analog Power Supply Input 37, 38 RX−, RX+ Receive Path − and + Analog Inputs 41 REFADJ TxDAC Full-Scale Current Adjust 42 REFIO TxDAC Reference Input/Output 45 IOUT_G− −Tx Amp Current Output_Sink 46 IOUT_N− −Tx Mirror Current Output_Sink 49 IOUT_G+ +Tx Amp Current Output_Sink 50 IOUT_N+ +Tx Mirror Current Output_Sink 51 IOUT_P− −TxDAC Current Output_Source 52 IOUT_P+ +TxDAC Current Output_Source 53 MODE Digital Interface Mode Select Input LOW = HD, HIGH = FD 54 CONFIG Power-Up SPI Register Default Setting Input 55 CLKVSS Clock Oscillator/Synthesizer Supply Return 56 XTAL Crystal Oscillator Inverter Output 57 OSCIN Crystal Oscillator Inverter Input 58 CLKVDD Clock Oscillator/Synthesizer Supply 59 DVSS Digital Supply Return 60 DVDD Digital Supply Input 61 CLKOUT2 f /L Clock Output, (L = 1, 2, or 4) OSCIN 62 PWR_DWN Power-Down Input 1 HD = half-duplex mode; FD = full-duplex mode. Rev. A | Page 11 of 48 AD9865 TYPICAL PERFORMANCE CHARACTERISTICS Rx PATH TYPICAL PERFORMANCE CHARACTERISTICS AVDD = CLKVDD = DVDD = DRVDD = 3.3 V, f = f = 50 MSPS, low-pass filter’s f = 22 MHz, AIN = −1 dBFS, OSCIN ADC −3 dB RIN = 50 Ω, half- or full-duplex interface, default power bias settings. 62 10.0 10 1MHz FUND = –1dBFS 0 SINAD = 59.1dBFS 5MHz ENOB = 9.53 BITS 59 10MHz 9.5 –10 SNR = 60.2dBFS 15MHz THD = –65.2dBFS 20MHz –20 56 9.0 SFDR = –64.9dBc (THIRD HARMONIC) RBW = 12.21kHz –30 53 8.5 –40 –50 50 8.0 –60 47 7.5 –70 –80 44 7.0 –90 41 6.5 –100 –6 0 6 12 18 24 30 36 42 48 0 6.25 12.50 18.75 25.00 RxPGA GAIN (dB) FREQUENCY (MHz) Figure 3. Spectral Plot with 4 k FFT of Input Sinusoid with Figure 6. SINAD/ENOB vs. RxPGA Gain and Frequency RxPGA = 0 dB and PIN = 9 dBm –30 –55 RBW = 12.2kHz 1MHz –40 5MHz 10MHz –60 –50 15MHz 20MHz –60 –65 –70 –80 –70 –90 –75 –100 –110 –80 –120 –130 –85 0 5 10 15 20 25 –6 0 6 12 18 24 30 36 42 48 FREQUENCY (MHz) RxPGA GAIN (dB) Figure 4. Spectral Plot with 4 k FFT of 84-Carrier DMT Signal Figure 7. THD vs. RxPGA Gain and Frequency with PAR = 10.2 dB, PIN = −33.7 dBm, and RxPGA = 36 dB 62 –45 66 –50 SINAD @ +25°C SINAD @ +85°C 59 SINAD @ –40°C –50 63 –56 60 –62 56 –55 THD @ +25°C THD @ +85°C 57 –68 53 –60 THD @ –40°C 54 –74 50 –65 51 –80 47 –70 48 SINAD @ 3.14V THD @ 3.14V –86 44 –75 SINAD @ 3.3V THD @ 3.3V SINAD @ 3.46V THD @ 3.46V 45 –92 –21 –18 –15 –12 –9 –6 –3 0 41 –80 –6 0 6 12 18 24 30 36 42 48 INPUT AMPLITUDE (dBFS) 0dBFS = 2V p-p RxPGA GAIN (dB) Figure 5. SINAD and THD vs. Input Amplitude and Supply Figure 8. SINAD/THD Performance vs. RxPGA Gain (fIN = 8 MHz, LPF f−3 dB = 26 MHz; Rx PGA = 0 dB) and Temperature ( f = 5 MHz) IN Rev. A | Page 12 of 48 SINAD (dBFS) INPUT REFERRED SPECTRUM (dBm) INPUT REFERRED SPECTRUM (dBm) 04493-0-040 04493-0-041 THD (dBFS) 04493-0-042 SINAD (dBFS) SINAD (dBFS) THD (dBFC) 04493-0-044 THD (dBc) ENOB (Bits) 04493-0-045 04493-0-043 AD9865 Rx PATH TYPICAL PERFORMANCE CHARACTERISTICS AVDD = CLKVDD = DVDD = DRVDD = 3.3 V, fOSCIN = fADC = 80 MSPS, low-pass filter’s f−3 dB = 30 MHz, AIN = −1 dBFS, RIN = 50 Ω, half- or full-duplex interface, default power bias settings. 10 62 10.0 5MHz FUND = –1dBFS 0 SINAD = 59.3dBFS 10MHz 15MHz ENOB = 9.56 BITS 59 9.5 –10 SNR = 59.8dBFS 20MHz THD = –69.1dBFS 30MHz –20 56 9.0 SFDR = –70.3dBc (THIRD HARMONIC) RBW = 19.53kHz –30 53 8.5 –40 –50 50 8.0 –60 47 7.5 –70 –80 44 7.0 –90 –100 41 6.5 0 1020 3040 –6 0 6 12 18 24 30 36 42 48 FREQUENCY (MHz) RxPGA GAIN (dB) Figure 9. Spectral Plot with 4k FFT of Input Sinusoid Figure 12. SINAD/ENOB vs. RxPGA Gain and Frequency with RxPGA = 0 dB and P = 9 dBm IN –30 –55 RBW = 19.53kHz –40 –60 –50 –60 –65 –70 –70 –80 –90 –75 –100 5MHz 10MHz –110 –80 15MHz 20MHz –120 30MHz –85 –130 –6 0 6 12 18 24 30 36 42 48 0 10203040 FREQUENCY (MHz) RxPGA GAIN (dB) Figure 10. Spectral Plot with 4k FFT of 111-Carrier DMT Signal with Figure 13. THD vs. RxPGA Gain and Frequency PAR = 11 dB, PIN = −33.7 dBm, LPF f−3 dB = 32 MHz, and RxPGA = 36 dB 62 –40 66 –50 SINAD @ +25°C SINAD @ 3.14V THD @ 3.14V SINAD @ +85°C SINAD @ 3.3V THD @ 3.3V 59 SINAD @ –40°C –45 63 –56 SINAD @ 3.46V THD @ 3.46V 56 –50 60 –62 THD @ +25°C THD @ +85°C 53 –55 57 –68 THD @ –40°C 50 –60 54 –74 47 –65 51 –80 44 –70 48 –86 41 –75 45 –92 –6 0 6 12 18 24 30 36 42 48 –21 –18 –15 –12 –9 –6 –3 0 RxPGA GAIN (dB) INPUT AMPLITUDE (dBFS) 0dBFS = 2V p-p Figure 14. SINAD/THD Performance vs. RxPGA Gain and Temperature Figure 11. SINAD and THD vs. Input Amplitude and Supply ( f = 10 MHz) IN (f = 8 MHz, LPF f = 26 MHz; RxPGA = 0 dB) IN −3 dB Rev. A | Page 13 of 48 SINAD (dBFS) INPUT REFERRED SPECTRUM (dBm) INPUT REFERRED SPECTRUM (dBm) 04493-0-047 04493-0-046 THD (dBFS) 04493-0-048 SINAD (dBFS) SINAD (dBFS) THD (dBc) 04493-0-050 ENOB (Bits) THD (dBc) 04493-0-049 04493-0-051 AD9865 61.0 –52 60.0 –20 SNR @ 3.13V SNR @ 3.3V 60.5 –54 59.5 SNR @ 3.47V 60.0 –56 59.0 –30 SNR @ 3.13V SNR @ 3.3V 59.5 –58 58.5 THD @ 3.13V SNR @ 3.46V THD @ 3.3V 59.0 –60 58.0 –40 THD @ 3.47V 58.5 –62 57.5 THD @ 3.13V 58.0 –64 THD @ 3.3V 57.0 –50 THD @ 3.46V 57.5 –66 56.5 57.0 –68 56.0 –60 56.5 –70 55.5 56.0 –72 55.0 –70 –6 0 6 12 18 24 30 36 42 48 20 30 40 50 60 70 80 INPUT FREQUENCY (MHz) INPUT FREQUENCY (MHz) Figure 15. SNR and THD vs. Input Frequency and Supply Figure 18. SNR and THD vs. Sample Rate and Supply ( LPF f = 26 MHz; RxPGA = 0 dB) −3 dB (LPF Disabled; RxPGA = 0 dB; f = 8 MHz) IN 109.4 20 45 98.5 18 44 87.5 16 43 76.6 14 AD9865: +25°C 65.6 AD9865: +85°C 12 42 AD9865: –40°C 54.7 10 41 43.8 8 32.8 6 40 21.9 4 39 10.9 2 0 0 38 –6 0 6 12 18 24 30 36 42 48 0 1020 3040 506070 80 RxPGA GAIN (dB) CUTOFF FREQUENCY (MHz) Figure 16. Input Referred Integrated Noise and Noise Spectral Density vs. Figure 19. SNR vs. Filter Cutoff Frequency RxPGA Gain (LPF f−3 dB = 26 MHz) (50 MSPS; fIN = 5 MHz; AIN = −1 dB; RxPGA = 48 dB) 5 0.5 4 0.4 3 0.3 2 0.2 1 0.1 0 0 –1 –0.1 –2 –0.2 DEVICE 1 –3 –0.3 DEVICE 2 AD9865: GAIN STEP ERROR @ +25°C DEVICE 3 –4 –0.4 AD9865: GAIN STEP ERROR @ +85°C DEVICE 4 AD9865: GAIN STEP ERROR @ –40°C –5 –0.5 –6 0 6 12 18 24 30 36 42 48 –6 0 6 12 18 24 30 36 42 48 GAIN (dB) RxPGA GAIN (dB) Figure 17. Rx DC Offset vs. RxPGA Gain Figure 20. RxPGA Gain Step Error vs. Gain (f = 10 MHz) IN Rev. A | Page 14 of 48 INTEGRATED NOISE (µV rms) SNR (dBFS) DC OFFSET (% of full-scale) 04493-0-054 NOISE SPECTRAL DENSITY (nV/ Hz) THD (dBc) 04493-0-053 04493-0-052 SNR (dBFS) GAIN STEP ERROR (dB) SNR (dBc) 04493-0-056 04493-0-057 THD (dBc) 04493-0-055 AD9865 Rx PATH TYPICAL PERFORMANCE CHARACTERISTICS AVDD = CLKVDD = DVDD = DRVDD = 3.3 V, fOSCIN = fADC = 50 MSPS, low-pass filter disabled, RxPGA = 0 dB, AIN = −1 dBFS, RIN = 50 Ω, half- or full-duplex interface, default power bias settings. 512 352 320 448 288 384 256 320 224 192 256 160 192 128 128 96 64 64 0 80 160 240 320 400 480 560 640 720 0 80 160 240 320 400 480 560 640 720 TIME (ns) TIME (ns) Figure 21. RxPGA Settling Time −12 dB to +48 dB Transition for DC Input Figure 24. RxPGA Settling Time for 0 dB to +5 dB Transition for DC Input (fADC = 50 MSPS, LPF Disabled) (fADC = 50 MSPS, LPF Disabled) 0 0 3.3V –6dB GAIN 3.0V 0dB GAIN –2 3.6V +6dB GAIN –3 –4 –6 –6 –8 –10 –9 +18dB GAIN +30dB GAIN –12 +42dB GAIN –12 –14 –16 –15 –18 –20 –18 0 5 10 15 20 25 30 35 40 45 50 0 5 10 15 20 25 30 35 40 45 50 INPUT FREQUENCY (MHz) INPUT FREQUENCY (MHz) Figure 22. Rx Low-Pass Filter Amplitude Response vs. Supply Figure 25. Rx Low-Pass Filter Amplitude Response vs. RxPGA Gain (f = 50 MSPS, f = 33 MHz, RxPGA = 0 dB) (LPF's f = 33 MHz) ADC −3 dB −3 dB 140 420 10 410 9 130 TxDAC ISOLATION @ 0dB 400 8 120 390 7 110 R IN 380 6 100 370 5 360 4 90 C IN 350 3 80 IAMP ISOLATION @ 0dB 340 2 70 330 1 60 320 0 0 5 10 15 20 25 30 35 5 15 25 35 45 55 65 75 85 95 105 FREQUENCY (MHz) FREQUENCY (MHz) Figure 23. Rx to Tx Full-Duplex Isolation @ 0 RxPGA Setting Figure 26. Rx Input Impedance vs. Frequency (Note: ATTEN @ RxPGA = x dB = ATTEN @ RxPGA = 0 dB − RxPGA Gain) Rev. A | Page 15 of 48 ATTEN (dB) AMPLITUDE RESPONSE (dB) CODE @RxPGA = 0dB 04493-0-060 04493-0-058 04493-0-059 RESISTANCE (Ω) FUNDAMENTAL (dB) CODE 04493-0-062 04493-0-061 CAPACITANCE (pF) 04493-0-090 AD9865 TxDAC PATH TYPICAL PERFORMANCE CHARACTERISTICS AVDD = CLKVDD = DVDD = DRVDD = 3.3 V, fOSCIN = 50 MSPS and 80 MSPS, RSET = 1.96 kΩ, 2:1 transformer coupled output (see Figure 63) into 50 Ω load half- or full-duplex interface, default power bias settings. 10 10 0 0 –10 –10 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 0 5 10 15 20 30 0 5 10 15 20 25 30 35 40 FREQUENCY (MHz) FREQUENCY (MHz) Figure 27. Dual-Tone Spectral Plot of TxDAC's Output Figure 30. Dual-Tone Spectral Plot of TxDAC's Output (fDATA = 50 MSPS, 4× Interpolation, 10 dBm Peak Power, (fDATA = 80 MSPS, 2× Interpolation, 10 dBm Peak Power, F1 = 17 MHz, F2 = 18 MHz) F1 = 27.1 MHz, F2 = 28.7 MHz) –65 –65 –70 –70 10dBm –75 –75 4dBm 4dBm 7dBm 7dBm –80 –80 10dBm –85 –85 –90 –90 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 0 5 10 15 20 25 30 2-TONE CENTER FREQUENCY (MHz) 2-TONE CENTER FREQUENCY (MHz) Figure 28. 2-Tone IMD Frequency Sweep vs. Peak Power Figure 31. 2-Tone IMD Frequency Sweep vs. Peak Power with f = 50 MSPS, 4× Interpolation with f = 80 MSPS, 2× Interpolation DATA DATA –65 –65 –70 –70 10dBm –75 –75 4dBm 4dBm 7dBm 10dBm –80 –80 7dBm –85 –85 –90 –90 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 0 5 10 15 20 25 30 2-TONE CENTER FREQUENCY (MHz) 2-TONE CENTER FREQUENCY (MHz) Figure 29. 2-Tone Worst Spur Frequency Sweep vs. Peak Power Figure 32. 2-Tone Worst Spur Frequency Sweep vs. Peak Power with fDATA = 50 MSPS, 4× Interpolation with fDATA = 80 MSPS, 2× Interpolation Rev. A | Page 16 of 48 SFDR (dBFS) IMD (dBFS) dBm (RELATIVE TO PEAK POWER) (RELATIVE TO PEAK POWER) 04493-0-072 04493-0-074 04493-0-073 SFDR (dBFS) IMD (dBFS) dBm (RELATIVE TO PEAK POWER) (RELATIVE TO PEAK POWER) 04493-0-075 04493-0-077 04493-0-076 AD9865 –20 –20 PAR = 11.4 PAR = 11.4 RMS = –1.4dBm RMS = –1.4dBm –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 –100 0 5 10 15 20 25 0 5 10 15 20 25 30 35 40 FREQUENCY (MHz) FREQUENCY (MHz) Figure 33. Spectral Plot of 84-Carrier OFDM Test Vector Figure 36. Spectral Plot of 111-Carrier OFDM Test Vector (fDATA = 50 MSPS, 4× Interpolation) (fDATA = 80 MSPS, 2× Interpolation) –20 –20 PAR = 11.4 PAR = 11.4 RMS = –1.4dBm RMS = –1.4dBm –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 –100 0 25 50 75 100 125 150 175 200 0 20 40 60 80 100 120 140 160 FREQUENCY (MHz) FREQUENCY (MHz) Figure 34. Wideband Spectral Plot of 88-Subcarrier OFDM Test Vector Figure 37. Wideband Spectral Plot of 111-Carrier OFDM Test Vector (f = 50 MSPS, 4× Interpolation) (f = 80 MSPS, 2× Interpolation) DATA DATA 100 95 2-TONE IMD 95 90 2-TONE IMD 90 85 85 80 80 75 75 70 70 SNR SNR 65 65 60 60 55 55 –24 –21 –18 –15 –12 –9 –6 –3 0 –24 –21 –18 –15 –12 –9 –6 –3 0 AOUT (dBFS) AOUT (dBFS) Figure 35. SNR and SFDR vs. POUT Figure 38. SNR and SFDR vs. POUT (fOUT = 12.55 MHz, fDATA = 50 MSPS, 4× Interpolation) (fOUT = 20 MHz, fDATA = 80 MSPS, 2× Interpolation) Rev. A | Page 17 of 48 SNR AND 2-TONE IMD (dBFS) dBm dBm (RELATIVE TO PEAK POWER) 04493-0-079 04493-0-078 04493-0-080 SNR AND 2-TONE IMD (dBFS) dBm dBm (RELATIVE TO PEAK POWER) 04493-0-082 04493-0-081 04493-0-083 AD9865 IAMP PATH TYPICAL PERFORMANCE CHARACTERISTICS AVDD = CLKVDD = DVDD = DRVDD = 3.3 V, fOSCIN = 50 MSPS, RSET = 1.58 kΩ, 1:1 transformer coupled output (see Figure 64 and Figure 65) into 50 Ω load, half- or full-duplex interface, default power bias settings. 20 48 RBW = 2.3kHz 2.5MHz 15 46 10 5MHz 5 44 0 –5 42 –10 –15 40 –20 10MHz 38 –25 20MHz 15MHz –30 36 –35 –40 34 –45 –50 32 –55 –60 30 0 5 10 15 20 25 3.0 3.5 4.0 4.5 5.0 FREQUENCY (MHz) VCM (V) Figure 39. Dual-Tone Spectral Plot of IAMPN Output Figure 42. IOUTN Third-Order Intercept vs. Common-Mode Voltage (IAMP Settings of I = 12.5 mA, N = 4, G = 0, (IAMP Settings of I = 12.5 mA, N = 4, G = 0, 2:1 2:1 Transformer into 75 Ω Loader, VCM = 4.8 V) Transformer into 75 Ω Load) 0 42 PAR = 11.4 RMS = 10.3dBm –10 40 2.5MHz –20 38 –30 5MHz –40 36 –50 10MHz 34 –60 15MHz 32 –70 20MHz –80 30 0 5 10 15 20 25 3.0 3.5 4.0 4.5 5.0 FREQUENCY (MHz) VCM (V) Figure 40. Spectral Plot of 84-Carrier OFDM Test Vector Using IAMPN in Figure 43. IOUTG Third-Order Intercept vs. Common-Mode Voltage Current-Mode Configuration (IAMP Settings of I = 4.25 mA, N = 0, G = 6, (IAMP Settings of I = 10 mA, N = 4, G = 0; VCM = 4.8 V) 2:1 Transformer into 75 Ω Load) 0 0 PAR = 11.4 PAR = 11.4 RMS = 10.4dBm RMS = 9.8dBm –10 –10 RBW = 10kHz –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 0 5 10 15 20 25 0 5 10 15 20 25 FREQUENCY (MHz) FREQUENCY (MHz) Figure 44. Spectral Plot of 84-Carrier OFDM Test Vector Using IAMP in Figure 41. Spectral Plot of 84-Carrier OFDM Test Vector Using IAMP in Voltage-Mode Configuration with AVDD = 3.3 V Voltage-Mode Configuration with AVDD = 5 V (PBR951 Transistors, IAMP Settings of I = 6 mA, N = 2, G = 6) (PBR951 Transistors, IAMP Settings of I = 6 mA, N = 2, G = 6) Rev. A | Page 18 of 48 dBm dBm dBm 04493-0-085 04493-0-086 04493-0-084 OIP3 (dBm) dBm OIP3 (dBm) 04493-0-088 04493-0-089 04493-0-087 AD9865 SERIAL PORT Table 10. SPI Register Mapping Power-Up Default Value Bit MODE = 0 (Half-Duplex) MODE = 1 (Full-Duplex) Address Break- 1 (Hex) down Description Width Comments CONFIG = 0 CONFIG = 1 CONFIG = 0 CONFIG = 1 SPI PORT CONFIGURATION AND SOFTWARE RESET 0x00 (7) 4-Wire SPI 1 0 0 0 0 Default SPI configuration is 3-wire, MSB first. (6) LSB First 1 0 0 0 0 (5) S/W Reset 1 0 0 0 0 POWER CONTROL REGISTERS (via PWR_DWN pin) 0x01 (7) 1 0 0 0 0 PWR_DWN = 0. Clock Syn. Default setting is for all (6) TxDAC/IAMP 1 0 0 0 0 blocks powered on. (5) Tx Digital 1 0 0 0 0 (4) REF 1 0 0 0 0 (3) ADC CML 1 0 0 0 0 (2) ADC 1 0 0 0 0 (1) PGA Bias 1 0 0 0 0 (0) RxPGA 1 0 0 0 0 0x02 (7) CLK Syn. 1 0 0 0 1* PWR_DWN = 1. Default setting* is for all (6) TxDAC/IAMP 1 1 1 1 1 functional blocks powered (5) Tx Digital 1 1 1 1 1 down except PLL. (4) REF 1 1 1 1 1 *MODE = CONFIG = 1. (3) ADC CML 1 1 1 1 1 Setting has PLL powered (2) ADC 1 1 1 1 1 down with OSCIN input routed to RXCLK output. (1) PGA Bias 1 1 1 1 1 (0) RxPGA 1 1 1 1 1 HALF-DUPLEX POWER CONTROL 0x03 (7:3) Tx OFF Delay 5 Default setting is for TXEN input to control power (2) Rx _TXEN 1 0xFF 0xFF N/A N/A on/off of Tx/Rx path. (1) Tx PWRDN 1 Tx driver delayed by 31 (0) Rx PWRDN 1 1/fDATA clock cycles. PLL CLOCK MULTIPLIER/SYNTHESIZER CONTROL 0x04 (5) Duty Cycle Enable 1 0 0 0 0 Default setting is Duty Cycle Restore disabled, ADC CLK (4) fADC from PLL 1 0 0 0 0 from OSCIN input, and PLL (3:2) PLL Divide-N 2 00 00 00 00 multiplier × 2 setting. (1:0) PLL Multiplier-M 2 01 10* 01 01 *PLL multiplier × 4 setting. 0x05 (2) OSCIN to RXCLK 1 0 0 0 1* Full-duplex RXCLK normally at nibble rate. (1) Invert RXCLK 1 0 0 0 0 *Exception on power-up. (0) Disabled RXCLK 1 0 0 0 0 0x06 (7:6) CLKOUT2 Divide 2 01 01 01 01 Default setting is CLKOUT2 and CLKOUT1 enabled with (5) CLKOUT2 Invert 1 0 0 0 0 divide-by-2. (4) CLKOUT2 Disable 1 0 0 0 1* *CLKOUT1 and CLKOUT2 (3:2) CLKOUT1 Divide 2 01 01 01 01 disabled. (1) CLKOUT1 Invert 1 0 0 0 0 (0) CLKOUT1 Disable 1 0 0 0 1* Rx PATH CONTROL 0x07 (5) Initiate Offset Cal. 1 0 0 0 0 Default setting has LPF ON and Rx path at nominal (4) Rx Low Power 1 0 1* 0 1* power bias setting. (0) Rx Filter ON 1 1 1 1 1 *Rx path to low power. Rev. A | Page 19 of 48 AD9865 Power-Up Default Value Bit MODE = 0 (Half-Duplex) MODE = 1 (Full-Duplex) Address Break- 1 (Hex) down Description Width Comments CONFIG = 0 CONFIG = 1 CONFIG = 0 CONFIG = 1 0x08 (7:0) Rx Filter Tuning 8 Refer to Low-Pass Filter 0x80 0x61 0x80 0x80 Cut-off Frequency section. Tx/Rx PATH GAIN CONTROL 0x09 (6) Use SPI Rx Gain 1 Default setting is for 0x00 0x00 0x00 0x00 hardware Rx gain code via (5:0) Rx Gain Code 6 PGA or Tx data port. 0x0A (6) Use SPI Tx Gain 1 Default setting is for Tx gain 0x7F 0x7F 0x7F 0x7F code via SPI control. (5:0) Tx Gain Code 6 Tx AND Rx PGA CONTROL 0x0B (6) PGA Code for Tx 1 0 0 0 0 Default setting is RxPGA control active. (5) PGA Code for Rx 1 1 1 1 1 *Tx port with GAIN strobe (3) Force GAIN strobe 1 0 0 0 0 (AD9875/AD9876-compatible). (2) Rx Gain on Tx Port 1 0 0 1* 1* ** 3-bit RxPGA gain map (1) 3-Bit RxPGA Port 1 0 1** 0 0 (AD9975-compatible). Tx DIGITAL FILTER AND INTERFACE 0x0C (7:6) Interpolation 2 01 00 01 01 Default setting is 2× Factor interpolation with LPF response. Data format is (4) Invert 1 0 0 0 0 straight binary for half- TXEN/TXSYNC duplex and twos (3) Tx 5/5 Nibble* 1 N/A N/A 0 0 complement for full-duplex (2) LS Nibble First* 1 N/A N/A 0 0 interface. (1) TXCLK neg. edge 1 0 0 0 0 *Full-duplex only. (0) Twos complement 1 0 0 1 1 Rx INTERFACE AND ANALOG/DIGITAL LOOPBACK 0x0D (7) Analog Loopback 1 0 0 0 0 Data format is straight binary for half-duplex and (6) Digital Loopback* 1 0 0 0 0 twos complement for full- (5) Rx Port 3-State 1 N/A N/A 0 0 duplex interface. (4) Invert 1 0 0 0 0 Analog loopback: ADC Rx RXEN/RXSYNC data fed back to TxDAC. (3) RX 5/5 Nibble 1 N/A N/A 0 0 Digital loopback: Tx input (2) LS Nibble First* 1 N/A N/A 0 0 data to Rx output port. *Full-duplex only. (1) RXCLK neg. edge 1 0 0 0 0 (0) Twos complement 1 0 0 1 1 DIGITAL OUTPUT DRIVE STRENGTH, TxDAC OUTPUT, AND REV ID 0x0E (7) Low Drive 1 0 0 0 0 Default setting is for high Strength drive strength and IAMP enabled. (0) TxDAC Output 1 0 0 0 0 0x0F (3:0) REV ID Number 4 0x00 0x00 0x00 0x00 Tx IAMP GAIN AND BIAS CONTROL 0x10 (7) Select Tx Gain 1 Secondary path G1 = 0, 1, 2, 3, 4. 0x44 0x44 0x44 0x44 (6:4) G1 3 Primary path N = 0, 1, 2, 3, 4. (2:0) N 3 0x11 (6:4) G2 3 Secondary path stages: 0x62 0x62 0x62 0x62 (2:0) G3 3 G2 = 0 to 1.50 in 0.25 steps and G3 = 0 to 6. 0x12 (6:4) Stand_Secondary 3 Standing current of primary 0x01 0x01 0x01 0x01 and secondary path. (2:0) Stand_Primary 3 Rev. A | Page 20 of 48 AD9865 Power-Up Default Value Bit MODE = 0 (Half-Duplex) MODE = 1 (Full-Duplex) Address Break- 1 (Hex) down Description Width Comments CONFIG = 0 CONFIG = 1 CONFIG = 0 CONFIG = 1 0x13 Current bias setting for Rx (7:5) CPGA Bias Adjust 3 path’s functional blocks. (4:3) SPGA Bias Adjust 2 0x00 0x00 0x00 0x00 Refer to page 41. (2:0) ADC Bias Adjust 4 1 Bits that are undefined should always be assigned a 0. Table 11. SPI Registers Pertaining to SPI Options REGISTER MAP DESCRIPTION Address (Hex) Bit Description The AD9865 contains a set of programmable registers described 0x00 (7) Enable 4-wire SPI in Table 10 that are used to optimize its numerous features, (6) Enable SPI LSB first interface options, and performance parameters from its default register settings. Registers pertaining to similar functions have A 4-wire SPI can be enabled by setting the 4-wire SPI bit high, been grouped together and assigned adjacent addresses to causing the output data to appear on the SDO pin instead of on minimize the update time when using the multibyte serial port the SDIO pin. The SDIO pin serves as an input-only throughout interface (SPI) read/write feature. Bits that are undefined within the read operation. Note that the SDO pin is active only during a register should be assigned a 0 when writing to that register. the transmission of data and remains three-stated at any other time. The default register settings were intended to allow some applications to operate without the use of an SPI. The AD9865 An 8-bit instruction header must accompany each read and can be configured to support a half- or full-duplex digital write operation. The instruction header is shown in Table 12. interface via the MODE pin, with each interface having two The MSB is an R/W indicator bit with logic high indicating a possible default register settings determined by the setting of read operation. The next two bits, N1 and N0, specify the the CONFIG pin. number of bytes (one to four bytes) to be transferred during the data transfer cycle. The remaining five bits specify the address For instance, applications that need to use only the Tx or Rx bits to be accessed during the data transfer portion. The data path functionality of the AD9865 can configure it for a half- bits immediately follow the instruction header for both read duplex interface (MODE = 0), and use the TXEN pin to select and write operations. between the Tx or Rx signal path with the unused path remaining in a reduced power state. The CONFIG pin can be Table 12. Instruction Header Information used to select the default interpolation ratio of the Tx path and MSB LSB RxPGA gain mapping. 17 16 15 14 13 12 11 10 R/W N1 N0 A4 A3 A2 A1 A0 SERIAL PORT INTERFACE (SPI) The serial port of the AD9865 has 3- or 4-wire SPI capability The AD9865 serial port can support both MSB (most allowing read/write access to all registers that configure the significant bit) first and LSB (least significant bit) first data device’s internal parameters. Registers pertaining to the SPI are formats. Figure 45 illustrates how the serial port words are built listed in Table 11. The default 3-wire serial communication port for the MSB first and LSB first modes. The bit order is con- SEN consists of a clock (SCLK), serial port enable ( ), and a bi- trolled by the SPI LSB first bit (Register 0, Bit 6). The default directional data (SDIO) signal. is an active low control SEN value is 0, MSB first. Multibyte data transfers in MSB format gating read and write cycle. When SEN is high, SDO and SDIO can be completed by writing an instruction byte that includes are three-stated. The inputs to SCLK, , and SDIO contain a SEN the register address of the last address to be accessed. The AD9865 automatically decrements the address for each succes- Schmitt trigger with a nominal hysteresis of 0.4 V centered sive byte required for the multibyte communication cycle. about VDDH/2. The SDO pin remains three-stated in a 3-wire SPI interface. Rev. A | Page 21 of 48 AD9865 INSTRUCTION CYCLE DATA TRANSFER CYCLE Figure 47 illustrates the timing for a 3-wire read operation to SEN the SPI port. After goes low, data (SDIO) pertaining to the SEN SCLK instruction header is read on the rising edges of SCLK. A read R/W N1 N2 A4 A3 A2 A1 A0 D7 D6 D1 D0 SDATA 1 1 N N operation occurs, if the read/not-write indicator is set high. After the address bits of the instruction header are read, the eight data bits pertaining to the specified register are shifted out of the SDIO pin on the falling edges of the next eight clock cycles. INSTRUCTION CYCLE DATA TRANSFER CYCLE SEN If a multibyte communication cycle is specified in the instruction SCLK header, a similar process as previously described for a multibyte A2 A4 D6 D7 SDATA A0 A1 A3 N2 N1 R/W D0 D1 N N 1 1 SPI write operation applies. The SDO pin remains three-stated in a 3-wire read operation. t 1/f S SCLK Figure 45. SPI Timing, MSB First (Upper), and LSB First (Lower) SEN t t LOW HI When the SPI LSB first bit is set high, the serial port interprets SCLK both instruction and data bytes LSB first. Multibyte data trans- t DV t DS t t DH EZ fers in LSB format can be completed by writing an instruction N1 A2 A1 A0 D7 D6 D1 D0 SDIO R/W byte that includes the register address of the first address to be Figure 47. SPI 3-Wire Read Operation Timing accessed. The AD9865 automatically increments the address for each successive byte required for the multibyte communication cycle. Figure 48 illustrates the timing for a 4-wire read operation to the SPI port. The timing is similar to the 3-wire read operation Figure 46 illustrates the timing requirements for a write opera- with the exception that data appears at the SDO pin, while the tion to the SPI port. After the serial port enable ( ) signal SEN SDIO pin remains high impedance throughout the operation. goes low, data (SDIO) pertaining to the instruction header is The SDO pin is an active output only during the data transfer read on the rising edges of the clock (SCLK). To initiate a write phase and remains three-stated at all other times. operation, the read/not-write bit is set low. After the instruction header is read, the eight data bits pertaining to the specified t S 1/f SCLK register are shifted into the SDIO pin on the rising edge of the SEN t t next eight clock cycles. If a multibyte communication cycle is HI LOW SCLK specified, the destination address is decremented (MSB first) t DS t t and shifts in another eight bits of data. This process repeats until DH EZ A1 A0 SDIO R/W N1 A2 all the bytes specified in the instruction header (N1, N0 bits) are t EZ t DV shifted into the SDIO pin. SEN must remain low during the data D7 D6 D1 D0 SDO transfer operation, only going high after the last bit is shifted into the SDIO pin. Figure 48. SPI 4-Wire Read Operation Timing t S 1/f SCLK t H SEN t t LOW HI SCLK t DS t DH A0 D6 D1 SDIO R/W N1 N0 D7 D0 Figure 46. SPI Write Operation Timing Rev. A | Page 22 of 48 4493-0-003 4493-0-004 4493-0-006 4493-0-005 AD9865 DIGITAL INTERFACE appears on the bus after a 6-clock-cycle delay due to the internal The digital interface port is configurable for half-duplex or full- FIFO delay. Note that Rx data is not latched back into the Tx duplex operation by pin-strapping the MODE pin low or high, path, if TXEN is high during this interval with TXCLK present. respectively. In half-duplex mode, the digital interface port The ADIO bus becomes three-stated once the RXEN pin returns becomes a 10-bit bidirectional bus called the ADIO port. In low. Figure 50 shows the receive path output timing. full-duplex mode, the digital interface port is divided into two 6-bit ports called Tx[5:0] and Rx[5:0] for simultaneous Tx and RXCLK Rx operations. In this mode, data is transferred between the RXEN t OD ASIC and AD9865 in 6-bit (or 5-bit) nibbles. The AD9865 also t PZL t VT t PLZ ADIO[9:0] RX0 RX1 RX2 RX3 features a flexible digital interface for updating the RxPGA and TxPGA gain registers via a 6-bit PGA port or Tx[5:0] port for fast updates, or via the SPI port for slower updates. See the Figure 50. Receive Data Output Timing Diagram RxPGA Control section for more information. To add flexibility to the digital interface port, several program- HALF-DUPLEX MODE ming options are available in the SPI registers. These options The half-duplex mode functions as follows when the MODE are listed in Table 13. The default Tx and Rx data input formats pin is tied low. The bidirectional ADIO port is typically shared are straight binary, but can be changed to twos complement. in burst fashion between the transmit path and receive path. The default TXEN and RXEN settings are active high, but can Two control signals, TXEN and RXEN, from a DSP (or digital be set to opposite polarities, thus allowing them to share the ASIC) control the bus direction by enabling the ADIO port’s same control. In this case, the ADIO port can still be placed input latch and output driver, respectively. Two clock signals are onto a shared bus by disabling its input latch via the control signal, and disabling the output driver via the SPI register. The also used: TXCLK to latch the Tx input data, and RXCLK to clock the Rx output data. The ADIO port can also be disabled clock timing can be independently changed on the transmit and by setting TXEN and RXEN low (default setting), thus allowing receive paths by selecting either the rising or falling clock edge it to be connected to a shared bus. as the validating/sampling edge of the clock. Lastly, the output driver’s strength can be reduced for lower data rate applications. Internally, the ADIO port consists of an input latch for the Tx path in parallel with an output latch with three-state outputs for Table 13. SPI Registers for Half-Duplex Interface the Rx path. TXEN is used to enable the input latch; RXEN is Address (Hex) Bit Description used to three-state the output latch. A five-sample-deep FIFO is 0x0C (4) Invert TXEN used on the Tx and Rx paths to absorb any phase difference be- (1) TXCLK negative edge tween the AD9865’s internal clocks and the externally supplied (0) Twos complement clocks (TXCLK, RXCLK). The ADIO bus accepts input data- 0x0D (5) Rx port three-state words into the transmit path when the TXEN pin is high, the (4) Invert RXEN RXEN pin is low, and a clock is present on the TXCLK pin, as (1) RXCLK negative edge shown in Figure 49. (0) Twos complement t DS 0x0E (7) Low digital drive strength TXCLK The half-duplex interface can be configured to act as a slave or a TXEN t t DIS EN t DH master to the digital ASIC. An example of a slave configuration TX1 TX2 TX3 TX4 ADIO[9:0] TX0 is shown in Figure 51. In this example, the AD9865 accepts all the clock and control signals from the digital ASIC. Because the RXEN sampling clocks for the DAC and ADC are derived internally from the OSCIN signal, the TXCLK and RXCLK signals must Figure 49. Transmit Data Input Timing Diagram be at exactly the same frequency as the OSCIN signal. The The Tx interpolation filter(s) following the ADIO port can be phase relationships among the TXCLK, RXCLK, and OSCIN flushed with zeros, if the clock signal into the TXCLK pin is signals can be arbitrary. If the digital ASIC cannot provide a low present for 33 clock cycles after TXEN goes low. Note that the jitter clock source to OSCIN, use the AD9865 to generate the data on the ADIO bus is irrelevant over this interval. clock for its DAC and ADC, and to pass the desired clock signal to the digital ASIC via CLKOUT1 or CLKOUT2. The output from the receive path is driven onto the ADIO bus when the RXEN pin is high, and a clock is present on the RXCLK pin. While the output latch is enabled by RXEN, valid data Rev. A | Page 23 of 48 4493-0-007 4493-0-008 AD9865 DIGITAL ASIC AD9865 than the nibble rate. Therefore, the 2× or 4× interpolation filter must be used with a full-duplex interface. 10 ADIO TO [9:0] Tx DIGITAL FILTER The AD9865 acts as the master, providing RXCLK as an output Tx/Rx Data[9:0] 10 clock that is used for the timing of both the Tx[5:0] and Rx[5:0] FROM Rx ADC ports. RXCLK always runs at the nibble rate and can be inverted or disabled via an SPI register. Because RXCLK is derived from RXEN RXEN TXEN the clock synthesizer, it remains active, provided that this func- TXEN TXCLK DAC_CLK tional block remains powered on. A buffered version of the ADC_CLK RXCLK signal appearing at OSCIN can also be directed to RXCLK by CLKOUT OSCIN setting Bit 2 of Register 0x05. This feature allows the AD9865 to be completely powered down (including the clock synthesizer) while serving as the master. Figure 51. Example of a Half-Duplex Digital Interface with AD9865 Serving as the Slave The Tx[5:0] port operates in the following manner with the SPI Figure 52 shows a half-duplex interface with the AD9865 acting register default settings. Two consecutive nibbles of the Tx data as the master, generating all the required clocks. CLKOUT1 are multiplexed together to form a 10-bit data-word in twos provides a clock equal to the bus data rate that is fed to the complement format. The clock appearing on the RXCLK pin is ASIC as well as back to the TXCLK and RXCLK inputs. This a buffered version of the internal clock used by the Tx[5:0] interface has the advantage of reducing the digital ASIC’s pin port’s input latch with a frequency that is always twice the ADC count by three. The ASIC needs only to generate a bus control sample rate (2 × fADC). Data from the Tx[5:0] port is read on the signal that controls the data flow on the bidirectional bus. rising edge of this sampling clock, as illustrated in the timing diagram shown in Figure 53. Note, TXQUIET must remain DIGITAL ASIC AD9865 high for the reconstructed Tx data to appear as an analog signal 10 ADIO TO at the output of the TxDAC or IAMP. [9:0] Tx DIGITAL Tx/Rx FILTER Data[9:0] t tDS 10 SU FROM Rx ADC RXCLK RXEN t t HD DH BUS_CTR TXEN TXSYNC TXCLK RXCLK Tx1MSB Tx1LSB Tx2MSB Tx3LSB Tx3MSB Tx[5:0] Tx0LSB Tx2LSB CLKIN CLKOUT1 Figure 53. Tx[5:0] Port Full-Duplex Timing Diagram OSCIN FROM The TXSYNC signal is used to indicate to which word a nibble CRYSTAL belongs. While TXSYNC is low, the first nibble of every word is OR MASTER CLK read as the most significant nibble. The second nibble of that Figure 52. Example of a Half-Duplex Digital Interface same word is read on the following TXSYNC high level as the with AD9865 Serving as the Master least significant nibble. If TXSYNC is low for more than one FULL-DUPLEX MODE clock cycle, the last transmit data is read continuously until TXSYNC is brought high for the second nibble of a new trans- The full-duplex mode interface is selected when the MODE pin mit word. This feature can be used to flush the interpolator is tied high. It can be used for full- or half-duplex applications. filters with zeros. Note that the GAIN signal must be kept low The digital interface port is divided into two 6-bit ports called during a Tx operation. Tx[5:0] and Rx[5:0], allowing simultaneous Tx and Rx opera- tions for full-duplex applications. In half-duplex applications, The Rx[5:0] port operates in the following manner with the SPI the Tx[5:0] port can also be used to provide a fast update of the register default settings. Two consecutive nibbles of the Rx data RxPGA (AD9875 backward-compatible) during an Rx opera- are multiplexed together to form a 10-bit data-word in twos tion. This feature is enabled by default and can be used to complement format. The Rx data is valid on the rising edge of reduce the required pin count of the ASIC (refer to RxPGA RXCLK, as illustrated in the timing diagram shown in Figure 54. Control section for details). The RXSYNC signal is used to indicate to which word a nibble belongs. While RXSYNC is low, the first nibble of every word is In either application, Tx and Rx data are transferred between transmitted as the most significant nibble. The second nibble of the ASIC and AD9865 in 6-bit (or 5-bit) nibbles at twice the that same word is transmitted on the following RXSYNC high internal input/output word rates of the Tx interpolation filter level as the least significant nibble. and ADC. Note that the TxDAC update rate must not be less Rev. A | Page 24 of 48 4493-0-009 4493-0-010 4493-0-011 AD9865 t For the AD9865, the most significant nibble defaults to 6 bits, DH RXCLK and the least significant nibble defaults to 4 bits. This can be changed so that the least significant nibble and most significant t Dv RXSYNC nibble have 5 bits each. To accomplish this, set the 5/5 nibble bit in Register 0x0C and Register 0x0D and use data pins Tx[5:1] Rx[5:0] Rx0LSB Rx1MSB Rx1LSB Rx2MSB Rx3LSB Rx3MSB and Rx[5:1]. Figure 54. Full-Duplex Rx Port Timing Figure 55 shows a possible digital interface between an ASIC and the AD9865. The AD9865 serves as the master generating To add flexibility to the full-duplex digital interface port, several the required clocks for the ASIC. This interface requires that the programming options are available in the SPI registers. These ASIC reserve 16 pins for the interface, assuming a 6-bit nibble options are listed in Table 14. The timing for the Tx[5:0] and/or width and the use of the Tx port for RxPGA gain control. Note Rx[5:0] ports can be independently changed by selecting either that the ASIC pin allocation can be reduced by 3, if a 5-bit the rising or falling clock edge as the sampling/validating edge nibble width is used and the gain (or gain strobe) of the RxPGA of the clock. Inverting RXCLK (via Bit 1 or Register 0x05) is controlled via the SPI port. affects both the Rx and Tx interface, because they both use RXCLK. AD9865/AD9866 DIGITAL ASIC 6 TO OPTIONAL GAIN RxPGA Table 14. SPI Registers for Full-Duplex Interface Address (Hex) Bit Description Tx[5:0] 10/12 TO 0x05 (2) OSCIN to RXCLK Tx Data[5:0] Tx DIGITAL FILTER (1) Invert RXCLK (0) Disable RXCLK Rx[5:0] 10/12 FROM 0x0B (2) Rx gain on Tx port Rx Data[5:0] RxADC 0x0C (4) Invert TXSYNC (3) Tx 5/5 nibble RX_SYNC RXSYNC (2) LS nibble first TX_SYNC TXSYNC (1) TXCLK negative edge RXCLK CLKIN (0) Twos complement CLKOUT1 0x0D (5) Rx port three-state CLKOUT2 (4) Invert RXSYNC OSCIN (3) Rx 5/5 nibble FROM (2) LS nibble first CRYSTAL (1) RXCLK negative edge OR MASTER CLK (0) Twos complement Figure 55. Example of a Full-Duplex Digital Interface with Optional RxPGA Gain Control via Tx[5:0] 0x0E (7) Low drive strength RxPGA CONTROL The default Tx and Rx data input formats are twos complement, The AD9865 contains a digital PGA in the Rx path that is used but can be changed to straight binary. The default TXSYNC and to extend the dynamic range. The RxPGA can be programmed RXSYNC settings can be changed such that the first nibble of over −12 dB to +48 dB with 1 dB resolution using a 6-bit word, the word appears while TXSYNC, RXSYNC, or both are high. and with a 0 dB setting corresponding to a 2 V p-p input signal. Also, the least significant nibble can be selected as the first The 6-bit word is fed into a LUT that is used to distribute the nibble of the word (LS nibble first). The output driver strength desired gain over three amplification stages within the Rx path. can also be reduced for lower data rate applications. Upon power-up, the RxPGA gain register is set to its minimum gain of −12 dB. The RxPGA gain mapping is shown in Figure 56. Table 15 lists the SPI registers pertaining to the RxPGA. Rev. A | Page 25 of 48 4493-0-012 MUX DEMUX 4493-0-013 AD9865 48 t SU 42 RXCLK 36 t HD Tx SYNC 30 24 Tx [5:0] GAIN 18 12 GAIN 6 Figure 57. Updating RxPGA via Tx[5:0] in Full-Duplex Mode 0 Updating the RxPGA (or TxPGA) via the PGA[5:0] port is an –6 3 option for both the half-duplex and full-duplex interface. The –12 PGA port consists of an input buffer that passes the 6-bit data 0 612 18 24 30 36 42 48 54 60 66 6-BIT DIGITAL WORD-DECIMAL EQUIVALENT appearing at its input directly to the RxPGA (or TxPGA) gain register with no gating signal required. Bit 5 or Bit 6 of Figure 56. Digital Gain Mapping of RxPGA Register 0x0B is used to select whether the data updates the RxPGA or TxPGA gain register. In applications that switch Table 15. SPI Registers RxPGA Control between RxPGA and TxPGA gain control via PGA[5:0], be Address careful that the RxPGA (or TxPGA) is not inadvertently loaded (Hex) Bit Description with the wrong data during a transition. In the case of an 0x09 (6) Enable RxPGA update via SPI RxPGA to TxPGA transition, first deselect the RxPGA gain (5:0) RxPGA gain code register, update the PGA[5:0] port with the desired TxPGA gain 0x0B (6) Select TxPGA via PGA[5:0] setting, and then select the TxPGA gain register. (5) Select RxPGA via PGA[5:0] (3) Enable software GAIN strobe – Full-duplex The RxPGA also offers an alternative 3-bit word gain mapping 4 (2) Enable RxPGA update via Tx[5:0] – Full-duplex option that provides a −12 dB to +36 dB span in 8 dB increments (1) 3-bit RxPGA gain mapping – Half-duplex as shown in Table 16. The 3-bit word is directed to PGA[5:3] with PGA[5] being the MSB. This feature is backward-compatible with the AD9975 MxFE and allows direct interfacing to the The RxPGA gain register can be updated via the Tx[5:0] port, the PGA[5:0] port, or the SPI port. The first two methods allow CX11647 or INT5130 HomePlug 1.0 PHYs. fast updates of the RxPGA gain register and should be considered for digital AGC functions requiring a fast closed- Table 16. PGA Timing for AD9975 Backward-Compatible loop response. The SPI port allows direct update and readback Mode of the RxPGA gain register via Register 0x09 with an update Digital Gain Setting rate limited to 1.6 MSPS (with SCLK = 32 MHz). Note that Bit 6 PGA[5:3] Decimal Gain (dB) of Register 0x09 must be set for a read or write operation. 000 0 −12 001 1 −12 Updating the RxPGA via the Tx[5:0] port is an option only in 010 2 −4 1 2 full-duplex mode . In this case, a high level on the GAIN pin, 011 3 4 with TXSYNC low, programs the PGA setting on either the 100 4 12 rising edge or falling edge of RXCLK, as shown in Figure 57. 101 5 20 The GAIN pin must be held high, TXSYNC must be held low, 110 6 28 and GAIN data must be stable for one or more clock cycles to 111 7 36 update the RxPGA gain setting. A low level on the GAIN pin enables data to be fed to the digital interpolation filter. This interface should be considered when upgrading existing designs from the AD9875/AD9876 MxFE products or half-duplex applications trying to minimize an 1 Default setting for full-duplex mode (MODE = 1). ASIC’s pin count. 2 The GAIN strobe can also be set in software via Reg. 0x0B, Bit 3 for continuous updating. This eliminates the requirement for external GAIN signal, reducing the ASIC pin count by 1. 3 Default setting for half-duplex mode (MODE = 0). 4 Default setting for MODE = 0 and CONFIG =1. Rev. A | Page 26 of 48 GAIN (dB) 4493-0-014 4493-0-015 AD9865 TXPGA CONTROL The TxPGA register can be updated via the PGA[5:0] port or SPI port. The first method should be considered for fast updates The AD9865 also contains a digital PGA in the Tx path distri- of the TxPGA register. Its operation is similar to the description buted between the TxDAC and IAMP. The TxPGA is used to in the RxPGA Control section. The SPI port allows direct up- control the peak current from the TxDAC and IAMP over a date and readback of the TxPGA register via Register 0x0A with 7.5 dB and 19.5 dB span, respectively, with 0.5 dB resolution. an update rate limited to 1.6 MSPS (SCLK = 32 MHz). Bit 6 of A 6-bit word is used to set the TxPGA attenuation according to Register 0x0A must be set for a read or write operation. the mapping shown in Figure 58. The TxDAC gain mapping is applicable only when Bit 0 of Register 0x0E is set, and only the Table 17 lists the SPI registers pertaining to the TxPGA. The four LSBs of the 6-bit gain word are relevant. TxPGA control register default setting is for minimum 0 attenuation (0 dBFS) with the PGA[5:0] port disabled for Tx –1 gain control. –2 –3 –4 –5 Table 17. SPI Registers TxPGA Control –6 –7 Address (Hex) Bit Description –8 –9 TxDACs IOUTP OUTPUT 0x0A (6) Enable TxPGA update via SPI HAS 7.5dB RANGE –10 –11 (5:0) TxPGA gain code –12 –13 0x0B (6) Select TxPGA via PGA[5:0] –14 (5) Select RxPGA via PGA[5:0] –15 IAMPs IOUTN AND IOUTG –16 0x0E (0) TxDAC output (IAMP disabled) OUTPUTS HAS 19.5dB RANGE –17 –18 –19 –20 0 8 16 24 32 40 48 56 64 6-BIT DIGITAL CODE (Decimal Equivalent) Figure 58. Digital Gain Mapping of TxPGA Rev. A | Page 27 of 48 Tx ATTENUATION (dBFS) 04493-0-063 AD9865 TRANSMIT PATH The AD9865 (or AD9866) transmit path consists of a selectable The pipeline delays of the 2× and 4× filter responses are 21.5 digital 2×/4× interpolation filter, a 10-bit or 12-bit TxDAC, and and 24 clock cycles, respectively, relative to fDATA. The filter delay a current-output amplifier (IAMP) as shown in Figure 59. Note is also taken into consideration for applications configured for a that the additional two bits of resolution offered by the AD9866 half-duplex interface with the half-duplex power-down mode result in a 10 dB to 12 dB reduction in the pass-band noise enabled. This feature allows the user to set a programmable floor. The digital interpolation filter relaxes the Tx analog delay that powers down the TxDAC and IAMP only after the filtering requirements by simultaneously reducing the images last Tx input sample has propagated through the digital filter. from the DAC reconstruction process while increasing the See the Power Control and Dissipation section for more details. analog filter’s transition band. The digital interpolation filter 2.5 10 WIDE BAND can also be bypassed, resulting in lower digital current 2.0 0 consumption. –10 1.5 1.0 –20 0.5 –30 IOUT_G+ PASS BAND ADIO[11:6]/ –40 0 10 2-4X IOUT_N+ TxDAC IAMP Tx[5:0] IOUT_N– –0.5 IOUT_G– –50 –1.0dB @ 0.441 f DATA 0 TO –12dB 0 TO –7.5dB ADIO[11:6]/ –1.0 –60 Rx[5:0] AD9865/AD9866 –70 –1.5 TXEN/SYNC TXCLK –80 –2.0 –2.5 –90 Figure 59. Functional Block Diagram of Tx Path 0 0.25 0.50 0.75 1.00 1.25 1.75 2.00 1.50 NORMALIZED FREQUENCY (Relative to f ) DATA DIGITAL INTERPOLATION FILTERS Figure 60. Frequency Response of 2× Interpolation Filter The input data from the Tx port can be fed into a selectable (Normalized to fDATA) 2×/4× interpolation filter or directly into the TxDAC (for a half- 10 2.5 WIDE BAND duplex only). The interpolation factor for the digital filter is set 2.0 0 via SPI Register 0x0C with the settings shown in Table 18. The –10 1.5 maximum input word rate, fDATA, into the interpolation filter is –20 1.0 80 MSPS; the maximum DAC update rate is 200 MSPS. There- fore, applications with input word rates at or below 50 MSPS 0.5 –30 PASS BAND can benefit from 4× interpolation, while applications with input 0 –40 word rates between 50 MSPS and 80 MSPS can benefit from –1.0dB @ 0.45 f –50 DATA –0.5 2× interpolation. –1.0 –60 –1.5 –70 Table 18. Interpolation Factor Set via SPI Register 0x0C –80 –2.0 Bits [7:6] Interpolation Factor –2.5 00 4 –90 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 01 2 NORMALIZED FREQUENCY (Relative to f ) DATA 10 1 (half-duplex only) Figure 61. Frequency Response of 4× Interpolation Filter 11 Do not use (Normalized to f ) DATA The interpolation filter consists of two cascaded half-band filter TxDAC AND IAMP ARCHITECTURE stages with each stage providing 2× interpolation. The first The Tx path contains a TxDAC with a current amplifier, IAMP. stage filter consists of 43 taps. The second stage filter, operating The TxDAC reconstructs the output of the interpolation filter at the higher data rate, consists of 11 taps. The normalized and sources a differential current output that can be directed to wideband and pass-band filter responses (relative f ) for the DATA an external load or fed into the IAMP for further amplification. 2× and 4× low-pass interpolation filters are shown in Figure 60 The TxDAC’s and IAMPS’s peak current outputs are digitally and Figure 61, respectively. These responses also include the programmable over a 0 to −7.5 dB and 0 to −19.5 dB range, inherent sinc(x) from the TxDAC reconstruction process and respectively, in 0.5 dB increments. Note that this assumes can be used to estimate any post analog filtering requirements. default register settings for Register 0x10 and Register 0x11. Rev. A | Page 28 of 48 IOUT_P+ IOUT_P– 4493-0-017 WIDE BAND RESPONSE (dB) WIDE BAND RESPONSE (dB) 4493-0-019 PASS BAND RESPONSE (dB) 4493-0-018 PASS BAND RESPONSE (dB) AD9865 clearing Bit 0 of Register 0x0E. As a result, the IOUTP pins Applications demanding the highest spectral performance must remain completely open, if the IAMP is to be used. The and/or lowest power consumption can use the TxDAC output IAMP contains two sets of current mirrors that are used to directly. The TxDAC is capable of delivering a peak signal replicate the TxDAC’s current output with a selectable gain. The power-up to 10 dBm while maintaining respectable linearity first set of current mirrors is designated as the primary path, performance, as shown in Figure 27 through Figure 38. For providing a gain factor of N that is programmable from 0 to 4 in power-sensitive applications requiring the highest Tx power steps of 1 via Bits 2:0 of Register 0x10 with a default setting of efficiency, the TxDAC’s full-scale current output can be reduced N = 4. Bit 7 of this register must be set to overwrite the default to as low as 2 mA, and its load resistors sized to provide a settings of this register. This differential path exhibits the best suitable voltage swing that can be amplified by a low-power op- linearity performance (see Figure 42) and is available at the amp-based driver. IOUTN+ and IOUTN− pins. The maximum peak current per Most applications requiring higher peak signal powers (up to output is 100 mA and occurs when the TxDAC’s standing 23 dBm) should consider using the IAMP. The IAMP can be current, I, is set for 12.5 mA (IOUTFS = 25 mA). configured as a current source for loads having a well defined The second set of current mirrors is designated as the secon- impedance (50 Ω or 75 Ω systems), or a voltage source (with the dary path providing a gain factor of G that is programmable addition of a pair of npn transistors) for poorly defined loads from 0 to 36 via Bits 6:4 of Register 0x10 and Bits 6:0 of Register having varying impedance (such as power lines). 0x11 with a default setting of G = 12. This differential path is Figure 62 shows the equivalent schematic of the TxDAC and intended to be used in the voltage mode configuration to bias IAMP. The TxDAC provides a differential current output the external npn transistors, because it exhibits degraded appearing at IOUTP+ and IOUTP−. It can be modeled as a linearity performance (see Figure 43) relative to the primary differential current source generating a signal-dependent ac path. It is capable of sinking up to 180 mA of peak current into current, when ∆IS has a peak current of I along with two dc either its IOUTG+ or IOUTG− pins. The secondary path current sources, sourcing a standing current equal to I. The full- actually consists of three gain stages (G1, G2, and G3), which scale output current, IOUTFS, is equal to the sum of these are individually programmable as shown in Table 19. While standing current sources (IOUTFS = 2 × I). many permutations may exist to provide a fixed gain of G, the linearity performance of a secondary path remains relatively independent of the various individual gain settings that are possible to achieve a particular overall gain factor. TxDAC Both sets of mirrors sink current, because they originate from I I ±∆I NMOS devices. Therefore, each output pin requires a dc current S REFADJ path to a positive supply. Although the voltage output of each REFIO R 0.1µF SET output pin can swing between 0.5 V and 7 V, optimum ac per- I I formance is typically achieved by limiting the ac voltage swing OFF2 OFF2 I I OFF1 OFF1 I + ∆I IOUTP+ with a dc bias voltage set between 4 to 5 V. Lastly, both the I– ∆I IOUTP– standing current, I, and the ac current, ∆IS, from the TxDAC are xN xN xG xG amplified by the gain factor (N and G) with the total standing current drawn from the positive supply being equal to IAMP 2 × (N = G) × I Figure 62. Equivalent Schematic of TxDAC and IAMP Programmable current sources I and I via Register 0x12 OFF1 OFF2 The value of I is determined by the RSET value at the REFADJ can be used to improve the primary and secondary path pin along with the Tx path’s digital attenuation setting. With mirrors’ linearity performance under certain conditions by 0 dB attenuation, the value of I is increasing their signal-to-standing current ratio. This feature provides a marginal improvement in distortion performance I = 16 × (1.23/RSET) (1) under large signal conditions when the peak ac current of the For example, an R value of 1.96 kΩ results in I equal to reconstructed waveform frequently approaches the dc standing SET 10.0 mA with IOUTFS equal to 20.0 mA. Note that the REFIO current within the TxDAC (0 to −1 dBFS sine wave) causing the pin provides a nominal band gap reference voltage of 1.23 V internal mirrors to turn off. However, the improvement in distortion performance diminishes as the crest factor (peak-to- and should be decoupled to analog ground via a 0.1 µF capacitor. rms ratio) of the ac signal increases. Most applications can disable these current sources (set to 0 mA via Register 0x12) to The differential current output of the TxDAC is always con- reduce the IAMP’s current consumption. nected to the IOUTP pins, but can be directed to the IAMP by Rev. A | Page 29 of 48 N × (I+∆I) IOUTN+ N × (I–∆I) IOUTN– G × (I+∆I) IOUTG+ G × (I–∆I) IOUTG– 4493-0-020 AD9865 1:1 Table 19. SPI Registers for TxDAC and IAMP Address (Hex) Bit Description R R S L 0.1µF R SET 0x0E (0) TxDAC output 0x10 (7) Enable current mirror gain settings IOUTN+ (6:4) Secondary path first stage gain of 0 to 4 with ∆ = 1 IOUTG+ (3) Not used IAMP (2:0) Primary path NMOS gain of 0 to 4 TxDAC with ∆ = 1 0 TO –7.5dB 0 TO –12dB 0x11 (7) Don’t care IOUTN– (6:4) Secondary path second stage gain of IOUTG– 0 to 1.5 with ∆ = 0.25 (3) Not used Figure 63. TxDAC Output Directly via Center-Tap Transformer (2:0) Secondary path third stage gain of 0 to 5 with ∆ = 1 The TxDAC is capable of delivering up to 10 dBm peak power 0x12 (6:4) IOFF2, secondary path standing to a load, R . To increase the peak power for a fixed standing L current current, one must increase V p-p across IOUTP+ and IOUTP− (2:0) IOFF1, primary path standing current by increasing one or more of the following parameters: RS, RL (if possible), and/or the turns ratio, N, of transformer. For exam- ple, the removal of RS and the use of a 2:1 impedance ratio Tx PROGRAMMABLE GAIN CONTROL transformer in the previous example results in 10 dBm of peak TxPGA functionality is also available to set the peak output power capabilities to the load. Note that increasing the power current from the TxDAC or IAMP. The TxDAC and IAMP are output capabilities of the TxDAC reduces the distortion per- digitally programmable via the PGA[5:0] port or SPI over a 0 dB formance due to the higher voltage swings seen at IOUTP+ and to −7.5 dB and 0 dB to −19.5 dB range, respectively, in 0.5 dB IOUTP−. See Figure 27 through Figure 38 for performance increments. plots on the TxDAC’s ac performance. Optimum distortion performance can typically be achieved by: The TxPGA can be considered as two cascaded attenuators with the TxDAC providing 7.5 dB range in 0.5 dB increments, and • Limiting the peak positive VIOUTP+ and VIOUTP to 0.8 V to − the IAMP providing 12 dB range in 6 dB increments. As a avoid onset of TxDAC’s output compression. (TxDAC’s result, the IAMP’s composite 19.5 dB span is valid only if voltage compliance is around 1.2 V.) Register 0x10 remains at its default setting of 0x44. Modifying • Limiting V p-p seen at IOUTP+ and IOUTP− to less this register setting corrupts the LUT and results in an invalid than 1.6 V. gain mapping. Applications demanding higher output voltage swings and TxDAC OUTPUT OPERATION power drive capabilities can benefit from using the IAMP. The differential current output of the TxDAC is available at the IOUTP+ and IOUTP− pins and the IAMP should be disabled IAMP CURRENT-MODE OPERATION by setting Bit 0 of Register 0x0E. Any load connected to these The IAMP can be configured for the current-mode operation as pins must be ground referenced to provide a dc path for the shown in Figure 64 for loads remaining relatively constant. In current sources. Figure 63 shows the outputs of the TxDAC this mode, the primary path mirrors should be used to deliver driving a doubly terminated 1:1 transformer with its center-tap the signal-dependent current to the load via a center-tapped tied to ground. The peak-to-peak voltage, V p-p, across RL (and transformer, because it provides the best linearity performance. IOUT+ to IOUT−) is equal to 2 × I × (R //R ). With I = 10 mA L S Because the mirrors exhibit a high output impedance, they can and R = R = 50 Ω, V p-p is equal to 0.5 V with 1 dBm of peak L S be easily back-terminated (if required). power being delivered to R and 1 dBm being dissipated in R . L S For peak signal currents (IOUTPK up to 50 mA), only the primary path mirror gain should be used for optimum distortion performance and power efficiency. The primary path’s gain should be set to 4, with the secondary path’s gain stages set to 0 (Register 0x10 = 0x84). The TxDAC’s standing current, I, can be set between 2.5 mA and 12.5 mA with the IOUTP outputs left open. The IOUTN outputs should be connected to the transformer, with the IOUTG (and IOUTP) Rev. A | Page 30 of 48 REFIO REFADJ IOUT_P+ IOUT_P– 4493-0-021 AD9865 outputs left open for optimum linearity performance. The IAMP VOLTAGE-MODE OPERATION 1 transformer should be specified to handle the dc standing The voltage-mode configuration is shown in Figure 65. This current, I , drawn by the IAMP. Also, because I remains BIAS BIAS configuration is suited for applications having a poorly defined signal independent, a series resistor (not shown) can be inserted load that can vary over a considerable range. A low impedance between AVDD and the transformer’s center-tap to reduce the voltage driver can be realized with the addition of two external IAMP’s common-mode voltage, VCM, and reduce the power RF bipolar npn transistors (Phillips PBR951) and resistors. In dissipation on the IC. The VCM bias should not exceed 5.0 V and this configuration, the current mirrors in the primary path the power dissipated in the IAMP alone is as follows: (IOUTN outputs) feed into scaling resistors, R, generating a P = 2 × (N + G) × I × V (2) differential voltage into the bases of the npn transistors. These IAMP CM transistors are configured as source followers with the secon- dary path current mirrors appearing at IOUTG+ and IOUTG− providing a signal-dependent bias current. Note that the 0.1µF AVDD R SET IOUTP outputs must remain open for proper operation. 0.1µF I = 2 × (N+G) × 1 BIAS IOUTN+ 0.1µF R SET AVDD IOUTG+ T:1 DUAL NPN R R PHILLIPS PBR951 IOUTN+ R IAMP TxDAC L R 0.1µF IOUT S PK IOUTG+ 0 TO –7.5dB 0 TO –12dB IOUT IOUTN– PK TxDAC IAMP TO LOAD AVDD IOUTG– 0 TO –7.5dB 0 TO –12dB IOUTN– IOUT = (N+G) × 1 PK IOUTG– 2 2 R P_OUT = (IOUT ) × T × R S 0.1µF PK PK L Figure 64. Current-Mode Operation Figure 65. Voltage-Mode Operation 1 A step-down transformer with a turn ratio, T, can be used to The peak differential voltage signal developed across the npn’s increase the output power, P_OUT, delivered to the load. This bases is as follows: , to be reflected back to the IAMP’s causes the output load, RL 2 differential output by T , resulting in a larger differential voltage VOUT = R × (N × I) (4) PK swing seen at the IAMP’s output. For example, the IAMP can deliver 24 dBm of peak power to a 50 Ω load, if a 1.41:1 step- where: down transformer is used. This results in 5 V p-p voltage swings N is the gain setting of the primary mirror. appearing at IOUTN+ and IOUTN− pins. Figure 42 shows how the third order intercept point, OIP3, of the IAMP varies as a I is the standing current of the TxDAC defined in Equation 1. function of common-mode voltage over a 2.5 MHz to 20.0 MHz span with a 2-tone signal having a peak power of approximately The common-mode bias voltage seen at IOUTN+ and IOUTN− 24 dBm with IOUTPK = 50 mA. is approximately AVDD − VOUT , while the common-mode PK voltage seen at IOUTG+ and IOUTG− is approximately the For applications requiring an IOUTPK exceeding 50 mA, set the npn’s V drop below this level (AVDD − VOUT − 0.65). In BE PK secondary’s path to deliver the additional current to the load. the voltage-mode configuration, the total power dissipated IOUTG+ and IOUTN+ should be shorted as well as IOUTG− within the IAMP is as follows : and IOUTN−. If IOUT represents the peak current to be PK delivered to the load, then the current gain in the secondary PIAMP = 2 × I × {(AVDD − VOUTPK) × N path, G, can be set by the following equation: + (AVDD − VOUTPK − 0.65) × G} (5) G = IOUTPK/12.5 − 4 (3) The emitters of the npn transistors are ac-coupled to the trans- 1 former via a 0.1 µF blocking capacitor and series resistor of 1 Ω The linearity performance becomes limited by the secondary to 2 Ω. Note that protection diodes are not shown for clarity mirror path’s distortion. purposes, but should be considered if interfacing to a power or phone line. The amount of standing and signal-dependent current used to bias the npn transistors depends on the peak current, IOUTPK, required by the load. If the load is variable, determine the worst case, IOUT , and add 3 mA of margin to ensure that the npn PK 1 The B6080 and BX6090 transformers from Pulse Engineering are worthy of transistors remain in the active region during peak load consideration for current and voltage modes. Rev. A | Page 31 of 48 REFIO REFADJ IOUT_P+ IOUT_P– 4493-0-022 REFIO REFADJ IOUT_P+ IOUT_P– 4493-0-023 AD9865 currents. The gain of the secondary path, G, and the TxDAC’s 100 standing current, I, can be set using the following equation: 90 IOUT + 3 mA = G × I (6) 80 PK 70 The voltage output driver exhibits a high output impedance if 60 the bias currents for the npn transistors are removed. This IAMPN OUTPUT feature is advantageous in half-duplex applications (for 50 example, power lines) in which the Tx output driver must go 40 into a high impedance state while in Rx mode. If the AD9865 is TxDACs AVDD 30 configured for the half-duplex mode (MODE = 0), the IAMP, TxDAC, and interpolation filter are automatically powered 20 down after a Tx burst (via TXEN), thus placing the Tx driver 10 12 345 678 9 10 11 12 13 into a high impedance state while reducing its power I (mA) consumption. Figure 66. Current Consumption of TxDAC and IAMP in Current-Mode IAMP CURRENT CONSUMPTION CONSIDERATIONS Operation with IOUTN Only (Default IAMP Settings) 150 The Tx path’s analog current consumption is an important 140 consideration when determining its contribution to the overall 130 on-chip power dissipation. This is especially the case in full- IOUTG OUTPUT 120 duplex applications, where the power dissipation can exceed the 110 maximum limit of 1.66 W, if the IAMP’s IOUT is set to high. PK 100 The analog current consumption includes the TxDAC’s analog 90 80 supply (Pin 43) along with the standing current from the IAMP’s 70 outputs. Equation 2 and Equation 5 can be used to calculate the 60 power dissipated in the IAMP for the current and voltage mode 50 TxDAC AVDD configuration. Figure 66 shows the current consumption for the 40 TxDAC and IAMP as a function of the TxDAC’s standing current, 30 IOUTN OUTPUT 20 I, when only the IOUTN outputs are used. Figure 67 shows the 10 current consumption for the TxDAC and IAMP as a function of 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 I (mA) the TxDAC’s standing current, I, when the IOUTN and IOUTG outputs are used. Both figures are with the default current mirror Figure 67. Current Consumption of TxDAC and IAMP in Current-Mode Operation with IOUTN Only (Default IAMP Settings) gain settings of N = 4 and G = 12. Rev. A | Page 32 of 48 I (mA) I (mA) SUPPLY SUPPLY 04493-0-065 04493-0-064 AD9865 RECEIVE PATH does not get amplified with high RxPGA gain settings, The receive path block diagram for the AD9865 (or AD9866) is potentially exceeding the ADC input range. shown in Figure 68. The receive signal path consists of a 3-stage RxPGA, a 3-pole programmable LPF, and a 10-bit (or 12-bit) To limit the RxPGA’s self-induced input offset, an offset ADC. Note that the additional two bits of resolution offered by cancellation loop is included. This cancellation loop is auto- the AD9866 result in a 3 dB to 5 dB lower noise floor depending matically performed upon power-up and can also be initiated on the RxPGA gain setting and LPF cutoff frequency. Also working via SPI. During calibration, the RxPGA’s first stage is internally in conjunction with the receive path is an offset correction circuit. shorted, and each gain stage set to a high gain setting. A digital These blocks are discussed in detail in the following sections. servo loop slaves a calibration DAC, which forces the Rx input Note that the power consumption of the RxPGA can be modified offset to be within ±32 LSB for this particular high gain setting. via Register 0x13 as discussed in the Power Control and Although the offset varies for other gain settings, the offset is Dissipation section. typically limited to ±5% of the ADC’s 2 V input span. Note that the offset cancellation circuitry is intended to reduce the voltage ADIO[11:6]/ offset attributed to only the RxPGA’s input stage, not any dc Tx[5:0] CLK CLKOUT_1 SYN. offsets attributed to an external source. CLKOUT_2 M 2 CLK OSCIN ADIO[11:6]/ MULTIPLIER XTAL Rx[5:0] The gain of the RxPGA should be set to minimize clipping of 10/12 the ADC while utilizing most of its dynamic range. The maxi- RX+ RXEN/SYNC ADC 2-POLE 1-POLE SPGA LPF LPF RXCLK 80MSPS RX– mum peak-to-peak differential voltage that does not result in 0 TO 6dB –6 TO 18dB –6 TO 24dB clipping of the ADC is shown in Figure 69. While the graph ∆ = 1dB ∆ = 6dB ∆ = 6dB suggests that maximum input signal for a gain setting of −12 dB GAIN 6 MAPPING PGA[5:0] is 8.0 V p-p, the maximum input voltage into the PGA should LUT 4 REGISTER be limited to less than 6 V p-p to prevent turning on ESD protec- SPORT AD9865/AD9866 CONTROL tion diodes. For applications having higher maximum input signals, consider adding an external resistive attenuator network. Figure 68. Functional Block Diagram of Rx Path While the input sensitivity of the Rx path is degraded by the RX PROGRAMMABLE GAIN AMPLIFIER amount of attenuation on a dB-to-dB basis, the low noise characteristics of the RxPGA provide some design margin such The RxPGA has a digitally programmable gain range from that the external line noise remains the dominant source. −12 dB to +48 dB with 1 dB resolution via a 6-bit word. Its purpose is to extend the dynamic range of the Rx path such that 8.0000 the input of the ADC is presented with a signal that scales 4.0000 within its fixed 2 V input span. There are multiple ways of 2.0000 setting the RxPGA’s gain as discussed in the RxPGA Control 1.0000 section, as well as an alternative 3-bit gain mapping having a range of −12 dB to +36 dB with 8 dB resolution. 0.5000 0.2500 The RxPGA is comprised of two sections: a continuous time 0.1250 PGA (CPGA) for course gain and a switched capacitor PGA (SPGA) for fine gain resolution. The CPGA consists of two 0.0625 cascaded gain stages providing a gain range from −12 dB to 0.0312 +42 dB with 6 dB resolution. The first stage features a low noise 0.0156 preamplifier (< 3.0 nV/rtHz), thereby eliminating the need for 0.0100 –12 –6 0 6 12 182430 3642 48 an external preamplifier. The SPGA provides a gain range from GAIN (dB) 0 dB to 6 dB with 1 dB resolution. A look-up table (LUT) is Figure 69. Maximum Peak-to-Peak Input vs. RxPGA Gain Setting used to select the appropriate gain setting for each stage. that Does Not Result in ADC Clipping The nominal differential input impedance of the RxPGA input appearing at the device RX+ and RX− input pins is 400 Ω//4 pF (±20%) and remains relatively independent of gain setting. The PGA input is self-biased at a 1.3 V common-mode level allowing maximum input voltage swings of ±1.5 V at RX+ and RX−. AC coupling the input signal to this stage via coupling capacitors (0.1 µF) is recommended to ensure that any external dc offset Rev. A | Page 33 of 48 4493-0-024 FULL-SCALE PEAK-TO-PEAK INPUT SPAN (V) 04493-0-031 AD9865 0.25 1.30 LOW-PASS FILTER 0 1.25 NORMALIZED GAIN RESPONSE The low-pass filter (LPF) provides a third order response with a –0.25 1.20 –0.50 1.15 cutoff frequency that is typically programmable over a 15 MHz –0.75 1.10 to 35 MHz span. Figure 68 shows that the first real pole is im- –1.00 1.05 plemented within the first CPGA gain stage, and the complex –1.25 1.00 pole pair is implemented in the second CPGA gain stage. –1.50 0.95 Capacitor arrays are used to vary the different R-C time con- –1.75 0.90 stants within these two stages in a manner that changes the –2.00 0.85 cutoff frequency while preserving the normalized frequency –2.25 0.80 NORMALIZED GROUP DELAY response. Because absolute resistor and capacitor values are –2.50 0.75 process-dependent, a calibration routine lasting less than 100 µs –2.75 0.70 automatically occurs each time the target cutoff frequency –3.00 0.65 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 register (Register 0x08) is updated, ensuring a repeatable cutoff NORMALIZED FREQUENCY frequency from device to device. Figure 71. LPF’s Normalized Pass-Band Gain and Group Delay Responses Although the default setting specifies that the LPF be active, it The −3 dB cut-off frequency, f , is programmable by writing −3 dB can also be bypassed providing a nominal f−3 dB of 55 MHz. an 8-bit word, referred to as the target, to Register 0x08. The Table 20 shows the SPI registers pertaining to the LPF. cutoff frequency is a function of the ADC sample rate, f , and ADC to a lesser extent, the RxPGA gain setting (in dB). Figure 72 Table 20. SPI Registers for Rx Low-Pass Filter shows how the frequency response, f−3 dB, varies as a function of Address (Hex) Bit Description the RxPGA gain setting. 0x07 (0) Enable Rx LPF 3 0x08 (7:0) Target value –6dB GAIN 0dB GAIN 0 +6dB GAIN The normalized wideband gain response is shown in Figure 70. +18dB GAIN +30dB GAIN The normalized pass-band gain and group delay responses are –3 +42dB GAIN shown in Figure 71. The normalized cutoff frequency, f , −3 dB –6 results in −3 dB attenuation. Also, the actual group delay time (GDT) response can be calculated given a programmed cutoff –9 frequency using the following equation: –12 Actual GDT = Normalized GDT/(2.45 × f−3dB) (7) –15 5 0 –18 01 50 15 20 25 30 35 4550 40 INPUT FREQUENCY (MHz) –5 Figure 72. Effects of RxPGA Gain on LPF Frequency Response –10 (f = 32 MHz (@ 0 dB and f = 80 MSPS) −3 dB ADC –15 1 The following formula can be used to estimate f for a −3 dB RxPGA gain setting of 0 dB: –20 –25 f = (128/target) × (f /80) ×(f /30 + 23.83) f (8) −3dB_0dB ADC ADC –30 Figure 73 compares the measured and calculated f−3 dB using this formula. –35 0 0.5 1.0 1.5 2.0 2.5 3.0 FREQUENCY 1 Empirically derived for a f−3 dB range of 15 MHz to 35 MHz and fADC of 40 MSPS Figure 70. LPF’s Normalized Wideband Gain Response to 80 MSPS with an RxPGA = 0 dB. Rev. A | Page 34 of 48 GAIN (dB) 4493-0-025 GAIN (dB) FUNDAMENTAL (dB) 4493-0-027 NORMALIZED GROUP DELAY TIME RESPONSE (GDT) 4493-0-026 AD9865 35 ANALOG-TO-DIGITAL CONVERTER (ADC) 33 The AD9865 features a 10-bit analog-to-digital converter 31 (ADC) capable of up to 80 MSPS. Referring to Figure 68, the 29 ADC is driven by the SPGA stage, which performs both the 27 sample-and-hold and the fine gain adjust functions. A buffer 80 MSPS MEASURED amplifier (not shown) isolates the last CPGA gain stage from 25 the dynamic load presented by the SPGA stage. The full-scale 80 MSPS CALCULATED 23 input span of the ADC is 2 V p-p, and depending on the PGA 21 gain setting, the full-scale input span into the SPGA is 19 adjustable from 1 V to 2 V in 1 dB increments. 50 MSPS MEASURED 17 50 MSPS CALCULATED A pipelined multistage ADC architecture is used to achieve high 15 48 64 80 96 112 128 144 160 176 192 208 224 sample rates while consuming low power. The ADC distributes TARGET-DECIMAL EQUIVALENT the conversion over several smaller A/D subblocks, refining the conversion with progressively higher accuracy as it passes the Figure 73. Measured and Calculated f−3 dB vs. Target Value for fADC = 50 MSPS and 80 MSPS results from stage to stage on each clock edge. The ADC typi- cally performs best when driven internally by a 50% duty cycle The following scaling factor can be applied to the previous clock. This is especially the case when operating the ADC at formula to compensate for the RxPGA gain setting on f : −3 dB high sample rate (55 MSPS to 80 MSPS) and/or lower internal Scale Factor = 1 − (RxPGA in dB)/382 (9) bias levels, which adversely affect interstage settling time requirements. This scaling factor reduces the calculated f−3 dB as the RxPGA is increased. Applications that need to maintain a minimum cut- The ADC sampling clock path also includes a duty cycle off frequency, f−3 dB_MIN, for all RxPGA gain settings should first restorer circuit, which ensures that the ADC gets a near 50% determine the scaling factor for the highest RxPGA gain setting duty cycle clock even when presented with a clock source with to be used. Next, the f should be divided by this scale −3 dB_MIN poor symmetry (35/65). This circuit should be enabled if the factor to normalize to the 0 dB RxPGA gain setting (f ). −3 dB_0 dB ADC sampling clock is a buffered version of the reference signal Equation 8 can then be used to calculate the target value. appearing at OSCIN (see the Clock Synthesizer section), and if this reference signal is derived from an oscillator or crystal The LPF frequency response shows a slight sensitivity to whose specified symmetry cannot be guaranteed to be within temperature, as shown in Figure 74. Applications sensitive to 45/55 (or 55/45). This circuit can remain disabled if the ADC temperature drift can recalibrate the LPF by rewriting the target sampling clock is derived from a divided down version of the value to Register 0x08. clock synthesizer’s VCO, because this clock is near 50%. 35 The ADC’s power consumption can be reduced by 25 mA, with minimal effect on its performance, by setting Bit 4 of Register 0x07. Alternative power bias settings are also available via 30 Register 0x13, as discussed in the Power Control and F ACTUAL 80MHz AND –40°C OUT Dissipation section. Lastly, the ADC can be completely powered down for half-duplex operation, further reducing the AD9865’s 25 F ACTUAL 80MHz AND +25°C OUT peak power consumption. F ACTUAL 80MHz AND +85°C OUT 20 15 96 112 128 144 160 176 192 208 240 224 TARGET-DECIMAL EQUIVALENT Figure 74. Temperature Drift of f−3 dB for fADC = 80 MSPS and RxPGA = 0 dB Rev. A | Page 35 of 48 FREQUENCY (MHz) FREQUENCY (MHz) 4493-0-029 4493-0-028 AD9865 Table 21. SPI Registers for Rx ADC REFT Address (Hex) Bit Description C3 0.1µF C2 TO 0x04 (5) Duty cycle restore circuit C1 10µF ADCs 0.1µF (4) ADC clock from PLL 0x07 (4) ADC low power mode C4 REFB 0.1µF 0x13 (2:0) ADC power bias adjust 1.0V AGC TIMING CONSIDERATIONS When implementing a digital AGC timing loop, it is important TOP to consider the Rx path latency and settling time of the Rx path VIEW in response to a change in gain setting. Figure 21 and Figure 24 show the RxPGA’s settling response to a 60 dB and 5 dB change C3 in gain setting when using the Tx[5:0] or PGA[5:0] port. While C1 the RxPGA settling time may also show a slight dependency on C4 C2 the LPF’s cut-off frequency, the ADC’s pipeline delay along with the ADIO bus interface presents a more significant delay. The Figure 75. ADC Reference and Decoupling amount of delay or latency is dependent on whether a half-or The ADC has an internal voltage reference and reference ampli- full-duplex is selected. An impulse response at the RxPGA’s fier as shown in Figure 75. The internal band gap reference input can be observed after 10.0 ADC clock cycles (1/fADC) in generates a stable 1 V reference level that is converted to a dif- the case of a half-duplex interface, and 10.5 ADC clock cycles in ferential 1 V reference centered about mid-supply (AVDD/2). the case of a full-duplex interface. This latency, along with the The outputs of the differential reference amplifier are available RxPGA settling time, should be considered to ensure stability of at the REFT and REFB pins and must be properly decoupled for the AGC loop. optimum performance. The REFT and REFB pins are conven- iently situated at the corners of the CSP package such that C1 (0603 type) can be placed directly across its pins. C3 and C4 can be placed underneath C1, and C2 (10 µF tantalum) can be placed furthest from the package. Rev. A | Page 36 of 48 04493-0-066 AD9865 CLOCK SYNTHESIZER (fDAC). The first option is the default setting and most desirable The AD9865 generates all its internal sampling clocks, as well as if fOSCIN is equal to the ADC sample rate, fADC. This option two user-programmable clock outputs appearing at CLKOUT1 typically results in the best jitter/phase noise performance for and CLKOUT2, from a single reference source as shown in the ADC sampling clock. The second option is suitable in cases Figure 76. The reference source can be either a fundamental where f is a factor of 2 or 4 less than the f . In this case, OSCIN ADC frequency or an overtone quartz crystal connected between the divider ratio, N, is chosen such that the divided down VCO OSCIN and XTAL with the parallel resonant load components output is equal to the ADC sample rate, as shown in the as specified by the crystal manufacturer. It can also be a TTL- following equation: level clock applied to OSCIN with XTAL left unconnected. N fADC = fDAC/2 (12) The data rate, fDATA, for the Tx and Rx data paths must always be equal. Therefore, the ADC’s sample rate, fADC, is always equal to where N = 0, 1, or 2. fDATA while the TxDAC update rate is a factor of 1, 2, or 4 of fDATA, depending on the interpolation factor selected. The data Figure 77 shows the degradation in phase noise performance rate refers to the word rate and should not be confused with the imparted onto the ADC’s sampling clock for different VCO nibble rate in full-duplex interface. output frequencies. In this case, a 25 MHz, 1 V p-p sine wave was used to drive OSCIN, and the PLL’s M and N factors were selected to provide an f of 50 MHz for VCO operating ADC TO ADC XTAL N ÷2 frequencies of 50, 100, and 200 MHz. The RxPGA input was XTAL M OSCIN 2 CLK driven with a near full-scale, 12.5 MHz input signal with a gain TO TxDAC MULTIPLIER C1 C2 setting of 0 dB. Operating the VCO at the highest possible CLKOUT2 L ÷2 frequency results in the best narrow and wideband phase noise CLKOUT1 characteristics. For comparison purposes, the clock source for R ÷2 the ADC was taken directly from OSCIN when driven by a 50 MHz square wave. Figure 76. Clock Oscillator and Synthesizer 0 DIRECT M The 2 CLK multiplier contains a PLL (with integrated loop –10 VCO = 50MHz VCO = 100MHz filter) and VCO capable of generating an output frequency that –20 VCO = 200MHz is a multiple of 1, 2, 4, or 8 of its input reference frequency, –30 f , appearing at OSCIN. The input frequency range of f OSCIN OSCIN –40 is between 20 MHz and 80 MHz, while the VCO can operate –50 over a 40 MHz to 200 MHz span. For the best phase noise/jitter –60 characteristics, it is advisable to operate the VCO with a fre- –70 quency between 100 MHz and 200 MHz. The VCO output –80 drives the TxDAC directly such that its update rate, f , is DAC –90 related to f by the following equation: OSCIN –100 M f = 2 × f (10) DAC OSCIN –110 2.5 4.5 6.5 8.5 10.5 12.5 14.5 16.5 18.5 20.5 22.5 FREQUENCY (MHz) where M = 0, 1, 2, or 3. Figure 77. Comparison of Phase Noise Performance when ADC Clock Source is Derived from Different VCO Output Frequencies M is the PLL’s multiplication factor set in Register 0x04. The value of M is determined by the Tx path’s word rate, fDATA, and The CLK synthesizer also has two clock outputs appearing at digital interpolation factor, F, as shown in the following CLKOUT1 and CLKOUT2. They are programmable via equation: Register 0x06. Both outputs can be inverted or disabled. The voltage levels appearing at these outputs are relative to DRVDD M = log (F × f /f) (11) 2 DATA OSCIN and remain active during a hardware or software reset. Table 22 Note: if the reference frequency appearing at OSCIN is chosen shows the SPI registers pertaining to the clock synthesizer. to be equal to the AD9865’s Tx and Rx path’s word rate, then M CLKOUT1 is a divided version of the VCO output and can be is simply equal to log2(F). R set to be a submultiple integer of f (f /2 , where R = 0, 1, 2, DAC DAC The clock source for the ADC can be selected in Register 0x04 or 3). Because this clock is actually derived from the same set of as a buffered version of the reference frequency appearing at dividers used within the PLL core, it is phase-locked to them OSCIN (default setting) or a divided version of the VCO output such that its phase relationship relative to the signal appearing Rev. A | Page 37 of 48 04493-0-030 dBFS 04493-0-067 AD9865 at OSCIN (or RXCLK) can be determined upon power up. Also, Table 22. SPI Registers for CLK Synthesizer this clock has near 50% duty cycle, because it is derived from Address (Hex) Bit Description the VCO. As a result, CLKOUT1 should be selected before 0x04 (4) ADC CLK from PLL CLKOUT2 as the primary source for system clock distribution. (3:2) PLL divide factor (P) (1:0) PLL multiplication factor (M) CLKOUT2 is a divided version of the reference frequency, fOSCIN, 0x06 (7:6) CLKOUT2 divide number L and can be set to be a submultiple integer of fOSCIN (fOSCIN/2 , (5) CLKOUT2 invert where L = 0, 1, or 2). With L set to 0, the output of CLKOUT2 is (4) CLKOUT2 disable a delayed version of the signal appearing at OSCIN, exhibiting (3:2) CLKOUT1 divide number the same duty cycle characteristics. With L set to 1 or 2, the (1) CLKOUT1 invert output of CLKOUT2 is a divided version of the OSCIN signal, (0) CLKOUT1 disable exhibiting a near 50% duty cycle, but without having a determi- nistic phase relationship relative to CLKOUT1 (or RXCLK). Rev. A | Page 38 of 48 AD9865 POWER CONTROL AND DISSIPATION POWER-DOWN HALF-DUPLEX POWER SAVINGS The AD9865 provides the ability to control the power-on state Significant power savings can be realized in applications having of various functional blocks. The state of the PWRDWN pin a half-duplex protocol allowing only the Rx or Tx path to be along with the contents of Register 0x01 and Register 0x02 operational at any instance. The power savings method depends allow two user-defined power settings that are pin selectable. on whether the AD9865 is configured for a full- or half-duplex 1 The default settings are such that Register 0x01 has all blocks interface. Functional blocks having fast power on/off times for powered on (all bits 0), while Register 0x02 has all blocks the Tx and Rx path are controlled by the following bits: powered down excluding the PLL such that the clock signal TxDAC/IAMP, TX Digital, ADC, and RxPGA. remains available at CLKOUT1 and CLKOUT2. When the In the case of a full-duplex digital interface (MODE = 1), one PWRDWN pin is low, the functional blocks corresponding to can set Register 0x01 to 0x60 and Register 0x02 to Register 0x05 the bits in Register 0x01 are powered down. When the (or vice versa) such that the AD9865’s Tx and Rx path are never PWRDWN is high, the functional blocks corresponding to the powered on simultaneously. The PWRDWN pin can then be bits in Register 0x02 are powered down. PWRDWN used to control which path is powered on, depending on the immediately affects the designated functional blocks with burst type. During a Tx burst, the Rx path’s PGA and ADC minimum digital delay. blocks can typically be powered down within 100 ns, while the Tx paths DAC, IAMP, and digital filter blocks are powered up Table 23. SPI Registers Associated with Power-Down and within 0.5 µs. For an Rx burst, the Tx path’s can be powered Half-Duplex Power Savings down within 100 ns, while the Rx circuitry is powered up Address (Hex) Bit Description Comments within 2 µs. 0x01 (7) PLL PWRDWN = 0. Setting the TXQUIET pin low allows it to be used with the full- (6) TxDAC/IAMP duplex interface to quickly power down the IAMP and disable Default setting is all (5) TX Digital functional blocks the interpolation filter. This is meant to maintain backward (4) REF powered on. compatibility with the AD9875/AD9876 MxFEs with the excep- (3) ADC CML tion that the TxDAC remains powered, if its IOUTP outputs are (2) ADC used. In most applications, the interpolation filter needs to be (1) PGA BIAS flushed with 0s before or after being powered down. This (0) RxPGA ensures that upon power-up, the TxDAC (and IAMP) have a 0x02 (7) PLL PWRDWN = 1. negligible differential dc offset, thus preventing spectral splatter (6) TxDAC/IAMP due to an impulse transient. Default setting is all (5) TX Digital functional blocks Applications using a half-duplex interface (MODE = 0) can (4) REF powered off benefit from an additional power savings feature made available (3) ADC CML excluding PLL. in Register 0x03. This register is effective only for a half-duplex (2) ADC interface. Besides providing power savings for half-duplex (1) PGA BIAS applications, this feature allows the AD9865 to be used in (0) RxPGA applications that need only its Rx (or Tx) path functionality 0x03 (7:3) Tx OFF Delay Half-duplex power through pin-strapping, making a serial port interface (SPI) savings. (2) Rx PWRDWN optional. This feature also allows the PWRDWN pin to retain via TXEN its default function as a master power control, as defined in (1) Enable Tx Table 10. PWRDWN (0) Enable Rx The default settings for Register 0x03 provide fast power control PWRDWN of the functional blocks in the Tx and Rx signal paths (outlined above) using the TXEN pin. The TxDAC still remains powered on in this mode, while the IAMP is powered down. Significant current savings are typically realized when the IAMP is powered down. 1 With MODE = 1 and CONFIG =1, Reg. 0x02 default settings are with all blocks For a Tx burst, the falling edge of TXEN is used to generate an powered off, with RXCLK providing a buffered version of the signal internal delayed signal for powering down the Tx circuitry. appearing at OSCIN. This setting results in the lowest power consumption Upon receipt of this signal, power-down of the Tx circuitry upon power-up, while still allowing AD9865 to generate the system clock via a crystal. Rev. A | Page 39 of 48 AD9865 occurs within 100 ns. The user-programmable delay for the Tx 55 path power-down is meant to match the pipeline delay of the 50 last Tx burst sample such that power-down of the TxDAC and 45 IAMP does not impact its transmission. A 5-bit field in Register 0x03 40 sets the delay from 0 to 31 TXCLK clock cycles, with the default being 31 (0.62 µs with fTXCLK = 50 MSPS). The digital interpolation 35 filter is automatically flushed with midscale samples prior to 30 power-down, if the clock signal into the TXCLK pin is present 25 for 33 additional clock cycles after TXEN returns low. For an Rx burst, the rising edge of TXEN is used to generate an internal 20 signal (with no delay) that powers up the Tx circuitry within 0.5 µs. 15 The Rx path power-on/power-off can be controlled by either 10 01 23 45 67 89 10 11 12 13 TXEN or RXEN by setting Bit 2 of Register 0x03. In the default I (mA) STANDING setting, the falling edge of TXEN powers up the Rx circuitry within 2 µs, while the rising edge of TXEN powers down the Rx Figure 78. Reduction in TxDAC’s Supply Current vs. Standing Current circuitry within 0.5 µs. If RXEN is selected as the control signal, then its rising edge powers up the Rx circuitry and the falling 65 edge powers it down. To disable the fast power-down of the Tx 60 and/or Rx circuitry, set Bit 1 and/or Bit 0 to 0. 4× INTERPOLATION 55 POWER REDUCTION OPTIONS 50 The power consumption of the AD9865 can be significantly 45 reduced from its default setting by optimizing the power 40 2× INTERPOLATION consumption versus performance of the various functional 35 blocks in the Tx and Rx signal path. On the Tx path, minimum 30 power consumption is realized when the TxDAC output is used 1× (HALF-DUPLEX ONLY) 25 directly and its standing current, I, is reduced to as low as 1 mA. 20 Although a slight degradation in THD performance results at reduced standing currents, it often remains adequate for most 15 20 30 40 50 60 70 80 applications, because the op amp driver typically limits the INPUT DATA RATE (MSPS) overall linearity performance of the Tx path. The load resistors Figure 79. Digital Supply Current Consumption vs. Input Data Rate used at the TxDAC outputs (IOUTP+ and IOUTP−) can be (DVDD = DRVDD =3.3 V and fOUT = fDATA/10) increased to generate an adequate differential voltage that can be further amplified via a power efficient op-amp-based driver Power consumption on the Rx path can be achieved by reduc- solution. Figure 78 shows how the supply current for the ing the bias levels of the various amplifiers contained within the TxDAC (Pin 43) is reduced from 55 mA to 14 mA as the RxPGA and ADC. As previously noted, the RxPGA consists of standing current is reduced from 12.5mA to 1.25 mA. Further two CPGA amplifiers and one SPGA amplifier. The bias levels Tx power savings can be achieved by bypassing or reducing the of each of these amplifiers along with the ADC can be con- interpolation factor of the digital filter as shown in Figure 79. trolled via Register 0x13, as shown in Table 24. The default setting for 0x13 is 0x00. Table 24. SPI Register for RxPGA and ADC Biasing Address (Hex) Bit Description 0x07 (4) ADC low power 0x13 (7:5) CPGA bias adjust (4:3) SPGA bias adjust (2:0) ADC power bias adjust Rev. A | Page 40 of 48 I (mA) IAVDD (mA) DVDD TxDAC 04493-0-069 04493-0-068 AD9865 210 Because the CPGA processes signals in the continuous time domain, its performance vs. bias setting remains mostly 205 independent of the sample rate. Table 25 shows how the typical 200 current consumption seen at AVDD (Pins 35 and 40) varies as a 01 function of Bits (7:5), while the remaining bits are maintained at 195 their default settings of 0. Only four of the possible settings 00 190 result in any reduction in current consumption relative to the default setting. Reducing the bias level typically results in a 185 degradation in the THD vs. frequency performance as shown in 10 180 Figure 80. This is due to a reduction of the amplifier’s unity gain 11 bandwidth, while the SNR performance remains relatively 175 unaffected. 170 20 30 40 50 60 70 80 Table 25. Analog Supply Current vs. CPGA Bias Settings at ADC SAMPLE RATE (MSPS) fADC = 65 MSPS Figure 81. AVDD Current vs. SPGA Bias Setting and Sample Rate Bit 7 Bit 6 Bit 5 ∆ mA 0 0 0 0 61 –54 0 0 1 −27 60 –56 0 1 0 −42 59 –58 0 1 1 −51 SNR-00 58 –60 1 0 0 −55 SNR-01 SNR-10 57 –62 1 0 1 27 SNR-11 1 1 0 69 56 –64 1 1 1 27 55 –66 54 –68 THD-00 THD-01 65.0 –20 53 –70 THD-10 SNR_RxPGA = 0dB THD-11 62.5 –25 52 –72 60.0 –30 51 –74 20 30 40 50 60 70 80 57.5 –35 SAMPLE RATE (MSPS) SNR_RxPGA = 36dB 55.0 –40 Figure 82. SNR and THD Performance vs. fADC and SPGA Bias Setting with RxPGA = 0 dB, fIN = 10 MHz, LPF set to 26 MHz, and AIN = −1 dBFS 52.5 –45 50.0 –50 The ADC is based on a pipeline architecture with each stage THD_RxPGA = 0dB 47.5 –55 consisting of a switched capacitor amplifier. Therefore, its per- 45.0 –60 formance vs. bias level is mostly dependent on the sample rate. 42.5 –65 Figure 83 shows how the typical current consumption seen at THD_RxPGA = 36dB AVDD (Pins 35 and 40) varies as a function of Bits (2:0) and 40.0 –70 000 001 010 011 100 sample rate, while the remaining bits are maintained at the CPGA BIAS SETTING-BITS (7:5) default setting of 0. Setting Bit 4 or Register 0x07 corresponds Figure 80. THD vs. fIN Performance and RxPGA Bias Settings to the 011 setting, and the settings of 101 and 111 result in (000,001,010,100 with RxPGA = 0 and +36 dB and AIN = −1 dBFS, higher current consumption. Figure 84 shows how the SNR and LPF set to 26 MHz, and fADC = 50 MSPS) THD performance are affected for a 10 MHz sine wave input The SPGA is implemented as a switched capacitor amplifier; for the lower power settings as the ADC sample rate is swept therefore, its performance vs. bias level is mostly dependent on from 20 MHz to 80 MHz. the sample rate. Figure 81 shows how the typical current consumption seen at AVDD (Pin 35 and Pin 40) varies as a function of Bits (4:3) and sample rate, while the remaining bits are maintained at the default setting of 0. Figure 82 shows how the SNR and THD performance is affected for a 10 MHz sine wave input as the ADC sample rate is swept from 20 MHz to 80 MHz. The SNR and THD performance remains relatively stable, suggesting that the SPGA bias can often be reduced from its de- fault setting without impacting the device’s overall performance. Rev. A | Page 41 of 48 SNR (dBFS) THD (dBc) 04493-0-091 SNR (dBc) I (mA) AVDD 04493-0-070 THD (dBc) 04493-0-092 AD9865 220 specification is based on the 64-pin LFSCP having a thermal 101 OR 111 o resistance, θ , of 24 C/W with its heat slug soldered. (The θ is JA JA 210 o 30.8 C/W, if the heat slug remains unsoldered.) If a particular 200 000 application’s maximum ambient temperature, TA, falls below 190 o 85 C, the maximum allowable power dissipation can be deter- 001 180 mined by the following equation: 010 170 PMAX = 1.66 + (85 − TA)/24 (13) 160 011 101 100 150 Assuming the IAMP’s common-mode bias voltage is operating off the same analog supply as the AD9865, the following equa- 140 tion can be used to calculate the maximum total current 130 consumption, I , of the IC: MAX 120 20 30 40 50 60 70 80 SAMPLE RATE (MSPS) IMAX = (PMAX − PIAMP)/3.47 (14) Figure 83. AVDD Current vs. ADC Bias Setting and Sample Rate With an ambient temperature of up to 85°C, IMAX is 478 mA. 61 –54 If the IAMP is operating off a different supply or in the voltage 60 –56 mode configuration, first calculate the power dissipated in the IAMP, P , using Equation 2 or Equation 5, and then 59 –58 IAMP THD-000 recalculate I , using Equation 14. MAX 58 –60 THD-001 THD-010 57 –62 THD-011 Figure 78, Figure 79, Figure 81, and Figure 83 can be used to THD-100 56 –64 calculate the current consumption of the Rx and Tx paths for a THD-101 given setting. 55 –66 54 –68 SNR-000 MODE SELECT UPON POWER-UP AND RESET SNR-001 53 –70 SNR-010 The AD9865 power-up state is determined by the logic levels SNR-011 52 –72 SNR-100 appearing at the MODE and CONFIG pins. The MODE pin is SNR-101 51 –74 used to select a half- or full-duplex interface by pin strapping it 20 30 40 50 60 70 80 low or high, respectively. The CONFIG pin is used in conjunc- SAMPLE RATE (MSPS) tion with the MODE pin to determine the default settings for Figure 84. SNR and THD Performance vs. fADC and ADC Bias Setting with the SPI registers as outlined in Table 10. RxPGA = 0 dB, fIN = 10 MHz, and AIN = −1 dBFS The intent of these particular default settings is to allow some A sine wave input is a standard and convenient method of applications to avoid using the SPI (disabled by pin-strapping analyzing the performance of a system. However, the amount of high), thereby reducing implementation costs. For SEN power reduction that is possible is application dependent, based example, setting MODE low and CONFIG high configures the on the nature of the input waveform (such as frequency content, AD9865 to be backward compatible with the AD9975, while peak-to-rms ratio), the minimum ADC sample, and the mini- setting MODE high and CONFIG low makes it backward mum acceptable level of performance. Thus, it is advisable that compatible with the AD9875. Other applications must use the power-sensitive applications optimize the power bias setting of SPI to configure the device. the Rx path using an input waveform that is representative of the application. A hardware (RESET pin) or software (Bit 5 of Register 0x00) reset can be used to place the AD9865 into a known state of POWER DISSIPATION operation as determined by the state of the MODE and The power dissipation of the AD9865 can become quite high in CONFIG pins. A dc offset calibration and filter tuning routine full-duplex applications in which the Tx and Rx paths are si- is also initiated upon a hardware reset, but not with a software multaneously operating with nominal power bias settings. In reset. Neither reset method flushes the digital interpolation fact, some applications that use the IAMP may need to either filters in the Tx path. Refer to the Half-Duplex Mode and Full- reduce its peak power capabilities or reduce the power con- Duplex Mode sections for information on flushing the digital sumption of the Rx path, so that the device’s maximum filters. allowable power consumption, P , is not exceeded. MAX A hardware reset can be triggered by pulsing the RESET pin low P is specified at 1.66 W to ensure that the die temperature MAX o o for a minimum of 50 ns. The SPI registers are instantly reset to does not exceed 125 C at an ambient temperature of 85 C. This their default settings upon RESET going low, while the dc offset Rev. A | Page 42 of 48 SNR (dBc) I (mA) AVDD 04493-0-071 THD (dBc) 04493-0-092 AD9865 calibration and filter tuning routine is initiated upon waveform) into the Rx input, and monitor the quality of the RESET reconstructed output from the TxDAC or IAMP to ensure a returning high. To ensure sufficient power-on time of the minimum level of performance. In this test, the user can various functional blocks, RESET returning high should occur exercise the RxPGA as well as validate the attenuation char- no less than 10 ms upon power-up. If a digital reset signal from acteristics of the RxLPF. Note that the RxPGA gain setting a microprocessor reset circuit (such as ADM1818) is not should be selected such that the input does not result in clipping available, a simple R-C network referenced to DVDD can be of the ADC. RESET used to hold low for approximately 10 ms upon power- up. Digital loop-back can be used to test the full-duplex digital interface of the AD9865. In this test, data appearing on the ANALOG AND DIGITAL LOOP-BACK TEST MODES Tx[5:0] port is routed back to the Rx[5:0] port, thereby The AD9865 features analog and digital loop-back capabilities confirming proper bus operation. The Rx port can also be that can assist in system debug and final test. Analog loop-back three-stated for half- and full-duplex interfaces. routes the digital output of the ADC back into the Tx data path prior to the interpolation filters such that the Rx input signal Table 26. SPI Registers for Test Modes can be monitored at the output of the TxDAC or IAMP. As a Address (Hex) Bit Description result, the analog loop-back feature can be used for a half- or 0x0D (7) Analog loop-back full-duplex interface, to allow testing of the functionality of the (6) Digital loop-back entire IC (excluding the digital data interface). (5) Rx port three-state For example, the user can configure the AD9865 with similar settings as the target system, inject an input signal (sinusoidal Rev. A | Page 43 of 48 AD9865 PCB DESIGN CONSIDERATIONS may be allocated to the IAMP, if its supply voltage differs from Although the AD9865 is a mixed-signal device, the part should the 3.3 V required by AVDD and CLKVDD. On the digital side, be treated as an analog component. The on-chip digital circuitry DVDD and DRVDD can share the same 3.3 V digital power has been specially designed to minimize the impact of its digital plane. This digital power plane brings the current used to power switching noise on the MxFE’s analog performance. the digital portion of the MxFE and its output drivers. This To achieve the best performance, the power, grounding, and digital plane should be kept from going underneath the analog layout recommendations in this section should be followed. components. Assembly instructions for the micro-lead frame package can be The analog and digital power planes allocated to the MxFE may found in an application note from Amkor at: be fed from the same low noise voltage source; however, they http://www.amkor.com/products/notes_papers/MLF_AppNote should be decoupled from each other to prevent the noise _0902.pdf. generated in the digital portion of the MxFE from corrupting COMPONENT PLACEMENT the AVDD supply. This can be done by using ferrite beads be- tween the voltage source and the respective analog and digital If the three following guidelines of component placement are power planes with a low ESR, bulk decoupling capacitor on the followed, chances for getting the best performance from the MxFE side of the ferrite. Each of the MxFE’s supply pins MxFE are greatly increased. First, manage the path of return (AVDD, CLKVDD, DVDD, and DRVDD) should also have currents flowing in the ground plane so that high frequency dedicated low ESR, ESL decoupling capacitors. The decoupling switching currents from the digital circuits do not flow on the capacitors should be placed as close to the MxFE supply pins as ground plane under the MxFE or analog circuits. Second, keep possible. noisy digital signal paths and sensitive receive signal paths as short as possible. Third, keep digital (noise generating) and GROUND PLANES analog (noise susceptible) circuits as far away from each other The AD9865 evaluation board uses a single serrated ground as possible. plane to help prevent any high frequency digital ground To best manage the return currents, pure digital circuits that currents from coupling over to the analog portion of the ground generate high switching currents should be closest to the power plane. The digital currents affiliated with the high speed data supply entry. This keeps the highest frequency return current bus interface (Pin 1 to Pin 16) have the highest potential of paths short and prevents them from traveling over the sensitive generating problematic high frequency noise. A ground MxFE and analog portions of the ground plane. Also, these serration that contains these currents should reduce the effects circuits should be generously bypassed at each device, which of this potential noise source. further reduces the high frequency ground currents. The MxFE The ground plane directly underneath the MxFE should be should be placed adjacent to the digital circuits, such that the continuous and uniform. The 64-lead LFCSP package is ground return currents from the digital sections do not flow in designed to provide excellent thermal conductivity. This is the ground plane under the MxFE. partly achieved by incorporating an exposed die paddle on the The AD9865 has several pins that are used to decouple sensitive bottom surface of the package. However, to take full advantage internal nodes. These pins are REFIO, REFB, and REFT. The of this feature, the PCB must have features to effectively decoupling capacitors connected to these points should have conduct heat away from the package. This can be achieved by low ESR and ESL. These capacitors should be placed as close to incorporating thermal pad and thermal vias on the PCB. While the MxFE as possible (see Figure 75) and be connected directly a thermal pad provides a solderable surface on the top surface to the analog ground plane. The resistor connected to the of the PCB (to solder the package die paddle on the board), REFADJ pin should also be placed close to the device and thermal vias are needed to provide a thermal path to inner connected directly to the analog ground plane. and/or bottom layers of the PCB to remove the heat. POWER PLANES AND DECOUPLING Lastly, all ground connections should be made as short as possible. This results in the lowest impedance return paths and While the AD9865 evaluation board demonstrates a very good the quietest ground connections. power supply distribution and decoupling strategy, it can be further simplified for many applications. The board has four SIGNAL ROUTING layers: two signal layers, one ground plane, and one power The digital Rx and Tx signal paths should be kept as short as plane. While the power plane on the evaluation board is split possible. Also, the impedance of these traces should have a into multiple analog and digital subsections, a permissible controlled characteristic impedance of about 50 Ω. This alternative would be to have AVDD and CLKVDD share the prevents poor signal integrity and the high currents that can same analog 3.3 V power plane. A separate analog plane/supply Rev. A | Page 44 of 48 AD9865 occur during undershoot or overshoot caused by ringing. If the form a differential pair and should be routed together as a pair. signal traces cannot be kept shorter than about 1.5 inches, series By keeping the traces adjacent to each other, noise coupled onto the signals appears as common mode and is largely rejected by termination resistors (33 Ω to 47 Ω) should be placed close to all digital signal sources. It is a good idea to series-terminate all the MxFE receive input. Keeping the driving point impedance clock signals at their source, regardless of trace length. of the receive signal low and placing any low-pass filtering of the signals close to the MxFE further reduces the possibility of The receive RX+ and RX− signals are the most sensitive signals noise corrupting these signals. on the entire board. Careful routing of these signals is essential for good receive path performance. The RX+ and RX− signals Rev. A | Page 45 of 48 AD9865 EVALUATION BOARD independent monitoring of the ac power line. The evaluation An evaluation board is available for the AD9865 and AD9866. board allows complete optimization of power line reference The digital interface to the evaluation board can be configured designs based around the AD9865 or AD9866. for a half- or full-duplex interface. Two 40-pin and one 26-pin male right angle headers (0.100 inches) provide easy interfacing Alternatively, the evaluation board allows independent evalua- to test equipment such as digital data capture boards, pattern tion of the TxDAC, IAMP, and Rx paths via SMA connectors. generators, or custom digital evaluation boards (FPGA, DSP, or The IAMP can be easily configured for a voltage or current ASIC). The reference clock source can originate from an exter- mode interface via jumper settings. The TxDAC’s performance nal generator, crystal oscillator, or crystal. Software and an can be evaluated directly or via an optional dual op amp driver interface cable are included to allow for programming of the SPI stage. The Rx path includes a transformer and termination registers via a PC. resistor allowing a calibrated differential input signal to be injected into its front end. The analog interface on the evaluation board provides a full analog front-end reference design for power line applications. It The Analog Devices, Inc. website offers more information on includes a power line socket, line transformer, protection diodes, the AD9865/AD9866 evaluation board. and passive filtering components. An auxiliary path allows Rev. A | Page 46 of 48 AD9865 OUTLINE DIMENSIONS 0.30 9.00 0.25 0.60 MAX BSC SQ 0.18 PIN 1 0.60 MAX INDICATOR 49 64 1 48 PIN 1 INDICATOR 7.25 8.75 EXPOSED PAD TOP BSC SQ 7.10 SQ* (BOTTOM VIEW) VIEW 6.95 0.45 33 0.40 16 32 17 0.35 0.25 MIN 7.50 REF 0.80 MAX 1.00 12° MAX 0.65 TYP 0.85 0.05 MAX 0.80 0.02 NOM 0.50 BSC 0.20 REF SEATING PLANE * COMPLIANT TO JEDEC STANDARDS MO-220-VMMD EXCEPT FOR EXPOSED PAD DIMENSION Figure 85. 64-Lead Lead Frame Chip Scale Package (LFCSP) [CP-64-3] Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option AD9865BCP −40°C to +85°C 64-Lead LFCSP CP-64-3 AD9865BCPRL −40°C to +85°C 64-Lead LFCSP CP-64-3 1 AD9865BCPZ −40°C to +85°C 64-Lead LFCSP CP-64-3 1 AD9865BCPZRL −40°C to +85°C 64-Lead LFCSP CP-64-3 AD9865CHIPS DIE AD9865-EB Evaluation Board 1 Z = Pb-free part. Rev. A | Page 47 of 48 AD9865 NOTES © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C04493–0–11/04(A) Rev. A | Page 48 of 48