ANALOG DEVICES AD9864

IF Digitizing Subsystem AD9864* PRODUCT OVERVIEW FEATURES The AD9864 is a general-purpose IF subsystem that digitizes a 10 MHz to 300 MHz input frequency low level 10 MHz to 300 MHz IF input with a signal bandwidth 6.8 kHz to 270 kHz output signal bandwidth ranging from 6.8 kHz to 270 kHz. The signal chain of the 7.5 dB SSB NF AD9864 consists of a low noise amplifier (LNA), a mixer, a –7.0 dBm IIP3 band-pass Σ-Δ analog-to-digital converter (ADC), and a deci- AGC free range up to –34 dBm mation filter with programmable decimation factor. An auto- 12 dB continuous AGC range matic gain control (AGC) circuit gives the AD9864 12 dB of 16 dB front end attenuator continuous gain adjustment. Auxiliary blocks include both Baseband I/Q 16-bit (or 24-bit) serial digital output clock and LO synthesizers. LO and sampling clock synthesizers The high dynamic range of the AD9864 and inherent antialias- Programmable decimation factor, output format, ing provided by the band-pass Σ-Δ converter allow the device to AGC, and sythesizer settings cope with blocking signals up to 95 dB stronger than the desired 370 Ω input impedance signal. This attribute often reduces the cost of a radio by reduc- 2.7 V to 3.6 V supply voltage ing IF filtering requirements. Also, it enables multimode radios Low current consumption: 17 mA of varying channel bandwidths, allowing the IF filter to be spe- 48-lead LFCSP package cified for the largest channel bandwidth. APPLICATIONS The SPI® port programs numerous parameters of the AD9864, allowing the device to be optimized for any given application. Multimode narrow-band radio products Programmable parameters include synthesizer divide ratios, Analog/digital UHF/VHF FDMA receivers AGC attenuation and attack/decay time, received signal TETRA, APCO25, GSM/EDGE strength level, decimation factor, output data format, 16 dB Portable and mobile radio products attenuator, and the selected bias currents. SATCOM terminals The AD9864 is available in a 48-lead LFCSP package and operates from a single 2.7 V to 3.6 V supply. The total power *Protected by U.S. Patent No. 5,969,657. consumption is typically 56 mW and a power-down mode is provided via serial interfacing. FUNCTIONAL BLOCK DIAGRAM MXOP MXON IF2P IF2N GCP GCN DAC AGC AD9864 –16dB DECIMATION LNA IFIN - ADC FORMATTING/SSI DOUTA FILTER DOUTB FS CLKOUT FREF CONTROL LOGIC LO VOLTAGE CLK SYN SYN REFERENCE SPI IOUTL LOP LON IOUTC CLKP CLKN VREFP VCM VREFN PC PD PE SYNCB LO VCO AND LOOP FILTER LOOP FILTER Figure 1. AD9864 Block Diagram Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 www.analog.com or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved. 04319-0-001 AD9864 TABLE OF CONTENTS General Description ......................................................................... 3 IF LNA/Mixer ............................................................................. 26 AD9864 Specifications..................................................................... 4 Band-Pass ∑-∆ ADC .................................................................. 27 Digital Specifications........................................................................ 6 Decimation Filter ....................................................................... 29 Absolute Maximum Ratings............................................................ 7 Variable Gain Amplifier Operation With Automatic Gain Control......................................................................................... 30 Thermal Resistance ...................................................................... 7 Variable Gain Control................................................................ 31 Pin Configuration and Functional Descriptions.......................... 8 Automatic Gain Control (AGC)............................................... 32 Definition of Specifications/Test Methods ............................... 9 System Noise Figure (NF) Versus VGA (or AGC) Control .. 34 Typical Performance Characteristics ........................................... 10 Applications Considerations..................................................... 35 Serial Peripheral Interface (SPI) ............................................... 15 Spurious Responses.................................................................... 37 Theory of Operation ...................................................................... 17 External Passive Component Requirements .......................... 37 Serial Port Interface (SPI).......................................................... 17 Applications ................................................................................ 38 Synchronous Serial Interface (SSI)........................................... 18 Layout Example, Evaluation Board, and Software ................. 42 Syncronization Using SYNCB .................................................. 22 Outline Dimensions ....................................................................... 43 Interfacing to DSPs..................................................................... 22 ESD Caution................................................................................ 43 Power Control............................................................................. 23 Ordering Guide .......................................................................... 43 LO Synthesizer ............................................................................ 23 Fast Acquire Mode...................................................................... 24 Clock Synthesizer ....................................................................... 24 REVISION HISTORY Revision 0: Initial Version Rev. 0 | Page 2 of 44 AD9864 GENERAL DESCRIPTION cascaded decimation factor is programmable from 48 to 960. The AD9864 is a general-purpose narrow-band IF subsystem that The decimation filter data is output via the synchronous serial digitizes a low level 10 MHz to 300 MHz IF input with a signal interface (SSI) of the chip. bandwidth ranging from 6.8 kHz to 270 kHz. The signal chain of the AD9864 consists of an LNA, a mixer, a band-pass Σ-∆ ADC, Additional functionality built into the AD9864 includes LO and and a decimation filter with programmable decimation factor. clock synthesizers, programmable AGC, and a flexible synchro- nous serial interface for output data. The input LNA is a fixed gain block with an input impedance of approximately 370 Ω||1.4 pF. The LNA input is single-ended The LO synthesizer is a programmable PLL consisting of a low and self-biasing, allowing the input IF to be ac-coupled. The noise phase frequency detector (PFD), a variable output current LNA can be disabled through the serial interface, providing a charge pump (CP), a 14-bit reference divider, A and B counters, fixed 16 dB attenuation to the input signal. and a dual modulus prescaler. The user only needs to add an appropriate loop filter and VCO for complete operation. The LNA drives the input port of a Gilbert-type active mixer. The mixer LO port is driven by the on-chip LO buffer, which The clock synthesizer is equivalent to the LO synthesizer with can be driven externally, single-ended or differential. The LO the following differences: buffer inputs are self-biasing and allow the LO input to be ac-coupled. The open-collector outputs of the mixer drive an • It does not include the prescaler or A counter. external resonant tank consisting of a differential LC network • It includes a negative resistance core used for VCO tuned to the IF of the band-pass Σ-∆ ADC. generation. The external differential LC tank forms the resonator for the The AD9864 contains both a variable gain amplifier (VGA) and a first stage of the band-pass Σ-∆ ADC. The tank LC values must digital VGA (DVGA). Both of these can operate manually or be selected for a center frequency of f /8, where f is the CLK CLK automatically. In manual mode, the gain for each is programmed sample rate of the ADC. The f /8 frequency is the IF digitized CLK through the SPI. In automatic gain control mode, the gains are by the band-pass Σ-∆ ADC. On-chip calibration allows stan- adjusted automatically to ensure the ADC does not clip and that dard tolerance inductor and capacitor values. The calibration is the rms output level of the ADC is equal to a programmable ref- typically performed once at power-up. erence level. The ADC contains a sixth order multibit band-pass Σ-∆ modu- The VGA has 12 dB of attenuation range and is implemented by lator that achieves very high instantaneous dynamic range over adjusting the ADC full-scale reference level. The DVGA gain is a narrow frequency band centered at fCLK/8. The modulator implemented by scaling the output of the decimation filter. The output is quadrature mixed to baseband and filtered by three DVGA is most useful in extending the dynamic range in nar- cascaded linear phase FIR filters to remove out-of-band noise. row-band applications requiring 16-bit I and Q data format. The first FIR filter is a fixed decimate by 12 using a fourth order The SSI provides a programmable frame structure, allowing comb filter. The second FIR filter also uses a fourth order comb 24-bit or 16-bit I and Q data and flexibility by including filter with programmable decimation from 1 to 16. The third attenuation and RSSI data if required. FIR stage is programmable for decimation of either 4 or 5. The Rev. 0 | Page 3 of 44 AD9864 AD9864 SPECIFICATIONS Table 1. VDDI = VDDF = VDDA = VDDC = VDDL = VDDH = 2.7 V to 3.6 V, VDDQ = VDDP = 2.7 V to 5.5 V, fCLK = 18 MSPS, fIF = 109.65 MHz, fLO = 107.4 MHz, fREF = 16.8 MHz, unless otherwise noted. Standard operating mode: VGA at minimum attenuation setting, synthesizers in normal (not fast acquire) mode, decimation factor = 900, 16-bit digital output, and 10 pF load on SSI output pins. Parameter Temperature Test Level Min Typ Max Unit 1 SYSTEM DYNAMIC PERFORMANCE 2, 3 SSB Noise Figure @ Minimum VGA Attenuation Full IV 7.5 9.5 dB 2,3 @ Maximum VGA Attenuation Full IV 13 dB 2,3 Dynamic Range with AGC Enabled Full IV 91 95 dB 3 IF Input Clip Point @ Maximum VGA Attenuation Full IV –20 –19 dBm 3 @ Minimum VGA Attenuation Full IV –32 –31 dBm Input Third Order Intercept (IIP3) Full IV –12 –7.0 dBm Gain Variation over Temperature Full IV 0.7 2 dB LNA + MIXER Maximum RF and LO Frequency Range Full IV 300 500 MHz LNA Input Impedance 25°C V 370||1.4 Ω||pF 1 Mixer LO Input Resistance 25°C V kΩ LO SYNTHESIZER LO Input Frequency Full IV 7.75 300 MHz LO Input Amplitude Full IV 0.3 2.0 V p-p FREF Frequency (for Sinusoidal Input Only) Full IV 8 25 MHz FREF Input Amplitude Full IV 0.3 3 V p-p FREF Slew Rate Full IV 7.5 V/µs 4 Minimum Charge Pump Current @ 5 V Full VI 0.67 mA 4 Maximum Charge Pump Current @ 5 V Full VI 5.3 mA 5 Charge Pump Output Compliance Full VI 0.4 VDDP – 0.4 V Synthesizer Resolution Full IV 6.25 kHz CLOCK SYNTHESIZER CLK Input Frequency Full IV 13 26 MHz CLK Input Amplitude Full IV 0.3 VDDC V p-p 4 Minimum Charge Pump Output Current Full VI 0.67 mA 4 Maximum Charge Pump Output Current Full VI 5.3 mA 5 Charge Pump Output Compliance Full VI 0.4 VDDQ – 0.4 V Synthesizer Resolution Full VI 2.2 kHz Σ-∆ ADC Resolution Full IV 16 24 Bits Clock Frequency (fCLK) Full IV 13 26 MHz Center Frequency Full V f/8 MHz CLK Pass-Band Gain Variation Full IV 1.0 dB Alias Attenuation Full IV 80 dB GAIN CONTROL Programmable Gain Step Full V 16 dB AGC Gain Range Full V 12 dB GCP Output Resistance Full IV 50 72.5 95 kΩ 1 This includes 0.9 dB loss of matching network. 2 AGC with DVGA enabled. 3 Measured in 10 kHz bandwidth. 4 Programmable in 0.67 mA steps. 5 Voltage span in which LO (or CLK) charge pump output current is maintained within 5% of nominal value of VDDP/2 (or VDDQ/2). Rev. 0 | Page 4 of 44 AD9864 Parameter Temperature Test Level Min Typ Max Unit OVERALL Analog Supply Voltage (VDDA, VDDF, VDDI) Full VI 2.7 3.0 3.6 V Digital Supply Voltage (VDDD, VDDC, VDDL) Full VI 2.7 3.0 3.6 V 1 Interface Supply Voltage (VDDH) Full VI 1.8 3.6 V Charge Pump Supply Voltage (VDDP, VDDQ) Full VI 2.7 5.0 5.5 V Total Current 2 Operation Mode Full VI 17 mA Standby Full VI 0.01 mA OPERATING TEMPERATURE RANGE –40 +85 °C 1 VDDH must be less than VDDD + 0.5 V. 2 Clock VCO off and additional 0.7 mA with VGA @ maximum attenuation. Rev. 0 | Page 5 of 44 AD9864 DIGITAL SPECIFICATIONS Table 2. VDDI = VDDF = VDDA = VDDC = VDDL = VDDH = 2.7 V to 3.6 V, VDDQ = VDDP = 2.7 V to 5.5 V, fCLK = 18 MSPS, fIF = 109.65 MHz, fLO = 107.4 MHz, fREF = 16.8 MHz, unless otherwise noted. Standard operating mode: VGA at minimum attenuation setting, synthesizers in normal (not fast acquire) mode, decimation factor = 900, 16-bit digital output, and 10 pF load on SSI output pins. Parameter Temperature Test Level Min Typ Max Unit DECIMATOR 1 Decimation Factor Full IV 48 960 Pass-Band Width Full V 50% fCLKOUT Pass-Band Gain Variation Full IV 1.2 dB Alias Attenuation Full IV 88 dBm SPI-READ OPERATION (See Figure 30) PC Clock Frequency Full IV 10 MHz PC Clock Period (t) Full IV 100 ns CLK PC Clock High (t) Full IV 45 ns HI PC Clock Low (tLOW) Full IV 45 ns PC to PD Setup Time (tDS) Full IV 2 ns PC to PD Hold Time (tDH) Full IV 2 ns PE to PC Setup Time (t) Full IV 5 ns S PC to PE Hold Time (t) Full IV 5 ns H 2 SPI-WRITE OPERATION (See Figure 29) PC Clock Frequency Full IV 10 MHz PC Clock Period (t) Full IV 100 ns CLK PC Clock High (t) Full IV 45 ns HI PC Clock Low (tLOW) Full IV 45 ns PC to PD Setup Time (tDS) Full IV 2 ns PC to PD Hold Time (tDH) Full IV 2 ns PC to PD (or DOUTB) Data Valid Time (t) Full IV 3 ns DV PE to PD Output Valid to Hi-Z (t) Full IV 8 ns EZ 2 SSI (See Figure 32) CLKOUT Frequency Full IV 0.867 26 MHz CLKOUT Period (t) Full IV 38.4 1153 ns CLK CLKOUT Duty Cycle (tHI, tLOW) Full IV 33 50 67 ns CLKOUT to FS Valid Time (tV) Full IV –1 +1 ns CLKOUT to DOUT Data Valid Time (tDV) Full IV –1 +1 ns 3 CMOS LOGIC INPUTS Logic 1 Voltage (VIH) Full IV VDDH – 0.2 V Logic 0 Voltage (VIL) Full IV 0.5 V Logic 1 Current (I) Full IV 10 µA IH Logic 0 Current (I) Full IV 10 µA IL Input Capacitance Full IV 3 pF 2, 3, 4 CMOS LOGIC OUTPUTS Logic 1 Voltage (V ) Full IV VDDH – 0.2 V OH Logic 0 Voltage (V) Full IV 0.2 V OL 1 Programmable in steps of 48 or 60. 2 CMOS output mode with CLOAD = 10 pF and Drive Strength = 7. 3 Absolute maximum and minimum input/output levels are VDDH + 0.3 V and –0.3 V. 4 IOL = 1 mA; specification is also dependent on drive strength setting. Rev. 0 | Page 6 of 44 AD9864 ABSOLUTE MAXIMUM RATINGS Table 3. AD9864 Absolute Maximum Ratings Parameter With Respect to Min Max Unit VDDF, VDDA, VDDC, GNDF, GNDA, GNDC, GNDD, –0.3 +4.0 V VDDD, VDDH, VDDL, VDDI GNDH, GNDL, GNDI, GNDS VDDF, VDDA, VDDC, VDDR, VDDA, VDDC, –4.0 +4.0 V VDDD, VDDH, VDDL, VDDI VDDD, VDDH, VDDL, VDDI VDDP, VDDQ GNDP, GNDQ –0.3 +6.0 V GNDF, GNDA, GNDC, GNDD, GNDF, GNDA, GNDC, GNDD, –0.3 +0.3 V GNDH, GNDL, GNDI, GNDQ, GNDP, GNDS GNDH, GNDL, GNDI, GNDQ, GNDP, GNDS MXOP, MXON, LOP, GNDH –0.3 VDDI + 0.3 V LON, IFIN, CXIF, CXVL, CXVM PC, PD, PE, CLKOUT, GNDH –0.3 VDDH + 0.3 V DOUTA, DOUTB, FS, SYNCB IF2N, IF2P, GCP, GCN GNDF –0.3 VDDF + 0.3 V VFEFP, VREGN, RREF GNDA –0.3 VDDA + 0.3 V IOUTC GNDQ –0.3 VDDQ + 0.3 V IOUTL GNDP –0.3 VDDP + 0.3 V CLKP, CLKN GNDC –0.3 VDDC + 0.3 V FREF GNDL –0.3 VDDL + 0.3 V Junction Temperature 150 °C Storage Temperature –65 +150 °C Lead Temperature 300 °C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE θJA is specified for the worst-case conditions, i.e., θJA is specified for device soldered in circuit board for surface-mount packages. Table 4. Thermal Resistance Package Type Unit θJA 48-Lead LFCSP 29.5 °C/W Rev. 0 | Page 7 of 44 AD9864 PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS 48 47 46 45 44 43 42 41 40 39 38 37 MXOP 1 36 GNDL PIN 1 2 35 MXON IDENTIFIER FREF 3 34 GNDF GNDS IF2N 4 33 SYNCB IF2P 5 32 GNDH AD9864 VDDF 6 31 FS TOP VIEW GCP 7 30 DOUTB (Not to Scale) GCN 8 29 DOUTA VDDA 9 28 CLKOUT GNDA 10 27 VDDH 11 26 VREFP VDDD 12 25 VREFN PE 13 14 15 16 17 18 19 20 21 22 23 24 Figure 2. 48-Lead LFCSP, Backside Paddle Contact Is Connected to Ground Table 5. Pin Function Descriptions—48-Lead Lead Frame Chip Scale Package (LFCSP) Pin No. Mnemonic Description Pin No. Mnemonic Description 1 MXOP Mixer Output, Positive 27 VDDH Positive Supply for Digital Interface 2 MXON Mixer Output, Negative 28 CLKOUT Clock Output for SSI Port 3 GNDF Ground for Front End of ADC 29 DOUTA Data Output for SSI Port 4 IF2N Second IF Input (to ADC), Negative 30 DOUTB Data Output for SSI Port (Inverted) or SPI Port 5 IF2P Second IF Input (to ADC), Positive 31 FS Frame Sync for SSI Port 6 VDDF Positive Supply for Front End of ADC 32 GNDH Ground for Digital Interface 7 GCP Filter Capacitor for ADC Full-Scale Control 33 SYNCB Resets SSI and DecimatorCounters; Active Low 8 GCN Full-Scale Control Ground 34 GNDS Substrate Ground 9 VDDA Positive Supply for ADC Back End 35 FREF Reference Frequency Input for Both 10 GNDA Ground for ADC Back End Synthesizers 11 VREFP Voltage Reference, Positive 36 GNDL Ground for LO Synthesizer 12 VREFN Voltage Reference, Negative 37 GNDP Ground for LO Synthesizer Charge 13 RREF Reference Resistor: Requires 100 kΩ to Pump GNDA 38 IOUTL LO Synthesizer Charge Pump Out 14 VDDQ Positive Supply for Clock Synthesizer Current 15 IOUTC Clock Synth Charge Pump Out Current 39 VDDP Positive Supply for LO Synthesizer 16 GNDQ Ground for Clock Synthesizer Charge Charge Pump Pump 40 VDDL Postive Supply for LO Synthesizer 17 VDDC Positive Supply for Clock Synthesizer 41 CXVM External Filter Capacitor; DC Output of 18 GNDC Ground for Clock Synthesizer LNA 19 CLKP Sampling Clock Input/Clock VCO Tank, 42 LON LO Input to Mixer and LO Synthesizer, Positive Negative 20 CLKN Sampling Clock Input/Clock VCO Tank, 43 LOP LO Input to Mixer and LO Synthesizer, Negative Positive 21 GNDS Substrate Ground 44 CXVL External Bypass Capacitor for LNA Power Supply 22 GNDD Ground for Digital Functions 23 PC Clock Input for SPI Port 45 GNDI Ground for Mixer and LNA 24 PD Data I/O for SPI Port 46 CXIF External Capacitor for Mixer V-I Converter Bias 25 PE Enable Input for SPI Port 47 IFIN First IF Input (to LNA) 26 VDDD Positive Supply for Internal Digital 48 VDDI Positive Supply for LNA and Mixer Rev. 0 | Page 8 of 44 RREF VDDI VDDQ IFIN IOUTC CXIF GNDQ GNDI VDDC CXVL GNDC LOP CLKP LON CLKN CXVM GNDS VDDL GNDD VDDP PC IOUTL PD GNDP 04319-0-002 AD9864 DEFINITION OF SPECIFICATIONS/TEST METHODS Single Sideband Noise Figure (SSB NF) Dynamic Range (DR) Noise figure (NF) is defined as the degradation in SNR per- Dynamic range is the measure of a small target input signal formance (in dB) of an IF input signal after it passes through a (PTARGET) in the presence of a large unwanted interferer signal component or system. It can be expressed with the equation (PINTER). Typically, the large signal will cause some unwanted characteristic of the component or system to degrade, thus mak- Noise Figure = 10× log(SNR /SNR ) IN OUT ing it unable to detect the smaller target signal correctly. In the case of the AD9864, it is often a degradation in noise figure at The term SSB is applicable for heterodyne systems containing a increased VGA attenuation settings that limits its dynamic range. mixer. It indicates that the desired signal spectrum resides on only one side of the LO frequency (i.e., single sideband); thus a The test method for the AD9864 is as follows. The small target “noiseless” mixer has a noise figure of 3 dB. signal (an unmodulated carrier) is input at the center of the IF frequency, and its power level (PTARGET) is adjusted to achieve an The SSB noise figure of the AD9864 is determined by the equation SNRTARGET of 6 dB. The power of the signal is then increased by 3 dB prior to injecting the interferer signal. The offset frequency SSB NF = P –[] 10 × log(BW) – (−174 dBm/Hz) – SNR IN of the interferer signal is selected so that aliases produced by the where P is the input power of an unmodulated carrier, BW is IN decimation filter’s response as well as phase noise from the LO the noise measurement bandwidth, –174 dBm/Hz is the ther- (due to reciprocal mixing) do not fall back within the measure- mal noise floor at 293K, and SNR is the measured signal-to- ment bandwidth. For this reason, an offset of 110 kHz was noise ratio in dB of the AD9864. selected. The interferer signal (also an unmodulated carrier) is then injected into the input and its power level is increased to the Note that PIN is set to –85 dBm to minimize any degradation in point (PINTER) where the target signal SNR is reduced to 6 dB. The measured SNR due to phase noise from the RF and LO signal dynamic range is determined with the equation generators. The IF frequency, CLK frequency, and decimation factors are selected to minimize any spurious components DR = P – P + SNR INTER TARGET TARGET falling within the measurement bandwidth. Note also that a Note that the AD9864’s AGC is enabled for this test. bandwidth of 10 kHz is used for the data sheet specification. All references to noise figures within this data sheet imply single IF Input Clip Point sideband noise figure. The IF input clip point is defined as the input power that results in a digital output level 2 dB below full-scale. Unlike Input Third Order Intercept (IIP3) other linear components that typically exhibit a soft compres- IIP3 is a figure of merit used to determine a component’s or sion (characterized by its 1 dB compression point), an ADC system’s susceptibility to intermodulation distortion (IMD) exhibits a hard compression once its input signal exceeds its from its third order nonlinearities. Two unmodulated carriers rated maximum input signal range. In the case of the AD9864, at a specified frequency relationship (f1 and f2) are injected into which contains a Σ-∆ ADC, hard compression should be a nonlinear system exhibiting third order nonlinearities pro- avoided because it causes severe SNR degradation. ducing IMD components at 2f1 – f2 and 2f2 – f1. IIP3 graphi- cally represents the extrapolated intersection of the carrier’s input power with the third order IMD component when plot- ted in dB. The difference in power (D in dBc) between the two carriers and the resulting third order IMD components can be determined from the equation D = 2×() IIP3 – P IN Rev. 0 | Page 9 of 44 AD9864 TYPICAL PERFORMANCE CHARACTERISTICS 0 9.5 9.0 –2 +85°C 8.5 –4 +85°C 8.0 –6 +25°C 7.5 +25°C –8 7.0 –40°C –40°C –10 6.5 –12 6.0 2.7 3.0 3.3 3.6 2.7 3.0 3.3 3.6 VDDx (V) VDDx (V) Figure 3. SSB Noise Figure vs. Supply Figure 6. IIP3 vs. Supply 98 –17.5 97 –18.0 +25°C 96 –18.5 –40°C +85°C 95 –19.0 +25°C 94 –19.5 +85°C –40°C 93 –20.0 92 –20.5 2.7 3.0 3.3 3.6 2.7 3.0 3.3 3.6 VDDx (V) VDDx (V) Figure 4. Dynamic Range vs. Supply Figure 7. Maximum VGA Attenuation Clip Point vs. Supply –29.5 0.1 0 –30.0 –0.1 –0.2 –30.5 –0.3 –0.4 +85°C –31.0 –0.5 +25°C –0.6 –31.5 –0.7 –40°C –0.8 –32.0 –20 –17 –14 –11 –8 –5 2.7 3.0 3.3 3.6 LO DRIVE (dBm) VDDx (V) Figure 5. Minimum VGA Attenuation Clip Point vs. Supply Figure 8. Normalized Gain Variation vs. LO Drive (VDDx = 3.0 V) Rev. 0 | Page 10 of 44 INPUT CLIP POINT (dBm) NF (dB) DR (dB) 04319-0-005 04319-0-003 04319-0-007 INPUT CLIP POINT (dBm) GAIN VARIATION (dB) IIP3 (dBm) 04319-0-008 04319-0-004 04319-0-006 AD9864 9.0 0 –12 8.8 –10 –15 8.6 –20 –18 8.4 –30 –21 8.2 NF 8.0 –40 –24 7.8 –50 –27 IMD 7.6 –60 –30 7.4 –70 –33 7.2 7.0 –80 –36 –20 –15 –10 –5 0 5 –36 –33 –30 –27 –24 –21 –18 –15 –12 –9 –6 –3 –0 LO DRIVE (dBm) IFIN (dBm) Figure 9. Noise Figure and IMD vs. LO Drive (VDDx = 3.0 V) Figure 12. Gain Compression vs. IFIN with 16 dB LNA Attenuator Enabled 0 –55 –15 ADC DOES NOT GO INTO –61 –18 HARD COMPRESSION –2 PIN 3.6V –67 –21 2.7V 3.3V –24 –4 –73 –79 –27 3.0V –6 –85 –30 3.3V 3.0V –8 –91 –33 2.7V –97 –36 –10 3.6V –103 –39 –12 –42 –109 –115 –45 –14 –51 –48 –45 –42 –39 –36 –33 –30 –30 –28 –26 –24 –22 –20 –18 –16 –14 IFIN (dBm) IFIN (dBm) Figure 13. IMD vs. IFIN Figure 10. Gain Compression vs. IFIN 10.0 10.0 9.5 9.5 16-BIT 16-BIT 16-BIT I/Q DATA DATA I/Q DATA WITH DVGA ENABLED 9.0 9.0 16-BIT DATA WITH DVGA ENABLED 8.5 8.5 8.0 8.0 24-BIT 24-BIT I/Q DATA DATA 7.5 7.5 10 100 1000 10 100 1000 CHANNEL BANDWIDTH (kHz) CHANNEL BANDWIDTH (kHz) Figure 11. Noise Figure vs. BW (Minimum Attenuation, f = 13 MSPS) Figure 14. Noise Figure vs. BW (Minimum Attenuation, f = 18 MSPS) CLK CLK Rev. 0 | Page 11 of 44 NOISE FIGURE (dBc) NOISE FIGURE (dB) dBFS 04319-0-011 IMD WITH IFIN = –36 dBm (dBc) 04319-0-013 04319-0-009 IMD (dBm) NOISE FIGURE (dB) dBm 04319-0-014 04319-0-010 PIN (dBFS) 04319-0-012 AD9864 10.0 11.5 16-BIT DATA WITH DVGA ENABLED 11.0 9.5 10.5 BW = 27.08kHz 24-BIT (K = 0, M = 3) 16-BIT DATA 10.0 DATA BW = 12.04kHz 9.0 (K = 0, M = 8) 9.5 9.0 8.5 BW = 6.78kHz 8.5 (K = 0, M = 15) 8.0 8.0 7.5 7.5 7.0 10 100 1000 0 3 6 9 12 CHANNEL BANDWIDTH (kHz) VGA ATTENUATION (dB) Figure 15. Noise Figure vs. BW (Minimum Attenuation, fCLK = 26 MSPS) Figure 18. Noise Figure vs. VGA Attenuation (fCLK = 13 MSPS) 14 14 13 13 BW = 75kHz BW = 135.42kHz (K = 0, M = 1) (K = 1, M = 1) BW = 90.28kHz 12 12 (K = 1, M = 2) BW = 50kHz (K = 0, M = 2) 11 11 BW = 15kHz (K = 0, M = 9) 10 10 BW = 27.08kHz (K = 1, M = 9) 9 9 8 8 7 7 0 3 69 12 0 3 6 9 12 VGA ATTENUATION (dB) VGA ATTENUATION (dB) Figure 16. Noise Figure vs. VGA Attenuation (fCLK = 18 MSPS) Figure 19. Noise Figure vs. VGA Attenuation (f = 26 MSPS) CLK –5 –30 –30 –5 –40 –40 –10 –10 –50 –50 –15 –15 PIN PIN –60 –60 –20 –20 –70 –70 –80 –25 –80 –25 –90 –90 –30 –30 –100 –100 –35 –35 –110 –110 –40 –40 –120 –120 –130 –45 –130 –45 –45 –42 –39 –36 –33 –30 –27 –24 –45 –42 –39 –36 –33 –30 –27 –24 IFIN (dB) IFIN (dBm) Figure 17. IMD vs. IFIN (fCLK = 13 MSPS) Figure 20. IMD vs. IFIN (f = 18 MSPS) CLK Rev. 0 | Page 12 of 44 IMD (dB) NOISE FIGURE (dB) NOISE FIGURE (dB) 04319-0-017 POUT (dBFS) 04319-0-015 04319-0-019 IMD (dBm) NOISE FIGURE (dB) NOISE FIGURE (dB) 04319-0-018 PIN (dBFS) 04319-0-016 04319-0-020 AD9864 –5 13 –30 –40 –10 12 –50 16-BIT WITH DVGA PIN –15 11 –60 –20 –70 10 –80 –25 9 –90 –30 24-BIT –100 8 –35 –110 –40 7 –120 –130 –45 6 –45 –42 –39 –36 –33 –30 –27 –24 0 50 100 150 200 250 300 350 400 450 500 IFIN (dBm) FREQUENCY (MHz) Figure 21. IMD vs. IFIN (fCLK = 26 MSPS) Figure 24. Noise Figure vs. Frequency (Minimum Attenuation, f = 18 MSPS, BW = 10 kHz) CLK 13 0 16-BIT WITH DVGA 12 –2 11 –4 10 9 24-BIT –6 8 –8 7 –10 6 0 50 100 150 200 250 300 350 400 450 500 0 50 100 150 200 250 300 350 400 450 500 FREQUENCY (MHz) FREQUENCY (MHz) Figure 22. Noise Figure vs. Frequency Figure 25. Input IIP3 vs. Frequency (fCLK = 18 MSPS) (Minimum Attenuation, f = 26 MSPS, BW = 10 kHz) CLK 0 20.0 128 18.5 112 AGC –2 17.0 96 15.5 80 –4 14.0 64 –6 12.5 48 NOISE FIGURE 11.0 32 –8 9.5 16 8.0 0 –10 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 0 50 100 150 200 250 300 350 400 450 500 INTERFERER LEVEL (dBm) FREQUENCY (MHz) Figure 26. Noise Figure vs. Interferer Level (16-Bit Data, Figure 23. Input IIP3 vs. Frequency (f = 26 MSPS) CLK BW = 12.5 kHz, AGCR = 1, fINTERFERER = fIF + 110 kHz) Rev. 0 | Page 13 of 44 IMD (dBc) IIP3 (dBm) NOISE FIGURE (dB) 04319-0-023 PIN (dBFS) 04319-0-023 04319-0-021 NOISE FIGURE (dBc) IIP3 (dBm) NOISE FIGURE (dB) 04319-0-022 MEAN AGC ATTN VALUE 04319-0-025 04319-0-026 AD9864 16 256 16 128 15 224 15 AGC ATTN AGC ATTN 14 192 14 96 13 160 13 12 128 12 64 NOISE FIGURE 11 96 11 NOISE FIGURE 10 64 32 10 9 32 9 0 0 8 8 –50 –45 –40 –35 –30 –25 –20 –15 –10 –65 –55 –45 –35 –25 –15 –5 INTERFERER LEVEL (dBm) INTERFERER LEVEL (dBm) Figure 27. Noise Figure vs. Interferer Level (16-Bit Data with DVGA, Figure 28. Noise Figure vs. Interferer Level (24-Bit Data, BW = 12.5 kHz, AGCR = 1, f = f + 110 kHz) BW = 12.5 kHz, AGCR = 1, f = f + 110 kHz) INTERFERER IF INTERFERER IF Rev. 0 | Page 14 of 44 NOISE FIGURE (dBc) MEAN AGC ATTN VALUE 04319-0-027 NOISE FIGURE (dBc) MEAN AGC ATTN VALUE 04319-0-028 AD9864 SERIAL PERIPHERAL INTERFACE (SPI) The SPI is a bidirectional serial port. It is used to load the configuration information into the registers listed below as well as to read back their contents. Table 6 provides a list of the registers that can be programmed through the SPI port. Addresses and default values are given in hexadecimal form. Table 6. SPI Address Map Bit Default Address (Hex) Breakdown Width Value Name Description POWER CONTROL REGISTERS 0x00 (7:0) 8 0xFF STBY Standby control bits (REF, LO, CKO, CK, GC, LNAMX, unused, and ADC). Default is power-up condition of standby. 0x01 (3:2) 2 0x00 CKOB CK oscillator bias (0 = 0.25 mA, 1 = 0.35 mA, 2 = 0.40 mA, 3 = 0.65 mA). (1:0) 2 0x00 ADCB Do not use. 0x02 (7:0) 8 0x00 TEST Factory test mode. Do not use. AGC 0x03 (7) 1 0 ATTEN Apply 16 dB attenuation in the front end. (6:0) 7 0x00 AGCG (14:8) AGC attenuation setting (7 MSBs of a 15-bit unsigned word). 0x04 (7:0) 8 0x00 AGCG (7:0) AGC attenuation setting (8 LSBs of a 15-bit unsigned word). 0x05 (7:4) 4 0x00 AGCA AGC attack bandwidth setting. Default yields 50 Hz loop bandwidth. (3:0) 4 0x00 AGCD AGC decay time setting. Default is decay time = attack time. 0x06 (7) 1 0 AGCV Enable digital VGA to increase AGC range by 12 dB. (6:4) 3 0x00 AGCO AGC overload update setting. Default is slowest update. (3) 1 0 AGCF Fast AGC (minimizes resistance seen between GCP and GCN). (2:0) 3 0x00 AGCR AGC enable/reference level (disabled, 3 dB, 6 dB, 9 dB, 12 dB, 15 dB below clip). DECIMATION FACTOR 0x07 (7:5) 3 Unused (4) 1 0 K Decimation factor = 60 × (M + 1), if K = 0; 48 × (M + 1), if K = 1. (3:0) 4 0x04 M Default is decimate-by-300. LO SYNTHESIZER 0x08 (5:0) 6 0x00 LOR (13:8) Reference frequency divider (6 MSBs of a 14-bit word). 0x09 (7:0) 8 0x38 LOR (7:0) Reference frequency divisor (8 LSBs of a 14-bit word). Default (56) yields 300 kHz from f = 16.8 MHz. REF 0x0A (7:5) 3 0x05 LOA A Counter (prescaler control counter). (4:0) 5 0x00 LOB (12:8) B Counter MSB (5 MSB of a 13-bit word). Default LOA and LOB values yield 300 kHz from 73.35 MHz to 2.25 MHz. 0x0B (7:0) 8 0x1D LOB (7:0) B Counter LSB (8 LSB of a 13-bit word). 0x0C (6) 1 0 LOF Enable fast acquire. (5) 1 0 LOINV Invert charge pump (0 = source current to increase VCO frequency). (4:2) 3 0x00 LOI Charge pump current in normal operation. IPUMP = (LOI +1) × 0.625 mA. (1:0) 2 0x03 LOTM Manual control of LO charge pump (0 = Off, 1 = Up, 2 = Down, and 3 = Normal). 0x0D (5:0) 6 0x00 LOFA (13:8) LO fast acquire time unit (6 MSBs of a 14-bit word). 0x0E (7:0) 8 0x04 LOFA (7:0) LO fast acquire time unit (8 LSBs of a 14-bit word). CLOCK SYNTHESIZER 0x10 (5:0) 6 0x00 CKR (13:8) Reference frequency divisor (6 MSBs of a 14-bit word). 0x11 (7:0) 8 0x38 CKR (7:0) Reference frequency divisor (8 LSBs of a 14-bit word). Default yields 300 kHz from f = 16.8 MHz; Minimum = 3, REF Maximum = 16383. 0x12 (4:0) 5 0x00 CKN (12:8) Synthesized frequency divisor (5 MSBs of a 13-bit word). Rev. 0 | Page 15 of 44 AD9864 Bit Default Address (Hex) Breakdown Width Value Name Description 0x13 (7:0) 8 0x3C CKN (7:0) Synthesized frequency divisor (8 LSBs of a 13-bit word). Default yields 300 kHz from 18 MHz; Minimum = 3, Maximum = 8191. 0x14 (6) 1 0 CKF Enable fast acquire. (5) 1 0 CKINV Invert charge pump (0 = source current to increase VCO frequency). (4:2) 3 0x00 CKI Charge pump current in normal operation. I = (CKI + 1) × 0.625 mA. PUMP (1:0) 2 0x03 CKTM Manual control of CLK charge pump (0 = Off, 1 = Up, 2 = Down, and 3 = Normal). 0x15 (5:0) 6 0x00 CKFA (13:8) CK fast acquire time unit (6 LSBs of a 14-bit word). 0x16 (7:0) 8 0x04 CKFA (7:0) CK fast acquire time unit (8 LSBs of a 14-bit word). SSI CONTROL 0x18 (7:0) 8 0x12 SSICRA SSI Control Register A. See Table 8. Default is FS and CLKOUT three-stated. 0x19 (7:0) 8 0x07 SSICRB SSI Control Register B. See Table 8 (16-Bit Data, maximum drive strength). 0x1A (3:0) 4 0x01 SSIORD Output rate divisor. fCLKOUT = fCLK/SSIORD. ADC TUNING 0x1C (1) 1 0 TUNE_LC Perform tuning on LC portion of the ADC (cleared when done). (0) 1 0 TUNE_RC Perform tuning on RC portion of the ADC (cleared when done). 0x1D (3:0) 3 0x00 CAPL1 (2:0) Coarse capacitance setting of LC tank (LSB is 25 pF, differential). 0x1E (5:0) 6 0x00 CAPL0 (5:0) Fine capacitance setting of LC tank (LSB is 0.4 pF, differential). 0x1F (7:0) 8 0x00 CAPR Capacitance setting for RC resonator (64 LSB of fixed capacitance). TEST REGISTERS AND SPI PORT READ ENABLE 0x37–0x39 (7:0) 8 0x00 TEST Factory test mode. Do not use. 0x3A (7:4) 4 0x00 TEST Factory test mode. Do not use. (3) 1 0 SPIREN Enable read from SPI port. (2:0) 3 0x00 TEST Factory test mode. Do not use. 0x3B (7:4) 4 0x00 TEST Factory test mode. Do not use. (3) 1 0 TRI Three-state DOUTB. (2:0) 3 0x00 TEST Factory test mode. Do not use. 0x3C–0x3E (7:0) 8 0x00 TEST Factory Test mode. Do not use. 0x3F (7:0) 8 Subject ID Revision ID (read-only); A write of 0x99 to this register is to equivalent to a power-on reset. Change Rev. 0 | Page 16 of 44 AD9864 THEORY OF OPERATION SERIAL PORT INTERFACE (SPI) The serial port of the AD9864 has 3-wire or 4-wire SPI capabil- eight clock cycles. PE stays low during the operation and goes ity, allowing read/write access to all registers that configure the high at the end of the transfer. If PE rises before the eight clock device’s internal parameters. The default 3-wire serial commu- cycles have passed, the operation is aborted. If PE stays low for nication port consists of a clock (PC), peripheral enable (PE), an additional eight clock cycles, the destination address is and bidirectional data (PD) signal. The inputs to PC, PE, and incremented and another eight bits of data are shifted in. PD contain a Schmitt trigger with a nominal hysteresis of 0.4 V Again, should PE rise early, the current byte is ignored. By centered about the digital interface supply, i.e., VDDH/2. using this implicit addressing mode, the chip can be configured A 4-wire SPI interface can be enabled by setting the MSB of the with a single write operation. Registers identified as being sub- SSICRB register (Reg. 0x19, Bit 7) and setting Reg. 0x3A to 00, ject to frequent updates, namely those associated with power resulting in the output data appearing on the DOUTB pin. control and AGC operation, have been assigned adjacent Note that since the default power-up state sets DOUTB low, addresses to minimize the time required to update them. Note bus contention is possible for systems sharing the SPI output that multibyte registers are big endian (the most significant line. To avoid any bus contention, the DOUTB pin can be byte has the lower address) and are updated when a write to the three-stated by setting the fourth control bit in the three-state least significant byte occurs. bit (Reg. 0x3B, Bit 3). This bit can then be toggled to gain access Figure 30 illustrates the timing for a read operation to the SPI to the shared SPI output line. An 8-bit instruction header must port. Although the AD9864 does not require read access for accompany each read and write SPI operation. Only the write proper operation, it is often useful in the product development operation supports an auto-increment mode, which allows the phase or for system authentication. Note that the read-back entire chip to be configured in a single write operation. The enable bit (Register 0x3A, Bit 3) must be set for a read opera- instruction header is shown in Table 7. It includes a read/not- tion with a 3-wire SPI interface. After the peripheral enable write indicator bit, six address bits, and a Don’t Care bit. The (PE) signal goes low, data (PD) pertaining to the instruction data bits immediately follow the instruction header for both header is read on the rising edges of the clock (PC). A read read and write operations. Note that the address and data are operation occurs if the read/not-write indicator is set high. always given MSB first. After the address bits of the instruction header are read, the Table 7. Instruction Header Information eight data bits pertaining to the specified register are shifted out MSB LSB of the data pin (PD) on the falling edges of the next eight clock I7 I6 I5 I4 I3 I2 I1 I0 cycles. If the 4-wire SPI interface is enabled, the eight data bits R/W A5 A4 A3 A2 A1 A0 X will also appear on the DOUTB pin with the same timing rela- tionship as those appearing at PD. After the last data bit is shifted out, the user should return PE high, causing PD to Figure 29 illustrates the timing requirements for a write opera- become three-stated and return to its normal status as an input tion to the SPI port. After the peripheral enable (PE) signal goes pin. Since the auto-increment mode is not supported for read low, data (PD) pertaining to the instruction header is read on operations, an instruction header is required for each register the rising edges of the clock (PC). To initiate a write operation, read operation and PE must return high before initiating the the read/not-write bit is set low. After the instruction header is next read operation. read, the eight data bits pertaining to the specified register are shifted into the data pin (PD) on the rising edges of the next t CLK t S t H PE t t HI LOW PC t DS t DH DON'T A5 A4 A0 D7 D6 D1 D0 PD R/W CARE Figure 29. SPI Write Operation Timing Rev. 0 | Page 17 of 44 04319-0-029 AD9864 t CLK t S PE t t HI LOW PC t t t DS DV EZ t DH DON'T PD R/W A5 A1 A0 D7 D6 D1 D0 CARE DON'T T DON'T DON'T DON'T DON'T DON'T DOUTB D7 D6 D1 D0 CARE CARE CARE CARE CARE CARE Figure 30. SPI Read Operation Timing SYNCHRONOUS SERIAL INTERFACE (SSI) fashion. In this alternate AGC data mode, the LSB of the byte containing the AGC attenuation is a 0, while the LSB of the The AD9864 provides a high degree of programmability of its byte containing reset and RSSI information is always a 1. SSI output data format, control signals, and timing parameters to accommodate various digital interfaces. In a 3-wire digital In a 2-wire interface, the embedded frame sync bit (EFS) within interface, the AD9864 provides a frame sync signal (FS), a clock the SSICRA register is set to 1. In this mode, the framing output (CLKOUT), and a serial data stream (DOUTA) signal to information is embedded in the data stream, with each eight the host device. In a 2-wire interface, the frame sync informa- bits of data surrounded by a start bit (low) and a stop bit (high), tion is embedded into the data stream, thus only CLKOUT and and each frame ends with at least 10 high bits. FS remains DOUTA output signals are provided to the host device. The SSI either low or three-stated (default), depending on the state of control registers are SSICRA, SSICRB, and SSIORD. Table 8 the SFST bit. Other control bits can be used to invert the frame shows the different bit fields associated with these registers. sync (SFSI), to delay the frame sync pulse by one clock period (SLFS), to invert the clock (SCKI), or to three-state the clock The primary output of the AD9864 is the converted I and Q (SCKT). Note that if EFS is set, SLFS is a Don’t Care. demodulated signal available from the SSI port as a serial bit stream contained within a frame. The output frame rate is equal 24-BIT I AND Q, EAGC = 0, AAGC = X:48 DATA BITS I(23:0) Q(23:0) ) divided by the digital to the modulator clock frequency (fCLK filter’s decimation factor that is programmed in the Decimator 24-BIT I AND Q, EAGC = 1, AAGC = 0:64 DATA BITS Register (0x07). The bit stream consists of an I word followed I(23:0) Q(23:0) ATTN(7:0) SSI(5:0) by a Q word, where each word is either 24 bits or 16 bits long RESET COUNT and is given MSB first in twos complement form. Two optional 16-BIT I AND Q, EAGC = 0, AAGC = X:32 DATA BITS bytes may also be included within the SSI frame following the I(15:0) Q(15:0) Q word. One byte contains the AGC attenuation and the other byte contains both a count of modulator reset events and an 16-BIT I AND Q, EAGC = 0, AAGC = 0:32 DATA BITS I(15:0) Q(15:0) ATTN(7:0) SSI(5:0) estimate of the received signal amplitude (relative to full scale of the AD9864’s ADC). Figure 31 illustrates the structure of the 16-BIT I AND Q, EAGC = 1, AAGC = 1:40 DATA BITS SSI data frames in a number of SSI modes. I(15:0) Q(15:0) ATTN(7:1) 0 I(15:0) Q(15:0) SSI(5:1) 1 The two optional bytes are output if the EAGC bit of SSICRA is set. The first byte contains the 8-bit attenuation setting (0 = no RESET COUNT attenuation, 255 = 24 dB of attenuation), while the second byte Figure 31. SSI Frame Structure contains a 2-bit reset field and 6-bit received signal strength The SSIORD register controls the output bit rate (f ) of the field. The reset field contains the number of modulator reset CLKOUT serial bit stream. f can be set equal to the modulator clock events since the last report, saturating at 3. The received signal CLKOUT frequency (f ) or an integer fraction of it. It is equal to f strength (RSSI) field is a linear estimate of the signal strength at CLK CLK divided by the contents of the SSIORD register. Note that f the output of the first decimation stage; 60 corresponds to a CLKOUT full-scale signal. should be chosen such that it does not introduce harmful spurs within the pass band of the target signal. Users must verify that The two optional bytes follow the I and Q data as a 16-bit word the output bit rate is sufficient to accommodate the required provided that the AAGC bit of SSICRA is not set. If the AAGC number of bits per frame for a selected word size and decimation bit is set, the two bytes follow the I and Q data in an alternating factor. Idle (high) bits are used to fill out each frame. Rev. 0 | Page 18 of 44 04319-0-030 04319-0-031 AD9864 Table 8. SSI Control Registers Name Width Default Description SSICRA (ADDR = 0x18) AAGC 1 0 Alternate AGC Data Bytes. EAGC 1 0 Embed AGC Data. EFS 1 0 Embed Frame Sync. SFST 1 1 Three-State Frame Sync. SFSI 1 0 Invert Frame Sync. SLFS 1 0 Late Frame Sync (1 = Late, 0 = Early). SCKT 1 1 Three-state CLKOUT. SCKI 1 0 Invert CLKOUT. SSICRB (ADDR = 0x19) 4_SPI 1 0 Enable 4-Wire SPI Interface for SPI Read Operation via DOUTB. DW 1 0 I/Q Data-Word Width (0 = 16 Bit, 1 Bit–24 Bit). Automatically 16-Bit when the AGCV = 1). DS 3 7 FS, CLKOUT, and DOUT Drive Strength. SSIORD (ADDR = 0x1A) DIV 4 1 Output Bit Rate Divisor fCLKOUT = fCLK/SSIORD. Rev. 0 | Page 19 of 44 4_SPI AAGC EAGC DIV_3 EFS DW DIV_2 SFST DS_2 DIV_1 SFSI DS_1 DIV_0 SLFS DS_0 SCKT SCKI AD9864 CLKOUT FS DOUT I15 I0 Q15 Q14 Q0 SCKI = 0, SCKT = 0, SLFS = 0, SFSI = 0, EFS = 0, SFST = 0, EAGC = 0 CLKOUT FS DOUT I15 I0 Q15 Q14 Q0 SCKI = 0, SCKT = 0, SLFS = 1, SFSI = 0, EFS = 0, SFST = 0, EAGC = 0 CLKOUT FS DOUT I15 I0 Q15 Q14 Q0 ATTN7 ATTEN6 RSSI0 SCKI = 0, SCKT = 0, SLFS = 0, SFSI = 0, EFS = 0, SFST = 0, EAGC = 1, AAGC CLKOUT FS HI-Z START START DOUT I15 I8 STOP BIT I7 I0 STOP BIT Q15 BIT BIT IDLE (HIGH) BITS SCKI = 0, SCKT = 0, SLFS = X, SFSI = X, EFS = 1, SFST = 1, EAGC = 0 SCKI = 0, SCKT = 0, SLFS = X, SFSI = X, EFS = 1, SFST = 0, EAGC = 0; AS ABOVE, BUT FS IS LOW Figure 32. SSI Timing for Several SSICRA Settings with 16-Bit I/Q Data Rev. 0 | Page 20 of 44 04319-0-032 AD9864 t Table 9. Number of Bits per Frame for Different SSICR Settings CLK t t HI LOW Number of Bits CLKOUT per t V DW EAGC EFS AAGC Frame FS 0 (16 Bit) 0 0 NA 32 t DV 0 1 NA 49* DOUT I15 I14 1 0 0 48 Figure 33. SSI Timing Parameters for SSI Timing* 1 0 1 40 *Timing parameters also apply to inverted CLKOUT or FS modes, with t DV 1 1 0 69* relative to the falling edge of the CLK and/or FS. 1 1 1 59* The AD9864 also provides the means for controlling the 1 (24 Bit) 0 0 NA 48 switching characteristics of the digital output signals via the DS 0 1 NA 69* (drive strength) field of the SSICRB. This feature is useful in 1 0 0 64 limiting switching transients and noise from the digital output 1 0 1 56 that may ultimately couple back into the analog signal path, 1 1 0 89* potentially degrading the AD9864’s sensitivity performance. 1 1 1 79* Figure 34 and Figure 35 show how the NF can vary as a func- *The number of bits per frame with embedded frame sync (EFS = 1); assume tion of the SSI setting for an IF frequency of 109.65 MHz. The at least 10 idle bits are desired. following two observations can be made from these figures: The maximum SSIORD setting can be determined by the 1. The NF becomes more sensitive to the SSI output drive equation strength level at higher signal bandwidth settings. SSIORD ≤TRUNC[(DecimationFactor)/(No.of Bits per Frame)] (1) 2. The NF is dependent on the number of bits within an SSI frame that become more sensitive to the SSI output drive where TRUNC is the truncated integer value. strength level as the number of bits is increased. As a result, one should select the lowest possible SSI drive strength set- Table 9 lists the number of bits within a frame for 16-bit and 24- ting that still meets the SSI timing requirements. bit output data formats for all of the different SSICR settings. The decimation factor is determined by the contents of Register 0x07. 10.0 9.8 An example helps illustrate how the maximum SSIORD setting 9.6 is determined. Suppose a user selects a decimation factor of 600 16-BIT I/O DATA 9.4 (Register 0x07, K = 0, M = 9) and prefers a 3-wire interface with a dedicated frame sync (EFS = 0) containing 24-bit data 9.2 (DW = 1) with nonalternating embedded AGC data included 9.0 (EAGC = 1, AAGC = 0). Referring to Table 9, each frame will 8.8 24-BIT I/O DATA consist of 64 data bits. Using Equation 1, the maximum 8.6 SSIORD setting is 9 (= TRUNC(600/64)). Thus, the user can 8.4 select any SSIORD setting between 1 and 9. 8.2 16-BIT I/0 DATA w/ DVGA ENABLED Figure 32 illustrates the output timing of the SSI port for several 8.0 1 2 3 4 5 6 7 SSI control register settings with 16-bit I/Q data, while Figure 33 SSI OUTPUT DRIVE STRENGTH SETTING shows the associated timing parameters. Note that the same timing relationship holds for 24-bit I/Q data, with the excep- Figure 34. NF vs. SSI Output Drive Strength (VDDx = 3.0 V, FCLK = 18 MSPS, BW = 10 kHz) tion that I and Q word lengths now become 24 bits. In the default mode of operation, data is shifted out on rising edges of CLKOUT after a pulse equal to a clock period is output from the frame sync (FS) pin. As described above, the output data consists of a 16-bit or 24-bit I sample followed by a 16-bit or 24-bit Q sample, plus two optional bytes containing AGC and status information. Rev. 0 | Page 21 of 44 NOISE FIGURE (dB) 04319-0-033 04319-0-034 AD9864 14 Figure 36 shows the timing relationship between SYNCB and the SSI port’s CLKOUT and FS signals. SYNCB is an asynchro- 13 24-BIT I/O DATA nous active-low signal that must remain low for at least half an 12 input clock period, i.e., 1/(2 × fCLK). CLKOUT remains high while FS remains low upon SYNCB going low. CLKOUT will 16-BIT I/O DATA 11 w/DVGA ENABLED become active within one to two output clock periods upon SYNCB returning high. FS will reappear several output cycles 10 16-BIT I/O DATA later, depending on the digital filter’s decimation factor and the 9 SSIORD setting. Note that for any decimation factor and SSIORD setting, this delay is fixed and repeatable. To verify 8 proper synchronization, the FS signals of the multiple AD9864 devices should be monitored. 7 1 2 3 4 5 6 7 SYNCB SSI OUTPUT DRIVE STRENGTH SETTING CLKOUT Figure 35. NF vs. SSI Output Drive Strength FS (VDDx = 3.0 V, FCLK = 18 MSPS, BW = 75 kHz) Table 10 lists the typical output rise/fall times as a function of DS Figure 36. SYNCB Timing for a 10 pF load. Rise/fall times for other capacitor loads can be INTERFACING TO DSPs determined by multiplying the typical values presented by a scal- The AD9864 connects directly to an Analog Devices program- ing factor equal to the desired capacitive load divided by 10 pF. mable digital signal processor (DSP). Figure 37 illustrates an Table 10. Typical Rise/Fall Times (±25%) with a 10 pF example with the Blackfin® series of ADSP-2153x processors. Capacitive Load for Each DS Setting The Blackfin DSP series of 16-bit products is optimized for DS Typ (ns) telecommunications applications with its dynamic power man- 0 13.5 agement feature, making it well suited for portable radio prod- 1 7.2 ucts. The code compatible family members share the funda- 2 50 mental core attributes of high performance, low power con- 3 3.7 sumption, and the ease-of-use advantages of a microcontroller 4 3.2 instruction set. 5 2.8 AD9864 ADSP-2153x 6 2.3 PC SCK 7 2.0 PE SEL SPI SPI-PORT PD MOSI DOUTBM ISO SYNCRONIZATION USING SYNCB CLKOUT RSCLK SSI SERIAL Many applications require the ability to synchronize one or FS RFS PORT DOUTAD R more AD9864s in a way that causes the output data to be pre- cisely aligned to an external asynchronous signal. For example, Figure 37. Example of AD9864 and ADSP-2153x Interface receiver applications employing diversity often require syn- chronization of multiple AD9864s’ digital outputs. Satellite As shown in Figure 37, AD9864’s synchronous serial interface communication applications using TDMA methods may (SSI) links the receive data stream to the DSP’s serial port require synchronization between payload bursts to compensate (SPORT). For AD9864 setup and register programming, the for reference frequency drift and Doppler effects. device connects directly to ADSP-2153x’s SPI port. Dedicated SYNCB can be used for this purpose. It is an active-low signal select lines (SEL) allow the ADSP-2153x to program and read back registers of multiple devices using only one SPI port. The that clears the clock counters in both the decimation filter and DSP driver code pertaining to this interface is available on the the SSI port. The counters in the clock synthesizers are not reset AD9864 Web page. because it is presumed that the CLK signals of multiple chips would be connected. SYNCB also resets the modulator, result- ing in a large-scale impulse that must propagate through the AD9864’s digital filter and SSI data formatting circuitry before recovering valid output data. As a result, data samples unaf- fected by this SYNCB induced impulse can be recovered 12 output data samples after SYNCB goes high (independent of the decimation factor). Rev. 0 | Page 22 of 44 NOISE FIGURE (dB) 04319-0-035 04319-0-037 04319-0-036 AD9864 input. A complete PLL can be implemented if the synthesizer is used POWER CONTROL with an external loop filter and voltage controlled oscillator (VCO). To allow power consumption to be minimized, the AD9864 possesses numerous SPI programmable power-down and bias The A, B, and R counters can be programmed via the following control bits. The AD9864 powers up with all of its functional registers: LOA, LOB, and LOR. The charge pump output blocks placed into a standby state, i.e., STBY register default is current is programmable via the LOI register from 0.625 mA to 0xFF. Each major block may then be powered up by writing a 0 5.0 mA using the equation to the appropriate bit of the STBY register. This scheme pro- IPUMP = (LOI +1)×0.625 mA (2) vides the greatest flexibility for configuring the IC to a specific application as well as for tailoring the IC’s power-down and An on-chip fast acquire function (enabled by the LOF bit) wake-up characteristics. Table 11 summarizes the function of automatically increases the output current for faster settling each of the STBY bits. Note that when all the blocks are in during channel changes. The synthesizer may also be disabled standby, the master reference circuit is also put into standby, using the LO standby bit located in the STBY register. and thus the current is reduced further by 0.4 mA. TO EXTERNAL Table 11. Standby Control Bits LOOP f f PHASE/ REF REF FILTER Current Wake-Up REF CHARGE ÷R FREQUENCY BUFFER PUMP STBY Bit Reduction Time (ms) DETECTOR 1 Effect (mA) LOR f LO FAST 7: REF Voltage reference OFF; 0.6 <0.1 (CREF ACQUIRE all biasing shut down. = 4.7 nF) LOA, LOB 6: LO LO synthesizer OFF, 1.2 Note 2 f LO A. B LO IOUTL three-state. ÷8/9 FROM COUNTERS BUFFER VCO 5: CKO Clock oscillator OFF. 1.1 Note 2 4: CK 1.3 Note 2 Clock synthesizer OFF, Figure 38. LO Synthesizer IOUTC three-state. Clock buffer OFF if ADC is OFF. The LO (and CLK) synthesizer works in the following manner. 3: GC Gain control DAC OFF. 0.2 Depends The externally supplied reference frequency, f , is buffered REF GCP and GCN three- on C GC and divided by the value held in the R counter. The internal fREF state. is then compared to a divided version of the VCO frequency, 2: LNAMX LNA and Mizer OFF. 8.2 <2.2 CXVM, CXVL, and CXIF fLO. The phase/frequency detector provides UP and DOWN three-state. pulses whose widths vary, depending upon the difference in 1: Unused phase and frequency of the detector’s input signals. The 0: ADC ADC OFF; Clock buffer 9.2 <0.1 UP/DOWN pulses control the charge pump, making current OFF if CLK synthesizer available to charge the external low-pass loop filter when there OFF; VCM three-state; is a discrepancy between the inputs of the PFD. The output of clock to the digital filter the low-pass filter feeds an external VCO whose output fre- halted; digital outputs static. quency, fLO, is driven such that its divided down version, fLO, NOTES matches that of fREF, thus closing the feedback loop. 1 When all blocks are in standby, the master reference circuit is also put into standby, and thus the current is further reduced by 0.4 mA. The synthesized frequency is related to the reference frequency 2 Wake-up time is dependent on programming and/or external components. and the LO register contents as follows: f = (8× LOB + LOA)/ LOR× f (3) LO REF LO SYNTHESIZER The LO synthesizer shown in Figure 38 is a fully programmable Note that the minimum allowable value in the LOB register is 3 phase-locked loop (PLL) capable of 6.25 kHz resolution at and its value must always be greater than that loaded into LOA. input frequencies up to 300 MHz and reference clocks of up to An example may help illustrate how the values of LOA, LOB, and 25 MHz. It consists of a low noise digital phase-frequency LOR can be selected. Consider an application employing a 13 detector (PFD), a variable output current charge pump (CP), a MHz crystal oscillator, i.e., fREF = 13 MHz, with the requirement 14-bit reference divider, programmable A and B counters, and that f = 100 kHz and f = 143 MHz, i.e., high side injection REF LO a dual-modulus 8/9 prescaler. with f = 140.75 MHz and f = 18 MSPS. LOR is selected to be IF CLK The A (3-bit) and B (13-bit) counters, in conjunction with the 130 such that f = 100 kHz. The N-divider factor is 1430, which REF dual 8/9 modulus prescaler, implement an N divider with N = 8 can be realized by selecting LOB = 178 and LOA = 6. × B + A. In addition, the 14-bit reference counter (R Counter) allows selectable input reference frequencies, fREF, at the PFD Rev. 0 | Page 23 of 44 04319-0-038 AD9864 The stability, phase noise, spur performance, and transient is 3I , and so forth, up to eight times the minimum output cur- 0 response of the AD9864’s LO (and CLK) synthesizers are rent. If the nominal charge pump current is more than the determined by the external loop filter, the VCO, the N-divide minimum value, i.e., LOI > 0, the preceding rule is only applied factor, and the reference frequency, fREF. A good overview of the if it results in an increase in the instantaneous charge pump theory and practical implementation of PLL synthesizers (fea- current. If the charge pump current is set to its lowest value tured as a three-part series in Analog Dialogue) can be found (LOI = 0) and the fast acquire circuit is enabled, the instantane- on the Analog Devices website. Also, a free software copy of the ous charge pump current will never fall below 2I0 when the Analog Devices’ ADIsimPLL, a PLL synthesizer simulation pulsewidth is less than T. Thus, the charge pump current when tool, is available at www.analog.com. Note that the ADF4112 fast acquire is enabled is given by model can be used as a close approximation to the AD9864’s I = I ×[1 = Max(1,LOI,Pulsewidth /T )] (4) PUMP–FA 0 LO synthesizer when using this software tool. The recommended setting for LOFA is LOR/16. Choosing a LOP 84kΩ larger value for LOFA will increase T. Thus, for a given phase LO BUFFER difference between the LO input and the fREF input, the instan- ~VDDL/2 LON taneous charge pump current will be less than that available for FREF TO MIXER a LOFA value of LOR/16. Similarly, a smaller value for LOFA LO PORT will decrease T, making more current available for the same 500Ω 500Ω phase difference. In other words, a smaller value of LOFA will 1.75V BIAS enable the synthesizer to settle faster in response to a frequency hop than will a large LOFA value. Care must be taken to choose NOTES a value for LOFA that is large enough (values greater than 4 1. ESD DIODE STRUCTURES OMITTED FOR CLARITY. 2. FREF STBY SWITCHES SHOWN WITH LO SYNTHESIZER ON. recommended) to prevent the loop from oscillating back and forth in response to a frequency hop. Figure 39. Equivalent Input of LO and REF Buffers Table 12. SPI Registers Associated with LO Synthesizer Figure 39 shows the equivalent input structures of the synthe- Address Bit Break– Default sizers’ LO and REF buffers (excluding the ESD structures). The (Hex) down Width Value Name LO input is fed to the LO synthesizer’s buffer as well as the LO 0x00 (7:0) 1 0xFF STBY port of the AD9864’s mixer. Both inputs are self-biasing and 0x08 (5:0) 6 0x00 LOR (13:8) thus tolerate ac-coupled inputs. The LO input can be driven 0x09 (7:0) 8 0x38 LOR (7:0) with a single-ended or differential signal. Single-ended dc- 0x0A (7:5) 3 0x5 LOA coupled inputs should ensure sufficient signal swing above and (4:0) 5 0x00 LOB (12:8) below the common-mode bias of the LO and REF buffers (i.e., 0x0B (7:0) 8 0xiD LOB(7:0) 1.75 V and VDDL/2). Note that the fREF input is slew rate 0x0C (6) 1 0 LOF dependent and must be driven with input signals exceeding (5) 1 0 LOINV 7.5 V/µs to ensure proper synthesizer operation. If this condi- (4:2) 3 0 LOI tion cannot be met, an external logic gate can be inserted prior (1:0) 2 0 LOTM to the f input to square up the signal, thus allowing an f 0x0D (3:0) 4 0x0 LOFA(13:8) REF REF input frequency approaching dc. 0x0E (7:0) 8 0x04 LOFA(7:0) FAST ACQUIRE MODE The fast acquire circuit attempts to boost the output current CLOCK SYNTHESIZER when the phase difference between the divided-down LO, i.e., The clock synthesizer is a fully programmable integer-N PLL fLO, and the divided-down reference frequency, i.e., fREF, exceeds capable of 2.2 kHz resolution at clock input frequencies up to the threshold determined by the LOFA register. The LOFA 18 MHz and reference frequencies up to 25 MHz. It is similar register specifies a divisor for the fREF signal that determines the to the LO synthesizer described in Figure 38 with the following period (T) of this divided-down clock. This period defines the exceptions: time interval used in the fast acquire algorithm to control the charge pump current. • It does not include an 8/9 prescaler nor an A counter. Assume for the moment that the nominal charge pump current • It includes a negative-resistance core that, when used in is at its lowest setting, i.e., LOI = 0, and denote this minimum conjunction with an external LC tank and varactor, serves current by I0. When the output pulse from the phase compara- as the VCO. tor exceeds T, the output current for the next pulse is 2I0. When the pulse is wider than 2T, the output current for the next pulse Rev. 0 | Page 24 of 44 04319-0-039 AD9864 The 14-bit reference counter and 13-bit N-divider counter can be CLK source or VCO is used, the clock oscillator must be programmed via registers CKR and CKN. The clock frequency, disabled via the CKO standby bit. f , is related to the reference frequency by the equation CLK The phase noise performance of the clock synthesizer is f =(CKN /CKR × f) (5) dependent on several factors, including the CLK oscillator IBIAS CLK REF setting, charge pump setting, loop filter component values, and The charge pump current is programmable via the CKI register internal fREF setting. Figure 41 and Figure 42 show how the from 0.625 mA to 5.0 mA using the equation measured phase noise attributed to the clock synthesizer varies (relative to an external f ) as a function of the I setting and CLK BIAS I =() CKI +1 ×0.625 mA (6) PUMP charge pump setting for a –31 dBm IFIN signal at 73.35 MHz with an external LO signal at 71.1 MHz. Figure 41 shows that The fast acquire subcircuit of the charge pump is controlled by the optimum phase noise is achieved with the highest I BIAS the CKFA register in the same manner the LO synthesizer is (CKO) setting, while Figure 42 shows that the higher charge controlled by the LOFA register. An on-chip lock detect func- pump values provide the optimum performance for the given tion (enabled by the CKF bit) automatically increases the out- loop filter configuration. The AD9864 clock synthesizer and put current for faster settling during channel changes. The syn- oscillator were set up to provide an fCLK of 18 MHz from an thesizer may also be disabled using the CK standby bit located external f of 16.8 MHz. The following external component REF in the STBY register. values were selected for the synthesizer: R = 390 Ω, R = 2 kΩ, F D VDDC = 3.0V C = 0.68 µF, C = 0.1 µF, C = 91 pF, L = 1.2 µH, and C Z P OSC OSC VAR LOOP = Toshiba 1SV228 Varactor. R BIAS FILTER C OSC L R OSC D 0 R 0.1µF –10 F C P C VAR –20 C Z –30 –40 15 19 20 –50 CLKP CLKN IOUTC –60 AD9864 –70 V = VDDC – R × I > 1.6V CM BIAS BIAS –80 1/2 f > 1/{2π× (L × (C ||C )) } CKO = 2 OSC OSC VARACTOR OSC –90 CK0 = 0 CKO = 3 –100 CKO = 1 –110 EXT CLK CLK OSC. BIAS I = 0.15mA, 0.25mA, BIAS 0.40mA, OR 0.65mA –120 2 –130 –140 0 –25 –20 –15 –10 –5 5 10 15 20 25 Figure 40. External Loop Filter, Varactor, and LC Tank Are Required to Realize a Complete Clock Synthesizer FREQUENCY OFFSET (kHz) Figure 41. CLK Phase Noise vs. IBIAS Setting (CKO) (IF = 73.35 MHz, IF = 71.1 MHz, IFIN = –31 dBm, fCLK = 18 MHz, fREF = 16.8 MHz) The AD9864 clock synthesizer circuitry includes a negative (CLK SYN Settings: CKI = 7, CLR = 56, and CLN = 60 with fREF = 300 kHz) resistance core so that only an external LC tank circuit with a 0 varactor is needed to realize a voltage controlled clock oscillator –10 (VCO). Figure 40 shows the external components required to –20 complete the clock synthesizer along with the equivalent input –30 circuitry of the CLK input. The resonant frequency of the VCO –40 is approximately determined by L and the series equivalent –50 OSC –60 capacitance of C and C . As a result, L , C , and C OSC VAR OSC OSC VAR –70 should be selected to provide a sufficient tuning range to ensure –80 CP = 0 proper locking of the clock synthesizer. –90 CP = 2 CP = 4 –100 CP = 6 The bias, IBIAS, of the negative-resistance core has four pro- –110 EXT CLK grammable settings. Lower equivalent Q of the LC tank circuit –120 may require a higher bias setting of the negative-resistance core –130 –140 to ensure proper oscillation. R should be selected so the BIAS –25 –20 –15 –10 5 0 5 10 15 20 25 common-mode voltage at CLKP and CLKN is approximately FREQUENCY OFFSET (kHz) 1.6 V. The synthesizer may be disabled via the CK standby bit Figure 42. CLK Phase Noise vs. IBIAS Setting (CKO) (IF = 73.35 MHz, to allow the user to employ an external synthesizer and/or VCO IF = 71.1 MHz, IFIN = –31 dBm, fCLK = 18 MHz, fREF = 16.8 MHz) (CLK SYN Settings: CKO Bias = 3, CKR = 56, and CKN = 60 with fREF = 300 kHz in place of those resident on the IC. Note that if an external Rev. 0 | Page 25 of 44 04319-0-040 dBc/Hz dBc/Hz 04319-0-042 04319-0-041 AD9864 600 Table 13. SPI Registers Associated with CLK Synthesizer Address Bit Default 550 (Hex) Breakdown Width Value Name 0x00 (7:0) 8 0xFF STBY 500 0x01 (3:2) 2 0 CKOB 0x10 (5:0) 6 00 CKR (13:8) 450 0x11 (7:0) 8 0x38 CKR (7:0) 0x12 (4:0) 5 0x00 CKN (12:8) 400 0x13 (7:0) 8 0x3C CKN (7:0) 0x14 (6) 1 0 CKF 350 (5) 1 0 CKINV (4:2) 3 0 CKI (1:0) 1 0 CKTM 300 0 50 100 150 200 250 300 350 0x15 (3:0) 4 0x0 CKFA (13:8) FREQUENCY (MHz) 0x16 (7:0) 8 0x04 CKFA (7:0) Figure 44. The Shunt Input Resistance vs. the Frequency of the AD9864’s IF1 Input 2.5 IF LNA/MIXER The AD9864 contains a single-ended LNA followed by a Gil- 2.0 bert-type active mixer, shown in Figure 43 with the required external components. The LNA uses negative shunt feedback to 1.5 set its input impedance at the IFIN pin, thus making it depend- ent on the input frequency. It can be modeled as approximately 370 Ω||1.4 pF (±20%) below 100 MHz. Figure 44 and Figure 45 1.0 show the equivalent input impedance versus frequency charac- teristics of the AD9864. The increase in shunt resistance versus 0.5 frequency can be attributed to the reduction in bandwidth, thus the amount of negative feedback of the LNA. Note that the 0 input signal into IFIN should be ac-coupled via a 10 nF capaci- 0 50 100 150 200 250 300 350 FREQUENCY (MHz) tor since the LNA input is self-biasing. Figure 45. The Shunt Capacitance vs. the Frequency of the AD9864’s IF1 Input 2.7V TO 3.6V The mixer’s differential LO port is driven by the LO buffer 50Ω stage shown in Figure 43, which can be driven single-ended or differential. Since it is self-biasing, the LO signal level can be L L ac-coupled and range from 0.3 V p-p to 1.0 V p-p with negligi- C ble effect on performance. The mixer’s open-collector outputs, VDDI MXOP MXON MXOP and MXON, drive an external resonant tank consisting of a differential LC network tuned to the IF of the band-pass Σ-∆ ADC, i.e., f = f /8. The two inductors provide a dc IF2_ADC CLK bias path for the mixer core via a series resistor of 50 Ω, which is included to dampen the common-mode response. The R BIAS CXVL mixer’s output must be ac-coupled to the input of the band- LO INPUT = 0.3V p-p TO pass Σ-∆ ADC, IF2P, and IF2N via two 100 pF capacitors to R GAIN 1.0V p-p ensure proper tuning of the LC center frequency. MULTI-TANH CXIF V–I STAGE R F The external differential LC tank forms the resonant element for CXVM the first resonator of the band-pass Σ-∆ modulator, and so must IFIN be tuned to the f /8center frequency of the modulator. The CLK DC SERVO inductors should be chosen such that their impedance at fCLK/8 is LOOP about 140, i.e., L = 180/fCLK. An accuracy of 20% is considered to Figure 43. Simplified Schematic of AD9864’s LNA/Mixer be adequate. For example, at fCLK = 18 MHz, L = 10 µH is a good choice. Once the inductors have been selected, the required tank capacitance may be calculated using the relation Rev. 0 | Page 26 of 44 04319-0-043 CAPACITANCE (pF) RESISTANCE (Ω) 04319-0-044 04319-0-045 AD9864 EXTERNAL f /8 = 1/[2× π×() 2L ×C ] LC CLK For example, at f = 18 MHz and L = 10 µH, a capacitance of CLK IF2P f = 13 MSPS TO 26 MSPS CLK 250 pF is needed. However, in order to accommodate an induc- RC SC NINE- RESO- RESO- LEVEL IF2N tor tolerance of ±10%, the tank capacitance must be adjustable NATOR NATOR FLASH MXOP MXON from 227 pF to 278 pF. Selecting an external capacitor of 180 pF ensures that even with a 10% tolerance and stray capacitances as high as 30 pF, the total capacitance will be less than the TO DIGITAL ESL DAC1 FILTER minimum value needed by the tank. Extra capacitance is sup- plied by the AD9864’s on-chip programmable capacitor array. MIXER OUTPUT GAIN Since the programming range of the capacitor array is at least CONTROL 160 pF, the AD9864 has plenty of range to make up for the tol- Figure 46. Equivalent Circuit of Sixth Order Band-Pass Σ-∆ Modulator erances of low cost external components. Note that if f is CLK increased by a factor of 1.44 MHz to 26 MHz so that fCLK/8 becomes 3.25 MHz, reducing L and C by approximately the Figure 47 shows the measured power spectral density measured at same factor (i.e., L = 6.9 µH and C = 120 pF) still satisfies the the output of the undecimated band-pass Σ-∆ modulator. Note requirements stated above. that the wide dynamic range achieved at the center frequency, A 16 dB step attenuator is also included within the LNA/mixer f /8, is achieved once the LC and RC resonators of the Σ-∆ CLK circuitry to prevent large signals (i.e., > –18 dBm) from over- modulator have been successfully tuned. The out-of-band noise is driving the Σ-∆ modulator. In such instances, the Σ-∆ modula- removed by the decimation filters following quadrature mixer. tor will become unstable, thus severely desensitizing the 0 receiver. The 16 dB step attenuator can be invoked by setting –2dBFS OUTPUT f = 18MHz CLK –10 NBW = 3.3kHz the ATTEN bit (Register 0x03, Bit 7), causing the mixer gain to –20 be reduced by 16 dB. The 16 dB step attenuator could be used in applications in which a potential target or blocker signal –30 could exceed the IF input clip point. Although the LNA will be –40 driven into compression, it may still be possible to recover the –50 desired signal if it is FM. Refer to Table 14 to see the gain com- –60 pression characteristics of the LNA and mixer with the 16 dB –70 attenuator enabled. –80 –90 Table 14. SPI Registers Associated with LNA/Mixer Address Bit Default –100 0 12 3 4 5 6 7 8 9 (Hex) Breakdown Width Value Name FREQUENCY (MHz) 0x00 (7:0) 8 0xFF STBY Figure 47. Measured Undecimated Spectral Output of Σ-∆ 0x03 (7) 1 0 ATTEN Modulator ADC with fCLK = 18 MSPS and Noise Bandwidth of 3.3 kHz The signal transfer function of the AD9864 possesses inherent anti-alias filtering by virtue of the continuous-time portions of BAND-PASS ∑-∆ ADC the loop filter in the band-pass Σ-∆ modulator. Figure 48 illus- The ADC of the AD9864 is shown in Figure 46. The ADC con- trates this property by plotting the nominal signal transfer tains a sixth order multibit band-pass Σ-∆ modulator that function of the ADC for frequencies up to 2f . The notches CLK achieves very high instantaneous dynamic range over a narrow that naturally occur for all frequencies that alias to the f /8 CLK frequency band. The loop filter of the band-pass Σ-∆ modulator pass band are clearly visible. Even at the widest bandwidth set- consists of two continuous-time resonators followed by a discrete ting, the notches are deep enough to provide greater than 80 dB time resonator, with each resonator stage contributing a pair of of alias protection. Thus, the wideband IF filtering require- complex poles. The first resonator is an external LC tank, while ments preceding the AD9864 will be determined mostly by the the second is an on-chip active RC filter. The output of the LC mixer’s image band, which is offset from the desired IF input resonator is ac-coupled to the second resonator input via 100 pF frequency by f /4 (i.e., 2 × f /8) rather than any aliasing CLK CLK capacitors. The center frequencies of these two continuous-time associated with the ADC. resonators must be tuned to fCLK/8 for the ADC to function prop- erly. The center frequency of the discrete-time resonator auto- matically scales with fCLK, thus no tuning is required. Rev. 0 | Page 27 of 44 dBFS/NBW 04319-0-048 04319-0-047 AD9864 0 When tuning the LC tank, the sampling clock frequency must be stable and the LNA/mixer, LO synthesizer, and ADC must –10 all be placed in standby. Large LO and IF signals present at the –20 inputs of the AD9864 can corrupt the calibration. These signals should be minimized or disabled during the calibration –30 NOTCH AT ALL ALIAS FREQUENCIES sequence. Tuning is triggered when the ADC is taken out of –40 standby if the TUNE_LC bit of Register 0x1C has been set. This bit will clear when the tuning operation is complete (less than –50 6 ms). The tuning codes can be read from the 3-bit CAPL1 –60 (0x1D) and the 6-bit CAPL0 (0x1E) registers. –70 In a similar manner, tuning of the RC resonator is activated if –80 the TUNE_RC bit of Register 0x1C is set when the ADC is 0 0.5 1.0 1.5 2.0 taken out of standby. This bit will clear when tuning is com- NORMALIZED FREQUENCY (RELATIVE TO f ) OUT plete. The tuning code can be read from the CAPR (0x1F) Figure 48. Signal Transfer Function of the Band-Pass Σ-∆ register. Setting both the TUNE_LC and TUNE_RC bits tunes Modulator from 0 fCLK to 2fCLK the LC tank and the active RC resonator in succession. During tuning, the ADC is not operational and neither data nor a clock Figure 49 shows the nominal signal transfer function magni- is available from the SSI port. Table 15 lists the recommended tude for frequencies near the fCLK/8 pass band. The width of the sequence of the SPI commands for tuning the ADC, and pass band determines the transfer function droop, but even at Table 16 lists all of the SPI registers associated with band-pass the lowest oversampling ratio (48) where the pass band edges Σ-∆ ADC. are at ±fCLK/192 (±0.005 fCLK), the gain variation is less than 0.5 dB. Note that the amount of attenuation offered by the sig- Table 15. Tuning Sequence nal transfer function near f /8 should also be considered when CLK Address (Hex) Value Comments determining the narrow-band IF filtering requirements preced- 0x00 0x45 LO synthesizer, LNA/mixer, and ing the AD9864. ADC are placed in standby.* 0x1C 0x03 Set TUNE_LC and TUNE_RC. Wait 0 for CLK to stabilize if CLK synthesizer used. 0x00 0x44 Take the ADC out of standby. Wait –5 for 0x1C to clear (<6 ms). LNA/mixer can now be taken out of standby *If external CLK VCO or source used, the CLK oscillator must also be disabled. –10 Large IF or LO signals can corrupt the calibration; these signals should be disabled during the calibration sequence. –15 Table 16. SPI Registers Associated with Band-Pass Σ-∆ ADC Address Default (Hex) Value Width Value Name –20 –0.10 –0.05 0 0.05 0.10 0x00 (7:0) 8 0xFF STBY NORMALIZED FREQUENCY (RELATIVE TO f ) CLK 0x1C (1) 1 0 TUNE_LC (0) 1 0 TUNE_RC Figure 49. Magnitude of the ADC’s Signal Transfer Function near f /8 CLK 0x1D (2:0) 3 0 CAPL1 (2:0) Tuning of the Σ-∆ modulator’s two continuous-time resonators 0x1E (5:0) 6 0x00 CAPL1 (5:0) is essential in realizing the ADC’s full dynamic range and must 0x1F (7:0) 8 0x00 CAPR be performed upon system startup. To facilitate tuning of the LC tank, a capacitor array is internally connected to the MXOP Once the AD9864 has been tuned, the noise figure degradation and MXON pins. The capacitance of this array is programmable attributed solely to the temperature drift of the LC and RC from 0 pF to 200 pF ± 20% and can be programmed either resonators is minimal. Since the drift of the RC resonator is automatically or manually via the SPI port. The capacitors of actually negligible compared to that of the LC resonator, the the active RC resonator are similarly programmable. Note that external L and C components’ temperature drift characteristics the AD9864 can be placed in and out of its standby mode with- tend to dominate. Figure 50 shows the degradation in noise out retuning since the tuning codes are stored in the SPI Registers. figure as the product of the LC value is allowed to vary from –12.5% to +12.5%. Note that the noise figure remains relatively Rev. 0 | Page 28 of 44 dB dB 04319-0-050 04319-0-049 AD9864 constant over a ±3.5% range (i.e., ±35,000 ppm), suggesting Note that signals falling around frequency offsets that are odd that most applications will not be required to retune over the integer multiples of f /2 (i.e., 10 kHz, 30 kHz, and 50 kHz) OUT operating temperature range. will fall back into the transition band of the digital filter. 12 0 –20 BW = 75kHz ±5.0kHz PASS BAND 11 FOLD- ING –40 POINT –88dB –88dB 10 –60 –101dB BW = 30kHz –103dB –80 9 BW = 10kHz –100 –120 120 8 –15 –10 –501 5015 03 10 200 40 50 60 70 80 90 100 FREQUENCY (kHz) LC ERROR (%) Figure 52. Decimation Filter Frequency Response for Figure 50. Typical Noise Figure Degradation from L and C f = 20 kSPS (f = 18 MHz, OSR = 900) Component Drift (fCLK = 18 MSPS, fIF = 73.3501 MHz) OUT CLK Figure 53 shows the response of the decimation filter with a DECIMATION FILTER decimation factor of 48 and a sampling clock rate of 26 MHz. The decimation filter shown in Figure 51 consists of an f /8 CLK The alias attenuation is at least 94 dB and occurs for frequen- complex mixer and a cascade of three linear phase FIR filters: cies at the edges of the fourth alias band. The difference DEC1, DEC2, and DEC3. DEC1 downsamples by a factor of 12 between the alias attenuation characteristics of Figure 52 and using a fourth order comb filter. DEC2 also uses a fourth order those of Figure 53 is due to the fact that the third decimation comb filter, but its decimation factor is set by the M field of stage decimates by a factor of 5 for Figure 52 compared with a Register 0x07. DEC3 is either a decimate-by-5 FIR filter or a factor of 4 for Figure 53. decimate-by-4 FIR filter, depending on the value of the K bit within Register 0x07. Thus, the composite decimation factor 0 can be set to either 60 × M or 48 × M for K equal to 0 or 1, respectively. –20 ±135.466kHz PASS BAND The output data rate (fOUT) is equal to the modulator clock fre- –40 quency (fCLK) divided by the digital filter’s decimation factor. Due to the transition region associated with the decimation –60 filter’s frequency response, the decimation factor must be selected such that f is equal to or greater than twice the sig- –98dB OUT –80 nal bandwidth. This ensures low amplitude ripple in the pass –94dB –115dB band along with the ability to provide further application- –100 specific digital filtering prior to demodulation. –120 MK COS 0 0.5 1.0 1.5 2.0 2.5 FREQUENCY (MHz) EQUENCY I DEC1 DEC2 DEC3 DATA COMPLEX SIN Figure 53. Decimation Filter Frequency Response for 4 DATA TO FROM Σ-∆ 4 4 FIR SINC SINC M + 1 12 OR MODULATOR SSI PORT fOUT = 541.666 kSPS (fCLK = 26 MHz, OSR = 48) FILTER FILTER FILTER Q 5 Figure 54 and Figure 55 show expanded views of the pass band Figure 51. Decimation Filter Architecture for the two possible configurations of the third decimation fil- ter. When decimating by 60n (K = 0), the pass-band gain varia- Figure 52 shows the response of the decimation filter at a deci- tion is 1.2 dB; when decimating by 48n (K = 1), the pass-band mation factor of 900 (K = 0, M = 14) and a sampling clock fre- gain variation is 0.9 dB. Normalization of full scale at band quency of 18 MHz. In this example, the output data rate (f ) OUT center is accurate to within 0.14 dB across all decimation is 20 kSPS, with a usable complex signal bandwidth of 10 kHz modes. Figure 56 and Figure 57 show the folded frequency centered around dc. As this figure shows, the first and second response of the decimator for K = 0 and K = 1, respectively. alias bands (occurring at even integer multiples of fOUT/2) have the least attenuation but provide at least 88 dB of attenuation. Rev. 0 | Page 29 of 44 NF (dB) 04319-0-051 04319-0-052 dB dB 04319-0-054 04319-0-053 AD9864 3 0 2 –20 PASS-BAND GAIN FREQUENCY = 1.2dB 1 –40 0 –60 –1 –80 MIN ALIAS ATTN = 97.2dB –2 –100 –3 –120 0 0.250 0 0.50 0.125 0.25 NORMALIZED FREQUENCY (RELATIVE TO f ) NORMALIZED FREQUENCY (RELATIVE TO f ) OUT OUT Figure 54. Pass-Band Frequency Response of the Decimator for K = 0 Figure 57. Folded Decimator Frequency Response for K = 1 3 VARIABLE GAIN AMPLIFIER OPERATION WITH AUTOMATIC GAIN CONTROL 2 The AD9864 contains both a variable gain amplifier (VGA) and a PASS-BAND GAIN VARIATION = 0.9dB digital VGA (DVGA) along with all of the necessary signal estimation 1 and control circuitry required to implement automatic gain control (AGC), as shown in Figure 58. The AGC control circuitry provides a 0 high degree of programmability, allowing users to optimize the AGC response as well as the AD9864’s dynamic range for a given applica- –1 tion. The VGA is programmable over a 12 dB range and implemented within the ADC by adjusting its full-scale reference level. Increasing the –2 ADC’s full scale is equivalent to attenuating the signal. An additional 12 dB of digital gain range is achieved by scaling the output of the –3 0.250 0 0.125 decimation filter in the DVGA. Note that a slight increase in the supply NORMALIZED FREQUENCY (RELATIVE TO f ) OUT current (i.e., 0.67 mA) is drawn from VDDI and VDDF as the VGA changes from 0 dB to 12 dB attenuation. Figure 55. Pass-Band Frequency Response of the Decimator for K = 1 0 The purpose of the VGA is to extend the usable dynamic range of the AD9864 by allowing the ADC to digitize a desired signal over a large –20 input power range as well as recover a low level signal in the presence of larger unfiltered interferers without saturating or clipping the ADC. –40 The DVGA is most useful in extending the dynamic range in narrow- band applications requiring a 16-bit I and Q data format. In these –60 applications, quantization noise resulting from internal truncation to 16 bits as well as external 16-bit fixed point post processing can –80 MIN ALIAS ATTN = 87.7dB degrade the AD9864’s effective noise figure by 1 dB or more. –100 The DVGA is enabled by writing a 1 to the AGCV field. The VGA (and the DVGA) can operate in either a user controlled variable gain –120 mode or automatic gain control (AGC) mode. It is worth noting that 0.50 0 0.25 the VGA imparts negligible phase error upon the desired signal as its NORMALIZED FREQUENCY (RELATIVE TO f ) OUT gain is varied over a 12 dB range. This is due to the bandwidth of the Figure 56. Folded Decimator Frequency Response for K = 0 VGA being far greater than the down converted desired signal (cen- tered about fCLK/8) and remaining relatively independent of gain setting. As a result, phase modulated signals should experience mini- mal phase error as the AGC varies the VGA gain while tracking an interferer or the desired signal under fading conditions. Note that the envelope of the signal will still be affected by the AGC settings. Rev. 0 | Page 30 of 44 dB dB dB 04319-0-055 04319-0-057 04319-0-056 dB 04319-0-058 AD9864 I/Q DATA TO SSI DEC2 Σ∆ - ADC DEC1 C1 AND DVGA FS ÷12 DEC3 AGCR REF LEVEL I+ Q SELECT 1 + K LARGER –1 (1 – Z ) I+ Q AGCA/AGCD AGCV CV SCALING SETTING VGA DAC RSSI DATA TO SSI GCP C DAC Figure 58. Functional Block Diagram of VGA and AGC ing at the gain control pin (GCP). For applications implement- VARIABLE GAIN CONTROL ing automatic gain control, the DAC’s output resistance can be The variable gain control is enabled by setting the AGCR field reduced by a factor of 9 to decrease the attack time of the AGC of Register 0x06 to 0. In this mode, the gain of the VGA (and response for faster signal acquisition. An external capacitor, the DVGA) can be adjusted by writing to the 16-bit AGCG CDAC, from GCP to analog ground is required to smooth the register. The maximum update rate of the AGCG register via DAC’s output each time it updates as well as to filter wideband the SPI port is fCLK/240. The MSB of this register is the bit that noise. Note that CDAC, in combination with the DAC’s pro- enables 16 dB of attenuation in the mixer. This feature allows grammable output resistance, sets the –3 dB bandwidth and the AD9864 to cope with large level signals beyond the VGA’s time constant associated with this RC network. range (i.e., > –18 dBm at LNA input) to prevent overloading of the ADC. A linear estimate of the received signal strength is performed at the output of the first decimation stage (DEC1) and output of The lower 15 bits specify the attenuation in the remainder of the DVGA (if enabled), as discussed in the AGC section. This the signal path. If the DVGA is enabled, the attenuation range data is available as a 6-bit RSSI field within an SSI frame with is from –12 dB to +12 dB since the DVGA provides 12 dB of 60 corresponding to a full-scale signal for a given AGC attenua- digital gain. In this case, all 15 bits are significant. However, tion setting. The RSSI field is updated at fCLK/60 and can be used with the DVGA disabled, the attenuation range extends from with the 8-bit attenuation field (or AGCG attenuation setting) 0 dB to 12 dB and only the lower 14 bits are useful. Figure 59 to determine the absolute signal strength. shows the relationship between the amount of attenuation and the AGC register setting for both cases. The accuracy of the mean RSSI reading (relative to the IF input power) depends on the input signal’s frequency offset relative 12 to the IF frequency since both DEC1 filter’s response as well as ONLY VGA ENABLED the ADC’s signal transfer function attenuate the mixer’s downconverted signal level centered at fCLK/8. As a result, the VGA 6 RANGE estimated signal strength of input signals falling within prox- DVGA AND imity to the IF is reported accurately, while those signals at VGA ENABLED increasingly higher frequency offsets incur larger measurement 0 errors. Figure 60 shows the normalized error of the RSSI read- ing as a function of the frequency offset from the IF frequency. DVGA Note that the significance of this error becomes apparent when –6 RANGE determining the maximum input interferer (or blocker) levels with the AGC enabled. –12 0000 1FFF 3FFF 5FFF 7FFF AGCG SETTING (HEX) Figure 59. AGC Gain Range Characteristics vs. AGCG Register Setting with and without DVGA Enabled Referring to Figure 58, the gain of the VGA is set by an 8-bit control DAC that provides a control signal to the VGA appear- Rev. 0 | Page 31 of 44 AGC ATTENUATION (dB) 04319-0-060 04319-0-059 AD9864 0 Signal estimation after the first decimation stage allows the AGC to cope with out-of-band interferers and in-band signals –3 that could otherwise overload the ADC. Signal estimation after the DVGA allows the AGC to minimize the effects of the 16-bit –6 truncation noise. –9 When the estimated signal level falls within the range of the AGC, the AGC loop adjusts the VGA (or DVGA) attenuation –12 setting so that the estimated signal level is equal to the pro- grammed level specified in the AGCR field. The absolute signal –15 strength can be determined from the contents of the ATTN and RSSI field that is available in the SSI data frame when properly –18 configured. Within this AGC tracking range, the 6-bit value in 0 0.01 0.02 0.03 0.04 0.05 the RSSI field remains constant while the 8-bit ATTN field var- NORMALIZED FREQUENCY OFFSET ((f –f ) f ) IN IF CLK ies according to the VGA/DVGA setting. Note that the ATTN Figure 60. Normalized RSSI Error vs. Normalized IF Frequency Offset value is based on the 8 MSB contained in the AGCG field of Registers 0x03 and 0x04. AUTOMATIC GAIN CONTROL (AGC) A description of the AGC control algorithm and the user The gain of the VGA (and DVGA) is automatically adjusted adjustable parameters follows. First, consider the case in which when the AGC is enabled via the AGCR field of Register 0x06. In this mode, the gain of the VGA is continuously updated at the in-band target signal is bigger than all out-of-band interfer- f /60 in an attempt to ensure that the maximum analog signal ers and the DVGA is disabled. With the DVGA disabled, a CLK control loop based only on the target signal power measured level into the ADC does not exceed the ADC clip level and that after DEC1 is used to control the VGA gain, and the target the rms output level of the ADC is equal to a programmable signal will be tracked to the programmed reference level. If the reference level. With the DVGA enabled, the AGC control loop signal is too large, the attenuation is increased with a propor- also attempts to minimize the effects of 16-bit truncation noise tionality constant determined by the AGCA setting. Large prior to the SSI output by continuously adjusting the DVGA’s AGCA values result in large gain changes, thus rapid tracking gain to ensure maximum digital gain while not exceeding the programmable reference level. of changes in signal strength. If the target signal is too small relative to the reference level, the attenuation is reduced; but This programmable level can be set at 3 dB, 6 dB, 9 dB, 12 dB, now the proportionality constant is determined by both the and 15 dB below the ADC saturation (clip) level by writing AGCA and AGCD settings. The AGCD value is effectively values from 1 to 5 to the 3-bit AGCR field. Note that the ADC subtracted from AGCA, so a large AGCD results in smaller clip level is defined to be 2 dB below its full scale (i.e., –18 dBm gain changes and thus slower tracking of fading signals. at the LNA input for a matched input and maximum attenua- The 4-bit code in the AGCA field sets the raw bandwidth of the tion). If AGCR is 0, automatic gain control is disabled. Since AGC loop. With AGCA = 0, the AGC loop bandwidth is at its clipping of the ADC input will degrade the SNR performance, the reference level should also take into consideration the peak- minimum of 50 Hz, assuming fCLK = 18 MHz. Each increment of AGCA increases the loop bandwidth by a factor of √2; thus to-rms characteristics of the target (or interferer) signals. the maximum bandwidth is 9 kHz. A general expression for the Referring again to Figure 58, the majority of the AGC loop attack bandwidth is operates in the discrete time domain. The sample rate of the (AGCA / 2) loop is fCLK/60; therefore, registers associated with the AGC ( ) BW = 50× f /18 MHz ×2 Hz (8) A CLK algorithm are updated at this rate. The number of overload and ADC reset occurrences within the final I/Q update rate of the and the corresponding attack time is AD9864, as well as the AGC value (8 MSB), can be read from (AGCA / 2) t = 2.2/(100× π×2 )= 35/ BW (9) the SSI data upon proper configuration. ATTACK A assuming that the loop dynamics are essentially those of a The AGC performs digital signal estimation at the output of the single-pole system. first decimation stage (DEC1) as well as the DVGA output that follows the last decimation stage (DEC3). The rms power of the The 4-bit code in the AGCD field sets the ratio of the attack I and Q signal is estimated by the equation time to the decay time in the amplitude estimation circuitry. Xest[] n = Abs() I[] n + Abs(Q[] n) (7) When AGCD is zero, this ratio is one. Incrementing AGCD multiplies the decay time constant by 21/2, allowing a 180:1 Rev. 0 | Page 32 of 44 MEASURED RSSI ERROR (dB) 04319-0-061 AD9864 128 range in the decay time relative to the attack time. The decay time may be computed from 112 (AGCD / 2) 96 t = t ×2 (10) DECAY ATTACK AGCO = 7 80 Figure 61 shows the AGC response to a 30 Hz pulse-modulated IF burst for different AGCA and AGCD settings. The 3-bit 64 AGCO = 4 value in the AGCO field determines the amount of attenuation 48 added in response to a reset event in the ADC. Each increment in AGCO doubles the weighting factor. At the highest AGCO 32 AGCD = 0 setting, the attenuation will change from 0 dB to 12 dB in 16 approximately 10 µs, while at the lowest setting the attenuation 0 will change from 0 dB to 12 dB in approximately 1.2 ms. Both 0 0.1 0.3 0.7 0.8 0.9 0.2 0.4 0.5 0.6 1.0 times assume f = 18 MHz. Figure 62 shows the AGC attack CLK TIME (ms) time response for different AGCO settings. Figure 62. AGC Response for Different AGCO Settings with f = 18 MSPS, CLK f = 300 kSPS, Decimate by 60 and AGCA = AGCD = 0 AGCA = 0 CLKOUT 96 AGCD = 8 80 Lastly, the AGCF bit reduces the DAC source resistance by at 64 least a factor of 10. This facilitates fast acquisition by lowering 48 the RC time constant that is formed with the external capaci- AGCD = 0 32 tors connected from the GCP pin to ground (GCN pin). For an 16 overshoot-free step response in the AGC loop, the capacitor 0 connected from the GCP pin to the GCN ground pin should be AGCA = 4 96 chosen so that the RC time constant is less than one quarter of 80 the raw loop. Specifically AGCD = 8 64 RC < 1/(8πBW ) (11) 48 AGCD = 0 32 where R is the resistance between the GCP pin and ground 16 (72.5 kΩ ±30% if AGCF = 0, < 8 kΩ if AGCF = 1) and BW is 0 the raw loop bandwidth. Note that with C chosen at this upper AGCA = 8 96 limit, the loop bandwidth increases by approximately 30%. 80 AGCD = 8 Now consider the case described above but with the DVGA 64 enabled to minimize the effects of 16-bit truncation. With the 48 DVGA enabled, a control loop based on the larger of the two 32 estimated signal levels, i.e., output of DEC1 and DVGA, is used AGCD = 0 16 to control the DVGA gain. The DVGA multiplies the output of 0 0 30 40 10 20 50 the decimation filter by a factor of 1 to 4, i.e., 0 dB to 12 dB. TIME (ms) When signals are small, the DVGA gain is 4 and the 16-bit out- put is extracted from the 24-bit data produced by the decima- Figure 61. AGC Response for Different AGCA and AGCD Settings with fCLK = 18 MSPS, fCLKOUT = 20 kSPS, Decimate by 900, and AGCO = 0 tion filter by dropping 2 MSB and taking the next 16 bits. As signals get larger, the DVGA gain decreases to the point where the DVGA gain is 1 and the 16-bit output data is simply the 16 MSB of the internal 24-bit data. As signals get even larger, attenuation is accomplished by the normal method of increas- ing the ADC’s full scale. The extra 12 dB of gain range provided by the DVGA reduces the input-referred truncation noise by 12 dB and makes the data more tolerant of LSB corruption within the DSP. The price paid for this extension to the gain range is that the start of AGC action is 12 dB lower and that the AGC loop will be unstable if its bandwidth is set too wide. The latter difficulty results from the large delay of the decimation filters, DEC2 and DEC3, when one implements a large decimation factor. As a result, given an Rev. 0 | Page 33 of 44 VGA ATTENUATION SETTING 04319-0-062 VGA ATTENUATION SETTING 04319-0-063 AD9864 0 option, the use of 24-bit data is preferable to using the DVGA. Table 17 indicates which AGCA values are reasonable for various decimation factors. The white cells indicate that the –3 (decimation factor/AGCA) combination works well; the light gray cells indicate ringing and an increase in the AGC settling time; and –6 the dark gray cells indicate that the combination results in instability or near instability in the AGC loop. Setting AGCF = 1 improves the –9 time-domain behavior at the expense of increased spectral spreading. –12 Table 17. AGCA Limits if the DVGA Is Enabled AGCA M 4 5 6 7 8 9 10 11 12 13 14 15 –15 0 0.01 0.02 0.03 0.04 0.05 60 0 NORMALIZED FREQUENCY OFFSET = (f –f )/f IN IF CLK 120 1 Figure 63. Maximum Interferer (or Blocker) Input Level vs. Normalized IF Frequency Offset 300 4 540 8 Table 18. SPI Registers Associated with AGC 900 E Address Bit Default (Hex) Breakdown Width Value Name 0x03 (7) 1 0 ATTEN Finally, consider the case of a strong out-of-band interferer (6:0) 7 0x00 AGCG (14:8) (i.e., –18 dBm to –32 dBm for matched IF input) that is larger 0x04 (7:0) 8 0x00 AGCG (7:0) than the target signal and large enough to be tracked by the 0x05 (7:4) 4 0 AGCA control loop based on the output of the DEC1. The ability of (3:0) 4 0x00 AGCO the control loop to track this interferer and set the VGA 0x06 (7) 1 0 AGCV attenuation to prevent clipping of the ADC is limited by the (6:4) 3 0 AGCO accuracy of the digital signal estimation occurring at the output (3) 1 0 AGCF of DEC1. The accuracy of the digital signal estimation is a (2:0) 3 0 AGCR function of the frequency offset of the out-of-band interferer relative to the IF frequency as shown in Figure 60. Interferers at SYSTEM NOISE FIGURE (NF) VERSUS VGA (OR increasingly higher frequency offsets incur larger measurement errors, potentially causing the control loop to inadvertently AGC) CONTROL reduce the amount of VGA attenuation that may result in clip- The AD9864’s system noise figure is a function of the ACG ping of the ADC. Figure 63 shows the maximum measured attenuation and output signal bandwidth. Figure 64 plots the interferer signal level versus the normalized IF offset frequency nominal system NF as a function of the AGC attenuation for (relative to f ) tolerated by the AD9864 relative to its maxi- CLK both narrow-band (20 kHz) and wideband (150 kHz) modes mum target input signal level (0 dBFS = –18 dBm). Note that with fCLK = 18 MHz. Also shown on the plot is the SNR that the increase in allowable interferer level occurring beyond would be observed at the output for a –2 dBFS input. The high 0.04 × fCLK results from the inherent signal attenuation provided dynamic range of the ADC within the AD9864 ensures that the by the ADC’s signal transfer function. system NF increases gradually as the AGC attenuation is increased. In narrow-band (BW = 20 kHz) mode, the system noise figure increases by less than 3 dB over a 12 dB AGC range, while in wideband (BW = 150 kHz) mode, the degrada- tion is about 5 dB. As a result, the highest instantaneous dynamic range for the AD9864 occurs with 12 dB of AGC attenuation, since the AD9864 can accommodate an additional 12 dB peak signal level with only a moderate increase in its noise floor. As Figure 64 shows, the AD9864 can achieve an SNR in excess of 100 dB in narrow-band applications. To realize the full performance of the AD9864 in such applications, it is recom- mended that the I/Q data be represented with 24 bits. If 16-bit Rev. 0 | Page 34 of 44 DECIMATION FACTOR RELATIVE TO CLIP POINT (dBFS) 04319-0-064 AD9864 data is used, the effective system NF will increase because of the APPLICATIONS CONSIDERATIONS quantization noise present in the 16-bit data after truncation. Frequency Planning The LO frequency (and/or ADC clock frequency) must be chosen 15 SNR = 90.1dBFS carefully to prevent known internally generated spurs from mixing 14 down along with the desired signal, thus degrading the SNR per- formance. The major sources of spurs in the AD9864 are the ADC 13 clock and digital circuitry operating at 1/3 of fCLK. Thus, the clock BW = 50kHz frequency (fCLK) is the most important variable in determining 12 which LO (and therefore IF) frequencies are viable. BW = 150kHz 11 Many applications have frequency plans that take advantage of SNR = 103.2dB SNR = 82.9dBFS 10 industry-standard IF frequencies due to the large selection of low cost crystal or SAW filters. If the selected IF frequency and BW = 10kHz 9 ADC clock rate result in a problematic spurious component, an SNR = 95.1dBFS alternative ADC clock rate should be selected by slightly modi- 8 0 36 912 fying the decimation factor and CLK synthesizer settings (if VGA ATTENUATION (dB) used) such that the output sample rate remains the same. Also, Figure 64. Nominal System Noise Figure and Peak SNR vs. AGCG Setting (f = IF applications requiring a certain degree of tuning range should 73.35 MHz, f = 18 MSPS, and 24-bit I/Q Data) CLK take into consideration the location and magnitude of these spurs when determining the tuning range as well as optimum Figure 65 plots the nominal system NF with 16-bit output data IF and ADC clock frequency. as a function of AGC in both narrow-band and wideband mode. In wideband mode, the NF curve is virtually unchanged Figure 66 plots the measured in-band noise power as a function relative to the 24-bit output data because the output SNR before of the LO frequency for fCLK = 18 MHz and an output signal truncation is always less than the 96 dB SNR that 16-bit data bandwidth of 150 kHz when no signal is present. Any LO can support. However, in narrow-band mode, where the output frequency resulting in large spurs should be avoided. As this SNR approaches or exceeds the SNR that can be supported with figure shows, large spurs result when the LO is fCLK/8 = 2.25 16-bit data, the degradation in system NF is more severe. Fur- MHz away from a harmonic of 18 MHz , i.e., n f ± f /8. CLK CLK thermore, if the signal processing within the DSP adds noise at Also problematic are LO frequencies whose odd order harmon- the level of an LSB, the system noise figure can be degraded , mix with harmonics of f to f /8. This spur ics, i.e., m fLO CLK CLK even more than Figure 65 shows. For example, this could occur mechanism is a result of the mixer being internally driven in a fixed 16-bit DSP whose code is not optimized to process by a squared-up version of the LO input consisting of the LO the AD9864’s 16-bit data with minimal quantization effects. To frequency and its odd order harmonics. These spur frequencies limit the quantization effects within the AD9864, the 24-bit can be calculated from the relation data undergoes noise shaping just prior to 16-bit truncation, thus reducing the in-band quantization noise by 5 dB (with 2× m× f = (n ±1/8)× f (12) LO CLK oversampling). This explains why 98.8 dBFS SNR performance is still achievable with 16-bit data in a 10 kHz BW. where m = 1, 3, 5... and n = 1, 2, 3... 17 A second source of spurs is a large block of digital circuitry that SNR = 98.8dBFS is clocked at f /3. Problematic LO frequencies associated with 16 CLK this spur source are given by 15 BW = 10kHz 14 f = f /3 + n× f ± f /8 (13) LO CLK CLK CLK 13 where n = 1, 2, 3... BW = 150kHz 12 SNR = 89.9dBFS Figure 67 shows that omitting the LO frequencies given by 11 SNR = 94.1dBFS Equation 12 for m = 1, 3, and 5 and by Equation 13 accounts 10 for most of the spurs. Some of the remaining low level spurs BW = 50kHz can be attributed to coupling from the SSI digital output. As a 9 SNR = 83dBFS result, users are also advised to optimize the output bit rate 8 6 9 12 (f via the SSIORD register) and the digital output driver 0 3 CLKOUT VGA ATTENUATION (dB) strength to achieve the lowest spurious and noise figure per- formance for a particular LO frequency and fCLK setting. This is Figure 65. Nominal System Noise Figure and Peak SNR vs. AGCG Setting (f = 73.35 MHz, f = 18 MSPS, and 16-bit I/Q Data) especially the case for particularly narrow-band channels in IF CLK Rev. 0 | Page 35 of 44 NOISE FIGURE (dB) NOISE FIGURE (dB) 04319-0-066 04319-0-065 AD9864 which low level spurs can degrade the AD9864’s sensitivity bandwidth of the AD9864. As evidence of this property, performance. Figure 68 shows that the in-band noise is quite constant for LO frequencies ranging from 70 MHz to 71 MHz. Despite the many spurs, sweet spots in the LO frequency are generally wide enough to accommodate the maximum signal –50 –60 –70 –80 –90 0 50 100 150 200 250 300 LO FREQUENCY (MHz) Figure 66. Total In-Band Noise + Spur Power with No Signal Applied as a Function of the LO Frequency (fCLK = 18 MHz and Output Signal Bandwidth = 150 kHz) –50 –60 –70 –80 –90 300 50 100 150 200 250 0 LO FREQUENCY (MHz) Figure 67. Same as Figure 66 Excluding LO Frequencies Known to Produce Large In-Band Spurs Rev. 0 | Page 36 of 44 IN-BAND POWER (dBFS) IN-BAND POWER (dBFS) 04319-0-068 04319-0-067 AD9864 –50 giving a selectivity of 90 dB for this spurious response. The largest spurious response at approximately –70 dBFS occurs with input frequencies of 70.35 MHz and 71.85 MHz. These –60 spurs result from third order nonlinearity in the signal path (i.e., abs [3 × fLO – 3 × fIF_INPUT] = fCLK /8). EXTERNAL PASSIVE COMPONENT REQUIREMENTS –70 Figure 70 shows an example circuit using the AD9864 and Table 19 shows the nominal dc bias voltages seen at the differ- –80 ent pins. The purpose is to show the various external passive components required by the AD9864, along with nominal dc voltages for troubleshooting purposes. –90 70.0 70.5 71.0 LO FREQUENCY (MHz) 50Ω Figure 68. Expanded View from 70 MHz to 71 MHz 0 D = f /4 = 4.5MHz 48 47 46 45 44 43 42 41 40 39 38 37 CLK 180pF –20 1 MXOP DESIRED GNDL 36 RESPONSES MXON 2 FREF 35 –40 100 100pF 3 GNDF GNDS pF 34 4 IF2N SYNCB 33 5 IF2P –60 GNDH 32 6 VDDF 2.2nF AD9864 FS 31 7 GCP DOUTB 30 GCN 8 –80 DOUTA 29 9 VDDA 100pF CLKOUT 28 10 GNDA VDDH 27 –100 11 VREFP VDDD 26 10nF 12 VREFN PE 25 100pF –120 13 14 15 16 17 18 19 20 21 22 23 24 50 60 70 80 90 100 IF FREQUENCY (MHz) 100kΩ 10nF 10nF Figure 69. Response of AD9864 to a –20 dBm IF Input when fLO = 71.1 MHz Figure 70. Example Circuit Showing Recommended Component Values SPURIOUS RESPONSES The spectral purity of the LO (including its phase noise) is an important consideration since LO spurs can mix with unde- Table 19. Nominal DC Bias Voltages sired signals present at the AD9864’s IFIN input to produce an Pin Number Mnemonic Nominal DC Bias (V) in-band response. To demonstrate the low LO spur level intro- 1 MXOP VDDI – 0.2 duced within the AD9864, Figure 69 plots the demodulated 2 MXON VDDI – 0.2 output power as a function of the input IF frequency for an LO 4 IF2N 1.3 – 1.7 frequency of 71.1 MHz and a clock frequency of 18 MHz. 5 IF2P 1.3 – 1.7 11 VREFP VDDA/2 + 0.250 The two large –10 dBFS spikes near the center of the plot are 12 VREFN VDDA/2 – 0.250 the desired responses at f , ± f , where f = f /8, i.e., LO IF2_ADC IF2_ADC CLK 13 RREF 1.2 at 68.85 MHz and 73.35 MHz. LO spurs at f ± f would LO SPUR 19 CLKP VDDC – 1.3 result in spurious responses at offsets of ± fSPUR around the 20 CLKN VDDC – 1.3 desired responses. Close-in spurs of this kind are not visible on 35 FREF VDDC/2 the plot, but small spurious responses at fLO ± fIF2_ADC ± fCLK, i.e., 41 CXVM 1.6 – 2.0 at 50.85 MHz, 55.35 MHz, 86.85 MHz, and 91.35 MHz, are 42 LON 1.65 – 1.9 visible at the –90 dBFS level. This data indicates that the AD9864 does an excellent job of preserving the purity of the LO 43 LOP 1.65 – 1.9 signal. 44 CXVL VDDI – 0.05 46 CXIF 1.6 – 2.0 Figure 69 can also be used to gauge how well the AD9864 47 IFIN 0.9 – 1.1 rejects undesired signals. For example, the half-IF response (at 69.975 MHz and 72.225 MHz) is approximately –100 dBFS, Rev. 0 | Page 37 of 44 dBFS IN-BAND POWER (dBFS) 04319-0-070 04319-0-069 LC TANK 10µH 10µH VDDI RREF 10nF VDDQ IFIN 100nF IOUTC CXIF GNDQ GNDI 100nF VDDC CXVL 10nF GNDC LOP 10nF CLKP LON CLKN CXVM 1nF GNDS VDDL GNDD VDDP PC IOUTL PD GNDP 04319-0-071 AD9864 The LO, CLK, and IFIN signals are coupled to their respective clock. For example, if f = 26 MHz, the two inductors should CLK inputs using 10 nF capacitors. The output of the mixer is cou- be = 6.9 µH and the capacitor should be about 120 pF. A toler- pled to the input of the ADC using 100 pF. An external 100 kΩ ance of 10% is sufficient for these components since tuning of resistor from the RREF pin to GND sets up the AD9864’s the LC tank is performed upon system startup. internal bias currents. VREFP and VREFN provide a differen- APPLICATIONS tial reference voltage to the AD9864’s Σ-∆ ADC and must be SuperHeterodyne Receiver Example decoupled by a 0.01 µF differential capacitor along with two The AD9864 is well suited for analog and/or digital narrow-band 100 pF capacitors to GND. The remaining capacitors are used radio systems based on a superheterodyne receiver architecture. The to decouple other sensitive internal nodes to GND. superheterodyne architecture is noted for achieving exceptional Although power supply decoupling capacitors are not shown, it dynamic range and selectivity by using two or more downconversion is recommended that a 0.1 µF surface-mount capacitor be stages to provide amplification of the target signal while filtering the placed as close as possible to each power supply pin for maxi- undesired signals. The AD9864 greatly simplifies the design of these mum effectiveness. Also not shown is the input impedance radio systems by integrating the complete IF strip (excluding the LO matching network used to match the AD9864’s IF input to the VCO) while providing an I/Q digital output (along with other sys- external IF filter. Lastly, the loop filter components associated tem parameters) for the demodulation of both analog and digital with the LO and CLK synthesizers are not shown. modulated signals. The AD9864’s exceptional dynamic range often simplifies the IF filtering requirements and eliminates the need for an LC component values for f = 18 MHz are given Figure 70. CLK external AGC. For other clock frequencies, the two inductors and the capaci- tor of the LC tank should be scaled in inverse proportion to the VDDA IF2 = f /8 CLK AD9864 IF CRYSTAL OR PRESELECT RF DAC AGC –16dB TUNER SAW FILTER FILTER INPUT DOUTA IFIN DECIMATION Σ-∆ ADC LNA LNA FORMATTING/SSI FILTER DOUTB TO DSP FS CLKOUT CONTROL LOGIC VCO SAMPLE CLOCK VOLTAGE LO SYNTHESIZER REFERENCE SYNTH. SPI ADF42xx PLL SYN REFIN VCO LOOP LOOP FILTER FILTER VDDC CRYSTAL OSCILLATOR FROM DSP Figure 71. Typical Dual Conversion Superheterodyne Application Using the AD9864 Rev. 0 | Page 38 of 44 IOUTC LOP VXOP LON VXON II-2P II-2N IOUTC GCP CLKP GCN CLKN VREFP VREFN RREF PC PD PE SYNCB 04319-0-072 AD9864 Figure 71 shows a typical dual conversion superheterodyne between the AD9864’s rated operating range of 13 MHz to receiver using the AD9864. An RF tuner is used to select and 26 MHz and no significant spurious products related to f fall CLK downconvert the target signal to a suitable first IF for the within the desired pass band, resulting in a reduction in sensi- AD9864. A preselect filter may precede the tuner to limit the tivity performance. If a spurious component is found to limit RF input to the band of interest. The output of the tuner drives the sensitivity performance, the decimation factor can often be an IF filter that provides partial suppression of adjacent chan- modified slightly to find a spurious free pass band. Selecting a nels and interferers that could otherwise limit the receiver’s higher fCLK is typically more desirable given a choice, since the dynamic range. The conversion gain of the tuner should be set first IF’s filtering requirements often depend on the transition such that the peak IF input signal level into the AD9864 is no region between the IF frequency and the image band (i.e., greater than –18 dBm to prevent clipping. The AD9864 down- ± f /4). Lastly, the output SSI clock rate, f , and digital CLK CLKOUT converts the first IF signal to a second IF that is exactly 1/8 of driver strength should be set to their lowest possible settings to the Σ-∆ ADC’s clock rate, i.e., fCLK/8, to simplify the digital minimize the potential harmful effects of digital induced noise quadrature demodulation process. while preserving a reliable data link to the DSP. Note that the SSICRA, SSICRB, and SSIORD registers, i.e., 0x18, 0x19, and This second IF signal is then digitized by the Σ-∆ ADC, 0x1A, provide a large degree of flexibility for optimization of demodulated into its quadrature I and Q components, filtered the SSI interface. via matching decimation filters, and reformatted to enable a Syncronization of Multiple AD9864S synchronous serial interface to a DSP. In this example, the AD9864’s LO and CLK synthesizers are both enabled, requiring Some applications, such as receiver diversity and beam steering, may require two or more AD9864s operating in parallel while some additional passive components (for the synthesizer’s loop maintaining synchronization. Figure 71 shows an example of filters and CLK oscillator) and a VCO for the LO synthesizer. how multiple AD9864s can be cascaded, with one device serv- Note that not all of the required decoupling capacitors are ing as the master and the other devices serving as the slaves. In shown. Refer to the previous section and Figure 70 for more this example, all of the devices have the same SPI register con- information on required external passive components. figuration since they share the same SPI interface to the DSP. The selection of the first IF frequency is often based on the Since the state of each of the AD9864’s internal counters is availability of low cost standard crystal or SAW filters as well as unknown upon initialization, synchronization of the devices is system frequency planning considerations. In general, crystal required via a SYNCB pulse (see Figure 36) to synchronize their filters are often used for narrow-band radios having channel digital filters and ensure precise time alignment of the data bandwidths below 50 kHz with IFs below 120 MHz, while SAW streams. filters are more suited for channel bandwidths greater than Although all of the devices’ synthesizers are enabled, the LO 50 kHz with IFs greater than 70 MHz. The ultimate stop-band and CLK signals for the slave(s) are derived from the masters’ rejection required by the IF filter will depend on how much synthesizers and are referenced to an external crystal oscillator. suppression is required at the AD9864’s image band resulting from downconversion to the second IF. This image band is All of the necessary external components(i.e., loop filters, varactor, LC, and VCO) required to ensure proper closed-loop offset from the first IF by twice the second IF frequency operation of these synthesizers are included. (i.e., ± fCLK/4, depending on high- or low-side injection). Note that although the VCO output of the LO synthesizer is The selectivity and bandwidth of the IF filter will depend on ac-coupled to the slave’s LO input(s), all of the CLK inputs of both the magnitude and frequency offset(s) of the adjacent the devices must be dc-coupled if the AD9864’s CLK oscillators channel blocker(s) that could overdrive the AD9864’s input or are enabled. This is because of the dc current required by the generate in-band intermodulation components. Further sup- pression is performed within the AD9864 by its inherent band- CLK oscillators in each device. In essence, these negative pass response and digital decimation filters. Note that some impedance cores are operating in parallel, increasing the effective Q of the LC resonator circuit. RBIAS should be sized applications will require additional application-specific filtering such that the sum of the oscillators’ dc bias currents maintains performed in the DSP that follows the AD9864 to remove the a common-mode voltage of around 1.6 V. adjacent channel and/or implement a matched filter for opti- mum signal detection. The output data rate of the AD9864, f , should be chosen to OUT be at least twice the bandwidth or symbol rate of the desired signal to ensure that the decimation filters provide a flat pass- band response as well as to allow for postprocessing by a DSP. Once fOUT is determined, the decimation factor of the digital filters should be set such that the input clock rate, fCLK, falls Rev. 0 | Page 39 of 44 AD9864 VDDC operating in parallel. The RF front end consists of a duplexer LOOP and preselect filter to pass the GSM RF band of interest. A high FILTER R BIAS C 0.1µF OSC R performance LNA isolates the duplexer from the preselect filter D L OSC while providing sufficient gain to minimize system NF. An RF R C P F C VAR mixer is used to downconvert the entire GSM band to a suitable C Z IF, where much of the channel selectivity is accomplished. The 170.6 MHz IF is chosen to avoid any self-induced spurs from 15 the AD9864. The IF stage consists of two SAW filters isolated IOUTC FROM 35 FREF CRYSTAL by a 15 dB gain stage. OSCILLATION 19 CLKP The cascaded SAW filter response must provide sufficient 20 CLKN blocker rejection in order for the receiver to meet its sensitivity 47 IFIN requirements under worst-case blocker conditions. A compos- FS 31 ite response having 27 dB, 60 dB, and 100 dB rejection at DOUTA 29 TO DSP CLKOUT 28 frequency offsets of ±0.8 MHz, ±1.6 MHz, and ±6.5 MHz, re- 43 LOP spectively, provides enough blocker suppression to ensure that PE 25 42 LON the AD9864 with the lower clip point will not be overdriven by PD 24 FROM AD9864 DSP MASTER PC 23 any blocker. This configuration results in the best possible re- SYNCB 33 ceiver sensitivity under all blocking conditions. IOUTL 38 The output of the last SAW filters drives the two AD9864s via a VCO direct signal path and an attenuated signal path. The direct path LOOP FILTER corresponds to the AD9864 having the lowest clip point and provides the highest receiver sensitivity with a system noise 15 figure of 4.7 dB. The VGA of this device is set for maximum IOUTC PE 25 attenuation, so its clip point is approximately –17 dBm. Since 47 IFIN PD 24 conversion gain from the antenna to the AD9864 is 19 dB, the PC 23 43 LOP digital output of this path will nominally be selected unless the SYNCB 33 42 LON target signal’s power exceeds –36 dBm at the antenna. The AD9864 attenuated path corresponds to the AD9864 having the highest SLAVE TO OTHER input-referred clip point, and its digital output point of this AD9864s 19 CLKP path is set to 7 dBm by inserting a 30 dB attenuator and setting 20 CLKN 31 FS the AD9864’s VGA to the middle of its 12 dB range. This TO 29 DOUTA DSP setting results in a ±6 dB adjustment of the clip point, allowing CLKOUT 28 TO OTHER the clip point difference to be calibrated to exactly 24 dB, so AD9864s FREF 35 that a simple 5-bit shift would make up the gain difference. The attenuated path can handle signal levels up to –12 dB at the Figure 72. Example of Synchronizing Multiple AD9864s antenna before being overdriven. Since the SAW filters provide Split Path Rx Architecture sufficient blocker suppression, the digital data from this path A split path Rx architecture may be attractive for those applica- need only be selected when the target signal exceeds –36 dBm. tions whose instantaneous dynamic range requirements exceed Although the sensitivity of the receiver with the attenuated path the capability of a single AD9864 device. To cope with these is 20 dB lower than the direct path, the strong target signal higher dynamic range requirements, two AD9864s can be oper- ensures a sufficiently high carrier-to-noise ratio. ated in parallel with their respective clip points offset by a fixed amount. Adding a fixed amount of attenuation in front of the Since GSM is based on a TDMA scheme, digital data (or path) AD9864 and/or programming the attenuation setting of its in- selection can occur on a slot-by-slot basis. The AD9864 would ternal VGA can adjust the input-referred clip point. To save be configured to provide Serial I and Q data at a frame rate of power and simplify hardware, the LO and CLK circuits of the 541.67 kSPS, as well as additional information including a 2-bit device can also be shared. Connecting the SYNCB pins of the two reset field and a 6-bit RSSI field. These two fields contain the devices and pulsing this line low synchronizes the two devices. information needed to decide whether the direct or attenuated path should be used for the current time slot. An example of this concept for possible use in a GSM base sta- tion is shown in Figure 73. The signal chain consists of a high linearity RF front end and IF stage followed by two AD9864s Rev. 0 | Page 40 of 44 04319-0-073 AD9864 VDDC LOOP R BIAS FILTER 0.1µF C OSC R D L OSC C R P F C VAR C Z ATTENUATED PATH WITH CLIP POINT = 7.0dBm 15 13MHz IO 19 CLKP 35 FREF 20 CLKN FS 31 47 IFIN DOUTA 29 CLKOUT 28 36dB PAD 43 LOP PE 25 42 LON AD9864 MASTER PD 24 PC 23 SYNCB 33 IOUTL 38 VCO LOOP FILTER DSP OR ASIC DUPLEXER PRESELECT IF SAW 1I F SAW 2 15 IO IF PE 25 LNA 47 IFIN AMP PD 24 MIXER PC 23 43 LOP SYNCB GAIN = –2dB GAIN = 22dB GAIN = –3dB GAIN = 5dB GAIN = 15dB GAIN = –9dB 33 42 LON NF = 2dB NF = 1dB NF = 3dB NF = 12dB NF = 2dB NF = –9dB AD9864 SLAVE DIRECT PATH WITH 31 FS CLIP POINT = –17dBm 19 CLKP 29 DOUTA 20 CLKN CLKOUT 28 FREF 35 Figure 73. Example of Split Path Rx Architecture to Increase Receiver Dynamic Range Capabilities Hung Mixer Mode The AD9864 can operate in hung mixer mode by tying one of Since the mixer does not have any losses associated with the mix- the LO’s self-biasing inputs to ground, i.e., GNDI, or the ing operation, the conversion gain through the LNA and mixer is positive supply (VDDI). In this mode, the AD9864 acts as a higher resulting in a nominal input clip point of –24 dBm. The narrow-band, band-pass Σ-∆ ADC, since its mixer passes the SNR performance is dependent on the VGA attenuation setting, IFIN signal without any frequency translation. The IFIN signal I/Q data resolution, and output bandwidth as shown in Figure 74. must be centered about the resonant frequency of the Σ-∆ ADC Applications requiring the highest instantaneous dynamic range (i.e., fCLK/8) and the clock rate, fCLK, and decimation factors must should set the VGA for maximum attenuation. Also, several extra be selected to accommodate the bandwidth of the desired input decibels in SNR performance can be gained at lower signal band- signal. Note that the LO synthesizer can be disabled because it widths by using 24-bit I/Q data. is no longer required. Rev. 0 | Page 41 of 44 04319-0-074 AD9864 105 The evaluation board is designed to interface to a PC via a f = 18MSPS CLK National Instruments NI 6533 digital IO card. An XILINX FPGA formats the data between the AD9864 and digital I/O card. 100 MAX ATTEN WITH 24-BIT I/Q DATA IF LO 95 INPUT INPUT VCO MAX ATTEN WITH MODULE AD9864 16-BIT I/Q DATA FREF INTERFACE INPUT 90 MIXER MIN ATTEN WITH INPUT DUT 16-BIT I/Q DATA CRYSTAL 85 OSCILLATOR (OPTIONAL) MIN ATTEN WITH 24-BIT I/Q DATA 80 XILINX 0 20 40 60 80 100 120 140 160 SPARTON IDT BW (kHz) FPGA FIFO Figure 74. Hung Mixer SNR vs. BW and VGA POWER SUPPLY DISTRIBUTION CLK EPROM INPUT LAYOUT EXAMPLE, EVALUATION BOARD, AND SOFTWARE Figure 75. Evaluation Board Platform The evaluation board and its accompanying software provide a Software developed using National Instruments’ LabVIEW™ simple way to evaluate the AD9864. The block diagram in (and provided as Microsoft® Windows® executable programs) is Figure 75 shows the major blocks of the evaluation board, supplied for the configuration of the SPI port registers and which is designed to be flexible, allowing configuration for evaluation of the AD9864 output data. These programs have a different applications. convenient graphical user interface that allows for easy access to the various SPI port configuration registers and frequency The power supply distribution block provides filtered, adjust- analysis of the output data. able voltages to the various supply pins of the AD9864. In the IF input signal path, component pads are available to implement For more information on the AD9864 evaluation board, includ- different IF impedance matching networks. The LO and CLK ing an example layout, please refer to the EVAL-AD9874EB signals can be externally applied or internally derived from a Data Sheet user-supplied VCO module interface daughter board. The refer- (www.analog.com/Analog_Root/static/pdf/techSupport/AD987 ence for the on-chip LO and CLK synthesizers can be applied via 4EB_0.pdf). the external fREF input or an on-board crystal oscillator. Rev. 0 | Page 42 of 44 SNR (dB) 04319-0-075 NIDAQ 68-PIN CONNECTOR 04319-0-076 AD9864 OUTLINE DIMENSIONS 0.30 7.00 0.23 0.60 MAX BSC SQ 0.18 0.60 MAX PIN 1 INDICATOR 37 48 36 1 PIN 1 INDICATOR 5.25 TOP 6.75 BOTTOM VIEW BSC SQ 5.10 SQ VIEW 4.95 0.50 25 12 0.40 13 24 0.30 0.25 MIN 5.50 1.00 MAX REF 1.00 12° MAX 0.65 NOM 0.90 0.05 MAX 0.80 0.02 NOM 0.20 0.50 BSC COPLANARITY REF SEATING 0.08 PLANE COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 Figure 76. 48-Lead Frame Chip Scale Package [LFCSP] (CP-48)—Dimensions shown in millimeters ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ORDERING GUIDE AD9864 Products Temperature Package Package Description Package Outline AD9864BCPZ* –40°C to +85°C Lead Frame Chip Scale Package (LFCSP) CP-48 AD9864BCPZRL* –40°C to +85°C Lead Frame Chip Scale Package (LFCSP) CP-48 AD9864-EB Evaluation Board *This is a lead free product. Rev. 0 | Page 43 of 44 AD9864 NOTES © 2003 Analog Devices, Inc. All rights reserved. Trademarks and regis- tered trademarks are the property of their respective companies. C04319-0-8/03(0) Rev. 0 | Page 44 of 44