ANALOG DEVICES AD9856

CMOS 200 MHz Quadrature Digital Upconverter AD9856 APPLICATIONS FEATURES HFC data, telephony, and video modems Universal low cost modulator solution for communications applications Wireless and satellite communications DC to 80 MHz output bandwidth Cellular base stations Integrated 12-bit D/A converter Programmable sample rate interpolation filter GENERAL DESCRIPTION Programmable reference clock multiplier The AD9856 integrates a high speed, direct digital synthesizer Internal SIN(x)/x compensation filter (DDS), a high performance, high speed, 12-bit digital-to-analog >52 dB SFDR @ 40 MHz AOUT converter (DAC), clock multiplier circuitry, digital filters, and >48 dB SFDR @ 70 MHz A OUT other DSP functions on a single chip to form a complete >80 dB narrow-band SFDR @ 70 MHz AOUT quadrature digital upconverter device. The AD9856 is intended +3 V single-supply operation to function as a universal I/Q modulator and agile upconverter Space-saving surface-mount packaging for communications applications where cost, size, power Bidirectional control bus interface dissipation, and dynamic performance are critical attributes. Supports burst and continuous Tx modes Single-tone mode for frequency synthesis applications The AD9856 is available in a space-saving surface-mount Four programmable, pin-selectable, modulator profiles package, and is specified to operate over the extended industrial Direct interface to AD8320/AD8321 PGA cable driver temperature range of −40°C to +85°C. FUNCTIONAL BLOCK DIAGRAM AD9856 4× TO 8× 12 12 2× TO 63× 12 12 SELECTABLE SELECTABLE INTERPOLATING INTERPOLATOR HALFBANDS 12 12 INV DC-80 MHz 12-BIT COMPLEX SINC OUTPUT DAC DATA IN 4× TO 8× 12 12 2× TO 63× 12 12 SELECTABLE DAC SELECTABLE INTERPOLATING R SET INTERPOLATOR HALFBANDS 12 12 SINE COSINE SPI INTERFACE 4× TO 20× PROG. TO AD8320/AD8321 TxENABLE CLOCK DDS AND CONTROL FUNCTIONS PROGRAMMABLE (I/Q SYNC) MULTIPLIER CABLE DRIVER AMPLIFIER REFERENCE PROFILE PROFILE MASTER BIDIRECTIONAL SPI CONTROL INTERFACE: CLOCK IN SELECT SELECT RESET 32-BIT FREQUENCY TUNING WORD 1–2 3–4 FREQUENCY UPDATE INTERPOLATION FILTER RATE REFERENCE CLOCK MULTIPLIER RATE SPECTRAL PHASE INVERSION ENABLE CABLE DRIVER AMPLIFIER CONTROL Figure 1. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 www.analog.com or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.326.8703 © 2005 Analog Devices, Inc. All rights reserved. DEMULTIPLEXER AND SERIAL-TO-PARALLEL CONVERTER 00637-C-001 AD9856 TABLE OF CONTENTS Specifications..................................................................................... 3 Digital Quadrature Modulator ................................................. 23 Absolute Maximum Ratings............................................................ 5 Inverse Sinc Filter (ISF) ............................................................. 24 Explanation of Test Levels........................................................... 5 Direct Digital Synthesizer Function ........................................ 25 ESD Caution.................................................................................. 5 D/A Converter............................................................................ 25 Pin Configuration and Function Descriptions............................. 6 Reference Clock Multiplier ....................................................... 26 Typical Performance Characteristics ............................................. 8 Throughput and Latency........................................................... 26 Typical Modulated Output Spectral Plots ................................. 8 Control Interface ........................................................................ 26 Typical Single-Tone Output Spectral Plots ............................... 9 General Operation of the Serial Interface............................... 26 Typical Narrow-Band SFDR Spectral Plots ............................ 10 Instruction Byte.......................................................................... 27 Typical Phase Noise Spectral Plots........................................... 10 Serial Interface Port Pin Descriptions ..................................... 28 Typical Plots of Output Constellations.................................... 11 MSB/LSB Transfers .................................................................... 28 Power Consumption .................................................................. 12 Notes on Serial Port Operation ................................................ 28 Serial Control Bus Register ........................................................... 13 Programming/Writing the AD8320/AD8321 Cable Driver Amplifier Gain Control............................................................. 30 Register Bit Definitions.............................................................. 14 Understanding and Using Pin-Selectable Modulator Profiles Theory of Operation ...................................................................... 15 ....................................................................................................... 31 Modulation Mode Operation ................................................... 15 Power Dissipation Considerations........................................... 31 Input Word Rate (fW) vs. REFCLK Relationship .................... 16 AD9856 Evaluation Board ........................................................ 32 I/Q Data Synchronization ......................................................... 16 Support ........................................................................................ 32 Half-Band Filters (HBFs) .......................................................... 20 Outline Dimensions ....................................................................... 35 Cascaded Integrator Comb (CIC) Filter.................................. 21 Ordering Guide .......................................................................... 35 REVISION HISTORY 1/05—Rev. B to Rev. C Updated Format..................................................................Universal Changes to Table 2............................................................................ 5 Changes to Input Word Rate (f ) vs. REFCLK w Relationship Section.................................................................. 16 Changes to Cascaded Integrator Comb (CIC) Filter Section ... 21 Updates to Direct Digital Synthesizer Function Section........... 25 Added Support Section.................................................................. 32 Updated Outline Dimensions ....................................................... 35 Changes to Ordering Guide .......................................................... 35 9/99—Rev. A to Rev. B Rev. C | Page 2 of 36 AD9856 SPECIFICATIONS VS = +3 V ± 5%, RSET = 3.9 kΩ, external reference clock frequency = 10 MHz with REFCLK multiplier enabled at 20×. Table 1. Parameter Temp Test Level Min Typ Max Unit REF CLOCK INPUT CHARACTERISTICS Frequency Range 1 REFCLK Multiplier Disabled Full VI 5 200 MHz REFCLK Multiplier Enabled at 4 × Full VI 5 50 MHz REFCLK Multiplier Enabled at 20 × Full VI 5 10 MHz Duty Cycle 25°C V 50 % Input Capacitance 25°C V 3 pF Input Impedance 25°C V 100 MΩ DAC OUTPUT CHARACTERISTICS Resolution 12 Bits Full-Scale Output Current 5 10 20 mA Gain Error 25°C I −10 +10 %FS Output Offset 25°C I 10 µ A Differential Nonlinearity 25°C V 0.5 LSB Integral Nonlinearity 25°C V 1 LSB Output Capacitance 25°C V 5 pF Phase Noise @ 1 kHz Offset, 40 MHz AOUT REFCLK Multiplier Enabled at 20× 25°C V −85 dBc/Hz REFCLK Multiplier at 4× 25°C V −100 dBc/Hz REFCLK Multiplier Disabled 25°C V −110 dBc/Hz Voltage Compliance Range 25°C I −0.5 1.5 V Wideband SFDR: 1 MHz Analog Out 25°C IV 70 dBc 20 MHz Analog Out 25°C IV 65 dBc 42 MHz Analog Out 25°C IV 60 dBc 65 MHz Analog Out 25°C IV 55 dBc 80 MHz Analog Out 25°C IV 50 dBc Narrow-Band SFDR: (± 100 kHz Window) 70 MHz Analog Out 25°C IV 80 dBc MODULATOR CHARACTERISTICS Adjacent Channel Power (CH Power = −6.98 dBm) 25°C IV 50 dBm Error Vector Magnitude 25°C IV 1 2 % I/Q Offset 25°C IV 50 55 dB Inband Spurious Emissions 25°C IV 45 50 dBc Pass-Band Amplitude Ripple (DC to 80 MHz) 25°C V ±0.3 dB 1 For 200 MHz operation in modulation mode at 85°C operating temperature, VS must be 3 V minimum. Rev. C | Page 3 of 36 AD9856 Parameter Temp Test Level Min Typ Max Unit TIMING CHARACTERISTICS Serial Control Bus Maximum Frequency Full IV 10 MHz Minimum Clock Pulse Width High (t ) Full IV 30 ns PWH Minimum Clock Pulse Width Low (t ) Full IV 30 ns PWL Maximum Clock Rise/Fall Time Full IV 1 ms Minimum Data Setup Time (tDS) Full IV 25 ns Minimum Data Hold Time (tDH) Full IV 0 ns Maximum Data Valid Time (t ) Full IV 30 ns DV 2 Wake-Up Time Full IV 1 ms Minimum RESET Pulse Width High (t ) Full IV 5 REFCLK cycles RH CMOS LOGIC INPUTS Logic 1 Voltage 25°C I 2.6 V Logic 0 Voltage 25°C I 0.4 V Logic 1 Current 25°C I 12 µA Logic 0 Current 25°C I 12 µA Input Capacitance 25°C V 3 pF CMOS LOGIC OUTPUTS (1 mA LOAD) Logic 1 Voltage 25°C I 2.7 mA Logic 0 Voltage 25°C I 0.4 mA POWER SUPPLY +VS Current 3 Full Operating Conditions 25°C I 530 mA Burst Operation (25%) 25°C I 450 mA Single-Tone Mode 25°C I 495 mA 160 MHz Clock 25°C I 445 mA 120 MHz Clock 25°C I 345 mA Power-Down Mode 25°C I 2 mA 2 Assuming 1.3 kΩ and 0.01 µF loop filter components. 3 Assuming 1.3 kW and 0.01 mF loop filter components. Rev. C | Page 4 of 36 AD9856 ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings are limiting values, to be applied EXPLANATION OF TEST LEVELS individually, and beyond which the serviceability of the circuit I. 100% production tested. may be impaired. Functional operability under any of these III. Sample tested only. conditions is not necessarily implied. Exposure of absolute maximum rating conditions for extended periods of time may IV. Parameter is guaranteed by design and characterization affect device reliability. testing. Table 2. V. Parameter is a typical value only. Parameter Rating Maximum Junction Temperature 150°C VI. Devices are 100% production tested at 25°C and Storage Temperature −65°C to +150°C guaranteed by design and characterization testing for V 4 V S industrial operating temperature range. Operating Temperature −40°C to +85°C Digital Inputs −0.7 V to +Vs Lead Temperature (Soldering 10 sec) 300°C Digital Output Current 5 mA θ Thermal Impedance 38°C/W JA ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. C | Page 5 of 36 AD9856 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 48 47 46 45 44 43 42 41 40 39 38 37 TxENABLE 1 36 CA DATA PIN 1 2 D11 IDENTIFIER 35 CA ENABLE D10 3 34 PLL SUPPLY 4 DVDD 33 PLL FILTER DGND 5 32 PLL GND AD9856 6 D9 31 AGND TOP VIEW D8 7 30 I OUT (Not to Scale) 8 D7 29 I OUTB D6 9 28 AGND DVDD 10 27 AVDD DGND 11 26 DAC REF BYPASS 12 D5 25 DAC R SET 13 14 15 16 17 18 19 20 21 22 23 24 NC = NO CONNECT Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No. Mnemonic Pin Function Pin No. Mnemonic Pin Function 1 TxENABLE Input Pulse that Synchronizes the 32 PLL GND PLL Ground Data Stream 2 D11 Input Data (Most Significant Bit) 33 PLL FILTER PLL Loop Filter Connection 3 D10 Input Data 34 PLL SUPPLY PLL Voltage Supply 4, 10, 21, 44 DVDD Digital Supply Voltage 35 CA ENABLE Cable Driver Amp Enable 5, 11, 20, 43 DGND Digital Ground 36 CA DATA Cable Driver Amp Data 6 to 9 D9 to D6 Input Data 37 CA CLK Cable Driver Amp Clock 12 to 16 D5 to D1 Input Data 38 CS Chip Select 17 D0 Input Data (Least Significant Bit) 39 SDO Serial Data Output 18, 19, 22 NC No Internal Connection 40 SDIO Serial Port I/O 23, 28, 31 AGND Analog Ground 41 SCLK Serial Port Clock 1 24 BG REF No External Connection 42 SYNC I/O Performs I/O Synchronization BYPASS 25 DAC R R Resistor Connection 45 PS0 Profile Select 0 SET SET 26 DAC REF No External Connection1 46 PS1 Profile Select 1 BYPASS 27 AVDD Analog Supply Voltage 47 REFCLK Reference Clock Input 29 I Complementary Analog Current 48 RESET Master Reset OUTB Output of the DAC 30 IOUT True Analog Current Output of DAC 1 In most cases, optimal performance is achieved with no external connection. For extremely noisy environments, BG REF BYPASS can be bypassed with up to a 0.1 µF capacitor to AGND (Pin 23). DAC REF BYPASS can be bypassed with up to a 0.1 µF capacitor to AVDD (Pin 27). Rev. C | Page 6 of 36 D4 RESET D3 REFCLK D2 PS1 D1 PS0 D0 DVDD NC DGND NC SYNC I/O DGND SCLK SDIO DVDD NC SDO AGND CS BG REF CA CLK BYPASS 00637-C-002 AD9856 Table 4. Functional Block Mode Descriptions Functional Block Mode Description Operating Modes 1. Complex quadrature modulator mode. 2. Single-tone output mode. Input Data Format Programmable: 12-bit, 6-bit, or 3-bit input formats. Data input to the AD9856 is 12-bit, twos complement. Complex I/Q symbol component data is required to be at least 2× oversampled, depending upon configuration. Input Sample Rate Up to 50 Msamples/sec @ 200 MHz SYSCLK rate. Input Reference For DC to 80 MHz AOUT operation (200 MHz SYSCLK rate) with REFCLK multiplier enabled: 10 MHz to50 MHz, Clock Frequency programmable via control bus; with REFCLK multiplier disabled: 200 MHz. Note: For optimum data synchronization, the AD9856 reference clock and the input data clock should be derived from the same clock source. Internal Reference Programmable in integer steps over the range of 4× to 20×. Can be disabled (effective REFCLK multiplier = 1) via Clock Multiplier control bus. Output of REFCLK multiplier = SYSCLK rate, which is the internal clock rate applied to the DDS and DAC function. Profile Select Four pin-selectable, preprogrammed formats. Available for modulation and single-tone operating modes. Interpolating Range Fixed 4×, selectable 2×, and selectable 2× to 63× range. Half-Band Filters Interpolating filters that provide upsampling and reduce the effects of the CIC passband roll-off characteristics. TxENABLE Function– When burst mode is enabled via the control bus, the rising edge of the applied TxENABLE pulse should be Burst Mode coincident with, and frame, the input data packet. This establishes data sampling synchronization. TxENABLE Function– When continuous mode is enabled via the control bus, the TxENABLE pin becomes an I/Q control line. A Logic 1 Continuous Mode on TxENABLE indicates I data is being presented to the AD9856. A Logic 0 on TxENABLE indicates Q data is being presented to the AD9856. Each rising edge of TxENABLE resynchronizes the AD9856 input sampling capability. Inverse SINC Filter Precompensates for SIN(x)/x roll-off of DAC; user bypassable. I/Q Channel Invert [I ×Cos(ωt) + Q ×Sin(ωt)] or [I ×Cos(ωt) − Q ×Sin(ωt)] (default), configurable via control bus, per profile. Full Sleep Mode Power dissipation reduced to less than 6 mW when full sleep mode is active; programmable via the control bus. Rev. C | Page 7 of 36 AD9856 TYPICAL PERFORMANCE CHARACTERISTICS TYPICAL MODULATED OUTPUT SPECTRAL PLOTS RBW 10kHz RF ATT 10dB RBW 10kHz RF ATT 10dB REF LVL VBW 1kHz REF LVL VBW 1kHz –25dBm SWT 12.5s UNIT dBm –25dBm SWT 20s UNIT dBm 0 0 –8 –8 –16 –16 1AP 1AP –24 –24 –32 –32 –40 –40 –48 –48 –56 –56 –64 –64 –72 –72 –80 –80 START 0Hz 5MHz/ STOP 50MHz START 0Hz 8MHz/ STOP 80MHz Figure 3. QPSK at 42 MHz and 2.56 MS/sec; 10.24 MHz External Clock with Figure 5. 16-QAM at 65 MHz and 2.56 MS/sec; 10.24 MHz External Clock with REFCLK Multiplier = 12, CIC = 3, HB3 On, 2× Data REFCLK Multiplier = 18, CIC = 9, HB3 Off, 2× Data RBW 10kHz RF ATT 10dB RBW 10kHz RF ATT 10dB REF LVL VBW 1kHz REF LVL VBW 1kHz –30dBm SWT 10s UNIT dBm –30dBm SWT 12.5s UNIT dBm 0 0 –8 –8 –16 –16 1AP 1AP –24 –24 –32 –32 –40 –40 –48 –48 –56 –56 –64 –64 –72 –72 –80 –80 0 START 0Hz 4MHz/ STOP 40MHz START 0Hz 5MHz/ STOP 50MHz Figure 4. 64-QAM at 28 MHz and 6 MS/sec; 36 MHz External Clock with Figure 6. 256-QAM at 38 MHz and 6 MS/sec; 48 MHz External Clock with REFCLK Multiplier = 4, CIC = 2, HB3 Off, 3× Data REFCLK Multiplier = 4, CIC = 2, HB3 Off, 4× Data Rev. C | Page 8 of 36 (dBm) (dBm) 00637-C-004 00637-C-003 (dBm) (dBm) 00637-C-006 00637-C-005 AD9856 TYPICAL SINGLE-TONE OUTPUT SPECTRAL PLOTS RBW 3kHz RF ATT 20dB RBW 3kHz RF ATT 20dB REF LVL VBW 3kHz REF LVL VBW 3kHz –5dBm SWT 28s UNIT dB –5dBm SWT 28s UNIT dB 0 0 A A –10 –10 –20 –20 –30 –30 1AP 1AP –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 –100 START 0Hz 10MHz/ STOP 100MHz START 0Hz 10MHz/ STOP 100MHz Figure 7. 21 MHz CW Output Figure 9. 42 MHz CW Output RBW 3kHz RF ATT 20dB RBW 3kHz RF ATT 20dB REF LVL VBW 3kHz REF LVL VBW 3kHz –5dBm SWT 28s UNIT dB –5dBm SWT 28s UNIT dB 0 0 A A –10 –10 –20 –20 –30 –30 1AP 1AP –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 –100 START 0Hz 10MHz/ STOP 100MHz START 0Hz 10MHz/ STOP 100MHz Figure 8. 65 MHz CW Output Figure 10. 79 MHz CW Output Rev. C | Page 9 of 36 (dBm) (dBm) 00637-C-008 00637-C-007 (dBm) (dBm) 00637-C-010 00637-C-009 AD9856 TYPICAL PHASE NOISE SPECTRAL PLOTS TYPICAL NARROW-BAND SFDR SPECTRAL PLOTS RBW 30Hz RF ATT 30dB RBW 100Hz RF ATT 20dB REF LVL VBW 30Hz REF LVL VBW 100Hz 0dBm SWT 28s UNIT dB –5dBm SWT 50s UNIT dB 0 0 FXD –2.248dBm A A –12 –10 –24 –20 –36 –30 1AP 1AP –48 –40 –60 –50 –72 –60 –84 –70 –96 –80 –108 –90 FXD –120 –100 CENTER 40.1MHz 500Hz/ SPAN 5kHz CENTER 70.1MHz 10kHz/ SPAN 100kHz Figure 11. 70.1 MHz Narrow-Band SFDR, 10 MHz External Clock Figure 13. 40.1 MHz Output, 10 MHz External Clock with REFCLK Multiplier = 20× with REFCLK Multiplier = 20× RBW 100Hz RF ATT 20dB RBW 30Hz RF ATT 30dB REF LVL VBW 100Hz REF LVL VBW 30Hz –5dBm SWT 50s UNIT dB 0dBm SWT 28s UNIT dB 0 0 FXD –2.248dBm A A –12 –12 –24 –24 –36 –36 1AP 1AP –48 –48 –60 –60 –72 –72 –84 –84 –96 –96 –108 –108 FXD –120 –120 CENTER 70.1MHz 10kHz/ SPAN 100kHz CENTER 40.1MHz 500Hz/ SPAN 5kHz Figure 14. 40.1 MHz Output, 200 MHz External Clock Figure 12. 70.1 MHz Narrow-Band SFDR, 200 MHz External Clock with REFCLK Multiplier Disabled with REFCLK Multiplier Disabled Rev. C | Page 10 of 36 (dBm) (dBm) 00637-C-012 00637-C-011 (dBm) (dBm) 00637-C-014 00637-C-013 AD9856 TYPICAL PLOTS OF OUTPUT CONSTELLATIONS TRACE A: CH 1 QPSK MEAS TIME TRACE A: CH 1 256QAM MEAS TIME 1.5 1 CONST CONST 300 200 M M /DIV /DIV –1.5 –1 –1.9607843757 1.96078437567 –1.3071895838 1.30718958378 Figure 15. QPSK, 65 MHz, 2.56 MS/sec Figure 18. 256-QAM, 42 MHz, 6 MS/sec TRACE A: CH 1 64QAM MEAS TIME TRACE A: CH 1 MSK1 MEAS TIME 1.5 1 CONST CONST 300 200 M M /DIV /DIV –1.5 –1 –1.9607843757 1.96078437567 –1.3071895838 1.30718958378 Figure 19. GMSK Modulation, 13 MS/sec Figure 16. 64-QAM, 42 MHz, 6 MS/sec TRACE A: CH 1 16QAM MEAS TIME 1.25 CONST 250 M /DIV –1.25 –1.6339869797 1.63398697972 Figure 17. 16-QAM, 65 MHz, 2.56 MS/sec Rev. C | Page 11 of 36 00637-C-017 00637-C-016 00637-C-015 00637-C-019 00637-C-018 AD9856 POWER CONSUMPTION 1600 1450 +V = +3V +V = +3V S S CIC = 2 CIC = 2 200 MHz +25°C +25°C 1400 1350 HB3 = OFF 1200 1250 HB3 = ON 1000 1150 800 1050 120 140 160 180 200 25 50 75 100 CLOCK SPEED (MHz) Tx ENABLE DUTY CYCLE Figure 20. Power Consumption vs. Clock Speed; V = 3 V, CIC = 2, 25°C s Figure 22. Power Consumption vs. Burst Duty Cycle; VS = 3 V, CIC = 2, 200 MHz, 25°C 1600 +V = +3V S CIC = 2 200 MHz +25°C 1500 HB3 = OFF 1400 1300 HB3 = ON 1200 03 1624864 CIC RATE Figure 21. Power Consumption vs. CIC Rate; VS = 3 V, 200 MHz, 2°C Rev. C | Page 12 of 36 POWER CONSUMPTION (mW) POWER CONSUMPTION (mW) 00637-C-021 00637-C-020 POWER CONSUMPTION (mW) 00637-C-022 AD9856 SERIAL CONTROL BUS REGISTER Table 5. Serial Control Bus Register Layout Register AD9856 Register Layout Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Profile (hex) (hex) 00 SDO LSB REFCLK REFCLK REFCLK REFCLK REFCLK Reserved 15 N/A Active First Mult.<4> Mult.<3> Mult.<2> Mult.<1> Mult.<0> 01 CIC Continuous Full Sleep Single-tone Bypass Bypass Input Input 06 N/A Gain Mode Mode Mode Inverse Sinc REFCLK Format Format Filter Mult. Select Select <1> <0> 02 Frequency Tuning Word <7:0> 04 1 03 Frequency Tuning Word <15:8> 00 1 04 Frequency Tuning Word <23:16> 00 1 05 Frequency Tuning Word <31:24> 00 1 06 Interpolator Interpolator Interpolator Interpolator Interpolator Interpolator Spectral Bypass FC 1 Rate <5> Rate <4> Rate <3> Rate <2> Rate <1> Rate <0> Inversion the Third Half-Band Filter 07 AD8320/AD8321 Gain Control Bits <7:0> 00 1 08 Frequency Tuning Word <7:0> 00 2 09 Frequency Tuning Word <15:8> 00 2 0A Frequency Tuning Word <23:16> 00 2 0B Frequency Tuning Word <31:24> 80 2 0C Interpolator Interpolator Interpolator Interpolator Interpolator Interpolator Spectral Bypass 1E 2 Rate <5> Rate <4> Rate <3> Rate <2> Rate <1> Rate <0> Inversion the Third Half-Band Filter 0D AD8320/AD8321 Gain Control Bits <7:0> 00 2 0E Frequency Tuning Word <7:0> Unset 3 0F Frequency Tuning Word <15:8> Unset 3 10 Frequency Tuning Word <23:16> Unset 3 11 Frequency Tuning Word <31:24> Unset 3 12 Interpolator Interpolator Interpolator Interpolator Interpolator Interpolator Spectral Bypass Unset 3 Rate <5> Rate <4> Rate <3> Rate <2> Rate <1> Rate <0> Inversion the Third Half-Band Filter 13 AD8320/AD8321 Gain Control Bits <7:0> 00 3 14 Frequency Tuning Word <7:0> Unset 4 15 Frequency Tuning Word <15:8> Unset 4 16 Frequency Tuning Word <23:16> Unset 4 17 Frequency Tuning Word <31:24> Unset 4 18 Interpolator Interpolator Interpolator Interpolator Interpolator Interpolator Spectral Bypass Unset 4 Rate <5> Rate <4> Rate <3> Rate <2> Rate <1> Rate <0> Inversion the Third Half-Band Filter 19 AD8320/AD8321 Gain Control Bits <7:0> 00 4 Rev. C | Page 13 of 36 AD9856 REGISTER BIT DEFINITIONS Control Bits—Register Address 00h and 01h Input Format Select—Register Address 01h, Bits 1 and 0, form SDO Active—Register Address 00h, Bit 7. Active high indicates the input format mode bits. serial port uses dedicated in/out lines. Default low configures 10b = 12-bit mode serial port as single-line I/O. 01b = 6-bit mode 00b = 3-bit mode LSB First—Register Address 00h, Bit 6. Active high indicates serial port access is LSB-to-MSB format. Default low indicates Default value is 10b (12-bit mode). MSB-to-LSB format. Profile 1 Registers—Active when PROFILE Inputs are 00b REFCLK Multiplier—Register Address 00h, Bits 5, 4, 3, 2, 1 Frequency Tuning Word (FTW)—The frequency tuning word form the reference clock multiplier. Valid entries range from for Profile 1 is formed via a concatenation of register addresses 4–20 (decimal). Straight binary to decimal conversion is 05h, 04h, 03h, and 02h. Bit 7 of Register Address 05h is the implemented. For example, to multiply the reference clock by most significant bit of the Profile 1 frequency tuning word. Bit 0 19 decimal, Program Register Address 00h, Bits 5–1, as 13h. of Register Address 02h is the least significant bit of the Profile Default value is 0A (hex). 1 frequency tuning word. The output frequency equation is 32 given as: fOUT = (FTW SYSCLK)/2 . Reserved Bit—Register Address 00h, Bit 0. This bit is reserved. Always set this bit to Logic 1 when writing to this register. Interpolation Rate—Register Address 06h, Bit 7 through Bit 2 form the Profile 1 CIC filter interpolation rate value. Allowed CIC Gain—Register Address 01h, Bit 7. The CIC GAIN bit values range from 2 to 63 (decimal). multiplies the CIC filter output by 2. See the Cascaded Integrator Comb (CIC) Filter section for more details. Default Spectral Inversion—Register Address 06h, Bit 1. Active value is 0 (inactive). high, Profile 1 spectral inversion bit. When active, inverted modulation is performed [I Cos(ωt) + Q × Sin( t)]. The Continuous Mode—Register Address 01h, Bit 6 is the Default is inactive, Logic 0, noninverted modulation continuous mode configuration bit. Active high configures the [I × Cos(ωt) − Q × Sin(ωt)]. AD9856 to accept continuous-mode timing on the TxENABLE input. A low configures the device for burst-mode timing. Bypass Half-Band Filter 3—Register Address 06h, Bit 0. Default value is 0 (burst mode). Active high, causes the AD9856 to bypass the third half-band filter stage that precedes the CIC interpolation filter. Bypassing Full Sleep Mode—Register Address 01h, Bit 5. Active high the third half-band filter negates the 2× upsample inherent with full sleep mode bit. When activated, the AD9856 enters a full this filter and reduces the overall interpolation rate of the half- shutdown mode, consuming less than 2 mA after completing band filter chain from 8× to 4×. Default value is 0 (Half-Band 3 a shutdown sequence. Default value is 0 (awake). enabled). Single-Tone Mode—Register Address 01h, Bit 4. Active high AD8320/AD8321 Gain Control—Register Address 07h, Bit 7 configures the AD9856 for single-tone applications. The through Bit 0 form the Profile 1 AD8320/AD8321 gain bits. AD9856 supplies a single-frequency output as determined by The AD9856 dedicates three output pins, which directly the frequency tuning word (FTW) selected by the active profile. interface to the AD8320/AD8321 cable driver amp. This In this mode, the 12 input data pins are ignored but should be allows direct control of the cable driver via the AD9856. See tied high or low. Default value is 0 (inactive). the Error! Reference source not found. section for more details. Bit 7 is the MSB, Bit 0 is the LSB. Default value is 00h. Bypass Inverse Sinc Filter—Register Address 01h, Bit 3. Active high configures the AD9856 to bypass the SIN(x)/x Profile 2 Registers—Active when PROFILE Inputs are 01b compensation filter. Default value is 0 (inverse SINC filter Profile 2 register functionality is identical to Profile 1, with the enabled). exception of the register addresses. Bypass REFCLK Multiplier—Register Address 01h, Bit 2. Profile 3 Registers—Active when PROFILE Inputs are 10b Active high configures the AD9856 to bypass the REFCLK Profile 3 register functionality is identical to Profile 1, with the multiplier function. When active, effectively causes the exception of the register addresses. REFCLK multiplier factor to be 1. Default value is 1 (REFCLK Profile 4 Registers—Active when PROFILE Inputs are 11b multiplier bypassed). Profile 4 register functionality is identical to Profile 1, with the exception of the register addresses. Rev. C | Page 14 of 36 AD9856 THEORY OF OPERATION To gain a general understanding of the functionality of the Once through the data assembler, the I/Q data streams are fed AD9856, it is helpful to refer to Figure 23, a block diagram of through two half-band filters (Half-Band Filters 1 and 2). The the device architecture. The following is a general description of combination of these two filters results in a factor of four (4) the device functionality. Later sections detail each of the data increase of the sample rate. Thus, at the output of Half-Band path building blocks. Filter 2, the sample rate is 4 × f . In addition to the sample rate IQ increase, the half-band filters provide the low-pass filtering MODULATION MODE OPERATION characteristic necessary to suppress the spectral images The AD9856 accepts 12-bit data-words, which are strobed into produced by the upsampling process. Further upsampling is the data assembler via an internal clock. The input, TxENABLE, available via an optional third half-band filter (Half-Band serves as the valve that allows data to be accepted or ignored by Filter 3). When selected, this provides an overall upsampling the data assembler. The user has the option to feed the 12-bit factor of eight (8). Thus, if Half-Band Filter 3 is selected, the data-words to the AD9856 as single 12-bit words, dual 6-bit sample rate at its output is 8 × fIQ. words, or quad 3-bit words. This provides the user with the After passing through the half-band filter stages, the I/Q data flexibility to use fewer interface pins, if desired. Furthermore, streams are fed to a cascaded integrator comb (CIC) filter. the incoming data is assumed to be complex in that alternating This filter is configured as an interpolating filter, which allows 12-bit words are regarded as the inphase (I) and quadrature (Q) further upsampling rates of any integer value between 2 and 63, components of a symbol. inclusive. The CIC filter, like the half-bands, has a built-in low- The rate at which the 12-bit words are presented to the AD9856 pass characteristic. Again, this provides for suppression of the is referred to as the input sample rate (f ). Note that f is not IN IN spectral images produced by the upsampling process. the same as the baseband data rate provided by the user. Rather, The digital quadrature modulator stage following the CIC the user’s baseband data is required to be upsampled by at least filters is used to frequency shift the baseband spectrum of a factor of two (2) before being applied to the AD9856 in order the incoming data stream up to the desired carrier frequency to minimize the frequency-dependent attenuation associated (a process known as upconversion). The carrier frequency is with the CIC filter stage (see the Cascaded Integrator Comb controlled numerically by a direct digital synthesizer (DDS). (CIC) Filter section ). The DDS uses its internal reference clock (SYSCLK) to generate The data assembler splits the incoming data-word pairs into the desired carrier frequency with a high degree of precision. separate I/Q data streams. The rate at which the I/Q data-word The carrier is applied to the I and Q multipliers in quadrature pairs appear at the output of the data assembler is referred to as fashion (90° phase offset) and summed to yield a data stream the I/Q sample rate (fIQ). Because two 12-bit input data-words that is the modulated carrier. Note that the incoming data has are used to construct the individual I and Q data paths, the been converted from an input sample rate of f to an output IN input sample rate is twice the I/Q sample rate (i.e., fIN = 2 × fIQ). sample rate of SYSCLK (see Figure 23). QUADRATURE MODULATOR HALF-BAND CIC FILTER #3 DATA HALF-BAND HALF-BAND HBF #3 FILTER ASSEMBLER FILTER #1 FILTER #2 COS BYPASS 12 R SET INV SINC 12 12 MUX 12 12 BYPASS I 3, 6, 12 12 DATA MUX DAC A OUT IN INV SINC TxENABLE 12 12 12 12 Q 12 HBF #3 MUX BYPASS SIN (F1) (F2) DDS M = 4...20 MUX REFCLK HBF #3 BYPASS MULTIPLIER (F3) (M) ÷2 ÷2 MUX (F5) ÷2 MUX ÷N (SYSCLK) REFCLK (F4) N = 2...63 Figure 23. AD9856 Block Diagram Rev. C | Page 15 of 36 00637-C-023 AD9856 The sampled carrier is ultimately destined to serve as the input INPUT WORD RATE (F ) vs. REFCLK RELATIONSHIP W data to the digital-to-analog converter (DAC) integrated on the There is a fundamental relationship between the input word AD9856. The DAC output spectrum is distorted due to the rate (fW) and the frequency of the clock that serves as the timing intrinsic zero-order hold effect associated with DAC-generated source for the AD9856 (REFCLK). The fW is defined as the rate signals. This distortion is deterministic, however, and follows at which K-bit data-words (K = 3, 6, or 12) are presented to the the familiar SIN(x)/x (or SINC) envelope. Because the SINC AD9856. However, the following factors affect this relationship: distortion is predictable, it is also correctable—therefore, the • The interpolation rate of the CIC filter stage. presence of the optional inverse SINC filter preceding the DAC. • Whether or not Half-Band Filter 3 is bypassed. This is a FIR filter, which has a transfer function conforming to • The value of the REFCLK multiplier (if selected). the inverse of the SINC response. Thus, when selected, it • Input word length. modifies the incoming data stream so that the SINC distortion, This relationship can be summed as which would otherwise appear in the DAC output spectrum, is virtually eliminated. REFCLK=(2 HNf )/MI W As mentioned earlier, the output data is sampled at the rate where H, N, I, and M are integers determined as follows: of SYSCLK. Because the AD9856 is designed to operate at H = 1: Half-Band Filter 3 bypassed SYSCLK frequencies up to 200 MHz, there is the potential 2: Half-Band Filter 3 enabled difficulty of trying to provide a stable input clock (REFCLK). M = 1: REFCLK multiplier bypassed Although stable, commercial high frequency oscillators tend 4 ≤ M ≤ 20: REFCLK multiplier enabled to be cost prohibitive. To alleviate this problem, the AD9856 has a built-in programmable clock multiplier circuit. This I = 1: Full-word input format allows the user to use a relatively low frequency (thus, less 2: Half-word input format expensive) oscillator to generate the REFCLK signal. The low 4: Quarter-Word input format frequency REFCLK signal can then be multiplied in frequency N = CIC interpolation rate (2 ≤ N ≤ 63) by an integer factor between 4 and 20, inclusive, to become the These conditions show that REFCLK and f have an integer W SYSCLK signal. ratio relationship. It is very important that users choose a value Single-Tone Output Operation of REFCLK to ensure that this integer ratio relationship is The AD9856 can be configured for frequency synthesis maintained. applications by writing the single-tone bit true. In single-tone I/Q DATA SYNCHRONIZATION mode, the AD9856 disengages the modulator and preceding data path logic to output a spectrally pure, single-frequency sine As mentioned previously, the AD9856 accepts I/Q data pairs wave. The AD9856 provides for a 32-bit frequency tuning word, and a twos complement numbering system in three different which results in a tuning resolution of 0.046 Hz at a SYSCLK word length modes. The full-word mode accepts 12-bit parallel rate of 200 MHz. I and Q data. The half-word mode accepts dual 6-bit I and Q data inputs to form a 12-bit word. The quarter-word mode When using the AD9856 as a frequency synthesizer, a general accepts multiple 3-bit I and Q data inputs to form a 12-bit word. rule is to limit the fundamental output frequency to 40% of For all word length modes, the AD9856 assembles the data for SYSCLK. This avoids generating aliases too close to the desired signal processing into time-aligned, parallel, 12-bit I/Q pairs. fundamental output frequency, thus minimizing the cost of In addition to the word length flexibility, the AD9856 has filtering the aliases. two input timing modes, burst or continuous, that are programmable via the serial port. All applicable programming features of the AD9856 apply when configured in single-tone mode. These features include: For burst-mode input timing, no external data clock needs to • Frequency hopping via the profile inputs and associated be provided, because the data is oversampled at the D<11:0> tuning word, which allows frequency shift keying (FSK) pins using the system clock (SYSCLK). The TxENABLE pin modulation. is required to frame the data burst, because the rising edge of • Ability to bypass the REFCLK multiplier, which results in TxENABLE is used to synchronize the AD9856 to the input lower phase noise and reduced output jitter. data rate. The AD9856 registers the input data at the approx- • Ability to bypass the SIN(x)/x compensation filter. imate center of the data valid time. Thus, for larger CIC interpolation rates, more SYSCLK cycles are available to • Full power-down mode. oversample the input data, maximizing clock jitter tolerances. Rev. C | Page 16 of 36 AD9856 For continuous-mode input timing, the TxENABLE pin can Figure 26 shows the input timing for half-word mode, burst be thought of as a data input clock running at half the input input timing operation. sample rate (f /2). In addition to synchronization, for contin- W In half-word mode, data is input on the D<11:6> inputs. The uous mode timing, the TxENABLE input indicates whether an D<5:0> inputs are unused in this mode and should be tied to I or Q input is being presented to the D<11:0> pins. It is DGND or DVDD. The AD9856 expects the data to be input intended that data is presented in alternating fashion such that in the following manner: I<11:6>, I<5:0>, Q<11:6>, Q<5:0>. I data is followed by Q data. Stated another way, the TxENABLE Data is twos complement; the sign bit is D<11> in the notation pin should maintain approximately a 50/50 duty cycle. As in I<11:0>, Q<11:0>. burst mode, the rising edge of TxENABLE synchronizes the AD9856 to the input data rate and the data is registered at the The input sample rate for half-word mode, when the third half- approximate center of the data-valid time. The continuous band filter is engaged, is given by operating mode can only be used in conjunction with the full- f = SYSCLK/4N word input format. IN Burst Mode Input Timing where N is the CIC interpolation rate. Figure 24 through Figure 28 show the input timing relationship The input sample rate for half-word mode, when the third half- between TxENABLE and the 12-bit input data-word for all band filter is not engaged is given by: three input format modes when the AD9856 is configured for burst input timing. Also shown in these diagrams is the time- f = SYSCLK/2N IN aligned, 12-bit parallel I/Q data as assembled by the AD9856. where N is the CIC interpolation rate. Figure 24 shows the classic burst-mode timing, for full-word input mode, in which TxENABLE frames the input data stream. Figure 27 shows the input timing for quarter-word, burst input Note that sequential input of alternating I/Q data, starting with timing operation. I data, is required. In quarter-word mode, data is input on the D<11:9> inputs. The The input sample rate for full-word mode, when the third half- D<8:0> inputs are unused in this mode and should be tied to band filter is engaged, is given by DGND or DVDD. The AD9856 expects the data to be input in the following manner: I<11:9>, I<8:6>, I<5:3>, I<2:0>, f = SYSCLK/4N IN Q<11:9>, Q<8:6>, Q<5:3>, Q<2:0>. Data is twos complement; the sign bit is D<11> in the notation I<11:0>, Q<11:0>. where N is the CIC interpolation rate. The input sample rate for quarter-word mode, when the third The input sample rate for full-word mode, when the third half- half-band filter is engaged, is given by: band filter is not engaged is given by: f = SYSCLK/N f = SYSCLK/2N IN IN where N is the CIC interpolation rate. where N is the CIC interpolation rate Note that Half-Band Filter 3 must be engaged when operating Figure 25 shows an alternate timing method for TxENABLE in quarter-word mode. when the AD9856 is configured in full-word, burst-mode operation. The benefit of this timing is that the AD9856 Figure 28 describes the end of burst timing and internal data resynchronizes the input sampling logic when the rising edge of assembly. Note that in burst-mode operation, if the TxENABLE TxENABLE is detected. The low time on TxENABLE is limited input is low for more than one input sample period, numerical to one input sample period and must be low during the Q data zeros are internally generated and passed to the data path logic period. The maximum high time on TxENABLE is unlimited. for signal processing. This is not valid for continuous-mode Thus, unlimited high time on TxENABLE results in the timing operation, as is discussed later. diagram of Figure 24. See Figure 28 for the ramifications of violating the TxENABLE low time constraint when operating To ensure proper operation, the minimum time between falling in burst mode. and rising edges of TxENABLE is one input sample period. Rev. C | Page 17 of 36 AD9856 TxENABLE D(11:0) I0 Q0 I1 Q1 I2 Q2 I3 Q3 I4 Q4 INTERNAL I I0 I1 I2 I3 INTERNAL Q Q0 Q1 Q2 Q3 Figure 24. 12-Bit Input Mode, Classic Burst Timing TxENABLE D(11:0) I0 Q0 I1 Q1 I2 Q2 I3 Q3 I4 Q4 INTERNAL I I0 I1 I2 I3 INTERNAL Q Q0 Q1 Q2 Q3 Figure 25. 12-Bit Input Mode, Alternate TxENABLE Timing TxENABLE D(11:6) I0(11:6) I0(5:0) Q0(5:0) Q0(11:6) I1(11:6) I1(5:0) Q1(11:6) Q1(5:0) I2(11:6) I2(5:0) INTERNAL I I0 I1 INTERNAL Q Q0 Q1 Figure 26. 6-Bit Input Mode, Burst Mode Timing TxENABLE D(11:9) I0(11:9) I0(8:6) I0(5:3) I0(2:0) Q0(11:9) Q0(8:6) Q0(5:3) Q0(2:0) I1(11:9) I1(8:6) INTERNAL I I0 INTERNAL Q Q0 Figure 27. 3-Bit Input Mode, Burst Mode Timing TxENABLE D(11:0) IN QN I0 Q0 I1 Q1 INTERNAL I IN–2 IN–1 IN LOGIC 0 I0 INTERNAL Q QN–2 QN–1 QN LOGIC 0 Q0 Figure 28. End of Burst Mode Input Timing Rev. C | Page 18 of 36 00637-C-027 00637-C-026 00637-C-024 00637-C-028 00637-C-025 AD9856 Continuous Mode Input Timing The AD9856 is configured for continuous mode input timing edge of TxENABLE. Also note that the significant difference by writing the continuous mode bit true (Logic 1). The between burst and continuous mode operation is that in continuous mode bit is in register address 01h, Bit 6. The addition to synchronizing the data, TxENABLE is used to AD9856 must be configured for full-word input format when indicate whether an I or Q input is being sampled. operating in continuous mode input timing. The input data rate Do not engage continuous mode simultaneously with the equations described previously for full-word mode apply for REFCLK multiplier function. This corrupts the CIC inter- continuous mode. Figure 25, which is the alternate burst mode polating filter, forcing unrecoverable mathematical overflow timing diagram, is also the continuous mode input timing. that can only be resolved by issuing a RESET command. The Figure 29 and Figure 30 show what the internal data assembler problem is due to the PLL failing to be locked to the reference presents to the signal processing logic when the TxENABLE clock while nonzero data is being clocked into the interpolation input is held static for greater than one input sample period. stages from the data inputs. The recommended sequence is to Please note that the timing diagram shown in Figure 29 and first engage the REFCLK multiplier function (allowing at least Figure 30 detail INCORRECT timing relationships between 1 ms for loop stabilization) and then engage continuous mode TxENABLE and data. They are only presented to indicate that via software. the AD9856 resynchronizes properly after detecting a rising TxENABLE D(11:0) QN IN+1 QN+1 IN+2 QN+2 IN+3 QN+3 IN+4 QN+4 IN+5 INTERNAL I IN–1 IN IN+1 IN+2 IN+3 IN+4 INTERNAL Q QN QN–1 QN+3 QN+4 Figure 29. Continuous Mode Input Timing—TxENABLE Static High (for illustrative purposes only) TxENABLE D(11:0) IN QN IN+1 QN+1 IN+2 QN+2 IN+3 QN+3 IN+4 QN+4 INTERNAL I IN–1 IN IN+3 INTERNAL Q QN–1 QN QN+1 QN+2 QN+3 Figure 30. Continuous Mode Input Timing—TxENABLE Static Low (for illustrative purposes only) Rev. C | Page 19 of 36 00637-C-030 00637-C-029 AD9856 HALF-BAND FILTERS (HBFS) Before presenting a detailed description of the HBFs, recall that a raised cosine response. In such cases, an α value is used to the input data stream is representative of complex data; i.e., two modify the bandwidth of the data where the value of α is such input samples are required to produce one I/Q data pair. The that 0 ≤ α ≤ 1. A value of 0 causes the data bandwidth to I/Q sample rate is one-half the input data rate. The I/Q sample correspond to the Nyquist bandwidth. A value of 1 causes the rate (the rate at which I or Q samples are presented to the input data bandwidth to be extended to twice the Nyquist bandwidth. of the first half-band filter) is referred to as f . Because the Thus, with 2× oversampling of the baseband data and α = 1, IQ AD9856 is a quadrature modulator, fIQ represents the baseband the Nyquist bandwidth of the data corresponds with the I/Q of the internal I/Q sample pairs. It should be emphasized here Nyquist bandwidth. As stated earlier, this results in problems that fIQ is not the same as the baseband of the user’s symbol rate near the upper edge of the data bandwidth due to the frequency data, which must be upsampled before presentation to the response of HBF 1 and 2. AD9856 (as is explained later). The I/Q sample rate (f ) puts IQ 10 a limit on the minimum bandwidth necessary to transmit the 0 f spectrum. This is the familiar Nyquist limit and is equal to IQ –10 one half f , which is referred to as f . IQ NYQ –20 HBF 1 is a 47-tap filter that provides a factor-of-two increase in –30 the sampling rate. HBF 2 is a 15-tap filter offering an additional –40 factor-of-two increase in the sampling rate. Together, HBF 1 –50 and HBF 2 provide a factor-of-four increase in the sampling –60 rate (4 × f or 8 × f ). Their combined insertion loss is a mere IQ NYQ –70 0.01 dB, so virtually no loss of signal level occurs through the –80 first two HBFs. HBF 3 is an 11-tap filter and, if selected, –90 increases the sampling rate by an additional factor of two. Thus, –100 the output sample rate of HBF 3 is 8 × fIQ or 16 × fNYQ. HBF 3 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 exhibits 0.03 dB of signal-level loss. As such, the loss in signal DISPLAYED FREQUENCY IS RELATIVE TO I/Q NYQ. BW level through all three HBFs is only 0.04 dB and may be ignored Figure 31. Half-Band 1 and 2 Frequency Response for all practical purposes. 1 In relation to phase response, all three HBFs are linear phase 0 filters. As such, virtually no phase distortion is introduced within the pass band of the filters. This is an important feature –1 as phase distortion is generally intolerable in a data transmission system. –2 In addition to knowledge of the insertion loss and phase –3 response of the HBFs, some knowledge of the frequency –4 response of the HBFs is useful as well. The combined frequency response of HBF 1 and 2 is shown in Figure 31 and Figure 32. –5 The usable bandwidth of the filter chain puts a limit on the –6 maximum data rate that can be propagated through the device. 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 A look at the pass-band detail of the HBF 1 and HFB 2 response DISPLAYED FREQUENCY IS RELATIVE TO I/Q NYQ. BW indicates that to maintain an amplitude error of no more than Figure 32. Pass-Band Detail: Combined Frequency Response of HBF 1 and 2 1 dB, users are restricted to signals having a bandwidth of no more than about 90% of f . To keep the bandwidth of the data NYQ To reiterate, the user must oversample the baseband data by at in the flat portion of the filter pass band, users must oversample least a factor of two (2). In addition, there is a further restriction the baseband data by at least a factor of two prior to presenting on pulse shaping—the maximum value of α that can be imple- it to the AD9856. Without over-sampling, the Nyquist band- mented is 0.8. This is because the data bandwidth becomes width of the baseband data corresponds to the fNYQ. As such, 1/2(1 + α) fNYQ = 0.9 fNYQ, which puts the data bandwidth at the the upper end of the data bandwidth suffers 6 dB or more of extreme edge of the flat portion of the filter response. If a attenuation due to the frequency response of HBF 1 and HBF 2. particular application requires an α value between 0.8 and 1, Furthermore, if the baseband data applied to the AD9856 has then the user must oversample the baseband data by at least a been pulse shaped, there is an additional concern. Typically, factor of four (4). pulse shaping is applied to the baseband data via a filter having Rev. C | Page 20 of 36 MAGNITUDE (dB) MAGNITUDE (dB) 00637-C-032 00637-C-031 AD9856 In applications requiring both a low data rate and a high output In addition to the ability to provide a change in sample rate sample rate, a third HBF is available (HBF 3). Selecting HBF 3 between input and output, a CIC filter also has an intrinsic low- offers an upsampling ratio of eight (8) instead of four (4). The pass frequency response characteristic. The frequency response combined frequency response of HBF 1, 2, and 3 is shown in of a CIC filter depends on: Figure 33 and Figure 34. Comparing the pass-band detail of • The rate change ratio, R. HBF 1 and 2 with the pass-band detail of HBF 1, 2, and 3, • The order of the filter, N. HBF 3 has virtually no impact on frequency response from • The number of unit delays per stage, M. 0 to 1 (where 1 corresponds to fNYQ). The system function, H(z), of a CIC filter is given by: 10 N N −RM RM−1 0 ⎛ ⎞ ⎛ ⎞ 1−z −κ ⎜ ⎟ ⎜ ⎟ H (z)= = z ∑ −1 ⎜ ⎟ ⎜ ⎟ –10 1−z κ=0 ⎝ ⎠ ⎝ ⎠ –20 The form on the far right has the advantage of providing a –30 result for z = 1 (corresponding to zero frequency or dc). The –40 alternate form yields an indeterminate form (0/0) for z = 1, –50 but is otherwise identical. The only variable parameter for –60 the AD9856 CIC filter is R. M and N are fixed at 1 and 4, –70 respectively. Thus, the CIC system function for the AD9856 –80 simplifies to: –90 4 4 –100 −R R−1 ⎛ ⎞ ⎛ ⎞ 05 12 3 4678 1−z −κ ⎜ ⎟ ⎜ ⎟ H (z)= = z ∑ −1 ⎜ ⎟ ⎜ ⎟ DISPLAYED FREQUENCY IS RELATIVE TO I/Q NYQ. BW 1−z κ=0 ⎝ ⎠ ⎝ ⎠ Figure 33. Half-Band 1, 2, and 3 Frequency Response The transfer function is given by: 1 4 4 −j (2π fR) R−1 ⎛ ⎞ ⎛ ⎞ 1−e −j (2π fκ ) 0 ⎜ ⎟ ⎜ ⎟ H (f )= = e ∑ −j (2π f ) ⎜ ⎟ ⎜ ⎟ 1−e κ=0 ⎝ ⎠ ⎝ ⎠ –1 The frequency response in this form is such that f is scaled –2 to the output sample rate of the CIC filter. That is, f = 1 corresponds to the frequency of the output sample rate of the –3 CIC filter. H(f/R) yields the frequency response with respect to the input sample of the CIC filter. Figure 35 to Figure 44 show –4 the CIC frequency response and pass-band detail for R = 2 and –5 R = 63, with HBF 3 bypassed. Figure 45 to Figure 50 are similar, but HBF 3 is selected. Note the flatter pass-band response when –6 HBF 3 is employed. 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 DISPLAYED FREQUENCY IS RELATIVE TO I/Q NYQ. BW As with HBFs, consideration must be given to the frequency- Figure 34. Pass-Band Detail: Combined Frequency Response of HBF 1 to 3 dependent attenuation that the CIC filter introduces over the frequency range of the data to be transmitted. Note that the CASCADED INTEGRATOR COMB (CIC) FILTER CIC frequency response figures have f as their reference NYQ A CIC filter is unlike a typical FIR filter in that it offers the frequency; i.e., unity (1) on the frequency scale corresponds flexibility to handle differing input and output sample rates to fNYQ. If the incoming data that is applied to the AD9856 is (only in integer ratios, however). In the purest sense, a CIC oversampled by a factor of 2 (as required), then the Nyquist filter can provide either an increase or a decrease in the sample bandwidth of the applied data is one-half fNYQ on the CIC rate at the output relative to the input, depending on the archi- frequency response figures. A look at the 0.5 point on the pass- tecture. If the integration stage precedes the comb stage, the band detail figures reveals a worst-case attenuation of about CIC filter provides sample rate reduction (decimation). When 0.25 dB (HBF 3 bypassed, R = 63). This, of course, assumes the comb stage precedes the integrator stage the CIC filter pulse-shaped data with α = 0 (minimum bandwidth scenario). provides an increase in sample rate (interpolation). In the When a value of α = 1 is used, the bandwidth of the data AD9856, the CIC filter is configured as an interpolator— corresponds to fNYQ (the point1.0 on the CIC frequency scale). a programmable interpolator—and provides a sample rate Thus, the worst-case attenuation for α = 1 is about 0.9 dB. increase, R, such that 2 ≤ R ≤ 63. Rev. C | Page 21 of 36 MAGNITUDE (dB) MAGNITUDE (dB) 00637-C-034 00637-C-033 AD9856 0 0 –0.5 –30 –1.0 –1.5 –60 –2.0 –90 –2.5 –3.0 –120 –3.5 –150 –4.0 02 48 12 160242832 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 DISPLAYED FREQUENCY IS RELATIVE TO I/Q NYQ. BW DISPLAYED FREQUENCY IS RELATIVE TO I/Q NYQ. BW Figure 35. CIC Filter Frequency Response (R = 2, HFB 3 Bypassed) Figure 36. Pass-Band Detail (R = 2, HFB 3 Bypassed) 0 0 –0.5 –30 –1.0 –1.5 –60 –2.0 –90 –2.5 –3.0 –120 –3.5 –150 –4.0 0 72 144 216 258 360 432 504 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 DISPLAYED FREQUENCY IS RELATIVE TO I/Q NYQ. BW DISPLAYED FREQUENCY IS RELATIVE TO I/Q NYQ. BW Figure 37. CIC Filter Frequency Response (R = 63, HFB 3 Bypassed) Figure 38. Pass-Band Detail (R = 63, HFB 3 Bypassed) The degree of the impact of the attenuation introduced by the To help overcome the insertion loss problem, the AD9856 CIC filter over the Nyquist bandwidth of the data is application provides the user a means to boost the gain through the CIC specific. The user must decide how much attenuation is stage by a factor of 2 (via the CIC Gain bit—see the Serial acceptable. If less attenuation is desired, then additional Control Bus Register section). The reason for this feature is to oversampling of the baseband data must be employed. allow the user to take advantage of the full dynamic range of the Alternatively, the user can precompensate the baseband data DAC, thus maximizing the signal-to-noise ratio (SNR) at the before presenting it to the AD9856. That is, if the data is output of the DAC stage. It is best to operate the DAC over its precompensated through a filter that has a frequency response full-scale range in order to minimize the inherent quantization characteristic, which is the inverse of the CIC filter response, effects associated with a DAC. Any significant loss through the then the overall system response can be nearly perfectly CIC stage is reflected at the DAC output as a reduction in SNR. flattened over the bandwidth of the data. The degradation in SNR can be overcome by boosting the CIC output level. Table 6 tabulates insertion loss as a function of R. Another issue to consider with the CIC filters is insertion loss. The values are provided in linear and decibel form, both with Unfortunately, CIC insertion loss is not fixed, but is a function and without the factor-of-2 gain employed. of R, M, and N. Because M, and N are fixed for the AD9856, the CIC insertion loss is a function of R only. A word of caution: When the CIC Gain bit is active, ensure that the data supplied to the AD9856 is scaled down to yield an Interpolation rates that are an integer power-of-2 result in no overall gain of unity (1) through the CIC filter stage. Gains in insertion loss. However, all noninteger power-of-2 interpolation excess of unity are likely to cause overflow errors in the data rates result in a specific amount of insertion loss. path, compromising the validity of the analog output signal. Rev. C | Page 22 of 36 MAGNITUDE (dB) MAGNITUDE (dB) 00637-C-036 00637-C-035 MAGNITUDE (dB) MAGNITUDE (dB) 00637-C-038 00637-C-037 AD9856 0 0 –0.5 –30 –1.0 –1.5 –60 –2.0 –90 –2.5 –3.0 –120 –3.5 –150 –4.0 02 48 12 160242832 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 DISPLAYED FREQUENCY IS RELATIVE TO I/Q NYQ. BW DISPLAYED FREQUENCY IS RELATIVE TO I/Q NYQ. BW Figure 39. CIC Filter Frequency Response (R = 2, HBF 3 Selected) Figure 40. Pass-Band Detail (R = 2, HBF 3 Selected) 0 0 –0.5 –30 –1.0 –1.5 –60 –2.0 –90 –2.5 –3.0 –120 –3.5 –150 –4.0 0 144 288 432 576 720 864 1008 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 DISPLAYED FREQUENCY IS RELATIVE TO I/Q NYQ. BW DISPLAYED FREQUENCY IS RELATIVE TO I/Q NYQ. BW Figure 41. CIC Filter Frequency Response (R = 63, HBF 3 Active) Figure 42. Pass-Band Detail (R = 63, HBF 3 Active) DIGITAL QUADRATURE MODULATOR Note that the architecture of the quadrature modulator results Following the CIC filter stage the I and Q data (which have in a 3 dB loss of signal level. To visualize this, assume that both been processed independently up to this point) are mixed in the the I data and Q data are fixed at the maximum possible digital modulator stage to produce a digital modulated carrier. The value, x. Then the output of the modulator, y, is: carrier frequency is selected by programming the direct digital synthesizer (see the Direct Digital Synthesizer Function section) y = x × cos(ω) + x × sin(ω) = x × [cos(ω) + sin(ω)] with the appropriate 32-bit tuning word via the AD9856 control From this equation, y assumes a maximum value of x√2 registers. The DDS simultaneously generates a digital (sampled) sine and cosine wave at the programmed carrier frequency. The (a gain of 3 dB). However, if the same number of bits were digital sine and cosine data is multiplied by the Q and I data, used to represent the y values, as is used to represent the x respectively, to create the quadrature components of the values, an overflow would occur. To prevent this, an effective original data upconverted to the carrier frequency. The divide-by-two is implemented on the y values, which reduces quadrature components are digitally summed and passed on to the maximum value of y by a factor of two. Because division by the subsequent stages. two results in a 6 dB loss, the modulator yields an overall loss of 3 dB (3 dB − 6 dB = −3 dB, or 3 dB of loss). The key point is that the modulation is done digitally, which eliminates the phase and gain imbalance and crosstalk issues typically associated with analog modulators. Note that the modulated signal is actually a number stream sampled at the rate of SYSCLK, which is the same rate at which the DAC is clocked (see Figure 23). Rev. C | Page 23 of 36 MAGNITUDE (dB) MAGNITUDE (dB) 00637-C-040 00637-C-039 MAGNITUDE (dB) MAGNITUDE (dB) 00637-C-042 00637-C-041 AD9856 Table 6. CIC Interpolation Filter Insertion Loss Table Default Gain 2 × Gain Default Gain 2 × Gain Interpolation Interpolation Rate Rate (Linear) (dB) (Linear) (dB) (Linear) (dB) (Linear) (dB) 2 1.0000 0.000 2.0000 6.021 50 0.9537 −0.412 1.9073 5.609 3 0.8438 −1.476 1.6875 4.545 51 0.5060 −5.917 1.0120 0.104 4 1.0000 0.000 2.0000 6.021 52 0.5364 −5.411 1.0728 0.610 5 0.9766 −0.206 1.9531 5.815 53 0.5679 −4.914 1.1358 1.106 6 0.8438 −1.476 1.6875 4.545 54 0.6007 −4.427 1.2014 1.593 7 0.6699 −3.480 1.3398 2.541 55 0.6347 −3.949 1.2693 2.072 8 1.0000 0.000 2.0000 6.021 56 0.6699 −3.480 1.3398 2.541 9 0.7119 −2.951 1.4238 3.069 57 0.7065 −3.018 1.4129 3.002 10 0.9766 −0.206 1.9531 5.815 58 0.7443 −2.565 1.4886 3.455 11 0.6499 −3.743 1.2998 2.278 59 0.7835 −2.120 1.5669 3.901 12 0.8438 −1.476 1.6875 4.545 60 0.8240 −1.682 1.6479 4.339 13 0.5364 −5.411 1.0728 0.610 61 0.8659 −1.251 1.7317 4.770 14 0.6699 −3.480 1.3398 2.541 62 0.9091 −0.827 1.8183 5.193 15 0.8240 −1.682 1.6479 4.339 63 0.9539 −0.410 1.9077 5.610 16 1.0000 0.000 2.0000 6.021 17 0.5997 −4.441 1.1995 1.580 INVERSE SINC FILTER (ISF) 18 0.7119 −2.951 1.4238 3.069 The AD9856 is almost entirely a digital device. The input signal 19 0.8373 −1.543 1.6746 4.478 is made up of a time series of digital data-words. These data- 20 0.9766 −0.206 1.9531 5.815 words propagate through the device as numbers. Ultimately, 21 0.5652 −4.955 1.1305 1.065 this number stream must be converted to an analog signal. 22 0.6499 −3.743 1.2998 2.278 To this end, the AD9856 incorporates an integrated DAC. 23 0.7426 −2.585 1.4852 3.436 The output waveform of the DAC is the familiar staircase 24 0.8438 −1.476 1.6875 4.545 pattern typical of a signal that is sampled and quantized. The 25 0.9537 −0.412 1.9073 5.609 staircase pattern is a result of the finite time that the DAC holds 26 0.5364 −5.411 1.0728 0.610 a quantized level until the next sampling instant. This is known 27 0.6007 −4.427 1.2014 1.593 as a zero-order hold function. The spectrum of the zero-order 28 0.6699 −3.480 1.3398 2.541 hold function is the SIN(x)/x, or SINC, envelope. 29 0.7443 −2.565 1.4886 3.455 The series of digital data-words presented at the input of the 30 0.8240 −1.682 1.6479 4.339 31 0.9091 −0.827 1.8183 5.193 DAC represent an impulse stream. It is the spectrum of this 32 1.0000 0.000 2.0000 6.021 impulse stream, which is the desired output signal. Due to 33 0.5484 −5.219 1.0967 0.802 the zero-order hold effect of the DAC, however, the output 34 0.5997 −4.441 1.1995 1.580 spectrum is the product of the zero-order hold spectrum 35 0.6542 −3.686 1.3084 2.335 (the SINC envelope) and the Fourier transform of the impulse stream. Thus, there is an intrinsic distortion in the output 36 0.7119 −2.951 1.4238 3.069 spectrum, which follows the SINC response. 37 0.7729 −2.237 1.5458 3.783 38 0.8373 −1.543 1.6746 4.478 The SINC response is deterministic and totally predictable. 39 0.9051 −0.866 1.8103 5.155 Thus, it is possible to predistort the input data stream in a 40 0.9766 −0.206 1.9531 5.815 manner that compensates for the SINC envelope distortion. 41 0.5258 −5.583 1.0517 0.437 This can be accomplished by means of an ISF. The ISF 42 0.5652 −4.955 1.1305 1.065 incorporated on the AD9856 is a 17-tap, linear phase FIR filter. 43 0.6066 −4.342 1.2132 1.679 Its frequency response characteristic is the inverse of the SINC 44 0.6499 −3.743 1.2998 2.278 envelope. Data sent through the ISF is altered to correct for the 45 0.6952 −3.157 1.3905 2.863 SINC envelope distortion. 46 0.7426 −2.585 1.4852 3.436 47 0.7921 −2.024 1.5842 3.996 Note, however, that the ISF is sampled at the same rate as 48 0.8438 −1.476 1.6875 4.545 the DAC. Thus, the effective range of the SINC envelope 49 0.8976 −0.938 1.7952 5.082 compensation only extends to the Nyquist frequency (1/2 of the DAC sample rate). Rev. C | Page 24 of 36 AD9856 Figure 43 shows the effectiveness of the ISF in correcting for A Technical Tutorial on Digital Signal Synthesis is available on the SINC distortion. The plot includes a graph of the SINC the Analog Devices website at: envelope, the ISF response and the SYSTEM response (which is http://www.analog.com/UploadedFiles/Tutorials/450968421DD the product of the SINC and ISF responses). Note that the ISF S_Tutorial_rev12-2-99.pdf exhibits an insertion loss of 3.1 dB. Thus, signal levels at the The tutorial provides basic applications information for a output of the AD9856 with the ISF bypassed are 3.1 dB higher variety of digital synthesis implementations, as well as a detailed than with the ISF engaged. For modulated output signals, explanation of aliases. however, which have a relatively wide bandwidth, the benefits of the SINC compensation usually outweigh the 3 dB loss in D/A CONVERTER output level. The decision of whether to use the ISF is an A 12-bit digital-to-analog converter (DAC) is used to convert application specific system design issue. the digitally processed waveform into an analog signal. The worst-case spurious signals due to the DAC are the harmonics 4 of the fundamental signal and their aliases (see the AD9851 3 Complete-DDS data sheet for a details about aliased images). ISF The wideband 12-bit DAC in the AD9856 maintains spurious- 2 free dynamic range (SFDR) performance of −60 dBc up to 1 AOUT = 42 MHz and −55 dBc up to AOUT = 65 MHz. SYSTEM 0 The conversion process produces aliased components of the –1 fundamental signal at n × SYSCLK ± FCARRIER (n = 1, 2, 3). These are typically filtered with an external RLC filter at the DAC –2 output. It is important for this analog filter to have a sufficiently SINC –3 flat gain and linear phase response across the bandwidth of interest to avoid modulation impairments. An inexpensive –4 0 0.1 0.2 0.3 0.4 0.5 seventh-order elliptical low-pass filter is sufficient to suppress FREQUENCY NORMALIZED TO SAMPLE RATE the aliased components for HFC network applications. Figure 43. Inverse SINC Filter Response The AD9856 provides true and complement current outputs on pins 30 and 29, respectively. The full-scale output current is set DIRECT DIGITAL SYNTHESIZER FUNCTION by the R resistor at Pin 25. The value of R for a particular SET SET The direct digital synthesizer (DDS) block generates the sine/ I is determined by OUT cosine carrier reference signals that are digitally modulated by the I/Q data paths. The DDS function is frequency tuned via R = 39.936/I SET OUT the serial control port with a 32-bit tuning word. This allows the AD9856’s output carrier frequency to be very precisely tuned For example, if a full-scale output current of 20 mA is desired, while still providing output frequency agility. then RSET = (39.936/0.02), or approximately 2 kΩ. Every doubling of the RSET value halves the output current. Maximum The equation relating output frequency of the AD9856 digital output current is specified as 20 mA. modulator to the frequency tuning word (FTWORD) and the system clock (SYSCLK) is given as: The full-scale output current range of the AD9856 is 5 mA to 20 mA. Full-scale output currents outside of this range degrade 32 A =() FTWORD× SYSCLK /2 OUT SFDR performance. SFDR is also slightly affected by output matching, that is, the two outputs should be terminated equally where A and SYSCLK frequencies are in Hz and FTWORD is OUT for best SFDR performance. 31 a decimal number from 0 to 4,294,967,296 (2 ). The output load should be located as close as possible to the For example, find the FTWORD for A = 41 MHz and OUT AD9856 package to minimize stray capacitance and inductance. SYSCLK = 122.88 MHz. The load may be a simple resistor to ground, an op amp current-to-voltage converter, or a transformer-coupled circuit. If AOUT = 41 MHz and SYSCLK = 122.88 MHz, then: It is best not to attempt to directly drive highly reactive loads FTWORD= 556AAAAB hex (such as an LC filter). Driving an LC filter without a transformer requires that the filter be doubly terminated for Loading 556AAAABh into control bus registers 02h–05h best performance, that is, the filter input and output should (for Profile 1) programs the AD9856 for A = 41 MHz, OUT both be resistively terminated with the appropriate values. The given a SYSCLK frequency of 122.88 MHz. parallel combination of the two terminations determines the Rev. C | Page 25 of 36 (dB) 00637-C-043 AD9856 load that the AD9856 sees for signals within the filter pass When the third half-band filter is engaged, the AD9856 latency band. For example, a 50 Ω terminated input/output low-pass is given by 126 N + 37 SYSCLK clock cycles, where N is the CIC filter looks like a 25 Ω load to the AD9856. interpolation rate. If the AD9856 is configured to bypass the third half-band filter, The output compliance voltage of the AD9856 is −0.5 V to the latency is given by 63 N + 37 SYSCLK clock cycles. +1.5 V. Any signal developed at the DAC output should not exceed +1.5 V, otherwise, signal distortion results. Furthermore, These equations should be considered estimates, as observed the signal may extend below ground as much as 0.5 V without latency may be data dependent. The latency was calculated damage or signal distortion. The use of a transformer with a using the linear delay model for the FIR filters. grounded center tap for common-mode rejection results in signals at the AD9856 DAC output pins that are symmetrical In single-tone mode, frequency hopping is accomplished via about ground. changing the PROFILE input pins. The time required to switch from one frequency to another is < 50 SYSCLK cycles with the As previously mentioned, by differentially combining the two inverse SINC filter engaged. With the inverse SINC filter signals the user can provide some degree of common-mode bypassed, the latency drops to < 35 SYSCLK cycles. signal rejection. A differential combiner might consist of a transformer or an op amp. The object is to combine or amplify CONTROL INTERFACE only the difference between two signals and to reject any The flexible AD9856 synchronous serial communications common, usually undesirable, characteristic, such as 60 Hz port allows easy interface to many industry standard micro- hum or clock feedthrough that is equally present on both input controllers and microprocessors. The serial I/O is compatible signals. The AD9856 true and complement outputs can be with most synchronous transfer formats, including the differentially combined using a broadband 1:1 transformer with Motorola 6905/11 SPI® and Intel® 8051 SSR protocols. a grounded, center-tapped primary to perform differential The interface allows read/write access to all registers that combining of the two DAC outputs. configure the AD9856. Single or multiple byte transfers are REFERENCE CLOCK MULTIPLIER supported, as well as MSB first or LSB first transfer formats. Because the AD9856 is a DDS-based modulator, a relatively The AD9856’s serial interface port can be configured as a high frequency system clock is required. For DDS applications, single-pin I/O (SDIO) or two unidirectional pins for the carrier is typically limited to about 40% of SYSCLK. For a input/output (SDIO/SDO). 65 MHz carrier, the system clock required is above 160 MHz. To GENERAL OPERATION OF THE SERIAL INTERFACE avoid the cost associated with these high frequency references and the noise coupling issues associated with operating a high There are two phases to a communication cycle with the frequency clock on a PC board, the AD9856 provides an on- AD9856. Phase 1 is the instruction cycle, which is the writing of an instruction byte into the AD9856, coincident with the first chip programmable clock multiplier (REFCLK multiplier). The eight SCLK rising edges. The instruction byte provides the available clock multiplier range is from 4× to 20×, in integer AD9856 serial port controller with information regarding the steps. With the REFCLK multiplier enabled, the input reference data transfer cycle, which is Phase 2 of the communication clock required for the AD9856 can be kept in the 10 MHz to cycle. The Phase 1 instruction byte defines whether the 50 MHz range for 200 MHz system operation, which results in upcoming data transfer is read or write, the number of bytes in cost and system implementation savings. The REFCLK mult- iplier function maintains clock integrity as evidenced by the the data transfer (1 to 4), and the starting register address for the first byte of the data transfer. AD9856’s system phase noise characteristics of −105 dBc/Hz (AOUT = 40 MHz, REFCLK multiplier = 6, Offset = 1 kHz) and The first eight SCLK rising edges of each communication cycle virtually no clock related spurii in the output spectrum. are used to write the instruction byte into the AD9856. The External loop filter components consisting of a series resistor remaining SCLK edges are for Phase 2 of the communication (1.3 kΩ) and capacitor (0.01 µF) provide the compensation zero cycle. Phase 2 is the actual data transfer between the AD9856 for the REFCLK multiplier PLL loop. The overall loop perform- and the system controller. Phase 2 of the communication cycle ance has been optimized for these component values. is a transfer of 1, 2, 3, or 4 data bytes as determined by the instruction byte. Normally, using one communication cycle in a THROUGHPUT AND LATENCY multibyte transfer is the preferred method. However, single-byte Data latency through the AD9856 is easiest to describe in terms communication cycles are useful to reduce CPU overhead when of SYSCLK clock cycles. Latency is a function of the AD9856 register access requires one byte only. Examples of this may be configuration primarily affected by the CIC interpolation rate to write the AD9856 SLEEP bit, or an AD8320/AD8321 gain and whether the third half-band filter is engaged. control byte. Rev. C | Page 26 of 36 AD9856 At the completion of any communication cycle, the AD9856 R/ —Bit 7 determines whether a read or write data transfer W serial port controller expects the next eight rising SCLK edges occurs after the instruction byte write. Logic high indicates a to be the instruction byte of the next communication cycle. read operation. Logic zero indicates a write operation. All data input to the AD9856 is registered on the rising edge N1, N0—Bits 6 and 5 of the instruction byte determine the of SCLK. All data is driven out of the AD9856 on the falling number of bytes to be transferred during the data transfer cycle edge of SCLK. Figure 44 through Figure 47 show the general of the communications cycle. Table 8 shows the decode bits. operation of the AD9856 serial port. Table 8. N1, N0 Decode Bits N1 N0 Description INSTRUCTION BYTE 0 0 Transfer 1 byte The instruction byte contains the following information as 0 1 Transfer 2 bytes shown in Table 7. 1 0 Transfer 3 bytes Table 7. Instruction Byte Information 1 1 Transfer 4 bytes MSB D6 D5 D4 D3 D2 D1 LSB A4, A3, A2, A1, A0—Bits 4, 3, 2, 1, 0 of the instruction byte R/W N1 N0 A4 A3 A2 A1 A0 determine which register is accessed during the data transfer portion of the communications cycle. For multibyte transfers, this address is the starting byte address. The remaining register addresses are generated by the AD9856. INSTRUCTION CYCLE DATA TRANSFER CYCLE CS SCLK I I I I I I I I D D D D D D D D SDIO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Figure 44. Serial Port Writing Timing—Clock Stall Low INSTRUCTION CYCLE DATA TRANSFER CYCLE CS SCLK SDIO I I I I I I I I DON'T CARE 7 6 5 4 3 2 1 0 D D D D D D D D SDO O7 O6 O5 O4 O3 O2 O1 O0 Figure 45. Three-Wire Serial Port Read Timing—Clock Stall Low INSTRUCTION CYCLE DATA TRANSFER CYCLE CS SCLK SDIO I I I I I I I I D D D D D D D D 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Figure 46. Serial Port Write Timing—Clock Stall High INSTRUCTION CYCLE DATA TRANSFER CYCLE CS SCLK I I I I I I I I D D D D D D D D SDIO 7 6 5 4 3 2 1 0 O7 O6 O5 O4 O3 O2 O1 O0 Figure 47. Two-Wire Serial Port Read Timing—Clock Stall High Rev. C | Page 27 of 36 00637-C-046 00637-C-045 00637-C-044 00637-C-047 AD9856 SERIAL INTERFACE PORT PIN DESCRIPTIONS REG0<6> is set active high, the AD9856 serial port is in LSB SCLK—Serial Clock first format. The instruction byte must be written in the format The serial clock pin is used to synchronize data to and from the indicated by REG0<6>. That is, if the AD9856 is in LSB-first AD9856 and to run the internal state machines. SCLK mode, the instruction byte must be written from least maximum frequency is 10 MHz. significant bit to most significant bit. Multibyte data transfers in MSB format can be completed by writing an instruction byte CS—Chip Select that includes the register address of the most significant byte. In Active low input that allows more than one device on the same MSB-first mode, the serial port internal byte address generator serial communications lines. The SDO and SDIO pins go to a decrements for each byte required of the multibyte commun- high impedance state when this input is high. If driven high ication cycle. Multibyte data transfers in LSB-first format can be during any communications cycle, that cycle is suspended until completed by writing an instruction byte that includes the CS is reactivated low. Chip Select can be tied low in systems that register address of the least significant byte. In LSB-first mode, maintain control of SCLK. the serial port internal byte address generator increments for SDIO—Serial Data I/O each byte required of the multibyte communication cycle. Data is always written into the AD9856 on this pin. However, this pin can be used as a bidirectional data line. The config- NOTES ON SERIAL PORT OPERATION uration of this pin is controlled by Bit 7 of register address 0h. The AD9856 serial port configuration bits reside in Bit 6 and The default is Logic 0, which configures the SDIO pin as Bit 7 of register address 0h. It is important to note that the bidirectional. configuration changes immediately upon writing to this SDO—Serial Data Out register. For multibyte transfers, writing to this register may Data is read from this pin for protocols that use separate lines occur during the middle of a communication cycle. Care must for transmitting and receiving data. In the case where the be taken to compensate for this new configuration for the AD9856 operates in a single bidirectional I/O mode, this pin remainder of the current communication cycle. does not output data and is set to a high impedance state. The AD9856 serial port controller address can roll from 19h to SYNC I/O 0h for multibyte I/O operations if the MSB-first mode is active. Synchronizes the I/O port state machines without affecting the The serial port controller address can roll from 0h to 19h for addressable registers contents. An active high input on the multibyte I/O operations if the LSB-first mode is active. SYNC I/O pin causes the current communication cycle to abort. After SYNC I/O returns low (Logic 0), another communication The system must maintain synchronization with the AD9856 cycle may begin, starting with the instruction byte write. or the internal control logic is not able to recognize further instructions. For example, if the system sends an instruction CA CLK byte for a 2-byte write, then pulses the SCLK pin for a 3-byte Output clock pin to the AD8320/AD8321. If using the AD9856 write (24 additional SCLK rising edges), communication to control the AD8320/AD8321 programmable cable driver synchronization is lost. In this case, the first 16 SCLK rising amplifier, connect this pin to the CLK input of the AD8320/ edges after the instruction cycle properly write the first two data AD8321. bytes into the AD9856, but the next eight rising SCLK edges are CA DATA interpreted as the next instruction byte, not the final byte of the Output data pin to the AD8320/AD8321. If using the AD9856 previous communication cycle. to control the AD8320/AD8321 programmable cable driver amplifier, connect this pin to the SDATA input of the AD8320/ In the case where synchronization is lost between the system AD8321. and the AD9856, the SYNC I/O pin provides a means to CA ENABLE reestablish synchronization without reinitializing the entire Output Enable pin to the AD8320/AD8321. If using the chip. The SYNC I/O pin enables the user to reset the AD9856 AD9856 to control the AD8320/AD8321 programmable cable state machine to accept the next eight SCLK rising edges to be driver amplifier, connect this pin to the DATEN input of the coincident with the instruction phase of a new communication AD8320/AD8321. cycle. By applying and removing a high signal to the SYNC I/O pin, the AD9856 is set to once again begin performing the MSB/LSB TRANSFERS communication cycle in synchronization with the system. Any The AD9856 serial port can support both MSB-first or LSB-first information that had been written to the AD9856 registers data formats. This functionality is controlled by the REG0<6> during a valid communication cycle prior to loss of synchronization remains intact. bit. The default value of REG0<6> is low (MSB first). When Rev. C | Page 28 of 36 AD9856 t t PRE SCLK CS t DSU t t SCLKPWH SCLKPWL SCLK t DHLD SDIO 1ST BIT 2ND BIT SYMBOL DEFINITION MIN t CS SETUP TIME 30ns PRE t PERIOD OF SERIAL DATA CLOCK 100ns SCLK t SERIAL DATA SETUP TIME 30ns DSU t SERIAL DATA CLOCK PULSEWIDTH HIGH 40ns SCLKPWH t SERIAL DATA CLOCK PULSEWIDTH LOW 40ns SCLKPWL t SERIAL DATA HOLD TIME 0ns DHLD Figure 48. Timing Diagram for Data Write to AD9856 CS SCLK SDIO 1ST BIT 2ND BIT SDO t DV SYMBOL DEFINITION MAX t DATA VALID TIME 30ns DV Figure 49. Timing Diagram for Read from AD9856 Rev. C | Page 29 of 36 00637-C-049 00637-C-048 AD9856 Change in Profile Selection Bits (PS1, PS0) PROGRAMMING/WRITING THE AD8320/AD8321 The AD9856 samples the PS1, PS0 input pins and writes to the CABLE DRIVER AMPLIFIER GAIN CONTROL AD8320/ AD8321 gain control register when a change in profile Programming the gain control register of the AD8320/AD8321 is determined. The data written to the AD8320/AD8321 comes programmable cable driver amplifier can be accomplished via from the AD9856 gain control register associated with the the AD9856 serial port. Four 8-bit registers (one per profile) current profile. within the AD9856 store the gain value to be written to the Serial Port Write of AD9856 Registers Containing AD8320/AD8321. The AD8320/AD8321 is written via three AD8320/AD8321 Data dedicated AD9856 output pins that are directly connected The AD9856 writes to the AD8320/AD8321 with data from the to the AD8320/AD8321 serial input port. The transfer of gain control register associated with the current profile data from the AD9856 to the AD8320/AD8321 requires whenever any AD9856 gain control register is updated. The 136 SYSCLK clock cycles and occurs upon detection of three user does not have to write the AD9856 in any particular order conditions. Each condition is described next. or to be concerned with time between writes. If the AD9856 is Power-Up Reset currently writing to the AD8320/AD8321 while one of the four Upon initial power up, the AD9856 clears (Logic 0) the contents AD9856 gain control registers is being addressed, the AD9856 of control registers 07h, 0Dh, 13h, and 19h, which defines the immediately terminates the AD8320/AD8321 write sequence lowest gain setting of the AD8320/AD8321. Thus, the AD9856 (without updating the AD8320/AD8321) and begins a new writes all 0s out of the AD8320/AD8321 serial interface. AD8320/AD8321 write sequence. VALID DATA WORD G1 VALID DATA WORD G2 CA DATA MSB...LSB t t DS CK t WH CA CLK t t ES EH 8 CLOCK CYCLES GAIN TRANSFER G2 CA ENABLE GAIN TRANSFER G1 SYMBOL DEFINITION MIN t CA DATA SETUP TIME 6.5ns DS t CA DATA HOLD TIME 2ns DH t CA CLOCK PULSE HIGH 9ns WH t CA CLOCK PERIOD 25ns CK t CA ENABLE SETUP TIME 17ns ES t CA ENABLE HOLD TIME 2.0ns EH Figure 50. Programmable Cable Driver Amplifier Output Control Interface Timing Rev. C | Page 30 of 36 00637-C-050 AD9856 AD8320/AD8321 Gain Control UNDERSTANDING AND USING PIN-SELECTABLE MODULATOR PROFILES An 8-bit word that controls the gain of an AD8320/AD8321 programmable gain amplifier connected to the AD9856 with The AD9856 quadrature digital upconverter is capable of the 3-bit SPI interface bus. Gain range is from −10 dB (00 hex) storing four preconfigured modulation modes called profiles to +26 dB (FFhex). The gain is linear in V/V/LSB and follows that define the following: the equation A = 0.316 + 0.077 × Code, where Code is the V • Output frequency—32 bits decimal equivalent of the 8-bit gain word. • Interpolation rate—6 bits Profile Selection • Spectral inversion status—1 bit After profiles have been loaded into the appropriate registers, • Bypass third half-band filter—1 bit the user may select which profile to use with two input pins: • Gain control of AD8320/AD8321—8 bits PS0 and PS1, Pins 45 and 46. Table 9 shows how profiles are Output Frequency selected. This attribute consists of four 8-bit words loaded into four Table 9. Profile Select Matrix register addresses to form a 32-bit frequency tuning word PS1 PS0 PROFILE (FTW) for each profile. The lowest register address corresponds 0 0 1 to the least significant 8-bit word. Ascending addresses 0 1 2 correspond to increasingly significant 8-bit words. The output 1 0 3 32 frequency equation is given as: fOUT = (FTW × SYSCLK)/2 . 1 1 4 Interpolation Rate Except while in single-tone mode, it is recommended that users Consists of a 6-bit word representing the allowed interpolation suspend the TxENABLE function by bringing the pin to Logic 0 values from 2 to 63. Interpolation is the mechanism used to up prior to changing from one profile to another and then re- sample or multiply the input data rate such that it exactly asserting TxENABLE. This assures that any discontinuities matches that of the DDS sample rate (SYSCLK). This implies resulting from register data transfer are not transmitted up or that the system clock must be an exact multiple of the symbol downstream. Furthermore, changing interpolation rates during rate. This 6-bit word represents the 6 MSBs of the eight bits a burst may create an unrecoverable digital overflow condition allocated for that address. The remaining two bits contain the that interrupts transmission of the current burst until a RESET spectral inversion status bit and half-band bypass bit. and reloading procedure is completed. Spectral Inversion Single bit that when at Logic 0 the default or noninverted POWER DISSIPATION CONSIDERATIONS output from the adder is sent to the following stages. A Logic 1 The majority of the AD9856 power dissipation comes from causes the inverted output to be sent to the following stages. digital switching currents. As such, power dissipation is highly The noninverted output is described as dependent upon chip configuration. I × Cos(ωt) − Q × Sin(ωt). The inverted output is described as The major contributor to switching current is the maximum I × Cos(ωt) + Q × Sin(ωt). clock rate at which the device is operated, but other factors can This bit is located adjacent to the LSB at the same address as the play a significant role. Factors such as the CIC interpolation interpolation rate previously described. rate, and whether the third half-band filter and inverse SINC filters are active, can affect the power dissipation of the device. Bypass Third Half-Band Filter A single bit located in the LSB position of the same address as It is important for the user to consider all of these factors when the interpolation rate. When this bit is Logic 0, the third half- optimizing performance for power dissipation. For example, band filter is engaged and its inherent 2× interpolation rate is there are two ways to achieve a 6 MS/s transmission rate with applied. When this bit is Logic 1, the third half-band filter is the AD9856. The first method uses an f of 192 MHz; the MAX bypassed and the 2× interpolation rate is negated. This allows other method uses an f of 144 MHz, which reduces power MAX users to input higher data rates—rates that may be too high for dissipation by nearly 25%. the minimum interpolation rate if all three half-band filters with their inherent 2× interpolation rate are engaged. The effect For the first method, the input data must be externally 4× is to reduce the minimum interpolation rate from 8× to 4×. upsampled. The AD9856 must be configured for a CIC interpolation rate of three while bypassing the 3rd half-band filter. This results in an I/Q input sample rate of 24 MHz which is further upsampled by a factor of 8 MHz to 192 MHz. Rev. C | Page 31 of 36 AD9856 The second method requires an f of 144 MHz with is 1.5 W. This permits operation over the industrial temperature MAX externally 2× upsampled input data. The AD9856 is configured range without exceeding the maximum junction temperature of for a CIC interpolation rate of 3 while bypassing the 3rd half- 150°C. To realize this quoted thermal impedance, all power and band filter. The input I/Q sample rate is 12 MHz, which is ground pins must be soldered down to a multilayer PCB with further upsampled by a factor of 12 MHz to 144 MHz. power and ground copper planes directly available at the package pins. For burst applications with relatively long nonbursting periods, the sleep bit is useful for saving power. When in sleep mode, Under worst-case conditions, that is, with power supplies at power is reduced to below 6 mW. Consideration must be given 2.85 V and ambient temperatures of 85°C, device operation to wake-up time, which generally is in the 400 µs to 750 µs at 200 MHz is guaranteed for single-tone mode only. For range. For applications that cannot use the sleep bit due to this modulation mode at 200 MHz, 85°C operation, the minimum wake-up time, there is an alternate method of reducing power power supply voltage is 3.0 V. dissipation when not transmitting. By writing the bypass AD9856 EVALUATION BOARD REFCLK multiplier bit active, the power is reduced by nearly An evaluation board is available to facilitate bench and system the REFCLK multiplier factor. For example, if the external analysis of AD9856 quadrature digital upconverter. The reference clock is 16 MHz and REFCLK multiplier is set to 10×, AD9856 printed circuit board (PCB) contains the AD9856 all clocks divide down by a factor of 10 when the REFCLK multiplier is bypassed. This effectively scales down the power device and Windows® software that the device to be controlled dissipation by nearly a factor of 10. In this case, both the via the printer port of a PC. The DAC output is provided on a jack for spectral analysis. The AD9856/PCB provides a single- REFCLK multiplier function and the DAC, which use relatively ended 65 MHz, 5 Ω, elliptical low-pass filter on the output of little power, remain fully powered. The REFCLK multiplier the DAC. circuit is locked to the 16 MHz external reference clock, but its output is driving a very small load—thus, there is little power The user can also implement the AD8320/AD8321 program- dissipation. When the REFCLK multiplier is reactivated, the mable cable driver amplifier on the AD9856/PCB evaluation acquisition time is small. In this power reduction technique, board. The AD8320/AD8321 gain is programmed through the the larger the REFCLK multiplier factor, the larger the power AD9856 via the menu driven control software. savings. SUPPORT The AD9856 is specified for operation at +3.0 V ±5%. The Applications assistance is available for the AD9856 and the thermal impedance of the device in the 48-LQFP plastic AD9856/PCB evaluation board. Please call 1-800-ANALOGD package is 38°C/W. At 200 MHz operation, power dissipation or visit www.analog.com. Rev. C | Page 32 of 36 AD9856 J6 PS0 SYNC I/O P3 J8 J7 SCLK J4 DVDD 1 PS1 SDIO E25 J15 J5 2 W10 GND SDO J14 REFCLKIN E26 W1 R7 E3 3 AVDD E2 CS 50Ω J3 E1 W6 GND E5 4 RST E8 +3.3V RESET CACLK 48 47 46 45 44 43 42 41 40 39 38 37 W5 E6 E4 5 +12V J2 CADAT TxENABLE W4 E7 E9 CAENB P1 1 36 W9 TxENABLE CA DATA E10 E11 AVDD 1 2 35 C15 D11 CA ENABLE C16 2 R5 3 34 0.1µ F D10 PLL SUPPLY 0.01µ F 1.3kΩ 4 33 C17 C18 C19 DVDD DVDD PLL FILTER J10 7pF 33pF 5 32 22pF W8 GND GND DGND PLL GND E12 E13 3 6 31 DUT D9 AGND 65MHz 4 J9 7 30 R3 AD9856 R4 L1 L2 L3 D8 I OUT LOW PASS 25Ω 5 8 29 50Ω 120nH 100nH 100nH D7 I FILTER OUTB 6 9 28 D6 AGND 10 27 C10 C11 C12 C13 DVDD DVDD AVDD W7 68pF 100pF 82pF 56pF 11 26 E14 E15 GND DGND DAC REF BYPASS 7 12 25 D5 DAC R SET R1 C9 AVDD 3.92Ω +3.3V 0.1µ F W11 R6 E20 GND J11 E21 1.3kΩ E22 PODN 8 13 14 15 16 17 18 19 20 21 22 23 24 POWER NC = NO CONNECT DOWN 9 U4 CONTROL 10 AD8320/21 C7 1 20 0.1µ F +12V 11 CADATA SDATA VCC1 J1 13 THRU 2 19 12 CACLK CLK VIN 20 ARE NC AVDD 3 18 C26 J13 DATEN VREF CAEN 21 THRU 0.1µ F 4 17 20 +3.3V GND VCC 40 ARE GND 0.1µ F 5 16 50Ω VOCM GND 1 74HC132 6 15 R9 INPUT C21 R11 R10 PD GND 2 62Ω 7 14 U8 0.1µ F 10kΩ 10kΩ P2 +12V +12V BYP 1 14 +3.3V 1A DVDD 8 13 C28 LATCH +12V GND 3 1 2 13 0.1µ F 4B 9 12 1B 75Ω J12 SCLK +12V GND 4 2 3 12 4A OUTPUT 10 11 1Y SDIO VOUT GND 5 3 4 11 4Y 2A RBE C23 4 CS 5 10 3B 2B 0.1µ F 5 6 9 3A 2Y 6 7 8 3Y DGND RBE 7 RST 8 SYNC I/O 9 10 +3.3V 11 12 U7 13 R8 74HC574 U6 10kΩ 14 1 20 +3.3V 74HC244A OE V CC 15 17 2 19 20 D0 Q0 2A4 V CC 16 15 3 18 3 D1 Q1 2A3 2Y4 SCLK 17 13 4 17 5 D2 Q2 2A2 2Y3 CS 18 11 5 16 7 D3 Q3 2A1 2Y2 SYNC I/O 19 8 6 15 9 D4 Q4 1A4 2Y1 RST 20 6 7 14 12 D5 Q5 1A3 1Y4 21 4 8 13 14 D6 Q6 1A2 1Y3 PS0 22 2 9 12 16 D7 Q7 1A1 1Y2 PS1 23 10 10 11 18 GND CLOCK GND 1Y1 24 1G 2G 25 1 19 W3 26 W2 E23 E18 +3.3V U3 +3.3V E16 E17 27 1 14 E24 E19 RBE V +3.3V 1G CC GND GND 28 2 13 4G RBE 1A 29 3 12 RBE 4A 1Y 30 4 11 4Y SDIO GND RBE 2G 31 5 10 SDO 3G 2A 32 SDO 6 9 3A +3.3V 2Y 33 7 8 DVDD GND +3.3V +12V 3Y GND 34 AVDD 74HC125A 35 C3 C29 C24 C30 C31 C4 C27 C22 C25 C14 C8 C5 C20 C1 C2 36 10µ F 0.1µ F 0.1µ F 0.1µ F 0.1µ F 10µ F 0.1µ F 0.1µ F 0.1µ F 0.1µ F 0.1µ F 0.1µ F 0.1µ F 10µ F 10µ F GND Figure 51. AD9856/PCB Evaluation Board Electrical Schematic Rev. C | Page 33 of 36 D4 RESET D3 REFCLK D2 PS1 D1 PS0 D0 DVDD DVDD NC DGND GND NC SYNC I/O DGND SCLK DVDD DVDD SDIO NC SDO AGND CS BG REF CA CLK BYPASS 00637-C-051 AD9856 Figure 52. PCB Lay Out Pattern for Four-Layer AD9856 PCB Evaluation Board Figure 54. PCB Lay Out Pattern for Four-Layer AD9856 PCB Evaluation Board Layer 1 (Top)—Signal Routing and Ground Plane Layer 3—DUT +V, +5 V and 12 V Power Plane Figure 53. PCB Lay Out Pattern for Four-Layer AD9856 PCB Evaluation Board Figure 55. PCB Lay Out Pattern for Four-Layer AD9856 PCB Evaluation Board Layer 2—Ground Plane Layer 4 (Bottom)—Signal Routing ENABLE AND GAIN CONTROL BUS DATA IN AD9856 AD8320/21 UPSTREAM 75Ω PROGRAMMABLE QUADRATURE DIGITAL LP FILTER CABLE DRIVER UPCONVERTER 75Ω 75Ω AMPLIFIER TO 8-20MHz 75Ω REF CLOCK IN CABLE PLANT TO DOWNSTREAM DEMODULATOR DIRECT CONTROL CONTROL LINES BUS CIU CONTROL PROCESSOR Figure 56. Basic Implementation of AD9856 Digital Modulator and AD8320/AD8321 Programmable Cable Driver Amplifier in 5 MHz to 65 MHz HFC Return-Path Application V DD V V DD DD DIGITAL DIGITAL OUT IN I I B OUT OUT Figure 57. Equivalent I/O Circuits Rev. C | Page 34 of 36 00637-C-052 00637-C-053 DIPLEXER 00637-C-057 00637-C-056 00637-C-055 00637-C-054 A D 9 8 56 R E V . C M A DE I N U . S . A . BO T T O M S I D E AD9856 OUTLINE DIMENSIONS 0.75 9.00 BSC 1.60 0.60 SQ MAX 0.45 37 48 36 1 PIN 1 SEATING PLANE 10° TOP VIEW 7.00 1.45 6° (PINS DOWN) BSC SQ 0.20 1.40 2° 0.09 1.35 VIEW A 7° ° 12 25 3.5 13 24 0° 0.15 SEATING 0.05 0.08 MAX 0.27 0.50 PLANE COPLANARITY 0.22 BSC VIEW A 0.17 ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026BBC Figure 58. 48-Lead Low Profile Quad Flat Package [LQFP] (ST-48) Dimensions shown in inches millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option AD9856AST −40° C to +85° C 48-Lead Low Profile Quad Flat Package [LQFP] ST-48 AD9856/PCB Evaluation Board Rev. C | Page 35 of 36 AD9856 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C00637–0–1/05(C) Rev. C | Page 36 of 36