ANALOG DEVICES AD9789

14-Bit, 2400 MSPS RF DAC with 4-Channel Signal Processing AD9789 The on-chip rate converter supports a wide range of baud rates FEATURES with a fixed DAC clock. The digital upconverter can place the DOCSIS 3.0 performance: 4 QAM carriers channels from 0 to 0.5 × fDAC. This permits four contiguous ACLR over full band (47 MHz to 1 GHz) channels to be synthesized and placed anywhere from dc to f /2. DAC −75 dBc @ f = 200 MHz OUT −72 dBc @ f = 800 MHz (noise) The AD9789 includes a serial peripheral interface (SPI) for OUT −67 dBc @ f = 800 MHz (harmonics) device configuration and status register readback. The flexible OUT Unequalized MER = 42 dB digital interface can be configured for data bus widths of 4, 8, On chip and bypassable 16, and 32 bits. It can accept real or complex data. 4 QAM encoders with SRRC filters, 16× to 512× interpolation, The AD9789 operates from 1.5 V, 1.8 V, and 3.3 V supplies for rate converters, and modulators a total power consumption of 1.6 W. It is supplied in a 164-ball Flexible data interface: 4, 8, 16, or 32 bits wide with parity chip scale package ball grid array for lower thermal impedance Power: 1.6 W (I = 20 mA, f = 2.4 GHz, LVDS interface) FS DAC and reduced package parasitics. No special power sequencing Direct to RF synthesis support with f mix mode S is required. The clock receiver powers up muted to prevent Built-in self-test (BIST) support start-up noise. Input connectivity check PRODUCT HIGHLIGHTS Internal random number generator 1. Highly integrated and configurable QAM mappers, inter- APPLICATIONS polators, and upconverters for direct synthesis of one to Broadband communications systems four DOCSIS- or DVB-C-compatible channels in a block. CMTS/DVB 2. Low noise and intermodulation distortion (IMD) perfor- Cellular infrastructure mance enable high quality synthesis of signals up to 1 GHz. Point-to-point wireless 3. Flexible data interface supports LVDS for improved SFDR or CMOS input data for less demanding applications. GENERAL DESCRIPTION 4. Interface is configurable from 4-bit nibbles to 32-bit words The AD9789 is a flexible QAM encoder/interpolator/upconverter and can run at up to 150 MHz CMOS or 150 MHz LVDS combined with a high performance, 2400 MSPS, 14-bit RF digital- double data rate (DDR). to-analog converter (DAC). The flexible digital interface can 5. Manufactured on a CMOS process, the AD9789 uses a accept up to four channels of complex data. The QAM encoder proprietary switching technique that enhances dynamic supports constellation sizes of 16, 32, 64, 128, and 256 with performance. SRRC filter coefficients for all standards. FUNCTIONAL BLOCK DIAGRAM QAM/ CMOS FILTER/ DATA 0TO 15 NCO LVDS 32 INPUT RISE PINS QAM/ AND DATA FILTER/ 2PARITY RETIMER NCO 16× 150MHz PINS 14-BIT DATA FORMATTER/ INTERPOLATOR LVDS/CMOS ASSEMBLER 2.4GSPS AND BPF DAC CMOS QAM/ + SCALARS DATA 16 TO 31 FILTER/ LVDS NCO FALL DCO SPI QAM/ IRQ RS DATA FILTER/ FS NCO Figure 1. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2009-2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 07852-001 AD9789 TABLE OF CONTENTS Features .............................................................................................. 1  SPI Register Descriptions.......................................................... 29  Applications....................................................................................... 1  Theory of Operation ...................................................................... 39  General Description ......................................................................... 1  Datapath Signal Processing....................................................... 39  Product Highlights ........................................................................... 1  Digital Block Upconverter ........................................................ 43  Functional Block Diagram .............................................................. 1  Digital Interface Modes ............................................................. 45  Revision History ............................................................................... 2  Analog Modes of Operation ..................................................... 54  Detailed Functional Block Diagrams............................................. 3  Analog Control Registers .......................................................... 55  Specifications..................................................................................... 4  Voltage Reference ....................................................................... 56  DC Specifications ......................................................................... 4  DAC Output Stages .................................................................... 56  Digital Specifications ................................................................... 5  Clocking the AD9789 ................................................................ 57  AC Specifications.......................................................................... 6  Mu Delay Controller.................................................................. 58  Absolute Maximum Ratings............................................................ 8  Interrupt Requests...................................................................... 61  Thermal Resistance ...................................................................... 8  Recommended Start-Up Sequence .......................................... 62  ESD Caution.................................................................................. 8  Customer BIST Modes................................................................... 63  Pin Configurations and Function Descriptions ........................... 9  Using the Internal PRN Generator to Test QAM Output AC Performance................................................................................ 63  Typical Performance Characteristics ........................................... 12  Using the Internal Built-In Self-Test (BIST) to Test for Digital Terminology .................................................................................... 22  Data Input Connectivity............................................................. 63  Serial Control Port.......................................................................... 23  QAM Constellation Maps ............................................................. 65  Serial Control Port Pin Descriptions ....................................... 23  Channelizer Mode Pin Mapping for CMOS and LVDS............ 68  General Operation of Serial Control Port............................... 23  Outline Dimensions....................................................................... 74  Instruction Word (16 Bits) ........................................................ 24  Ordering Guide .......................................................................... 74  MSB/LSB First Transfers............................................................ 24  SPI Register Map............................................................................. 27  REVISION HISTORY 7/11—Rev. 0 to Rev. A Changes to Table 2, DAC Clock Input (CLKP, CLKN): Added DAC Clock Rate Parameter............................................................. 5 Changes to Table 3, Dynamic Performance, DAC Update Rate Parameter; Added Adjusted DAC Update Rate Parameter......... 6 Changes to Captions for Figure 42, Figure 44, Figure 46, Figure 49 .......................................................................................... 18 Changes to Digital 16x Tunable Band-Pass Filter Section, Third Paragraph......................................................................................... 44 Changes to Retimer and Latency Look-Up Tables Section, Second Paragraph ........................................................................... 50 Changes to Captions for Figure 122, Figure 124, Figure 125.... 65 4/09—Revision 0: Initial Version Rev. A | Page 2 of 76 AD9789 DETAILED FUNCTIONAL BLOCK DIAGRAMS DATA- UP TO CMOS PATH 32 BITS 0TO 15 0 LVDS RISE DATA- 32 INPUT 4TO UP TO RETIMER PATH PINS 32 BITS 32 BITS DATA FORMATTER/ 1 BPF LVDS/CMOS 16× ASSEMBLER f = 0 TO INTERPOLATOR C CMOS 16 TO 31 f /2 DAC DATA- UP TO LVDS 32 BITS PATH FALL 2 SUM SCALE P0 BPF P1 DATA- UP TO f C 32 BITS PATH FS CLK DCO 3 CTL Figure 2. Digital Signal Processing Functional Block Diagram 24-BIT NCO 0TO f /16 QAM DAC MAPPER SRRC RATE 2 CONVERTER N 2 P/Q 24-BIT (N = 0 TO 5) (P/Q = 0.5 TO 1) INPUT BYPASS CH GAIN SCALE QAM 0× TO 2× BYPASS SRRC Figure 3. Channel 0 Through Channel 3 Datapath Block Detail (I and Q Paths Are Identical So Only One Is Shown) Rev. A | Page 3 of 76 07852-003 07852-002 AD9789 SPECIFICATIONS DC SPECIFICATIONS AVDD33 = DVDD33 = 3.3 V, CVDD18 = DVDD18 = 1.8 V, DVDD15 = 1.5 V, f = 2.4 GHz, I = 20 mA, unless otherwise noted. DAC FS Table 1. Parameter Min Typ Max Unit DAC RESOLUTION 14 Bits ANALOG OUTPUTS Offset Error 6.5 % FSR Gain Error (with Internal Reference) 3.5 % FSR Full-Scale Output Current (Monotonicity Guaranteed) 8.66 20.2 31.66 mA Output Compliance Range −1.0 +1.0 V Output Resistance 70 Ω Output Capacitance 1 pF TEMPERATURE DRIFT Gain 135 ppm/°C Reference Voltage 25 ppm/°C REFERENCE Internal Reference Voltage 1.2 V 1 Output Resistance 5 kΩ ANALOG SUPPLY VOLTAGES AVDD33 3.14 3.3 3.47 V CVDD18 1.71 1.8 1.89 V DIGITAL SUPPLY VOLTAGES DVDD33 3.14 3.3 3.47 V DVDD18 1.71 1.8 1.89 V DVDD15 1.43 1.5 1.58 V SUPPLY CURRENTS AND POWER DISSIPATION fDAC = 2.4 GSPS, fOUT = 930 MHz, IFS = 25 mA, Four Channels Enabled IAVDD33 45 mA I 72 mA DVDD18 I 180 mA CVDD18 IDVDD33 CMOS Interface 42 mA LVDS Interface 16 mA I 640 mA DVDD15 f = 2.0 GSPS, f = 70 MHz, I = 20 mA, CMOS Interface DAC OUT FS I 37.4 38.5 mA AVDD33 IDVDD18 67.3 70.5 mA ICVDD18 155.4 180 mA IDVDD33 40.3 50.7 mA I (Four Channels Enabled, All Signal Processing Enabled) 517 556 mA DVDD15 I (One Channel Enabled, 16× Interpolation Only) 365 391 mA DVDD15 Power Dissipation fDAC = 2.4 GSPS, fOUT = 930 MHz, IFS = 25 mA, Four Channels Enabled CMOS Interface 1.7 W LVDS Interface 1.63 W 1 Use an external amplifier to drive any external load. Rev. A | Page 4 of 76 AD9789 DIGITAL SPECIFICATIONS AVDD33 = DVDD33 = 3.3 V, CVDD18 = DVDD18 = 1.8 V, DVDD15 = 1.5 V, fDAC = 2.4 GHz, IFS = 20 mA, LVDS drivers and receivers are compliant with the IEEE Std 1596.3-1996 reduced range link, unless otherwise noted. Table 2. Parameter Min Typ Max Unit CMOS DATA INPUTS (D[31:0], P0, P1) Input Voltage High, VIH 2.0 3.3 V Input Voltage Low, VIL 0 0.8 V Input Current High, I −10 +10 μA IH Input Current Low, I −10 +10 μA IL Input Capacitance 2 pF 1 Setup Time, CMOS Data Input to CMOS_DCO 5.3 ns 1 Hold Time, CMOS Data Input to CMOS_DCO −1.4 ns CMOS OUTPUTS (CMOS_FS, CMOS_DCO) Output Voltage High, VOH 2.4 3.3 V Output Voltage Low, VOL 0 0.4 V Output Current High, I 12 mA OH Output Current Low, I 12 mA OL Maximum Clock Rate (CMOS_DCO) 150 MHz CMOS_DCO to CMOS_FS Delay 0.28 0.85 ns LVDS DATA INPUTS (D[15:0]P, D[15:0]N, PARP, PARN) Input Voltage Range, V or V 825 1575 mV IA IB Input Differential Threshold, VIDTH −100 +100 mV Input Differential Hysteresis, VIDTHH, VIDTHL 25 mV Input Differential Input Impedance, RIN 80 120 Ω Maximum LVDS Input Rate 150 MSPS 2 Setup Time, LVDS Differential Input Data to Differential DCOx 1.41 ns 2 Hold Time, LVDS Differential Input Data to Differential DCOx 0.24 ns LVDS OUTPUTS (DCOP, DCON, FSP, FSN) DCOP, FSP = V ; DCON, FSN = V ; 100 Ω Termination OA OB Output Voltage High, VOA or VOB 1375 mV Output Voltage Low, VOA or VOB 1025 mV Output Differential Voltage, |VOD| 150 200 250 mV Output Offset Voltage, V 1150 1250 mV OS Output Impedance, Single Ended, R 40 140 Ω O R Mismatch Between A and B, ∆R 10 % O O Change in |VOD| Between 0 and 1, |∆VOD| 25 mV Change in VOS Between 0 and 1, ∆VOS 25 mV Output Current—Driver Shorted to Ground, ISA, ISB 20 mA Output Current—Drivers Shorted Together, I 4 mA SAB Power-Off Output Leakage, |I |, |I| 10 mA XA XB Maximum Clock Rate (DCOP, DCON) 150 MHz DCOx to FSx Delay 0.12 0.37 ns 3 DAC CLOCK INPUT (CLKP, CLKN) Differential Peak Voltage 1.4 1.8 V Common-Mode Voltage 900 mV DAC Clock Rate 2400 MHz SERIAL PERIPHERAL INTERFACE Maximum Clock Rate (fSCLK, 1/tSCLK) 25 MHz Minimum Pulse Width High, tPWH 20 ns Minimum Pulse Width Low, t 20 ns PWL Minimum SDIO and CS to SCLK Setup, t 10 ns DS Rev. A | Page 5 of 76 AD9789 Parameter Min Typ Max Unit Minimum SCLK to SDIO Hold, tDH 5 ns Maximum SCLK to Valid SDIO and SDO, tDV 20 ns Minimum SCLK to Invalid SDIO and SDO, tDNV 5 ns INPUTS (SDIO, SCLK, CS) Input Voltage High, VIH 2.0 3.3 V Input Voltage Low, VIL 0 0.8 V Input Current High, I −10 +10 μA IH Input Current Low, I −10 +10 μA IL OUTPUTS (SDO, SDIO) Output Voltage High, V 2.4 3.6 V OH Output Voltage Low, V 0 0.4 V OL Output Current High, IOH 4 mA Output Current Low, IOL 4 mA 1 See the CMOS Interface Timing section for more information. 2 See the LVDS Interface Timing section for more information. 3 See the Clock Phase Noise Effects on AC Performance section for more information. AC SPECIFICATIONS AVDD33 = DVDD33 = 3.3 V, CVDD18 = DVDD18 = 1.8 V, DVDD15 = 1.5 V, f = 2.4 GHz, I = 20 mA, digital scale = 0 dBFS, unless DAC FS otherwise noted. Table 3. Parameter Test Conditions/Comments Min Typ Max Unit DYNAMIC PERFORMANCE DAC Update Rate 2400 MSPS 1 Adjusted DAC Update Rate 150 MSPS Output Settling Time (tST) To 0.025% 13 ns SPURIOUS-FREE DYNAMIC RANGE (SFDR) fDAC = 2000 MSPS fOUT = 100 MHz 70 dBc fOUT = 316 MHz 63 dBc f = 550 MHz 58 dBc OUT f = 2400 MSPS DAC f = 100 MHz 70 dBc OUT fOUT = 316 MHz 70 dBc fOUT = 550 MHz 60 dBc fOUT = 850 MHz 60 dBc TWO-TONE INTERMODULATION DISTORTION fOUT2 = fOUT1 + 1.25 MHz (IMD) f = 2000 MSPS DAC f = 100 MHz 86 dBc OUT f = 316 MHz 73 dBc OUT fOUT = 550 MHz 62 dBc fDAC = 2400 MSPS fOUT = 100 MHz 86 dBc f = 316 MHz 74 dBc OUT f = 550 MHz 66 dBc OUT f = 850 MHz 66 dBc OUT NOISE SPECTRAL DENSITY (NSD) 1-Channel QAM f = 2400 MSPS DAC fOUT = 100 MHz POUT = −14.5 dBm −167 dBm/Hz fOUT = 316 MHz POUT = −15.5 dBm −166.5 dBm/Hz fOUT = 550 MHz POUT = −18 dBm −166.5 dBm/Hz f = 850 MHz P = −18.5 dBm −166.5 dBm/Hz OUT OUT Rev. A | Page 6 of 76 AD9789 Parameter Test Conditions/Comments Min Typ Max Unit ADJACENT CHANNEL LEAKAGE RATIO (ACLR) fDAC = 2293.76 MSPS measured in 6 MHz channels 1-Channel QAM f = 200 MHz (Harmonics) −76 dBc OUT f = 200 MHz (Noise Floor) −82 dBc OUT f = 500 MHz (Harmonics) −74.5 dBc OUT fOUT = 500 MHz (Noise Floor) −78 dBc fOUT = 800 MHz (Harmonics) −69 dBc fOUT = 800 MHz (Noise Floor) −78 dBc 2-Channel QAM f = 200 MHz (Harmonics) −77.5 dBc OUT fOUT = 200 MHz (Noise Floor) −81 dBc fOUT = 500 MHz (Harmonics) −68 dBc fOUT = 500 MHz (Noise Floor) −76 dBc f = 800 MHz (Harmonics) −66 dBc OUT f = 800 MHz (Noise Floor) −76 dBc OUT 4-Channel QAM fOUT = 200 MHz (Harmonics) −75 dBc fOUT = 200 MHz (Noise Floor) −76 dBc fOUT = 500 MHz (Harmonics) −69 dBc f = 500 MHz (Noise Floor) −72 dBc OUT f = 800 MHz (Harmonics) −67 dBc OUT fOUT = 800 MHz (Noise Floor) −72 dBc WCDMA ACLR f = 2304 MSPS, mix mode second DAC Nyquist zone Single Carrier fOUT = 1850 MHz First Adjacent Channel −70 dBc Second Alternate Channel −72.5 dBc Third Alternate Channel −74 dBc Single Carrier f = 2100 MHz OUT First Adjacent Channel −68 dBc Second Alternate Channel −70.4 dBc Third Alternate Channel −72.7 dBc Four Carrier fOUT = 2100 MHz First Adjacent Channel −63.5 dBc Second Alternate Channel −65.1 dBc Third Alternate Channel −66.9 dBc 1 Adjusted DAC update rate is calculated as f divided by the minimum required interpolation factor. For the AD9789, the minimum interpolation factor is 16. Thus, DAC with fDAC = 2400 MSPS, FDACadj = 2400 MSPS/16 = 150 MSPS. Rev. A | Page 7 of 76 AD9789 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 4. Parameter Rating θ is specified for the worst-case conditions, that is, a device JA soldered in a circuit board for surface-mount packages. AVDD33 to AVSS −0.3 V to +3.6 V DVDD18 to DVSS −0.3 V to +1.98 V Table 5. Thermal Resistance DVDD33 to DVSS −0.3 V to +3.6 V Package DVDD15 to DVSS −0.3 V to +1.98 V Type θJA θJB θJC Unit Notes CVDD18 to AVSS −0.3 V to +1.98 V 164-Ball 25.5 14.4 6.8 °C/W 4-layer board, no vias AVSS to DVSS −0.3 V to +0.3 V CSP_BGA 24.4 °C/W 4-layer board, 4 PCB vias CLKP, CLKN to AVSS −0.3 V to CVDD18 + 0.3 V 19.0 °C/W 8-layer board, 4 PCB vias FS, DCO to DVSS −0.3 V to DVDD33 + 0.3 V 17.2 °C/W 8-layer board, 16 PCB vias CMOS and LVDS Data Inputs −0.3 V to DVDD33 + 0.3 V to DVSS IOUTN, IOUTP to AVSS −1.0 V to AVDD33 + 0.3 V ESD CAUTION I120, VREF, IPTAT to AVSS −0.3 V to AVDD33 + 0.3 V IRQ, CS, SCLK, SDO, SDIO, RESET −0.3 V to DVDD33 + 0.3 V to DVSS Junction Temperature 150°C Storage Temperature Range −65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. A | Page 8 of 76 AD9789 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS CVDD18 IOUTN IOUTP AVDD33 11 24 3 5 6 7 89 10 11 12 134 11 24 3 5 6 7 89 10 11 12 134 A A +++ – XX NC B B XX I120 + + C CLKN C N + + XX VREF D CLKP D P + + XX IPTAT E E F F DVDD18 G ++ + + ++ ++ + + G H H J J K XX X X XX X X K CS L SB NC NC L CK NC NC SCLK M M SDO N DO R NC NC N IO I NC NC SDIO P P RESET IRQ X NC + CVDD18 AVDD33 AVSS DVDD18 NO CONNECT DVSS X DVDD33 + DVDD15 Figure 4. Clock and Analog Pins (Top View) Figure 6. Digital Supply and SPI Pins (Top View) 11 24 3 5 6 7 89 10 11 12 134 11 24 3 5 6 7 89 10 11 12 134 A A B B C C D D E E F F G G H H J J PARP FSP K K PARN FSN L P1 31 27 23 19 15 11 7 3 BU L P+ 13 11 9 53 1 FS CMOS_BUS 15 7 P0 P– DCOP M 30 26 22 18 14 10 6 2 CT CMOS_CTRL M 15 13 11 9 7 53 1 FS DCON N 29 25 21 17 13 9 5 1 FS N 14 12 10 8 6 4 2 0 DC CMOS_FS DC DC P 28 24 20 16 12 8 4 0 CMOS_DCO P 14 12 10 8 6 4 2 0 D[31:0] CMOS DATA INPUTS 14 +LVDS 14 –LVDS PARITY AND CONTROL INPUTS Figure 5. CMOS Mode Data Input Pins (Top View) Figure 7. LVDS Mode Data Input Pins (Top View) Rev. A | Page 9 of 76 07852-004 07852-005 07852-006 07852-007 AD9789 Table 6. Pin Function Descriptions Pin No. Mnemonic Description A1, A2, A3, A6, A9, A10, A11, AVSS Analog Supply Ground. B1, B2, B3, B6, B7, B8, B9, B10, B11, C2, C3, C6, C7, C8, C9, C10, C11, D2, D3, D6, D7, D8, D9, D10, D11, E1, E2, E3, E4, E13, E14, F1, F2, F3, F4, F11, F12, F13, F14 A4, A5, B4, B5, C4, C5, D4, D5 CVDD18 1.8 V Clock Supply. A7 IOUTN DAC Negative Output Current. A8 IOUTP DAC Positive Output Current. A12, A13, B12, B13, C12, C13, AVDD33 3.3 V Analog Supply. D12, D13 A14 NC No Connect. Leave floating. B14 I120 Tie this pin to analog ground with a 10 kΩ resistor to generate a 120 μA reference current. C1 CLKN Negative DAC Clock Input (DACCLK). C14 VREF Band Gap Voltage Reference I/O. Decouple to analog ground with a 1 nF capacitor. Output impedance is approximately 5 kΩ. D1 CLKP Positive DAC Clock Input (DACCLK). D14 IPTAT Factory Test Pin. Output current, proportional to absolute temperature, is approximately 10 μA at 25°C with a slope of approximately 20 nA/°C. E11, E12 DVDD18 1.8 V Digital Supply. DVDD15 1.5 V Digital Supply. G1, G2, G3, G4, G7, G8, G11, G12, G13, G14 H1, H2, H3, H4, H7, H8, H11, DVSS Digital Supply Ground. H12, H13, H14, J1, J2, J3, J4, J11, J12, J13, J14 K1, K2, K3, K4, K11, K12, K13, DVDD33 3.3 V Digital Supply. K14 L1 CS Active Low Chip Select for SPI. L2, L3, M2, M3, N3, N4, P3, P4 NC Not Used. Leave unconnected. L4 P1/PARP CMOS/LVDS Parity Bit. L5 D31/D15P CMOS/LVDS Data Input. L6 D27/D13P CMOS/LVDS Data Input. L7 D23/D11P CMOS/LVDS Data Input. L8 D19/D9P CMOS/LVDS Data Input. L9 D15/D7P CMOS/LVDS Data Input. L10 D11/D5P CMOS/LVDS Data Input. L11 D7/D3P CMOS/LVDS Data Input. L12 D3/D1P CMOS/LVDS Data Input. L13 FSP Positive LVDS Frame Sync (FSP) for Data Bus. L14 CMOS_BUS Active High Input. Configures data bus for CMOS inputs. Low input configures data bus to accept LVDS inputs. M1 SCLK Qualifying Clock for SPI. M4 P0/PARN CMOS/LVDS Parity Bit. M5 D30/D15N CMOS/LVDS Data Input. M6 D26/D13N CMOS/LVDS Data Input. M7 D22/D11N CMOS/LVDS Data Input. M8 D18/D9N CMOS/LVDS Data Input. M9 D14/D7N CMOS/LVDS Data Input. M10 D10/D5N CMOS/LVDS Data Input. M11 D6/D3N CMOS/LVDS Data Input. M12 D2/D1N CMOS/LVDS Data Input. M13 FSN Negative LVDS Frame Sync (FSN) for Data Bus. Rev. A | Page 10 of 76 AD9789 Pin No. Mnemonic Description M14 CMOS_CTRL Active High Input. Enables CMOS_DCO and CMOS_FS signals and disables DCOP/DCON and FSP/FSN signals. Low input disables CMOS_DCO and CMOS_FS signals and enables DCOP/DCON and FSP/FSN signals. N1 SDO Serial Data Output for SPI. N2 RESET Active High Input. Resets the AD9789. N5 D29/D14P CMOS/LVDS Data Input. N6 D25/D12P CMOS/LVDS Data Input. N7 D21/D10P CMOS/LVDS Data Input. N8 D17/D8P CMOS/LVDS Data Input. N9 D13/D6P CMOS/LVDS Data Input. N10 D9/D4P CMOS/LVDS Data Input. N11 D5/D2P CMOS/LVDS Data Input. N12 D1/D0P CMOS/LVDS Data Input. N13 DCOP Positive LVDS Data Clock Output (DCOP) for Data Bus. N14 CMOS_FS CMOS Frame Sync for Data Bus. P1 SDIO Serial Data Input/Output for SPI. P2 IRQ Active Low, Open-Drain Interrupt Request Output. Pull up to DVDD33 with a 10 kΩ resistor. P5 D28/D14N CMOS/LVDS Data Input. P6 D24/D12N CMOS/LVDS Data Input. P7 D20/D10N CMOS/LVDS Data Input. P8 D16/D8N CMOS/LVDS Data Input. P9 D12/D6N CMOS/LVDS Data Input. P10 D8/D4N CMOS/LVDS Data Input. P11 D4/D2N CMOS/LVDS Data Input. P12 D0/D0N CMOS/LVDS Data Input. P13 DCON Negative LVDS Data Clock Output (DCON) for Data Bus. P14 CMOS_DCO CMOS Data Clock Output for Data Bus. Rev. A | Page 11 of 76 AD9789 TYPICAL PERFORMANCE CHARACTERISTICS –40 –40 –45 –45 –50 –50 –55 –55 –60 –60 –65 –65 –70 –70 –75 –75 2.4GHz 2.2GHz 0dBFS –80 –80 2GHz –3dBFS 1.6GHz –6dBFS –85 –85 1GHz –12dBFS –90 –90 0 200 400 600 800 1000 1200 0 200 400 600 800 1000 1200 f (MHz) f (MHz) OUT OUT Figure 8. SFDR vs. fOUT over fDAC, Full-Scale Current = 20 mA, Figure 11. SFDR vs. fOUT over Digital Full Scale, fDAC = 2.4 GHz, Digital Scale = 0 dBFS, Temperature = 25°C Full-Scale Current = 20 mA, Temperature = 25°C –40 –40 –45 –45 –50 –50 –55 –55 –60 –60 –65 –65 –70 –70 –75 –75 0dBFS 0dBFS –80 –80 –3dBFS –3dBFS –6dBFS –6dBFS –85 –85 –12dBFS –12dBFS –90 –90 0 200 400 600 800 1000 1200 0 200 400 600 800 1000 1200 f (MHz) f (MHz) OUT OUT Figure 9. Second-Order Harmonic vs. f over Digital Full Scale, Figure 12. Third-Order Harmonic vs. f over Digital Full Scale, OUT OUT f = 2.4 GHz, Full-Scale Current = 20 mA, Temperature = 25°C f = 2.4 GHz, Full-Scale Current = 20 mA, Temperature = 25°C DAC DAC –40 –50 –45 –55 –50 –60 –55 –65 –60 –70 –65 –75 –70 –80 –75 –85 +85°C 32mA –80 –90 +25°C 20mA –40°C 8mA –85 –95 –90 –100 0 200 400 600 800 1000 1200 0 200 400 600 800 1000 1200 f (MHz) f (MHz) OUT OUT Figure 10. SFDR vs. f over Full-Scale Current, f = 2.4 GHz, Figure 13. SFDR vs. f over Temperature, f = 2.4 GHz, OUT DAC OUT DAC Digital Scale = 0 dBFS, Temperature = 25°C Full-Scale Current = 20 mA, Digital Scale = 0 dBFS Rev. A | Page 12 of 76 SFDR (dBc) HARMONIC LEVEL (dBc) SFDR (dBc) 07852-011 07852-009 07852-013 SFDR (dBc) HARMONIC LEVEL (dBc) SFDR (dBc) 07852-012 07852-010 07852-008 AD9789 100 90 90 80 80 70 70 60 60 50 50 0dBFS 2.4GHz –3dBFS 2.0GHz 40 –6dBFS 1.6GHz 40 –12dBFS 1.0GHz 30 30 0 100 200 300 400 500 600 700 800 900 1000 1100 0 100 200 300 400 500 600 700 800 900 1000 1100 f (MHz) f (MHz) OUT OUT Figure 14. Third-Order IMD vs. fOUT over fDAC, Full-Scale Current = 20 mA, Figure 17. Third-Order IMD vs. fOUT over Digital Full Scale, fDAC = 2.4 GHz, Digital Scale = 0 dBFS, Temperature = 25°C Full-Scale Current = 20 mA, Temperature = 25°C 100 90 90 80 80 70 70 60 60 50 50 +85°C 32mA +25°C 40 20mA 40 –40°C 8mA 30 30 0 100 200 300 400 500 600 700 800 900 1000 1100 0 100 200 300 400 500 600 700 800 900 1000 1100 f (MHz) OUT f (MHz) OUT Figure 18. Third-Order IMD vs. f over Temperature, f = 2.4 GHz, Figure 15. Third-Order IMD vs. fOUT over Full-Scale Current, fDAC = 2.4 GHz, OUT DAC Full-Scale Current = 20 mA, Digital Scale = 0 dBFS Digital Scale = 0 dBFS, Temperature = 25°C –155 –155 –157 –157 –159 –159 –161 –161 –163 –163 –165 –165 –167 –167 –169 –169 2.4GHz +85°C –171 –171 2.0GHz +25°C –173 1.6GHz –173 –40°C –175 –175 0 200 400 600 800 1000 1200 0 200 400 600 800 1000 1200 f (MHz) f (MHz) OUT OUT Figure 16. NSD vs. fOUT over fDAC, 1-Channel QAM, Full-Scale Current = 20 mA Figure 19. NSD vs. fOUT over Temperature, 1-Channel QAM, fDAC = 2.4 GHz, Full-Scale Current = 20 mA Rev. A | Page 13 of 76 NSD (dBm/Hz) IMD (dBc) IMD (dBc) 07852-034 07852-038 07852-016 NSD (dBm/Hz) IMD (dBc) IMD (dBc) 07852-041 07852-037 07852-019 AD9789 –5 –5 DOCSIS3 DOCSIS3 –15 –15 –40°C –40°C 0°C 0°C +25°C –25 –25 +25°C +85°C +85°C –35 –35 –45 –45 –55 –55 –65 –65 –75 –75 –85 –85 50 250 450 650 850 50 150 250 350 450 550 650 750 850 950 FREQUENCY (MHz) FREQUENCY (MHz) Figure 20. ACLR Performance over Temperature, 1-Channel QAM, Figure 23. ACLR Performance over Temperature, 1-Channel QAM, fDAC = 2.3 GHz, Full-Scale Current = 20 mA, fOUT = 200 MHz, Sum Scale = 48 fDAC = 2.3 GHz, Full-Scale Current = 20 mA, fOUT = 800 MHz, Sum Scale = 48 (DOCSIS SPEC Is −73 dBc; Harmonic Exception Is −63 dBc) (DOCSIS SPEC Is −73 dBc) –55 –55 –60 –60 –65 –65 –70 –70 –75 –75 DOCSIS3 DOCSIS3 25°C 25°C –80 –80 65°C 65°C 85°C 85°C –85 –85 0 100 200 300 400 500 600 700 800 900 1000 0 100 200 300 400 500 600 700 800 900 1000 f (MHz) f (MHz) OUT OUT Figure 21. Second-Order Harmonic Performance vs. fOUT over Temperature, Figure 24. Third-Order Harmonic Performance vs. fOUT over Temperature, 1-Channel QAM, fDAC = 2.3 GHz, Full-Scale Current = 20 mA, Sum Scale = 48 1-Channel QAM, fDAC = 2.3 GHz, Full-Scale Current = 20 mA, Sum Scale = 48 (DOCSIS SPEC Is −73 dBc; Harmonic Exception Is −63 dBc) (DOCSIS SPEC Is −73 dBc; Harmonic Exception Is −63 dBc) –55 –5 DOCSIS3 DOCSIS3 2.3GHz 25°C –60 –15 2.2GHz 65°C 2.4GHz 85°C –25 –65 –35 –70 –45 –55 –75 –65 –80 –75 –85 –85 50 250 450 650 850 1050 0 100 200 300 400 500 600 700 800 900 1000 FREQUENCY (MHz) f (MHz) OUT Figure 22. Noise Floor vs. f over Temperature (ACLR Measured Beyond 30 MHz), Figure 25. ACLR Performance over f , 1-Channel QAM, f = 850 MHz, OUT DAC OUT 1-Channel QAM, f = 2.3 GHz, Full-Scale Current = 20 mA, Sum Scale = 48 Full-Scale Current = 20 mA, Temperature = 25°C, Sum Scale = 48 DAC (DOCSIS SPEC Is −73 dBc) (DOCSIS SPEC Is −73 dBc) Rev. A | Page 14 of 76 ACLR (dBc) HARMONIC LEVEL (dBc) ACLR (dBc) 07852-015 07852-031 07852-014 HARMONIC LEVEL (dBc) ACLR (dBc) ACLR (dBc) 07852-039 07852-018 07852-017 AD9789 0 –5 DOCSIS3 DOCSIS3 –10 25°C CMOS 65°C –15 LVDS 85°C –20 –25 –30 –35 –40 –45 –50 –55 –60 –65 –70 –75 –80 –85 –90 50 250 450 650 850 1050 0 100 200 300 400 500 600 700 800 900 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 26. ACLR Performance for CMOS and LVDS Interfaces, 1-Channel QAM, Figure 29. ACLR Performance over Temperature, 2-Channel QAM, fOUT = 840 MHz, fDAC = 2.4 GHz, Full-Scale Current = 20 mA, Sum Scale = 48 f = 200 MHz, f = 2.3 GHz, Full-Scale Current = 25 mA, Sum Scale = 32 OUT DAC (DOCSIS SPEC Is −73 dBc) (DOCSIS SPEC Is −70 dBc; Harmonic Exception Is −63 dBc) –55 –5 DOCSIS3 25°C 65°C –15 –60 85°C –25 –65 –35 –70 –45 –55 –75 –65 DOCSIS3 25°C –80 –75 65°C 85°C –85 –85 50 250 450 650 850 1050 0 100 200 300 400 500 600 700 800 900 1000 FREQUENCY (MHz) f (MHz) OUT Figure 27. ACLR Performance over Temperature, 2-Channel QAM, Figure 30. Second Harmonic Performance vs. fOUT over Temperature, fOUT = 800 MHz, fDAC = 2.3 GHz, Full-Scale Current = 25 mA, Sum Scale = 32 2-Channel QAM, fDAC = 2.3 GHz, Full-Scale Current = 25 mA, Sum Scale = 32 (DOCSIS SPEC Is −70 dBc) (DOCSIS SPEC Is −70 dBc; Harmonic Exception Is −63 dBc) –55 –55 DOCSIS3 25°C –60 –60 65°C 85°C –65 –65 –70 –70 –75 –75 DOCSIS3 25°C –80 –80 65°C 85°C –85 –85 0 100 200 300 400 500 600 700 800 900 1000 0 100 200 300 400 500 600 700 800 900 1000 f (MHz) f (MHz) OUT OUT Figure 28. Third-Order Harmonic Performance vs. fOUT over Temperature, Figure 31. Noise Floor vs. fOUT over Temperature (ACLR Measured Beyond 30 MHz), 2-Channel QAM, fDAC = 2.3 GHz, Full-Scale Current = 25 mA, Sum Scale = 32 2-Channel QAM, fDAC = 2.3 GHz, Full-Scale Current = 25 mA, Sum Scale = 32 (DOCSIS SPEC Is −70 dBc; Harmonic Exception Is −63 dBc) (DOCSIS SPEC Is −70 dBc) Rev. A | Page 15 of 76 HARMONIC LEVEL (dBc) ACLR (dBc) ACLR (dBc) 07852-042 07852-043 07852-040 ACLR (dBc) HARMONIC LEVEL (dBc) ACLR (dBc) 07852-044 07852-046 07852-045 AD9789 0 0 –10 –10 DOCSIS3 DOCSIS3 –40°C –20 –20 –40°C 0°C 0°C +25°C +25°C –30 –30 +85°C +85°C –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 50 250 450 650 850 1050 50 250 450 650 850 1050 FREQUENCY (MHz) FREQUENCY (MHz) Figure 32. ACLR Performance over Temperature, 4-Channel QAM, Figure 35. ACLR Performance over Temperature, 4-Channel QAM, fOUT = 200 MHz, fDAC = 2.3 GHz, Full-Scale Current = 25 mA, Sum Scale = 20 f = 800 MHz, f = 2.3 GHz, Full-Scale Current = 25 mA, Sum Scale = 20 OUT DAC (DOCSIS SPEC Is −67 dBc; Harmonic Exception Is −63 dBc) (DOCSIS SPEC Is −67 dBc) –55 –55 –60 –60 –65 –65 –70 –70 –75 –75 DOCSIS3 DOCSIS3 25°C 25°C –80 –80 65°C 65°C 85°C 85°C –85 –85 0 100 200 300 400 500 600 700 800 900 1000 0 100 200 300 400 500 600 700 800 900 1000 f (MHz) f (MHz) OUT OUT Figure 33. Second-Order Harmonic Performance vs. fOUT over Temperature, Figure 36. Third-Order Harmonic Performance vs. fOUT over Temperature, 4-Channel QAM, fDAC = 2.3 GHz, Full-Scale Current = 25 mA, Sum Scale = 20 4-Channel QAM, fDAC = 2.3 GHz, Full-Scale Current = 25 mA, Sum Scale = 20 (DOCSIS SPEC Is −67 dBc; Harmonic Exception Is −63 dBc) (DOCSIS SPEC Is −67 dBc; Harmonic Exception Is −63 dBc) –55 0 DOCSIS3 2.3GHz –10 2.2GHz –60 2.4GHz –20 –65 –30 –70 –40 –50 –75 –60 DOCSIS3 25°C –80 65°C –70 85°C –85 –80 50 250 450 650 850 1050 0 100 200 300 400 500 600 700 800 900 1000 f (MHz) FREQUENCY (MHz) OUT Figure 37. ACLR Performance over f , 4-Channel QAM, f = 850 MHz, Figure 34. Noise Floor vs. fOUT over Temperature (ACLR Measured Beyond 30 MHz), DAC OUT Full-Scale Current = 25 mA, Temperature = 25°C, Sum Scale = 20 4-Channel QAM, fDAC = 2.3 GHz, Full-Scale Current = 25 mA, Sum Scale = 20 (DOCSIS SPEC Is −67 dBc) (DOCSIS SPEC Is −67 dBc) Rev. A | Page 16 of 76 ACLR (dBc) HARMONIC LEVEL (dBc) ACLR (dBc) 07852-027 07852-028 07852-026 HARMONIC LEVEL (dBc) ACLR (dBc) ACLR (dBc) 07852-047 07852-030 07852-029 AD9789 REF –32.76dBm ATTEN 2dB REF –32.76dBm ATTEN 2dB CENTER 840.00MHz SPAN 42MHz CENTER 840.00MHz SPAN 18MHz RES BW 56kHz VBW 560kHz SWEEP 39.12ms (601 PTS) RES BW 30kHz VBW 300kHz SWEEP 58.4ms (601 PTS) FREQ. LOWER UPPER FREQ. LOWER UPPER OFFSET REF BW dBc dBm dBc dBm OFFSET REF BW dBc dBm dBc dBm RMS RESULTS RMS RESULTS CARRIER POWER 3.375MHz 750.0kHz –65.57 –83.66 –68.98 –87.07 CARRIER POWER 3.375MHz 750.0kHz –73.99 –91.97 –74.93 –92.91 –18.10dBm/ 6.375MHz 5.250MHz –75.01 –93.11 –74.62 –92.71 –17.98dBm/ 6.375MHz 5.250MHz –74.94 –92.92 –75.35 –93.33 6.00000MHz 12.00MHz 6.000MHz –76.83 –94.92 –76.46 –94.55 6.00000MHz 18.00MHz 6.000MHz –77.17 –95.26 –76.56 –94.66 Figure 38. 1-Channel QAM ACLR, f = 840 MHz, Temperature = 25°C, Figure 40. 1-Channel QAM ACLR, f = 840 MHz, Temperature = 25°C, OUT OUT Sum Scale = 48, Full-Scale Current = 20 mA, Span = 42 MHz Sum Scale = 48, Full-Scale Current = 20 mA, Span = 18 MHz REF –35.91dBm ATTEN 2dB REF –35.91dBm ATTEN 2dB CENTER 840.00MHz SPAN 42MHz START 831.00MHz STOP 873MHz RES BW 30kHz VBW 300kHz SWEEP 136.2ms (601 PTS) RES BW 30kHz VBW 300kHz SWEEP 136.2ms (601 PTS) FREQ. LOWER UPPER FREQ. LOWER UPPER RMS RESULTS OFFSET REF BW dBc dBm dBc dBm RMS RESULTS OFFSET REF BW dBc dBm dBc dBm CARRIER POWER 3.375MHz 750.0kHz –71.64 –93.39 –72.50 –94.25 CARRIER POWER 3.375MHz 750.0kHz –70.07 –92.16 –73.20 –94.49 –21.75dBm/ 6.375MHz 5.250MHz –73.71 –95.47 –66.72 –88.47 –21.29dBm/ 6.375MHz 5.250MHz –69.05 –90.34 –73.87 –95.16 6.00000MHz 12.00MHz 6.000MHz –73.58 –95.33 0.50 –21.10 6.00000MHz 12.00MHz 6.000MHz –0.49 –21.78 –73.29 –94.58 18.00MHz 6.000MHz –73.70 –95.45 –66.72 –88.48 18.00MHz 6.000MHz –66.61 –87.90 –73.98 –95.27 Figure 39. 2-Channel QAM ACLR, fOUT = 840 MHz, Sum Scale = 32, Figure 41. 2-Channel QAM ACLR, fOUT = 840 MHz, Sum Scale = 32, Full-Scale Current = 25 mA, Span = 42 MHz, Channel 1 Full-Scale Current = 25 mA, Span = 42 MHz, Channel 2 Rev. A | Page 17 of 76 07852-061 07852-020 07852-066 07852-023 AD9789 REF –35.91dBm ATTEN 2dB REF –35.91dBm ATTEN 2dB CENTER 840.00MHz SPAN 18MHz CENTER 852.00MHz SPAN 18MHz RES BW 30kHz VBW 300kHz SWEEP 58.4ms (601 PTS) RES BW 30kHz VBW 300kHz SWEEP 58.4ms (601 PTS) FREQ. LOWER UPPER FREQ. LOWER UPPER OFFSET REF BW dBc dBm dBc dBm OFFSET REF BW dBc dBm dBc dBm RMS RESULTS RMS RESULTS CARRIER POWER CARRIER POWER 3.375MHz 750.0kHz –75.37 –96.93 –75.56 –97.11 3.375MHz 750.0kHz –75.51 –96.54 –75.17 –96.20 –21.56dBm/ –21.03dBm/ 6.375MHz 5.250MHz –73.85 –95.41 –72.54 –94.10 6.375MHz 5.250MHz –72.55 –93.58 –73.90 –94.93 6.00000MHz 6.00000MHz Figure 42. Zoomed 2-Channel QAM ACLR, fOUT = 840 MHz, Sum Scale = 32, Figure 44. Zoomed 2-Channel QAM ACLR, fOUT = 840 MHz, Sum Scale = 32, Full-Scale Current = 25 mA, Span = 18 MHz, Channel 1 Full-Scale Current = 25 mA, Span = 18 MHz, Channel 2 REF –35.96dBm ATTEN 2dB REF –35.96dBm ATTEN 2dB CENTER 834.00MHz SPAN 42MHz CENTER 852.00MHz SPAN 42MHz RES BW 30kHz VBW 300kHz SWEEP 136.2ms (601 PTS) RES BW 30kHz VBW 300kHz SWEEP 136.2ms (601 PTS) FREQ. LOWER UPPER FREQ. LOWER UPPER RMS RESULTS OFFSET REF BW dBc dBm dBc dBm RMS RESULTS OFFSET REF BW dBc dBm dBc dBm CARRIER POWER 3.375MHz 750.0kHz –70.33 –93.96 –11.07 –34.70 CARRIER POWER 3.375MHz 750.0kHz –11.10 –34.32 –72.19 –95.42 –23.63dBm/ 6.375MHz 5.250MHz –69.04 –92.67 –0.49 –24.12 –23.23dBm/ 6.375MHz 5.250MHz –0.75 –23.98 –68.97 –92.20 6.00000MHz 12.00MHz 6.000MHz –70.38 –94.01 0.00 –23.63 6.00000MHz 12.00MHz 6.000MHz –0.59 –23.81 –70.32 –93.55 18.00MHz 6.000MHz –71.02 –94.65 0.43 –23.20 18.00MHz 6.000MHz –0.35 –23.58 –70.70 –93.93 Figure 43. 4-Channel QAM ACLR, f = 840 MHz, Temperature = 25°C, Figure 45. 4-Channel QAM ACLR, f = 840 MHz, Temperature = 25°C, OUT OUT Sum Scale = 20, Full-Scale Current = 25 mA, Span = 42 MHz, Channel 1 Sum Scale = 20, Full-Scale Current = 25 mA, Span = 42 MHz, Channel 4 Rev. A | Page 18 of 76 07852-021 07852-065 07852-022 07852-067 AD9789 REF –35.96dBm ATTEN 2dB REF –35.96dBm ATTEN 2dB CENTER 834.00MHz SPAN 18MHz CENTER 852.00MHz SPAN 18MHz RES BW 30kHz VBW 300kHz SWEEP 58.4ms (601 PTS) RES BW 30kHz VBW 300kHz SWEEP 58.4ms (601 PTS) FREQ. LOWER UPPER FREQ. LOWER UPPER RMS RESULTS OFFSET REF BW dBc dBm dBc dBm RMS RESULTS OFFSET REF BW dBc dBm dBc dBm 3.375MHz 750.0kHz –72.95 –96.56 –10.86 –34.48 3.375MHz 750.0kHz –11.20 –34.40 –74.44 –97.64 CARRIER POWER CARRIER POWER 6.375MHz 5.250MHz –69.38 –92.99 –0.51 –24.13 6.375MHz 5.250MHz –0.77 –23.96 –69.07 –92.26 –23.62dBm/ –23.20dBm/ 6.00000MHz 6.00000MHz Figure 46. Zoomed 4-Channel QAM ACLR, fOUT = 840 MHz, Temperature = Figure 49. Zoomed 4-Channel QAM ACLR, fOUT = 840 MHz, Temperature = 25°C, Sum Scale = 20, Full-Scale Current = 25 mA, Span = 18 MHz, Channel 1 25°C, Sum Scale = 20, Full-Scale Current = 25 mA, Span = 18 MHz, Channel 4 50 50 48 48 46 46 44 44 42 42 40 40 38 38 36 36 +25°C +25°C 34 34 +85°C +85°C 32 32 –40°C –40°C 30 30 50 150 250 350 450 550 650 750 850 950 50 150 250 350 450 550 650 750 850 950 f (MHz) f (MHz) OUT OUT Figure 47. Modulation Error Ratio, Equalized, 1-Channel 256-QAM, Figure 50. Modulation Error Ratio, Equalized, 4-Channel 256-QAM, fDAC = 2.29376 GHz, Full-Scale Current = 20 mA, Sum Scale = 48 fDAC = 2.29376 GHz, Full-Scale Current = 25 mA, Sum Scale = 20 (Equalization Filter from Demodulation Toolbox on Spectrum Analyzer Used) (Equalization Filter from Demodulation Toolbox on Spectrum Analyzer Used) 50 50 48 48 46 46 44 44 42 42 40 40 38 38 36 36 +25°C +25°C 34 34 +85°C +85°C –40°C –40°C 32 32 30 30 50 150 250 350 450 550 650 750 850 950 50 150 250 350 450 550 650 750 850 950 f (MHz) f (MHz) OUT OUT Figure 48. Modulation Error Ratio, Unequalized, 1-Channel 256-QAM, Figure 51. Modulation Error Ratio, Unequalized, 4-Channel 256-QAM, fDAC = 2.29376 GHz, Full-Scale Current = 20 mA, Sum Scale = 48 fDAC = 2.29376 GHz, Full-Scale Current = 25 mA, Sum Scale = 20 Rev. A | Page 19 of 76 MER (dB) MER (dB) 07852-033 07852-032 07852-024 MER (dB) MER (dB) 07852-036 07852-035 07852-025 AD9789 REF –32.62dBm ATTEN 0dB 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 CENTER 2.100GHz SPAN 53.84MHz f (MHz) OUT RES BW 30kHz VBW 300kHz SWEEP 174.6ms (601 PTS) FREQ. LOWER UPPER Figure 52. SFDR vs. f in Mix Mode, f = 2.4 GHz, Full-Scale Current = 20 mA OUT DAC OFFSET REF BW dBc dBm dBc dBm RMS RESULTS (Second Nyquist Zone Performance) CARRIER POWER 5.000MHz 3.840MHz –68.93 –88.88 –67.99 –87.94 –19.95dBm/ 10.00MHz 3.840MHz –71.31 –91.26 –70.42 –90.37 3.84000MHz 15.00MHz 3.840MHz –73.43 –93.37 –72.68 –92.63 90 20.00MHz 3.840MHz –75.12 –95.07 –74.89 –94.84 25.00MHz 3.840MHz –75.60 –95.55 –76.51 –96.46 85 Figure 55. One-Carrier WCDMA ACLR in Mix Mode, fOUT = 2.1 GHz, 80 fDAC = 2304 MHz, Full-Scale Current = 20 mA 75 70 REF –38.62dBm ATTEN 2dB 65 60 55 50 45 40 35 30 1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 f (MHz) OUT Figure 53. IMD vs. fOUT in Mix Mode, fDAC = 2.4 GHz, Full-Scale Current = 20 mA (Second Nyquist Zone Performance) –40 CENTER 2.102 50GHz SPAN 63.84MHz FIRST ADJACENT CHANNEL RES BW 30kHz VBW 300kHz SWEEP 207ms (601 PTS) –45 SECOND ADJACENT CHANNEL FREQ. LOWER UPPER THIRD ADJACENT CHANNEL RMS RESULTS OFFSET REF BW dBc dBm dBc dBm –50 FIFTH ADJACENT CHANNEL CARRIER POWER 5.000MHz 3.840MHz –0.25 –26.31 –0.42 –26.47 –26.06dBm/ 10.00MHz 3.840MHz –0.42 –26.48 –63.50 –89.56 –55 3.84000MHz 15.00MHz 3.840MHz –64.07 –90.13 –65.13 –91.18 20.00MHz 3.840MHz –65.36 –91.42 –66.97 –93.03 –60 25.00MHz 3.840MHz –66.86 –92.92 –68.70 –94.76 30.00MHz 3.840MHz –67.83 –93.89 –68.64 –94.70 –65 Figure 56. Four-Carrier WCDMA ACLR in Mix Mode, f = 2.1 GHz, OUT f = 2304 MHz, Full-Scale Current = 20 mA DAC –70 –75 –80 –85 1150 1250 1350 1450 1550 1650 1750 1850 1950 2050 2150 2250 f (MHz) OUT Figure 54. ACLR vs. f in Mix Mode with One-Carrier WCDMA, f = 2304 MHz, OUT DAC Full-Scale Current = 20 mA (Second Nyquist Zone Performance) Rev. A | Page 20 of 76 IMD (dBc) SFDR (dBc) ACLR (dBc) 07852-075 07852-076 07852-068 07852-093 07852-092 AD9789 1100 2000 AVDD33 TOTAL (CMOS) 1000 1800 DVDD33 (LVDS) TOTAL (LVDS) DVDD33 (CMOS) 900 DVDD18 1600 DVDD15 800 CVDD18 1400 700 1200 600 1000 500 800 400 600 300 400 200 200 100 0 0 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 f (GHz) f (GHz) DAC DAC Figure 57. Power Dissipation by Supply vs. f , 4-Channel DOCSIS, f = 915 MHz, Figure 60. Total Power Dissipation vs. f , 4-Channel DOCSIS, f = 915 MHz, DAC OUT DAC OUT Full-Scale Current = 25 mA (Datapath Configuration: QAM Encoder On, Full-Scale Current = 25 mA (Datapath Configuration: QAM Encoder On, SRRC Filter On, Four 2× Interpolation Filters On) SRRC Filter On, Four 2× Interpolation Filters On) 700 1400 TOTAL (CMOS) AVDD33 TOTAL (LVDS) DVDD33 (LVDS) 600 1200 DVDD33 (CMOS) DVDD18 DVDD15 500 1000 CVDD18 400 800 300 600 200 400 100 200 0 0 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 f (GHz) f (GHz) DAC DAC Figure 58. Power Dissipation by Supply vs. fDAC, 16× Interpolation, Figure 61. Total Power Dissipation vs. fDAC, 16× Interpolation, One Channel Enabled, fOUT = 70 MHz, Full-Scale Current = 20 mA One Channel Enabled, fOUT = 70 MHz, Full-Scale Current = 20 mA 200 180 160 140 AVDD33 120 100 80 60 40 20 0 8 10 1214 16 1820 22 24 26 283032 FULL-SCALE CURRENT (mA) Figure 59. AVDD33 Power Dissipation vs. Full-Scale Current Rev. A | Page 21 of 76 POWER DISSIPATION (mW) POWER DISSIPATION (mW) POWER DISSIPATION (mW) 07852-098 07852-095 07852-094 POWER DISSIPATION (mW) POWER DISSIPATION (mW) 07852-097 07852-096 AD9789 TERMINOLOGY Monotonicity Spurious-Free Dynamic Range (SFDR) A DAC is monotonic if the output either increases or remains SFDR is the difference, in dB, between the peak amplitude of constant as the digital input increases. the output signal and the peak spurious signal over the specified bandwidth. Offset Error Offset error is the deviation of the output current from the ideal Noise Spectral Density (NSD) of 0. For IOUTP, 0 mA output is expected when all inputs are NSD is the converter noise power per unit of bandwidth. NSD set to 0. For IOUTN, 0 mA output is expected when all inputs is usually specified in dBm/Hz in the presence of a 0 dBm full- are set to 1. scale signal. Gain Error Adjacent Channel Leakage Ratio (ACLR) Gain error is the difference between the actual and ideal output The adjacent channel leakage (power) ratio is the ratio, in dBc, span. The actual span is determined by the output when all inputs between the measured power within a channel relative to its are set to 1s minus the output when all inputs are set to 0s. adjacent channels. Temperature Drift Modulation Error Ratio (MER) Modulated signals create a discrete set of output values referred Temperature drift is specified as the maximum change from the to as a constellation. Each symbol creates an output signal corre- ambient (25°C) value to the value at either T or T . For offset, MIN MAX sponding to one point on the constellation. MER is a measure gain, and reference drift, the drift is reported in ppm per °C. of the discrepancy between the average output symbol magnitude Power Supply Rejection (PSR) and the rms error magnitude of the individual symbol. PSR is the maximum change in the full-scale output as the Intermodulation Distortion (IMD) supplies are varied from nominal to minimum and maximum IMD is the result of two or more signals at different frequencies specified voltages. mixing together. Many products are created according to the Output Compliance Range formula af ± bf , where a and b are integer values. 1 2 The output compliance range is the range of allowable voltage at the output of a current output DAC. Operation beyond the maximum compliance limits may cause either output stage saturation or breakdown, resulting in nonlinear performance. Rev. A | Page 22 of 76 AD9789 SERIAL CONTROL PORT The AD9789 serial control port is a flexible, synchronous serial transfers or by returning CS low for at least one complete SCLK communications port that allows an easy interface to many cycle (but less than eight SCLK cycles). Raising CS on a nonbyte industry-standard microcontrollers and microprocessors. The boundary terminates the serial transfer and flushes the buffer. AD9789 serial control port is compatible with most synchronous In streaming mode (see Table 7), any number of data bytes can transfer formats, including both the Motorola SPI® and Intel® SSR be transferred in a continuous stream. The register address is protocols. The serial control port allows read/write access to all automatically incremented or decremented (see the MSB/LSB registers that configure the AD9789. Single- or multiple-byte CS First Transfers section). must be raised at the end of the last transfers are supported, as well as MSB first or LSB first transfer byte to be transferred, thereby ending streaming mode. formats. The AD9789 serial control port can be configured for a Communication Cycle—Instruction Plus Data single bidirectional I/O pin (SDIO only) or for two unidirectional I/O pins (SDIO/SDO). By default, the AD9789 is in unidirectional There are two parts to a communication cycle with the AD9789. long instruction mode (long instruction mode is the only In the first part, a 16-bit instruction word is written to the instruction mode supported). AD9789, coincident with the first 16 SCLK rising edges. The instruction word provides the AD9789 serial control port with SERIAL CONTROL PORT PIN DESCRIPTIONS information regarding the data transfer, which is the second The SCLK (serial clock) pin is the serial shift clock. This pin is part of the communication cycle. The instruction word defines an input. SCLK is used to synchronize serial control port reads whether the upcoming data transfer is a read or a write, the and writes. Write data bits are registered on the rising edge of number of bytes in the data transfer, and the starting register this clock, and read data bits are registered on the falling edge. address for the first byte of the data transfer. This pin is internally pulled down by a 30 kΩ resistor to ground. Write SDIO (serial data input/output) is a dual-purpose pin that acts If the instruction word is for a write operation, the second part as an input only (unidirectional mode) or as both an input and of the communication cycle is the transfer of data into the serial an output (bidirectional mode). The AD9789 defaults to the control port buffer of the AD9789. Data bits are registered on unidirectional I/O mode (Register 0x00[7] = 0). the rising edge of SCLK. The SDO (serial data output) pin is used only in the unidirectional The length of the transfer (one, two, or three bytes or streaming I/O mode as a separate output pin for reading back data. mode) is indicated by two bits (N1 and N0) in the instruction byte. CS (chip select bar) is an active low control that gates the read When the transfer is one, two, or three bytes (but not streaming CS and write cycles. When is high, SDO and SDIO are in a high CS mode), can be raised after each sequence of eight bits to stall impedance state. This pin is internally pulled up by a 30 kΩ the bus, except after the last byte, where it ends the cycle. When resistor to DVDD33. the bus is stalled, the serial transfer resumes when CS is lowered. Raising CS on a nonbyte boundary resets the serial control port. M1 SCLK During a write, streaming mode does not skip reserved or blank AD9789 CS L1 SERIAL registers; therefore, the user must know what bit pattern to write CONTROL SDO N1 to the reserved registers to preserve proper operation of the PORT SDIO P1 part. It does not matter what data is written to blank registers. Figure 62. Serial Control Port Most writes to the control registers immediately reconfigure the device. However, Register 0x16 through Register 0x1D do not GENERAL OPERATION OF SERIAL CONTROL PORT directly control device operation. They provide data to internal A write or read operation to the AD9789 is initiated by pulling logic that must perform additional operations on the data before CS low. CS stall high is supported in modes where three or it is downloaded and the device configuration is changed. For fewer bytes of data (plus the instruction data) are transferred any updates to Register 0x16 through Register 0x1D to take (see Table 7). In these modes, CS can temporarily return high effect, the FREQNEW bit (Register 0x1E[7]) must be set to 1 on any byte boundary, allowing time for the system controller (this bit is self-clearing). Any number of bytes of data can be CS to process the next byte. can go high on byte boundaries changed before updating registers. Setting the FREQNEW bit only and can go high during either part (instruction or data) simultaneously updates Register 0x16 through Register 0x1D. of the transfer. In a similar fashion, any changes to Register 0x22 and Register 0x23 require PARMNEW (Register 0x24[7]) to be toggled from During CS stall high mode, the serial control port state machine a low state to a high state before the new values take effect. enters a wait state until all data is sent. If the system controller Unlike the FREQNEW bit, PARMNEW is not self-clearing. decides to abort the transfer before all of the data is sent, the state machine must be reset by either completing the remaining Rev. A | Page 23 of 76 07852-048 AD9789 Read Bits[A12:A0] select the address within the register map that is written to or read from during the data transfer portion of the If the instruction word is for a read operation, the next N × 8 communication cycle. Only Bits[A6:A0] are needed to cover the SCLK cycles clock out the data from the address specified in the range of the 0x55 registers used by the AD9789. Bits[A12:A7] instruction word, where N is 1 to 3 as determined by Bits[N1:N0]. must always be 0. For multibyte transfers, this address is the If N = 4, the read operation is in streaming mode, continuing starting byte address. In MSB first mode, subsequent bytes CS until is raised. Streaming mode does not skip over reserved increment the address. or blank registers. The readback data is valid on the falling edge of SCLK. MSB/LSB FIRST TRANSFERS The default mode of the AD9789 serial control port is the uni- The AD9789 instruction word and byte data can be MSB first or directional mode. In unidirectional mode, the readback data LSB first. Any data written to Register 0x00 must be mirrored, appears on the SDO pin. It is also possible to set the AD9789 to the upper four bits (Bits[7:4]) with the lower four bits (Bits [3:0]). bidirectional mode using the SDIO_DIR bit (Register 0x00[7]). This makes it irrelevant whether LSB first or MSB first is in In bidirectional mode, both the sent data and the readback data effect. As an example of this mirroring, the default setting for appear on the SDIO pin. Register 0x00[7:0] is 0x18, which mirrors Bit 4 and Bit 3. These bits set the long instruction mode (the default and the only A readback request reads the data that is in the serial control port mode supported). The default for the AD9789 is MSB first. buffer area or the data in the active registers (see Figure 63). When LSB first is set by Register 0x00[1] and Register 0x00[6], The AD9789 supports only the long instruction mode; therefore, it takes effect immediately. In multibyte transfers, subsequent Register 0x00[4:3] reads 11 (this register uses mirrored bits). bytes reflect any changes in the serial port configuration. Long instruction mode is the default at power-up or reset, and writing to these bits has no effect. When MSB first mode is active, the instruction and data bytes must be written from MSB to LSB. Multibyte data transfers in The AD9789 uses Register Address 0x00 to Register Address 0x55. MSB first format start with an instruction byte that includes the register address of the most significant data byte. Subsequent SCLK data bytes must follow in order from the high address to the low SDIO address. In MSB first mode, the serial control port internal address generator decrements for each data byte of the multi- SDO FREQNEW byte transfer cycle. CS SERIAL CONTROL When LSB first mode is active, the instruction and data bytes PORT must be written from LSB to MSB. Multibyte data transfers in WRITE REGISTER 0x1E = 0x10 TO UPDATE REGISTERS LSB first format start with an instruction byte that includes the Figure 63. Relationship Between Serial Control Port Buffer Registers and register address of the least significant data byte followed by Active Registers of the AD9789 multiple data bytes. The internal byte address generator of the serial control port increments for each byte of the multibyte INSTRUCTION WORD (16 BITS) transfer cycle. W The MSB of the instruction word is R/ , which indicates The AD9789 serial control port register address decrements whether the instruction is a read or a write. The next two bits, from the register address just written toward 0x00 for multibyte N1 and N0, indicate the length of the transfer in bytes. The final I/O operations if the MSB first mode is active (default). If the 13 bits (Bits[A12:A0]) are the address at which to begin the read LSB first mode is active, the register address of the serial control or write operation. port increments from the address just written toward 0x55 for For a write, the instruction word is followed by the number of multibyte I/O operations. bytes of data indicated by Bits[N1:N0] (see Table 7). Streaming mode always terminates when it reaches Address 0x2F. Table 7. Byte Transfer Count Note that unused addresses are not skipped during multibyte I/O N1 N0 Bytes to Transfer operations. 0 0 1 Table 8. Streaming Mode (No Addresses Are Skipped) 0 1 2 Write Mode Address Direction Stop Sequence 1 0 3 LSB First Increment 0x02D, 0x02E, 0x02F, stop 1 1 Streaming mode MSB First Decrement 0x001, 0x000, 0x02F, stop Rev. A | Page 24 of 76 BUFFER REGISTERS ACTIVE REGISTERS 07852-049 AD9789 Table 9. Serial Control Port, 16-Bit Instruction Word, MSB First MSB LSB I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0 R/W N1 N0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 CS SCLK DON'T CARE DON'T CARE SDIO DON'T CARE R/W N1 N0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 DON'T CARE 16-BIT INSTRUCTION HEADER REGISTER (N) DATA REGISTER (N – 1) DATA Figure 64. Serial Control Port Write—MSB First, 16-Bit Instruction, Two Bytes of Data CS SCLK DON'T CARE DON'T CARE R/W N1 N0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 SDIO DON'T CARE D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SDO DON'T 16-BIT INSTRUCTION HEADER REGISTER (N) DATA REGISTER (N – 1) DATA REGISTER (N – 2) DATA REGISTER (N – 3) DATA CARE Figure 65. Serial Control Port Read—MSB First, 16-Bit Instruction, Four Bytes of Data t DS t HI t t S t C CLK t DH t LO CS SCLK DON'T CARE DON'T CARE SDIO DON'T CARE R/W N1 N0 A12 A11 A10 A9A8A7A6A5 D4 D3D2D1D0 DON'T CARE Figure 66. Serial Control Port Write—MSB First, 16-Bit Instruction, Timing Measurements CS SCLK t DV SDIO DATA BIT N DATA BIT N – 1 SDO Figure 67. Timing Diagram for Serial Control Port Register Read CS SCLK DON'T CARE DON'T CARE DON'T CARE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 N0 N1 R/W D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 DON'T CARE SDIO 16-BIT INSTRUCTION HEADER REGISTER (N) DATA REGISTER (N + 1) DATA Figure 68. Serial Control Port Write—LSB First, 16-Bit Instruction, Two Bytes of Data Rev. A | Page 25 of 76 07852-053 07852-052 07852-051 07852-054 07852-050 AD9789 t t S C CS t CLK t t HI LO t DS SCLK t DH SDIO BIT N BIT N + 1 Figure 69. Serial Control Port Timing—Write Table 10. Serial Control Port Timing Parameter Description tDS Setup time between data and rising edge of SCLK t Hold time between data and rising edge of SCLK DH t Period of the clock CLK tS Setup time between CS falling edge and SCLK rising edge (start of communication cycle) tC Setup time between SCLK rising edge and CS rising edge (end of communication cycle) tHI Minimum period that SCLK should be in a logic high state t Minimum period that SCLK should be in a logic low state LO t SCLK to valid SDIO and SDO (see Figure 67) DV Rev. A | Page 26 of 76 07852-055 AD9789 SPI REGISTER MAP Do not write to the following registers unless instructed otherwise: Register 0x34, Register 0x35, Register 0x37, Register 0x3B, Register 0x3F, or Register 0x40 through Register 0x55. Table 11. Register Map De- Addr Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 fault 0x00 SPI control SDIO_DIR LSBFIRST RESET LNG_INST 0x18 0x01 Saturation SATCNT[7:0] 0x00 counter 0x02 Parity counter PARCNT[7:0] 0x00 0x03 Interrupt enable PARERR BISTDONE PARMSET PARMCLR LOCKACQ LOCKLOST SATERR Reserved 0x00 0x04 Interrupt PARERR BISTDONE PARMSET PARMCLR LOCKACQ LOCKLOST SATERR Reserved 0x00 status/clear 0x05 Channel enable Reserved CHANEN[3:0] 0x00 0x06 Bypass QAM SRRC Reserved INT[4:0] 0x00 0x07 QAM/SRRC Reserved ALPHA[1:0] Reserved MAPPING[2:0] 0x01 configuration 0x08 Summing node SUMSCALE[7:0] 0x0D scalar 0x09 Input scalar INSCALE[7:0] 0x20 0x0A NCO 0 frequency FTW0[7:0] 0x00 tuning word 0x0B FTW0[15:8] 0x00 0x0C FTW0[23:16] 0x00 0x0D NCO 1 frequency FTW1[7:0] 0x00 tuning word 0x0E FTW1[15:8] 0x00 0x0F FTW1[23:16] 0x00 0x10 NCO 2 frequency FTW2[7:0] 0x00 tuning word 0x11 FTW2[15:8] 0x00 0x12 FTW2[23:16] 0x00 0x13 NCO 3 frequency FTW3[7:0] 0x00 tuning word 0x14 FTW3[15:8] 0x00 0x15 FTW3[23:16] 0x00 0x16 Rate converter Q[7:0] 0x00 denominator (Q) 0x17 Q[15:8] 0x00 0x18 Q[23:16] 0x80 0x19 Rate converter P[7:0] 0x00 numerator (P) 0x1A P[15:8] 0x00 0x1B P[23:16] 0x80 0x1C Interpolating BPF FC[7:0] 0x00 center frequency 0x1D FC[15:8] 0x00 0x1E Frequency update FREQNEW Reserved 0x00 0x1F Hardware version Reserved VER[3:0] 0x03 0x20 Interface CMOS_BUS CMOS_CTRL Reserved DCO_INV IF_MODE CHANPRI PAR[1:0] 0xC8 configuration 0x21 Data control BIN BUSWDTH[1:0] DATWDTH CMPLX LTNCY[2:0] 0x61 0x22 DCO frequency Reserved DCODIV[2:0] ONES[3:0] 0x1F 0x23 Internal clock DSCPHZ[3:0] SNCPHZ[3:0] 0x85 phase adjust 0x24 Parameter update PARMNEW Reserved 0x00 0x25 Channel 0 gain CHAN0GAIN[7:0] 0x80 0x26 Channel 1 gain CHAN1GAIN[7:0] 0x80 0x27 Channel 2 gain CHAN2GAIN[7:0] 0x80 0x28 Channel 3 gain CHAN3GAIN[7:0] 0x80 0x29 Spectrum shaping Reserved SPEC_INV 0x00 Rev. A | Page 27 of 76 AD9789 De- Addr Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 fault 0x2F Mu Delay SEARCH_ SEARCH_ERR TRACK_ GUARDBAND[4:0] 0x0B Control 1 TOL ERR 0x30 Mu control duty Duty cycle INC_DEC MANUAL_ADJ[5:0] 0x40 cycle correct (Factory) (Factory test only) enable 0x31 Clock Receiver 1 CLKN_CML[3:0] Reserved 0xF0 0x32 Clock Receiver 2 CLK_DIS Reserved PSIGN CLKP_CML[3:0] NSIGN 0x3F 0x33 Mu Delay MU_CLKDIS SLOPE MODE[1:0] MUSAMP GAIN[1:0] MU_EN 0x42 Control 2 0x34 Reserved Reserved 0x00 0x35 Reserved Reserved 0xCA 0x36 DAC bias PDBIAS Reserved MSEL[1:0] 0x03 0x37 Reserved Reserved 0x00 0x38 DAC decoder Reserved DAC decoder mode 0x00 0x39 Mu Delay MUDLY[0] SEARCH_DIR[1:0] MUPHZ[4:0] 0x40 Control 3 0x3A Mu Delay MUDLY[8:1] 0x00 Control 4 0x3B Reserved Reserved 0x00 0x3C Full-Scale FSC[7:0] 0x00 Current 1 0x3D Full-Scale Reserved FSC[9:8] 0x02 Current 2 0x3E Phase detector PHZ_PD Reserved CMP_BST AUTO_CAL PHZ_DET_BIAS[3:0] 0x18 control 0x3F Reserved Reserved 0x00 0x40 BIST control CLKSHDN INPUTSEL Reserved BENABLE BMODE[3:0] 0x00 0x41 BIST status BDONE BSTATUS[6:0] 0x00 0x42 BIST zero PADLEN[7:0] 0x00 padding length 0x43 PADLEN[15:8] 0x00 0x44 BIST vector VECTLEN[7:0] 0x00 length 0x45 VECTLEN[15:8] 0x00 0x46 VECTLEN[23:16] 0x00 0x47 BIST clock adjust BCLKDIV[3:0] BCLKPHZ[3:0] 0x00 0x48 Sign 0 control S0ENABL S0RDEN S0PRNG S0ZERO S0NEG S0FNLCH S0SEL[1:0] 0x00 0x49 Sign 0 clock S0CLKDIV[3:0] S0CLKPHZ[3:0] 0x00 adjust 0x4A Sign 1 control S1ENABL S1RDEN S1PRNG S1ZERO S1NEG S1FNLCH S1SEL[1:0] 0x00 0x4B Sign 1 clock S1CLKDIV[3:0] S1CLKPHZ[3:0] 0x00 adjust 0x4C RegFnl0Freq 0x00 Final Rate/Offset Control 0 [7:0] 0x4D RegFnl1Freq Final Rate/Offset Control 1 [7:0] 0x00 0x50 BIST Signature 0 SGN0[7:0] 0x00 0x51 SGN0[15:8] 0x00 0x52 SGN0[23:16] 0x00 0x53 BIST Signature 1 SGN1[7:0] 0x00 0x54 SGN1[15:8] 0x00 0x55 SGN1[23:16] 0x00 Rev. A | Page 28 of 76 AD9789 SPI REGISTER DESCRIPTIONS Table 12. SPI Control Register (Address 0x00) Bit Bit Name Description 7 SDIO_DIR This bit configures the SDIO pin as an input-only pin or as a bidirectional input/output pin. Both choices conform to the SPI standard. 0 = input only. 1 = bidirectional (input/output). 6 LSBFIRST This bit configures the SPI interface for MSB first or LSB first mode. Both choices conform to the SPI standard. 0 = MSB first. 1 = LSB first. 5 RESET When set to 1, this bit resets the part. After the part is reset, 0 is written to this bit on the next cycle. 0 = no reset. 1 = software reset. 4 LNG_INST This bit sets the SPI to long instruction mode; 1 is the only valid value. [3:0] These bits should mirror Bits[7:4]. Bit 3 should mirror Bit 4, Bit 2 should mirror Bit 5, Bit 1 should mirror Bit 6, and Bit 0 should mirror Bit 7. Table 13. Saturation Counter Register (Address 0x01) Bit Bit Name Description [7:0] SATCNT[7:0] This read-only register contains the saturation counter. This register reflects the number of samples at the output of the SUMSCALE gain block that overrange the datapath and are digitally clipped. The count is cleared by writing a 1 to Register 0x04, Bit 1. Table 14. Parity Counter Register (Address 0x02) Bit Bit Name Description [7:0] PARCNT[7:0] This read-only register contains the input data parity error counter. The count is cleared by writing a 1 to Register 0x04, Bit 7. Table 15. Interrupt Enable Register (Address 0x03) Bit Name Description 7 PARERR Setting this bit to 1 enables a PARERR flag to generate an interrupt request. Generating an interrupt request results in Interrupt Bit 7 being set in Register 0x04 and the IRQ pin going low. 6 BISTDONE Setting this bit to 1 enables a BISTDONE flag to generate an interrupt request. Generating an interrupt request results in Interrupt Bit 6 being set in Register 0x04 and the IRQ pin going low. 5 PARMSET Setting this bit to 1 enables a PARMS_SET flag to generate an interrupt request. Generating an interrupt request results in Interrupt Bit 5 being set in Register 0x04 and the IRQ pin going low. 4 PARMCLR Setting this bit to 1 enables a PARMS_CLR flag to generate an interrupt request. Generating an interrupt request results in Interrupt Bit 4 being set in Register 0x04 and the IRQ pin going low. 3 LOCKACQ Setting this bit to 1 enables a LOCKACQ flag to generate an interrupt request. Generating an interrupt request results in Interrupt Bit 3 being set in Register 0x04 and the IRQ pin going low. 2 LOCKLOST Setting this bit to 1 enables a LOCKLOST flag to generate an interrupt request. Generating an interrupt request results in Interrupt Bit 2 being set in Register 0x04 and the IRQ pin going low. 1 SATERR Setting this bit to 1 enables a SATERR (overflow into 16× interpolator) flag to generate an interrupt request. Generating an interrupt request results in Interrupt Bit 1 being set in Register 0x04 and the IRQ pin going low. 0 Reserved Reserved. Rev. A | Page 29 of 76 AD9789 Table 16. Interrupt Status/Clear Register (Address 0x04) Bit Name Description 7 PARERR If this bit is set to 1, one or more parity errors has occurred. Writing a 1 to this bit clears the interrupt. 6 BISTDONE If this bit is set to 1, the BIST has reached the terminal state. Writing a 1 to this bit clears the interrupt. 5 PARMSET If this bit is set to 1, the parameter update register (Address 0x24) has been updated. Writing a 1 to this bit clears the interrupt. 4 PARMCLR If this bit is set to 1, the parameter update register (Address 0x24) has been cleared. Writing a 1 to this bit clears the interrupt. 3 LOCKACQ If this bit is set to 1, proper data handoff between the digital engine and the DAC core is occurring. 2 LOCKLOST If this bit is set to 1, proper data handoff between the digital engine and the DAC core has been lost. Writing a 1 to this bit clears the interrupt. 1 SATERR If this bit is set to 1, one or more saturation errors (overflow into 16× interpolator) has occurred. Writing a 1 to this bit clears the interrupt. 0 Reserved Reserved. Table 17. Channel Enable Register (Address 0x05) Bit Bit Name Description [7:4] Reserved Reserved. [3:0] CHANEN[3:0] A Logic 1 in any bit position enables the corresponding channel; 0000 means that all channels are disabled. Setting Channels Enabled 0000 All channels disabled. 0001 Channel 0 enabled. 0010 Channel 1 enabled. 0011 Channel 0 and Channel 1 enabled. … … 1110 Channel 1, Channel 2, and Channel 3 enabled. 1111 All channels enabled. Table 18. Bypass Register (Address 0x06) Bit Bit Name Description 7 QAM If this bit is set to 1, the QAM mappers are bypassed. 6 SRRC If this bit is set to 1, the square root raised cosine (SRRC) filters are bypassed. 5 Reserved Reserved. [4:0] INT[4:0] A Logic 1 in any bit position bypasses the corresponding interpolation filter. The preferred order for bypassing interpolation filters is to first bypass Filter 0, then Filter 1, and so on. Setting Interpolation Filters Bypassed 00000 All interpolation filters enabled. 00001 Interpolation Filter 0 bypassed. 00010 Interpolation Filter 1 bypassed. 00011 Interpolation Filter 0 and Interpolation Filter 1 bypassed. … … 01111 Interpolation Filter 0, Interpolation Filter 1, Interpolation Filter 2, and Interpolation Filter 3 bypassed. … … 11111 All interpolation filters bypassed. Rev. A | Page 30 of 76 AD9789 Table 19. QAM/SRRC Configuration Register (Address 0x07) Bit Bit Name Description [7:6] Reserved Reserved. [5:4] ALPHA[1:0] These bits set the SRRC filter alpha. Setting Alpha Filter 00 0.12 01 0.18 10 0.15 11 0.13 3 Reserved Reserved. [2:0] MAPPING[2:0] These bits set the QAM encoding. Setting QAM Encoding 000 DOCSIS 64-QAM 001 DOCSIS 256-QAM 010 DVB-C 16-QAM 011 DVB-C 32-QAM 100 DVB-C 64-QAM 101 DVB-C 128-QAM 110 DVB-C 256-QAM 111 Unused Table 20. Summing Node Scalar Register (Address 0x08) Bit Bit Name Description [7:0] SUMSCALE[7:0] This register sets the value of the 2.6 multiplier that is applied to the output of the channel summing node. Setting 2.6 Multiplier 00000000 0 00000001 0.015625 00000010 0.03125 … … 00001101 0.203125 (default) … … 11111110 3.96875 11111111 3.984375 Table 21. Input Scalar Register (Address 0x09) Bit Bit Name Description [7:0] INSCALE[7:0] This register sets the value of the 3.5 multiplier that is applied to the input data. This scaling block is in parallel with the QAM encoder block and is used when the QAM encoder block is bypassed. Setting 3.5 Multiplier 00000000 0 00000001 0.03125 00000010 0.0625 … … 00100000 1 (default) … … 11111110 7.9375 11111111 7.96875 Rev. A | Page 31 of 76 AD9789 The three NCO 0 frequency tuning word registers together compose the 24-bit frequency tuning word for NCO 0. For more information about programming these registers, see the Baseband Digital Upconverter section. Table 22. NCO 0 Frequency Tuning Word Registers (Address 0x0A to Address 0x0C) Address Bit Name Description 0x0A FTW0[7:0] Frequency tuning word for NCO 0, Bits[7:0] 0x0B FTW0[15:8] Frequency tuning word for NCO 0, Bits[15:8] 0x0C FTW0[23:16] Frequency tuning word for NCO 0, Bits[23:16] The three NCO 1 frequency tuning word registers together compose the 24-bit frequency tuning word for NCO 1. For more information about programming these registers, see the Baseband Digital Upconverter section. Table 23. NCO 1 Frequency Tuning Word Registers (Address 0x0D to Address 0x0F) Address Bit Name Description 0x0D FTW1[7:0] Frequency tuning word for NCO 1, Bits[7:0] 0x0E FTW1[15:8] Frequency tuning word for NCO 1, Bits[15:8] 0x0F FTW1[23:16] Frequency tuning word for NCO 1, Bits[23:16] The three NCO 2 frequency tuning word registers together compose the 24-bit frequency tuning word for NCO 2. For more information about programming these registers, see the Baseband Digital Upconverter section. Table 24. NCO 2 Frequency Tuning Word Registers (Address 0x10 to Address 0x12) Address Bit Name Description 0x10 FTW2[7:0] Frequency tuning word for NCO 2, Bits[7:0] 0x11 FTW2[15:8] Frequency tuning word for NCO 2, Bits[15:8] 0x12 FTW2[23:16] Frequency tuning word for NCO 2, Bits[23:16] The three NCO 3 frequency tuning word registers together compose the 24-bit frequency tuning word for NCO 3. For more information about programming these registers, see the Baseband Digital Upconverter section. Table 25. NCO 3 Frequency Tuning Word Registers (Address 0x13 to Address 0x15) Address Bit Name Description 0x13 FTW3[7:0] Frequency tuning word for NCO 3, Bits[7:0] 0x14 FTW3[15:8] Frequency tuning word for NCO 3, Bits[15:8] 0x15 FTW3[23:16] Frequency tuning word for NCO 3, Bits[23:16] The three rate converter denominator (Q) registers together compose the 24-bit denominator for the rate converter decimation ratio. For more information about programming these registers, see the Sample Rate Converter section. Table 26. Rate Converter Denominator (Q) Registers (Address 0x16 to Address 0x18) Address Bit Name Description 0x16 Q[7:0] Rate converter denominator, Bits[7:0] 0x17 Q[15:8] Rate converter denominator, Bits[15:8] 0x18 Q[23:16] Rate converter denominator, Bits[23:16] The three rate converter numerator (P) registers together compose the 24-bit numerator for the rate converter decimation ratio. For more information about programming these registers, see the Sample Rate Converter section. Table 27. Rate Converter Numerator (P) Registers (Address 0x19 to Address 0x1B) Address Bit Name Description 0x19 P[7:0] Rate converter numerator, Bits[7:0] 0x1A P[15:8] Rate converter numerator, Bits[15:8] 0x1B P[23:16] Rate converter numerator, Bits[23:16] Rev. A | Page 32 of 76 AD9789 The two interpolating BPF center frequency registers together compose the 16-bit center frequency of the 16× band-pass interpolation filter. For more information about programming these registers, see the Digital 16× Tunable Band-Pass Filter section. Table 28. Interpolating BPF Center Frequency Registers (Address 0x1C and Address 0x1D) Address Bit Name Description 0x1C FC[7:0] Center frequency, Bits[7:0] 0x1D FC[15:8] Center frequency, Bits[15:8] Table 29. Frequency Update Register (Address 0x1E) Bit Name Description 7 FREQNEW Setting this bit to 1 updates the derived registers in the AD9789. This bit must be set for changes to Register 0x16 through Register 0x1D to take effect. This self-clearing bit is reset to 0 after the derived registers are updated. [6:0] Reserved Reserved. Table 30. Hardware Version Register (Address 0x1F) Bit Name Description [7:4] Reserved Reserved. [3:0] VER[3:0] This read-only register indicates the version of the chip (0011). Table 31. Interface Configuration Register (Address 0x20) Bit Bit Name Description 7 CMOS_BUS This bit reflects the state of the CMOS_BUS pin (L14). 6 CMOS_CTRL This bit reflects the state of the CMOS_CTRL pin (M14). 5 Reserved Reserved. 4 DCO_INV When set to 1, the DCO pin is inverted. 3 IF_MODE This bit sets the data interface mode. 0 = channelizer mode. Supports all available interface widths and 8- and 16-bit word widths. Supports maximum fBAUD of fDAC/48. 1 = quadrature digital upconverter (QDUC) mode. Supports 32-bit interface, 16-bit word mode only. Supports maximum fBAUD of fDAC/16. 2 CHANPRI This bit selects the channel prioritization value (used in channelizer mode only). 0 = device expects input samples only for those channels that are enabled. 1 = device expects data for all four channels. Data for disabled channels is expected and must be sent, but this data is discarded by the AD9789. [1:0] PAR[1:0] These bits set the parity checking. For more information, see the Parity section. Setting Parity Checking 00 Parity checking deactivated 01 IQ parity (a value of 0 is expected on the I channel and a value of 1 is expected on the Q channel) 10 Even parity 11 Odd parity Rev. A | Page 33 of 76 AD9789 Table 32. Data Control Register (Address 0x21) Bit Bit Name Description 7 BIN This bit selects the coding for the device. 0 = twos complement coding. 1 = straight binary coding. [6:5] BUSWDTH[1:0] These bits set the input data bus width for the device. Setting Input Bus Width 00 4 bits 01 8 bits 10 16 bits 11 32 bits 4 DATWDTH This bit sets the data-word width that is sent to the datapaths. 0 = 8-bit data-word. 1 = 16-bit data-word. 3 CMPLX This bit configures the datapath for real or complex data. 0 = real data. 1 = complex data. [2:0] LTNCY[2:0] These bits set the turnaround latency from the FS pulse to the internal data sampling time. For more information, see the Latency Register section. Setting Latency 000 Input data begins to be sampled at approximately the first rising edge of DCO after FS goes low. 001 Input data begins to be sampled at approximately the second rising edge of DCO after FS goes low. … … 111 Input data begins to be sampled at approximately the eighth rising edge of DCO after FS goes low. Table 33. DCO Frequency Register (Address 0x22) Bit Bit Name Description 7 Reserved Reserved. [6:4] DCODIV[2:0] These bits configure the data clock output (DCO) frequency. Setting DCO Clock Frequency 000 DCO clock disabled 001 f /16 DACCLK 010 fDACCLK/32 011 Invalid 100 fDACCLK/64 101 Invalid 11x Invalid [3:0] ONES[3:0] These bits always read back 1111. Rev. A | Page 34 of 76 AD9789 Table 34. Internal Clock Phase Adjust Register (Address 0x23) Bit Bit Name Description [7:4] DSCPHZ[3:0] The data sampling clock (DSC) is an internal clock that is used to sample the input data. This clock can occur on 1 of 16 phases to optimize the setup and hold timing of the data interface. Setting Selected Phase 0000 Earliest clock phase 0001 Second earliest clock phase that occurs 1/16 of a DSC cycle later … … 1111 Last available clock phase [3:0] SNCPHZ[3:0] The synchronization clock (SNC) is an internal clock that is used to synchronize the digital datapath clock with the DAC clock. This clock can occur on 1 of 16 phases to optimize the DAC-to-datapath timing. Setting Selected Phase 0000 Earliest clock phase 0001 Second earliest clock phase that occurs 1/16 of a DSC cycle later … … 1111 Last available clock phase Table 35. Parameter Update Register (Address 0x24) Bit Name Description 7 PARMNEW This bit must transition from 0 to 1 for changes to Register 0x22 and Register 0x23 to take effect. Assuming that this bit was previously set to 0, writing a 1 to this bit causes the readback value of the bit to reflect the state of the chip. (The state of the chip is updated very quickly; for this reason, users with slow SPI implementations may never read back a 0 after an update.) 0 = values have not been updated. 1 = values have been updated. [6:0] Reserved Reserved. Table 36. Channel Gain Registers (Address 0x25 to Address 0x28) Address Register Name Bit Name Description 0x25 Channel 0 gain CHAN0GAIN[7:0] These registers configure a value for the 1.7 multiplier applied to each individual 0x26 Channel 1 gain CHAN1GAIN[7:0] channel just prior to the SUMSCALE block. The range of the channel gain is 0 to 0x27 Channel 2 gain CHAN2GAIN[7:0] 1.9921875 with a step size of 0.0078125. To mute an individual channel, set the 0x28 Channel 3 gain CHAN3GAIN[7:0] scale factor to 0. Setting Channel Gain 00000000 0 00000001 0.0078125 … … 11111111 1.9921875 Table 37. Spectrum Shaping Register (Address 0x29) Bit Name Description [7:1] Reserved Reserved. 0 SPEC_INV Setting this bit to 1 spectrally inverts the signal, effectively multiplying the Q data by −1. Rev. A | Page 35 of 76 AD9789 Table 38. Mu Delay Control 1 Register (Address 0x2F) Bit Bit Name Description 7 SEARCH_TOL This bit specifies the accuracy of the phase search. The optimal value for this bit is 1. 0 = not exact: the search can find a phase within two values of the desired phase. 1 = exact: the search finds the exact phase specified. 6 SEARCH_ERR This bit configures the search behavior when an error is encountered. 0 = stop on error. 1 = retry on error. 5 TRACK_ERR This bit configures the track behavior if the controller does not find the desired phase. The optimal value for this bit is 0. 0 = continue on error. 1 = reset on error. [4:0] GUARDBAND[4:0] These bits set the guard band value. The guard band is defined as follows: GUARDBAND[4:0] × 8 = number of mu delay codes of guard band from the endpoints If the search mode is alternating, the search proceeds in both directions until the guard band is reached in one direction. When the guard band is reached, the search continues only in the opposite direction. If the desired phase is not found before the guard band is reached in the second direction, the search reverts to the alternating mode and continues looking within the guard band. The search fails if the mu delay reaches the endpoints. For more information, see the Mu Delay Controller section. Setting Guard Band 00000 0 … … 01011 11 (default) … … 11111 31 Table 39. Mu Control Duty Cycle Register (Address 0x30) Bit Bit Name Description 7 Duty cycle Setting this bit to 1 turns on the mu control duty cycle correction circuitry. Turn on this function before correct enable enabling the mu controller. Along with the phase comparator boost (enabled in Register 0x3E[5]), this function allows for more robust operation of the mu controller over the entire operating speed of the part. 6 INC_DEC Reserved (factory use only). [5:0] MANUAL_ADJ[5:0] Reserved (factory use only). Table 40. Clock Receiver 1 Register (Address 0x31) Bit Bit Name Description [7:4] CLKN_CML[3:0] These bits adjust the common-mode level at the CLKN pin. The recommended value for these bits and the CLKP_CML[3:0] bits is 0xF. For more information, see the Optimizing the Clock Common-Mode Voltage section. [3:0] Reserved Reserved. Table 41. Clock Receiver 2 Register (Address 0x32) Bit Bit Name Description 7 CLK_DIS This bit disables or enables the clock receiver. When the AD9789 powers up, this bit is set to 0 to prevent severe output noise that occurs on power-up with no clock. When the DAC clock is stable, set this bit to 1. 0 = disabled. 1 = enabled. 6 Reserved Reserved (factory use only; leave at default value). 5 PSIGN This bit specifies the sign for the CLKP_CML bits. 0 = negative (recommended). 1 = positive. [4:1] CLKP_CML[3:0] These bits adjust the common-mode level at the CLKP pin. The recommended value for these bits and the CLKN_CML[3:0] bits is 0xF. For more information, see the Optimizing the Clock Common-Mode Voltage section. 0 NSIGN This bit specifies the sign for the CLKN_CML bits. 0 = negative (recommended). 1 = positive. Rev. A | Page 36 of 76 AD9789 Table 42. Mu Delay Control 2 Register (Address 0x33) Bit Bit Name Description 7 MU_CLKDIS This bit disables or enables the clock to the mu delay controller. 0 = enabled. 1 = disabled. 6 SLOPE This bit configures the desired slope for the phase measurement of the mu delay. When the desired phase is measured, the slope of the phase measurement is calculated and compared to the value of this bit. For optimal ac performance, the best setting for the search is a positive slope and a phase value of 14. 0 = negative. 1 = positive. [5:4] MODE[1:0] These bits configure the mode of operation for the mu controller. 00 = search and track (recommended). 01 = track only. 10 = search only. 11 = invalid. 3 MUSAMP Transitioning this bit from 0 to 1 enables the user to read back the mu delay value that the controller locked to (the MUDLY bits in Register 0x39 and Register 0x3A), as well as the phase that it locked to (the MUPHZ bits in Register 0x39). 0 = no action. 1 = transition from 0 to 1 captures the readback of the mu controller phase and delay. [2:1] GAIN[1:0] These bits set the tracking rate of the mu controller. 00 = slowest tracking. 01 = nominal tracking (recommended). 10 = fastest tracking. 11 = invalid (do not use). 0 MU_EN This bit enables or disables the mu controller. Before enabling the mu controller, turn on both the phase comparator boost (Register 0x3E[5]) and the mu control duty cycle correction circuitry (Register 0x30[7]). Both of these functions allow for more robust operation of the mu controller over the entire operating speed of the part. 0 = mu controller off (manual mode). 1 = mu controller on (auto mode). Table 43. DAC Bias Register (Address 0x36) Bit Bit Name Description 7 PDBIAS Setting this bit to 1 powers down the DAC circuitry. [6:2] Reserved Reserved. [1:0] MSEL[1:0] These bits set the mirror roll-off frequency control, which can be used to adjust the noise contribution of the internal current mirror to optimize the 1/f noise. 00 = bypass the mirror roll-off frequency control. 01 = narrowest bandwidth. 10 = medium bandwidth. 11 = widest bandwidth. Table 44. DAC Decoder Register (Address 0x38) Bit Bit Name Description [7:2] Reserved Reserved. [1:0] DAC decoder These bits set the decoder mode for the DAC. It is recommended that normal mode (the default) be used. mode 00 = normal mode. 01 = return to zero mode. 10 = mix mode. 11 = invalid. Rev. A | Page 37 of 76 AD9789 Table 45. Mu Delay Control 3 Register (Address 0x39) Bit Bit Name Description 7 MUDLY[0] This bit is the LSB of the mu delay value. Along with Bits[7:0] in Register 0x3A, this bit configures the programmable mu delay; the search algorithm begins at this specified mu delay value. In manual mode, the MUDLY bits can be written to. In tracking mode, the sampled MUDLY value can be read back. Even though there are 9 bits of resolution for this delay line value, the maximum allowable mu delay is 431 (0x1AF). The optimal point to begin the search is in the middle of the delay line, or approximately 216 (0xD8). [6:5] SEARCH_DIR[1:0] These bits configure the search direction, starting at the selected mu delay value. 00 = search down. 01 = search up. 10 = search up and down (optimal). 11 = invalid. [4:0] MUPHZ[4:0] These bits specify the phase to be measured with the maximum allowable phase being 16 (10000). If a value larger than 16 is loaded, the controller will not lock. When the desired phase is measured, the slope of the phase measurement is calculated and compared to the configured slope, which is specified by the SLOPE bit in Register 0x33[6]. For optimal ac performance, the best setting for the search is for a positive slope and a phase value of 14 (01110). Table 46. Mu Delay Control 4 Register (Address 0x3A) Bit Bit Name Description [7:0] MUDLY[8:1] Along with Bit 7 in Register 0x39, these bits configure the programmable mu delay; the search algorithm begins at this specified mu delay value. In manual mode, the MUDLY bits can be written to. In tracking mode, the sampled MUDLY value can be read back. Even though there are 9 bits of resolution for this delay line value, the maximum allowable mu delay is 431 (0x1AF). The optimal point to begin the search is in the middle of the delay line, or approximately 216 (0xD8). Table 47. Full-Scale Current 1 Register (Address 0x3C) Bit Bit Name Description [7:0] FSC[7:0] Along with Bits[1:0] in Register 0x3D, this register sets the full-scale current for the DAC. For more information, see the Voltage Reference section. Setting (Includes Register 0x3D[1:0]) Full-Scale Current (mA) 0000000000 8.6 … … 1000000000 20 (default) … … 1011010000 25 … … 1111111111 32.1 Table 48. Full-Scale Current 2 Register (Address 0x3D) Bit Bit Name Description [7:2] Reserved Reserved. [1:0] FSC[9:8] Along with the FSC[7:0] bits in Register 0x3C, these bits set the full-scale current for the DAC. For more infor- mation, see Table 47 and the Voltage Reference section. Table 49. Phase Detector Control Register (Address 0x3E) Bit Bit Name Description 7 PHZ_PD Powers down the phase detector. This bit is for factory use only; this bit should be set to 0. 6 Reserved Reserved. 5 CMP_BST Comparator boost. This bit is for factory use only; this bit should always be set to 1. 4 AUTO_CAL This bit is for factory use only; this bit should always be set to 1. [3:0] PHZ_DET_BIAS[3:0] These bits display the binary weighted current. Do not write to these bits (factory use only). Rev. A | Page 38 of 76 AD9789 THEORY OF OPERATION The AD9789 is a flexible digital signal processing (DSP) engine QAM Encoder combined with a high performance, 2400 MSPS, 14-bit DAC The QAM encoder supports seven different standards-compliant (Figure 70). The DSP blocks include a QAM encoder, a 2× mappings. (For illustrations of the supported mappings, see the upsampling square root raised cosine (SRRC) filter, selectable QAM Constellation Maps section.) The QAM encoder receives interpolation from 16× to 512×, a rate converter, and a complex input data-words of 8 bits in width and maps them into 16, 32, modulator. The digital interface can accept up to four channels 64, 128, or 256 point constellations. It outputs 5-bit complex of complex data. The QAM encoder supports constellation sizes QAM modulated samples. The mode in which the QAM of 16, 32, 64, 128, and 256. The on-chip rate converter allows encoder runs is selected via the QAM/SRRC configuration fine resolution of baud rates with a fixed DAC sampling clock. register (Register 0x07[2:0]). The digital upconverters can place the input signals from dc to 5 I 0.5 × fDAC. An analog mix mode extends the output spectrum 8 QAM FROM INPUT INTERFACE ENCODER into the second and third DAC Nyquist zones. 5 Q Control of the AD9789 functions is via a serial peripheral Figure 72. QAM Encoder I/O interface (SPI). Table 50 lists the available QAM mapper modes along with the QAM/ CMOS corresponding input bits and output range. The operation of the FILTER/ DATA 0TO 15 NCO LVDS 32 INPUT QAM encoder when configured in DOCSIS 64-QAM mode is RISE PINS QAM/ described in this section. The operation of the QAM encoder in AND DATA FILTER/ 2 PARITY 16× NCO the other modes is conceptually the same; only the input data 14-BIT PINS INTERPOLATOR 2.4GSPS AND BPF bit encoding and scale factors are different. CMOS QAM/ DAC + SCALARS 16 TO 31 DATA FILTER/ LVDS NCO The DOCSIS 64-QAM constellation diagram is shown in FALL DCO QAM/ Figure 73. The constellation diagram shows how the QAM SPI IRQ RS DATA FILTER/ FS encoder input is mapped into the QAM constellation. For NCO example, an input data-word of 111111 maps to the constellation Figure 70. Top Level Functional Block Diagram point in the upper right corner of the 64-QAM constellation. DATAPATH SIGNAL PROCESSING C5 C4 C3, C2 C1 C0 The DSP blocks included on the AD9789 can be grouped into Q two sections. The first is the datapath signal processing. Four identical datapaths, or channels, can be used. A block diagram 110,111 111,011 010,111 011,011 100,101 101,111 110,101 111,111 of a single channel is shown in Figure 71. Enabling and disabling each DSP block within the datapath takes effect on all channels. 110,100 111,000 010,100 011,000 100,000 101,010 110,000 111,010 There is independent control of the scaling and the frequency placement of each channel. 100,111 101,011 000,111 001,011 000,101 001,111 010,101 011,111 24-BIT NCO 0TO f /16 QAM DAC SRRC MAPPER 100,100 101,000 000,100 001,000 000,000 001,010 010,000 011,010 RATE I CONVERTER 2 N 2 P/Q 24-BIT 010,011 011,001 000,011 001,001 000,001 001,101 100,001 101,101 (N = 0 TO 5) (P/Q = 0.5 TO 1) BYPASS INSCALE QAM CH GAIN 010,110 011,100 000,110 001,100 000,010 001,110 100,010 101,110 BYPASS 0× TO 2× SRRC Figure 71. Datapath Block Diagram 110,011 111,001 100,011 101,001 010,001 011,101 110,001 111,101 The following sections describe each of the DSP blocks included in the datapath. 110,110 111,100 100,110 101,100 010,010 011,110 110,010 111,110 Figure 73. DOCSIS 64-QAM Constellation Rev. A | Page 39 of 76 150MHz LVDS/CMOS RETIMER DATA FORMATTER/ASSEMBLER 07852-099 07852-129 07852-056 07852-057 AD9789 Table 50. QAM Mapper Input and Output Range vs. Mode ITU-T J.83 SPI Register 0x07, Bit Range Input Bits 1 Annex Description MAPPING[2:0] Bits at Output B7 B6 B5 B4 B3 B2 B1 B0 B DOCSIS 64-QAM 000 −14 to +14 X X C5 C4 C3 C2 C1 C0 B DOCSIS 256-QAM 001 −15 to +15 C7 C6 C5 C4 C3 C2 C1 C0 A DVB-C 16-QAM 010 −15 to +15 X X X X C3 C2 C1 C0 A DVB-C 32-QAM 011 −15 to +15 X X X C4 C3 C2 C1 C0 A and C DVB-C 64-QAM 100 −14 to +14 X X C5 C4 C3 C2 C1 C0 A and C DVB-C 128-QAM 101 −11 to +11 X C6 C5 C4 C3 C2 C1 C0 A and C DVB-C 256-QAM 110 −15 to +15 C7 C6 C5 C4 C3 C2 C1 C0 Unused 111 1 X = don’t care. Each constellation point corresponds to an I and Q coordinate Input Scalar pair, as shown in Figure 74. In the figure, two symbols are high- The input scalar block is active only when the QAM mapper lighted in a 64-QAM constellation: I = 14, Q = 14 (Pair 1) and is bypassed. The value of INSCALE[7:0] is programmed in I = 6, Q = −10 (Pair 2). Register 0x09[7:0]. The scale factor applied to the input data is calculated as follows: To represent the I and Q coordinate points, 5-bit, twos com- plement numbers are used. For example, an input of 011101 INSCALE[7:0] ScaleFactor into the QAM encoder maps to the I = 6, Q = −10 position of 32 the QAM-64 constellation and results in output samples of This factor provides a scaling range of the input data from 0 to I = 00110, Q = 10110. 7.96875 in steps of 0.03125. The default value of 0x20 provides a SYMBOL I = 14, Q = 14 I = 01110, Q = 01110 scale factor of 1. As shown in Figure 76, the output of the input Q scalar block is rounded to the nearest 16-bit value. If the output 14 exceeds the maximum or minimum value, it is clipped to either positive or negative full scale (0x7FFF or 0x8000). 10 ROUND SATURATE 6 8 INSCALE 2 –14 –10 –6 –2 2 6 10 14 Figure 76. Input Scalar Block Diagram I –2 SRRC Filter The square root raised cosine (SRRC) filter performs a 2× –6 interpolation and filtering operation on the input data. The SRRC filter has a pass band, transition band, and stop band –10 requirement as per the DOCSIS, Euro-DOCSIS, and DVB-C standards. –14 To cover all the standards, the value of alpha can be set to 0.12, SYMBOL I = 6, Q = –10 0.13, 0.15, or 0.18. This value is programmed in Register 0x07[5:4]. I = 00110, Q = 10110 The frequency, f , is determined by the input data baud rate. N Figure 74. I and Q Symbol Mapping The response of the SRRC filter is illustrated in Figure 77. The SRRC filter accepts only five bits at its input and can be 8 5 QAM bypassed (Register 0x06[6]). If the SRRC filter is the first block SRRC MAPPER 5 16 enabled in the datapath, these five bits are the five MSBs of the 16 16 2 16 8-bit data-word. X 16 INSCALE BYPASS QAM BYPASS SRRC Figure 75. QAM Mapper and SRRC Filter Detail (I and Q Paths Are Identical So Only One Is Shown) Rev. A | Page 40 of 76 07852-059 07852-058 07852-100 AD9789 10 0 –10 <0.4dB FREQUENCY 0dB –20 –30 <0.4dB –40 –3.01dB –50 –60 <–43dB –70 –80 (1 –α) f f (1 +α) f N N N –90 Figure 77. SRRC Filter Characteristics –100 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 If the SRRC filter is used, at least four of the 2× interpolation FREQUENCY × f (Hz) INPUT filters must be enabled. The reason for this is that the SRRC Figure 80. 2× Half-Band Interpolation Filter 1 Response filter requires a minimum of 12 clock cycles at the f /16 rate DAC per sample to function properly. 10 Half-Band Interpolation Filters 0 The AD9789 can provide from 1× to 32× interpolation through –10 the datapath using five bypassable half-band interpolation filters. –20 The half-band interpolation filters are controlled via Register –30 0x06[4:0]. The preferred order in terms of power savings for –40 bypassing these filters is to bypass Filter 0 first, then Filter 1, –50 and so on. The frequency response of the low-pass filters is –60 shown in Figure 79 through Figure 82. All of the filters have a –70 pass band of 0.8 × fINPUT, where fINPUT is the data rate at the input –80 of each filter. The pass band is flat to within 0.01 dB for all –90 filters. The stop-band attenuation exceeds 85 dB in Filter 0, –100 Filter 1, and Filter 2, and 75 dB in Filter 3 and Filter 4. –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 FREQUENCY × f (Hz) INPUT 2 0 Figure 81. 2× Half-Band Interpolation Filter 2 Response 1 10 0 BYPASS REGISTER 0x06[4:0] –10 Figure 78. Conceptual Block Diagram of 2× Half-Band Interpolation Filters –20 10 –30 0 –40 –10 –50 –20 –60 –30 –70 –40 –80 –50 –90 –60 –100 –1.875 –1.250 –0.625 0 0.625 1.250 1.875 –70 FREQUENCY × f (Hz) INPUT –80 Figure 82. 2× Half-Band Interpolation Filter 3 and Filter 4 Response –90 –100 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 FREQUENCY × f (Hz) INPUT Figure 79. 2× Half-Band Interpolation Filter 0 Response Rev. A | Page 41 of 76 MAGNITUDE (dB) 07852-101 07852-102 07852-060 MAGNITUDE (dB) MAGNITUDE (dB) MAGNITUDE (dB) 07852-105 07852-104 07852-103 AD9789 Sample Rate Converter Example The purpose of the sample rate converter (SRC) is to provide A DOCSIS application has a master system clock that runs at a increased flexibility in the ratio of the input baud rate to the frequency of fMASTER. Several channel baud rates are supported, DAC update rate. Each of the four channelization datapaths all of which are fractions of the master clock and can be contains a sample rate converter (SRC) that provides a data rate represented by the following equation: conversion in the range of 0.5 to 1.0 inclusive. The rate conversion M factor is set by the ratio of two 24-bit values, P and Q. Figure 83 f = × f (4) BAUD MASTER N is a conceptual block diagram of the SRC. It can be thought of Equation 1 must be satisfied for f to be exactly maintained. BAUD as an interpolation block, followed by filtering and decimation To facilitate this, the DAC sampling frequency is selected to be a blocks. multiple of fMASTER that satisfies the signal bandwidth and output frequency requirements. For fMASTER = 10.24 MHz, a signal band- P Q width requirement of 32 MHz or greater, and a supported output frequency band of up to 1 GHz, the following DAC sampling 24 24 frequency can be selected: PQ Figure 83. Conceptual Block Diagram of the Sample Rate Converter f = 224× f = 2293.76 MHz (5) DAC MASTER The values of P and Q are set by programming the P[23:0] and Inserting Equation 4 and Equation 5 into Equation 1 results in Q[23:0] registers at Address 0x16 through Address 0x1B. Equation 6. Table 51. Register Locations for Sample Rate Converter P M 224× f = I× ×16× × f (6) MASTER MASTER Bits Numerator (P) Denominator (Q) Q N [23:16] (Byte 2) Register 0x1B Register 0x18 Enabling the SRRC filter and four of the half-band interpolation [15:8] (Byte 1) Register 0x1A Register 0x17 filters would result in the total interpolation factor, I, being equal [7:0] (Byte 0) Register 0x19 Register 0x16 to 32. Substituting 32 for I and simplifying Equation 6 results in Equation 7. The values of P and Q should be selected to satisfy the following P N 7 equation for the desired baud rate (fBAUD) and DAC clock fre- = × (7) Q M 16 quency (f ). DAC Recall that N and M are given by the required baud rate. For P f = I× ×16 × f (1) example, assume a baud rate of 5.0569 MHz, which results from DAC BAUD Q M = 401 and N = 812. where I is the total interpolation ratio of the SRRC filter and the 401 five half-band interpolation filters. f = ×10.24 MHz= 5.0569 MHz (8) BAUD 812 If Equation 1 is satisfied, the long-term baud rate, f , is BAUD P and Q can then be calculated from the numerator and exactly maintained. No residual frequency offset errors are denominator of Equation 9. introduced by the rate conversion process. P 812 7 5684 0x1634 The values of P and Q must be selected within the following = × = = (9) Q 401 16 6416 0x1910 constraints: Because the value of Q must be MSB justified, both numbers P 0.5≤ ≤ 1.0 (2) can be shifted by 11 bits, resulting in the final P and Q values Q of 0xB1A000 and 0xC80000, respectively. Q[23] = 1 (3) Baseband Digital Upconverter Equation 3 states that the value of Q must be shifted so that the The digital upconverter enables each baseband channel to be MSB of Q is set. placed anywhere from dc to fDAC/16. The center frequency for In most systems, the baud rate is a given, and the DAC sample each of the four channels is register programmable through the rate is selected so that it is high enough to support the signal 24-bit frequency tuning words, FTW 0 through FTW 3. For the bandwidth and output frequency requirements. In many cases, desired center frequency of each individual channel, the FTW it is desirable to set the DAC clock rate to a multiple of a system can be calculated as follows: clock rate. The following example shows how P and Q can be f CENTER 24 selected in such a system. () FTW= × 2 −1 f ⎛ ⎞ DAC ⎜ ⎟ 16 ⎝ ⎠ Rev. A | Page 42 of 76 07852-106 AD9789 The calculated FTW for each channel should be entered into DIGITAL BLOCK UPCONVERTER the register locations listed in Table 52. The second half of the DSP engine on the AD9789 combines the outputs of the four datapaths into one block, scales the block of Table 52. Register Locations of FTWs for Each Channel channels, interpolates by 16× to the full DAC rate, and performs FTW Channel 0 Channel 1 Channel 2 Channel 3 a band-pass filter operation allowing the block of channels to be [23:16] Reg. 0x0C Reg. 0x0F Reg. 0x12 Reg. 0x15 placed anywhere in the Nyquist bandwidth of the DAC. [15:8] Reg. 0x0B Reg. 0x0E Reg. 0x11 Reg. 0x14 DATA- [7:0] Reg 0x0A Reg 0x0D Reg 0x10 Reg 0x13 DIGITAL BLOCK PATH UPCONVERTER 0 The FTW sets the frequency of the sine and cosine signals DATA- generated by the numerically controlled oscillator (NCO). PATH 1 The complex output from the NCO is multiplied by the input BPF f = 0 TO C datapath signal to modulate the signal to the desired output DATA- f DAC/2 PATH frequency. A conceptual block diagram of the baseband digital 2 SUM upconverter is shown in Figure 84. SCALE DATA- PATH BPF 3 f C SIN Figure 86. Functional Block Diagram of the Digital Block Upconverter COS Each block of the digital block upconverter is described in more 24 detail in the following sections. FTW NCO FREQUENCY TUNING WORD Summing Junction Scalar Figure 84. Conceptual Block Diagram of the Baseband Digital Upconverter The summing junction scalar block operates on the sum of the Individual Channel Scalar four channels. The value of SUMSCALE[7:0] is programmed in Register 0x08. The scale factor applied to the data is calculated The last block in the datapath is an 8-bit scalar (Register 0x25 to as follows: Register 0x28) intended for compensating out any sampling and hardware roll-offs that may be encountered. The scale factor SUMSCALE[7:0] applied to each channel is calculated as follows: ScaleFactor= 64 CHANxGAIN[7:0] This factor provides a scaling range of the input data from 0 to ScaleFactor= 128 3.984375 with a step size of 0.015625. The default value of 0x0D The range of the channel gain is 0 to 1.9921875 with a step size provides a scale factor of 0.203125. Note that when the channels of 0.0078125. An individual channel can be easily and quickly are summed, they are clipped at the output of the summing junction scalar block if the value exceeds the maximum or muted, if desired, by setting the scale factor to 0. minimum full-scale value (0x7FFF or 0x8000). If the full 16-bit Table 53. Register Locations for Channel Gain Scalar range of each individual channel is used, the sum scalar should CHANxGAIN Channel 0 Channel 1 Channel 2 Channel 3 be set to 0x10 (0.25) to avoid the possibility of clipping. [7:0] Reg. 0x25 Reg. 0x26 Reg. 0x27 Reg. 0x28 TO SATURATION COUNTER SATERR The default value of the channel gain provides a scale factor of REGISTER 0x03[1] 1. As shown in Figure 85, the output of the input scalar block is rounded to the nearest 16-bit value. If the output exceeds the ROUND maximum or minimum value, it is clipped to either positive or SATURATE negative full scale (0x7FFF or 0x8000). 8 ROUND SUMSCALE SATURATE REGISTER 0x08 8 Figure 87. Block Diagram of the Summing Junction Scalar In practice, the signal-to-noise ratio (SNR) of the channel can CHANxGAIN[7:0] be improved by increasing the sum scale factor and permitting Figure 85. Individual Channel Gain Control a small amount of clipping. The larger signal amplitude can improve the SNR if the clipping is brief and infrequent. Rev. A | Page 43 of 76 07852-107 07852-108 16× INTERPOLATOR 07852-110 07852-109 AD9789 Table 54 shows recommended sum scale values for each QAM should be taken to appropriately filter the desired signal with mapper mode. The criteria used to determine the recommended the interpolation filters prior to the input of the BPF.. sum scale values were MER/EVM measurements and spectral 0 purity. Because clipping results in impulsive noise, it can be observed in the output spectrum as a transient increase in the –20 output noise floor. These sum scale values were chosen such that the transient increases in the noise floor were minimal. –40 These tests were completed for one, two, three, and four carrier outputs at approximately 850 MHz. Because clipping can occur in the RF chain following the DAC, further verification of these –60 values should be performed at the system level by adding BER tests to the sum scale selection criteria. –80 Table 54. Recommended Sum Scale Values for all QAM Mapper Modes and Channel Count –100 0 0.5 1.0 1.5 2.0 Sum Scale Value (Decimal) QAM FREQUENCY (GHz) Mode 1 Channel 2 Channels 3 Channels 4 Channels Figure 89. Band-Pass Filter Response at 200 MHz, fDAC = 2.4 GHz DVB-C 48 28 22 16 16-QAM DVB-C 54 34 26 20 0 32-QAM DVB-C 54 34 26 20 64-QAM –20 DVB-C 80 50 38 30 128-QAM –40 DVB-C 54 34 26 20 256-QAM DOCSIS 54 34 26 20 –60 64-QAM DOCSIS 54 34 26 20 –80 256-QAM Digital 16× Tunable Band-Pass Filter –100 0 0.5 1.0 1.5 2.0 The digital band-pass filter works in conjunction with a fixed FREQUENCY (GHz) 16× interpolator (see Figure 88). The 16× interpolation filter Figure 90. Band-Pass Filter Response at 1 GHz, f = 2.4 GHz DAC creates 16 images of the baseband signal in the Nyquist band of the DAC. The digital band-pass filter must then be tuned to reject the 15 undesired images. The center frequency of the 0 band-pass filter can be placed anywhere from dc to f /2. The DAC tuning word for the band-pass filter center frequency can be calculated as follows: –2 f CENTER 16 BPF_Center_Freq  2 1 –4 f DAC –6 The resulting tuning word is a 16-bit value where the most significant byte is written to Register 0x1D[7:0] and the least significant byte is written to Register 0x1C[7:0]. –8 16 –10 020 40 60 80 16 FREQUENCY (MHz) f C Figure 91. Band-Pass Filter Pass-Band Detail, fDAC = 2.4 GHz Figure 88. Conceptual Block Diagram of 16× Tunable Band-Pass Filter The width of the filter’s stop band is fixed at approximately f /64. The effective FLAT pass band is f /64. As can be DAC DAC inferred from Figure 89 to Figure 91, mistuning of the BPF center frequency can result in unwanted images appearing. Care Rev. A | Page 44 of 76 07852-111 MAGNITUDE (dB) MAGNITUDE (dB) MAGNITUDE (dB) 07852-064 07852-063 07852-062 AD9789 f DAC DIGITAL INTERFACE MODES 16 TO 1024 The AD9789 can be configured for two main digital interface DATA- CMOS UP TO PATH modes of operation: 0TO 15 32 BITS 0 LVDS f DAC f DAC RISE • Channelizer mode DATA- 16 UP TO PATH • Quadrature digital upconverter (QDUC ) mode 32 BITS 1 BPF f = 0 TO C In channelizer mode (Register 0x20[3] = 0), the interface can be CMOS DATA- UP TO f 16 TO 31 DAC/2 PATH 32 BITS configured for 4- to 32-bit bus widths and can accept up to four LVDS 32 2 FALL SUM P0 channels of complex data. Any of the signal processing blocks in SCALE DATA- P1 UP TO PATH BPF the digital datapath can be used. The maximum baud rate 32 BITS FS CLK 3 f C DCO CTL supported in channelizer mode is f /48. DAC Figure 92. Channelizer Mode In QDUC mode (Register 0x20[3] = 1), the interface is fixed at a 32-bit bus width and one channel of complex data. The available Table 55. Interface Configurations Supported signal processing methods are interpolation (16× to 512×), rate in Channelizer Mode conversion (0.5 to 1.0), and complex modulation. The maximum First Input Bus Width Data Width Data Format baud rate supported in QDUC mode is f /16. Block Enabled Reg. 0x21[6:5] Reg. 0x21[4] Reg. 0x21[3] DAC QAM Encoder 32 bits 8 bits Real In both channelizer and QDUC modes, the input data bus 16 bits 8 bits Real can be configured to accept LVDS or CMOS data via the 8 bits 8 bits Real CMOS_BUS pin (L14). If CMOS_BUS is pulled to 3.3 V, the 4 bits 8 bits Real data bus is configured to accept CMOS inputs (D[31:0], P0, SRRC Filter 32 bits 8 bits Complex and P1). If CMOS_BUS is pulled to 0 V, the bus is configured 16 bits 8 bits Complex to accept LVDS inputs (D[15:0]P, D[15:0]N, PARP, and PARN). 8 bits 8 bits Complex Two output signals are used to source data into the AD9789. 4 bits 8 bits Complex The first is the data clock output signal (DCO), which is Interpolation 32 bits 16 bits Complex provided to clock data from the digital data source. DCO is a Filter 16 bits 16 bits Complex divided-down version of DACCLK. The second is the frame sync 8 bits 16 bits Complex signal (FS), which is provided to request a new data-word. The average frequency of the FS signal is equal to the symbol rate or If the QAM encoder is the first block enabled in the datapath, baud rate of the data. As with the input data bus, the DCO and the data width should be set to an 8-bit word and real data FS signals can be configured as LVDS or CMOS outputs via the format. If the SRRC filter is the first block enabled in the CMOS_CTRL pin (M14). If CMOS_CTRL is pulled to 3.3 V, datapath, the data width should be set to an 8-bit word and DCO and FS are output as CMOS signals on the P14 and N14 complex data format. If both the QAM encoder and the SRRC pins (CMOS_DCO and CMOS_FS), respectively. If CMOS_CTRL filters are bypassed, the data width should be set to a 16-bit is pulled to 0 V, DCO and FS are output as LVDS signals on the word and complex data format. N13, P13, L13, and M13 pins (DCOP, DCON, FSP, and FSN), Pin Mapping in Channelizer Mode respectively. In CMOS mode (CMOS_BUS and CMOS_CTRL pins = 3.3 V), Channelizer Mode the various interface width options are mapped to the AD9789 In channelizer mode, the digital interface has programmable input pins as shown in Table 56. bus width, data width, and data format. The bus width, which is Table 56. CMOS Pin Assignments for Various Interface Widths the physical width of the digital data bus at the input of the AD9789, can be set to a 4-, 8-, 16-, or 32-bit wide interface. The Interface Width Pin Assignments BUSWDTH[1:0] data width, which is the internal width of the data at the input 4 bits D[3:0] 00 to the digital datapath, can be set to an 8-bit or 16-bit word. The 8 bits D[7:0] 01 data format can be programmed for real or complex data. A list 16 bits D[15:0] 10 of supported interface modes is shown in Table 55. 32 bits D[31:0] 11 Rev. A | Page 45 of 76 32 INPUT PINS LVDS/CMOS RETIMER 4 TO 32 BITS PROGRAMMABLE DATA FORMATTER/ASSEMBLER 16× INTERPOLATOR 07852-112 AD9789 In LVDS mode, the various interface width options are mapped Example 3 to the AD9789 input pins as shown in Table 57. When the inter- For an LVDS interface with a 16-bit bus width, 8-bit data width, face width is set to 32 bits in LVDS mode, the interface becomes complex data format, and four channels enabled, the data in double data rate (DDR). In DDR mode, the first 16 bits are Table 60 is expected on the input port after data is requested. sampled on the rising edge of the data sampling clock (DSC, which is synchronous to DCO), and the second 16 bits are Table 60. LVDS Pin Mapping for Bus Width = 16 Bits, 1 sampled on the falling edge of DSC. All other interface widths Data Width = 8 Bits, Data Format = Complex, Four Channels are single data rate (SDR), where the input data is sampled on DCO D[15:8]P, D[15:8]N D[7:0]P, D[7:0]N the falling edge of DSC. 1 Q0 I0 2 Q1 I1 Table 57. LVDS Pin Assignments for Various Interface Widths 3 Q2 I2 Interface Width Pin Assignments BUSWDTH[1:0] 4 Q3 I3 4 bits D[3:0]P, D[3:0]N 00 1 I represents the in-phase term and Q represents the quadrature term of the 8 bits D[7:0]P, D[7:0]N 01 complex data loaded to a given channel; the channel number follows I or Q. 16 bits D[15:0]P, D[15:0]N 10 Example 4 32 bits 11 D[15:0]P, D[15:0]N rising For an LVDS interface with a 32-bit bus width, 8-bit data width, edge and falling edge complex data format, and four channels enabled, the data in In nibble or byte loading, the most significant nibble or byte Table 61 is expected on the input port after data is requested. should be loaded first. Data for Channel 0 should be loaded first followed by Channel 1, Channel 2, and Channel 3. In complex Table 61. LVDS Pin Mapping for Bus Width = 32 Bits, 1 data format, the in-phase part should be loaded before the Data Width = 8 Bits, Data Format = Complex, Four Channels quadrature part of the data-word. The data bus is LSB justified 2 DCO D[15:8]P, D[15:8]N D[7:0]P, D[7:0]N when the data for each channel is assembled internally. A few 1 rise Q0 I0 examples of how the interface maps for different configurations 1 fall Q1 I1 follow. For more information on how a particular configuration 2 rise Q2 I2 is mapped, see the Channelizer Mode Pin Mapping for CMOS 2 fall Q3 I3 and LVDS section. 1 I represents the in-phase term and Q represents the quadrature term of the complex data loaded to a given channel; the channel number follows I or Q. Example 1 2 “Rise” means that the data is sourced on the rising edge of DCOx; “fall” means For a CMOS interface with a 32-bit bus width, 8-bit data width, that the data is sourced on the falling edge of DCOx. real data format, and four channels enabled, the data in Table 58 DCO and FS Rates in Channelizer Mode is expected on the input port after data is requested. The DCO signal is a data clock output provided to clock data from the digital data source. The DCO is a divided version of Table 58. CMOS Pin Mapping for Bus Width = 32 Bits, 1 the DAC clock. The FS signal is an output provided to request a Data Width = 8 Bits, Data Format = Real, Four Channels new data-word. The average frequency of the FS signal (f ) is FS DCO D[31:24] D[23:16] D[15:8] D[7:0] exactly equal to the symbol rate or baud rate (f ) of the data. BAUD 1 R3 R2 R1 R0 FS is intended as a request line; timing should be taken from the 1 R represents the real data loaded to a given channel; the channel number DCO. The frequencies of the DCO signal (fDCO), the baud rate follows R. (fBAUD), and the DAC clock (fDAC) are related as shown by the Example 2 following two equations: For a CMOS interface with a 32-bit bus width, 8-bit data width, P complex data format, and four channels enabled, the data in f = I× × 16× f (1) DAC BAUD Q Table 59 is expected on the input port after data is requested. fDCO = fDAC /(16 × N) (2) Table 59. CMOS Pin Mapping for Bus Width = 32 Bits, 1 where: Data Width = 8 Bits, Data Format = Complex, Four Channels I is the interpolation factor, which can range from 1 to 64. DCO D[31:24] D[23:16] D[15:8] D[7:0] P/Q is the rate conversion factor (0.5 to 1.0, inclusive). 1 Q1 I1 Q0 I0 N is a programmable DCO divide factor set using the 2 Q3 I3 Q2 I2 DCODIV[2:0] bits in Register 0x22[6:4]. 1 I represents the in-phase term and Q represents the quadrature term of the complex data loaded to a given channel; the channel number follows I or Q. Set DCODIV[2:0] to 1, 2, or 4. A value of 0 disables the DCO. A DCODIV value of 3 is not functional. The frequency of the DSC signal is always equal to DCO. Rev. A | Page 46 of 76 AD9789 Before choosing an interface configuration, divide the frequency If the number of channels enabled is always less than four and of DCO by the highest frequency baud rate that will be used in the user does not plan to enable and disable channels dynamically, the system and truncate it. The result is the number of available setting channel prioritization to 0 is the best choice because DCO cycles (cycles ) between FS pulses. fewer clocks and/or pins are required to transfer the input data. AVAIL An example of channel prioritization set to 0 is shown in Table 62. ⎛ f ⎞ DCO ⎜ ⎟ cycles = floor AVAIL In this example, the data interface is configured for CMOS with ⎜ ⎟ max f ⎝ BAUD⎠ 32-bit bus width, 8-bit data width, and real data format. Each interface configuration requires a particular number of Table 62. Input Mapping vs. Enabled Channels, DCO cycles between FS pulses to successfully load data into all Channel Prioritization = 0 channels. This number can be calculated using the following CMOS Bit Mapping formula: Channels [D31:D24] [D23:D16] [D15:D8] [D7:D0] DW 4 Channels Channel 3 Channel 2 Channel 1 Channel 0 cycles = N× F× INTERFACE BW Enabled Channel 0 Channel 3 Channel 2 Channel 1 where: Disabled N is the number of channels enabled (1 to 4). N is always equal Channel 0, Channel 3 Channel 1 to 4 if channel prioritization is set to 1 (see the Channel Channel 2 Prioritization section). Disabled F represents the data format. If the data format is real, F = 1; The same example behaves differently when channel prioritization if the data format is complex, F = 2. is set to 1, as shown in Table 63. DW is the data width in number of bits (8 or 16). BW is the bus width in number of bits (4, 8, 16, or 32). Table 63. Input Mapping vs. Enabled Channels, Channel Prioritization = 1 For a successful interface design, the number of DCO cycles CMOS Bit Mapping between FS pulses must be greater than the number of DCO Channels [D31:D24] [D23:D16] [D15:D8] [D7:D0] cycles required by the interface. 4 Channels Channel 3 Channel 2 Channel 1 Channel 0 Design Example Enabled In this example, a system has the baud rate f = 6.4 MHz. If a Channel 0 Channel 3 Channel 2 Channel 1 FS Disabled 4-bit-wide interface is desired for four channels with real data Channel 0, Channel 3 Channel 1 format and a data width of 8 bits, the selected fDCO should be at Channel 2 least 8 × fFS. First, using Equation 1 and Equation 2, evaluate the Disabled interface speed with N = 1, P/Q = 0.7, and I = 32. Quadrature Digital Upconverter (QDUC) Mode f = 32 × 0.7 × 16 × 6.4 MHz = 2293.76 MHz DAC In QDUC mode (Register 0x20[3] = 1), the data interface is fixed f = 2293.76 MHz/(16 × 1) = 143.36 MHz DCO at a 32-bit bus width, 16-bit data width, and complex data format. The f /f ratio = 22.4. If a value of N = 2 is selected, the DCO BAUD In QDUC mode, only one channel should be enabled. If more number of available DCO cycles is reduced to 11; this option than one channel is enabled, identical I and Q data is sent to may not be feasible when the latency values are taken into each enabled channel. Within the datapath, the QAM mapper account. See the Latency Effects on Channelizer Mode section and the SRRC filter must be bypassed (Register 0x06[7:6] = 11). for more information about latency. Channel Prioritization CMOS IAND Q ON I 0TO 15 16 BITS LVDS When channels are enabled and disabled, the input interface 32 RISE mapping can be affected. If channel prioritization (Register INPUT IAND Q OFF PINS 16 BITS BPF 0x20[2]) is set to 0, the device expects input samples for only f = C the channels that are enabled. In this configuration, the physical 0TO f /2 IAND Q CMOS DAC channel mapping at the DUT input can move around based on OFF Q 16 BITS 16 TO 31 the number of channels enabled, where Channel 0 has highest LVDS FALL P0 BPF priority (it never moves location when enabled). If channel P1 f IAND Q C OFF 16 BITS prioritization is set to 1, data is expected for all four channels FS DCO but the data is ignored internally if the channel is disabled. Figure 93. QDUC Mode This method is recommended because enabling and disabling channels does not shift the input data bus. Rev. A | Page 47 of 76 LVDS/CMOS 16× INTERPOLATOR 07852-069 AD9789 11 24 3 5 6 7 89 10 11 12 134 Pin Mapping in QDUC Mode A In CMOS mode, the AD9789 input pins are mapped as shown B in Table 64. C Table 64. Pin Mapping in QDUC Mode for CMOS Interface D Data Bit Description Pin No. E D31 MSB of I data L5 F D16 LSB of I data P8 G D15 MSB of Q data L9 H D0 LSB of Q data P12 J PARP P1 Parity for D[31:16] L4 FSP K PARN P0 Parity for D[15:0] M4 FSN L P+ 15 13 11 9 7 53 1 FS DCOP P– 15 13 11 9 53 1 FS M 7 DCON N 14 12 10 8 6 4 2 0 DC 11 24 3 5 6 7 89 10 11 12 134 P 14 12 10 8 6 4 2 0 DC A B 14 +LVDS 14 –LVDS C Figure 95. LVDS Data Input Pin Mapping D DCO and FS Rates in QDUC Mode E In QDUC mode, DCODIV should always be set to 1 (Register F 0x22[6:4] = 001). The clock period of DCO is equal to 16 DAC G clock periods. When only 16× interpolation is required and the H rate converter is not used, the data rate of the interface is equal J to f . DCO K L P1 31 27 23 19 15 11 7 3 BU CMOS_BUS If further interpolation or rate conversion is enabled in the P0 CT M 30 26 22 18 14 10 6 2 CMOS_CTRL datapath, the data rate of the interface is fBAUD. The average rate N 29 25 21 17 13 9 5 1 FS CMOS_FS of FS, fFS, is equal to the baud rate, fBAUD. The baud rate can be 28 24 20 16 12 8 4 0 DC P CMOS_DCO specified by the following equation: f D[31:0] CMOS DATA INPUTS DCO f = BAUD P PARITY AND CONTROL INPUTS N 2 × Q Figure 94. CMOS Data Input Pin Mapping In LVDS mode, the AD9789 input pins are mapped as shown in where: Table 65. N is the number of 2× interpolation filters enabled. P/Q is the rate converter ratio. 1 Table 65. Pin Mapping in QDUC Mode for LVDS Interface The FS signal becomes a request for data that effectively gates the Data Bit Description Pin No. DCO clock and ensures that data is sent at the correct baud rate. D15P, D15N rising MSB of I data L5, M5 If P/Q = 1 and N = 0, DCO occurs at the baud rate and FS is not D0P, D0N rising LSB of I data N12, P12 required. In this case, FS is inactive (always high). The DCO D15P, D15N falling MSB of Q data L5, M5 signal can be used as a constant rate clock to request samples D0P, D0N falling LSB of Q data N12, P12 from the data source. PARP, PARN rising Parity for D[15:0]P, D[15:0]N L4, M4 rising PARP, PARN falling Parity for D[15:0]P, D[15:0]N L4, M4 falling 1 “Rising” means that the data is sourced on the rising edge of DCOx; “falling” means that the data is sourced on the falling edge of DCOx. Rev. A | Page 48 of 76 07852-113 07852-114 AD9789 DCO 7 DCO CYCLES 6 DCO CYCLES 7 DCO CYCLES FS t t t PD PD PD SAMPLE SAMPLE SAMPLE D[31:0] 0 1 2 DSC Figure 96. QDUC Mode Interface Timing Diagram for Design Example When FS Is Active 16 16 Design Example 16 Q Q Q LVDS BITS D D D DATA 0TO 15 In this example, a system has a DAC rate of 1600 MHz and a CLK CLK CLK baud rate of 15 MHz. Because fDCO = fDAC/16 = 100 MHz, the 16 16 16 Q Q Q Q ratio of fDCO/fFS = 6.667. To satisfy the requirement that P/Q be BITS D D D D 16 TO 31 between 0.5 and 1.0, an additional interpolation factor of 8× CLK CLK CLK CLK must be applied, so N = 3. Solving for P/Q results in 5/6. DSC Φ 0TO 15 Therefore, three out of every 20 DCO clock edges should SNC Φ 0TO 13 result in data samples being loaded into the device (the ratio PHZ of f /f = 3/20). Figure 96 shows a timing diagram that Φ 15 FS DCO Figure 98. LVDS Rearranges the DSC Register illustrates the operation of the interface in this example. In the timing diagram, tPD corresponds to the propagation delay Register 0x23 and Register 0x21[2:0] can provide timing adjust- between the rising edge of FS and when the first sample in a ments with very low jitter penalty, but they can also be set to the given transmission is sampled into the AD9789. Note that tPD following recommended safe values: can vary by more than 1 DCO cycle. • In LVDS mode, DSCPHZ = 0, SNCPHZ = 3, LTNCY = 0 Retimer Operation (see the Latency Register section) The AD9789 uses a three-register retimer. The first two registers • In CMOS mode, DSCPHZ = 0, SNCPHZ = 7, LTNCY = 0 are clocked from any one of 16 phases derived from the DAC (see the Latency Register section) clock. The clock for the last register is fixed to Phase 15. The Timing adjustments can then be made in an FPGA or other programmable register clocks are the digital sample clock (DSC) data source. and the synchronizer clock (SNC). By choosing different phases, fine adjustment of the sampling time can be made to Note that selecting Phase 14 or Phase 15 for SNCPHZ results in adjust for delays in the data source. Register 0x23[7:4] sets the a timing violation. In CMOS mode, setting DSCPHZ one step DSC phase (DSCPHZ) and Register 0x23[3:0] sets the SNC behind or at SNCPHZ also results in a timing violation. phase (SNCPHZ) to any one of the 16 phases. The last register Latency Register in the chain is always clocked from Phase 15. A latency register, controlled via Register 0x21[2:0], follows the The parity counters can aid in identifying the edges of the data three-register retimer and can delay the data up to seven DCO valid windows. Operation in CMOS mode is quite similar to oper- clocks in steps of one DCO clock. The critical retiming is ation in LVDS mode, as can be seen in Figure 97 and Figure 98. already done in the first three registers, so an incorrect latency 32 32 value does not result in a timing violation. The latency value 32 Q Q Q BITS CMOS D D D 0TO 31 determines which data sample is the first sample in a trans- DATA CLK CLK CLK mission and routes that sample to the appropriate channel. DSC Φ 0TO 15 Latency is affected by the round-trip delay from when FS goes SNC high to when the first data sample is output from the retimer. If Φ 0TO 13 the latency value programmed into the part is incorrect, the PHZ Φ 15 input data samples will not be assembled properly. Figure 97. CMOS Retiming Registers Rev. A | Page 49 of 76 07852-070 07852-071 07852-115 AD9789 012345678 1624 3240 4856 6472 DCO FS LVDS DDR SAMPLE SAMPLE SAMPLE SAMPLE SAMPLE SAMPLE SAMPLE SAMPLE SAMPLE SAMPLE LVDS SDR SAMPLE SAMPLE SAMPLE SAMPLE SAMPLE CMOS SAMPLE SAMPLE SAMPLE SAMPLE SAMPLE Figure 99. Sampling Points at Delay = 0 Retimer and Latency Look-Up Tables For LVDS DDR, In practice, the retimer and latency parameters can be reduced Delay + 1.6 ns MEASURED Delay = + 16 OPTIMAL to a single verified and guaranteed table that provides delays at t /16 DCO optimum sample points from 0 to over 100 DAC clocks. The For LVDS SDR, sampling points for LVDS DDR, LVDS SDR, and CMOS inter- face modes are given in Figure 99 for delay = 0. The number Delay +1.6 ns MEASURED Delay = + 8 scale above the DCO signal in Figure 99 corresponds to the OPTIMAL t /16 DCO delay value in DAC clock cycles in Table 66 and Table 67. For CMOS, The delay of the pins should be taken into account. This delay is 800 ps for the output delay and 800 ps for the input delay, for a Delay +1.6 ns MEASURED Delay = + 8 OPTIMAL total of 1.6 ns. This delay is included in the following formulas. t /16 DCO See Table 66 for a complete set of recommended retimer settings For a maximum valid sampling window, the sampling point for all delay values. Note: for LVDS DDR, zero (0) measured delay should be fine-tuned based on the data input setup and hold results in a retimer setting of 20, while for .LVDS SDR or CMOS, times. If the setup and hold times are symmetric about the the zero(0) delay corresponds to a retimer setting of 12 at fDAC = DCO edge, choosing a sampling point at the center of the data 2.4 GHz. window results in the maximum valid sampling window. For To use Table 66 and Table 67, probe the FS, DCO, and data more information on the input data setup and hold times, refer input signals at the AD9789. While viewing these signals on an to the CMOS Interface Timing section or the LVDS Interface oscilloscope, measure the delay between the rising edge of FS Timing section. and the start of the first data sample and add 1.6 ns from the The LAT, SNC, and DSC values for the optimal sampling point in delay of the pins to this value. Normalize this total delay to one Table 66 or Table 67 should be written to the LTNCY[2:0] bits in DAC clock period. The optimum sampling point in number of Register 0x21[2:0], the SNCPHZ[3:0] bits in Register 0x23[3:0], DAC clock cycles, which corresponds to the delay number in and the DSCPHZ[3:0] bits in Register 0x23[7:4], respectively. Table 66 and Table 67, can be found from this measured value for each interface mode. Rev. A | Page 50 of 76 07852-116 AD9789 Delay 96 97 98 99 100 101 102 103 Table 66. Recommended Retimer Settings for All Delay LAT 6 6 6 6 6 6 7 7 Values, LVDS Mode SNC 7 8 9 9 10 10 2 3 Delay 0 1 2 3 4 5 6 7 DSC 8 9 10 11 12 13 14 15 LAT 0 0 0 0 0 0 1 1 Delay 104 105 106 107 108 109 110 111 SNC 7 8 9 9 10 10 2 3 LAT 7 7 7 7 7 7 7 7 DSC 8 9 10 11 12 13 14 15 SNC 3 4 4 5 5 6 6 7 Delay 8 9 10 11 12 13 14 15 DSC 0 1 2 3 4 5 6 7 LAT 1 1 1 1 1 1 1 1 Delay 112 113 114 115 116 117 X X SNC 3 4 4 5 5 6 6 7 LAT 7 7 7 7 7 7 X X DSC 0 1 2 3 4 5 6 7 SNC 7 8 9 9 10 10 X X Delay 16 17 18 19 20 21 22 23 DSC 8 9 10 11 12 13 X X LAT 1 1 1 1 1 1 2 2 SNC 7 8 9 9 10 10 2 3 DSC 8 9 10 11 12 13 14 15 Table 67. Recommended Retimer Settings for All Delay Delay 24 25 26 27 28 29 30 31 Values, CMOS Mode LAT 2 2 2 2 2 2 2 2 Delay 0 1 2 3 4 5 6 7 SNC 3 4 4 5 5 6 6 7 LAT 0 0 0 0 0 0 1 1 DSC 0 1 2 3 4 5 6 7 SNC 7 8 8 9 9 2 2 3 Delay 32 33 34 35 36 37 38 39 DSC 0 1 2 3 4 5 6 7 LAT 2 2 2 2 2 2 3 3 Delay 8 9 10 11 12 13 14 15 SNC 7 8 9 9 10 10 2 3 LAT 1 1 1 1 1 1 1 1 DSC 8 9 10 11 12 13 14 15 SNC 3 4 4 5 5 6 6 7 Delay 40 41 42 43 44 45 46 47 DSC 8 9 10 11 12 13 14 15 LAT 3 3 3 3 3 3 3 3 Delay 16 17 18 19 20 21 22 23 SNC 3 4 4 5 5 6 6 7 LAT 1 1 1 1 1 1 2 2 DSC 0 1 2 3 4 5 6 7 SNC 7 8 8 9 9 2 2 3 Delay 48 49 50 51 52 53 54 55 DSC 0 1 2 3 4 5 6 7 LAT 3 3 3 3 3 3 4 4 Delay 24 25 26 27 28 29 30 31 SNC 7 8 9 9 10 10 2 3 LAT 2 2 2 2 2 2 2 2 DSC 8 9 10 11 12 13 14 15 SNC 3 4 4 5 5 6 6 7 Delay 56 57 58 59 60 61 62 63 DSC 8 9 10 11 12 13 14 15 LAT 4 4 4 4 4 4 4 4 Delay 32 33 34 35 36 37 38 39 SNC 3 4 4 5 5 6 6 7 LAT 2 2 2 2 2 2 3 3 DSC 0 1 2 3 4 5 6 7 SNC 7 8 8 9 9 2 2 3 Delay 64 65 66 67 68 69 70 71 DSC 0 1 2 3 4 5 6 7 LAT 4 4 4 4 4 4 5 5 Delay 40 41 42 43 44 45 46 47 SNC 7 8 9 9 10 10 2 3 LAT 3 3 3 3 3 3 3 3 DSC 8 9 10 11 12 13 14 15 SNC 3 4 4 5 5 6 6 7 Delay 72 73 74 75 76 77 78 79 DSC 8 9 10 11 12 13 14 15 LAT 5 5 5 5 5 5 5 5 Delay 48 49 50 51 52 53 54 55 SNC 3 4 4 5 5 6 6 7 LAT 3 3 3 3 3 3 4 4 DSC 0 1 2 3 4 5 6 7 SNC 7 8 8 9 9 2 2 3 Delay 80 81 82 83 84 85 86 87 DSC 0 1 2 3 4 5 6 7 LAT 5 5 5 5 5 5 6 6 Delay 56 57 58 59 60 61 62 63 SNC 7 8 9 9 10 10 2 3 LAT 4 4 4 4 4 4 4 4 DSC 8 9 10 11 12 13 14 15 SNC 3 4 4 5 5 6 6 7 Delay 88 89 90 91 92 93 94 95 DSC 8 9 10 11 12 13 14 15 LAT 6 6 6 6 6 6 6 6 Delay 64 65 66 67 68 69 70 71 SNC 3 4 4 5 5 6 6 7 LAT 4 4 4 4 4 4 5 5 DSC 0 1 2 3 4 5 6 7 SNC 7 8 8 9 9 2 2 3 DSC 0 1 2 3 4 5 6 7 Rev. A | Page 51 of 76 AD9789 The timing of the input data is referenced to DCO for a given Delay 72 73 74 75 76 77 78 79 phase of DSC. The CMOS data input timing over temperature is LAT 5 5 5 5 5 5 5 5 shown in Table 68 for DCO_INV = 0 (Register 0x20[4]), SNC 3 4 4 5 5 6 6 7 DSCPHZ = 0 (Register 0x23[7:4]), and DCODIV = 1 (Register DSC 8 9 10 11 12 13 14 15 0x22[6:4]). Table 68 also shows the data valid window (DVW). Delay 80 81 82 83 84 85 86 87 The data valid window is the sum of the setup and hold times of LAT 5 5 5 5 5 5 6 6 the interface. DVW is the minimum amount of time that valid SNC 7 8 8 9 9 2 2 3 data must be presented to the device to ensure proper sampling. DSC 0 1 2 3 4 5 6 7 Delay 88 89 90 91 92 93 94 95 Table 68. CMOS Data Input Timing with Respect to DCO LAT 6 6 6 6 6 6 6 6 Temperature Min t (ns) Min t (ns) Min DVW (ns) S H SNC 3 4 4 5 5 6 6 7 −40°C 4.9 −1.4 3.5 DSC 8 9 10 11 12 13 14 15 +25°C 5.1 −1.6 3.5 Delay 96 97 98 99 100 101 102 103 +85°C 5.3 −1.7 3.6 LAT 6 6 6 6 6 6 7 7 −40°C to +85°C 5.3 −1.4 3.9 SNC 7 8 8 9 9 2 2 3 For any value of DSCPHZ greater than 0, the setup and hold DSC 0 1 2 3 4 5 6 7 times shift by increments of tDCO/16, where tDCO is the period of Delay 104 105 106 107 108 109 110 111 the data clock. LAT 7 7 7 7 7 7 7 7 t = 5.3 ns − ((t /16) × DSCPHZ) SNC 3 4 4 5 5 6 6 7 S DCO DSC 8 9 10 11 12 13 14 15 t = 0.24 ns + ((t /16) × DSCPHZ) H DCO Delay 112 113 114 115 116 117 X X LAT 7 7 7 7 7 7 X X SNC 7 8 8 9 9 2 X X DCO DSC 0 1 2 3 4 5 X X t t S H Latency Effects on Channelizer Mode INPUT DATA When selecting an interface configuration in channelizer mode, the number of DCO cycles between FS pulses (cyclesAVAIL) must DSC be greater than the number of DCO cycles required by the inter- Figure 100. CMOS Input Timing face configuration (cyclesINTERFACE). Latency consumes some of these available DCO cycles between FS. This decrease in available In some interface modes, the delay from the rising edge of DCO DCO cycles is a result of the round-trip propagation delay from to the rising edge of FS needs to be known. This delay is summa- the FS output of the AD9789 to the respective data sample at the rized over temperature in Table 69. input of the AD9789 (LTNCY[2:0]) in addition to the internal DCO latency of the device. t D For a successful interface design, the following condition must FS be met: cyclesAVAIL ≥ cyclesINTERFACE + LTNCY[2:0] + 2 DSC CMOS Interface Timing Figure 101. CMOS_DCO to CMOS_FS Delay When the AD9789 is configured with a CMOS interface (CMOS_CTRL = CMOS_BUS = 3.3 V), a CMOS data clock Table 69. Timing Delay Between CMOS_DCO and CMOS_FS output signal, DCO, is provided to drive data from the data Temperature tD, MAX DCO to FS (ns) tD, MIN DCO to FS (ns) source. The output signal operates at the input data rate, which −40°C 0.64 0.28 is equal to f /16 when DCODIV = 1. CMOS data on the bus is DAC +25°C 0.71 0.4 sampled on the rising edge of an internal sampling clock (DSC). +85°C 0.85 0.49 Note that the frequency of DCO is equal to the frequency of −40°C to +85°C 0.85 0.28 DSC and the phase relationship between DCO and DSC is determined by DSCPHZ (Register 0x23[7:4]). Rev. A | Page 52 of 76 07852-118 07852-117 AD9789 LVDS Interface Timing In some interface modes, the delay from the rising edge of DCO to the rising edge of FS needs to be known. This delay When the AD9789 is configured with an LVDS interface is summarized over temperature in Table 71. (CMOS_CTRL = CMOS_BUS = 0 V), an LVDS data clock out- put signal, DCO, is provided to drive data from the data source. DCO The LVDS interface may be single data rate (SDR) or double t D data rate (DDR) depending on the bus width configuration. In FS SDR, data is sampled into the part only on the falling edge of the internal sampling clock (DSC). Note that the frequency of DCO is equal to the frequency of DSC, so the effective data rate DSC is equal to the DCO frequency. The phase relationship between Figure 103. LVDS DCO to FS Delay DCO and DSC is determined by DSCPHZ (Register 0x23[7:4]). In DDR, data is sampled into the part on both the rising and falling Table 71. Timing Delay Between LVDS DCO and FS edges of DSC, so the effective data rate is equal to twice the DCO Temperature tD, MAX DCO to FS (ns) tD, MIN DCO to FS (ns) frequency. The interface is DDR only when the bus width is equal to −40°C 0.37 0.21 32 bits. The DCO frequency is equal to f /16 when DCODIV = 1. DAC +25°C 0.35 0.16 +85°C 0.32 0.12 The timing of the input data is referenced to DCO for a given phase −40°C to +85°C 0.37 0.12 of DSC. The LVDS input data timing over temperature is shown in Table 70 for DCO_INV = 0 (Register 0x20[4]), DSCPHZ = 0 Parity (Register 0x23[7:4]), and DCODIV = 1 (Register 0x22[6:4]). The AD9789 supports parity checking on the input data bus. Table 70. LVDS Data Input Timing with Respect to DCO There are three parity checking modes: even parity, odd parity, and IQ parity. In IQ parity mode, a value of 0 is always expected Temperature Min tS (ns) Min tH (ns) Min DVW (ns) on the I channel and a value of 1 is always expected on the Q −40°C 1.04 0.24 1.28 channel. Note that IQ parity mode is generally useful only when +25°C 1.23 0.16 1.39 the LVDS interface is used. These modes are controlled via +85°C 1.41 0.03 1.44 Register 0x20[1:0]. −40°C to +85°C 1.41 0.24 1.65 In DDR mode, these setup and hold times must be applied to Table 72. Parity Mode SPI Settings both edges of DCO. In SDR mode, these setup and hold times Parity Mode Register 0x20[1:0] must be applied to the falling edge of DCO. Deactivates Parity Checking 00 IQ Parity 01 For any value of DSCPHZ greater than 0, the setup and hold times shift by increments of t /16, where t is the period Even Parity 10 DCO DCO of the data clock. Odd Parity 11 t = 1.41 ns − ((t /16) × DSCPHZ) If parity checking is used, each data-word that is transferred S DCO into the AD9789 should have a parity bit accompanying it, tH = 0.24 ns + ((tDCO/16) × DSCPHZ) regardless of FS. In other words, parity must be valid for every SINGLE DATA RATE (SDR) DCO edge. The parity bits are located at Pin L4 and Pin M4. When operating the interface in CMOS mode, the input parity DCO bits are referred to as P1 and P0, respectively. When operating t t S H the interface in LVDS mode, the input parity bits are referred INPUT to as PARP and PARN, respectively. DATA Recall that the LVDS interface can be single data rate (SDR) or DSC double data rate (DDR), depending on the bus width configu- ration. The interface is DDR only when the bus width is equal to 32 bits. DOUBLE DATA RATE (DDR) DCO t t t t t t S H S H S H INPUT DATA DSC Figure 102. LVDS Input Timing, SDR vs. DDR Rev. A | Page 53 of 76 07852-119 07852-120 AD9789 In QDUC mode, where the interface is fixed at a 32-bit bus If a parity error occurs, the parity counter (Register 0x02[7:0]) width, the parity behavior is straightforward (see Table 73). is incremented. The parity counter continues to accumulate until it is cleared or until it reaches a maximum value of 255. Table 73. Parity Behavior in QDUC Mode The count can be cleared by writing a 1 to Register 0x04[7]. Inter- Bus face Width Even/Odd Parity IQ Parity An IRQ can be enabled to trigger when a parity error occurs by CMOS 32 bits P1 checks D[31:16] P1 = 0 writing a 1 to Register 0x03[7]. The status of IRQ can be meas- P0 checks D[15:0] P0 = 1 ured via Register 0x04[7] or by using the IRQ pin (Pin P2). If 1 LVDS 32 bits [PARP, PARN] rising checks PARP rising = 0 using the IRQ pin and more than one IRQ is enabled, the user (DDR) D[15:0]P, D[15:0]N rising PARN rising = 1 must check Register 0x04 when an IRQ event occurs to determine [PARP, PARN] falling checks PARP falling = 1 whether the IRQ was caused by a parity error. The IRQ can also D[15:0]P, D[15:0]N falling PARN falling = 0 be cleared by writing a 1 to Register 0x04[7]. 1 “Rising” corresponds to the data sampled on the rising edge of DSC; “falling” corresponds to the data sampled on the falling edge of DSC. ANALOG MODES OF OPERATION In channelizer mode, where the interface is configurable for The AD9789 uses a quad-switch architecture that can be config- different bus widths, data widths, and data formats, the parity ured to operate in one of three modes via the serial peripheral bits check the data-word on the bus. interface: normal mode, RZ mode, and mix mode. For example, consider a configuration in channelizer mode where The quad-switch architecture masks the code-dependent glitches the bus width is 4, the data width is 8, and the data format is that occur in a conventional two-switch DAC. Figure 104 shows real. In this case, eight clock cycles are required to transfer all of the waveforms for a conventional DAC and the quad-switch DAC. the baud rate data to represent four channels. In the even parity In the two-switch architecture with D1 and D2 in different states, or odd parity mode, one parity bit and four data bits are sent on a switch transition results in a glitch. However, if D1 and D2 are each clock; the parity bit checks the four data bits to verify that at the same state, the switch does not create a glitch. This code- all of the data was sent over the interface. dependent glitching causes an increased amount of distortion in Table 74 summarizes the behavior of the two parity pins and the DAC. In the quad-switch architecture, two switches are how they interact with the data in all interface modes. always transitioning at each half clock cycle, regardless of the code; therefore, code-dependent glitches are eliminated, but a Table 74. Parity Behavior in Channelizer Mode constant glitch at 2 × fDAC is created. Inter- Bus face Width Even/Odd Parity IQ Parity INPUT DATA D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 CMOS 4 bits P1 ignored P1 = 0 P0 checks D[3:0] P0 = 1 DACCLK CMOS 8 bits P1 ignored P1 = 0 P0 checks D[7:0] P0 = 1 CMOS 16 bits P1 ignored P1 = 0 D1 D2 D3 D4 D5 t 2-SWITCH P0 checks D[15:0] P0 = 1 DAC OUTPUT D6 D7 D8 D9 D10 CMOS 32 bits P1 checks D[31:16] P1 = 0 P0 checks D[15:0] P0 = 1 LVDS 4 bits [PARP, PARN] falling checks Not supported 1 4-SWITCH (SDR) D[3:0]P, D[3:0]N falling D6 D7 D8 D9 D10 t DAC OUTPUT D1 D2 D3 D4 D5 LVDS 8 bits [PARP, PARN] falling checks Not supported (NORMAL MODE) 1 (SDR) D[7:0]P, D[7:0]N falling LVDS 16 bits [PARP, PARN] falling checks Not supported 1 Figure 104. Two-Switch and Quad-Switch DAC Waveforms (SDR) D[15:0]P, D[15:0]N falling LVDS 32 bits [PARP, PARN] rising checks PARP rising = 0 The quad-switch architecture can also be easily configured to 1 (DDR) D[15:0]P, D[15:0]N rising PARN rising = 1 perform an analog mix or return-to-zero (RZ) function. In mix [PARP, PARN] falling checks PARP falling = 1 mode, the output is effectively chopped at the DAC sample rate. D[15:0]P, D[15:0]N falling PARN falling = 0 1 The RZ mode is similar to mix mode, except that the inter- “Rising” corresponds to the data sampled on the rising edge of DSC; “falling” corresponds to the data sampled on the falling edge of DSC. mediate data samples are replaced with midscale values instead of inverting values. Figure 105 shows the DAC waveforms for both mix mode and RZ mode. Rev. A | Page 54 of 76 07852-072 AD9789 INPUT DATA D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 ANALOG CONTROL REGISTERS DACCLK The AD9789 includes registers for optimizing its analog –D8 performance. These registers include noise reduction in the D3 –D7 –D9 D2 D4 output current mirror and output current mirror headroom D1 D5 –D6 –D10 adjustments. 4-SWITCH t DAC OUTPUT (f MIX MODE) Mirror Roll-Off Frequency Control S –D1 –D5 D6 D10 Using the MSEL[1:0] bits (Register 0x36[1:0]), the user can –D2 –D4 D7 D9 –D3 D8 adjust the noise contribution of the internal current mirror to optimize the 1/f noise. Figure 107 shows MSEL vs. the 1/f noise 4-SWITCH with 20 mA full-scale current into a 50 Ω resistor. DAC OUTPUT D6 D7 D8 D9 D10 t (RETURN-TO- D1 D2 D3 D4 D5 –110 ZERO MODE) –115 Figure 105. Mix Mode and RZ Mode DAC Waveforms Switching between analog modes reshapes the sinc roll-off –120 MSEL = 01 inherent at the DAC output. The performance and maximum MSEL = 11 –125 amplitude in all three Nyquist zones is affected by this sinc MSEL = 10 roll-off depending on where the carrier is placed, as shown in –130 Figure 106. FIRST SECOND THIRD MSEL = 00 NYQUIST ZONE NYQUIST ZONE NYQUIST ZONE –135 0 MIX MODE –140 RZ MODE –5 110 100 FREQUENCY (kHz) –10 Figure 107. 1/f Noise with Respect to MSEL Bits –15 NORMAL MODE –20 –25 –30 –35 0 0.5 1.0 1.5 2.0 2.5 3.0 FREQUENCY (Hz) Figure 106. Sinc Roll-Off for Each Analog Operating Mode (f = 2 × DACCLK) S The RZ mode, with its lower but flat response, can be quite useful for quick checks of system frequency response. Rev. A | Page 55 of 76 AMPLITUDE (dBm) 07852-074 07852-073 NOISE (dBm/Hz) 07852-083 AD9789 VREF (Pin C14) must be bypassed to ground with a 1 nF VOLTAGE REFERENCE capacitor. The band gap voltage is present on this pin and can The AD9789 output current is set by a combination of digital be buffered for use in external circuitry. The typical output control bits and the I120 reference current, as shown in impedance is near 5 kΩ. If desired, an external reference can be Figure 108. used to overdrive the internal reference by connecting it to the AD9789 VREF pin. FSC[9:0] V BG DAC 1.2V IPTAT (Pin D14) is used for factory testing and can simply be VREF left floating. IPTAT is an output current that is proportional to – I120 CURRENT absolute temperature. At 25°C, the output current is approx- + 1nF SCALING FULL-SCALE imately 10 μA and follows a slope of approximately 20 nA/°C. 10kΩ CURRENT For optimal DOCSIS 3.0 ACLR performance, the full-scale I120 AVSS output current settings provided in Table 75 are recommended. Figure 108. Voltage Reference Circuit Table 75. Recommended Full-Scale Current Settings vs. The reference current is obtained by forcing the band gap Number of QAM Channels voltage across an external 10 kΩ resistor from I120 (Pin B14) to Number of ground. The 1.2 V nominal band gap voltage, VREF (Pin C14), QAM Channels Recommended I (mA) FSC[9:0] FS generates a 120 μA reference current in the 10 kΩ resistor. This 1 20 512 current is adjusted digitally by FSC[7:0] (Register 0x3C[7:0]) 2 25 720 and FSC[9:8] (Register 0x3D[1:0]) to set the output full-scale 3 25 720 current, IFS, in milliamperes. 4 25 720 I = 0.023 × FSC[9:0] + 8.58 FS DAC OUTPUT STAGES The full-scale output current range is approximately 8.6 mA to To properly evaluate the AD9789 in the lab, three distinct 32.1 mA for register values from 0x000 to 0x3FF. The default output coupling circuits were used. value of 0x200 generates 20 mA full scale. The typical range is shown in Figure 109. Figure 110 shows the optimal output network when measuring 35 traditional DAC performance specifications such as SFDR and IMD performance with sine waves. 30 IOUTP 90Ω 25 JTX-2-10T 70Ω 90Ω IOUTN 20 Figure 110. Recommended Transformer Output Stage 15 for Single-Tone/Multitone Measurements 10 Figure 111 shows the optimal output network when measuring signals in mix mode (second or third Nyquist zone). The band- 5 width of the center tap transformer is not sufficient to support mix mode outputs, so the best solution is to use a wideband 0 0 200 400 600 800 1000 balun by itself. DAC GAIN CODE Figure 109. Full-Scale Current vs. DAC Gain Code 90Ω IOUTP Always connect a 10 kΩ resistor from the I120 pin to ground 70Ω and use the digital controls to adjust the full-scale current. The AD9789 is not a multiplying DAC. Applying an analog signal to IOUTN MABACT0039 I120 is not supported. 90Ω Figure 111. Recommended Transformer Output Stage for Mix Mode Rev. A | Page 56 of 76 I (mA) FS 07852-084 07852-085 07852-122 07852-121 AD9789 Finally, when measuring performance for CMTS and other The buffer, in turn, can be easily driven from lower level signals digital TV applications, it is advantageous to insert a 1 dB, such as CML or attenuated PECL that might be encountered on 1.2 GHz Chebyshev low-pass filter between the DAC and the a PCB. This buffer also provides very low, 100 fs added random transformer to better control the impedance seen at the DAC jitter, which is important to obtain the optimal ac performance core. This helps to decrease the folded back harmonics for from the AD9789. A functional block diagram of the ADCLK914 higher frequency outputs. The optimal transformer for CMTS is shown in Figure 113. Figure 114 shows the recommended measurements is the JTX-2-10T, which consists of a balun and schematic for the ADCLK914/AD9789 interface. Refer to the center-tapped transformer in a single package. This output stage ADCLK914 data sheet for more information. Any time that the is shown in Figure 112. noise floor from the DAC cannot meet the specifications in this data sheet, the clock should be examined. 4.7pF V CC 5.6nH IOUTP V REF 90Ω 2.2pF JTX-2-10T ADCLK914 70Ω V T 90Ω 5.6nH 50Ω 50Ω 50Ω 50Ω IOUTN Q 4.7pF D Q D Figure 112. Recommended Transformer Output Stage for CMTS Measurements V EE Traces from the DAC to the transformer should be 50 Ω imped- Figure 113. ADCLK914 Functional Block Diagram ance to ground each in Figure 110 and Figure 112 and 25 Ω to ground each in Figure 111 to avoid unnecessary parasitics. The internal 50 Ω resistors shown at the ADCLK914 inputs are rated to carry currents from PECL or CML drivers. The VT pin CLOCKING THE AD9789 can be connected to VCC, a PECL current sink, or the internal To provide the required signal swing for the internal clock VREF, or it can be left floating depending on the source. The receiver of the AD9789, it is necessary to use an external clock common-mode input range of the ADCLK914 does not include buffer chip to drive the CLKP and CLKN inputs. These high LVDS voltage levels, so ac coupling is required in that case. level, high slew rate signals should not be routed any distance on a PCB. The recommended clock buffer for this application is the ADCLK914. This ultrafast clock buffer is capable of providing 1.9 V out of each side into a 50 Ω load terminated to V (3.3 V) for a total differential swing of 3.8 V. CC GND VCC33 C83 0.01µF VCC33 C99 R13 R14 2400pF 49.9Ω 49.9Ω C0803H50 U3 CLKP ADCLK914 16 15 14 13 J3 GND R17 C81 C102 PSTRNKPE4117 100Ω 0.01µF 2400pF 1 1 12 R0402 D Q C0803H50 2 11 D Q CLKN 3 10 NC NC 2 3 4 5 C82 4 9 0.01µF NC NC ADCLK914 SUPPLY DECOUPLING GND VCC33 R15 56 78 49.9Ω VCC33 C31 C32 C33 C34 0.1µF 0.01µF 0.1µF 0.01µF GND C0402 C0402 C0402 C0402 GND GND GND GND GND Figure 114. ADCLK914/AD9789 Interface Circuit for Use with a Lab Generator Rev. A | Page 57 of 76 V NC T V NC REF V V EE EE V V CC CC 07852-123 07852-125 07852-124 AD9789 Optimizing the Clock Common-Mode Voltage Table 76. Four-Carrier DOCSIS Close-In ACLR Performance at 900 MHz for Various Phase Noise Profiles In addition to the system that optimizes the handoff timing, an Phase Noise (dBc) additional system sets the common-mode voltage of the clock. Band Profile 1 Profile 2 Profile 3 Profile 4 Spec This system can be used to properly align the crossing point of 750 kHz −71 −67.2 −62.4 −59.1 −60 the CLKP and CLKN signals to ensure that the duty cycle of the to 6 MHz clock is set properly. Figure 115 shows how the common-mode 6 MHz to −70.9 −70.3 −67 −63.8 −63 voltage of CLKP and CLKN is set. There are eight switches 12 MHz controlled by the CLKP_CML bits (Register 0x32[4:1]) and the 12 MHz to −71 −70.8 −70.8 −70.8 −65 CLKN_CML bits (Register 0x31[7:4]) for both the CLKP and 18 MHz CLKN signals. The direction of the adjustment is determined by Table 77 shows the phase noise at various offsets for each the PSIGN and NSIGN bits (Register 0x32, Bit 5 and Bit 0). If profile. (All phase noise numbers are specified in dBc/Hz.) PSIGN and NSIGN are low, the common-mode voltage decreases with CLKP_CML/CLKN_CML values. If PSIGN and NSIGN are Table 77. Phase Noise Summary for Each Profile high, the common-mode voltage increases with CLKP_CML/ Phase Noise (dBc/Hz) CLKN_CML values, as shown in Figure 116. With both 1 Offset Profile 1 Profile 2 Profile 3 Profile 4 CLKP_CML and CLKN_CML set to 0, the feedback path forces 2 kHz −114.8 −112.8 −111.7 −111.2 the common-mode voltage to be set to approximately 0.9 V. The 20 kHz −117.8 −115.5 −114.6 −113.8 optimal ac performance occurs at a setting of −15 on both the 200 kHz −128.3 −118.9 −118.3 −116.8 CLKP and CLKN offset bits. 2 MHz −148.5 −127.9 −122.2 −117.9 20 MHz −152.5 −149.9 −148 −145.7 1 At offsets less than 500 kHz, the measurement instrument dominates the phase noise performance. CLKx_CML SIGN = 0 To meet the close-in ACLR requirements for four-carrier CLKP/CLKN DOCSIS, the phase noise found in Profile 3 is the minimum requirement necessary. CLKx_CML MU DELAY CONTROLLER SIGN = 1 The mu delay adjusts timing between the digital and analog blocks. The mu delay controller receives phase relational CVDD18 information between the digital and analog clock domains. The Figure 115. Clock Common-Mode Control control system continuously adjusts the mu delay to maintain 1.10 CLKP CLKN the desired phase relationship between the digital and analog 1.05 sections. A top level diagram of the mu delay within the DAC is shown in Figure 117. 1.00 14-BIT 16-BIT 16 14 0.95 DIGITAL 2.4GSPS DATA CIRCUITRY DAC 0.90 DAC MU MU 0.85 CLOCK DELAY Φ DET 0.80 MU Φ CONTROL 0.75 Figure 117. Mu Delay Controller Block Diagram 0.70 –15 –13 –11 –9 –7 –5 –3 –1 1 3 5 7 9 11 13 15 The mu controller has two modes of operation: initial phase OFFSET CODE search and phase tracking. In the phase search mode, the con- Figure 116. Common-Mode Voltage with Respect to CLKP_CML/CLKN_CML and PSIGN/NSIGN troller looks for the initial mu delay value to use before going into tracking mode. In tracking mode, the controller makes Clock Phase Noise Effects on AC Performance adjustments to the initial mu delay value to keep the phase at The quality of the clock source driving the ADCLK914 deter- the desired value. The initial phase search is required because mines the achievable ACLR performance of the AD9789. multiple mu delay settings may result in the desired phase, but Table 76 summarizes the close-in ACLR for a four-carrier the device may not operate correctly at all of those mu delay values. DOCSIS signal at 900 MHz with respect to various phase noise profiles. (All ACLR values are specified in dBc.) Rev. A | Page 58 of 76 COMMON-MODE VOLTAGE (V) 07852-081 07852-082 07852-077 AD9789 Operating the Mu Controller in Auto Mode The search fails if the mu delay reaches the endpoints. If the controller does not find the desired phase during the search, the The mu controller is enabled via Register 0x33[0]. Enabling the TRACK_ERR bit (Register 0x2F[5]) determines the corrective controller sets in motion the phase search mode. Before enabling action as follows: the controller, it is important to turn on both the phase comparator boost (Register 0x3E[5]) and the mu control duty cycle correction Continue (0): continues to search (optimal setting) • circuitry (Register 0x30[7]). Both of these functions allow for more • Reset (1) robust operation of the mu controller over the entire operating 18 DESIRED speed of the part. The three modes of operation for the mu con- PHASE 16 troller are specified by the MODE[1:0] bits in Register 0x33[5:4] AND GUARD SLOPE BAND as follows: 14 12 • Search and track (00) (optimal setting) GUARD BAND • Track only (01) 10 • Search only (10) 8 The search algorithm begins at a specified mu delay value set using 6 the MUDLY[8:0] bits, where the LSB is located in Register 0x39[7] 4 and the MSBs are located in Register 0x3A[7:0]. Even though 2 SEARCH STARTING there are nine bits of resolution for this delay line value, the LOCATION maximum allowable mu delay is 431 (decimal). The optimal 0 0 40 80 120 160 200 240 280 320 360 400 440 point to begin the search is in the middle of the delay line, or MU DELAY approximately 216. The initial search algorithm works by sweep- Figure 118. Typical Mu Phase Characteristics @ 2.4 GSPS ing through different mu delay values until the desired phase is To determine whether the search is on the correct slope, the measured; this phase is specified using the MUPHZ[4:0] bits in controller measures the slope by first incrementing and then Register 0x39[4:0], with the maximum allowable phase being 16. decrementing the mu delay value until any of the following If values larger than 16 are loaded, the controller will not lock. events happens: When the desired phase is measured, the slope of the phase measurement is calculated and compared to the desired slope, • The phase changes by 2. which is specified by the SLOPE bit in Register 0x33[6]. For • The phase is equal to 16 (the maximum value). optimal ac performance, the best setting for the search is a • The phase is equal to 0 (the minimum value). positive slope and a phase value of 14. If the phase and slope • The mu delay is 431 (the maximum value). match the configured values, the search algorithm is finished. • The mu delay is 0 (the minimum value). The SEARCH_TOL bit (Register 0x2F[7]) can be used to specify the accuracy of the search as follows: After incrementing and then decrementing the mu delay value, the values of the measured phases are compared to determine • Not exact (0): can find a phase within two values of the whether the slope matches the desired slope. To consider the desired phase slope valid, the positive direction phase and the negative • Exact (1): finds the exact phase specified (optimal setting) direction phase must be on opposite sides of the desired phase. Figure 118 shows a typical plot of mu phase vs. mu delay line Examples of valid and invalid phase choices are shown in value at 2.4 GSPS. Starting at the selected mu delay value, the Figure 119 and Figure 120. search direction can be specified via the SEARCH_DIR[1:0] bits in Register 0x39[6:5]. The three possible choices for the 15 9 search are as follows: 14 8 • Down only (00) 13 7 • Up only (01) 12 • Alternating up and down (10) (optimal setting) 6 DESIRED DESIRED If the search direction is alternating, the search proceeds in both 11 5 directions until a programmable guard band is reached in one 4 of the directions, specified by the GUARDBAND[4:0] bits in 10 Register 0x2F[4:0]. When the guard band is reached, the search continues only in the opposite direction. If the desired phase is POSITIVE SLOPE NEGATIVE SLOPE not found before the guard band is reached in the second direc- Figure 119. Valid Positive and Negative Slope Phase Examples tion, the search reverts to the alternating mode and continues looking within the guard band. Rev. A | Page 59 of 76 MU PHASE 07852-078 07852-079 AD9789 Table 78 lists register writes and reads to lock to the controller. 15 4 15 The program assumes that the clock receiver is already enabled DESIRED 14 3 3 14 and that a clean lock is provided. The typical locking time for 13 2 13 2 the mu controller is approximately 180,000 DAC cycles (at DESIRED 2 GSPS, ~75 μs). 12 11 Figure 120. Invalid Slope Phase Examples Table 78. AD9789 Mu Delay Controller Routine Address Data R/W Description When the initial mu delay value has been found by the search 0x30 0x80 Write Enable duty cycle correction. algorithm, the tracking mode is enabled. In tracking mode, a 0x31 0xF0 Write Set common-mode level of CLKN: simple control loop is used to increment by 1, decrement by 1, CLKN_CML = 0xF. or not change the mu delay value depending on the measured 0x32 0x9E Write Set common-mode level of CLKP: phase. The control loop uses the desired slope to determine CLKP_CML = 0xF. whether the mu delay should be incremented or decremented. Set direction of CLKP_CML and No attempt is made to determine whether the actual slope has CLKN_CML: PSIGN = 0; NSIGN = 0. changed or is still valid. Enable clock receiver: CLK_DIS = 1. 0x3E 0x38 Write Set phase comparator boost Two status bits, LOCKACQ (Register 0x04[3]) and LOCKLOST (AUTO_CAL must be set to its (Register 0x04[2]) are available to signal proper operation of the default value, 1). control loop. If the current phase is more than five steps away 0x24 0x00 Write Enable digital clocks. from the desired phase and the LOCKACQ bit was previously 0x24 0x80 Write set, the LOCKACQ bit is cleared and the LOCKLOST interrupt 0x2F 0xCE Write Search for exact phase with a guard bit is set. Furthermore, if lock is lost, the controller can remain band of 98 codes from endpoints. in the tracking loop, or it can be reset to start the search again. 0x33 0x42 Write Set search slope to positive. By setting the MUSAMP bit high (Register 0x33[3]) from a low 0x39 0x4E Write Set search phase to 14, search up and down. state, the user can read back the mu delay value that the controller 0x3A 0x6C Write Set start point of search to mid- locked to by reading the MUDLY bits (Register 0x39[7] and point of mu delay line (Code 216). Register 0x3A[7:0]), as well as the phase it locked to by reading 0x03 0x00 Write Disable lock and lock lost indicators. back the MUPHZ[4:0] bits (Register 0x39[4:0]). These bits will 0x04 0xFE Write Clear lock and lock lost indicators. no longer read back the value that the search started at or the 0x03 0x0C Write Enable lock and lock lost indicators. desired phase, but instead will read back the mu delay line value 0x33 0x43 Write Enable mu delay controller and and phase that the controller is locked to. start search/track routine. 0x33 0x4B Write Set mu phase read bit high. 0x33 0x43 Write Set mu phase read bit low. 0x04 Read Check lock and lock lost bits: LOCKACQ should be on. LOCKLOST should be off. 0x39 Read Check phase readback (should be equal to 14). Rev. A | Page 60 of 76 07852-080 AD9789 INTERRUPT REQUESTS Operating the Mu Controller in Manual Mode The following interrupt (IRQ) requests can be used for additional In manual mode, the user must sweep through all the mu delay information and verification of the status of various functional values and record the phase value at each value of MUDLY as blocks: shown in Figure 118. Every time that the MUDLY value is stepped, the MUSAMP bit must be toggled from low to high • PARERR—triggered when one or more parity errors to read the corresponding phase for the specified mu delay line occurs on the data bus value. It is not possible to keep read high and continuously read • PARMSET—triggered when PARMNEW is set and back the phase value. As with auto mode, the optimal ac perfor- internally registered mance occurs at a positive slope and a phase of 14; therefore, • PARMCLR—triggered when PARMNEW is cleared and when the curve is complete, choose the MUDLY value that internally registered corresponds to this condition and write that value to the • LOCKACQ—triggered when the mu controller is locked to MUDLY[8:0] bits (Register 0x39[7] and Register 0x3A). the user-defined phase Calculating Mu Delay Line Step Size • LOCKLOST—triggered when the mu controller loses lock Stepping through all of the mu delay line values and plotting (if the LOCKACQ bit was previously set) mu phase vs. mu delay not only allows the user to find the • SATERR—triggered when one or more saturation errors optimal mu delay value, but can also allow the user to determine occurs the mu delay line step size. To calculate the step size, take one Each IRQ is enabled using the enable bits in the interrupt full cycle of the mu phase curve and divide the period of the enable register, Register 0x03. The status of the IRQ can be DAC clock by this delta. From Figure 118, the two transition measured in one of the following ways: via the SPI bits found in points are approximately 56 and 270, providing a delta of approx- the interrupt status/clear register (Register 0x04) or using the imately 214 steps. Therefore, the mu delay line step size would IRQ pin (Pin P2). be approximately 2 ps/step, as shown in the following equation: If the pin is used to determine that an interrupt has occurred, ⎛ ⎞ 1 it is necessary to check Register 0x04 to determine which bit ⎜ ⎟ ⎜ ⎟ 2.4 GHz caused the interrupt because the pin indicates only that an ⎝ ⎠ = 1.95 ps interrupt has occurred. To clear an IRQ, it is necessary to write 214 a 1 to the bit in Register 0x04 that corresponds to the interrupt. If the mu controller is enabled, this value allows the user to calculate (in picoseconds) how much drift is in their system with respect to the DAC clock period over temperature. Rev. A | Page 61 of 76 AD9789 RECOMMENDED START-UP SEQUENCE The steps necessary to optimize the performance of the part and generate an output waveform are listed in Table 79. Table 79. Recommended System Start-Up Sequence Step Description Register Data 0 Power up the AD9789. 0 Apply the clock. 1 Enable the clock receiver and set the clock CML. 0x32 0x9E 1 Enable duty cycle correction. 0x30 0x80 2 Enable digital clocks. 0x24 0x00 3 0x24 0x80 4 Set up mu controller. 0x2F 0xCE 4 0x33 0x42 4 0x39 0x4E 4 0x3A 0x6C 5 Disable all interrupts. 0x03 0x00 6 Clear all interrupts. 0x04 0xFE 7 Enable mu control interrupts. 0x03 0x0C 8 Enable mu delay controller. 0x33 0x43 9 Set up digital datapath. 0x06 to 0x15 9 Set up rate converter. 0x16 to 0x1B 9 Set up BPF center frequency. 0x1C to 0x1D 9 Set up interface. 0x20 to 0x23 9 Set up channel gains. 0x25 to 0x28 9 Set up spectral invert. 0x29 9 Set up full-scale current. 0x3C to 0x3D 1 10 Wait until mu delay controller is locked (SPI read). 0x04 0x08 11 Update rate converter and BPF. 0x1E 0x80 12 Update interface clocks. 0x24 0x00 13 0x24 0x80 14 Enable channels. 0x05 15 Enable other interrupts if desired. 0x03 1 Typical lock time of the mu controller is approximately 180,000 DAC cycles (at 2 GSPS, ~75 μs). Rev. A | Page 62 of 76 AD9789 CUSTOMER BIST MODES USING THE INTERNAL PRN GENERATOR TO TEST After the PRN generator is started, users can freely configure QAM OUTPUT AC PERFORMANCE the datapath for their desired test configuration as long as Register 0x40 to Register 0x55 are not modified. The AD9789 can be configured to enable an on-chip pseudo- random number (PRN) generator. The PRN output is connected To disable the PRN generator, write 0x00 to Register 0x40. to the front end of the datapath and disconnects the datapath USING THE INTERNAL BUILT-IN SELF-TEST (BIST) from the input pins. In this way, the PRN generator can be used TO TEST FOR DIGITAL DATA INPUT CONNECTIVITY in conjunction with the on-chip QAM encoder to generate a QAM output. The PRN generator allows the user to measure The AD9789 includes an internal built-in self-test (BIST) engine that processes incoming data and creates a signature that can be the ac performance of a QAM signal at the DAC output without an external data source. To enable the internal PRN generator read back via the serial port. This BIST feature can be configured via the serial port, follow these steps. to observe the static state of the digital data input pins (L4 to L12, M4 to M12, N5 to N12, and P5 to P12) and to reflect the 1. Ensure that the clock is enabled and that the clock state of these pins via the signature registers (Register 0x50 to common-mode level is set to its optimal value by setting Register 0x55). In this way, the user can verify digital data input the registers in Table 80 to the values shown in the table. connectivity. Table 80. Register Settings to Configure the Clock Testing Connectivity for LVDS Interface Mode Register Data Description To test the connectivity of the digital data input pins in LVDS 0x30 0x80 Enable duty cycle correction. interface mode, follow these steps. 0x31 0xF0 Set the common-mode level of CLKN: CLKN_CML = 0xF. 1. Ensure that the clock is enabled and that the clock 0x32 0x9E common-mode level is set to its optimal value by setting Set the common-mode level of CLKP: CLKP_CML = 0xF. Set PSIGN = 0, NSIGN = 0. the registers in Table 83 to the values shown in the table. Enable clock receiver (CLK_DIS = 1). Table 83. Register Settings to Configure the Clock 2. Configure BIST mode for PRN generation and disconnect Register Data Description the inputs by setting the registers in Table 81 to the values 0x30 0x80 Enable duty cycle correction. shown in the table. 0x31 0xF0 Set the common-mode level of CLKN: CLKN_CML = 0xF. Table 81. Register Settings to Configure PRN Generation 0x32 0x9E Set the common-mode level of CLKP: Register Setting CLKP_CML = 0xF. Set PSIGN = 0, NSIGN = 0. 0x42 0x10 Enable clock receiver (CLK_DIS = 1). 0x43 0x00 0x44 0x10 2. Cycle the PARMNEW bit to ensure that the digital clocks 0x45 0x00 are active by first setting Register 0x24 to 0x00, and then 0x46 0x00 setting Register 0x24 to 0x80. 0x47 0x10 3. Configure the LVDS interface for high speed, 16-bit bus 0x49 0x16 width, 16-bit data width operation by setting the registers 0x4B 0x17 in Table 84 to the values shown in the table. 0x4C 0x4E 0x4D 0x1F Table 84. Register Settings for LVDS Interface 0x05 0x0F Register Setting 3. Cycle the PARMNEW bit to ensure that the digital clocks 0x20 0x08 are active by first setting Register 0x24 to 0x00, and then 0x21 0x41 setting Register 0x24 to 0x80. 0x22 0x1F 4. Start PRN generation by setting the registers in Table 82 to 0x23 0x87 the values shown in the table. Table 82. Register Settings to Start PRN Generation Register Setting 0x48 0xAB 0x4A 0xAB 0x40 0x56 Rev. A | Page 63 of 76 AD9789 2. Cycle the PARMNEW bit to ensure that the digital clocks 4. Configure pin mode by setting the registers in Table 85 to are active by first setting Register 0x24 to 0x00, and then the values shown in the table. setting Register 0x24 to 0x80. Table 85. Register Settings to Configure Pin Modes 3. Configure the CMOS interface for high speed, 32-bit bus Register Setting width, 16-bit data width operation by setting the registers in Table 89 to the values shown in the table. 0x42 0x00 0x43 0x08 Table 89. Register Settings for CMOS Interface 0x44 0x00 Register Setting 0x45 0x08 0x20 0x08 0x46 0x00 0x21 0x61 0x47 0x10 0x22 0x1F 0x49 0x1C 0x23 0x87 0x4B 0x1C 0x4C 0x00 4. Configure pin mode by setting the registers in Table 90 to 0x4D 0x00 the values shown in the table. 5. Cycle the PARMNEW bit to ensure that the interface Table 90. Register Settings to Configure Pin Modes configuration was updated by first setting Register 0x24 Register Setting to 0x00, and then setting Register 0x24 to 0x80. 0x42 0x00 6. Apply static LVDS data to the input ports. 0x43 0x08 7. Enable the BIST pin test by setting the registers in Table 86 0x44 0x00 to the values shown in the table. 0x45 0x08 0x46 0x00 Table 86. Register Settings for BIST Pin Test 0x47 0x10 Register Setting 0x49 0x1C 0x48 0x80 0x4B 0x1C 0x4A 0x80 0x4C 0x00 0x40 0x55 0x4D 0x00 8. Read back the signature registers (Register 0x50 to 5. Cycle the PARMNEW bit to ensure that the interface Register 0x55) to determine the pin states (see Table 87). configuration was updated by first setting Register 0x24 Table 87. Signature Register Settings to 0x00, and then setting Register 0x24 to 0x80. 6. Apply static CMOS data to the input ports. Register Associated LVDS Pairs 7. Enable the BIST pin test by setting the registers in Table 91 0x50 Data bits D[7:0] to the values shown in the table. 0x51 Data bits D[15:8] 0x52 Parity PAR Table 91. Register Settings for BIST Pin Test 0x53 Data bits D[7:0] (repeated) Register Setting 0x54 Data bits D[15:8] (repeated) 0x48 0x80 0x55 Parity PAR (repeated) 0x4A 0x80 Testing Connectivity for CMOS Interface Mode 0x40 0x55 To test the connectivity of the digital data input pins in CMOS 8. Read back the signature registers (Register 0x50 to Register interface mode, follow these steps. 0x55) to determine the pin states (see Table 92). 1. Ensure that the clock is enabled and that the clock Table 92. Signature Register Settings common-mode level is set to its optimal value by setting Register Associated CMOS Pairs the registers in Table 88 to the values shown in the table. 0x50 Data bits D[23:16] Table 88. Register Settings to Configure the Clock 0x51 Data bits D[31:24] Register Data Description 0x52 Parity P1 0x30 0x80 Enable duty cycle correction. 0x53 Data bits D[7:0] 0x31 0xF0 Set the common-mode level of CLKN: 0x54 Data bits [D15:8] CLKN_CML = 0xF. 0x55 Parity P0 0x32 0x9E Set the common-mode level of CLKP: CLKP_CML = 0xF. Set PSIGN = 0, NSIGN = 0. Enable clock receiver (CLK_DIS = 1). Rev. A | Page 64 of 76 AD9789 QAM CONSTELLATION MAPS Q I Q = 10 10111 10011 00110 00010 I Q = 00 Q K K K K I Q = 10 I Q = 00 K K K K 1011 1001 0010 0011 10010 10101 10001 00100 00101 00111 1010 1000 0000 0001 10110 10100 10000 00000 00001 00011 1101 1100 0100 0110 I 11011 11001 11000 01000 01100 01110 I 1111 1110 0101 0111 11111 11101 11100 01001 01101 01010 I Q =11 I Q = 01 K K K K 11010 11110 01011 01111 I Q ARE THE TWO MSBs IN EACH QUADRANT. I Q =11 I Q = 01 K K K K K K I Q ARE THE TWO MSBs IN EACH QUADRANT. K K Figure 121. DVB-C 16-QAM Constellation Figure 123. DVB-C 32-QAM Constellation 11010 11011 01011 01010 Q = 00 11 I K K Q 11000 11001 01001 01000 101100 101110 100110 100100 001000 001001 001101 001100 9 I Q = 10 101101 101111 100111 100101 001010 001011 001111 001110 I Q = 00 10000 10001 10101 10100 11100 11101 K K K K I Q = 10 K K 7 π/2 ROTATION 101001 101011 100011 100001 000010 000011 000111 000110 10010 10011 10111 10110 11110 11111 5 101000 101010 100010 100000 000000 000001 000101 000100 00010 00011 00111 00110 01110 01111 3 110100 110101 110001 110000 010000 010010 011010 011000 I 00000 00001 00101 00100 01100 01101 1 110110 110111 110011 110010 010001 010011 011011 011001 1 3 579 11 111110 111111 111011 111010 010101 010111 011111 011101 I Q =11 I Q = 01 K K K K I Q =11 I Q = 01 111100 111101 111001 111000 010100 010110 011110 011100 K K K K π ROTATION 3π/2 ROTATION I Q ARE THE TWO MSBs IN EACH QUADRANT. K K I Q ARE THE TWO MSBs IN EACH QUADRANT. K K Figure 122. DVB-C 64-QAM Constellation Figure 124. DVB -C128-QAM Constellation3 Rev. A | Page 65 of 76 07852-086 07852-087 07852-088 07852-089 AD9789 I Q = 00 K K 0000 0001 0101 0100 0100 0101 0001 0000 15 0010 0011 0111 0110 0110 0111 0011 0010 13 1010 1011 1111 1110 1110 1111 1011 1010 11 I Q = 10 K K 10 11 10 1000 1001 1101 1100 11 1100 1101 1001 1000 π/2 ROTATION 9 1000 1001 1101 1100 1100 1101 1001 1000 7 1010 1011 1111 1110 1110 1111 1011 1010 5 0010 0011 0111 0110 0110 0111 0011 0010 3 00 01 00 0000 0001 0101 0100 01 0100 0101 0001 0000 1 1 357 9 11 13 15 I Q =11 I Q = 01 K K K K π ROTATION 3π/2 ROTATION I Q ARE THE TWO MSBs IN EACH QUADRANT. K K Figure 125. DVB-C 256-QAM Constellation Q C5 C4 C3, C2 C1 C0 110,111 111,011 010,111 011,011 100,101 101,111 110,101 111,111 110,100 111,000 010,100 011,000 100,000 101,010 110,000 111,010 100,111 101,011 000,111 001,011 000,101 001,111 010,101 011,111 100,100 101,000 000,100 001,000 000,000 001,010 010,000 011,010 I 010,011 011,001 000,011 001,001 000,001 001,101 100,001 101,101 010,110 011,100 000,110 001,100 000,010 001,110 100,010 101,110 110,011 111,001 100,011 101,001 010,001 011,101 110,001 111,101 110,110 111,100 100,110 101,100 010,010 011,110 110,010 111,110 Figure 126. DOCSIS 64-QAM Constellation Rev. A | Page 66 of 76 07852-091 07852-090 AD9789 Q C7 C6 C5 C4, C3 C2 C1 C0 1110, 1111, 1110, 1111, 1110, 1111, 1110, 1111, 0000, 0011, 0100, 0111, 1000, 1011, 1100, 1111, 1111 1101 1011 1001 0111 0101 0011 0001 1111 1111 1111 1111 1111 1111 1111 1111 1100, 1101, 1100, 1101, 1100, 1101, 1100, 1101, 0000, 0011, 0100, 0111, 1000, 1011, 1100, 1111, 1110 1100 1010 1000 0110 0100 0010 0000 1100 1100 1100 1100 1100 1100 1100 1100 1010, 1011, 1010, 1011, 1010, 1011, 1010, 1011, 0000, 0011, 0100, 0111, 1000, 1011, 1100, 1111, 1111 1101 1011 1001 0111 0101 0011 0001 1011 1011 1011 1011 1011 1011 1011 1011 1000, 1001, 1000, 1001, 1000, 1001, 1000, 1001, 0000, 0011, 0100, 0111, 1000, 1011, 1100, 1111, 1110 1100 1010 1000 0110 0100 0010 0000 1000 1000 1000 1000 1000 1000 1000 1000 0110, 0111, 0110, 0111, 0110, 0111, 0110, 0111, 0000, 0011, 0100, 0111, 1000, 1011, 1100, 1111, 1111 1101 1011 1001 0111 0101 0011 0001 0111 0111 0111 0111 0111 0111 0111 0111 0100, 0101, 0100, 0101, 0100, 0101, 0100, 0101, 0000, 0011, 0100, 0111, 1000, 1011, 1100, 1111, 1110 1100 1010 1000 0110 0100 0010 0000 0100 0100 0100 0100 0100 0100 0100 0100 0010, 0011, 0010, 0011, 0010, 0011, 0010, 0011, 0000, 0011, 0100, 0111, 1000, 1011, 1100, 1111, 1111 1101 1011 1001 0111 0101 0011 0001 0011 0011 0011 0011 0011 0011 0011 0011 0000, 0001, 0000, 0001, 0000, 0001, 0000, 0001, 0000, 0011, 0100, 0111, 1000, 1011, 1100, 1111, 1110 1100 1010 1000 0110 0100 0010 0000 0000 0000 0000 0000 0000 0000 0000 0000 I 1110, 1101, 1010, 1001, 0110, 0101, 0010, 0001, 0000, 0001, 0000, 0001, 0000, 0001, 0000, 0001, 0001 0001 0001 0001 0001 0001 0001 0001 0001 0011 0101 0111 1001 1011 1101 1111 1110, 1101, 1010, 1001, 0110, 0101, 0010, 0001, 0010, 0011, 0010, 0011, 0010, 0011, 0010, 0011, 0010 0010 0010 0010 0010 0010 0010 0010 0000 0010 0100 0110 1000 1010 1100 1110 1110, 1101, 1010, 1001, 0110, 0101, 0010, 0001, 0100, 0101, 0100, 0101, 0100, 0101, 0100, 0101, 0101 0101 0101 0101 0101 0101 0101 0101 0001 0011 0101 0111 1001 1011 1101 1111 1110, 1101, 1010, 1001, 0110, 0101, 0010, 0001, 0110, 0111, 0110, 0111, 0110, 0111, 0110, 0111, 0110 0110 0110 0110 0110 0110 0110 0110 0000 0010 0100 0110 1000 1010 1100 1110 1110, 1101, 1010, 1001, 0110, 0101, 0010, 0001, 1000, 1001, 1000, 1001, 1000, 1001, 1000, 1001, 1001 1001 1001 1001 1001 1001 1001 1001 0001 0011 0101 0111 1001 1011 1101 1111 1110, 1101, 1010, 1001, 0110, 0101, 0010, 0001, 1010, 1011, 1010, 1011, 1010, 1011, 1010, 1011, 1010 1010 1010 1010 1010 1010 1010 1010 0000 0010 0100 0110 1000 1010 1100 1110 1110, 1101, 1010, 1001, 0110, 0101, 0010, 0001, 1100, 1101, 1100, 1101, 1100, 1101, 1100, 1101, 1101 1101 1101 1101 1101 1101 1101 1101 0001 0011 0101 0111 1001 1011 1101 1111 1110, 1101, 1010, 1001, 0110, 0101, 0010, 0001, 1110, 1111, 1110, 1111, 1110, 1111, 1110, 1111, 1110 1110 1110 1110 1110 1110 1110 1110 0000 0010 0100 0110 1000 1010 1100 1110 Figure 127. DOCSIS 256-QAM Constellation Rev. A | Page 67 of 76 07852-126 AD9789 CHANNELIZER MODE PIN MAPPING FOR CMOS AND LVDS 11 24 3 5 6 7 89 10 11 12 134 Table 93 lists the available combinations of data input configu- ration parameters when the AD9789 is in channelizer mode. A Many of these configurations require multiple clocks to load all B channels. All of these configurations are described in detail in C Table 96 and Table 97. D E Table 94 and Table 95, along with Figure 128 and Figure 129, F describe CMOS and LVDS data input pin mapping. CMOS G mode is always single data rate and samples on the rising edge H of DSC. LVDS mode is single data rate (SDR) for bus widths J of 4 bits through 16 bits and double data rate (DDR) for a bus K width of 32 bits. L P1 31 27 23 19 15 11 7 3 BU CMOS_BUS Table 93. Data Input Configurations for Channelizer Mode P0 M 30 26 22 18 14 10 6 2 CT CMOS_CTRL Bus Width Data Width Data Format N 29 25 21 17 13 9 5 1 FS CMOS_FS 4 8 Real 28 24 20 16 12 8 4 0 DC P CMOS_DCO 4 8 Complex D[31:0] CMOS DATA INPUTS 8 8 Real PARITY AND CONTROL INPUTS 8 8 Complex Figure 128. CMOS Data Input Pin Mapping 8 16 Complex 16 8 Real 16 8 Complex 11 24 3 5 6 7 89 10 11 12 134 16 16 Complex A 32 8 Real B 32 8 Complex C 32 16 Complex D E F Table 94. CMOS Pin Assignments for Various Interface Widths G Interface Width Pin Assignments BUSWDTH[1:0] H 4 bits D[3:0] 00 J PARP 8 bits D[7:0] 01 FSP K PARN 16 bits D[15:0] 10 FSN L P+ 15 13 11 9 7 53 1 FS 32 bits D[31:0] 11 DCOP M P– 15 13 11 9 7 53 1 FS DCON N 14 12 10 8 6 4 2 0 DC DC P 14 12 10 8 6 4 2 0 Table 95. LVDS Pin Assignments for Various Interface Widths 14 +LVDS 14 –LVDS Interface Width Pin Assignments BUSWDTH[1:0] Figure 129. LVDS Data Input Pin Mapping 4 bits D[3:0]P, D[3:0]N 00 8 bits D[7:0]P, D[7:0]N 01 16 bits D[15:0]P, D[15:0]N 10 32 bits D[15:0]P, D[15:0]N rising 11 edge and falling edge Rev. A | Page 68 of 76 07852-127 07852-128 AD9789 In Table 96, “R” represents real data loaded to a given channel, “I” represents the in-phase term, and “Q” represents the quadrature term of complex data. The channel number follows R, I, or Q. Table 96. Channelizer Mode Configurations and Channel Construction: CMOS Interface, Channel Prioritization = 1 Datapath Configuration CMOS Pin Mapping BW DW Format DCO [D31:D28] [D27:D24] [D23:D20] [D19:D16] [D15:D12] [D11:D8] [D7:D4] [D3:D0] 4 8 Real 1 R0 2 R0 3 R1 4 R1 5 R2 6 R2 7 R3 8 R3 Datapath Configuration CMOS Pin Mapping BW DW Format DCO [D31:D28] [D27:D24] [D23:D20] [D19:D16] [D15:D12] [D11:D8] [D7:D4] [D3:D0] 4 8 Complex 1 I0 2 I0 3 Q0 4 Q0 5 I1 6 I1 7 Q1 8 Q1 9 I2 10 I2 11 Q2 12 Q2 13 I3 14 I3 15 Q3 16 Q3 Datapath Configuration CMOS Pin Mapping BW DW Format DCO [D31:D28] [D27:D24] [D23:D20] [D19:D16] [D15:D12] [D11:D8] [D7:D4] [D3:D0] 8 8 Real 1 R0 2 R1 3 R2 4 R3 Datapath Configuration CMOS Pin Mapping BW DW Format DCO [D31:D28] [D27:D24] [D23:D20] [D19:D16] [D15:D12] [D11:D8] [D7:D4] [D3:D0] 8 8 Complex 1 I0 2 Q0 3 I1 4 Q1 5 I2 6 Q2 7 I3 8 Q3 Rev. A | Page 69 of 76 AD9789 Datapath Configuration CMOS Pin Mapping BW DW Format DCO [D31:D28] [D27:D24] [D23:D20] [D19:D16] [D15:D12] [D11:D8] [D7:D4] [D3:D0] 8 16 Complex 1 I0 2 I0 3 Q0 4 Q0 5 I1 6 I1 7 Q1 8 Q1 9 I2 10 I2 11 Q2 12 Q2 13 I3 14 I3 15 Q3 16 Q3 Datapath Configuration CMOS Pin Mapping BW DW Format DCO [D31:D28] [D27:D24] [D23:D20] [D19:D16] [D15:D12] [D11:D8] [D7:D4] [D3:D0] 16 8 Real 1 R1 R0 2 R3 R2 Datapath Configuration CMOS Pin Mapping BW DW Format DCO [D31:D28] [D27:D24] [D23:D20] [D19:D16] [D15:D12] [D11:D8] [D7:D4] [D3:D0] 16 8 Complex 1 Q0 I0 2 Q1 I1 3 Q2 I2 4 Q3 I3 Datapath Configuration CMOS Pin Mapping BW DW Format DCO [D31:D28] [D27:D24] [D23:D20] [D19:D16] [D15:D12] [D11:D8] [D7:D4] [D3:D0] 16 16 Complex 1 I0 2 Q0 3 I1 4 Q1 5 I2 6 Q2 7 I3 8 Q3 Datapath Configuration CMOS Pin Mapping BW DW Format DCO [D31:D28] [D27:D24] [D23:D20] [D19:D16] [D15:D12] [D11:D8] [D7:D4] [D3:D0] 32 8 Real 1 R3 R2 R1 R0 Datapath Configuration CMOS Pin Mapping BW DW Format DCO [D31:D28] [D27:D24] [D23:D20] [D19:D16] [D15:D12] [D11:D8] [D7:D4] [D3:D0] 32 8 Complex 1 Q1 I1 Q0 I0 2 Q3 I3 Q2 I2 Datapath Configuration CMOS Pin Mapping BW DW Format DCO [D31:D28] [D27:D24] [D23:D20] [D19:D16] [D15:D12] [D11:D8] [D7:D4] [D3:D0] 32 16 Complex 1 Q0 I0 2 Q1 I1 3 Q2 I2 4 Q3 I3 Rev. A | Page 70 of 76 AD9789 In DDR mode, “rise” corresponds to data sampled on the rising edge of DSC; “fall” corresponds to data sampled on the falling edge of DSC. Table 97. Channelizer Mode Configurations and Channel Construction: LVDS Interface, Channel Prioritization = 1 Datapath Configuration LVDS Pin Mapping BW DW Format DCO [D15:D12] [D11:D8] [D7:D4] [D3:D0] 4 8 Real 1 R0 2 R0 3 R1 4 R1 5 R2 6 R2 7 R3 8 R3 Datapath Configuration LVDS Pin Mapping BW DW Format DCO [D15:D12] [D11:D8] [D7:D4] [D3:D0] 4 8 Complex 1 I0 2 I0 3 Q0 4 Q0 5 I1 6 I1 7 Q1 8 Q1 9 I2 10 I2 11 Q2 12 Q2 13 I3 14 I3 15 Q3 16 Q3 Datapath Configuration LVDS Pin Mapping BW DW Format DCO [D15:D12] [D11:D8] [D7:D4] [D3:D0] 8 8 Real 1 R0 2 R1 3 R2 4 R3 Datapath Configuration LVDS Pin Mapping BW DW Format DCO [D15:D12] [D11:D8] [D7:D4] [D3:D0] 8 8 Complex 1 I0 2 Q0 3 I1 4 Q1 5 I2 6 Q2 7 I3 8 Q3 Rev. A | Page 71 of 76 AD9789 Datapath Configuration LVDS Pin Mapping BW DW Format DCO [D15:D12] [D11:D8] [D7:D4] [D3:D0] 8 16 Complex 1 I0 2 I0 3 Q0 4 Q0 5 I1 6 I1 7 Q1 8 Q1 9 I2 10 I2 11 Q2 12 Q2 13 I3 14 I3 15 Q3 16 Q3 Datapath Configuration LVDS Pin Mapping BW DW Format DCO [D15:D12] [D11:D8] [D7:D4] [D3:D0] 16 8 Real 1 R1 R0 2 R3 R2 Datapath Configuration LVDS Pin Mapping BW DW Format DCO [D15:D12] [D11:D8] [D7:D4] [D3:D0] 16 8 Complex 1 Q0 I0 2 Q1 I1 3 Q2 I2 4 Q3 I3 Datapath Configuration LVDS Pin Mapping BW DW Format DCO [D15:D12] [D11:D8] [D7:D4] [D3:D0] 16 16 Complex 1 I0 2 Q0 3 I1 4 Q1 5 I2 6 Q2 7 I3 8 Q3 Datapath Configuration LVDS Pin Mapping BW DW Format DCO [D15:D12] [D11:D8] [D7:D4] [D3:D0] 32 8 Real 1 rise R1 R0 1 fall R3 R2 Datapath Configuration LVDS Pin Mapping BW DW Format DCO [D15:D12] [D11:D8] [D7:D4] [D3:D0] 32 8 Complex 1 rise Q0 I0 1 fall Q1 I1 2 rise Q2 I2 2 fall Q3 I3 Rev. A | Page 72 of 76 AD9789 Datapath Configuration LVDS Pin Mapping BW DW Format DCO [D15:D12] [D11:D8] [D7:D4] [D3:D0] 32 16 Complex 1 rise I0 1 fall Q0 2 rise I1 2 fall Q1 3 rise I2 3 fall Q2 4 rise I3 4 fall Q3 Rev. A | Page 73 of 76 AD9789 OUTLINE DIMENSIONS 12.00 BSC SQ A1 BALL 14 12 10 8 6 4 2 13 11 9 7 5 3 1 CORNER A B C D E 10.40 F BSC SQ G H J 0.80 K BSC L M N P 0.80 TOP VIEW BOTTOM VIEW REF DETAIL A 0.96 * 1.30 0.89 1.22 0.82 DETAIL A 1.14 0.65 REF 0.38 0.33 0.28 0.24 REF 0.53 SEATING COPLANARITY PLANE 0.08 0.48 0.43 BALL DIAMETER * COMPLIANT TO JEDEC STANDARDS MO-219 WITH THE EXCEPTION TO PACKAGE HEIGHT. Figure 130. 164-Ball Chip Scale Package Ball Grid Array [CSP_BGA] (BC-164-1) Dimensions shown in millimeters ORDERING GUIDE 1 Model Temperature Range Package Description Package Option AD9789BBCZ −40°C to +85°C 164-Ball Chip Scale Package Ball Grid Array (CSP_BGA) BC-164-1 AD9789BBCZRL −40°C to +85°C 164-Ball Chip Scale Package Ball Grid Array (CSP_BGA) BC-164-1 AD9789BBC −40°C to +85°C 164-Ball Chip Scale Package Ball Grid Array (CSP_BGA) BC-164-1 AD9789BBCRL −40°C to +85°C 164-Ball Chip Scale Package Ball Grid Array (CSP_BGA) BC-164-1 AD9789-EBZ Evaluation Board for CMTS and Normal Mode Evaluation AD9789-MIX-EBZ Evaluation Board for Mix Mode Evaluation 1 Z = RoHS Compliant Part. Rev. A | Page 74 of 76 111808-A AD9789 NOTES Rev. A | Page 75 of 76 AD9789 NOTES ©2009-2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07852-0-7/11(A) Rev. A | Page 76 of 76