ANALOG DEVICES AD9787

Dual 12-/14-/16-Bit 800 MSPS DAC with Low Power 32-Bit Complex NCO AD9785/AD9787/AD9788 FEATURES GENERAL DESCRIPTION Analog output: adjustable 8.7 mA to 31.7 mA, The AD9785/AD9787/AD9788 are 12-bit, 14-bit, and 16-bit, R = 25 Ω to 50 Ω L high dynamic range TxDAC® devices, respectively, that provide Low power, fine complex NCO allows carrier placement a sample rate of 800 MSPS, permitting multicarrier generation anywhere in DAC bandwidth while adding <300 mW power up to the Nyquist frequency. Features are included for optimizing Auxiliary DACs allow I and Q gain matching and offset control direct conversion transmit applications, including complex Includes programmable I and Q phase compensation digital modulation, as well as gain, phase, and offset compens- Internal digital upconversion capability ation. The DAC outputs are optimized to interface seamlessly Multiple chip synchronization interface with analog quadrature modulators, such as the ADL537x High performance, low noise PLL clock multiplier family from Analog Devices, Inc. A serial peripheral interface Digital inverse sinc filter (SPI) provides for programming and readback of many internal 100-lead, exposed paddle TQFP package parameters. Full-scale output current can be programmed over a range of 10 mA to 30 mA. The AD978x family is manufactured APPLICATIONS on a 0.18 μm CMOS process and operates from 1.8 V and 3.3 V Wireless infrastructure supplies. It is enclosed in a 100-lead TQFP package. WCDMA, CDMA2000, TD-SCDMA, WiMAX, GSM PRODUCT HIGHLIGHTS Digital high or low IF synthesis Transmit diversity 1. Low noise and intermodulation distortion (IMD) enable Wideband communications high quality synthesis of wideband signals from baseband LMDS/MMDS, point-to-point to high intermediate frequencies. 2. Proprietary DAC output switching technique enhances dynamic performance. 3. CMOS data input interface with adjustable setup and hold. 4. Low power complex 32-bit numerically controlled oscillators (NCOs). TYPICAL SIGNAL CHAIN QUADRATURE MODULATOR/ COMPLEX I AND Q MIXER/ AMPLIFIER LO DC DC DIGITAL INTERPOLATION FILTERS I DAC POST DAC FPGA/ASIC/DSP ANALOG FILTER Q DAC A Figure 1. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2008–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 07098-001 AD9785/AD9787/AD9788 TABLE OF CONTENTS Features .............................................................................................. 1  Input Data RAM ......................................................................... 37  Applications ....................................................................................... 1  Digital Datapath ............................................................................. 38  General Description ......................................................................... 1  Interpolation Filters ................................................................... 38  Product Highlights ........................................................................... 1  Quadrature Modulator .............................................................. 40  Typical Signal Chain ......................................................................... 1  Numerically Controlled Oscillator .......................................... 40  Revision History ............................................................................... 2  Inverse Sinc Filter ....................................................................... 40  Specif ica t ions ..................................................................................... 3  Digital Amplitude and Offset Control .................................... 41  DC Specifications ......................................................................... 3  Digital Phase Correction ........................................................... 41  Digital Specifications ................................................................... 4  Device Synchronization ................................................................. 42  AC Specifications .......................................................................... 5  Synchronization Logic Overview ............................................. 42  Absolute Maximum Ratings ............................................................ 6  Synchronizing Devices to a System Clock .............................. 44  Thermal Resistance ...................................................................... 6  Synchronizing Multiple Devices to Each Other ..................... 45  ESD Caution .................................................................................. 6  Interrupt Request Operation .................................................... 46  Pin Configurations and Function Descriptions ........................... 7  Driving the REFCLK Input ........................................................... 47  Typical Performance Characteristics ........................................... 13  DAC REFCLK Configuration ................................................... 47  Terminology .................................................................................... 20  Analog Outputs............................................................................... 50  Theory of Operation ...................................................................... 21  Digital Amplitude Scaling ......................................................... 50  Serial Port Interface .................................................................... 21  Power Dissipation ........................................................................... 52  SPI Register Map ............................................................................. 24  AD9785/AD9787/AD9788 Evaluation Boards........................... 54  SPI Register Descriptions .......................................................... 25  Output Configuration ................................................................ 54  Input Data Ports .............................................................................. 33  Digital Picture of Evaluation Board ......................................... 54  Single-Port Mode ........................................................................ 33  Evaluation Board Software ........................................................ 55  Dual-Port Mode .......................................................................... 33  Evaluation Board Schematics ................................................... 56  Input Data Referenced to DATACLK ...................................... 33  Outline Dimensions ....................................................................... 62  Input Data Referenced to REFCLK .......................................... 35  Ordering Guide .......................................................................... 62  Optimizing the Data Input Timing .......................................... 36  REVISION HISTORY 2/09—Rev. 0 to Rev. A Changes to Table 13 ....................................................................... 28 Added Settling Time, to Within ±0.5 LSBs Parameter, Table 1 .. 3 Changes to Table 22 ....................................................................... 32 Added REFCLK Frequency Range, PLL Enabled Parameter, Changes to Dual-Port Mode Section ........................................... 33 Table 2 ................................................................................................ 4 Changes to Input Data RAM Section .......................................... 37 Changes to SPI_SDIO—Serial Data I/O Section ....................... 23 Changes to Digital Amplitude and Offset Control Section ...... 41 Changes to Table 9 .......................................................................... 24 Changes to Direct Clocking Section ............................................ 47 Changes to Table 11 ........................................................................ 26 Changes to Table 12 ........................................................................ 27 1/08—Revision 0: Initial Version Rev. A | Page 2 of 64 AD9785/AD9787/AD9788 SPECIFICATIONS DC SPECIFICATIONS T to T , AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, I = 20 mA, maximum sample rate, unless MIN MAX OUTFS otherwise noted. LVDS driver and receiver are compliant to the IEEE 1596 reduced range link, unless otherwise noted. Table 1. AD9785 AD9787 AD9788 Parameter Min Typ Max Min Typ Max Min Typ Max Unit RESOLUTION 12 14 16 Bits ACCURACY Differential Nonlinearity (DNL) ±0.2 ±0.5 ±2.1 LSB Integral Nonlinearity (INL) ±0.3 ±1.0 ±3.7 LSB MAIN DAC OUTPUTS Offset Error –0.001 0 +0.001 −0.001 0 +0.001 −0.001 0 +0.001 % FSR Gain Error (with Internal Reference) ±2 ±2 ±2 % FSR Full-Scale Output Current 8.66 20.2 31.66 8.66 20.2 31.66 8.66 20.2 31.66 mA Output Compliance Range –1.0 +1.0 –1.0 +1.0 –1.0 +1.0 V Output Resistance 10 10 10 MΩ Gain DAC Monotonicity 10 10 10 Bits Guaranteed Settling Time, to Within ±0.5 LSBs 20 20 20 ns MAIN DAC TEMPERATURE DRIFT Offset 0.04 0.04 0.04 ppm/°C Gain 100 100 100 ppm/°C Reference Voltage 30 30 30 ppm/°C AUX DAC OUTPUTS Resolution 10 10 10 Bits 1 Full-Scale Output Current –1.998 +1.998 –1.998 +1.998 –1.998 +1.998 mA Output Compliance Range (Source) 0 1.6 0 1.6 0 1.6 V Output Compliance Range (Sink) 0.8 1.6 0.8 1.6 0.8 1.6 V Output Resistance 1 1 1 MΩ Aux DAC Monotonicity Guaranteed 10 10 10 Bits REFERENCE Internal Reference Voltage 1.2 1.2 1.2 V Output Resistance 5 5 5 kΩ ANALOG SUPPLY VOLTAGES AVDD33 3.13 3.3 3.47 3.13 3.3 3.47 3.13 3.3 3.47 V CVDD18 1.70 1.8 1.90 1.70 1.8 1.90 1.70 1.8 1.90 V DIGITAL SUPPLY VOLTAGES DVDD33 3.13 3.3 3.47 3.13 3.3 3.47 3.13 3.3 3.47 V DVDD18 1.70 1.8 1.90 1.70 1.8 1.90 1.70 1.8 1.90 V POWER CONSUMPTION 1× Mode, f = 100 MSPS, 375 450 375 450 375 450 mW DATA PLL Off, IF = 2 MHz 2× Mode, fDATA = 100 MSPS, 533 533 533 mW Inverse Sinc Off, PLL Off 4× Mode, f = 100 MSPS, 754 754 754 mW DATA Inverse Sinc Off, PLL Off 8× Mode, fDATA = 100 MSPS, 1054 1054 1054 mW Inverse Sinc Off, PLL Off Power-Down Mode 2.5 9.0 2.5 9.0 2.5 9.0 mW OPERATING RANGE –40 +25 +85 –40 +25 +85 –40 +25 +85 °C 1 Based on a 10 Ω external resistor. Rev. A | Page 3 of 64 AD9785/AD9787/AD9788 DIGITAL SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless otherwise noted. Table 2. Parameter Test Conditions/Comments Min Typ Max Unit CMOS INPUT LOGIC LEVEL Input VIN Logic High 2.0 V Input V Logic Low 0.8 V IN LVDS INPUT (SYNC_I+, SYNC_I−) SYNC_I+ = V1A, SYNC_I− = V1B Input Voltage Range, V or V 825 1575 mV IA IB Input Differential Threshold, V –100 +100 mV IDTH Input Differential Hysteresis, V − V 20 mV IDTHH IDTHL Receiver Differential Input Impedance, RIN 80 120 Ω LVDS Input Rate (fSYNC_I = fDATA) 30 MHz Setup Time, SYNC_I to DAC Clock 0.45 ns Hold Time, SYNC _I to DAC Clock 0.25 ns LVDS DRIVER OUTPUTS (SYNC_O+, SYNC_O−) SYNC_O+ = VOA, SYNC_O− = VOB, 100 Ω termination Output Voltage High, V or V 825 1575 mV OA OB Output Voltage Low, V or V 1025 mV OA OB Output Differential Voltage, |V| 150 200 250 mV OD Output Offset Voltage, VOS 1150 1250 mV Output Impedance, Single-Ended, RO 80 100 120 Ω DAC CLOCK INPUT (REFCLK+, REFCLK–) Differential Peak-to-Peak Voltage 400 800 1600 mV Common-Mode Voltage 300 400 500 mV Maximum Clock Rate DVDD18 = 1.8 V ± 5% 800 MHz DVDD18 = 1.9 V ± 5% 900 MHz REFCLK Frequency Range, PLL Enabled 30 250 MHz MAXIMUM INPUT DATA RATE 1× Interpolation 250 MSPS 2× Interpolation 250 MSPS 4× Interpolation DVDD18 = 1.8 V ± 5% 200 MSPS DVDD18 = 1.9 V ± 5% 225 MSPS 8× Interpolation DVDD18 = 1.8 V ±5% 100 MSPS DVDD18 = 1.9 V ± 5% 112.5 MSPS SERIAL PERIPHERAL INTERFACE Maximum Clock Rate (SCLK) 40 MHz Minimum Pulse Width High 12.5 ns Minimum Pulse Width Low 12.5 ns Setup Time, SPI_SDIO to SCLK 2.8 ns Hold Time, SPI_SDIO to SCLK 0.0 ns Setup Time, SPI_CSB to SCLK 3.0 ns Data Valid, SPI_SDO to SCLK 10.0 ns 1 INPUT DATA All modes, −40°C to +85°C Setup Time, Input Data to DATACLK 460 ns Hold Time, Input Data to DATACLK −1.5 ns Setup Time, Input Data to REFCLK −0.25 ns Hold Time, Input Data to REFCLK 2.4 ns Rev. A | Page 4 of 64 AD9785/AD9787/AD9788 Parameter Test Conditions/Comments Min Typ Max Unit LATENCY (DACCLK CYCLES) 1× Interpolation With or without modulation 40 Cycles 2× Interpolation With or without modulation 83 Cycles 4× Interpolation With or without modulation 155 Cycles 8× Interpolation With or without modulation 294 Cycles Inverse Sinc 18 Cycles 2 POWER-UP TIME 260 ms 3 DAC Wake-Up Time I current settling to 1% 22 ms OUT 4 DAC Sleep Time IOUT current to less than 1% of full scale 22 ms 1 Timing vs. temperature and data valid windows are delineated in Table 25. 2 Measured from SPI_CSB rising edge on Register 0x00; toggle Bit 4 from 0 to 1. VREF decoupling capacitor = 0.1 μF. 3 Measured from SPI_CSB rising edge on Register 0x05 or Register 0x07; toggle Bit 15 or Bit 14 from 0 to 1. 4 Measured from SPI_CSB rising edge on Register 0x05 or Register 0x07; toggle Bit 15 or Bit 14 from 1 to 0. AC SPECIFICATIONS T to T , AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, I = 20 mA, maximum sample rate, unless MIN MAX OUTFS otherwise noted. Table 3. AD9785 AD9787 AD9788 Parameter Min Typ Max Min Typ Max Min Typ Max Unit SPURIOUS-FREE DYNAMIC RANGE (IN-BAND SFDR) fDACCLK = 200 MSPS, fOUT = 70 MHz 1× Interpolation 80 82 83 dBc fDACCLK = 200 MSPS, fOUT = 70 MHz 2× Interpolation 80 82 83 dBc fDACCLK = 200 MSPS, fOUT = 70 MHz 4× Interpolation 78 80 81 dBc f = 800 MSPS, f = 40 MHz 8× Interpolation 85 87 90 dBc DACCLK OUT TWO-TONE INTERMODULATION DISTORTION (IMD) fDATA = 200 MSPS, fOUT = 50 MHz 1× Interpolation 80 82 83 dBc f = 200 MSPS, f = 50 MHz 2× Interpolation 78 79 80 dBc DATA OUT f = 200 MSPS, f = 100 MHz 4× Interpolation 78 79 80 dBc DATA OUT f = 100 MSPS, f = 100 MHz 8× Interpolation 70 70 70 dBc DATA OUT NOISE SPECTRAL DENSITY (NSD), EIGHT TONE, 500 kHz TONE SPACING fDACCLK = 200 MSPS, fOUT = 80 MHz −154 −157 −158 dBm/Hz fDACCLK = 400 MSPS, fOUT = 80 MHz −154 −158 −161 dBm/Hz fDACCLK = 800 MSPS, fOUT = 80 MHz −154 −159 −162 dBm/Hz WCDMA ADJACENT CHANNEL LEAKAGE RATIO (ACLR), SINGLE CARRIER fDACCLK = 491.52 MSPS, fOUT = 100 MHz 4× Interpolation 78 80 82 dBc f = 491.52 MSPS, f = 200 MHz 4× Interpolation 72 74 76 dBc DACCLK OUT WCDMA SECOND ADJACENT CHANNEL LEAKAGE RATIO (ACLR), SINGLE CARRIER f = 491.52 MSPS, f = 100 MHz 4× Interpolation 80 82 88 dBc DACCLK OUT f = 491.52 MSPS, f = 200 MHz 4× Interpolation 78 80 82 dBc DACCLK OUT Rev. A | Page 5 of 64 AD9785/AD9787/AD9788 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter Rating THERMAL RESISTANCE AVDD33 to AGND, DGND, CGND −0.3 V to +3.6 V For this 100-lead, thermally enhanced TQFP, the exposed paddle DVDD33, DVDD18, CVDD18 −0.3 V to +2.1 V (EPAD) must be soldered to the ground plane. Note that these to AGND, DGND, CGND specifications are valid with no airflow movement. AGND to DGND, CGND −0.3 V to +0.3 V DGND to AGND, CGND −0.3 V to +0.3 V Table 5. Thermal Resistance CGND to AGND, DGND −0.3 V to +0.3 V Resistance Unit Conditions I120, VREF, IPTAT to AGND −0.3 V to AVDD33 + 0.3 V θ 19.1°C/W EPAD soldered. No airflow. JA OUT1_P, OUT1_N, OUT2_P, OUT2_N, −1.0 V to AVDD33 + 0.3 V θ 12.4°C/W EPAD soldered. No airflow. JB AUX1_P, AUX1_N, AUX2_P, θJC 7.1°C/W EPAD soldered. No airflow. AUX2_N to AGND P1D[15] to P1D[0], P2D[15] to P2D[0] −0.3 V to DVDD33 + 0.3 V to DGND ESD CAUTION DATACLK, TXENABLE to DGND −0.3 V to DVDD33 + 0.3 V −0.3 V to CVDD18 + 0.3 V REFCLK+, REFCLK−, RESET, IRQ, PLL_LOCK, SYNC_O+, SYNC_O−, SYNC_I+, SYNC_I− to CGND RESET, IRQ, PLL_LOCK, SYNC_O+, −0.3 V to DVDD33 + 0.3 V SYNC_O−, SYNC_I+, SYNC_I−, SPI_CSB, SCLK, SPI_SDIO, SPI_SDO to DGND Junction Temperature 125°C Storage Temperature Range −65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. A | Page 6 of 64 AD9785/AD9787/AD9788 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 75 CVDD18 I120 PIN 1 INDICATOR CVDD18 2 74 VREF CGND 3 73 IPTAT ANALOG DOMAIN CGND 4 72 AGND REFCLK+ 5 71 IRQ REFCLK– 6 DIGITAL DOMAIN 70 RESET CGND 7 69 SPI_CSB CGND 8 68 SCLK CVDD18 9 AD9785 67 SPI_SDIO CVDD18 10 66 SPI_SDO TOP VIEW 11 (Not to Scale) 65 CGND PLL_LOCK 12 64 AGND DGND 13 63 SYNC_I+ SYNC_O+ 14 62 SYNC_I– SYNC_O– 15 61 DGND DVDD33 16 60 DVDD18 DVDD18 17 59 P1D[11] NC 18 58 P1D[10] NC 19 57 P1D[9] NC P1D[8] 20 56 NC P1D[7] 21 55 P2D[0] DGND 22 54 DGND DVDD18 23 53 DVDD18 P1D[6] 24 52 P2D[1] P1D[5] 25 51 P2D[2] 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC = NO CONNECT Figure 2. AD9785 Pin Configuration Table 6. AD9785 Pin Function Descriptions Pin No. Mnemonic Description 1, 2, 9, 10 CVDD18 1.8 V Clock Supply. 3, 4, 7, 8, 11 CGND Clock Common. 5 REFCLK+ Differential Clock Input, Positive. 6 REFCLK− Differential Clock Input, Negative. 12, 72, 77, 79, 81, 82, 85, AGND Analog Common. 88, 91, 94, 95, 97, 99 13 SYNC_I+ Differential Synchronization Input, Positive. 14 SYNC_I− Differential Synchronization Input, Negative. 15, 22, 32, 44, 54, 64 DGND Digital Common. 16, 23, 33, 43, 53, 60 DVDD18 1.8 V Digital Supply. 17 P1D[11] Port 1, Data Input D11 (MSB). 18 P1D[10] Port 1, Data Input D10. 19 P1D[9] Port 1, Data Input D9. 20 P1D[8] Port 1, Data Input D8. 21 P1D[7] Port 1, Data Input D7. 24 P1D[6] Port 1, Data Input D6. 25 P1D[5] Port 1, Data Input D5. 26 P1D[4] Port 1, Data Input D4. 27 P1D[3] Port 1, Data Input D3. 28 P1D[2] Port 1, Data Input D2. Rev. A | Page 7 of 64 P1D[4] AVDD33 P1D[3] AGND P1D[2] AVDD33 P1D[1] AGND P1D[0] AVDD33 NC AGND DGND AGND DVDD18 OUT1_P NC OUT1_N NC AGND NC AUX1_P DATACLK AUX1_N DVDD33 AGND TXENABLE AUX2_N P2D[11] AUX2_P P2D[10] AGND P2D[9] OUT2_N DVDD18 OUT2_P DGND AGND P2D[8] AGND P2D[7] AVDD33 P2D[6] AGND P2D[5] AVDD33 P2D[4] AGND P2D[3] AVDD33 07098-005 AD9785/AD9787/AD9788 Pin No. Mnemonic Description 29 P1D[1] Port 1, Data Input D1. 30 P1D[0] Port 1, Data Input D0 (LSB). 31, 34 to 36, 56 to 59 NC No Connection Necessary. 37 DATACLK Data Clock Output. 38, 61 DVDD33 3.3 V Digital Supply. 39 TXENABLE Transmit Enable. 40 P2D[11] Port 2, Data Input D11 (MSB). 41 P2D[10] Port 2, Data Input D10. 42 P2D[9] Port 2, Data Input D9. 45 P2D[8] Port 2, Data Input D8. 46 P2D[7] Port 2, Data Input D7. 47 P2D[6] Port 2, Data Input D6. 48 P2D[5] Port 2, Data Input D5. 49 P2D[4] Port 2, Data Input D4. 50 P2D[3] Port 2, Data Input D3. 51 P2D[2] Port 2, Data Input D2. 52 P2D[1] Port 2, Data Input D1. 55 P2D[0] Port 2, Data Input D0 (LSB). 62 SYNC_O− Differential Synchronization Output, Negative. 63 SYNC_O+ Differential Synchronization Output, Positive. 65 PLL_LOCK PLL Lock Indicator. 66 SPI_SDO SPI Port Data Output. 67 SPI_SDIO SPI Port Data Input/Output. 68 SCLK SPI Port Clock. 69 SPI_CSB SPI Port Chip Select Bar. 70 RESET Reset, Active High. 71 IRQ Interrupt Request. 73 IPTAT Factory Test Pin. Output current is proportional to absolute temperature, approximately 10 μA at 25°C with approximately 20 nA/°C slope. This pin should remain floating. 74 VREF Voltage Reference Output. 75 I120 120 μA Reference Current. 76, 78, 80, 96, 98, 100 AVDD33 3.3 V Analog Supply. 83 OUT2_P Differential DAC Current Output, Positive, Channel 2. 84 OUT2_N Differential DAC Current Output, Negative, Channel 2. 86 AUX2_P Auxiliary DAC Current Output, Positive, Channel 2. 87 AUX2_N Auxiliary DAC Current Output, Negative, Channel 2. 89 AUX1_N Auxiliary DAC Current Output, Negative, Channel 1. 90 AUX1_P Auxiliary DAC Current Output, Positive, Channel 1. 92 OUT1_N Differential DAC Current Output, Negative, Channel 1. 93 OUT1_P Differential DAC Current Output, Positive, Channel 1. Exposed Paddle EPAD Conductive Heat Sink. Connect to analog common (AGND). Rev. A | Page 8 of 64 AD9785/AD9787/AD9788 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 75 CVDD18 I120 PIN 1 INDICATOR CVDD18 2 74 VREF 3 73 CGND IPTAT ANALOG DOMAIN 4 72 CGND AGND 5 71 REFCLK+ IRQ 6 70 REFCLK– DIGITAL DOMAIN RESET 7 69 CGND SPI_CSB CGND 8 68 SCLK CVDD18 9 67 SPI_SDIO AD9787 10 66 CVDD18 SPI_SDO TOP VIEW (Not to Scale) 11 65 CGND PLL_LOCK 12 64 AGND DGND SYNC_I+ 13 63 SYNC_O+ SYNC_I– 14 62 SYNC_O– DGND 15 61 DVDD33 DVDD18 16 60 DVDD18 P1D[13] 17 59 NC P1D[12] 18 58 NC 19 57 P1D[11] P2D[0] 20 56 P1D[10] P2D[1] 21 55 P1D[9] P2D[2] 22 54 DGND DGND 23 53 DVDD18 DVDD18 24 52 P1D[8] P2D[3] 25 51 P1D[7] P2D[4] 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC = NO CONNECT Figure 3. AD9787 Pin Configuration Table 7. AD9787 Pin Function Descriptions Pin No. Mnemonic Description 1, 2, 9, 10 CVDD18 1.8 V Clock Supply. 3, 4, 7, 8, 11 CGND Clock Common. 5 REFCLK+ Differential Clock Input, Positive. 6 REFCLK− Differential Clock Input, Negative. 12, 72, 77, 79, 81, 82, 85, AGND Analog Common. 88, 91, 94, 95, 97, 99 13 SYNC_I+ Differential Synchronization Input, Positive. 14 SYNC_I− Differential Synchronization Input, Negative. 15, 22, 32, 44, 54, 64 DGND Digital Common. 16, 23, 33, 43, 53, 60 DVDD18 1.8 V Digital Supply. 17 P1D[13] Port 1, Data Input D13 (MSB). 18 P1D[12] Port 1, Data Input D12. 19 P1D[11] Port 1, Data Input D11. 20 P1D[10] Port 1, Data Input D10. 21 P1D[9] Port 1, Data Input D9. 24 P1D[8] Port 1, Data Input D8. 25 P1D[7] Port 1, Data Input D7. 26 P1D[6] Port 1, Data Input D6. 27 P1D[5] Port 1, Data Input D5. 28 P1D[4] Port 1, Data Input D4. 29 P1D[3] Port 1, Data Input D3. 30 P1D[2] Port 1, Data Input D2. Rev. A | Page 9 of 64 P1D[6] AVDD33 P1D[5] AGND P1D[4] AVDD33 P1D[3] AGND P1D[2] AVDD33 P1D[1] AGND DGND AGND DVDD18 OUT1_P P1D[0] OUT1_N NC AGND NC AUX1_P DATACLK AUX1_N DVDD33 AGND TXENABLE AUX2_N P2D[13] AUX2_P P2D[12] AGND P2D[11] OUT2_N DVDD18 OUT2_P DGND AGND P2D[10] AGND P2D[9] AVDD33 P2D[8] AGND P2D[7] AVDD33 P2D[6] AGND P2D[5] AVDD33 07098-004 AD9785/AD9787/AD9788 Pin No. Mnemonic Description 31 P1D[1] Port 1, Data Input D1. 34 P1D[0] Port 1, Data Input D0 (LSB). 35, 36, 58, 59 NC No Connection Necessary. 37 DATACLK Data Clock Output. 38, 61 DVDD33 3.3 V Digital Supply. 39 TXENABLE Transmit Enable. 40 P2D[13] Port 2, Data Input D13 (MSB). 41 P2D[12] Port 2, Data Input D12. 42 P2D[11] Port 2, Data Input D11. 45 P2D[10] Port 2, Data Input D10. 46 P2D[9] Port 2, Data Input D9. 47 P2D[8] Port 2, Data Input D8. 48 P2D[7] Port 2, Data Input D7. 49 P2D[6] Port 2, Data Input D6. 50 P2D[5] Port 2, Data Input D5. 51 P2D[4] Port 2, Data Input D4. 52 P2D[3] Port 2, Data Input D3. 55 P2D[2] Port 2, Data Input D2. 56 P2D[1] Port 2, Data Input D1. 57 P2D[0] Port 2, Data Input D0 (LSB). 62 SYNC_O− Differential Synchronization Output, Negative. 63 SYNC_O+ Differential Synchronization Output, Positive. 65 PLL_LOCK PLL Lock Indicator. 66 SPI_SDO SPI Port Data Output. 67 SPI_SDIO SPI Port Data Input/Output. 68 SCLK SPI Port Clock. 69 SPI_CSB SPI Port Chip Select Bar. 70 RESET Reset, Active High. 71 IRQ Interrupt Request. 73 IPTAT Factory Test Pin. Output current is proportional to absolute temperature, approximately 10 μA at 25°C with approximately 20 nA/°C slope. This pin should remain floating. 74 VREF Voltage Reference Output. 75 I120 120 μA Reference Current. 76, 78, 80, 96, 98, 100 AVDD33 3.3 V Analog Supply. 83 OUT2_P Differential DAC Current Output, Positive, Channel 2. 84 OUT2_N Differential DAC Current Output, Negative, Channel 2. 86 AUX2_P Auxiliary DAC Current Output, Positive, Channel 2. 87 AUX2_N Auxiliary DAC Current Output, Negative, Channel 2. 89 AUX1_N Auxiliary DAC Current Output, Negative, Channel 1. 90 AUX1_P Auxiliary DAC Current Output, Positive, Channel 1. 92 OUT1_N Differential DAC Current Output, Negative, Channel 1. 93 OUT1_P Differential DAC Current Output, Positive, Channel 1. Exposed Paddle EPAD Conductive Heat Sink. Connect to analog common (AGND). Rev. A | Page 10 of 64 AD9785/AD9787/AD9788 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 CVDD18 1 75 I120 PIN 1 INDICATOR CVDD18 2 74 VREF 3 73 CGND IPTAT ANALOG DOMAIN 4 72 CGND AGND 5 71 REFCLK+ IRQ 6 70 REFCLK– DIGITAL DOMAIN RESET 7 69 CGND SPI_CSB 8 68 CGND SCLK CVDD18 9 67 SPI_SDIO AD9788 10 66 CVDD18 SPI_SDO TOP VIEW 11 (Not to Scale) 65 CGND PLL_LOCK 12 64 AGND DGND SYNC_I+ 13 63 SYNC_O+ SYNC_I– 14 62 SYNC_O– DGND 15 61 DVDD33 DVDD18 16 60 DVDD18 P1D[15] 17 59 P2D[0] P1D[14] 18 58 P2D[1] P1D[13] 19 57 P2D[2] 20 56 P1D[12] P2D[3] 21 55 P1D[11] P2D[4] 22 54 DGND DGND 23 53 DVDD18 DVDD18 24 52 P1D[10] P2D[5] 25 51 P1D[9] P2D[6] 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Figure 4. AD9788 Pin Configuration Table 8. AD9788 Pin Function Descriptions Pin No. Mnemonic Description 1, 2, 9, 10 CVDD18 1.8 V Clock Supply. 3, 4, 7, 8, 11 CGND Clock Common. 5 REFCLK+ Differential Clock Input, Positive. 6 REFCLK− Differential Clock Input, Negative. 12, 72, 77, 79, 81, 82, 85, AGND Analog Common. 88, 91, 94, 95, 97, 99 13 SYNC_I+ Differential Synchronization Input, Positive. 14 SYNC_I− Differential Synchronization Input, Negative. 15, 22, 32, 44, 54, 64 DGND Digital Common. 16, 23, 33, 43, 53, 60 DVDD18 1.8 V Digital Supply. 17 P1D[15] Port 1, Data Input D15 (MSB). 18 P1D[14] Port 1, Data Input D14. 19 P1D[13] Port 1, Data Input D13. 20 P1D[12] Port 1, Data Input D12. 21 P1D[11] Port 1, Data Input D11. 24 P1D[10] Port 1, Data Input D10. 25 P1D[9] Port 1, Data Input D9. 26 P1D[8] Port 1, Data Input D8. 27 P1D[7] Port 1, Data Input D7. 28 P1D[6] Port 1, Data Input D6. 29 P1D[5] Port 1, Data Input D5. 30 P1D[4] Port 1, Data Input D4. Rev. A | Page 11 of 64 P1D[8] AVDD33 P1D[7] AGND P1D[6] AVDD33 P1D[5] AGND P1D[4] AVDD33 P1D[3] AGND DGND AGND DVDD18 OUT1_P P1D[2] OUT1_N P1D[1] AGND P1D[0] AUX1_P DATACLK AUX1_N DVDD33 AGND TXENABLE AUX2_N P2D[15] AUX2_P P2D[14] AGND P2D[13] OUT2_N DVDD18 OUT2_P DGND AGND P2D[12] AGND P2D[11] AVDD33 P2D[10] AGND P2D[9] AVDD33 P2D[8] AGND P2D[7] AVDD33 07098-003 AD9785/AD9787/AD9788 Pin No. Mnemonic Description 31 P1D[3] Port 1, Data Input D3. 34 P1D[2] Port 1, Data Input D2. 35 P1D[1] Port 1, Data Input D1. 36 P1D[0] Port 1, Data Input D0 (LSB). 37 DATACLK Data Clock Output. 38, 61 DVDD33 3.3 V Digital Supply. 39 TXENABLE Transmit Enable. 40 P2D[15] Port 2, Data Input D15 (MSB). 41 P2D[14] Port 2, Data Input D14. 42 P2D[13] Port 2, Data Input D13. 45 P2D[12] Port 2, Data Input D12. 46 P2D[11] Port 2, Data Input D11. 47 P2D[10] Port 2, Data Input D10. 48 P2D[9] Port 2, Data Input D9. 49 P2D[8] Port 2, Data Input D8. 50 P2D[7] Port 2, Data Input D7. 51 P2D[6] Port 2, Data Input D6. 52 P2D[5] Port 2, Data Input D5. 55 P2D[4] Port 2, Data Input D4. 56 P2D[3] Port 2, Data Input D3. 57 P2D[2] Port 2, Data Input D2. 58 P2D[1] Port 2, Data Input D1. 59 P2D[0] Port 2, Data Input D0 (LSB). 62 SYNC_O− Differential Synchronization Output, Negative. 63 SYNC_O+ Differential Synchronization Output, Positive. 65 PLL_LOCK PLL Lock Indicator. 66 SPI_SDO SPI Port Data Output. 67 SPI_SDIO SPI Port Data Input/Output. 68 SCLK SPI Port Clock. 69 SPI_CSB SPI Port Chip Select Bar. 70 RESET Reset, Active High. 71 IRQ Interrupt Request. 73 IPTAT Factory Test Pin. Output current is proportional to absolute temperature, approximately 10 μA at 25°C with approximately 20 nA/°C slope. This pin should remain floating. 74 VREF Voltage Reference Output. 75 I120 120 μA Reference Current. 76, 78, 80, 96, 98, 100 AVDD33 3.3 V Analog Supply. 83 OUT2_P Differential DAC Current Output, Positive, Channel 2. 84 OUT2_N Differential DAC Current Output, Negative, Channel 2. 86 AUX2_P Auxiliary DAC Current Output, Positive, Channel 2. 87 AUX2_N Auxiliary DAC Current Output, Negative, Channel 2. 89 AUX1_N Auxiliary DAC Current Output, Negative, Channel 1. 90 AUX1_P Auxiliary DAC Current Output, Positive, Channel 1. 92 OUT1_N Differential DAC Current Output, Negative, Channel 1. 93 OUT1_P Differential DAC Current Output, Positive, Channel 1. Exposed Paddle EPAD Conductive Heat Sink. Connect to analog common (AGND). Rev. A | Page 12 of 64 AD9785/AD9787/AD9788 TYPICAL PERFORMANCE CHARACTERISTICS –142 100 95 200 MSPS –146 250 MSPS 4× 90 –150 85 2× 160 MSPS 80 –154 75 1× –158 70 65 –162 60 –166 55 –170 50 0 20 40 60 80 100 0 20 40 60 80 100 f (MHz) f (MHz) OUT OUT Figure 5. AD9785 Noise Spectral Density vs. fOUT, Multitone Input, Figure 8. AD9785 In-Band SFDR vs. fOUT, 2× Interpolation fDATA = 200 MSPS –142 100 –146 90 2× 150 MSPS –150 4× 80 –154 –158 1× 70 –162 100 MSPS 60 200 MSPS –166 –170 50 0 20 40 60 80 100 0 40 80 120 160 200 240 280 320 360 400 f (MHz) f (MHz) OUT OUT Figure 6. AD9785 Noise Spectral Density vs. fOUT, Single-Tone Input, Figure 9. AD9785 IMD vs. fOUT, 4× Interpolation fDATA = 200 MSPS –55 –55 –60 –60 –65 –65 FIRST ADJ CHAN –70 –70 FIRST ADJ CHAN –75 –75 SECOND ADJ CHAN SECOND ADJ CHAN –80 –80 –85 –85 THIRD ADJ CHAN THIRD ADJ CHAN –90 –90 0 20 40 60 80 100 120 140 160 180 200 220 240 260 0 20 40 60 80 100 120 140 160 180 200 220 240 260 f (MHz) f (MHz) OUT OUT Figure 10. AD9787 ACLR, 4× Interpolation, f = 122.88 MSPS Figure 7. AD9785 ACLR, 4× Interpolation, fDATA = 122.88 MSPS DATA Rev. A | Page 13 of 64 ACLR (dBc) NSD (dBm/Hz) NSD (dBm/Hz) 07098-066 07098-065 07098-064 ACLR (dBc) IMD (dBc) SFDR (dB) 07098-069 07098-068 07098-067 AD9785/AD9787/AD9788 –55 –142 –60 –146 –65 –150 –70 –154 FIRST ADJ CHAN –75 –158 1× 2× SECOND ADJ CHAN 4× –162 –80 –85 –166 THIRD ADJ CHAN –170 –90 0 0 20 40 60 80 100 120 140 160 180 200 220 240 260 20 40 60 80 100 f (MHz) f (MHz) OUT OUT Figure 14. AD9787 Noise Spectral Density vs. fOUT over Output Frequency of Figure 11. AD9787 ACLR, 4× Interpolation, fDATA = 122.88 MSPS, Multitone Input, fDATA = 200 MSPS Amplitude = −3 dB –142 100 –146 90 –150 80 –154 200MSPS 1× 100MSPS –158 70 2× 4× 150MSPS –162 60 –166 –170 50 0 20 40 60 80 100 0 40 80 120 160 200 240 280 320 360 400 f (MHz) f (MHz) OUT OUT Figure 15. AD9787 Noise Spectral Density vs. f , Single-Tone Input, Figure 12. AD9787 IMD vs. f , 4× Interpolation OUT OUT f = 200 MSPS DATA 100 –55 95 –60 0 dBFS PLL ON 90 160MSPS –65 85 250MSPS 80 –70 200MSPS 0 dBFS PLL OFF 75 –3 dBFS PLL OFF –75 70 65 –80 60 –85 55 –6 dBFS PLL OFF –90 50 0 20 40 60 80 100 0 260 20 40 60 80 100 120 140 160 180 200 220 240 f (MHz) f (MHz) OUT OUT Figure 13. AD9787 In-Band SFDR vs. f , 2× Interpolation OUT Figure 16. AD9788 ACLR for First Adjacent Band WCDMA, 4× Interpolation, f = 122.88 MSPS, NCO Translates Baseband Signal to IF DATA Rev. A | Page 14 of 64 SFDR (dB) IMD (dBc) ACLR (dBc) 07098-071 07098-070 07098-072 NSD (dBm/Hz) ACLR (dBc) NSD (dBm/Hz) 07098-076 07098-074 07098-073 AD9785/AD9787/AD9788 –55 100 –60 200MSPS 90 –65 80 0 dBFS PLL ON –70 160MSPS 250MSPS –6 dBFS PLL OFF –75 70 –80 60 –85 –3 dBFS PLL OFF 0 dBFS PLL OFF –90 50 0 50 100 150 200 0 20 40 60 80 100 120 140 160 180 200 220 240 260 f (MHz) f (MHz) OUT OUT Figure 17. AD9788 ACLR for Second Adjacent Band WCDMA, Figure 20. AD9788 IMD vs. fOUT, 2× Interpolation 4× Interpolation, f = 122.88 MSPS, NCO Translates Baseband Signal to IF DATA –70 100 90 –75 0 dBFS PLL ON 80 150MSPS –6 dBFS PLL OFF –80 70 200MSPS –85 100MSPS –3 dBFS PLL OFF 60 0 dBFS PLL OFF –90 50 0 40 80 120 160 200 240 280 320 360 400 0 260 20 40 60 80 100 120 140 160 180 200 220 240 f (MHz) f (MHz) OUT OUT Figure 18. AD9788 ACLR for Third Adjacent Band WCDMA, 4× Interpolation, Figure 21. AD9788 IMD vs. f , 4× Interpolation OUT f = 122.88 MSPS, NCO Translates Baseband Signal to IF DATA 100 100 160MSPS 90 90 250MSPS 80 80 200MSPS PLL ON 70 70 PLL OFF 60 60 50 50 0 20 40 60 80 100 120 0 20 40 60 80 100 120 140 160 180 200 f (MHz) f (MHz) OUT OUT Figure 19. AD9788 IMD vs. fOUT, 1× Interpolation Figure 22. AD9788 IMD vs. fOUT, 8× Interpolation, fDATA = 100 MSPS, PLL On/PLL Off Rev. A | Page 15 of 64 ACLR (dBc) ACLR (dBc) IMD (dBc) 07098-079 07098-078 07098-077 IMD (dBc) IMD (dBc) IMD (dBc) 07098-082 07098-081 07098-080 AD9785/AD9787/AD9788 100 100 95 90 90 85 80 80 75MSPS 75 70 70 50MSPS 100MSPS 65 60 60 55 50 50 0 50 100 150 200 250 300 350 400 450 0 40 80 120 160 200 240 280 320 360 400 f (MHz) f (MHz) OUT OUT Figure 23. AD9788 IMD vs. fOUT, 8× Interpolation Figure 26. AD9788 IMD vs. fOUT, over 50 Parts, 4× Interpolation, fDATA = 200 MSPS –142 100 –146 90 –150 80 –6dBFS –154 –3dBFS 0dBFS –158 –3dBFS 70 0dBFS –162 –6dBFS 60 –166 –170 50 0 20 40 60 80 100 0 40 80 120 160 200 240 280 320 360 400 f (MHz) f (MHz) OUT OUT Figure 27. AD9788 Noise Spectral Density vs. Digital Full-Scale Single-Tone Figure 24. AD9788 IMD Performance vs. Digital Full-Scale Input, Input, fDATA = 200 MSPS, 2× Interpolation 4× Interpolation, fDATA = 200 MSPS –142 100 –146 90 –150 20mA 80 –154 30mA –158 70 2× –162 10mA 4× 8× 60 –166 –170 50 0 40 80 120 160 200 240 280 320 360 400 0 1020 3040 50 f (MHz) f (MHz) OUT OUT Figure 25. AD9788 IMD Performance vs. Full-Scale Output Current, Figure 28. AD9788 Noise Spectral Density vs. f , Multitone Input, OUT 4× Interpolation, f = 200 MSPS f = 100 MSPS DATA DATA Rev. A | Page 16 of 64 IMD (dBc) IMD (dBc) IMD (dBc) 07098-085 07098-084 07098-083 IMD (dBc) NSD (dBm/Hz) NSD (dBm/Hz) 07098-087 07098-088 07098-086 AD9785/AD9787/AD9788 –142 90 85 –146 200MSPS 80 –150 160MSPS 75 –154 70 –158 250MSPS 2× 65 4× –162 60 8× –166 55 –170 50 0 1020 3040 50 020 4060 80 100 f (MHz) f (MHz) OUT OUT Figure 29. AD9788 Noise Spectral Density vs. f , Single-Tone Input, Figure 32. AD9788 In-Band SFDR vs. f , 1× Interpolation OUT OUT f = 100 MSPS DATA –142 80 –146 75 250MSPS –150 200MSPS 70 160MSPS –154 65 –158 1× 2× 60 –162 4× 55 –166 50 –170 020 40 60 80 100 0 102030 4050 607080 90 100 f (MHz) f (MHz) OUT OUT Figure 30. AD9788 Noise Spectral Density vs. f , Eight-Tone Input Figure 33. AD9788 Out-of-Band SFDR vs. f , 2× Interpolation DAC OUT with 500 kHz Spacing, f = 200 MSPS DATA –142 95 90 –146 10mA 85 20mA –150 80 –154 75 30mA 1× 70 –158 2× 65 –162 4× 60 –166 55 –170 50 0 2040 6080 100 0 1020 304050 607080 f (MHz) f (MHz) OUT OUT Figure 31. AD9788 Noise Spectral Density vs. f , Full-Scale Single-Tone Figure 34. AD9788 In-Band SFDR vs. Full-Scale Output Current, DAC Input at −6 dB, f = 200 MSPS 2× Interpolation, f = 200 MSPS DATA DATA Rev. A | Page 17 of 64 NSD (dBm/Hz) NSD (dBm/Hz) NSD (dBm/Hz) 07098-091 07098-090 07098-089 SFDR (dB) SFDR (dB) SFDR (dB) 07098-094 07098-093 07098-092 AD9785/AD9787/AD9788 110 100 100MSPS 95 160MSPS 100 90 250MSPS 150MSPS 85 90 200MSPS 80 200MSPS 80 75 70 70 65 60 60 55 50 50 010 2030 40 506070 8090 0 204060 80 100 f (MHz) f (MHz) OUT OUT Figure 35. AD9788 In-Band SFDR vs. f , 4× Interpolation Figure 38. AD9788 In-Band SFDR vs. f , 2× Interpolation OUT OUT 80 110 100MSPS 100MSPS 75 100 50MSPS 150MSPS 70 90 200MSPS 65 80 60 70 55 60 50 50 010 2030 40 506070 8090 0 10 2030 4050 f (MHz) f (MHz) OUT OUT Figure 36. AD9788 Out-of-Band SFDR vs. f , 4× Interpolation OUT Figure 39. AD9788 In-Band SFDR vs. fOUT, 8× Interpolation 90 90 –3dBFS 0dBFS 50MSPS 85 85 100MSPS 80 80 –6dBFS 75 75 70 70 65 65 60 60 55 55 50 50 0 10203040 50607080 0 5 10 15 20 25 30 35 40 45 f (MHz) f (MHz) OUT OUT Figure 37. AD9788 In-Band SFDR vs. Digital Full-Scale Input, Figure 40. AD9788 Out-of-Band SFDR vs. fOUT, 8× Interpolation 2× Interpolation, fDATA = 200 MSPS Rev. A | Page 18 of 64 SFDR (dB) SFDR (dB) SFDR (dB) 07098-097 07098-096 07098-095 SFDR (dB) SFDR (dB) SFDR (dB) 07098-100 07098-099 07098-098 AD9785/AD9787/AD9788 110 PLL OFF 100 PLL ON 90 80 70 60 50 0 1020 3040 50 f (MHz) OUT Figure 41. AD9788 In-Band SFDR vs. f , 4× Interpolation, f = 100 MSPS, OUT DATA PLL On/PLL Off Rev. A | Page 19 of 64 SFDR (dB) 07098-101 AD9785/AD9787/AD9788 TERMINOLOGY Integral Nonlinearity (INL) Spurious-Free Dynamic Range (SFDR) INL is defined as the maximum deviation of the actual analog Spurious-free dynamic range is the difference, in decibels, output from the ideal output, determined by a straight line between the peak amplitude of the output signal and the peak drawn from zero scale to full scale. amplitude of the largest spurious signal in a given frequency band from the signal. For out-of-band SFDR, the frequency Differential Nonlinearity (DNL) band is 0 to one half the DAC sample rate. For in-band SFDR, DNL is the measure of the variation in analog value, normalized the frequency band is 0 to one half the input data rate. to full scale, associated with a 1 LSB change in digital input code. Total Harmonic Distortion (THD) Monotonicity THD is the ratio of the rms sum of the first six harmonic com- A DAC is monotonic if the output either increases or remains ponents to the rms value of the measured fundamental. It is constant as the digital input increases. expressed as a percentage or in decibels. Offset Error Noise Spectral Density (NSD) The deviation of the output current from the ideal of zero is NSD is the noise power at the analog output measured in a 1 Hz called offset error. For I , 0 mA output is expected when the OUTA bandwidth. inputs are all 0s. For I , 0 mA output is expected when all OUTB inputs are set to 1. Interpolation Filter If the digital inputs to the DAC are sampled at a multiple rate of Gain Error fDATA (interpolation rate), a digital filter can be constructed that The difference between the actual and ideal output span is has a sharp transition band near fDATA/2. Images that typically called gain error. The actual span is determined by the differ- appear around fDAC (output data rate) can be greatly suppressed. ence between the output when all inputs are set to 1 and the output when all inputs are set to 0. Adjacent Channel Leakage Ratio (ACLR) ACLR is the ratio in dBc between the measured power within a Output Compliance Range channel relative to its adjacent channel. The output compliance range is the range of allowable voltage at the output of a current output DAC. Operation beyond the Complex Image Rejection maximum compliance limits can cause either output stage In a traditional two-part upconversion, two images are created saturation or breakdown, resulting in nonlinear performance. around the second intermediate frequency (IF). These images have the effect of wasting transmitter power and system band- Temperature Drift width. By placing the real part of a second complex modulator Temperature drift is specified as the maximum change from the in series with the first complex modulator, either the upper or ambient (25°C) value to the value at either T or T . For MIN MAX lower frequency image near the second IF can be rejected. offset and gain drift, the drift is reported in ppm of full-scale range (FSR) per degree Celsius. For reference drift, the drift is Sinc reported in ppm per degree Celsius. Sinc is shorthand for the mathematical function Power Supply Rejection (PSR) sinc(x) = sin(x)/x PSR is the maximum change in the full-scale output as the This function is a useful tool for digital signal processing. The supplies are varied from minimum to maximum specified normalized sinc function is used here and is defined as follows: voltages. sinc(x) = sin(π × x)/(π × x) Settling Time Settling time is the time required for the output to reach and remain within a specified error band around its final value, measured from the start of the output transition. Rev. A | Page 20 of 64 AD9785/AD9787/AD9788 THEORY OF OPERATION The AD9785/AD9787/AD9788 devices combine many features SERIAL PORT INTERFACE that make them very attractive DACs for wired and wireless The AD9785/AD9787/AD9788 serial port is a flexible, communications systems. The dual digital signal path and dual synchronous serial communications port allowing easy DAC structure allow an easy interface to common quadrature interface to many industry-standard microcontrollers and modulators when designing single sideband transmitters. The microprocessors. The serial I/O is compatible with most speed and performance of the AD9785/AD9787/AD9788 allow synchronous transfer formats, including both the Motorola® wider bandwidths and more carriers to be synthesized than in 6905/11 SPI and the Intel® 8051 SSR protocols. previously available DACs. In addition, these devices include The serial interface allows read/write access to all registers that an innovative low power, 32-bit complex NCO that greatly configure the AD9785/AD9787/AD9788. MSB first and LSB increases the ease of frequency placement. first transfer formats are supported. In addition, the serial The AD9785/AD9787/AD9788 offer features that allow interface port can be configured as a single-pin I/O (SDIO), simplified synchronization with incoming data and between which allows a 3-wire interface, or two unidirectional pins for multiple parts, as well as the capability to phase synchronize input/output (SDIO/SDO), which enables a 4-wire interface. NCOs on multiple devices. Auxiliary DACs are also provided One optional pin, SPI_CSB (chip select), allows enabling of on chip for output dc offset compensation (for LO compen- multiple devices on a single bus. sation in SSB transmitters) and for gain matching (for image With the AD9785/AD9787/AD9788, the instruction byte rejection optimization in SSB transmitters). Another innovative specifies read/write operation and the register address. Serial feature in the devices is the digitally programmable output operations on the AD9785/AD9787/AD9788 occur only at the phase compensation, which increases the amount of image register level, not at the byte level, due to the lack of byte cancellation capability in SSB (single sideband) transmitters. address space in the instruction byte. 16 + × 0 OUT1_P SIN(×) 16-BIT DAC1 0 + 1 OUT1_N TXENABLE 1 I-OFFSET 2 I-SCALE 16 16 16 QUAD QUAD QUAD 3 COS 10 θ P1D[15:0] HB HB HB NCO FILTER FILTER FILTER OUT2_P 16 32 SIN 16-BIT (2×) (2×) (2×) 3 ω Q-SCALE DAC2 OUT2_N Q-OFFSET 2 16 1 0 P2D[15:0] 0 16 + × 1 SIN(×) + VREF PHASE RESET CORRECTION 10 AUX1_P AUX1 AUX1_N INTERNAL CLOCK TIMING AND CONTROL LOGIC 10 AUX2_P PLL CONTROL AUX2 DELAY DATACLK AUX2_N LINE 1 LVDS SERIAL 0 SYNC_O DAC_CLK PROGRAMMING POWER-ON I/O DELAY 0 CLOCK REGISTERS RESET REFCLK+ PORT CLK LINE MULTICHIP 1 MULTIPLIER R SYNCHRONIZATION CVR (2× – 16×) REFCLK– LVDS DELAY SYNC_I LINE Figure 42. Functional Block Diagram Rev. A | Page 21 of 64 DATA ASSEMBLER HB1_CLK HB2_CLK HB3_CLK INTERPOLATION FACTOR SPI_SDO SPI_SDIO SCLK SPI_CSB FREQUENCY IRQ PHASE RESET INV_SINC_EN 10 GAIN1 PLL_LOCK 10 GAIN2 REFERENCE AND BIAS 07098-002 AD9785/AD9787/AD9788 There are two phases to a communication cycle with the Figure 43 through Figure 46 are useful in understanding the AD9785/AD9787/AD9788. Phase 1 is the instruction cycle, general operation of the AD9785/AD9787/AD9788 serial port. which is the writing of an instruction byte into the AD9785/ INSTRUCTION CYCLE DATA TRANSFER CYCLE AD9787/AD9788, coincident with the first eight SCLK rising SPI_CSB edges. The instruction byte provides the AD9785/AD9787/ AD9788 serial port controller with information regarding the SCLK data transfer cycle, which is Phase 2 of the communication R/W N1 N0 A4 A3 A2 A1 A0 D7 D6 D5 D3 D2 D1 D0 cycle. The instruction byte defines whether the upcoming data SPI_SDIO N N 0 0 0 0 transfer is read or write and the serial address of the register D7 D6 D5 D3 D2 D1 D0 N N 0 0 0 0 SPI_SDO being accessed. Figure 43. Serial Register Interface Timing, MSB First The first eight SCLK rising edges of each communication cycle are used to write the instruction byte into the AD9785/AD9787/ INSTRUCTION CYCLE DATA TRANSFER CYCLE AD9788. The remaining SCLK edges are for Phase 2 of the SPI_CSB communication cycle. Phase 2 is the actual data transfer between the AD9785/AD9787/AD9788 and the system SCLK controller. The number of bytes transferred during Phase 2 of the communication cycle is a function of the register being A0 A1 A2 A3 A4 N0 N1 R/W D0 D1 D2 D4 D5 D6 D7 SPI_SDIO 0 0 0 N N N N accessed. For example, when accessing the frequency tuning word (FTW) SPI_SDO D0 D1 D2 D4 D5 D6 D7 0 0 0 N N N N register, which is four bytes wide, Phase 2 requires that four Figure 44. Serial Register Interface Timing, LSB First bytes be transferred. If accessing the amplitude scale factor (ASF) register, which is three bytes wide, Phase 2 requires that three t DS bytes be transferred. After transferring all data bytes per the t SCLK instruction byte, the communication cycle is completed. SPI_CSB At the completion of any communication cycle, the AD9785/ t t PWH PWL AD9787/AD9788 serial port controller expects the next eight SCLK rising SCLK edges to be the instruction byte of the next t DS t DH communication cycle. INSTRUCTION BIT 7 INSTRUCTION BIT 6 SPI_SDIO All data input is registered on the rising edge of SCLK. All data Figure 45. SPI Register Write Timing is driven out of the AD9785/AD9787/AD9788 on the falling edge of SCLK. SPI_CSB SCLK t DV SPI_SDIO DATA BIT n DATA BIT n–1 SPI_SDO Figure 46. SPI Register Read Timing Instruction Byte Rev. A | Page 22 of 64 07098-009 07098-008 07098-007 07098-006 AD9785/AD9787/AD9788 Instruction Byte SPI_SDO—Serial Data Output The instruction byte contains the following information as shown in the instruction byte bit map. Data is read from this pin for protocols that use separate lines for transmitting and receiving data. In the case where the Instruction Byte Information Bit Map AD9785/AD9787/AD9788 operate in a single bidirectional MSB LSB I/O mode, this pin does not output data and is set to a high D7 D6 D5 D4 D3 D2 D1 D0 impedance state. R/W X X A4 A3 A2 A1 A0 MSB/LSB Transfers W R/ —Bit 7 of the instruction byte determines whether a read The AD9785/AD9787/AD9788 serial port can support both or write data transfer occurs after the instruction byte write. most significant bit (MSB) first or least significant bit (LSB) Logic 1 indicates a read operation. Logic 0 indicates a write first data formats. This functionality is controlled by Bit 6 of the operation. communication (COMM) register. The default value of COMM Register Bit 6 is low (MSB first). When COMM Register Bit 6 is X, X —Bit 6 and Bit 5 of the instruction byte are don’t care. In set high, the serial port is in LSB first format. The instruction byte previous TxDACs, such as the AD9779, these bits define the must be written in the format indicated by COMM Register Bit 6. number of registers written to or read from in an SPI read/write That is, if the device is in LSB first mode, the instruction byte operation. In the AD9785/AD9787/AD9788, the register itself must be written from least significant bit to most significant bit. now defines how many bytes are written to or read from. A4, A3, A2, A1, A0—Bit 4, Bit 3, Bit 2, Bit 1, and Bit 0 of the For MSB first operation, the serial port controller generates the instruction byte determine which register is accessed during the most significant byte (of the specified register) address first, data transfer portion of the communication cycle. followed by the next lesser significant byte addresses until the I/O operation is complete. All data written to or read from the Serial Interface Port Pin Description AD9785/AD9787/AD9788 must be in MSB first order. SCLK—Serial Clock If the LSB mode is active, the serial port controller generates the The serial clock pin is used to synchronize data to and from the least significant byte address first, followed by the next greater AD9785/AD9787/AD9788 and to run the internal state machines. significant byte addresses until the I/O operation is complete. SCLK maximum frequency is 40 MHz. All data written to or read from the AD9785/AD9787/AD9788 SPI_CSB—Chip Select must be in LSB first order. Active low input that allows more than one device on the same SPI Resynchronization Capability serial communications line. The SPI_SDO and SPI_SDIO pins If the SPI port becomes unsynchronized at any time, toggling go to a high impedance state when this input is high. If driven SCLK for eight or more cycles with SPI_CSB held high resets high during any communication cycle, that cycle is suspended the SPI port state machine. The device is then ready for the next until SPI_CSB is reactivated low. Chip select can be tied low in register read or write access. systems that maintain control of SCLK. SPI_SDIO—Serial Data I/O Data is always written into the AD9785/AD9787/AD9788 on this pin. However, this pin can be used as a bidirectional data line. Bit 7 of Register 0x00 controls the configuration of this pin. The default is Logic 0, which configures the SPI_SDIO pin for input only (4-wire) operation. Rev. A | Page 23 of 64 AD9785/AD9787/AD9788 SPI REGISTER MAP th th When reading Table 9, note that the AD9785/AD9787/AD9788 is a 32-bit part and, therefore, the 4 through the 11 columns (beginning with the MSB and ending with the LSB) represent a set of eight bits. Refer to the Bit Range column for the actual bits being described. Table 9. Register Bit Address Name Range MSB MSB − 1 MSB − 2 MSB − 3 MSB − 4 MSB − 5 MSB − 6 LSB Default 0x00 Comm. [7:0] SPI_SDIO LSB first Software Power- Auto I/O Automatic Open 0x02 (COMM) bidirectional reset down power- transfer I/O Register (active high, mode down (self- transfer 3-wire) enable reset) enable 0x01 Digital [7:0] Interpolation Factor [1:0] Data Single- Real IQ select Q first Modulator 0x00 Control format port mode invert gain Register mode control [15:8] Reserved Clear phase PN code Sync Pulse Reserved Inverse DATACLK 0x31 accumulator sync mode sync sinc output enable select enable enable enable 0x02 Data Sync [7:0] Data Timing LVDS data DATACLK DATACLK Data Set high Data sync Reserved 0x00 Control Margin [0] clock enable invert delay timing polarity Register enable mode [15:8] DATACLK Delay [4:0] Data Timing Margin [3:1] 0x00 0x03 Multichip [7:0] Clock State [3:0] Sync Timing Margin [3:0] 0x00 Sync [15:8] SYNC _O Delay [4:0] Set high SYNC_O Sync 0x00 Control polarity loopback Register enable [23:16] SYNC_I Delay [4:0] Sync Set low DATACLK 0x00 error input check mode [31:24] Correlate Threshold [4:0] SYNC _I SYNC _O Set low 0x80 enable enable 0x04 PLL [7:0] PLL Band Select [5:0] PLL VCO Drive [1:0] 0xCF Control [15:8] PLL enable PLL VCO Divisor [1:0] PLL Loop Divisor [1:0] PLL Bias [2:0] 0x37 Register [23:16] VCO Control Voltage [2:0] PLL Loop Bandwidth [4:0] 0x38 0x05 I DAC [7:0] I DAC Gain Adjustment [7:0] 0xF9 Control [15:8] I DAC sleep I DAC Reserved I DAC Gain Adjustment 0x01 Register power-down [9:8] 0x06 Auxiliary [7:0] Auxiliary DAC 1 Data [7:0] 0x00 DAC 1 [15:8] Auxiliary Auxiliary Auxiliary Reserved Auxiliary DAC 1 Data 0x00 Control DAC 1 sign DAC 1 DAC 1 [9:8] Register current power- direction down 0x07 Q DAC [7:0] Q DAC Gain Adjustment [7:0] 0xF9 Control [15:8] Q DAC sleep Q DAC Reserved Q DAC Gain Adjustment 0x01 Register power-down [9:8] 0x08 Auxiliary [7:0] Auxiliary DAC 2 Data [7:0] 0x00 DAC 2 [15:8] Auxiliary Auxiliary Auxiliary Reserved Auxiliary DAC 2 Data 0x00 Control DAC 2 sign DAC 2 DAC 2 [9:8] Register current power- direction down 0x09 Interrupt [7:0] Data timing Sync timing Data Sync PLL lock Reserved Data port Sync port 0x00 Control error IRQ error IRQ timing timing indicator IRQ enable IRQ Register error error enable type type [15:8] Reserved Clear lock Sync Sync lock Reserved 0x00 indicator lock status (self- lost reset) status 0x0A Frequency [31:0] Frequency Tuning Word [31:0] 0x00 Tuning Word Register Rev. A | Page 24 of 64 AD9785/AD9787/AD9788 Register Bit Address Name Range MSB MSB − 1 MSB − 2 MSB − 3 MSB − 4 MSB − 5 MSB − 6 LSB Default 0x0B Phase [15:0] NCO Phase Offset Word [15:0] 0x00 Control [23:16] Phase Correction Word [7:0] 0x00 Register [31:24] Reserved Phase Correction Word 0x00 [9:8] 0x0C Amplitude [7:0] I DAC Amplitude Scale Factor [7:0] 0x80 Scale [15:8] Q DAC Amplitude Scale Factor [6:0] I DAC 0x00 Factor Amplitude Register Scale Factor [8] [23:16] Reserved Q DAC Amplitude Scale 0x01 Factor [8:7] 0x0D Output [15:0] I DAC Offset [15:0] 0x00 Offset [31:16] Q DAC Offset [15:0] 0x00 Register 1 0x0E Version [7:0] Version ID Register [15:8] Reserved 1 0x1D RAM [31:0] RAM 0x1E Test [23:0] Test Register 1 Address space between Address 0x0E and Address 0x1D is intentionally left open. SPI REGISTER DESCRIPTIONS The communication (COMM) register comprises one byte located at Address 0x00. Table 10. Communication (COMM) Register Address Bit Name Description 0x00 [7] SPI_SDIO 0: Default. Use the SPI_SDIO pin for input data only, 4-wire serial mode. bidirectional 1: Use SPI_SDIO as a read/write pin, 3-wire serial mode. [6] LSB first 0: Default. MSB first format is active. 1: Serial interface accepts serial data in LSB first format. [5] Software reset 0: Default. Bit is in the inactive state. 1: In the AD9785/AD9787/AD9788, all programmable bits return to their power-up state except for the COMM register bits, which are unaffected by the software reset. The software reset remains in effect until this bit is set to 0 (inactive state). [4] Power-down mode 0: Default. The full chip power-down is not active. 1: The AD9785/AD9787/AD9788 enter a power-down mode in which all functions are powered down. This power-down puts the part into its lowest possible power dissipation state. The part remains in this low power state until the user sets this bit to a Logic 0. The analog circuitry requires 250 ms to become operational. [3] Auto power-down 0: Default. Inactive state, automatic power-down feature is not enabled. enable 1: The device automatically switches into its low power mode whenever TXENABLE is deasserted for a sufficiently long period of time. [2] I/O transfer 0: Default. Inactive state. (self-reset) 1: The contents of the frequency tuning word memory buffer, phase control memory buffer, amplitude scale factor memory buffer, and the output offset memory buffer are moved to a memory location that affects operation of the device. The one-word memory buffer is employed to simultaneously update the NCO frequency, phase, amplitude, and offset control. Note that this bit automatically clears itself after the I/O transfer occurs. For this reason, unless the reference clock is stopped, it is difficult to read back a Logic 1 on this bit. [1] Automatic I/O 0: Automatic I/O transfer disabled. The I/O transfer bit (Bit 2) must be set to update the device transfer enable in the event that changes have been made to Register 0x0A, Register 0x0B, Register 0x0C, or Register 0x0D. This allows the user to change important operating modes of the device all at once, rather than one at a time with individual SPI writes. 1: Default. Automatic I/O transfer enabled. The device updates its operation immediately when SPI writes are completed to Register 0x0A, Register 0x0B, Register 0x0C, or Register 0x0D. Rev. A | Page 25 of 64 AD9785/AD9787/AD9788 The digital control (DCTL) register comprises two bytes located at Address 0x01. Table 11. Digital Control (DCTL) Register Address Bit Name Description 0x01 [15] Reserved Reserved for future use. [14] Clear phase 0: Default. The feature that clears the NCO phase accumulator is inactive. The phase accumulator accumulator operates as normal. 1: The NCO phase accumulator is held in the reset state until this bit is cleared. [13] PN code sync 0: PN code synchronization mode is disabled. enable 1: PN code synchronization mode is enabled. See the Device Synchronization section for details. [12] Sync mode select 0: Selects pulse mode synchronization. 1: Selects PN code synchronization. See the Device Synchronization section for details. [11] Pulse sync enable 0: Pulse mode synchronization is disabled. 1: Pulse mode synchronization is enabled. See the Device Synchronization section for details. [10] Reserved Reserved for future use. [9] Inverse sinc 0: Default. The inverse sinc filter is bypassed. enable 1: The inverse sinc filter is enabled and operational. [8] DATACLK 0: Data clock pin is disabled. output enable 1: Default. The output data clock pin is active (configured as an output). [7:6] Interpolation Specifies the filter interpolation rate where: Factor [1:0] 00: 1× interpolation 01: 2× interpolation 10: 4× interpolation 11: 8× interpolation [5] Data format 0: Default. The incoming data is expected to be twos complement. 1: The incoming data is expected to be offset binary. [4] Single-port mode 0: Default. When the single-port bit is cleared, I/Q data is sampled simultaneously on the P1D and P2D input ports. Specifically, I data is registered from the P1D[15:0] pins and Q data is registered from the P2D[15:0] pins. 1: When the single-port bit is set, I/Q data is sampled in a serial word fashion on the P1D input port. In this mode, the I/Q data is sampled into the part at twice the I/Q sample rate. [3] Real mode 0: Default. Logic 0 is the inactive state for this bit. 1: When the real mode bit is set, the Q path logic after modulation and phase compensation is disabled. [2] IQ select invert 0: Default. When the IQ Select Invert bit is cleared, a Logic 1 on the TXENABLE pin indicates I data, and a Logic 0 on the TXENABLE pin indicates Q data, if the user is employing a continuous timing style on the TXENABLE pin. 1: When the IQ Select Invert bit is set, a Logic 1 on the TXENABLE pin indicates Q data, and a Logic 0 on the TXENABLE pin indicates I data, if the user is employing a continuous timing style on the TXENABLE pin. [1] Q first (data 0: Default. When the Q first bit is cleared, the I/Q data pairing is nominal, that is, the I data pairing) precedes the Q data in the assembly of the I/Q data pair. As such, data input to the device as I0, Q0, I1, Q1 . . . In, Qn is paired as follows: (I0/Q0), (I1/Q1) … (In/Qn). 1: When the Q first bit is set, the I/Q data pairing is altered such that the I data is paired with the previous Q data. As such, data input to the device as I0, Q0, I1, Q1, I2, Q2, I3, Q3 . . . In, Qn is paired as follows: (I1/Q0), (I2/Q1), (I3/Q2) … (In + 1/Qn). [0] Modulator gain 0: Default. No gain scaling is applied to the NCO input to the internal digital modulator. control 1: Gain scaling of 0.5 is applied to the NCO input to the modulator. This can eliminate saturation of the modulator output for some combinations of data inputs and NCO signals. Rev. A | Page 26 of 64 AD9785/AD9787/AD9788 The data synchronization control register (DSCR) comprises two bytes located at Address 0x02. Table 12. Data Synchronization Control Register (DSCR) Address Bit Name Description 0x02 [15:11] DATACLK Delay [4:0] Controls the amount of delay applied to the output data clock signal. The minimum delay corresponds to the 00000 state, and the maximum delay corresponds to the 11111 state. The minimum delay is 0.7 ns and the maximum delay is 6.5 ns. The incremental delay is 190 ps and corresponds to an incremental change in the data clock delay bits. [10:7] Data Timing Margin [3:0] The data timing margin bits control the amount of delay applied to the data and clock signals used for checking setup and hold times, respectively, on the input data ports, with respect to the internal data assembler clock. The minimum delay corresponds to the 0000 state, and the maximum delay corresponds to the 1111 state. The delays are 190 ps. [6] LVDS data clock enable 0: Default. When the LVDS data clock enable bit is cleared, the SYNC_O+ and SYNC_O− LVDS pad cells are driven by the multichip synchronization logic. 1: When the LVDS data clock enable bit is set, the SYNC_O+ and SYNC_O− LVDS pad cells are driven by the signal that drives the CMOS DATACLK output pad. [5] DATACLK invert 0: Default. When the data clock invert bit is cleared, the DATACLK signal is in phase with the clock that samples the data into the part. 1: When the DATACLK invert bit is set, the DATACLK signal is inverted from the clock that samples the data into the part. [4] DATACLK delay enable 0: Default. When the DATACLK delay enable bit is cleared, the data port input synchronization function is effectively inactive and the delay is bypassed. 1: When the DATACLK delay enable bit is set, the data port input synchronization function is active and controlled by the data delay mode bits. The data output clock is routed through the delay cell. [3] Data timing mode Determines the timing optimization mode. See the Optimizing the Data Input Timing section for details. 0: Manual timing optimization mode 1: Automatic timing optimization mode [2] Set high This bit should always be set high. [1] Data sync polarity 0: Default. The digital input data sampling edge is aligned with the falling edge of DCI. 1: The digital input data sampling edge is aligned with the rising edge of DCI. Used only in slave mode (see the MSCR register, Address 0x03, Bit 16). [0] Reserved Reserved for future use. Rev. A | Page 27 of 64 AD9785/AD9787/AD9788 The multichip synchronization register (MSCR) comprises four bytes located at Address 0x03. Table 13. Multichip Synchronization Register (MSCR) Address Bit Name Description 0x03 [31:27] Correlate Threshold Sets the threshold for determining if the received synchronization data can be demodulated [4:0] accurately. A smaller threshold value makes the demodulator more noise immune; however, the system becomes more susceptible to false locks (or demodulation errors). [26] SYNC_I enable 0: Default. The synchronization receive logic is disabled. 1: The synchronization receive logic is enabled. [25] SYNC_O enable 0: Default. The output synchronization pulse generation logic is disabled. 1: The output synchronization pulse generation logic is enabled. [24] Set low This bit should always be set low. [23:19] SYNC_I Delay [4:0] This value programs the value of the delay line of the SYNC_I signal. The delay line resolution is 80 ps per step. 00000: nominal delay 00001: adds 80 ps delay to SYNC_I 00010: adds 160 ps delay to SYNC_I … 11111: adds 2480 ps delay to SYNC_I [18] Sync error check mode Specifies the synchronization pulse error check mode. 0: Manual error check 1: Automatic continuous error check [17] Set low This bit should always be set low. [16] DATACLK input 0: Default. Slave mode is disabled. 1: Slave mode is enabled. Pin 37 functions as an input for the DATACLK signal, called DCI (DATACLK input) in this mode. Depending on the state of Bit 1 in the DSCR register (Address 0x02), the sampling edge (where the data is latched into the AD9785/AD9787/AD9788) can be programmed to be aligned with either the rising or falling edge of DCI. This mode can only be used with 4× or 8× interpolation. [15:11] SYNC_O Delay [4:0] This value programs the value of the delay line of the SYNC_O signal. The delay of SYNC_O is relative to REFCLK. The delay line resolution is 80 ps per step. 00000: nominal delay 00001: adds 80 ps delay to SYNC_O 00010: adds 160 ps delay to SYNC_O … 11111: adds 2480 ps delay to SYNC_O [10] Set high This bit should always be set high. [9] SYNC_O polarity 0: Default. SYNC_O changes state on the rising edge of DACCLK. 1: SYNC_O is generated on the falling edge of DACCLK. [8] Sync loopback enable 0: Default. The AD9785/AD9787/AD9788 are not operating in internal loopback mode. 1: If the SYNC_O enable and Sync loopback enable bits are set, the AD9785/AD9787/AD9788 are operating in a mode in which the internal synchronization pulse of the device is used at the multichip receiver logic and the SYNC_I+ and SYNC_I− input pins are ignored. For proper operation of the loopback synchronization mode, the synchronization driver enable and sync enable bits must be set. [7:4] Clock State [3:0] This value determines the state of the internal clock generation state machine upon synchronization. [3:0] Sync Timing Margin These bits are the synchronization window delay word. These bits are don’t care if the [3:0] synchronization driver enable bit is cleared. Rev. A | Page 28 of 64 AD9785/AD9787/AD9788 The PLL control (PLLCTL) register comprises three bytes located at Address 0x04. These bits are routed directly to the periphery of the digital logic. No digital functionality within the main digital block is required. Table 14. PLL Control (PLLCTL) Register Address Bit Name Description 0x04 [23:21] VCO Control Voltage 000 to 111, proportional to voltage at VCO, control voltage input (readback only). A value of [2:0] 011 indicates that the VCO control voltage is centered. [20:16] PLL Loop Bandwidth These bits control the bandwidth of the PLL filter. Increasing the value lowers the loop [4:0] bandwidth. Set to 01111 for optimal performance. [15] PLL enable 0: Default. With PLL off, the DAC sample clock is sourced directly by the REFCLK input. 1: With PLL on, the DAC clock is synthesized internally from the REFCLK input via the PLL clock multiplier. See the Clock Multiplication section for details. [14:13] PLL VCO Divisor [1:0] Sets the value of the VCO output divider, which determines the ratio of the VCO output frequency to the DAC sample clock frequency, f /f . VCO DACCLK 00: fVCO/fDACCLK = 1 01: fVCO/fDACCLK = 2 10: fVCO/fDACCLK = 4 11: f /f = 8 VCO DACCLK [12:11] PLL Loop Divisor [1:0] Sets the value of the DACCLK divider, which determines the ratio of the DAC sample clock frequency to the REFCLK frequency, f /f . DACCLK REFCLK 00: f /f = 2 DACCLK REFCLK 01: f /f = 4 DACCLK REFCLK 10: fDACCLK/fREFCLK = 8 11: fDACCLK/fREFCLK = 16 [10:8] PLL Bias [2:0] These bits control the VCO bias current. Set to 011 for optimal performance. [7:2] PLL Band Select [5:0] These bits set the operating frequency of the VCO. For further details, refer to Table 35. [1:0] PLL VCO Drive [1:0] These bits control the signal strength of the VCO output. Set to 11 for optimal performance. The I DAC control register comprises two bytes located at Address 0x05. These bits are routed directly to the periphery of the digital logic. No digital functionality within the main digital block is required. Table 15. I DAC Control Register Address Bit Name Description 0x05 [15] I DAC sleep 0: Default. If the I DAC sleep bit is cleared, the I DAC is active. 1: If the I DAC sleep bit is set, the I DAC is inactive and enters a low power state. [14] I DAC power-down 0: Default. If the I DAC power-down bit is cleared, the I DAC is active. 1: If the I DAC power-down bit is set, the I DAC is inactive and enters a low power state. [13:10] Reserved Reserved for future use. [9:0] I DAC gain These bits are the I DAC gain adjustment bits. adjustment Rev. A | Page 29 of 64 AD9785/AD9787/AD9788 The Auxiliary DAC 1 control register comprises two bytes located at Address 0x06. These bits are routed directly to the periphery of the digital logic. No digital functionality within the main digital block is required. Table 16. Auxiliary DAC 1 Control Register Address Bit Name Description 0x06 [15] Auxiliary DAC 1 sign 0: Default. If the Auxiliary DAC 1 sign bit is cleared, the Aux DAC 1 sign is positive. Pin 90 is the active pin. 1: If the Auxiliary DAC 1 sign bit is set, the Aux DAC 1 sign is negative. Pin 89 is the active pin. [14] Auxiliary DAC 1 0: Default. If the Auxiliary DAC 1 current direction bit is cleared, the Aux DAC 1 sources current direction current. 1: If the Auxiliary DAC 1 current direction bit is set, the Aux DAC 1 sinks current. [13] Auxiliary DAC 1 0: Default. If the Auxiliary DAC 1 power-down bit is cleared, the Aux DAC 1 is active. power-down 1: If the Auxiliary DAC 1 power-down bit is set, the Aux DAC 1 is inactive and enters a low power state. [12:10] Reserved Reserved for future use. [9:0] Auxiliary DAC 1 data These bits are the Auxiliary DAC 1 gain adjustment bits. The Q DAC control register comprises two bytes located at Address 0x07. These bits are routed directly to the periphery of the digital logic. No digital functionality within the main digital block is required. Table 17. Q DAC Control Register Address Bit Name Description 0x07 [15] Q DAC sleep 0: Default. If the Q DAC sleep bit is cleared, the Q DAC is active. 1: If the Q DAC sleep bit is set, the Q DAC is inactive and enters a low power state. [14] Q DAC power-down 0: Default. If the Q DAC power-down bit is cleared, the Q DAC is active. 1: If the Q DAC power-down bit is set, the Q DAC is inactive and enters a low power state. [13:10] Reserved Reserved for future use. [9:0] Q DAC gain adjustment These bits are the Q DAC gain adjustment bits. The Auxiliary DAC 2 control register comprises two bytes located at Address 0x08. These bits are routed directly to the periphery of the digital logic. No digital functionality within the main digital block is required. Table 18. Auxiliary DAC 2 Control Register Address Bit Name Description 0x08 [15] Auxiliary DAC 2 sign 0: Default. If the Auxiliary DAC 2 sign bit is cleared, the Aux DAC 2 sign is positive. Pin 86 is the active pin. 1: If the Auxiliary DAC 2 sign bit is set, the Aux DAC 2 sign is negative. Pin 87 is the active pin. [14] Auxiliary DAC 2 0: Default. If the Auxiliary DAC 2 current direction bit is cleared, the Aux DAC 2 sources current direction current. 1: If the Auxiliary DAC 2 current direction bit is set, the Aux DAC 2 sinks current. [13] Auxiliary DAC 2 0: Default. If the Auxiliary DAC 2 power-down bit is cleared, the Aux DAC 2 is active. power-down 1: If the Auxiliary DAC 2 power-down bit is set, the Aux DAC 2 is inactive and enters a low power state. [12:10] Reserved Reserved for future use. [9:0] Auxiliary DAC 2 data These bits are the Auxiliary DAC 2 gain adjustment bits. Rev. A | Page 30 of 64 AD9785/AD9787/AD9788 The interrupt control register comprises two bytes located at Address 0x09. Bits [11:10] and Bits [7:3] are read-only bits that indicate the current status of a specific event that may cause an interrupt request (IRQ pin active low). These bits are controlled via the digital logic and are read only via the serial port. Bits [1:0] are the IRQ mask (or enable) bits, which are writable by the user and can also be read back. Table 19. Interrupt Control Register Address Bit Name Description 0x09 [15:13] Reserved Reserved for future use. [12] Clear lock indicator Writing a 1 to this bit clears the sync lock lost status bit. This bit does not automatically reset itself to 0 when the reset is complete. [11] Sync lock lost status When high, this bit indicates that the device has lost synchronization. This bit is latched and does not reset automatically after the device regains synchronization. To reset this bit to 0, a 1 must be written to the clear lock indicator bit. [10] Sync lock status When this bit is low, the device is not synchronized. When this bit is high, the device is synchronized. [9:8] Reserved Reserved for future use. [7] Data timing error IRQ 0: Default. No setup or hold time error has been detected via the input data port setup/hold error checking logic. 1: A setup or hold time error has been detected via the input data port setup/hold error checking logic. [6] Sync timing error IRQ 0: Default. No setup or hold time error has been detected via the multichip synchronization receive pulse setup/hold error checking logic. 1: A setup or hold time error has been detected via the multichip synchronization receive pulse setup/hold error checking logic. [5] Data timing error type 0: Default. A hold error has been detected via the input data port setup/hold error checking logic. This bit is valid only if the data timing error IRQ bit (Bit 7) is set. 1: A setup error has been detected via the input data port setup/hold error checking logic. This bit is valid only if the data timing error IRQ bit (Bit 7) bit is set. [4] Sync timing error type 0: Default. A hold error has been detected via the multichip synchronization receive pulse setup/hold error checking logic. This bit is valid only if the sync timing error IRQ bit (Bit 6) is set. 1: A setup error has been detected via the multichip synchronization receive pulse setup/hold error checking logic. This bit is valid only if the sync timing error IRQ bit (Bit 6) is set. [3] PLL lock indicator 0: Default. The PLL clock multiplier is not locked to the input reference clock. 1: The PLL clock multiplier is locked to the input reference clock. [2] Reserved Reserved for future use. [1] Data port IRQ enable 0: Default. The data IRQ bit (and the IRQ pin) are not enabled (masked) for any errors that may be detected via the input data port setup/hold error checking logic. 1: The data IRQ bit (and the IRQ pin) are enabled and go active if a setup or hold error is detected via the input data port setup/hold error checking logic. [0] Sync port IRQ enable 0: Default. The sync IRQ bit (and the IRQ pin) are not enabled (masked) for any errors that may be detected via the multichip synchronization receive pulse setup/hold error checking logic. 1: The sync IRQ bit (and the IRQ pin) are enabled and go active if a setup or hold error is detected via the multichip synchronization receive pulse setup/hold error checking logic. Rev. A | Page 31 of 64 AD9785/AD9787/AD9788 The frequency tuning word (FTW) register comprises four bytes located at Address 0x0A. Table 20. Frequency Tuning Word (FTW) Register Address Bit Name Description 0x0A [31:0] Frequency Tuning These bits make up the frequency tuning word applied to the NCO phase accumulator. Word [31:0] See the Numerically Controlled Oscillator section for details. The phase control register (PCR) comprises four bytes located at Address 0x0B. Table 21. Phase Control Register (PCR) Address Bit Name Description 0x0B [31:26] Reserved Reserved for future use. [25:16] Phase Correction These bits are the 10-bit phase correction word. Word [9:0] [15:0] NCO Phase Offset These bits are the 16-bit NCO phase offset word. See the Numerically Controlled Oscillator Word [15:0] section for details. The amplitude scale factor (ASF) register comprises three bytes located at Address 0x0C. Table 22. Amplitude Scale Factor (ASF) Register Address Bit Name Description 0x0C [23:18] Reserved Reserved for future use. 1 [17:9] Q DAC Amplitude These bits are the 9-bit Q DAC amplitude scale factor. The bit weighting is MSB = 2 , −7 Scale Factor [8:0] LSB = 2 , which yields a multiplier range of 0 to 3.9921875. Note that by setting the gain to 1.0 (0x080), the gain block is bypassed. This changes the latency of the signal. Therefore, in systems using quadrature signals, either both I and Q scale factors should be bypassed or both should have gains set to a value other than 1.0. 1 [8:0] I DAC Amplitude These bits are the 9-bit I DAC amplitude scale factor. The bit weighting is MSB = 2 , −7 Scale Factor [8:0] LSB = 2 , which yields a multiplier range of 0 to 3.9921875. The output offset (OOF) register comprises four bytes located at Address 0x0D. Table 23. Output Offset (OOF) Register Address Bit Name Description 0 0x0D [31:16] Q DAC Offset [15:0] These bits are the 16-bit Q DAC offset factor. The LSB bit weight is 2 . 0 [15:0] I DAC Offset [15:0] These bits are the 16-bit I DAC offset factor. The LSB bit weight is 2 . The version register (VR) comprises two bytes located at Address 0x0E and is read only. Table 24. Version Register (VR) Address Bit Name Description 0x0E [15:8] Reserved Reserved for future use. [7:0] Version ID These bits read back the current version of the product. Rev. A | Page 32 of 64 AD9785/AD9787/AD9788 INPUT DATA PORTS The AD9785/AD9787/AD9788 can operate in two data input The Q first bit (Register 0x01, Bit 1) controls the pairing modes: dual-port mode and single-port mode. In the default order of the input data. With the Q first bit set to the default dual-port mode (single-port mode = 0), each DAC receives data of 0, the I/Q pairing sent to the DACs is the two input data- from a dedicated input port. In single-port mode (single-port words corresponding to TXENABLE low followed by mode = 1), both DACs receive data from Port 1. In single-port TXENABLE high. mode, DAC 1 and DAC 2 data is interleaved and the TXENABLE With the Q first bit set to 1, the I/Q pairing sent to the DACs is input is used to steer data to the intended DAC. In dual-port the two input data-words corresponding to TXENABLE high mode, the TXENABLE input is used to power down the digital followed by TXENABLE low. Note that with Q first set, the datapath. I data still corresponds to the TXENABLE high word and the In dual-port mode, the data must be delivered at the input data Q data corresponds to the TXENABLE low word and only the rate. In single-port mode, data must be delivered at twice the pairing order changes. input data rate of each DAC. Because the data inputs function up DUAL-PORT MODE to a maximum of 300 MSPS, it is only practical to operate with In dual-port mode, data for each DAC is received on the input data rates up to 150 MHz per DAC in single-port mode. respective input bus (P1D[15:0] or P2D[15:0]). I and Q data In both dual-port and single-port modes, a data clock output arrive simultaneously and are sampled on the rising edge of an (DATACLK) signal is available as a fixed-time base with which internal sampling clock (SMP_CLK) that is synchronous with to drive data from an FPGA (field programmable gate array) or DATACLK. In dual-port mode, driving the TXENABLE input from another data source. This output signal operates at the low powers down the digital datapath. TXENABLE should be input data rate. The DATACLK pin can operate as either an held high during normal data transmission. input or an output. INPUT DATA REFERENCED TO DATACLK SINGLE-PORT MODE The simplest method of interfacing to the AD9785/AD9787/ In single-port mode, data for both DACs is received on the AD9788 is when the input data is referenced to the DATACLK Port 1 input bus (P1D[15:0]). I and Q data samples are inter- output. The DATACLK output is phase-locked (with some leaved and are latched on the rising edges of DATACLK. offset) to the internal clock that is used to latch the input data. Accompanying the data is the TXENABLE (Pin 39) input Therefore, if the setup and hold times of the input data with signal, which steers incoming data to its respective DAC. When respect to DATACLK are met, the interface timing latches in the TXENABLE is high, the corresponding data-word is sent to the data correctly. I DAC and, when TXENABLE is low, the corresponding data is Table 25 shows the setup and hold time requirements for the sent to the Q DAC. The timing of the digital interface in input data over the operating temperature range of the device. interleaved mode is shown in Figure 48. Table 25 also shows the data valid window (DVW). The data valid window is the sum of the setup and hold times of the interface. This is the minimum amount of time valid data must be presented to the device in order to ensure proper sampling. Rev. A | Page 33 of 64 AD9785/AD9787/AD9788 DATACLK t t SDATACLK HDATACLK INPUT DATA Figure 47. DATACLK Timing DATACLK P1D[15:0] P1D(1) P1D(2) P1D(3) P1D(4) P1D(5) P1D(6) P1D(7) P1D(8) TXENABLE SMP_CLK P1D_SMP[15:0] P1D(1) P1D(2) P1D(3) P1D(4) P1D(5) P1D(6) P1D(7) P1D(8) IQSEL_SMP P1D(1) P1D(3) P1D(5) I DAC[15:0] QFIRST = 0 P1D(2) P1D(4) P1D(6) Q DAC[15:0] I DAC[15:0] P1D(1) P1D(3) P1D(5) QFIRST = 1 P1D(4) P1D(6) Q DAC[15:0] Figure 48. Single-Port (Interleaved) Mode Digital Interface Timing Table 25. Data Timing Specifications vs. Temperature Timing Parameter Temperature Min t (ns) Min t (ns) Min DVW (ns) S H Data with respect to REFCLK −40°C −0.25 1.7 1.45 +25°C −0.45 2.1 1.65 +85°C −0.6 2.4 1.8 −40°C to +85°C −0.25 2.4 2.15 Data with respect to DATACLK −40°C 3.7 −1.5 2.2 +25°C 4.2 −1.8 2.4 +85°C 4.6 −2.0 2.6 −40°C to +85°C 4.6 −1.5 3.1 SYNC_I with respect to REFCLK −40°C 0.45 −0.1 0.35 +25°C 0.3 0.1 0.4 +85°C 0.2 0.25 0.45 −40°C to +85°C 0.45 0.25 0.7 Rev. A | Page 34 of 64 07098-112 07098-110 AD9785/AD9787/AD9788 Setting the Frequency of DATACLK INPUT DATA REFERENCED TO REFCLK The DATACLK signal is derived from the internal DAC sample In some systems, it may be more convenient to use the REFCLK clock, DACCLK. The frequency of DATACLK output depends input instead of the DATACLK output as the input data timing on several programmable settings. The relationship between the reference. If the frequency of DACCLK is equal to the frequency frequency of DACCLK and DATACLK is of the data input (PLL is bypassed and no interpolation is used), the timing parameter “Data with respect to REFCLK” shown in f DACCLK f  Table 25 applies directly without further considerations. If the DATACLK IF P frequency of DACCLK is greater than the frequency of the data where the variables have the values shown in Table 26. input, a divider is used to generate the internal data sampling clock (DCLK_SMP). This divider creates a phase ambiguity between Table 26. DACCLK to DATACLK Divisor Values REFCLK and DCLK_SMP, which, in turn, causes a sampling Address time uncertainty. To establish fixed setup and hold times for the Variable Value Register Bits data interface, this phase ambiguity must be eliminated. IF Interpolation factor 0x01 [7:6] To eliminate the phase ambiguity, the SYNC_I input pins P 0.5 (if single port is enabled) 0x01 [4] 1 (if dual port is selected) (Pin 13 and Pin 14) must be used to synchronize the data to a specific DCLK_SMP phase. The specific steps for accom- plishing this are detailed in the Device Synchronization section. The timing relationships between SYNC_I, DACCLK, REFCLK, and the input data are shown in Figure 49 through Figure 51. SYNC_I t H_SYNC t S_SYNC DACCLK REFCLK t HREFCLK t SREFCLK INPUT DATA Figure 49. REFCLK 2× SYNC_I t H_SYNC t S_SYNC DACCLK REFCLK t SREFCLK t HREFCLK INPUT DATA Figure 50. REFCLK 4× Rev. A | Page 35 of 64 07098-113 07098-114 AD9785/AD9787/AD9788 SYNC_I t H_SYNC t S_SYNC DACCLK REFCLK t SREFCLK t HREFCLK INPUT DATA Figure 51. REFCLK 8× The Data Timing Margin [3:0] variable (Register 0x02, Bits [10:7]) OPTIMIZING THE DATA INPUT TIMING determines the amount of time before and after the actual data The AD9785/AD9787/AD9788 have on-chip circuitry that sampling point the margin test data are latched. That is, the enables the user to optimize the input data timing by adjusting Data Timing Margin [3:0] variable determines how much setup the relationship between the DATACLK output and DCLK_SMP, and hold margin the interface needs for the data timing error the internal clock that samples the input data. This optimization IRQ to remain inactive (to show error-free operation). There- is made by a sequence of SPI register read and write operations. fore, the data timing error IRQ is set whenever the setup and The timing optimization can be done under strict control of the hold margins drop below the Data Timing Margin [3:0] value. user, or the device can be programmed to maintain a configurable This does not necessarily indicate that the data latched into the timing margin automatically. device is incorrect. Figure 52 shows the circuitry that detects sample timing errors In addition to setting the data timing error IRQ, the data timing and adjusts the data interface timing. The DCLK_SMP signal is error type bit (Register 0x09, Bit 5) is set when an error occurs. the internal clock used to latch the input data. Ultimately, it is The data timing error bit is set low to indicate a hold error and the rising edge of this signal that must be centered in the valid high to indicate a setup error. Figure 53 shows a timing diagram sampling period of the input data. This is accomplished by of the data interface and the status of the data timing error type bit. adjusting the time delay, tD, which changes the DATACLK timing and, as a result, the arrival time of the input data with DATA respect to DCLK_SMP. TIMING ERROR = 0 TIMING ERROR Δt D Q M IRQ DATA TIMING TIMING CLK DATA TIMING MARGIN[3:0] ERROR ERROR DETECTION TYPE TIMING ERROR = 1, PD1[0] D Q DATA TIMING ERROR TYPE = 1 Δt CLK M DATA DATACLK DELAY[4:0] DATA TIMING ERROR = 1, Δt Δt M M DATA TIMING ERROR TYPE = 0 DCLK_SMP DATACLK Δt D DELAYED ACTUAL DELAYED Figure 52. Timing Error Detection and Optimization Circuitry DATA SAMPLING CLOCK SAMPLING INSTANT SAMPLING The error detection circuitry works by creating two sets of Figure 53. Timing Diagram of Margin Test Data sampled data (referred to as the margin test data) in addition to Automatic Timing Optimization Mode the actual sampled data used in the device datapath. One set of sampled data is latched before the actual data sampling point. When the automatic timing optimization mode is enabled The other set of sampled data is latched after the actual data (Register 0x02, Bit 3 = 1), the device continuously monitors the sampling point. If the margin test data matches the actual data, timing error IRQ and timing error type bits. The DATACLK the sampling is considered valid and no error is declared. If Delay [4:0] value (Register 0x02, Bits [4:0]) increases if a setup there is a mismatch between the actual data and the margin test error is detected and decreases if a hold error is detected. The data, an error is declared. value of the DATACLK Delay [4:0] setting currently in use can be read back by the user. Rev. A | Page 36 of 64 07098-061 07098-111 07098-062 AD9785/AD9787/AD9788 Manual Timing Optimization Mode The data can be written to the RAM in either LSB first or MSB first format. When the device is operating in manual timing optimization mode (Register 0x02, Bit 3 = 0), the device does not alter the To write to the RAM in MSB first format, complete the DATACLK Delay [4:0] value that is programmed by the user. By following steps: default, the DATACLK delay enable is inactive. This bit must be 1. Set Bit 6 of Register 0x00 to 0. set high for the DATACLK Delay [4:0] value to be realized. 2. Apply an instruction byte of 0xEE followed by the data to The delay (in absolute time) when programming the DATACLK be stored. delay from 00000 to 11111 varies from about 700 ps to about After the instruction byte (a write to Register 0x1D) is received, 6.5 ns. Typical delays per increment over temperature are shown the device automatically generates the addresses required to write in Table 27. the RAM, starting at the most significant address. The 32 rising SCLK edges following the instruction byte write the first RAM Table 27. Data Delay Line Typical Delays over Temperature word. At this time, the internal address generator decrements Delay −40°C +25°C +85°C Unit and the next 32 rising edges of SCLK write the second RAM Zero code delay (delay upon 630 700 740 ps word. This cycle of decrementing the RAM address and writing enabling delay line) 32-bit words continues until the last word is written. After the Average unit delay 175 190 210 ps 64th word is written, the communication cycle is complete. In manual mode, the error checking logic is activated and To write to the RAM in LSB first format, complete the following generates an interrupt if a setup/hold violation is detected. One steps: error check operation is performed per device configuration. Any change to the Data Timing Margin [3:0] or DATACLK 1. Set Bit 6 of Register 0x00 to 1. Delay [4:0] values triggers a new error check operation. 2. Apply an instruction byte of 0xEE followed by the data to be stored. INPUT DATA RAM The AD9785/AD9787/AD9788 feature on-chip RAM that can All memory elements must be accessed to complete a commu- be used as an alternative input data source to the input data pins. nication cycle. Note that the RAM is not a dual-port memory The input data RAM is loaded through the SPI port. After the element; therefore, if an I/O operation is begun while the RAM input data is stored in memory, the device can be configured to is being used to drive data into the signal processing path, the transmit the stored data instead of receiving data through the I/O operation has priority. input data pins. This can be a useful test mode for factory or To begin using the RAM as an internal data generator, set in-system testing. Register 0x1E (test register) to a value of 0x00C000. After these The RAM is 64 words long and 32 bits wide. The 16 MSBs drive 24 bits are written, the DAC starts to output the waveform the I datapath, and the 16 LSBs drive the Q datapath. The RAM stored in memory. configuration is shown in Figure 54. I-SIDE Q-SIDE 64 WORDS 0x1D 16 BITS 16 BITS 32 BITS Figure 54. Input Data RAM Configuration Rev. A | Page 37 of 64 RAM 07098-060 AD9785/AD9787/AD9788 DIGITAL DATAPATH 10 The AD9785/AD9787/AD9788 digital datapath consists of 0 three 2× half-band interpolation filters, a quadrature modulator, –10 and an inverse sinc filter. A 32-bit NCO provides the sine and –20 cosine carrier signals required for the quadrature modulator. –30 INTERPOLATION FILTERS –40 The AD9785/AD9787/AD9788 contain three half-band filters –50 that can be bypassed. This allows the device to operate with 2×, –60 4×, or 8× interpolation rates, or without interpolation. The –70 interpolation filters have a linear phase response. The coefficients –80 of the low-pass filters are given in Table 28, Table 29, and –90 Table 30. Spectral plots for the filter responses are shown in –100 Figure 55, Figure 56, and Figure 57. –4 –3 –2 –1 0123 4 In 2×, 4×, or 8× interpolation mode, the usable bandwidth of f (× Input Data Rate) OUT the interpolation filter is 80% of the complex input data rate. Figure 56. 4× Interpolation, Low-Pass Response to ±4× Input Data Rate The usable bandwidth has a pass-band ripple of less than (Dotted Lines Indicate 1 dB Roll-Off) 0.0005 dB and a stop-band attenuation of greater than 85 dB. 10 The center frequency of the interpolation filter is set by the 0 NCO frequency tuning word (Register 0x0A, Bits [31:0]), so –10 baseband input signals are always centered in the interpolation –20 filter pass band. –30 –40 10 –50 0 –60 –10 –70 –20 –80 –30 –90 –40 –100 –4 –3 –2 –1 0123 4 –50 f (× Input Data Rate) OUT –60 Figure 57. 8× Interpolation, Low-Pass Response to ±4× Input Data Rate –70 (Dotted Lines Indicate 1 dB Roll-Off) –80 –90 –100 –4 –3 –2 –1 0123 4 f (× Input Data Rate) OUT Figure 55. 2× Interpolation, Low-Pass Response to ±4× Input Data Rate (Dotted Lines Indicate 1 dB Roll-Off) Rev. A | Page 38 of 64 ATTENUATION (dB) 07098-010 ATTENUATION (dB) ATTENUATION (dB) 07098-012 07098-011 AD9785/AD9787/AD9788 Table 28. Half-Band Filter 1 Table 29. Half-Band Filter 2 Lower Coefficient Upper Coefficient Integer Value Lower Coefficient Upper Coefficient Integer Value H(1) H(55) −4 H(1) H(23) −2 H(2) H(54) 0 H(2) H(22) 0 H(3) H(53) +13 H(3) H(21) +17 H(4) H(52) 0 H(4) H(20) 0 H(5) H(51) −34 H(5) H(19) −75 H(6) H(50) 0 H(6) H(18) 0 H(7) H(49) +72 H(7) H(17) +238 H(8) H(48) 0 H(8) H(16) 0 H(9) H(47) −138 H(9) H(15) −660 H(10) H(46) 0 H(10) H(14) 0 H(11) H(45) +245 H(11) H(13) +2530 H(12) H(44) 0 H(12) +4096 H(13) H(43) −408 Table 30. Half-Band Filter 3 H(14) H(42) 0 Lower Coefficient Upper Coefficient Integer Value H(15) H(41) +650 H(1) H(15) −39 H(16) H(40) 0 H(2) H(14) 0 H(17) H(39) −1003 H(3) H(13) +273 H(18) H(38) 0 H(4) H(12) 0 H(19) H(37) +1521 H(5) H(11) −1102 H(20) H(36) 0 H(6) H(10) 0 H(21) H(35) −2315 H(7) H(9) +4964 H(22) H(34) 0 H(8) +8192 H(23) H(33) +3671 H(24) H(32) 0 H(25) H(31) −6642 H(26) H(30) 0 H(27) H(29) +20,755 H(28) +32,768 Rev. A | Page 39 of 64 AD9785/AD9787/AD9788 results in an output signal that is offset by a constant angle QUADRATURE MODULATOR relative to the nominal signal. This allows the user to phase The quadrature modulator is used to mix the carrier signal align the NCO output with some external signal, if necessary. generated by the NCO with the upsampled I and Q data This can be especially useful when NCOs of multiple AD9785/ provided by the user at the 16-bit parallel input port of the AD9787/AD9788 devices are programmed for synchronization. device. Figure 58 shows a detailed block diagram of the The phase offset allows for the adjustment of the output timing quadrature modulator. between the devices. The static phase adjustment is sourced The NCO provides a quadrature carrier signal with a frequency from the NCO Phase Offset Word [15:0] value located in determined by the 32-bit frequency tuning word (FTW) set in Register 0x0B. Register 0x0A, Bits [31:0]. The NCO operates at the rate equal By default, when an SPI write is completed for the frequency to the upsampled I data and Q data. The generated carrier tuning word, phase control, DAC gain scaling, or DAC offset signal is mixed via multipliers with the I data and Q data. The registers (Register 0x0A through Register 0x0D), the operation quadrature products are then summed. of the AD9785/AD9787/AD9788 is immediately updated to Note that the sine output of the NCO contains a mux that reflect these changes. However, in many applications it may be allows negating of the data. The mux is controlled with a more useful to update these registers without changing the spectral inversion bit that the user stores in an I/O register device operation until all these functions can be updated at (Register 0x01, Bit 10). The default condition is to select once. With the automatic I/O transfer enable bit set low in the negated sine data. COMM register (Register 0x00, Bit 1), the value of all these functions is stored in a buffer after the initial SPI write. To NUMERICALLY CONTROLLED OSCILLATOR update all these functions simultaneously, Bit 2 of the COMM The NCO generates a complex carrier signal to translate the register should be set. This bit is self-resetting and thus does not input signal to a new center frequency. A complex carrier signal require another reset in a later SPI write. is a pair of sinusoidal waveforms of the same frequency, offset 90° from each other. The frequency of the complex carrier INVERSE SINC FILTER signal is set via the Frequency Tuning Word [31:0] value in The inverse sinc filter is implemented as a nine-tap FIR filter. It Register 0x0A. The frequency of the complex carrier signal is is designed to provide greater than ±0.05 dB pass-band ripple calculated as follows: up to a frequency of 0.4 × fDACCLK. To provide the necessary 31 32 If {0 ≤ FTW ≤ 2 }, use f = (FTW) (f )/2 peaking at the upper end of the pass band, the inverse sinc filter CENTER DACCLK has an intrinsic insertion loss of 3.4 dB. The tap coefficients are 31 32 32 If {2 < FTW < 2 − 1}, use f = f × (1 − (FTW/2 )) CENTER DACCLK given in Table 31. A 16-bit phase offset may be added to the output of the phase accumulator via the serial port. This static phase adjustment I INTERPOLATION DATA COSINE FTW [31:0] NCO NCO PHASE OFFSET OUT_I WORD [15:0] SINE OUT_Q – + –1 SPECTRAL 0 1 INVERSION Q INTERPOLATION DATA Figure 58. Quadrature Modulator Block Diagram Rev. A | Page 40 of 64 07098-107 AD9785/AD9787/AD9788 Table 31. Inverse Sinc Filter 20 0 Lower Coefficient Upper Coefficient Integer Value H(1) H(9) +2 H(2) H(8) −4 15 5 H(3) H(7) +10 H(4) H(6) −35 H(5) – +401 10 10 The inverse sinc filter is disabled by default. It can be enabled by setting the inverse sinc enable bit (Bit 9) in Register 0x01. 5 15 DIGITAL AMPLITUDE AND OFFSET CONTROL The gain of the I datapath and the Q datapath can be independ- 0 20 0x0000 0x4000 0x8000 0xC000 0xFFFF ently scaled by adjusting the I DAC Amplitude Scale Factor [8:0] DAC OFFSET VALUE or Q DAC Amplitude Scale Factor [8:0] value in Register 0x0C. Figure 59. DAC Output Currents vs. DAC Offset Value These values control the input to a digital multiplier. The value of the scale factor ranges from 0 to 3.9921875 and can be The offset currents generated by the DAC offset parameter calculated as follows: increase from 0 mA to 10 mA as the offset is swept from 0 to 0x7FFF. The offset currents increase from −10 mA to 0 mA as Scale Factor [8 : 0] Scale Factor Value the offset is swept from 0x8000 to 0xFFFF. 128 DIGITAL PHASE CORRECTION The digital scale factor can be used to compensate for amplitude The purpose of the phase correction block is to enable compens- imbalance between the I and Q channels or to provide equal ation of the phase imbalance of the analog quadrature modulator gain scaling to both channels for output level adjustment. Note following the DAC. If the quadrature modulator has a phase that when the gain is set to 1.0 (scale factor = 0x80), the gain imbalance, the unwanted sideband appears with significant block is bypassed. When bypassed, the gain block has a different energy. Adjusting the phase correction word can optimize image delay from when it is used. Therefore, to maintain matched rejection in single sideband radios. latency in each path, both gain blocks should be set to exactly 1.0, or neither path should be set to exactly 1.0. Failing to Ordinarily the I and Q channels have an angle of precisely 90° maintain matched latencies in the I and Q paths creates a phase between them. The Phase Correction Word [9:0] (Register 0x0B) imbalance in quadrature signals, which results in poor sideband is used to change the angle between the I and Q channels. When suppression of upconverted signals. the Phase Correction Word [9:0] is set to 1000000000b, the Q DAC output moves approximately 14° away from the I DAC The dc value of the I datapath and the Q datapath can also be output, creating an angle of 104° between the channels. When independently controlled. This is accomplished by adjusting the Phase Correction Word [9:0] is set to 0111111111b, the the I DAC Offset [15:0] and Q DAC Offset [15:0] values in Q DAC output moves approximately 14° towards the I DAC Register 0x0D. These values are added directly to the datapath output, creating an angle of 76° between the channels. Based on values. Care should be taken not to overrange the transmitted these two endpoints, the resolution of the phase compensation values. register is approximately 28°/1024 or 0.027° per code. Figure 59 shows how the DAC offset current varies as a function of the I DAC Offset [15:0] and Q DAC Offset [15:0] values. With the digital inputs fixed at midscale (0x0000, twos complement data format), the figure shows the nominal I and I OUTx_P OUTx_N currents as the DAC offset value is swept from 0 to 65535. Because IOUTx_P and IOUTx_N are complementary current outputs, the sum of IOUTx_P and IOUTx_N is always 20 mA. Rev. A | Page 41 of 64 I (mA) OUTx_P I (mA) OUTx_N 07098-108 AD9785/AD9787/AD9788 DEVICE SYNCHRONIZATION System demands may impose two different requirements for initialization pulse that sets the clock generation state machine synchronization. Some systems require multiple DACs to be logic to a known state. In pulse mode, this pulse is generated at synchronized to each other, for example, a system that supports every rising edge of the SYNC_I inputs. In PN code mode, the transmit diversity or beamforming, where multiple antennas are pulse is generated every time the correct code sequence is used to transmit a correlated signal. In this case, the DAC outputs received on the SYNC_I inputs. need to be phase aligned with each other, but there may not be a This initialization pulse loads the clock generation state machine requirement for the DAC outputs to be aligned with a system- with the Clock State [3:0] value (Register 0x03, Bits [7:4]) as its level reference clock. In systems with a time division multiplexing next state. If the initialization pulse from the synchronization transmit chain, one or more DACs may be required to be logic is generated properly, it is active for one DAC clock cycle, synchronized with a system-level reference clock. every 32 (or multiple of 32) DAC clock cycles. Because the clock Multiple devices are considered synchronized to each other generation state machine has 32 states operating at the DACCLK when the state of the clock generation state machines is rate, every initialization pulse received after the first pulse loads identical for all parts and the NCO phase accumulator is the current state (the state to which the state machine is already identical for all parts. Devices are considered synchronized to a set), maintaining the proper clock operation of the device. system clock when there is a fixed and known relationship The Clock State [3:0] value is the state to which the clock between the clock generation state machine and the NCO phase generation state machine resets upon initialization. By varying accumulator of the device to a particular clock edge of the this value, the timing of the internal clocks, with respect to system clock. The AD9785/AD9787/AD9788 support two the SYNC_I signal, can be adjusted. Every increment of the modes of operation, pulse mode and PN code mode, for Clock State [3:0] value advances the internal clocks by one synchronizing devices under these two conditions. DACCLK period. SYNCHRONIZATION LOGIC OVERVIEW The NCO phase accumulators can be initialized in pulse mode or PN code mode. In pulse mode, a simultaneous strobe signal Figure 60 shows a block diagram of the on-chip synchronization must be sent to the TXENABLE pin of all devices that is receive logic. There are two different modes of operation for the synchronous to the DATACLK signal. This signal resets the multichip synchronization feature: pulse mode and pseudorandom noise code (PN code) modulation/demodulation mode. The basic phase accumulator of the NCOs across all devices, effectively function of these two modes is to initialize the internal clock synchronizing the NCOs. generation state machine and the NCO phase accumulator In PN code mode, the phase information of the master device is upon the application of external signals to the device. sent to the slave devices by the SYNC_I signal. The slave devices decode this phase information and automatically initialize their The receive logic responsible for initializing the clock gener- NCO phase accumulators to match the master device. ation state machine generates a single DACCLK cycle-wide Rev. A | Page 42 of 64 AD9785/AD9787/AD9788 DACCLK INTERNAL CLOCK NCO PHASE • GENERATION CLOCKS ACCUMULATOR • • RESET STATE LD-STATE CLOCK NCO STATE [3:0] RESET GENERATOR PULSE MODE SYNC MODE 01 ENABLE SELECT TXENABLE TRANSMIT (PIN 39) PATH EDGE DETECTOR SYNC_I CODE PN CODE MODE ENABLE Δt (PIN 13, PIN 14) DEMODULATOR CORRELATE THRESHOLD [4:0] SYNC_I DELAY [4:0] SYNC ERROR SYNC TIMING SYNC_I DETECTOR ERROR IRQ ENABLE Figure 60. Synchronization Receive Circuitry Block Diagram MATCHED LENGTH TRACES REFCLK OUT TXENABLE SYNC_I SYSTEM CLOCK LOW SKEW CLOCK DRIVER REFCLK TXENABLE OUT PULSE GENERATOR SYNC_I LOW SKEW MATCHED CLOCK DRIVER LENGTH TRACES Figure 61. Multichip Synchronization in Pulse Mode Rev. A | Page 43 of 64 07098-102 07098-104 AD9785/AD9787/AD9788 high logic level pin, the strobe signal should be a low logic level SYNCHRONIZING DEVICES TO A SYSTEM CLOCK pulse unless the TXENABLE invert bit is set in the SPI. The AD9785/AD9787/AD9788 offer a pulse mode synchron- For this synchronization scheme, all devices are slave devices, ization scheme (see Figure 61) to align the DAC outputs of multiple devices within a system to the same DAC clock edge. while the system clock generation/distribution chip serves as The pulse mode synchronization scheme is a two-part the master. The external LVDS signal should be connected to the operation. First, the internal clocks are synchronized by SYNC_I inputs of all the slave devices following the constraints. providing either a one-time pulse or periodic signal to the The DAC clock inputs and the SYNC_I inputs must be matched in length across all devices. SYNC_I (SYNC_I+/SYNC_I−) inputs. The SYNC_I signal is sampled by the internal DACCLK sample rate clock. It is vital that the SYNC_I signal be distributed between the DACs with low skew. Likewise, the REFCLK signals must be The SYNC_I input frequency has the following two constraints: distributed with low skew. Any skew on these signals between f  f SYNC _ IN DATACLK the DACs must be accounted for in the timing budget. The f DAC SYNC_I signal is sampled at the DACCLK rate, thus the data f  SYNC _ IN 16 N valid window of the SYNC_I pulse must be presented to all the DACs within the same DACCLK period. where N is an integer. Figure 62 shows the timing of the SYNC_I input with respect to When the internal clocks are synchronized, the data sampling the REFCLK input. Note that although the timing is relative to clocks between all devices are phase aligned. The next step the REFCLK signal, SYNC_I is sampled at the DACCLK rate. requires a simultaneous strobe signal to the TXENABLE pin of This means that the rising edge of the SYNC_I signal must all devices that is synchronous to the DATACLK signal. This occur after the hold time of the preceding DACCLK rising edge resets the phase accumulator of the NCOs across all devices, and not the preceding REFCLK rising edge. Figure 63 shows a effectively synchronizing the NCOs. The strobe signal is timing diagram of the TXENABLE input. sampled by fDATACLK and must meet the same setup and hold times as the input data. Because the TXENABLE pin is an active SYNC_I t H_SYNC t REFCLK S_SYNC DACCLK Figure 62. Timing Diagram of SYNC_I with Respect to REFCLK REFCLK DATACLK t t SREFCLK HREFCLK t t SDATACLK HDATACLK TXENABLE Figure 63. Timing Diagram of TXENABLE vs. DATACLK and REFCLK Rev. A | Page 44 of 64 07098-106 07098-105 AD9785/AD9787/AD9788 Table 32 shows the register settings required to enable the pulse 6. Read back sync timing error IRQ and sync timing error mode synchronization feature. type (Register 0x09, Bit 4). If sync timing error IRQ is high, a sampling error has occurred, and sync timing error type Table 32. Register Settings for Enabling Pulse Sync Mode indicates whether the sampling error is due to a setup time Register Bit Parameter Value violation or a hold time violation. 0x01 [13] PN code sync enable 0 7. Adjust the SYNC_I Delay [4:0] value until the sync timing [12] Sync mode select 0 error IRQ is no longer present. [11] Pulse sync enable 1 SYNCHRONIZING MULTIPLE DEVICES TO EACH 0x03 [26] SYNC_I enable 1 OTHER [25] SYNC_O enable 0 [10] Set high 1 The AD9785/AD9787/AD9788 synchronization engine uses a PN code synchronization scheme to align multiple devices Synchronization Timing Error Detection within a system to the same DAC clock edge. The PN code The synchronization logic has error detection circuitry similar scheme synchronizes all the internal clocks, as well as the phase to the input data timing. The Sync Timing Margin [3:0] variable accumulator of the NCO for all devices. With this scheme, one (Register 0x03) determines the setup and hold margin that the device functions as the master, and the remainder of the devices synchronization interface needs for the SYNC timing error IRQ are configured as slaves. to remain inactive (show error-free operation). Thus, the SYNC The master device generates the PN encoded signal and drives timing error IRQ is set whenever the setup and hold margins the signal out on the SYNC_O (SYNC_O+/SYNC_O−) output drop below the Sync Timing Margin [3:0] value and does not pins. This signal is then sent to the SYNC_I (SYNC_I+/ necessarily indicate that the SYNC_I input was latched incorrectly. SYNC_I−) inputs of all the slave devices and to itself. The slave When a SYNC timing error IRQ is set, corrective action can devices receive the code from the master and demodulate the restore the timing margin. The device can be configured for signal to produce a synchronization pulse every time a valid manual mode sync error monitoring and error correction. code is received. The encoded signal of every device must be Follow these steps to monitor SYNC_I setup and hold timing sampled on the same DAC clock edge for the devices to be margins in manual mode: properly synchronized. Therefore, it is extremely important that the REFCLK signals arrive at all the devices with as little skew 1. Set sync error check mode (Register 0x03, Bit 18) = 0 between them as possible. In addition, the SYNC_I signals must (manual check mode). arrive at all the devices with as little skew as possible. At high 2. Set Sync Timing Margin [3:0] (Register 0x03, Bits [3:0]) = DACCLK frequencies, this requires using low skew clock 0000 (timing margin to minimum value). distribution devices to deliver the REFCLK and SYNC_I signals 3. Set SYNC_I Delay [4:0] (Register 0x03, Bits [23:19]) = and paying careful attention to printed circuit board signal 00000 (SYNC_I delay line to minimum value). routing to equalize the trace lengths of these signals. 4. Set sync port IRQ enable (Register 0x09, Bit 0) = 1. 5. Write 1 to sync timing error IRQ (Register 0x09, Bit 6) to clear. MATCHED LENGTH TRACES REFCLK OUT TXENABLE SYNC_I SYSTEM CLOCK LOW SKEW CLOCK DRIVER REFCLK TXENABLE OUT SYNC_I SYNC_O LOW SKEW MATCHED CLOCK DRIVER LENGTH TRACES Figure 64. Multichip Synchronization in PN Code Mode Rev. A | Page 45 of 64 07098-103 AD9785/AD9787/AD9788 Table 33 lists the register settings required to enable the PN The Correlate Threshold [4:0] value (Register 0x03, code mode synchronization feature. Bits [31:27]) indicates how closely the code of the received SYNC_I signal is to the expected code. A high threshold Table 33. Register Settings for Enabling PN Code Mode requires a closer match of the encoded signal to set the Register Bit Parameter Value sync lock status bit; a lower value reduces the matching 0x01 [13] PN code sync enable 1 requirements to set the sync lock status bit. [12] Sync mode select 1 Increasing the Correlate Threshold [4:0] value makes the part [11] Pulse sync enable 0 more resistant to false synchronization locks but requires a 0x03 [31:27] Correlate Threshold 10000 lower bit error rate on the SYNC_I input to maintain locked [4:0] status. Decreasing the Correlate Threshold [4:0] value makes [26] SYNC_I enable 1 the part more susceptible to false synchronization locks, but [25] SYNC_O enable 0 (slave devices) maintains a locked status in the face of a higher bit error rate 1 (master device) on the SYNC_I input (that is, it is more noise resistant). The [10] Set high 1 recommended value for Correlate Threshold [4:0] is the default To verify that the devices have successfully synchronized, read value of 16. back the sync lock status bit on all devices (Register 0x09, INTERRUPT REQUEST OPERATION Bit 10). The sync lock status bit should read back as 1 on all devices. Next, read back the sync lock lost status bit on all The IRQ pin (Pin 71) acts as an alert that the device has devices (Register 0x09, Bit 11). The sync lock lost status bit experienced a timing error and that it should be queried (by should read back as 0 on all devices. To clear the sync lock lost reading Register 0x09) to determine the exact fault condition. status bit, set the clear lock indicator bit to 1, followed by a 0 The IRQ pin is an open-drain, active low output. The IRQ pin (Register 0x09, Bit 12). should be pulled high external to the device. This pin may be tied to the IRQ pins of other devices with open-drain outputs to Because the SYNC_O signal generated by the master is spread wire-OR these pins together. over many bits, this method of synchronization is very robust. Any individual bits that may become corrupted or somehow There are two different error flags that can trigger an interrupt misread by the slave device usually have no effect on the request: a data timing error or a sync timing error. By default, synchronization of the device. If the devices do not reliably when either or both of these error flags are set, the IRQ pin is synchronize, there are several options for correcting the situation. active low. Either or both of these error flags can be masked to The SYNC_O Delay [4:0] value (Register 0x03, Bits [15:11]) on prevent them from activating an interrupt on the IRQ pin. the master device can be used to adjust the timing in 80 ps steps The error flags are latched and remain active until the flag bits effective across all devices. In addition, the SYNC_O polarity bit are overwritten. (Register 0x03, Bit 9) on the master device can be set to provide a delay of one half the DACCLK period. The SYNC_I Delay [4:0] bits (Register 0x03, Bits [23:19]) can be used to adjust the timing on a single slave device in 80 ps steps. Rev. A | Page 46 of 64 AD9785/AD9787/AD9788 DRIVING THE REFCLK INPUT on-chip clock multiplier removes the burden of generating and The REFCLK input requires a low jitter differential drive signal. distributing the high speed DACCLK. REFCLK is a PMOS input differential pair powered from the 1.8 V supply; therefore, it is important to maintain the specified 400 mV The second mode bypasses the clock multiplier circuitry and input common-mode voltage. Each input pin can safely swing allows DACCLK to be directly sourced through the REFCLK from 200 mV p-p to 1 V p-p about the 400 mV common-mode pins. This mode enables the user to source a very high quality voltage. Although these input levels are not directly LVDS- clock directly to the DAC core. Sourcing the DACCLK directly compatible, REFCLK can be driven by an offset ac-coupled through the REFCLK pins may be necessary in demanding LVDS signal, as shown in Figure 65. applications that require the lowest possible DAC output noise 0.1µF at higher output frequencies. LVDS_P_IN REFCLK+ In either case, using the on-chip clock multiplier or sourcing 50Ω the DACCLK directly through the REFCLK pins, it is necessary V = 400mV CM that the REFCLK signal have low jitter to maximize the DAC 50Ω noise performance. LVDS_N_IN REFCLK– 0.1µF Direct Clocking Figure 65. LVDS REFCLK Drive Circuit When the PLL is disabled (Register 0x04, Bit 15 = 0), the If a clean sine clock is available, it can be transformer-coupled REFCLK input is used directly as the DAC sample clock to REFCLK, as shown in Figure 66. Use of a CMOS or TTL (DACCLK). The output frequency of the DATACLK output clock is also acceptable for lower sample rates. It can be routed pin is through a CMOS-to-LVDS translator, then ac-coupled. f = f /(IF × P) DATACLK DACCLK 0.1µF 50Ω TTL OR CMOS REFCLK+ where IF is the interpolation factor, set in Register 0x01, Bits [7:6], CLK INPUT and P = 0.5 if in single-port mode. Clock Multiplication REFCLK– 50Ω BAV99ZXCT When the PLL is enabled (Register 0x04, Bit 15 = 1), the clock HIGH SPEED DUAL DIODE multiplication circuit generates the DAC sample clock from the V = 400mV CM lower rate REFCLK input. The functional diagram of the clock Figure 66. TTL or CMOS REFCLK Drive Circuit multiplier is shown in Figure 68. A simple bias network for generating V is shown in Figure 67. CM The clock multiplication circuit operates such that the VCO It is important to use CVDD18 and CGND for the clock bias outputs a frequency, fVCO, equal to the REFCLK input signal circuit. Any noise or other signal that is coupled onto the clock frequency multiplied by N1 × N2. is multiplied by the DAC digital input signal and can degrade fVCO = fREFCLK × (N1 × N2) DAC performance. The DAC sample clock frequency, fDACCLK, is equal to V = 400mV CM f = f × N2 DACCLK REFCLK CVDD18 1kΩ The values of N1 and N2 must be chosen to keep f in the VCO 1nF optimal operating range of 1.0 GHz to 2.0 GHz. When the VCO 287Ω 0.1µF1nF CGND output frequency is known, the correct PLL band select value Figure 67. REFCLK V Generator Circuit CM (Register 0x04, Bits [7:2]) can be chosen. DAC REFCLK CONFIGURATION PLL Bias Settings There are three bias settings for the PLL circuitry that should be The AD9785/AD9787/AD9788 offer two modes of sourcing programmed to their nominal values. The PLL values shown in the DAC sample clock (DACCLK). The first mode employs an Table 34 are the recommended settings for these parameters. on-chip clock multiplier that accepts a reference clock operating at the lower input frequency, most commonly the data input Table 34. PLL Settings frequency. The on-chip phase-locked loop (PLL) then multiplies Address Optimal the reference clock up to a higher frequency, which can then be PLL SPI Control Register Bit Setting used to generate all the internal clocks required by the DAC. PLL Loop Bandwidth 0x04 [20:16] 01111 The clock multiplier provides a high quality clock that meets PLL VCO Drive 0x04 [1:0] 11 the performance requirements of most applications. Using the PLL Bias 0x04 [10:8] 011 Rev. A | Page 47 of 64 07098-024 07098-026 07098-025 AD9785/AD9787/AD9788 0x04 [23:21] ADC VCO CONTROL PLL_LOCK (PIN 65) VOLTAGE 0x09 [3] REFCLK PHASE LOOP (PIN 5 AND PIN 6) VCO DETECTION FILTER ÷N ÷N 2 1 DAC 0x04 [12:11] 0x04 [14:13] INTERPOLATION PLL LOOP PLL VCO RATE DIVISOR DIVISOR ÷IF DATACLK (PIN 37) 0x01 [7:6] 0x04 [15] PLL ENABLE DAC CLOCK Figure 68. Clock Multiplication Circuit Table 35. Typical VCO Freq Range vs. PLL Band Select Value PLL Lock Ranges over Temperature, −40°C to +85°C PLL Lock Ranges over Temperature, −40°C to +85°C 1 1 VCO Frequency Range in MHz VCO Frequency Range in MHz PLL Band Select f f PLL Band Select f f LOW HIGH LOW HIGH 111111 (63) Auto mode Auto mode 011111 (31) 1402 1468 111110 (62) 1975 2026 011110 (30) 1397 1451 111101 (61) 1956 2008 011101 (29) 1361 1427 111100 (60) 1938 1992 011100 (28) 1356 1412 111011 (59) 1923 1977 011011 (27) 1324 1389 111010 (58) 1902 1961 011010 (26) 1317 1375 111001 (57) 1883 1942 011001 (25) 1287 1352 111000 (56) 1870 1931 011000 (24) 1282 1336 110111 (55) 1848 1915 010111 (23) 1250 1313 110110 (54) 1830 1897 010110 (22) 1245 1299 110101 (53) 1822 1885 010101 (21) 1215 1277 110100 (52) 1794 1869 010100 (20) 1210 1264 110011 (51) 1779 1853 010011 (19) 1182 1242 110010 (50) 1774 1840 010010 (18) 1174 1231 110001 (49) 1748 1825 010001 (17) 1149 1210 110000 (48) 1729 1810 010000 (16) 1141 1198 101111 (47) 1730 1794 001111 (15) 1115 1178 101110 (46) 1699 1780 001110 (14) 1109 1166 101101 (45) 1685 1766 001101 (13) 1086 1145 101100 (44) 1684 1748 001100 (12) 1078 1135 101011 (43) 1651 1729 001011 (11) 1055 1106 101010 (42) 1640 1702 001010 (10) 1047 1103 101001 (41) 1604 1681 001001 (9) 1026 1067 101000 (40) 1596 1658 001000 (8) 1019 1072 100111 (39) 1564 1639 000111 (7) 998 1049 100110 (38) 1555 1606 000110 (6) 991 1041 100101 (37) 1521 1600 000101 (5) 976 1026 100100 (36) 1514 1575 000100 (4) 963 1011 100011 (35) 1480 1553 000011 (3) 950 996 100010 (34) 1475 1529 000010 (2) 935 981 100001 (33) 1439 1505 000001 (1) 922 966 100000 (32) 1435 1489 000000 (0) 911 951 1 The lock ranges in this table are typical values. Actual lock ranges will vary from device to device. Rev. A | Page 48 of 64 07098-027 AD9785/AD9787/AD9788 4. Based on the temperature when the PLL auto mode is Configuring the PLL Band Select Value enabled, set the PLL band indicated in Table 36 or Table 37 The PLL VCO has a valid operating range from approximately by rewriting the readback values into the PLL Band Select 1.0 GHz to 2.0 GHz covered in 63 overlapping frequency bands [5:0] parameter (Register 0x04, Bits [7:2]). as shown in Table 35. For any desired VCO output frequency, there are multiple valid PLL band select values. Note that the Table 36. Setting Optimal PLL Band for Lower Range data shown in Table 35 is for a typical device. Device-to-device (0 to 31) Bands variations can shift the actual VCO output frequency range by System Start-Up Temperature Set PLL Band to 30 MHz to 40 MHz. Also, the VCO output frequency varies as −40°C to −10°C Readback Band + 2 a function of temperature. Therefore, it is required that the −10°C to +15°C Readback Band + 1 optimal PLL band select value be determined for each 15°C to 55°C Readback Band individual device at the particular operating temperature. 55°C to 85°C Readback Band − 1 The device has an automatic PLL band select feature on chip. Table 37. Setting Optimal PLL Band for Higher Range When enabled, the device determines the optimal PLL band (32 to 62) Bands setting for the device at the given temperature. This setting holds System Start-Up Temperature Set PLL Band to for a ±60°C temperature swing in ambient temperature. If the −40°C to −30°C Readback Band + 3 device operates in an environment that experiences a larger −30°C to −10°C Readback Band + 2 temperature swing, an offset should be applied to the automat- −10°C to +15°C Readback Band + 1 ically selected PLL band. The following procedure outlines a 15°C to 55°C Readback Band method for setting the PLL band select value for a device 55°C to 85°C Readback Band − 1 operating at a particular temperature that holds for a change in ambient temperature over the total −40°C to +85°C operating Known Temperature Calibration with Memory range of the device without further user intervention. (Note that The procedure in the Configuring PLL Band Select with REFCLK must be applied to the device during this procedure.) Temperature Sensing section requires temperature sensing Configuring PLL Band Select with Temperature Sensing upon start-up or reset of the device to choose the optimal PLL band select value to hold over the entire operating temperature The values of N1 (Register 0x04, Bits [14:13]) and N2 range. If temperature sensing is not available in the system, (Register 0x04, Bits [12:11]) should be programmed along another option is to use the automatic PLL band select to with the PLL settings shown in Table 34. determine the optimal setting for the device when the device is 1. Set the PLL Band Select [5:0] value (Register 0x04, in a factory environment where the temperature is known. The Bits [7:2]) to 63 to enable PLL auto mode. optimal band can then be stored in nonvolatile memory. 2. Wait for the PLL_LOCK pin or the PLL lock indicator Whenever the system is powered up or restarted, the optimal (Register 0x09, Bit 3) to go high. This should occur value can be loaded back into the device. within 5 ms. 3. Read back the 6-bit PLL band select value (Register 0x04, Bits [7:2]). Rev. A | Page 49 of 64 AD9785/AD9787/AD9788 ANALOG OUTPUTS Full-scale current on the I DAC and Q DAC can be set from DIGITAL AMPLITUDE SCALING 8.66 mA to 31.66 mA. Initially, the 1.2 V band gap reference is Gain scaling of the analog DAC output can be achieved by used to set up a current in an external resistor connected to changing the values in Register 0x05 and Register 0x07. I120 (Pin 75). A simplified block diagram of the reference However, if this is done, the output common-mode voltage at circuitry is shown in Figure 69. the analog output also decreases proportionally. This poses a problem when the AD9785/AD9787/AD9788 are dc-coupled to AD9788 I DAC GAIN a quadrature modulator. Typical quadrature modulators have 1.2V BAND GAP REFERENCE I DAC tight restrictions on input common-mode variation. 5kΩ VREF The AD9785/AD9787/AD9788 use a digital gain scaling block DAC FULL-SCALE CURRENT REFERENCE I120 0.1µF SCALING to get around this problem. Because the gain scaling is done in CURRENT 10kΩ the digital processing of the AD9785/AD9787/AD9788, there is Q DAC no effect on the output full-scale current. This digital gain Q DAC GAIN scaling is done in such a way that the midscale value of the Figure 69. Full-Scale Current Generation Circuitry signal is unaffected; the swing of the signal around midscale is The recommended value for the external resistor is 10 kΩ, the value that is adjusted with the register settings. Digital gain which sets up an IREFERENCE in the resistor of 120 μA, which in scaling is done using the amplitude scale factor (ASF) register turn provides a DAC output full-scale current of 20 mA. Because (Register 0x0C). the gain error is a linear function of this resistor, a high precision Auxiliary DAC Operation resistor improves gain matching to the internal matching Two auxiliary DACs are provided on the AD9785/AD9787/ specification of the devices. Internal current mirrors provide AD9788. The full-scale output current on these DACs is derived a current-gain scaling, where DAC gain is a 10-bit word in the from the 1.2 V band gap reference and external resistor. The SPI port register (Register 0x05 and Register 0x07). The default gain scale from the reference amplifier current, I , to the REFERENCE value for the DAC gain registers gives an IFS of approximately auxiliary DAC reference current is 16.67 with the auxiliary DAC 20 mA, where IFS for either I DAC or Q DAC is equal to gain set to full scale (10-bit values, Register 0x06, Bits [9:0] and 1.2 V 27 6     Register 0x08, Bits [9:0]). This gives a full-scale current of approx-    DAC gain  32     R 12  1024    imately 2 mA for Auxiliary DAC 1 and Auxiliary DAC 2. The auxiliary DAC outputs are not differential. Only one side of 35 the auxiliary DAC (P or N) is active at one time. The inactive side goes into a high impedance state (100 kΩ). In addition, the P or N 30 output can act as a current source or a current sink. Control of the P and N sides for both auxiliary DACs is via Register 0x06 and 25 Register 0x08, Bits [15:14]. When sourcing current, the output compliance voltage is 0 V to 1.6 V. When sinking current, the 20 output compliance voltage is 0.8 V to 1.6 V. 15 10 5 0 0 200 400 600 800 1000 DAC GAIN CODE Figure 70. DAC Full-Scale Current vs. DAC Gain Code Rev. A | Page 50 of 64 I (mA) FS 07098-031 07098-030 AD9785/AD9787/AD9788 There are two output signals on each auxiliary DAC. One signal The choice of sinking or sourcing should be made at circuit is designated P, the other N. The sign bit in each auxiliary DAC design time. There is no advantage to switching between control register (Bit 15) controls whether the P side or the N side sourcing and sinking current after the circuit is in place. of the auxiliary DAC is turned on. Only one side of the auxiliary The auxiliary DACs can be used for local oscillator (LO) cancel- DAC is active at a time. The auxiliary DAC structure is shown lation when the DAC output is followed by a quadrature modu- in Figure 71. lator. This LO feedthrough is caused by the input referred dc offset voltage of the quadrature modulator (and the DAC output 0TO 2mA (SOURCE) offset voltage mismatch) and can degrade system performance. AUX_P V BIAS Typical DAC-to-quadrature modulator interfaces are shown in Figure 72 and Figure 73. Often, the input common-mode 0TO 2mA AUX_N voltage for the modulator is much higher than the output (SINK) P/N compliance range of the DAC, so that ac coupling or a dc level SOURCE/ shift is necessary. If the required common-mode input voltage SINK on the quadrature modulator matches that of the DAC, then the Figure 71. Auxiliary DAC Structure dc blocking capacitors in Figure 72 can be removed. The magnitude of the auxiliary DAC 1 current is controlled by A low-pass or band-pass passive filter is recommended when the auxiliary DAC 1 control register (Register 0x06), and the spurious signals from the DAC (distortion and DAC images) at magnitude of the auxiliary DAC 2 current is controlled by the the quadrature modulator inputs can affect system performance. auxiliary DAC 2 control register (Register 0x08). These auxiliary Placing the filter at the location shown in Figure 72 and Figure 73 DACs have the ability to source or sink current. This selection is allows easy design of the filter, as the source and load impedances programmable via Bit 14 in either auxiliary DAC control register. can easily be designed close to 50 Ω. QUADRATURE MODULATOR V+ AUX DAC1 QUADRATURE MODULATOR V+ 0.1µF AUX OPTIONAL DAC2 QUAD MOD I DAC PASSIVE I INPUTS FILTERING 0.1µF 25Ω TO 50Ω 0.1µF OPTIONAL QUAD MOD Q DAC PASSIVE Q INPUTS FILTERING 0.1µF 25Ω TO 50Ω Figure 72. Typical Use of Auxiliary DACs AC Coupling to Quadrature Modulator AUX DAC1 OR DAC2 OPTIONAL QUAD MOD I OR Q DAC PASSIVE I AND Q INPUTS FILTERING 25Ω TO 50Ω 25Ω TO 50Ω Figure 73. Typical Use of Auxiliary DACs DC Coupling to Quadrature Modulator with DC Shift Rev. A | Page 51 of 64 07098-032 07098-115 07098-033 AD9785/AD9787/AD9788 POWER DISSIPATION Figure 74 through Figure 78 detail the power dissipation of the The power dissipation of the AVDD33 supply rail is independent AD9785/AD9787/AD9788 under a variety of operating conditions. of the digital operating mode and sample rate. The current drawn All of the graphs are taken with data being supplied to both the from the AVDD33 supply rail is typically 51 mA (182 mW) when I and Q channels. The power consumption of the device does the full-scale current of the I and Q DACs is set to the nominal not vary significantly with changes in the modulation mode or value of 20 mA. Changing the full-scale current directly impacts analog output frequency. Graphs of the total power dissipation the supply current drawn from the AVDD33 rail. For example, are shown along with the power dissipation of the DVDD18, if the full-scale current of the I DAC and the Q DAC is changed DVDD33, and CVDD18 supplies. to 10 mA each, the AVDD33 supply current drops to 31 mA. 1800 70 1600 60 1400 4× NCO 8× NCO 50 8× 1200 4× 2× NCO 40 1000 2× 800 30 8× NCO 600 8× 1× NCO 20 4× NCO 400 4× 1× 2× NCO 10 2× 200 1× NCO 1× 0 0 0 50 100 150 200 250 300 0 50 100 150 200 250 300 f (MSPS) f (MSPS) DATA DATA Figure 74. Power Dissipation, I and Q Data, Dual DAC Mode Figure 76. Power Dissipation, Digital 3.3 V Supply, I and Q Data, Dual DAC Mode 120 1400 4× NCO 1200 100 8× NCO 1000 4× 80 8× 800 2× NCO 60 600 2× 40 400 2× NCO 8× NCO 1× NCO 20 200 2× 8× 1× 1× NCO 4× NCO 1× 4× 0 0 0 50 100 150 200 250 300 0 50 100 150 200 250 300 f (MSPS) f (MSPS) DATA DATA Figure 75. Power Dissipation, Digital 1.8 V Supply, I and Q Data, Figure 77. Power Dissipation, Clock 1.8 V Supply, I and Q Data, Dual DAC Mode Dual DAC Mode Rev. A | Page 52 of 64 POWER (mW) POWER (mW) 07098-036 07098-035 POWER (mW) POWER (mW) 07098-038 07098-037 AD9785/AD9787/AD9788 140 120 100 80 60 40 20 0 0 200 400 600 800 1000 f (MSPS) DAC Figure 78. Digital 1.8 V Supply, Power Dissipation of Inverse Sinc Filter Rev. A | Page 53 of 64 POWER (mW) 07098-039 AD9785/AD9787/AD9788 AD9785/AD9787/AD9788 EVALUATION BOARDS The remainder of this data sheet describes the evaluation The factory default jumper configuration is as follows: boards for testing the AD9785, AD9787, and AD9788 devices.  Jumpers JP2, JP3, JP4, and JP8 are unsoldered. OUTPUT CONFIGURATION  Jumpers JP14, JP15, JP16, and JP17 are soldered. Each evaluation board contains an Analog Devices ADL5372 To evaluate the ADL5372 on the evaluation board, reverse the quadrature modulator. The AD9785/AD9787/AD9788 devices jumper positions as follows: and the ADL5372 provide an easy-to-interface DAC/modulator  Jumpers JP2, JP3, JP4, and JP8 are soldered. combination that can be easily characterized on the evaluation board.  Jumpers JP14, JP15, JP16, and JP17 are unsoldered. Solderable jumpers can be configured to evaluate the single- Note that the ADL5372 also requires its own separate 5 V and ended or differential outputs of the AD9785/AD9787/AD9788. GND connection on the evaluation board. DIGITAL PICTURE OF EVALUATION BOARD 5V POWER SYNC INPUTS REFCLK INPUT S5 GND JP4 JP15 +5V DIGITAL DATA JP8 JP14 INPUTS ADL5372 S8 OUTPUT AD9788 ADL5372 ADL5372 S9 LO INPUT JP3 JP16 DATACLK JP2 JP17 OUTPUT S6 RESET SYNC OUTPUTS SPI PORT Figure 79. Evaluation Board Rev. A | Page 54 of 64 07098-058 AD9785/AD9787/AD9788 EVALUATION BOARD SOFTWARE Figure 80 shows this user interface. The most important A GUI .exe file for Microsoft® Windows® is included on the CD features for configuring the AD9785/AD9787/AD9788 are that ships with the evaluation board. This file allows the user to called out in the figure. easily program all the functions on the AD9785/AD9787/AD9788. INTERPOLATION AND FILTER MODE SETTINGS I/Q FULL SCALE OUTPUT CURRENT CONTROL I/Q CHANNEL DIGITAL GAIN I/Q OFFSET I/Q PHASE NCO FREQUENCY GAIN MATCHING SCALING CONTROL COMPENSATION AND PHASE OFFSET Figure 80. AD9788 User Interface Rev. A | Page 55 of 64 07098-059 AD9785/AD9787/AD9788 EVALUATION BOARD SCHEMATICS Figure 81. Evaluation Board, Power Supply and Decoupling Rev. A | Page 56 of 64 TP1 EXC-CL4532U1 TP14 RED VDDM_IN L12 TP13 EXC-CL4532U1 RED LC1812 VDDM L1 C67 RED LC1812 CVDD18_IN CVDD18 C66 .1UF C46 ACASE CC0402 CC0402 U6 C77 .1UF .1UF RED 3 4 SO14 TP15 22UF .1UF ACASE CC0603 CC0603 GND TP17 22UF 16V 74AC14 C68 C69 BLACK GND U6 TP2 16V 11 10 SO14 BLK 74AC14 U6 TP3 EXC-CL4532U1 9 8 SO14 RED L2 74AC14 LC1812 U6 DVDD18_IN DVDD18 56 SO14 74AC14 C76 .1UF .1UF RED ACASE CC0603 CC0603 22UF TP18 C71 C70 16V TP4 BLK TP5 EXC-CL4532U1 RED L3 LC1812 AVDD33_IN AVDD33 .1UF .1UF R51 9K U5 U5 C20 RED ACASE CC0603 CC0603 2 1 12 13 TP19 SO14 SO14 RC0805 22UF C28 C26 74AC14 74AC14 16V TP8 R53 9K U5 U5 BLK 43 10 11 SO14 SO14 RC0805 P1 74AC14 74AC14 1 TP6 R54 9K U5 U5 RED 2 6 589 EXC-CL4532U1 SO14 SO14 SPI_CSB RC0805 3 74AC14 74AC14 L4 SCLK 4 LC1812 DVDD33_IN SPI_SDIO DVDD33 5 U6 U6 .1UF .1UF 12 13 12 6 SO14 SO14 RED SPI_SDO C21 ACASE CC0603 CC0603 74AC14 74AC14 TP20 22UF C45 C42 TJAK06RAP CLASS=IO 16V TP9 R55 FCI-68898 R52 BLK 10K 10K RED TP16 RC080 5 RC080 5 07098-044 S8 IOUT_N S9 1 6 1 6 QN 1 T2B T1B R10 1 50 QOUT_N 2 PS PS IN T3A T4A 34 34 2 50 JP16 TC1-1T TC1-1T S6 ADTL1-12 ADTL1-12 R7 0 R9 34 JP14 RC0603 R6 34 2 6 1 RC0603 R8 0 2 1 6 6 1 QOUT-QOUT_P 2 2 RC0603 1 6 0 JP15 2 4 3 RC0603 JP17 1 4 3 0 ADTL1-12 ADTL1-12 TC1-1T TC1-1T S5 QP 4 3 4 3 R5 T2A T1A 50 S P S P IOUT-IOUT_P IP R1 R11 T3B T4B 6 1 6 1 50 DVDD33 JP2 JP3 D2P D2N C34 1NF C62 C33 JP4 JP8 D1N .1UF 1NF RC1206 D1P C61 C38 C37 1NF C4 0 .1UF 1NF C18 .1UF .1UF C60 250 JP1 .1UF C24 RC0603 6.3V S11 C25 AUX1_P IP C8 C59 C35 1NF 1 1NF 1NF R2 1NF S14 2 C10 C9 10UF 1 C39 .1UF .1UF .1UF R56 2 10K C1 DVDD33 C3 6 1NF AVDD33 C2 250 DVDD18 JP5 RC0603 C27 1NF AUX1_N IN R4 C11 .1UF C3 250 JP6 C58 RC0603 AUX2_P QP 1NF R14 C57 .1UF C29 C56 1NF 1NF C12 C55 .1UF .1UF C30 C31 1NF 1NF 250 JP11 C13 RC0603 C14 C4 AUX2_N QN .1UF .1UF 4.7UF R16 C5 4.7UF DVDD33 DVDD18 CVDD18 CLK_P CLK_N S15 1 P2D15 2 JP7 R59 S16 DVDD33 1 6 1 2 5 RC0805 S12 22 34 2 1 R58 6PINCONN RC0805 2 22 R18 100 DVDD33 10 U11 S7 4 PRE R3 2 25 11 9 J Q 3 PRE 5 1 Y GND J Q 13 RC0603 JP18 CLK 4 3 1 12 7 A CLK 2 2 K Q_ 2 6 CLR VCC NC K Q_ 5 1 DVDD33 CLR 14 .1UF U10 15 U10 74LCX112 C84 C78 74LCX112 SN74LVC1G34 4.7UF GND R26 100 C7 4.7UF C15 1NF C32 .1UF AD9785/AD9787/AD9788 R17 R15 R12 R3 RC 060 3 RC 060 3 RC 060 3 RC 060 3 50 0 50 0 50 0 50 0 R20 RC 060 3 R19 0 RC 060 3 DNP C6 CC 040 2 CC 040 2 CC 040 2 CC 040 2 CC 040 2 CC 040 2 CC 040 2 CC 040 2 CC 040 2 CC 040 2 ACA S E VOLT 4.7U F ACA S E CC 040 2 CC 040 2 CC 040 2 CC 040 2 1 10 0 VDDC 18 _ 1 VDDA 33 _10 0 VOLT 2 99 VDDC 18 _ 2 VSS A_99 3 98 VSS C_3 VDDA 33 _98 4.7U F 4 97 VSS C_4 VSS A_97 5 96 CLK_P VDDA 33 _96 6 95 CC 040 2 CC 040 2 CLK_N VSS A_95 7 94 VSS C_7 VSS A_94 IOUT1_P 8 93 VSS C_8 IOU T1_P 9 92 VDDC 18 _ 9 IOU T1_N 10 91 IOUT1_N VDDC 18 _10 VSS A_91 11 90 AUX1_P VSS C_11 AUX1_P 12 89 AUX1_N V SS_ 12 AUX1_N 13 88 SYNC_1P VSS A_88 14 87 AUX2_N SYNC_1N AUX2_N 15 86 AUX2_P VSS D_15 AUX2_P 16 85 VDDD 33 _16 VSS A_85 IOUT2_N 17 84 P1D15 P1D15 IOU T2_N 18 83 P1D14 P1D14 IOU T2_P 19 82 P1D13 P1D13 VSS A_82 IOUT2_P 20 81 P1D12 P1D12 VSS A_81 21 80 RC 060 3 RC 060 3 P1D11 P1D11 VDDA 33 _80 22 79 VSS D_22 VSS A_79 23 78 VDDD 18 _23 VDDA 33 _78 RC 080 5 24 77 P1D10 P1D10 VSS A_77 25 76 P1D9 P1D9 VDDA 33 _76 CC 060 3 26 75 P1D8 P1D8 I12 0 RC 060 3 27 74 P1D7 P1D7 VR E F _ 7 4 RED TP 11 28 73 RC 060 3 P1D6 P1D6 IPT AT 29 72 TP 12 P1D5 P1D5 VSS_ 72 CR1 RC 120 6 30 71 P1D4 RED P1D4 IRQ 1K 31 70 R64 VAL P1D3 P1D3 R ESE T 32 69 VSS D_32 SP I_ C S B SPI_CSB 33 68 SPI_CLK VDDD 18 _33 SP I_ C L K 34 67 CC 060 3 P1D2 P1D2 SP I_S DI SPI_SDI SW1 35 66 P1D1 P1D1 SP I_ S DO SPI_SDO 42 RC 120 6 36 65 P1D0 P1D0 PLL _LO CK 3 1 37 64 DC LK VSS D_64 1K R65 38 63 VDDD 33 _38 SYNC_OP GN D ;5 39 62 R63 TX SYNC_ON 10 K 40 61 P2D15 P2D15 VDDD 33 _61 41 60 P2D14 P2D14 VDDD 18 _60 42 59 P2D13 P2D0 P2D13 P2D0 43 58 VDD 18 _43 P2D1 P2D1 44 57 VSS D_44 P2D2 P2D2 45 56 P2D12 P2D3 P2D12 P2D3 46 55 P2D11 P2D11 P2D4 P2D4 47 54 P2D10 P2D10 VSS D_54 48 53 P2D9 P2D9 VDDD 18 _53 49 52 P2D8 P2D8 P2D5 P2D5 50 51 P2D6 P2D7 P2D7 P2D6 PAD PAD 9779 T QF P U1 R21 RC 060 3 DNP 2 R22 1 RC 060 3 0 ACA S E VOLT CC 040 2 CC 040 2 CC 040 2 CC 040 2 ACA S E CC 040 2 CC 040 2 CC 040 2 CC 040 2 VOLT ACA S E VOLT 4.7U F CC 040 2 CC 040 2 CC 040 2 CC 040 2 CC 040 2 CC 040 2 ACA S E VOLT 4.7U F Figure 82. Evaluation Board, Analog and Digital Interfaces to TxDAC Rev. A | Page 57 of 64 07098-045 CR2 VAL ACA SE RC 060 3 RC 060 3 ACA S E ACA S E VOLT VOLT AD9785/AD9787/AD9788 34 T4 2 SP 1 5 ETC1-1-13 Figure 83. Evaluation Board, ADL5372 (FMOD2) Quadrature Modulator Rev. A | Page 58 of 64 MOD_IP VAL VAL CC0603 CC0603 C81 L10 C82 D1P LC0805 VAL D1N LC0805 VAL VAL VAL L11 CC0603 CC0603 MOD_IN C80 C79 VAL VAL MOD_QN CC0603 CC0603 C74 L8 C75 D2N LC0805 VAL .1UF 100PF LC0805 D2P C52 C51 VAL VAL VAL MOD_QP VDDM L9 CC0603 CC0603 C65 C64 C44 CC0402 CC0402 ACASE 10UF 10V MOD_QN MOD_IN GND MOD_QP MOD_IP VDDM 100PF U9 C83 R25 .1UF CC0402 JP12 18 10K 1 L17 C90 GND 17 2 LC0805 VDDM 16 3 VAL 15 4 VDDM LC0805 CC0402 14 5 VAL 13 C43 6 L18 CC0402 CC0402 CC0402 ACASE 10UF C50 C87 C47 10V 78 9 100PF FMOD .1UF GND 100PF VDDM C41 CC0402 CC0402 CC0402 ACASE 10UF C72 C63 10V .1UF CC0402 CC0402 GND 100PF 1 J3 MODULATED 2 GND OUTPUT GND 1 J4 2 GND R24 RC0603 R23 DNP RC0603 RC0603 DNP 100PF C53 PAD 24 23 22 100PF 10 21 C54 11 20 12 19 C73 100PF 07098-046 AD9785/AD9787/AD9788 Figure 84. Evaluation Board, TxDAC Clock Interface Rev. A | Page 59 of 64 CLK_P CVDD18 C19 R30 R28 .1UF T2 C16 CC0402 1K J1 25 DNP 4 3 1 2 P S 2 R13 5 1 VAL R31 R29 CC0402 ETC1-1-13 300 C17 C23 .1UF 25 .1UF CLK_N RC040 2 CC040 2 CC040 2 RC040 2 RC040 2 RC040 2 RC040 2 07098-047 AD9785/AD9787/AD9788 Figure 85. Evaluation Board, Digital Input Data Lines Rev. A | Page 60 of 64 P4 P4 P4 P4 P4 A1 B1 C1 D1 E1 A2 B2 C2 D2 E2 A3 B3 C3 P2D0 D3 E3 P2D1 A4 B4 C4 P2D2 D4 E4 P2D3 A5 B5 C5 P2D4 D5 E5 P2D5 A6 B6 C6 P2D6 D6 E6 P2D7 A7 B7 C7 P2D8 D7 E7 P2D9 A8 B8 C8 P2D10 D8 E8 P2D11 A9 B9 C9 P2D12 D9 E9 P2D13 A10 B10 C10 P2D14 D10 E10 P2D15 A11 B11 C11 D11 E11 A15 B15 C15 D15 E15 A16 B16 C16 D16 E16 A17 B17 C17 P1D0 D17 E17 P1D1 A18 B18 C18 P1D2 D18 E18 P1D3 A19 B19 C19 P1D4 D19 E19 P1D5 A20 B20 C20 P1D6 D20 E20 P1D7 A21 B21 C21 P1D8 D21 E21 P1D9 A22 B22 C22 P1D10 D22 E22 P1D11 A23 B23 C23 P1D12 D23 E23 P1D13 A24 B24 C24 P1D14 D24 E24 P1D15 A25 B25 C25 D25 E25 PKG_TYPE=MOLEX110 PKG_TYPE=MOLEX110 PKG_TYPE=MOLEX110 VAL VAL VAL PKG_TYPE=MOLEX110 PKG_TYPE=MOLEX110 VAL VAL GND TP7 BLK BLK 07098-048 AD9785/AD9787/AD9788 Figure 86. Evaluation Board, On-Board Power Supply Rev. A | Page 61 of 64 1 J2 U2 2 1 2 4 CVDD18_IN 3 JP19 P2 1UF 1UF ADP3339-1-8 1 CC0603 CC0603 2 C86 C85 VAL CNTERM_2P U3 1 2 4 DVDD18_IN 3 JP20 1UF 1UF ADP3339-1-8 CC0603 CC0603 C89 C88 U4 1 2 4 DVDD33_IN 3 JP21 ADP3339-3-3 1UF 1UF CC0603 CC0603 C92 C91 U7 1 2 4 AVDD33_IN 3 JP22 ADP3339-3-3 1UF 1UF CC0603 CC0603 C93 C94 07098-049 AD9785/AD9787/AD9788 OUTLINE DIMENSIONS 1.20 16.00 BSC SQ 0.75 MAX 0.60 14.00 BSC SQ 0.45 100 76 76 100 1 75 75 1 SEATING PIN 1 BOTTOM VIEW PLANE (PINS UP) TOP VIEW (PINS DOWN) CONDUCTIVE HEAT SINK 51 51 25 25 26 50 50 26 0.20 1.05 6.50 0.09 NOM 1.00 7° 0.95 3.5° 0° 0.15 0.50 BSC 0.27 COPLANARITY 0.08 0.05 0.22 0.17 COMPLIANT TO JEDEC STANDARDS MS-026-AED-HDT NOTES: 1. CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED. 2. THE PACKAGE HAS A CONDUCTIVE HEAT SLUG TO HELP DISSIPATE HEAT AND ENSURE RELIABLE OPERATION OF THE DEVICE OVER THE FULL INDUSTRIAL TEMPERATURE RANGE. THE SLUG IS EXPOSED ON THE BOTTOM OF THE PACKAGE AND ELECTRICALLY CONNECTED TO CHIP GROUND. IT IS RECOMMENDED THAT NO PCB SIGNAL TRACES OR VIAS BE LOCATED UNDER THE PACKAGE THAT COULD COME IN CONTACT WITH THE CONDUCTIVE SLUG. ATTACHING THE SLUG TO A GROUND PLANE WILL REDUCE THE JUNCTION TEMPERATURE OF THE DEVICE, WHICH MAY BE BENEFICIAL IN HIGH TEMPERATURE ENVIRONMENTS. 3. θ : 27.4°C/W WITH THERMAL PAD UNSOLDERED, 19.1°C/W WITH THERMAL PAD SOLDERED TO PCB. JA Figure 87. 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] (SV-100-1) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option 1 AD9785BSVZ 100-Lead TQFP_EP SV-100-1 −40C to +85C 1 AD9785BSVZRL 100-Lead TQFP_EP SV-100-1 −40C to +85C 1 AD9787BSVZ 100-Lead TQFP_EP SV-100-1 −40C to +85C 1 AD9787BSVZRL 100-Lead TQFP_EP SV-100-1 −40C to +85C 1 AD9788BSVZ 100-Lead TQFP_EP SV-100-1 −40C to +85C 1 AD9788BSVZRL 100-Lead TQFP_EP SV-100-1 −40C to +85C 1 AD9785-EBZ Evaluation Board 1 AD9787-EBZ Evaluation Board 1 AD9788-EBZ Evaluation Board 1 RoHS Compliant Part. Rev. A | Page 62 of 64 121207-A AD9785/AD9787/AD9788 NOTES Rev. A | Page 63 of 64 AD9785/AD9787/AD9788 NOTES ©2008–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07098-0-2/09(A) Rev. A | Page 64 of 64