ANALOG DEVICES AD9786

® 16-Bit, 200 MSPS/500 MSPS TxDAC+ with 2×/4×/8× Interpolation and Signal Processing AD9786 FEATURES PRODUCT HIGHLIGHTS 16-bit resolution, 200 MSPS input data rate 1. 16-bit, high speed, interpolating TxDAC+. IMD 90 dBc @10 MHz 2. 2×/4×/8× user-selectable interpolating filter. The filter Noise spectral density (NSD): −164 dBm/Hz @ 10 MHz eases data rate and output signal reconstruction filter WCDMA ACLR = 80 dBc @ 40 MHz IF requirements. DNL = ±0.3 LSB INL = ±0.6 LSB 3. 200 MSPS input data rate. Selectable 2×/4×/8× interpolation filters Selectable fDAC/2, fDAC/4, fDAC/8 modulation modes 4. Ultra high speed, 500 MSPS DAC conversion rate. Single- or dual-channel signal processing 5. Flexible clock with single-ended or differential input. Selectable image rejection Hilbert transform CMOS, 1 V p-p sine wave, and LVPECL capability. Flexible calibration engine Direct IF transmission features 6. Complete CMOS DAC function. It operates from a 3.1 V Serial control interface to 3.5 V single analog (AVDD) supply, 2.5 V digital supply, Versatile clock and data interface and a 3.3 V digital (DRVDD) supply. The DAC full-scale 3.3 V-compatible digital interface current can be reduced for lower power operation, and On-chip 1.2 V reference a sleep mode is provided for low power idle periods. 80-lead, thermally enhanced, TQFP_EP package 7. On-chip voltage reference. The AD9786 includes a 1.20 V temperature-compensated band gap voltage APPLICATIONS reference. Base stations: multicarrier WCDMA, GSM/EDGE, TD-SCDMA, IS136, TETRA 8. Multichip synchronization. Multiple AD9786 DACs can Instrumentation be synchronized to a single master AD9786 to ease timing RF signal generators, arbitrary waveform generators design requirements and optimize image reject transmit HDTV transmitters performance. Broadband wireless systems Digital radio links Satellite systems FUNCTIONAL BLOCK DIAGRAM LATCH 2× 2× 2× FSADJ I REFIO 0 Δt 90 P1B[15:0] f /2 ZERO IOUTA DAC 16-BIT DAC 0 STUFF f /4 IOUTB DAC 90 P2B[15:0] f /8 DAC SDIO 0 HILBERT SDO 90 CSB Q SCLK ×1 RESET DATACLK LATCH 2× 2× 2× CLK+ CLOCK DISTRIBUTION AND CONTROL CLK– Figure 1. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. DATA PORT DATA SYNCHRONIZER ASSEMBLER Re()/Im() CALIBRATION REFERENCE SPI CIRCUITS 03152-001 AD9786 TABLE OF CONTENTS Features .............................................................................................. 1 General Operation of the Serial Interface............................... 20 Applications....................................................................................... 1 Serial Interface Port Pin Descriptions ..................................... 20 Product Highlights ........................................................................... 1 MSB/LSB Transfers .................................................................... 21 Functional Block Diagram .............................................................. 1 Notes on Serial Port Operation ................................................ 21 Revision History ............................................................................... 3 Mode Control (via Serial Port)..................................................... 22 General Description ......................................................................... 4 Digital Filter Specifications ........................................................... 26 Specifications..................................................................................... 5 Digital Interpolation Filter Coefficients.................................. 26 DC Specifications ......................................................................... 5 Clock/Data Timing .................................................................... 27 Dynamic Specifications ............................................................... 6 Real and Complex Signals......................................................... 32 Digital Specifications ................................................................... 7 Modulation Modes..................................................................... 33 Absolute Maximum Ratings............................................................ 8 Power Dissipation....................................................................... 38 Thermal Resistance ...................................................................... 8 Hilbert Transform Implementation......................................... 40 ESD Caution.................................................................................. 8 Operating the AD9786 Rev. F Evaluation Board ....................... 44 Pin Configuration and Function Descriptions............................. 9 Power Supplies............................................................................ 44 Clock .............................................................................................. 9 PECL Clock Driver .................................................................... 44 Analog.......................................................................................... 10 Data Inputs.................................................................................. 45 Data .............................................................................................. 10 Serial Port .................................................................................... 45 Serial Interface ............................................................................ 11 Analog Output............................................................................ 45 Terminology .................................................................................... 12 Outline Dimensions ....................................................................... 55 Typical Performance Characteristics ........................................... 14 Ordering Guide .......................................................................... 55 Serial Control Interface.................................................................. 20 Rev. B | Page 2 of 56 AD9786 REVISION HISTORY Replaced Figure 26..........................................................................16 10/05—Rev. A to Rev. B Replaced Figure 27..........................................................................17 Updated Format.................................................................. Universal Changes to Table 15 ........................................................................22 Changes to Figure 1...........................................................................1 Change to Figure 44........................................................................26 Changes to Table 2 ............................................................................6 Replaced Figure 45..........................................................................26 Changes to Table 3 ............................................................................7 Change to Figure 47........................................................................27 Changes to External Sync Mode Section .....................................31 Change to Figure 48........................................................................27 Updated Outline Dimensions........................................................58 Change to Figure 51........................................................................29 Changes to Ordering Guide...........................................................58 Change to Figure 52........................................................................29 2/05—Rev. 0 to Rev. A Change to Figure 53........................................................................30 Changed DRVDD Supply Range...................................... Universal Change to DATAADJUST Synchronization Section..................31 Changes to DC Specifications .........................................................4 Changes to Power Dissipation Section.........................................40 Changes to Dynamic Specifications ...............................................5 Changes to Table 37 ........................................................................42 Changes to Digital Specifications....................................................6 Changes to Data Inputs Section ....................................................46 Changes to Absolute Maximum Ratings........................................7 Change to Figure 88........................................................................49 Change to Figure 2 ............................................................................8 Replaced Figure 95..........................................................................55 Replaced Figure 13..........................................................................14 Updated Outline Dimensions........................................................60 Replaced Figure 14..........................................................................14 Changes to Ordering Guide...........................................................60 Replaced Figure 16..........................................................................15 7/04—Revision 0: Initial Version Replaced Figure 21..........................................................................16 Replaced Figure 22..........................................................................16 Rev. B | Page 3 of 56 AD9786 GENERAL DESCRIPTION The AD9786 is a 16-bit, high speed, CMOS DAC with The flexible clock interface accepts a variety of input types such 2×/4×/8× interpolation and signal processing features tuned as 1 V p-p sine wave, CMOS, and LVPECL in single-ended or for communications applications. It offers state-of-the-art differential mode. Internal dividers generate the required data distortion and noise performance. The AD9786 was developed rate interface clocks. to meet the demanding performance requirements of multicarrier The AD9786 provides a differential current output, supporting and third-generation base stations. The selectable interpolation single-ended or differential applications; it provides a nominal filters simplify interfacing to a variety of input data rates while full-scale current from 10 mA to 20 mA. The AD9786 is also taking advantage of oversampling performance gains. The manufactured on an advanced, low cost, 0.25 μm CMOS process. modulation modes allow convenient bandwidth placement and selectable sideband suppression. Rev. B | Page 4 of 56 AD9786 SPECIFICATIONS DC SPECIFICATIONS T to T ; AVDD1, AVDD2, DRVDD = 3.3 V; ACVDD, ADVDD, CLKVDD, DVDD = 2.5 V; I = 20 mA, unless otherwise noted. MIN MAX OUTFS Table 1. Parameter Min Typ Max Unit RESOLUTION 16 Bits 1 DC Accuracy Integral Nonlinearity ±0.6 LSB Differential Nonlinearity ±0.3 LSB ANALOG OUTPUT Offset Error ±0.015 ±0.0175 % of FSR Gain Error (with Internal Reference) ±1.5 % of FSR 2 Full-Scale Output Current 10 20 mA Output Compliance Range –1.0 +1.0 V Output Resistance 10 MΩ REFERENCE OUTPUT Reference Voltage 1.15 1.23 1.30 V 3 Reference Output Current 1 μA REFERENCE INPUT Input Compliance Range 0.1 1.25 V Reference Input Resistance (External Reference Mode) 10 MΩ Small Signal Bandwith 200 kHz TEMPERATURE COEFFICIENTS Unipolar Offset Drift 0 ppm of FSR/°C Gain Drift (with Internal Reference) ±4 ppm of FSR/°C Reference Voltage Drift ±30 ppm/°C POWER SUPPLY AVDD1, AVDD2 Voltage Range 3.1 3.3 3.5 V Analog Supply Current (I + I) 50 mA AVDD1 AVDD2 I + I in Sleep Mode 18 mA AVDD1 AVDD2 ACVDD, ADVDD Voltage Range 2.35 2.5 2.65 V Analog Supply Current (IACVDD + IADVDD) 2.5 mA CLKVDD Voltage Range 2.35 2.5 2.65 V Clock Supply Current (I) 12 mA CLKVDD DVDD Voltage Range 2.35 2.5 2.65 V Digital Supply Current (IDVDD) 52.5 mA DRVDD Voltage Range 3.1 3.3 3.5 V Digital Supply Current (IDRVDD) 5.3 μA 4 Nominal Power Dissipation 1.25 W OPERATING RANGE –40 +85 °C 1 Measured at I driving a virtual ground. OUTA 2 Nominal full-scale current, IOUTFS, is 32× the IREF current. 3 Use an external amplifier to drive any external load. 4 Measured under the following conditions: fDATA = 125 MSPS, fDAC = 500 MSPS, 4× interpolation, fDAC/4 modulation, Hilbert off. Rev. B | Page 5 of 56 AD9786 DYNAMIC SPECIFICATIONS TMIN to TMAX; AVDD1, AVDD2, DRVDD = 3.3 V; ACVDD, ADVDD, CLKVDD, DVDD = 2.5 V; IOUTFS = 20 mA; differential transformer coupled output; 50 Ω doubly terminated, unless otherwise noted. Table 2. Parameter Min Typ Max Unit DYNAMIC PERFORMANCE Minimum DAC Output Update Rate 20 MHz Maximum DAC Output Update Rate (fDAC) 500 MSPS AC LINEARITY/BASEBAND MODE Spurious-Free Dynamic Range (SFDR) to Nyquist (fOUT = 0 dBFS) fDATA = 100 MSPS; fOUT = 5 MHz, 4×, 2× Interpolation 93 dBc f = 200 MSPS; f = 10 MHz 85 dBc DATA OUT f = 200 MSPS; f = 25 MHz 78 dBc DATA OUT fDATA = 200 MSPS; fOUT = 50 MHz 78 dBc Two-Tone Intermodulation (IMD) to Nyquist (fOUT1 = fOUT2 = –6 dBFS) fDATA = 200 MSPS; fOUT1 = 5 MHz; fOUT2 = 6 MHz 85 dBc f = 200 MSPS; f = 15 MHz; f = 16 MHz 85 dBc DATA OUT1 OUT2 f = 200 MSPS; f = 25 MHz; f = 26 MHz 84 dBc DATA OUT1 OUT2 f = 200 MSPS; f = 45 MHz; f = 46 MHz 80 dBc DATA OUT1 OUT2 fDATA = 200 MSPS; fOUT1 = 65 MHz; fOUT2 = 66 MHz 78 dBc fDATA = 200 MSPS; fOUT1 = 85 MHz; fOUT2 = 86 MHz 75 dBc Noise Power Spectral Density (NPSD) f = 156 MSPS; f = 10 MHz; 0 dBFS, 8 Tones, Separation = 500 kHz −164 dBm/Hz DATA OUT f = 156 MSPS; f = 50 MHz; 0 dBFS, 8 Tones, Separation = 500 kHz −161 dBm/Hz DATA OUT Adjacent Channel Power Ratio (ACLR) WCDMA ACLR with 3.84 MHz BW, Single Carrier IF = 21 MHz, fDATA = 122.88 MSPS, 4× Interpolation 80 dB IF = 224.76 MHz, f = 122.88 MSPS, 4× Interpolation, High-Pass Interpolation Filter Mode 72 dB DATA Rev. B | Page 6 of 56 AD9786 DIGITAL SPECIFICATIONS TMIN to TMAX; AVDD1, AVDD2, DRVDD = 3.3 V; ACVDD, ADVDD, CLKVDD, DVDD = 2.5 V; IOUTFS = 20 mA, unless otherwise noted. Table 3. Parameter Min Typ Max Unit DIGITAL INPUTS Logic 1 Voltage 1.6 V Logic 0 Voltage 0 0.9 V Logic 1 Current –10 +10 μA Logic 0 Current –10 +10 μA Input Capacitance 5 pF 1 CLOCK INPUTS Input Voltage Range 0 2.65 V Common-Mode Voltage 0.75 1.5 2.25 V Differential Voltage 0.5 1.5 V Latch Pulse Width (tLPW) 5 ns Data Setup Time to DACCLK Out in Master Mode (tS) −0.5 ns Data Hold Time to DACCLK Out in Master Mode (t) 2.9 ns H 1 See the Clock/Data Timing section for setup and hold times in various timing modes. Rev. B | Page 7 of 56 AD9786 ABSOLUTE MAXIMUM RATINGS Table 4. Stresses above those listed under Absolute Maximum Ratings Parameter With Respect to Rating may cause permanent damage to the device. This is a stress AVDD1, AVDD2, AGND1, AGND2, −0.3 V to +3.6 V rating only; functional operation of the device at these or any DRVDD ACGND, ADGND, other conditions above those indicated in the operational CLKGND, DGND section of this specification is not implied. Exposure to absolute −0.3 V to +2.8 V ACVDD, ADVDD, AGND1, AGND2, maximum rating conditions for extended periods may affect CLKVDD, DVDD ACGND, ADGND, device reliability. CLKGND, DGND AGND1, AGND2, AGND1, AGND2, −0.3 V to +0.3 V THERMAL RESISTANCE ACGND, ADGND, ACGND, ADGND, θ is specified for the worst-case conditions, that is, a device CLKGND, DGND CLKGND, DGND JA soldered in a circuit board for surface-mount packages. REFIO, FSADJ AGND1 −0.3 to AVDD1 + 0.3 IOUTA, IOUTB AGND1 −1.0 to AVDD1 +0.3 Table 5. Thermal Resistance P1B15 to P1B0, DGND −0.3 to DRVDD + 0.3 1 Package Type θJA Unit P2B15 to P2B0, RESET 80-lead TQFP_EP (Thermally Enhanced) 23.5 °C/W DATACLK DGND −0.3 to DRVDD + 0.3 ` 1 With thermal pad soldered to PCB. CLK+, CLK− CLKGND −0.3 to CLKVDD + 0.3 CSB, SCLK, DGND −0.3 to DRVDD + 0.3 SDIO, SDO Junction −65°C to +125°C Temperature Range Storage 150°C Temperature Lead Temperature 300°C (10 sec) ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. B | Page 8 of 56 AD9786 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 CLKVDD 1 60 FSADJ PIN 1 DNC 2 59 REFIO IDENTIFIER CLKVDD 3 58 RESET CLKGND 4 57 CSB CLK+ 5 56 SCLK CLK– 6 55 SDIO CLKGND 7 54 SDO DGND 8 53 DGND DVDD 9 52 DVDD AD9786 P1B15 10 51 P2B0 TOP VIEW P1B14 11 50 P2B1 (Not to Scale) P1B13 12 49 P2B2 P1B12 13 48 P2B3 P1B11 14 47 P2B4 P1B10 15 46 P2B5 DGND 16 45 DGND DVDD 17 44 DVDD P1B9 18 43 P2B6 P1B8 19 42 P2B7 P1B7 20 41 P2B8 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 DNC = DO NOT CONNECT Figure 2. Pin Configuration CLOCK Table 6. Clock Pin Function Descriptions Pin No. Mnemonic Direction Description 5, 6 CLK+, CLK– I Differential Clock Input. 2 DNC Do Not Connect. 31 DATACLK I/O DCLKEXT 0x02[3] Mode 0 Pin configured for input of channel data rate or synchronizer clock. Internal clock synchronizer can be turned on or off with DCLKCRC (0x02[2]). 1 Pin configured for output of channel data rate or synchronizer clock. 1, 3 CLKVDD Clock Domain 2.5 V. 4, 7 CLKGND Clock Domain 0 V. Rev. B | Page 9 of 56 P1B6 DNC P1B5 ADVDD P1B4 ADGND P1B3 ACVDD DGND ACGND DVDD AVDD2 P1B2 AGND2 P1B1 AVDD1 P1B0 AGND1 DRVDD IOUTA DATACLK IOUTB IQSEL/P2B15 AGND1 ONEPORTCLOCK/P2B14 AVDD1 P2B13 AGND2 DGND AVDD2 DVDD ACGND P2B12 ACVDD P2B11 ADGND P2B10 ADVDD P2B9 DNC 03152-002 AD9786 ANALOG Table 7. Analog Pin Function Descriptions Pin No. Mnemonic Direction Description 59 REFIO A Reference. 60 FSADJ A Full-Scale Adjust. 70, 71 IOUTB, IOUTA A Differential DAC Output Currents. 61 DNC Do Not Connect. 62, 79 ADVDD Analog Domain Digital Content 2.5 V. 63, 78 ADGND Analog Domain Digital Content 0 V. 64, 77 ACVDD Analog Domain Clock Content 2.5 V. 65, 76 ACGND Analog Domain Clock Content 0 V. 66, 75 AVDD2 Analog Domain Clock Switching 3.3 V. 67, 74 AGND2 Analog Domain Switching 0 V. 68, 73 AVDD1 Analog Domain Quiet 3.3 V. 69, 72 AGND1 Analog Domain Quiet 0 V. 80 DNC Do Not Connect. DATA Table 8. Data Pin Function Descriptions Pin No. Mnemonic Direction Description 10 to 15, 18 to P1B15 to P1B0 I Input Data Port 1. 24, 27 to 29 ONEPORT 0x02[6] Mode 0 Latched data routed for I channel processing. 1 Latched data demultiplexed by IQSEL and routed for interleaved I/Q processing. 32 IQSEL/P2B15 I ONEPORT IQPOL IQSEL/ 0x02[6] 0x02[1] P2B15 Mode (IQPOL = 0) 0 X X Latched data routed to Q channel Bit 15 (MSB) processing. 1 0 0 Latched data on Data Port 1 routed to Q channel processing. 1 0 1 Latched data on Data Port 1 routed to I channel processing. 1 1 0 Latched data on Data Port 1 routed to I channel processing. 1 1 1 Latched data on Data Port 1 routed to Q channel processing. 33 ONEPORTCLOCK/P2B14 I/O ONEPORT 0x02[6] 0 Latched data routed for Q channel Bit 14 processing. 1 Pin configured for output of clock at twice the channel data route. 34, 37 to 43, P2B13 to P2B0 I Input Data Port 2, Bit 13 to Bit 0. 46 to 51 30 DRVDD Digital Output Pin Supply, 3.3 V. 9, 17, 26, DVDD Digital Domain, 2.5 V. 36, 44, 52 8, 16, 25, DGND Digital Domain, 0 V. 35, 45, 53 Rev. B | Page 10 of 56 AD9786 SERIAL INTERFACE Table 9. Serial Interface Pin Function Descriptions Pin No. Mnemonic Direction Description 54 SDO O SDIODIR CSB 0x00[7] Mode 1 X High impedance. 0 0 Serial data output. 0 1 High impedance. 55 SDIO I/O SDIODIR CSB 0x00[7] Mode 1 X High impedance. 0 0 Serial data output. 0 1 Serial data input/output depending on Bit 7 of the serial instruction byte. 56 SCLK I Serial Interface Clock. 57 CSB I Serial Interface Chip Select. 58 RESET I Resets entire chip to default state. Rev. B | Page 11 of 56 AD9786 TERMINOLOGY Linearity Error (Integral Nonlinearity or INL) Settling Time Linearity error is defined as the maximum deviation of the The time required for the output to reach and remain within a actual analog output from the ideal output, determined by a specified error band about its final value, measured from the straight line drawn from zero to full scale. start of the output transition. Differential Nonlinearity (DNL) Glitch Impulse DNL is the measure of the variation in analog value, normal- Asymmetrical switching times in a DAC give rise to undesired ized to full scale, associated with a 1 LSB change in digital output transients that are quantified by a glitch impulse. It is input code. specified as the net area of the glitch in pV-sec. Monotonicity Spurious-Free Dynamic Range (SFDR) A D/A converter is monotonic if the output either increases or The difference between the rms amplitude of the output signal remains constant as the digital input increases. and the amplitude of the peak spurious signal over the specified bandwidth. The units are often in dBc (dB with respect to the Offset Error carrier). The deviation of the output current from the ideal of zero is called offset error. For I , 0 mA output is expected when the Total Harmonic Distortion (THD) OUTA inputs are all 0s. For I , 0 mA output is expected when all THD is the ratio of the rms sum of the first six harmonic OUTB inputs are set to 1. components to the rms value of the measured fundamental. It is expressed as a percentage or in decibels. Gain Error The difference between the actual and ideal output span. The Signal-to-Noise Ratio (SNR) actual span is determined by the output when all inputs are set SNR is the ratio of the rms value of the measured output signal to 1, minus the output when all inputs are set to 0. to the rms sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. Output Compliance Range The value for SNR is expressed in decibels. The range of allowable voltage at the output of a current-output DAC. Operation beyond the maximum compliance limits can Interpolation Filter cause either output stage saturation or breakdown, resulting in If the digital inputs to the DAC are sampled at a multiple rate of nonlinear performance. fDATA (interpolation rate), a digital filter can be constructed that has a sharp transition band near fDATA/2. Images that would typically Temperature Drift appear around fDAC (output data rate) can be greatly suppressed. Temperature drift is specified as the maximum change from the ambient (+25°C) value to the value at either T or T . For Pass Band MIN MAX offset and gain drift, the drift is reported in ppm of full-scale Frequency band in which any input applied therein passes range (FSR) per degree Celsius. For reference drift, the drift is unattenuated to the DAC output. reported in ppm per degree Celsius. Stop-Band Rejection Power Supply Rejection The amount of attenuation of a frequency outside the pass band The maximum change in the full-scale output as the supplies applied to the DAC, relative to a full-scale signal applied at the are varied from minimum to maximum specified voltages. DAC input within the pass band. Rev. B | Page 12 of 56 AD9786 Hilbert Transform Group Delay A function with unity gain over all frequencies, but with a phase Number of input clocks between an impulse applied at the shift of 90° for negative frequencies and a phase shift of –90° for device input and peak DAC output current. A half-band FIR positive frequencies. Although this function cannot be imple- filter has constant group delay over its entire frequency range mented ideally, it can be approximated with a short FIR filter Impulse Response with enough accuracy to be very useful in single sideband radio Response of the device to an impulse applied to the input. architectures. Adjacent Channel Leakage Ratio (ACLR) Complex Image Rejection A ratio in dBc between the measured power within a channel In a traditional two-part upconversion, two images are created relative to its adjacent channel. around the second IF frequency. These images are redundant and have the effect of wasting transmitter power and system Complex Modulation bandwidth. By placing the real part of a second complex modulator The process of passing the real and imaginary components of a in series with the first complex modulator, either the upper or jwt signal through a complex modulator (transfer function = e = lower frequency image near the second IF can be rejected. coswt + jsinwt) and realizing real and imaginary components on the modulator output. Rev. B | Page 13 of 56 AD9786 TYPICAL PERFORMANCE CHARACTERISTICS TMIN to TMAX; AVDD1, AVDD2, DRVDD = 3.3 V; ACVDD, ADVDD, CLKVDD, DVDD = 2.5 V; IOUTFS = 20 mA; differential transformer coupled output; 50 Ω doubly terminated, unless otherwise noted. 120 120 100 100 –6dBFS –6dBFS –3dBFS –3dBFS 80 80 0dBFS 60 60 0dBFS 40 40 20 20 0 0 0 1020 3040 5060 70 80 0 1020 3040 5060 70 80 FREQUENCY (MHz) FREQUENCY (MHz) Figure 3. SFDR vs. Frequency, fDATA = 200 MSPS, 1× Interpolation Figure 6. SFDR vs. Frequency, fDATA = 200 MSPS, 2× Interpolation 120 120 –3dBFS 100 100 –3dBFS –6dBFS –6dBFS 80 80 0dBFS 60 60 0dBFS 40 40 20 20 0 0 0 5 10 15 20 25 30 35 40 45 0 102030 4050 60 FREQUENCY (MHz) FREQUENCY (MHz) Figure 4. SFDR vs. Frequency, fDATA = 100 MSPS, 4× Interpolation Figure 7. SFDR vs. Frequency, fDATA = 125 MSPS, 4× Interpolation 120 120 –6dBFS –6dBFS 100 100 –3dBFS 80 80 0dBFS 0dBFS 60 60 –3dBFS 40 40 20 20 0 0 0 5 10 15 20 25 0 5 10 15 20 25 30 FREQUENCY (MHz) FREQUENCY (MHz) Figure 5. SFDR vs. Frequency, fDATA = 50 MSPS, 8× Interpolation Figure 8. SFDR vs. Frequency, fDATA = 62.5 MSPS, 8× Interpolation Rev. B | Page 14 of 56 SFDR (dBc) SFDR (dBc) SFDR (dBc) 03152-005 03152-004 03152-003 SFDR (dBc) SFDR (dBc) SFDR (dBc) 03152-008 03152-007 03152-006 AD9786 90 90 85 85 80 80 0dBFS –3dBFS –3dBFS 75 75 –6dBFS 70 70 –6dBFS 0dBFS 65 65 60 60 55 55 50 50 0 10 2030 40 50 6070 80 010 20 30 40 ANALOG OUTPUT FREQUENCY (MHz) F (MHz) OUT Figure 12. Out-of-Band SFDR, fDATA = 100 MSPS, 4× Interpolation Figure 9. Out-of-Band SFDR, f = 200 MSPS, 2× Interpolation DATA 100 90 95 0dBFS 85 90 0dBFS 80 85 –6dBFS –6dBFS 80 75 –3dBFS 75 70 70 65 65 –3dBFS 60 60 55 55 50 50 0 20 40 60 80 100 120 140 160 180 200 220 240 260 0 5 10 15 20 25 F (MHz) OUT ANALOG OUTPUT FREQUENCY (MHz) Figure 10. Out-of-Band SFDR, f = 125 MSPS, 4× Interpolation DATA Figure 13. Out-of-Band SFDR, fDATA = 50 MSPS, 8× Interpolation 100 100 –3dBFS 95 95 –3dBFS 90 90 85 85 –6dBFS 80 80 0dBFS –6dBFS 75 75 70 70 0dBFS 65 65 60 60 55 55 50 50 0 20 40 60 80 100 120 140 160 180 200 220 240 260 0 204060 80 F (MHz) F (MHz) OUT OUT Figure 14. Third-Order IMD vs. Frequency, f = 160 MSPS, 1× Interpolation Figure 11. Out-of-Band SFDR, fDATA = 62.5 MSPS, 8× Interpolation DATA Rev. B | Page 15 of 56 IMD (dBc) IMD (dBc) SFDR (dBc) 03152-010 03152-009 03152-011 IMD (dBc) OUT OF BAND SFDR (dBc) OUT OF BAND SFDR (dBc) 03152-014 03152-013 03152-012 AD9786 100 100 95 95 –3dBFS –3dBFS 90 90 –6dBFS –6dBFS 85 85 80 80 75 75 0dBFS 0dBFS 70 70 65 65 60 60 55 55 50 50 0 20 40 60 80 100 120 140 160 020 40 60 80 100 F (MHz) F (MHz) OUT OUT Figure 15. Third-Order IMD vs. Frequency, f = 160 MSPS, 2× Interpolation Figure 18. Third-Order IMD vs. Frequency, f = 200 MSPS,1x Interpolation DATA DATA 100 100 –3dBFS –3dBFS 95 95 90 90 –6dBFS –6dBFS 85 85 80 80 75 75 70 70 0dBFS 0dBFS 65 65 60 60 55 55 50 50 0 20 40 60 80 100 120 140 160 180 200 0 20 40 60 80 100 120 140 160 180 200 F (MHz) F (MHz) OUT OUT Figure 16. Third-Order IMD vs. Frequency, f = 200 MSPS, 2× Interpolation Figure 19. Third-Order IMD vs. Frequency, f = 100 MSPS, 4× Interpolation DATA DATA 100 100 95 95 –3dBFS 0dBFS 90 90 –6dBFS 85 85 –6dBFS 80 80 75 75 70 70 0dBFS 65 65 –3dBFS 60 60 55 55 50 50 0 20 40 60 80 100 120 140 160 180 200 220 240 260 0 20 40 60 80 100 120 140 160 180 200 F (MHz) F (MHz) OUT OUT Figure 17. Third-Order IMD vs. Frequency, fDATA = 125 MSPS, 4× Interpolation Figure 20. Third-Order IMD vs. Frequency, fDATA = 50 MSPS, 8× Interpolation Rev. B | Page 16 of 56 IMD (dBc) IMD (dBc) IMD (dBc) 03152-017 03152-015 03152-016 IMD (dBc) IMD (dBc) IMD (dBc) 03152-019 03152-018 03152-020 AD9786 100 0.3 95 –3dBFS 0.2 90 0.1 85 –6dBFS 80 0 75 –0.1 70 0dBFS 65 –0.2 60 –0.3 55 –0.4 50 0 204060 80 100120 140 160 180 200 220 240 260 0 8192 16384 24576 32768 40960 49152 57344 65536 F (MHz) CODE OUT Figure 21. Third-Order IMD vs. Frequency, f = 62.5 MSPS, 8× Interpolation Figure 24. Typical DNL DATA 1.25 –140 1.00 –145 –150 0.75 F = 78MSPS, 1× INTERPOLATION DATA –155 0.50 –160 0.25 –165 F = 78MSPS, 2× INTERPOLATION DATA 0 –170 –0.25 –175 –0.50 –180 0 8192 16384 24576 32768 40960 49152 57344 65536 0 10 2030 40 50 6070 80 CODE ANALOG OUTPUT FREQUENCY (MHz) Figure 25. Noise Spectral Density vs. Analog Figure 22. Typical INL Input Frequency, f = 78 MSPS DATA –150 –140 –152 –145 –154 –150 –156 F = 156MSPS, 1× INTERPOLATION DATA –155 –158 A = –3DBFS IN –160 –160 A = 0DBFS IN –162 –165 F = 156MSPS, 2× INTERPOLATION DATA –164 –170 –166 A = –6DBFS IN –175 –168 –170 –180 0 1020 3040 506070 80 0 20 40 60 80 100 120 140 160 ANALOG OUTPUT FREQUENCY (MHz) ANALOG OUTPUT FREQUENCY (MHz) Figure 26. Noise Spectral Density vs. Analog Input Frequency, Figure 23. Noise Spectral Density vs. Analog f = 78 MSPS, 2x Interpolation Input Frequency, f = 156 MSPS DATA DATA Rev. B | Page 17 of 56 NOISE SPECTRAL DENSITY (dBm/Hz) INL (LSBs) IMD (dBc) 03152-021 03152-023 03152-022 NOISE SPECTRAL DENSITY (dBm/Hz) NOISE SPECTRAL DENSITY (dBm/Hz) DNL (LSBs) 03152-026 03152-025 03152-024 AD9786 –150 –152 Marker 1 [T1] RBW 10 kHz RF Att 20 dB Ref Lv1 –87.73 dBm VBW 10 kHz –154 10 dBm 9.71442886 MHz SWT 5 s Unit dBm 10 A = –3dBFS A IN –156 0 –10 –158 –20 A = 0dBFS IN –160 –30 1AVG 1MA –40 –162 –50 A = –6dBFS IN –164 –60 –70 –166 –80 1 –168 –90 –100 –170 –110 0 20 40 60 80 100 120 140 160 START 100 kHz 19.9 MHz/ STOP 200 MHz ANALOG OUTPUT FREQUENCY (MHz) Figure 30. Two Tones Around 23 MHz, f = 200 MSPS, Figure 27. Noise Spectral Density vs. Analog Input Frequency, DATA 2× Interpolation, Low-Pass Digital Filter Mode fDATA = 156 MSPS, 2x Interpolation –60 Marker 1 [T1] RBW 10 kHz RF Att 20 dB –65 Ref Lv1 –87.95 dBm VBW 10 kHz 10 dBm 11.71743487 MHz SWT 5 s Unit dBm 10 A 0 –70 –10 –3dBFS 0dBFS –20 –75 –30 1MA 1AVG –40 –80 –50 –6dBFS –60 –70 –85 –80 1 –90 –90 –100 0 25 50 75 100 125 150 –110 F (MHz) START 100 kHz 19.9 MHz/ STOP 200 MHz OUT Figure 28. ACLR for First Adjacent Band vs. Frequency, Figure 31. Two Tones Around 177 MHz, fDATA = 200 MSPS, fDATA = 61.44 MSPS, 4× Interpolation 2× Interpolation, High-Pass Digital Filter Mode REF –29.82dBm *ATTEN 6dB *AVG Log 10dB/ –60 –65 –6dBFS –70 AVERAGE 103 0dBFS –75 –3dBFS PAVG –80 22 W1 S2 CENTER 51.44MHz SPAN 43.84MHz –85 *RES BW 30kHz VBW 300kHz SWEEP 142.2ms (601 pts) LOWER UPPER RMS RESULTS FREQ OFFSET REF BW dBc dBm dBc dBm CARRIER POWER 5.000MHz 3.840MHz 0.15 –17.26 –74.63 –92.05 –90 –17.41dBm/ 10.000MHz 3.840MHz –74.24 –91.65 –75.67 –93.08 0 20 40 60 80 100 120 140 160 180 200 3.84MHz 15.000MHz 3.840MHz –75.73 –93.14 –76.38 –93.79 F (MHz) OUT 20.000MHz 3.840MHz –75.67 –93.08 –75.75 –93.17 Figure 32. ACLR for Two WCDMA Carriers @ 51.44 MHz, Figure 29. ACLR for First Adjacent Band vs. Frequency, f = 61.44 MSPS, 4× Interpolation fDATA = 76.8 MSPS, 4× Interpolation DATA Rev. B | Page 18 of 56 ACLR (dBc) ACLR (dBc) NOISE SPECTRAL DENSITY (dBm/Hz) 03152-027 03152-029 03152-028 03152-031 03152-032 AD9786 REF –33.3dBm *ATTEN 6dB *AVG REF –22.76dBm *ATTEN 8dB Log *AVG 10dB/ AC-COUPLED Log 10dB/ AC-COUPLED AVERAGE 104 AVERAGE 22 PAVG 104 PAVG W1 S2 22 CENTER 46.40MHz SPAN 53.84MHz W1 S2 *RES BW 30kHz VBW 300kHz SWEEP 174.6ms (601 pts) CENTER 20.00MHz SPAN 33.84MHz LOWER UPPER *RES BW 30kHz VBW 300kHz SWEEP 109.8ms (601 pts) RMS RESULTS FREQ OFFSET REF BW dBc dBm dBc dBm LOWER UPPER CARRIER POWER 5.000MHz 3.840MHz 0.22 –20.11 –0.16 –20.48 –20.32dBm/ 10.000MHz 3.840MHz –0.60 –20.92 –72.05 –92.37 RMS RESULTS FREQ OFFSET REF BW dBc dBm dBc dBm 3.84MHz 15.000MHz 3.840MHz –72.68 –93.00 –72.85 –93.18 CARRIER POWER 5.000MHz 3.840MHz –79.00 –89.38 –79.63 –90.01 20.000MHz 3.840MHz –72.74 –93.06 –72.55 –92.88 –10.38dBm/ 10.000MHz 3.840MHz –80.78 –91.16 –81.77 –92.15 25.000MHz 3.840MHz –73.05 –93.37 –72.02 –92.35 3.84 MHz 15.000MHz 3.840MHz –79.71 –90.09 –81.45 –91.83 Figure 35. ACLR for Four WCDMA Carriers Near 50 MHz, Figure 33. ACLR for Single WCDMA Carrier @ 20 MHz, fDATA = 61.44 MSPS, 4× Interpolation fDATA = 61.44 MSPS, 4× Interpolation REF –28.2dBm *ATTEN 6dB *AVG Log 10dB/ AVERAGE 22 PAVG 22 W1 S2 CENTER 142.88MHz SPAN 33.84MHz *RES BW 30kHz VBW 300kHz SWEEP 109.8ms (601 pts) LOWER UPPER RMS RESULTS FREQ OFFSET REF BW dBc dBm dBc dBm CARRIER POWER 5.000MHz 3.840MHz –72.33 –87.64 –72.13 –87.43 –15.30dBm/ 10.000MHz 3.840MHz –72.41 –87.71 –73.02 –88.32 3.84MHz 15.000MHz 3.840MHz –72.67 –87.97 –73.50 –88.88 Figure 34. ACLR for Single WCDMA Carrier @ 142.88 MHz, f = 61.44 MSPS, 4× Interpolation DATA Rev. B | Page 19 of 56 03152-034 03152-033 03152-035 AD9786 SERIAL CONTROL INTERFACE Instruction Byte SDO (PIN 54) SDIO (PIN 55) AD9786 SPI R/W, Bit 7 of the instruction byte, determines whether a read or SCLK (PIN 56) PORT INTERFACE a write data transfer occurs after the instruction byte write. CSB (PIN 57) Logic high indicates a read operation; Logic 0 indicates a write operation. N1 and N0, Bit 6 and Bit 5 of the instruction byte, Figure 36. AD9786 SPI Port Interface determine the number of bytes to be transferred during the data transfer cycle (see Table 10). The AD9786 serial port is a flexible, synchronous serial commu- nications port, allowing easy interface to many industry-standard Table 10. Bytes Transferred During Data Transfer Cycle microcontrollers and microprocessors. The serial I/O is compatible N1 N2 Description with most synchronous transfer formats, including both the 0 0 Transfer 1 byte Motorola SPI® and Intel® SSR protocols. The interface allows 0 1 Transfer 2 bytes read/write access to all registers that configure the AD9786. Single- 1 0 Transfer 3 bytes or multiple-byte transfers are supported, as well as MSB-first or 1 1 Transfer 4 bytes LSB-first transfer formats. The AD9786 serial interface port can be configured as a single pin I/O (SDIO), or as two unidirectional The bit decodes are shown as follows: pins for input/output (SDIO/SDO). MSB LSB I7 I6 I5 I4 I3 I2 I1 I0 GENERAL OPERATION OF THE SERIAL INTERFACE R/W N1 N0 A4 A3 A2 A1 A0 There are two phases to a communication cycle with the AD9786. Phase 1 is the instruction cycle, which is the writing of an A4, A3, A2, A1, and A0 (Bit 4, Bit 3, Bit 2, Bit 1, and Bit 0) of instruction byte into the AD9786, coincident with the first eight the instruction byte determine which register is accessed during SCLK rising edges. The instruction byte provides the AD9786 the data transfer portion of the communication cycle. For multibyte serial port controller with information regarding the data transfer transfers, this address is the starting byte address. The remaining cycle, which is Phase 2 of the communication cycle. The Phase 1 register addresses are generated by the AD9786. instruction byte defines whether the upcoming data transfer is a read or a write, the number of bytes in the data transfer, and the SERIAL INTERFACE PORT PIN DESCRIPTIONS starting register address for the first byte of the data transfer. The SCLK—Serial Clock. The serial clock pin is used to first eight SCLK rising edges of each communication cycle are synchronize data to and from the AD9786 and to run the used to write the instruction byte into the AD9786. internal state machines. The maximum frequency of SCLK A logic high on the CSB pin, followed by a logic low, resets the is 20 MHz. All data input to the AD9786 is registered on the SPI port timing to the initial state of the instruction cycle. This rising edge of SCLK. All data is driven out of the AD9786 is true regardless of the present state of the internal registers or on the falling edge of SCLK. the other signal levels present at the inputs to the SPI port. If the CSB—Chip Select. Active low input starts and gates a communi- SPI port is in the midst of an instruction cycle or a data transfer cation cycle. It allows more than one device to be used on the cycle, none of the present data is written. same serial communication lines. The SDO and SDIO pins go to a high impedance state when this input is high. Chip select The remaining SCLK edges are for Phase 2 of the communication should stay low during the entire communication cycle. cycle. Phase 2 is the actual data transfer between the AD9786 and the system controller. Phase 2 of the communication cycle SDIO—Serial Data I/O. Data is always written into the is a transfer of 1, 2, 3, or 4 data bytes, as determined by the instruc- AD9786 on this pin. However, this pin can be used as a tion byte. Using one multibyte transfer is the preferred method. bidirectional data line. The configuration of this pin is Single-byte data transfers are useful to reduce CPU overhead controlled by Bit 7 of Register Address 0x00. The default is when register access requires one byte only. Registers change Logic 0, which configures the SDIO pin as unidirectional. immediately upon writing to the last bit of each transfer byte. SDO—Serial Data Out. Data is read from this pin for protocols that use separate lines for transmitting and receiving data. In the case where the AD9786 operates in a single bidirectional I/O mode, this pin does not output data and is set to a high impedance state. Rev. B | Page 20 of 56 03152-036 AD9786 INSTRUCTION CYCLE DATA TRANSFER CYCLE MSB/LSB TRANSFERS CSB The AD9786 serial port can support both MSB-first or LSB-first data formats. This functionality is controlled by register address SCLK DATADIR (0x00[6]). The default is MSB first. When this bit is set active high, the AD9786 serial port is in LSB-first format. R/W N1 N0 A4 A3 A2 A1 A0 D7 D6 D5 D3 D2 D1 D0 N N 0 0 0 0 SDIO That is, if the AD9786 is in LSB-first mode, the instruction byte must be written from least significant bit to most significant bit. D7 D6 D5 D3 D2 D1 D0 N N 0 0 0 0 SDO Multibyte data transfers in MSB-first format can be completed Figure 37. Serial Register Interface Timing MSB First by writing an instruction byte that includes the register address of the most significant byte. In MSB-first mode, the serial port internal byte address generator decrements for each byte INSTRUCTION CYCLE DATA TRANSFER CYCLE required of the multibyte communication cycle. Multibyte data CSB transfers in LSB-first format can be completed by writing an instruction byte that includes the register address of the least SCLK significant byte. In LSB-first mode, the serial port internal byte address generator increments for each byte required of the A0 A1 A2 A3 A4 N0 N1 R/W D0 D1 D2 D4 D5 D6 D7 0 0 0 N N N N SDIO multibyte communication cycle. D0 D1 D2 D4 D5 D6 D7 0 0 0 N N N N SDO The AD9786 serial port controller address increments from 0x1F Figure 38. Serial Register Interface Timing LSB First to 0x00 for multibyte I/O operations if the MSB-first mode is active. The serial port controller address decrements from 0x00 to 0x1F for multibyte I/O operations if the LSB-first mode is active. t DS t SCLK NOTES ON SERIAL PORT OPERATION CSB The AD9786 serial port configuration bits reside in Bit 6 and t t PWH PWL Bit 7 of Register Address 0x00. Note that the configuration changes immediately upon writing to the last bit of the register. SCLK t For multibyte transfers, writing to this register might occur DS t DH during the middle of a communication cycle. Care must be INSTRUCTION BIT 7 INSTRUCTION BIT 6 SDIO taken to compensate for this new configuration for the Figure 39. Timing Diagram for Register Write remaining bytes of the current communication cycle. The same considerations apply to setting the software reset CSB SWRST (0x00[5]) bit. All other registers are set to their default values, but the software reset does not affect the bits in Register Address 0x00 and Register Address 0x04. SCLK t DV It is recommended to use only single-byte transfers when SDIO DATA BIT n DATA BIT n–1 changing serial port configurations or initiating a software SDO reset. Figure 40. Timing Diagram for Register Read Rev. B | Page 21 of 56 03152-040 03152-039 03152-038 03152-037 AD9786 MODE CONTROL (VIA SERIAL PORT) Table 11. Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 COMMS 00 SDIODIR DATADIR SWRST SLEEP PDN EXREF FILTER 01 INTERP[1] INTERP[0] ZSTUFF HPFX8 HPFX4 HPFX2 DATA 02 DATAFMT ONEPORT DCLKSTR DCLKPOL DCLKEXT DCLKCRC IQPOL CRAYDIN MODULATE 03 CHANNEL HILBERT MODDUAL SIDEBAND MOD[1] MOD[0] RESERVED 04 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved DCLKCRC 05 DATAADJ[3] DATAADJ[2] DATAADJ[1] DATAADJ[0] MODSYNC MODADJ[2] MODADJ[1] MODADJ[0] 06 Reserved 07 Reserved 08 Reserved 09 Reserved 0A Reserved 0B Reserved 0C Reserved 0D Reserved CALMEMCK 0E CALMEM[1] CALMEN[0] CALCKDIV[2] CALCKDIV[2] CALCKDIV[2] MEMRDWR 0F CALSTAT CALEN XFERSTAT XFEREN SMEMWR SMEMRD FMEMRD UNCAL MEMADDR 10 MEMADDR[7] MEMADDR[6] MEMADDR[5] MEMADDR[4] MEMADDR[3] MEMADDR[2] MEMADDR[1] MEMADDR[0] MEMDATA 11 MEMDATA[5] MEMDATA[4] MEMDATA[3] MEMDATA[2] MEMDATA[1] MEMDATA[0] DCRCSTAT 12 DCRCSTAT[2] DCRCSTAT[1] DCRCSTAT[0] Table 12. COMMS(00) Bit Direction Default Description SDIODIR 7 I 0 0: SDIO pin configured for input only during data transfer 1: SDIO configured for input or output during data transfer DATADIR 6 I 0 0: Serial data uses MSB-first format 1: Serial data uses LSB-first format SWRST 5 I 0 1: Default all serial register bits, except Address 0x00 and Address 0x04 SLEEP 4 I 0 1: DAC output current off PDN 3 I 0 1: All analog and digital circuitry, except serial interface, off EXREF 0 I 0 0: Internal band gap reference 1: External reference Table 13. FILTER(01) Bit Direction Default Description INTERP[1:0] [7:6] I 00 00: No interpolation 01: Interpolation 2× 10: Interpolation 4× 11: Interpolation 8× ZSTUFF 3 I 0 1: Zero stuffing on HPFX8 2 I 0 0: ×8 interpolation filter configured for low-pass 1: ×8 interpolation filter configured for high-pass HPFX4 1 I 0 0: ×4 interpolation filter configured for low-pass 1: ×4 interpolation filter configured for high-pass HPFX2 0 I 0 0: ×2 interpolation filter configured for low-pass 1: ×2 interpolation filter configured for high-pass Rev. B | Page 22 of 56 AD9786 Table 14. DATA(02) Bit Direction Default Description DATAFMT 7 I 0 0: Twos complement data format 1: Unsigned binary input data format ONEPORT 6 I 0 0: I and Q input data onto Port 1 and Port 2, respectively 1: I and Q input data interleaved onto Port 1 DCLKSTR 5 I 0 0: DATACLK pin, 12 mA drive strength 1: DATACLK pin, 24 mA drive strength DCLKPOL 4 I 0 0: Input data latched on DATACLK/DACCLK rising edge (dependent on mode) 1: Input data latched on DATACLK/DACCLK falling edge (dependent on mode) DCLKEXT 3 I 0 0: DATACLK pin inputs channel data rate or modulator synchronizer clock 1: DATACLK pin outputs channel data rate or modulator synchronizer clock DCLKCRC 2 I 0 0: With DATACLK pin as input, DATACLK clock recovery off 1: With DATACLK pin as input, DATACLK clock recovery on IQPOL 1 I 0 0: In one-port mode, IQSEL = 1 latches data into I channel, IQSEL = 0 latches data into Q channel 1: In one-port mode, IQSEL = 0 latches data into I channel, IQSEL = 1 latches data into Q channel GRAYDIN 0 I 0 0: Gray decoder off 1: Gray decoder on Table 15. MODULATE(03) Bit Direction Default Description CHANNEL 7 I 0 MODDUAL CHANNEL 0x03[5] 0x03[7] 0 0 I channel processing routed to DAC 0 1 Q channel processing routed to DAC 1 0 Modulator real output routed to DAC 1 1 Modulator imaginary output routed to DAC HILBERT 6 I 0 1: With MODDUAL on, Hilbert transform on MODDUAL 5 I 0 0: Modulator uses a single channel 1: Modulator uses both I and Q channels SIDEBAND 4 I 0 0: With MODDUAL on, upper sideband rejected 1: With MODDUAL on, lower sideband rejected MOD[1:0] [3:2] I 00 00: No modulation 01: fS/2 modulation 10: f /4 modulation S 11: f /8 modulation S Rev. B | Page 23 of 56 AD9786 Table 16. DCLKCRC(05) Bit Direction Default Description DATAADJ[3:0] [7:4] I 0000 DATACLK offset (twos complement representation) 0111: +7 : 0000: 0 : 1000: −8 MODSYNC 3 I 00 0: Channel data rate clock synchronizer mode 1: State machine clock synchronizer mode MODADJ[2:0] [2:0] I 000 f/8 f/4 f /2 Modulator coefficient offset S S S 000 1 1 1 001 +1/√2 0 –1 010 0 –1 1 011 –1/√2 0 –1 100 –1 +1 +1 101 –1/√2 0 –1 110 0 –1 +1 111 +1/√2 0 –1 Table 17. VERSION(0D) Bit Direction Default Description VERSION[3:0] [3:0] O Hardware version identifier Table 18. CALMEMCK(OE) Bit Direction Default Description CALMEM [5:4] O 00 Calibration memory 00: Uncalibrated 01: Self-calibration 10: Factory calibration 11: User input CALCKDIV[2:0] [2:0] I 00 Calibration clock divide ratio from channel data rate 000: /32 001: /64 : 110: /2048 111: /4096 Table 19. MEMRDWR(OF) Bit Direction Default Description CALSTAT 7 O 0 0: Self-calibration cycle not complete 1: Self-calibration cycle complete CALEN 6 I 0 1: Self-calibration in progress XFERSTAT 5 O 0 0: Factory memory transfer not complete 1: Factory memory transfer complete XFEREN 4 I 0 1: Factory memory transfer in progress SMEMWR 3 I 0 1: Write static memory data from external port SMEMRD 2 I 0 1: Read static memory to external port FMEMRD 1 I 0 1: Read factory memory data to external port UNCAL 0 I 0 1: Use uncalibrated Rev. B | Page 24 of 56 AD9786 Table 20. MEMADDR(10) Bit Direction Default Description MEMADDR [7:0] [7:0] I/O 00000000 Address of factory or static memory to be accessed Table 21. MEMDATA(11) Bit Direction Default Description MEMDATA [5:0] [5:0] I/O 000000 Data or factory or static memory access Table 22. DCRCSTAT(12) Bit Direction Default Description DCRCSTAT (2) 2 O 0 0: With DATACLK CRC on, lock has never been achieved 1: With DATACLK CRC on, lock has been achieved at least once DCRCSTAT(1) 1 O 0 0: With DATACLK CRC on, system is currently not locked 1: With DATACLK CRC on, system is currently locked DCRCSTAT(0) 0 O 0 0: With DATACLK CRC on, system is currently locked 1: With DATACLK CRC on, system lost lock due to jitter Rev. B | Page 25 of 56 AD9786 DIGITAL FILTER SPECIFICATIONS 0 DIGITAL INTERPOLATION FILTER COEFFICIENTS Table 23. Stage 1 Interpolation Filter Coefficients –20 Lower Coefficient Upper Coefficient Integer Value H(1) H(43) 9 –40 H(2) H(42) 0 –60 H(3) H(41) –27 H(4) H(40) 0 –80 H(5) H(39) 65 –100 H(6) H(38) 0 H(7) H(37) –131 –120 H(8) H(36) 0 H(9) H(35) 239 –140 –0.5 –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4 0.5 H(10) H(34) 0 H(11) H(33) –407 Figure 41. 2× Interpolation Filter Response H(12) H(32) 0 H(13) H(31) 665 H(14) H(30) 0 0 H(15) H(29) –1070 H(16) H(28) 0 –20 H(17) H(27) 1764 –40 H(18) H(26) 0 H(19) H(25) –3273 –60 H(20) H(24) 0 H(21) H(23) 10358 –80 H(22) 16384 –100 –120 Table 24. Stage 2 Interpolation Filter Coefficients Lower Coefficient Upper Coefficient Integer Value –140 –0.5 –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4 0.5 H(1) H(19) 19 H(2) H(18) 0 Figure 42. 4× Interpolation Filter Response H(3) H(17) –120 H(4) H(16) 0 H(5) H(15) 436 0 H(6) H(14) 0 H(7) H(13) –1284 –20 H(8) H(12) 0 –40 H(9) H(11) 5045 H(10) 8192 –60 –80 Table 25. Stage 3 Interpolation Filter Coefficients Lower Coefficient Upper Coefficient Integer Value –100 H(1) H(11) 7 –120 H(2) H(10) 0 H(3) H(9) –53 –140 –0.5 –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4 0.5 H(4) H(8) 0 H(5) H(7) 302 Figure 43. 8× Interpolation Filter Response H(6) 512 Rev. B | Page 26 of 56 03152-043 03152-042 03152-041 AD9786 CLOCK/DATA TIMING Table 26. Data Port Synchronization DCLKEXT MODSYNC DCLKCRC 0x02, Bit 3 0x05, Bit 3 0x02, Bit 2 Mode Function 1 0 X DATACLK Master Channel data rate clock output 1 1 X Modulator Master Modulator synchronization DATACLK output 0 0 0 External Sync Mode DATACLK inactive, DACCLK synchronous with external data 0 0 1 DATACLK Slave DATACLK input, data rate clock, data recovery on 0 1 0 Low Setup/Hold DATACLK input, input data synchronous with DATACLK 0 1 1 Modulator Slave Input modulator synchronizer DATACLK input Two-Port Data Input Mode (DATACLK Master) With the interpolation set to 2×, the DACCLK input runs at twice the speed of the DATACLK. Data is latched into the digital With the interpolation set to 1×, the DATACLK output is a inputs of the AD9786 upon every other rising edge of DACCLK, delayed and inverted version of DACCLK at the same frequency. as shown in Figure 47 and Figure 48. With DCLKPOL = 0, as Note that DACCLK refers to the differential clock inputs applied shown in Figure 47, the latching edge of DACCLK is the rising at Pin 5 and Pin 6. As Figure 44 and Figure 45 show, there is a edge that occurs just before the falling edge of DATACLK. With constant delay between the edges of DACCLK and DATACLK. DCLKPOL = 1, as in Figure 48, the latching edge of DACCLK is The DCLKPOL bit (Register 0x02, Bit 4) allows the data to be the rising edge of DACCLK that occurs just before the rising edge latched into the AD9786 upon either the rising or falling edge of DATACLK. The setup and hold time values are identical to of DACCLK. With DCLKPOL = 0, the data is latched in upon those in Figure 44 and Figure 45. the falling edge of DACCLK, as shown in Figure 44. With Note that there is a slight difference in the delay from the rising DCLKPOL = 1, as shown in Figure 45, data is latched in upon edge of DACCLK to the falling edge of DATACLK, and the the rising edge of DACCLK. The setup and hold times are delay from the rising edge of DACCLK to the rising edge of always with respect to the latching edge of DACCLK. DATACLK. As Figure 46 shows, the DATACLK duty cycle is slightly less than 50%. This is true in all modes. DACCLK IN With the interpolation set to 4× or 8×, the DACCLK input runs at 4× or 8× the speed of the DATACLK output. The data is latched in upon a rising edge of DACCLK, similar to the DATACLK OUT 2× interpolation mode. t = 6ns TYP t 12 D t = –0.5ns MIN t = 2.9ns MIN S H However, the latching edge is every fourth edge in 4× inter- DATA polation mode and every eighth edge in the 8× interpolation mode. Similar to operation in the 2× interpolation mode, with DCLKPOL = 0, the latching edge of DACCLK is the rising edge Figure 44. Data Timing, 1× Interpolation, DCLKPOL = 0 that occurs just before the falling edge of DATACLK. With DCLKPOL = 1, the latching edge of DACCLK is the rising DACCLK IN edge that occurs just before the rising edge of DATACLK. The setup and hold time values are identical to those in 1× and 2× interpolation. DATACLK OUT t = 5.5ns TYP D t = –0.5ns MIN t = 2.9ns MIN S H DATA Figure 45. Data Timing, 1× Interpolation, DCLKPOL = 1 Rev. B | Page 27 of 56 03152-044 03152-045 AD9786 Note that DCLKPOL (Register 0x02, Bit 4) can be used to select the edge of DACCLK upon which the input data is latched. There is a defined setup-and-hold window with respect to input data and the latching edge of DACCLK. There is also a required timing relationship between DATACLK and DACCLK. This is referred to in Figure 49 and Figure 50 as tST and tHT (setup and hold for transition). For example, with DCLKPOL set to Logic 0, the input data latches upon the first rising edge of DACCLK that occurs more than 1.5 ns before the falling edge of DATACLK. DACCLK should not be given a rising edge in the window of 500 ps to 1.5 ns before the latching edge (falling edge when Figure 46. DATACLK Duty Cycle DCLKPOL = 0, rising edge when DCLKPOL = 1) of DATACLK. Failure to account for this timing relationship could result in corrupt data. DACCLK IN There are three status bits available for a read that allow the user to verify DLL lock. These are Bit 0, Bit 1, and Bit 2 (DCRCSTAT) in Register 0x12. DATACLK OUT t = 6ns TYP D t = –0.5ns MIN t = 2.9ns MIN S H DACCLK IN DATA DATACLK Figure 47. Data Timing, 2× Interpolation, DCLKPOL = 0 IN t = 1.5ns MIN HT t = –500ps MIN ST DACCLK IN t = 0.0ns MIN t = 3.2ns MIN S H DATA Figure 49. Slave Mode Timing, 2× Interpolation, DCLKPOL = 0 DATACLK OUT t = 5ns TYP D DACCLK IN t = –0.5ns MIN t = 2.9ns MIN S H DATA DATACLK IN Figure 48. Data Timing, 2× Interpolation, DCLKPOL = 1 t = –1.0ns MIN ST t = 2.0ns MIN HT DATACLK Slave Mode (Data Recovery On) t = 0.0ns MIN t = 3.2ns MIN S H DATA DATACLK (Pin 31) can be used as an input to synchronize multiple AD9786s. A clock generated by an AD9786 operating Figure 50. Slave Mode Timing, 2× Interpolation, DCLKPOL = 1 in master mode, or a clock from an external source, can be used to drive DATACLK. In this mode, two clocks are required to be applied to the AD9786. A clock running at the DAC sample rate, referred to as DACCLK, must be applied to the differential inputs (Pin 5 and Pin 6) of the AD9786. As described previously, a clock at the input sample rate must also be applied to Pin 31 (DATACLK). An internal DLL synchronizes the two applied clocks. The timing relationships between the input data, DATACLK, and DACCLK are given in Figure 49 and Figure 50. Rev. B | Page 28 of 56 03152-046 03152-047 03152-048 03152-050 03152-049 AD9786 Low Setup/Hold Mode (DATACLK Input, Data Recovery Off) DACCLK IN Some applications might require that digital input data be synchronized with the DATACLK input, rather than DACCLK. For these applications, the AD9786 can be programmed for low t = –300ps MIN t = 2.9ns MIN S H setup/hold mode by entering the values in Table 26 into the SPI registers. With data recovery off and the MODSYNC bit set to Logic 1, the AD9786 latches data in upon the rising or falling DATA edge of DATACLK input, depending on the state of DCLKPOL. DACCLK IN Figure 53. External Sync Mode with 2× Interpolation Note that when using the AD9786 in external sync mode with 1× interpolation, that functionality is identical to master mode, DATACLK IN except that DATACLK out is not available. That is, with DATACLKPOL = 0, data is latched on the falling edge of DACCLK, t = 0.0ns MIN HT t = 3.0ns MIN ST and with DATACLKPOL = 1, data is latched on the rising edge of DACCLK. t = –1.1ns MIN t = 2.8ns MIN S H DATA DATAADJUST Synchronization When designing the digital interface for high speed DACs, care Figure 51. Low Setup and Hold Mode Timing, 1× Interpolation, DCLKPOL = 0 must be taken to ensure that the DAC input data meets setup and hold requirements. Often, compensation must be used in DACCLK IN the clock delay path to the digital engine driving the DAC. The AD9786 has the on-chip capability to vary the latching edge of DACCLK. With the interpolation function enabled, this allows the user the choice of multiple edges upon which to latch the DATACLK IN data. For instance, if the AD9786 is using 8× interpolation, the t = 2.0ns MIN ST user can latch from one of eight edges before the rising edge of t = 1.0ns MIN HT DATACLK, or seven edges after this rising edge. The specific t = –1.8ns MIN t = 3.1ns MIN S H DATA edge upon which data is latched is controlled by SPI Register 0x05, Bits 7:4. Table 27 shows the relationship of the latching edge of DACCLK and DATACLK with the various settings of Figure 52. Low Setup and Hold Mode Timing, 1× Interpolation, DCLKPOL = 1 the DATAADJ bits. External Sync Mode Table 27. DATAADJ Values for Latching Edge Sync In the external sync mode, the DATACLK is programmed as an SPI Register 0x05 input but is not used. Applying a DATACLK input while in this Latching Edge Write DATACLK Bit 7 Bit 6 Bit 5 Bit 4 mode has no effect. The digital input data is synchronized solely 0 0 0 0 0 to the DACCLK input. With 1× interpolation, the data input is 0 0 0 1 +1 latched upon every rising edge of DACCLK. The challenge is 0 0 1 0 +2 that the user has no way of knowing exactly which edge is the 0 0 1 1 +3 latching edge when the interpolating filters are in use. In 2×, 4×, 0 1 0 0 +4 and 8× interpolation modes, the latching edge of DACCLK is 0 1 0 1 +5 nd th th every 2 , 4 , or 8 edge, respectively. 0 1 1 0 +6 0 1 1 1 +7 With the 2 ns keep-out window, shown in Figure 53, there is a 1 0 0 0 –8 strong possibility of violating setup and hold times, especially at 1 0 0 1 –7 high speeds. It is recommended that users sense the DAC output 1 0 1 0 –6 noise floor for setup and hold violations. If setup and hold is violated, 1 0 1 1 –5 DCLKPOL can be switched. The effect of switching the state of 1 1 0 0 –4 DCLKPOL is that the latching edge is moved by one, two, or four 1 1 0 1 –3 DACCLK cycles if the AD9786 is in 2×, 4×, or 8× interpolation 1 1 1 0 –2 modes, respectively. Note that in this mode, the DATAADJ bits 1 1 1 1 –1 have no effect. Rev. B | Page 29 of 56 03152-052 03152-051 03152-053 AD9786 Note that the data in Figure 44 to Figure 53 was taken with the Figure 55 shows the same conditions, but with DATAADJ set to DATAADJ default of 0000. Changing the DATAADJ values allows 1111. This moves DATACLK to the left in the plot, indicating that the user to select the specific edge of DACCLK upon which the it occurs one DACCLK cycle before it did in Figure 54; therefore, the latching edge of DACCLK also occurs one cycle earlier. input data is latched. This can be done in master mode, but it is most useful in slave mode. For more information on using RISING EDGE OF DATACLK DATAADJ and MODADJ to synchronize multiple AD9786s, CONCURRENT WITH LATCHING EDGE OF DACCLK see Analog Devices Application Note 747. Table 27 lists the values available for 8× interpolation, which, in turn, provides a choice of 16 edges to sync data. With 4× interpolation, there is a choice of eight edges, and the relevant values from Table 27 DACCLK LATCHING EDGE are 0000, 0010, 0100, 0110, 1000, 1010, 1100, and 1110. These options allow latching edge placement from +3 cycles to −4 cycles. In 2× interpolation, four edges are available, and the relevant values from Table 27 are 0000, 0100, 1000, and 1100. The choices for DATAADJ are diminished to +1 cycle to –2 cycles. Figure 54, Figure 55, and Figure 56 show the alignment for the DATA TRANSITION latching edge of DACCLK with 4× interpolation and different settings for DATAADJ. In Figure 54, the AD9786 is in DATACLK master mode. DATAADJ is set to 0000, with Figure 55. DATAADJ = 1111 DCLKPOL set to 0 so that the latching edge of DACCLK is Figure 56 shows the same conditions, with DATAADJ set immediately before the rising edge of DATACLK. The data transitions shown in Figure 54 are synchronous with the to 0001; therefore, DATACLK moves to the right in the plot. DACCLK, so that DACCLK and input data are constant with This indicates that it occurs one DACCLK cycle after it did in respect to each other. Figure 54; therefore, the latching edge of DACCLK also occurs one cycle later. The only visible change when DATAADJ is altered is that RISING EDGE OF DATACLK DATACLK moves, indicating the latching edge has moved as CONCURRENT WITH LATCHING EDGE OF DACCLK well. Note that in DATACLK master mode, when DATAADJ is altered, the latching edge with respect to DATACLK remains the same. RISING EDGE OF DATACLK DACCLK CONCURRENT WITH LATCHING EDGE LATCHING EDGE OF DACCLK DACCLK LATCHING EDGE DATA TRANSITION Figure 56. DATAADJ = 0001 DATA TRANSITION Figure 54. DATAADJ = 0000 Rev. B | Page 30 of 56 03152-054 03152-055 03152-056 AD9786 data images falling in the interpolation filter pass band are passed. Interpolation Modes In band-limited applications, the images at the output |of the Table 28. Interpolation Modes DAC must be limited by an analog reconstruction filter. The INTERP[1] INTERP[0] Mode complexity of the analog reconstruction filter is determined by 0 0 No interpolation the proximity of the closest image to the required signal band. 0 1 ×2 interpolation Higher interpolation rates yield larger stop-band regions, 1 0 ×4 interpolation suppressing more input images and resulting in a much relaxed 1 1 ×8 interpolation analog reconstruction filter. Interpolation is the process of increasing the number of points A DAC shapes its output with a sinc function, having a null at in a time domain waveform by approximating points between the sampling frequency of the DAC. The higher the DAC sam- the input data points on a uniform time grid. This produces pling rate compared to the input signal bandwidth, the less the a higher output data rate. Applied to an interpolation DAC, DAC sinc function shapes the output. The higher the a digital interpolation filter is used to approximate the interpolated interpolation rate, the more input data images fall in the points, having an output data rate increased by the interpolation interpolation filter stop band and are rejected; the bandwidth factor. Interpolation filter responses are achieved by cascading between passed images is larger with higher interpolation individual digital filter banks, whose filter coefficients are given in factors. The sinc function shaping is also reduced with a higher Table 23, Table 24, and Table 25. Filter responses are shown in interpolation factor. Figure 57, which shows the interpolation filters of the AD9786 under different interpolation rates, normalized to the input data Table 29. Sinc Shaping at Band Edge of Interpolation Filters . rate, fSIN Sinc Shaping Mode @ 0.43 fSIN (dB) Bandwidth to First Image The digital filter’s frequency domain response exhibits symmetry No interpolation –2.8241 f SIN about half the output data rate and dc. It causes images of the ×2 interpolation –0.6708 2 f SIN input data to be shaped by the interpolation filter’s frequency ×4 interpolation –0.1657 4 fSIN response. This has the advantage of causing input data images ×8 interpolation –0.0413 8 fSIN that fall in the stop band of the digital filter to be rejected by the stop-band attenuation of the interpolation filter, while input SINC RESPONSE NO INTERPOLATION 0 –50 INTERP[1] = 0 INTERP[0] = 0 –100 –150 –8 –6 –4 –2 –0 2 4 6 8 f SIN ×2 INTERPOLATION 0 –50 INTERP[1] = 0 INTERP[0] = 1 –100 –150 –8 –6 –4 –2 0 2 4 6 8 f SIN ×4 INTERPOLATION 0 –50 INTERP[1] = 1 INTERP[0] = 0 –100 –150 –8 –6 –4 –2 0 2 4 68 f SIN ×8 INTERPOLATION 0 –50 INTERP[1] = 1 INTERP[0] = 1 –100 –150 –8 –6 –4 –2 0 2 4 68 f SIN Figure 57. Interpolation Modes Rev. B | Page 31 of 56 03152-057 AD9786 REAL AND COMPLEX SIGNALS The cosine term—referred to as the real in-phase, or I component, A complex signal contains both magnitude and phase of a complex signal—represents a signal on the real plane with information. Given two signals at the same frequency, if the mirror symmetry about dc. The sine term—referred to as the leading signal in phase is cosinusoidal and the lagging signal is imaginary quadrature, or Q complex signal component— sinusoidal, information pertaining to the magnitude and phase of represents a signal on the imaginary plane with mirror a combination of the two signals can be derived; the combination asymmetry about dc. of the two signals can be considered a complex signal. The cosine The AD9786 has two channels of interpolation filters, allowing and sine can be represented as a series of exponentials, recalling both I and Q components to be shaped by the same filter transfer that a multiplication by j is a counterclockwise rotation about function. The interpolation filter’s frequency response is a real the Re/Im plane. The phasor representation of a complex signal transfer function. Two DACs are required to represent a complex with Frequency f is shown in Figure 58. signal. A single DAC can only synthesize a real signal. When a Im Im DAC synthesizes a real signal, negative frequency components Re fold onto the positive frequency axis. If the input to the DAC is C mirrored symmetrically about dc, the negative frequency A/2 A/2 components fold directly onto the positive frequency compo- 2πft Re A/2 nents in phase-producing, constructive signal summation. If A –f the input to the DAC is not mirrored symmetrically about dc, 0 +f negative frequency components might not be in phase with FREQUENCY A/2 positive frequency components, causing destructive signal 2πft C = Ae = Acos(2πft) + jAsin(2πft) summation. Different applications might benefit from either +j2πft –j2πft e + e A +j2πft –j2πft type of signal summation. Acos(2πft) = A = [e + e ] 2 2 +j2πft –j2πft e + e A +j2πft –j2πft Asin(2πft) = A = [je + e ] 2j 2 Figure 58. Complex Phasor Representation Rev. B | Page 32 of 56 03152-058 AD9786 MODULATION MODES Table 30. Single-Channel Modulation MODDUAL CHANNEL MOD[1] MOD[0] Mode 0 0 0 0 I channel, no modulation 0 0 0 1 I channel, modulation by f /2 DAC 0 0 1 0 I channel, modulation by fDAC/4 0 0 1 1 I channel, modulation by fDAC/8 0 1 0 0 Q channel, no modulation 0 1 0 1 Q channel, modulation by f /2 DAC 0 1 1 0 Q channel, modulation by f /4 DAC 0 1 1 1 Q channel, modulation by fDAC/8 Table 31. Synthesis Bandwidth vs. Interpolation Modes Either channel of the AD9786 interpolation filter channels can Interpolation be routed to the DAC and modulated. In single-channel Modulation None ×2 ×4 ×8 operation, the input data can be modulated by a real sinusoid; None fSIN 2 fSIN 4 fSIN 8 fSIN the input data and the modulating sinusoid contain both fDAC/2 fSIN 2 fSIN 4 fSIN 8 fSIN positive and negative frequency components. A double side- f/4 Overlap Touching 2 f 4 f DAC SIN SIN band output results when modulating two real signals. At the f/8 Overlap Overlap Touching 6 f DAC SIN DAC output, the positive and negative frequency components add in phase, resulting in constructive signal summation. Table 32. Modulated Pass-Band Edges Sinc Shaping As the modulating sinusoidal frequency becomes a larger (Lower/Upper) fraction of the DAC update rate, f the sinc function of the DAC, Interpolation DAC shapes the modulated signal bandwidth more, and the first image moves closer. Modulation None ×2 ×4 ×8 None 0 0 0 0 Because the AD9786 interpolation filter pass band represents a –2.8241 –0.6708 –0.1657 –0.0413 large portion of the input data Nyquist band, it is possible for f /2 –0.0701 –1.1932 –2.3248 –3.0590 DAC modulated signal bands to touch or overlap images if sufficient –22.5378 –9.1824 –6.1190 –4.9337 interpolation is not used under certain modulation and f/4 Overlap Touching –0.2921 –0.5974 DAC interpolation modes. –1.9096 –1.3607 fDAC/8 Overlap Overlap Touching –0.0727 Figure 59 shows the effects of f /8 modulation when using 8× DAC –0.4614 interpolation. Figure 60 to Figure 62 show the effects of real modulation under all interpolation modes. The sinc shaping at the corners of the modulated signal band and the bandwidth to the first image for those cases whose pass bands do not touch or overlap are tabulated. Rev. B | Page 33 of 56 AD9786 FILTERED INTERPOLATION IMAGES f /8 MODULATION S Figure 59. Double Sideband Modulation NO INTERPOLATION 0 INTERP[1] = 0 INTERP[0] = 0 –50 MOD[1] = 0 MOD[0] = 1 –100 –150 –8 –6 –4 –2 0 2 4 68 f SIN ×2 INTERPOLATION 0 INTERP[1] = 0 INTERP[0] = 1 –50 MOD[1] = 0 MOD[0] = 1 –100 –150 –8 –6 –4 –2 0 2468 f SIN ×4 INTERPOLATION 0 INTERP[1] = 1 INTERP[0] = 0 –50 MOD[1] = 0 MOD[0] = 1 –100 –150 –8 –6 –4 –2 0 2468 f SIN ×8 INTERPOLATION 0 INTERP[1] = 1 INTERP[0] = 1 –50 MOD[1] = 0 MOD[0] = 1 –100 –150 –8 –6 –4 –2 0 2468 f SIN Figure 60. Real Modulation by f /2 Under All Interpolation Modes DAC Rev. B | Page 34 of 56 –f –f DAC DAC –7f /8 –7f /8 DAC DAC –3f /4 –3f /4 DAC DAC –5f /8 –5f /8 DAC DAC –f /2 –f /2 DAC DAC –3f /8 –3f /8 DAC DAC –f /4 –f /4 DAC DAC –f –f DAC/8 DAC/8 0 f f DAC/8 DAC/8 f f DAC/4 DAC/4 3f 3f DAC/8 DAC/8 f f DAC/2 DAC/2 5f 5f DAC/8 DAC/8 3f 3f DAC/4 DAC/4 7f 7f DAC/8 DAC/8 f f DAC DAC 03152-059 03152-060 AD9786 NO INTERPOLATION 0 INTERP[1] = 0 INTERP[0] = 0 –50 MOD[1] = 1 –100 MOD[0] = 0 –150 –8 –6 –4 –2 0 2 4 68 f SIN ×2 INTERPOLATION 0 INTERP[1] = 0 INTERP[0] = 1 –50 MOD[1] = 1 –100 MOD[0] = 0 –150 –8 –6 –4 –2 0 2 46 8 f SIN ×4 INTERPOLATION 0 INTERP[1] = 1 INTERP[0] = 0  –50 MOD[1] = 1 –100 MOD[0] = 0 –150 –8 –6 –4 –2 0 2 4 6 8 f SIN ×8 INTERPOLATION 0 INTERP[1] = 1 INTERP[0] = 1 –50 MOD[1] = 1 –100 MOD[0] = 0 –150 –8 –6 –4 –2 0 2 4 6 8 f SIN Figure 61. Real Modulation by fDAC/4 Under All Interpolation Modes NO INTERPOLATION 0 INTERP[1] = 0 INTERP[0] = 0 –50 MOD[1] = 1 –100 MOD[0] = 0 –150 4 6 8 f –8 –6 –4 –2 0 2 SIN ×2 INTERPOLATION 0 INTERP[1] = 0 INTERP[0] = 1 –50 MOD[1] = 1 –100 MOD[0] = 0 –150 –8 –6 –4 –2 0 24 6 8 f SIN ×4 INTERPOLATION 0 INTERP[1] = 1 INTERP[0] = 0 –50 MOD[1] = 1 –100 MOD[0] = 0 –150 24 6 8 –8 –6 –4 –2 0 f SIN ×8 INTERPOLATION 0 INTERP[1] = 1 INTERP[0] = 1 –50 MOD[1] = 1 –100 MOD[0] = 0 –150 –4 –2 02 4 68 8– –6 f SIN Figure 62. Real Modulation by fDAC/8 Under All Interpolation Modes Rev. B | Page 35 of 56 03215-061 03152-062 AD9786 Table 33. Dual-Channel Complex Modulation MODDUAL CHANNEL MOD[1] MOD[0] Mode 0 0 0 0 Real output, no modulation 0 0 0 1 Real output, modulation by fDAC/2 0 0 1 0 Real output, modulation f /4 DAC 0 0 1 1 Real output, modulation f /8 DAC 0 1 0 0 Image output, no modulation 0 1 0 1 Image output, modulation by fDAC/2 0 1 1 0 Image output, modulation by fDAC/4 0 1 1 1 Image output, modulation by fDAC/8 Table 34. Complex Modulated Pass-Band Edges Sinc Shaping In dual-channel mode, the two channels can be modulated by (Lower/Upper) a complex signal, with either the real or imaginary modulation Interpolation result directed to the DAC. Assume initially, as in Figure 63, Modulation None ×2 ×4 ×8 that the complex modulating signal is defined for a positive None 0 0 0 0 frequency only. This causes the output spectrum to be trans- –2.8241 –0.6708 –0.1657 –0.0413 lated in frequency by the modulation factor only. No additional f/2 –0.0701 –1.1932 –2.3248 –3.0590 DAC sidebands are created as a result of the modulation process; –22.5378 –9.1824 –6.1190 –4.9337 therefore, the bandwidth to the first image from the baseband f/4 –0.4680 –0.0175 –0.2921 –0.5974 bandwidth is the same as the output of the interpolation filters. DAC –6.0630 –3.3447 –1.9096 –1.3607 Furthermore, pass bands do not overlap or touch. The sinc shaping at the corners of the modulated signal band is tabulated fDAC/8 –1.3723 –0.1160 –0.0044 –0.0727 in Table 34. Figure 64, Figure 65, and Figure 66 show the effects –4.9592 –1.7195 –0.7866 –0.4614 of complex modulation with varying interpolation rates. FILTERED INTERPOLATION IMAGES f /8 MODULATION NO NEGATIVE S SIDEBAND Figure 63. Complex Modulation Rev. B | Page 36 of 56 –f –f DAC DAC –7f /8 –7f /8 DAC DAC –3f /4 –3f /4 DAC DAC –5f /8 –5f /8 DAC DAC –f /2 –f /2 DAC DAC –3f /8 –3f /8 DAC DAC –f /4 –f /4 DAC DAC –f /8 –f /8 DAC DAC 0 0 f /8 f /8 DAC DAC f /4 f /4 DAC DAC 3f /8 3f /8 DAC DAC f /2 f /2 DAC DAC 5f /8 5f /8 DAC DAC 3f /4 3f /4 DAC DAC 7f /8 7f /8 DAC DAC f f DAC DAC 03152-063 AD9786 ×2INTERPOLATION 0 INTERP[1] = 0 INTERP[0] = 1 –50 MOD[1] = 0 –100 MOD[0] = 1 –150 –8 –6 –4 –2 0 2 4 68 f SIN ×4INTERPOLATION 0 INTERP[1] = 1 INTERP[0] = 0 –50 MOD[1] = 0 –100 MOD[0] = 1 –150 –8 –6 –4 –2 0 2 46 8 f SIN ×8INTERPOLATION 0 INTERP[1] = 1 INTERP[0] = 1 –50 MOD[1] = 0 –100 MOD[0] = 1 –150 –8 –6 –4 –2 0 2 4 6 8 f SIN Figure 64. Complex Modulation by fDAC/2 Under All Interpolation Modes ×2INTERPOLATION 0 INTERP[1] = 0 INTERP[0] = 1 –50 MOD[1] = 1 –100 MOD[0] = 0 –150 –8 –6 –4 –2 0 2 4 68 f SIN ×4INTERPOLATION 0 INTERP[1] = 1 INTERP[0] = 0 –50 MOD[1] = 1 –100 MOD[0] = 0 –150 –8 –6 –4 –2 0 2 4 6 8 f SIN ×8INTERPOLATION 0 INTERP[1] = 1 INTERP[0] = 1 –50 MOD[1] = 1 –100 MOD[0] = 0 –150 –8 –6 –4 –2 0 2 4 6 8 f SIN Figure 65. Complex Modulation by fDAC/4 Under All Interpolation Modes ×2INTERPOLATION 0 INTERP[1] = 0 INTERP[0] = 1 –50 MOD[1] = 1 –100 MOD[0] = 1 –150 –8 –6 –4 –2 0 2 4 68 f SIN ×4INTERPOLATION 0 INTERP[1] = 1 INTERP[0] = 0 –50 MOD[1] = 1 –100 MOD[0] = 1 –150 –8 –6 –4 –2 0 2 4 68 f SIN ×8INTERPOLATION 0 INTERP[1] = 1 INTERP[0] = 1 –50 MOD[1] = 1 –100 MOD[0] = 1 –150 –8 –6 –4 –2 0 2 4 68 f SIN Figure 66. Complex Modulation by f /8 Under All Interpolation Modes DAC Rev. B | Page 37 of 56 03152-065 03152-066 03152-064 AD9786 POWER DISSIPATION 60 The AD9786 has seven power-supply domains: two 3.3 V 8× 4× 2× 50 analog domains (AVDD1 and AVDD2), two 2.5 V analog domains (ADVDD and ACVDD), one 2.5 V clock domain 40 (CLKVDD), and two digital domains (DVDD, which runs from 2.5 V; and DRVDD, which runs from 3.3 V). 30 The current needed for the 3.3 V analog supplies, AVDD1 and 1× 20 AVDD2, is consistent across speed and varying modes of the AD9786. Nominally, the current for AVDD1 is 29 mA across all 10 speeds and modes, whereas the current for AVDD2 is 20 mA. The current for the 2.5 V analog supplies and the digital 0 0 25 50 75 100 125 150 175 200 225 250 supplies varies depending on speed and mode of operation. F (MSPS) DATA Figure 67, Figure 68, and Figure 69 show this variation. Note that CLKVDD, ADVDD, and ACVDD vary with clock speed Figure 68. CLKVDD Supply Current vs. Clock Speed and Interpolation Rates and interpolation rate, but not with modulation rate. 30 425 2× fs/8 400 4× fs/8 8× fs/8 375 4× fs/4 25 350 8× fs/4 325 2× fs/4 8× 2× 4× 300 4× 20 275 8× 2× 250 225 15 200 175 1× 150 10 125 1× 100 75 5 50 25 0 0 0 25 50 75 100 125 150 175 200 225 250 0 25 50 75 100 125 150 175 200 225 250 F (MSPS) F (MSPS) DATA DATA Figure 69. ADVDD and ACVDD Supply Current vs. Clock Speed Figure 67. DVDD Supply Current vs. Clock Speed, and Interpolation Rates Interpolation, and Modulation Rates Rev. B | Page 38 of 56 IDVDD (mA) 03152-067 IADVDD AND IACVDD (mA) ICLKVDD (mA) 03152-069 03152-068 AD9786 FILTERED INTERPOLATION IMAGES f /8 MODULATION S f /4 MODULATION S Figure 70. Complex Modulation with Negative Frequency Aliasing Table 35. Dual Channel Complex Modulation with Hilbert The operation of the Hilbert transform (Figure Z) rotates the Hilbert Mode negative frequency components of Figure Y by +π/2, and the 0 Hilbert transform off positive frequency components of Figure Y by −π/2. The result 1 Hilbert transform on of the Hilbert transform output is then summed with the complex signal in the main signal path. The result is that negative frequen- When complex modulation is performed, the entire spectrum is cies are cancelled and, therefore, do not fold back into the translated by the modulation factor. If the resulting modulated positive side of the frequency spectrum. The Δt block in the main spectrum is not mirrored symmetrically about dc when the signal path offsets the delay inherent in the Hilbert transform DAC synthesizes the modulated signal, negative frequency (nine DAC clock cycle delay). When the DAC synthesizes the components fall on the positive frequency axis and can cause modulated output, there are no negative frequency components to destructive summation of the signals, as shown in Figure 70. For fold onto the positive frequency axis out of phase; consequently, some applications, this can distort the modulated output signal. no distortion is produced as a result of the modulation process. j2π(f + fm)t j2π(f + fm)t –π/2 X = Ae Y = Ae Z = HILBERT(Y) C = X – Z 0 Im Im Im Im ALIASED NEGATIVE FREQUENCY INTERPOLATION IMAGES Re Re Re Re A/2 A/2 A/2 A/2 A/2 A A/2 –50 A/2 00 00 f A/2 f f f A/2 A/2 A/2 A/2 A –100 Figure 71. Negative Frequency Image Rejection In Figure 71, Figure X represents a complex signal typically –150 found in the AD9786 signal path. Figure Y is identical to Figure X, –0.5 –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4 0.5 but it is shifted by π/2. The phase shifting in the AD9786 occurs Figure 72. Negative Frequency Aliasing Distortion because the digital LO driving the digital quadrature modulator in the Hilbert transform path is phase shifted by π/2. Rev. B | Page 39 of 56 –f –f –f DAC DAC DAC –7f /8 –7f /8 –7f /8 DAC DAC DAC –3f /4 –3f /4 –3f /4 DAC DAC DAC –5f /8 –5f /8 –5f /8 DAC DAC DAC –f /2 –f /2 –f /2 DAC DAC DAC –3f /8 –3f /8 –3f /8 DAC DAC DAC –f /4 –f /4 –f /4 DAC DAC DAC –f /8 –f /8 –f /8 DAC DAC DAC 03152-071 0 0 0 f /8 f /8 f /8 DAC DAC DAC dBFS f /4 f /4 f /4 DAC DAC DAC 3f /8 3f /8 DAC DAC 3f /8 DAC f /2 f /2 f /2 DAC DAC DAC 5f /8 5f /8 5f /8 DAC DAC DAC 3f /4 3f /4 3f /4 DAC DAC DAC 7f /8 7f /8 7f /8 DAC DAC DAC f f f DAC DAC DAC 03152-070 03152-072 AD9786 Figure 72 shows this effect at the DAC output for a signal The transfer function of an ideal Hilbert transform has a +90° mirrored asymmetrically about dc that is produced by complex phase shift for negative frequencies, and a –90° phase shift for modulation without a Hilbert transform. The signal bandwidth positive frequencies. Because of the discontinuities that occur at was narrowed to show the aliased negative frequency 0 Hz and at 0.5 × the sample rate, any real implementation of interpolation images. the Hilbert transform trades off bandwidth vs. ripple. In contrast, Figure 73 shows the same waveform with the Figure 74 and Figure 75 show the gain of the Hilbert transform Hilbert transform applied. Clearly, the aliased interpolation vs. frequency. Gain is essentially flat, with a pass-band ripple of images are not present. 0.1 dB over the frequency range of 0.07 × the sample rate to 0.43 × the sample rate. 0 Figure 76 shows the phase response of the Hilbert transform implemented in the AD9786. The phase response for positive frequencies begins at –90° at 0 Hz, followed by a linear phase –50 response (pure time delay) equal to nine filter taps (nine DACCLK cycles). For negative frequencies, the phase response at 0 Hz is +90°, followed by a linear phase delay of nine filter taps. To compensate for the unwanted 9-cycle delay, an equal –100 delay of nine taps is used in the AD9786 digital signal path opposite the Hilbert transform. This delay block is shown as Δt in the Functional Block Diagram (Figure 1). –150 –0.5 –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4 0.5 10 0 Figure 73. Effects of Hilbert Transform –10 If the output of the AD9786 is used with a quadrature modulator, –20 negative frequency images are cancelled without the need for –30 a Hilbert transform. –40 –50 HILBERT TRANSFORM IMPLEMENTATION –60 The Hilbert transform on the AD9786 is implemented as a –70 19-coefficient FIR. The coefficients are given in Table 36. –80 Table 36. –90 Coefficient Integer Value –100 100 200 300 400 500 600 700 800 900 1000 H(1) –6 H(2) 0 H(3) –17 Figure 74. Hilbert Transform Gain H(4) 0 1.0 H(5) –40 H(6) 0 0.8 H(7) –91 0.6 H(8) 0 0.4 H(9) –318 0.2 H(10) 0 0 H(11) +318 H(12) 0 –0.2 H(13) +91 –0.4 H(14) 0 –0.6 H(15) +40 –0.8 H(16) 0 –1.0 H(17) +17 100 200 300 400 500 600 700 800 900 1000 H(18) 0 H(19) +6 Figure 75. Hilbert Transform Ripple Rev. B | Page 40 of 56 dBFS 03152-073 03152-075 03152-074 AD9786 A baseband double sideband signal modulated to IF increases 4 IF filter complexity and reduces power efficiency. If the base- band signal is complex, a single sideband IF modulation can be 3 used, relaxing IF filter complexity and increasing power 2 efficiency. 1 The AD9786 has the ability to place the baseband single side- 0 band complex signal either above or below the IF frequency. Figure 78, Figure 79, and Figure 80 illustrate this. –1 0 –2 –3 –4 100 200 400 600 800 1000 1200 –50 Figure 76. Phase Response of Hilbert Transform –100 Table 37. Dual Channel Complex Modulation Sideband Selection Sideband Mode 0 Upper IF sideband rejected –150 1 Lower IF sideband rejected –0.5 –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4 0.5 Re() I Figure 78. Upper IF Sideband Rejected AD9786 0 LO 90 0 Im() AD9786 Q Figure 77. AD9786 Driving Quadrature Modulator –50 The AD9786 can be configured to drive a quadrature modulator, as in Figure 77. When two AD9786s are used with one AD9786 producing the real output, the second AD9786 produces the –100 imaginary output. By configuring the AD9786 as a complex modulator coupled to a quadrature modulator, IF image rejection is possible. The quadrature modulator acts as the real part of a complex modulation, producing a double sideband –150 –0.5 –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4 0.5 spectrum at the local oscillator (LO) frequency with mirror symmetry about dc. Figure 79. Lower IF Sideband Rejected BASEBAND IF SIDEBAND = 1 SIDEBAND = 0 Figure 80. IF Quadrature Modulation of Real and Complex Baseband Signals Rev. B | Page 41 of 56 –f –f –f IF IF IF 03152-077 0 0 0 03152-076 dBFS dBFS f f IF IF f IF 03152-080 03152-079 03152-078 AD9786 The second master mode, DATACLK master mode, generates a Master/Slave, Modulator/DATACLK Master Modes reference clock that is at the channel data rate. In this mode, the In applications where two or more AD9786s are used to synthe- slave devices align their internal channel data rate clock to the size several digital data paths, it might be necessary to ensure master. If modulator phase alignment is needed, a concurrent that the digital inputs to each device are latched synchronously. serial write to all slave devices is necessary. To achieve this, the In complex data processing applications, digital modulator phase CSB pin on all slaves must be connected together, and a group alignment might be required between two AD9786s. To allow serial write to the MODADJ register bits must be performed. data synchronization and phase alignment, only one AD9786 Following a successful serial write, the modulator coefficient should be configured as a master device, providing a reference alignment is updated upon the next rising edge of the internal clock for another slave-configured AD9786. state machine (see Figure 81). Modulator master mode does not need a concurrent serial write, because slaves lock to the master With synchronization enabled, a reference clock signal is phase automatically. generated on the DATACLK pin of the master. The DATACLK pins on the slave devices act as inputs for the reference clock In a slave device, the local channel data rate clock and the generated by the master. The DATACLK pin on the master and digital modulator clock are created from the internal state all slaves must be directly connected. All master and slave devices machine. The local channel data rate clock is used by the slave must have the same clock source connected to their respective to latch digital input data. At high data rates, the delay inherent CLK+/CLK– pins. in the signal path from master to slave can cause the slave to lag the master when acquiring synchronization. To accommodate When configured as a master, the reference clock generated can for this, an integer number of the DAC update clock cycles can take one of two forms. In modulator master mode, the reference be programmed into the slave device as an offset. The value in clock is a square wave with a period equal to 16 cycles of the DATAADJ allows the local channel data rate clock in the slave DAC update clock. Internal to the AD9786 is a 16-state, finite device to advance by up to eight cycles of the DAC clock, or to state machine, running at the DAC update rate. This state machine be delayed by up to seven cycles (see Figure 82). generates all internal and external synchronization clocks and modulator phasings. The rising edge of the master reference clock The digital modulator coefficients are updated at the DAC clock is time aligned to state zero of the internal state machine. Slave rate and decoded in sequential order from the state machine devices use the master reference clock to synchronize data latching according to Figure 83. The MODADJ bits can be used to align and align modulator phase by aligning state zero of the local a different coefficient to the finite state machine’s zero state, as state machine to the master. shown in Figure 84. DAC CLOCK STATE 01 2345 6789 10 11 12 13 14 15 01 23456 789 10 11 12 13 14 15 MACHINE MODULATOR 10 –1 010 –1 010 –1 010 –1 0 –1 0 10 –1 01 0 –1 0 1 0 –1 01 0 COEFFICIENT MODADJ 000 000 STATE MACHINE CYCLE CLOCK CHANNEL DATA RATE CLOCK Figure 81. Synchronous Serial Modulator Phase Alignment Rev. B | Page 42 of 56 03152-081 AD9786 DATADJ[3:0] 0000 1111 0001 DAC CLOCK RECEIVED CHANNEL DATA RATE CLOCK LOCAL CHANNEL DATA RATE CLOCK –1 +1 Figure 82. Local Channel Data Rate Clock Synchronized with Offset STATE 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 DECODE 1 0 1/ 2 0 0 0 –1/ 2 0 –1 0 –1/ 2 0 0 0 –1/ 2 0 fs/8 0 1234567 fs/4 0 1 2 3 fs/2 0 1 Figure 83. Digital Modulator State Machine Decode MODADJ[2:0] 000 010 101 DAC CLOCK STATE 14 15 0123 15 01 15 01 2 MACHINE MODULATOR –1 0 1 0 –1 0 0 –1 0 1 0 –1 0 COEFFICIENT STATE MACHINE CYCLE CLOCK Figure 84. Local Modulator Coefficient Synchronized with Offset Rev. B | Page 43 of 56 03152-084 03152-083 03152-082 AD9786 OPERATING THE AD9786 REV. F EVALUATION BOARD This section provides information to power up the board and PECL CLOCK DRIVER verify correct operation; a description of more advanced modes The AD9786 system clock is driven from an external source via of operation has been omitted. Connector S1. The AD9786 evaluation board includes an ON Semiconductor® MC100EPT22 PECL clock driver. In the POWER SUPPLIES factory, the evaluation board is set to use this PECL driver as a The AD9786 Rev. F evaluation board has five power supply single-ended-to-differential clock receiver. The PECL driver can connectors, labeled AVDD1, AVDD2, ACVDD/ADVDD, be set to run from 2.5 V from the CLKVDD power connector CLKVDD, and DVDD, whereas the AD9786 has seven power or 3.3 V from the VDD3IN power connector. This setting is supply domains. To reconcile the power supply domains on the done via Jumper JP2, situated next to the CLKVDD power chip with the power supply connectors on the evaluation board, connector, and by setting Input Bias Resistor R23 and Input use Table 38. Bias Resistor R4 on the evaluation board. The factory default is for the PECL driver to be powered from CLKVDD at 2.5 V Additionally, the DRVDD power supply on the AD9786 is used (R23 = 90.9 Ω, R4 = 115 Ω). To operate the PECL driver with to supply power for the digital input bus. DRVDD should be a 3.3 V supply, R23 must be replaced with a 115 Ω resistor; R4 run from 3.3 V. On the evaluation board, DRVDD is jumper- must be replaced with a 90.9 Ω resistor; and the position of JP2 selectable by JP1, which is just to the left of the chip on the must be changed. The schematic of the PECL driver section of evaluation board. With the jumper set to the 3.3 V position, the the evaluation board is shown in Figure 85. A low jitter sine DRVDD chip receives its power from VDD3IN. wave should be used as the clock source. Care must be taken to ensure that the clock amplitude does not exceed the power supply rails for the PECL driver. CLKVDDS CLKVDDS CLK+ R23 R5 115Ω MC100EPT22 50Ω C32 1 0.1μF 7 COND;5 ACLKX U2 CLKVDDS;8 R7 2 50Ω R4 R6 90.9Ω 50Ω CLK– Figure 85. PECL Driver on AD9786 Rev. F Evaluation Board Table 38. Power Supply Domains on AD9786 Rev. F Evaluation Board Nominal Power Evaluation Board Label/PS Domain on Chip Supply Voltage (V) Description DVDD 2.5 SPI port CLKVDD 2.5 Clock circuitry ACVDD/ADVDD 2.5 Analog circuitry containing clock and digital interface circuitry AVDD2 3.3 Switching analog circuitry AVDD1 3.3 Analog output circuitry Rev. B | Page 44 of 56 03152-085 AD9786 DATA INPUTS ANALOG OUTPUT Digital data inputs to the AD9786 are accessed on the evaluation The analog output of the AD9786 is accessed via Connector S3. board through Connector J1 and Connector J2. These are 40-pin, Once all settings are selected and the current levels and SPI port right-angle connectors that are intended to be used with standard functionality are verified, the analog signal at S3 can be viewed. ribbon cable connectors. The input level should be 3.3 V. The For most of the AD9786 applications, a spectrum analyzer is the data format is selectable through Register 0x02, Bit 7 (DATAFMT). preferred instrument to verify proper performance. A typical With this bit set to a default 0, the AD9786 assumes that the input spectral plot is shown in Figure 86, with the AD9786 synthesizing data is in twos complement format. With this bit set to 1, data a two-tone signal in the default mode with a 200 MSPS sample should be input in offset binary format. rate. A single-tone CW signal should provide output power of approximately +0.5 dBm to the spectrum analyzer. When the evaluation board is first powered up and the clock If the spectrum does not look correct at this point, the data and data are running, it is recommended that the proper operating input might be violating setup and hold times with respect to current be verified. Press Reset Switch SW1 to ensure that the the input clock. To correct this, the user should vary the input AD9786 is in default mode. The default mode for the AD9786 is data timing. If this is not possible, SPI Register 0x02, Bit 4 for the interpolation set to 1×. The modulator is turned off in (DCLKPOL), can be inverted. This bit controls the clock edge default mode. The nominal operating currents for the evaluation upon which the data is latched. If neither of these methods corrects board in the power-up default mode are shown in Table 39. the spectrum, it is unlikely that the issue is timing related. In this Table 39. Nominal Operating Currents in Power-Up Default case, verify that all instructions have been followed correctly and Mode that the SPI port readback indicates the correct values. Nominal Current @ Speed (mA) Evaluation Board MARKER 1 [T1] RBW 30kHz RF ATT 20dB 50 100 150 200 REF LVL –84.96dBm VBW 30kHz Power Supply MSPS MSPS MSPS MSPS 0dBm 193.00170300MHz SWT 560ms UNIT dBm 0 DVDD 26 49 74 99 A –10 CLKVDD 78 83 87 92 –20 ACVDD/ADVDD 1 4 6 8 –30 AVDD1 30 30 30 30 –40 1AVG 1MA AVDD2 27 27 27 27 –50 –60 Table 40. SPI Registers –70 Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 0 –80 0x01 INTERP[1] INTERP[0] –90 –100 SERIAL PORT –110 SW1 is a hard reset switch that sets the AD9786 to its default –120 START 100MHz 19.9MHz/ STOP 200MHz state. It should be used every time the AD9786 power supply is cycled, the clock is interrupted, or new data is to be written via Figure 86. Typical Spectral Plot the SPI port. Set the SPI software to read back data from the AD9786, and then verify that the expected values are read back when the software is run. Rev. B | Page 45 of 56 03152-086 AD9786 Figure 87. Power Supply Distribution, Rev. F Evaluation Board Rev. B | Page 46 of 56 ADVDD2_IN TP1 AVD3 SMAEDGE L11 L8 JP30 RED S7 ADVDD AGND2; 3,4,5 FERRITE FERRITE L12 JP33 C45 2.5V + C47 22μF ACVDD 0.1μF FERRITE 16V TP12 C75 C76 CLKVDDS BLK 0.1μF 0.1μF DVDD_IN CLK+ TP13 SMAEDGE L9 JP34 RED R23 S5 DVDD R5 MC100EPT22 DGND; 3,4,5 FERRITE C32 90.9Ω 50Ω JP1 1 VDD 0.1μF C46 2 R7 + C48 7 2.5VN 1 3 CGND; 5 22μF DVDD AVDD2 ACLKX U2 AB 0.1μF CLKVDDS; 8 50Ω 16V TP17 TP18 TP16 2 JP36 R6 R4 BLK BLK BLK 50Ω DVDDS DRVDD 115Ω CLK– ADVDD3_IN TP2 MC100EPT22 SMAEDGE L3 JP9 CLKVDDS RED 3 AVDD2 S9 C28 6 FERRITE + AGND2; 3,4,5 C35 3 U2 4.7μF AVD2 L6 0.1μF C65 JP2 B 6.3V 3.3V + C67 4 2 CLKVDDS 22μF 0.1μF A FERRITE CLKVDDS; 8 16V TP3 + C29 C34 1 CGND; 5 BLK 22μF 0.1μF 16V AVDD_IN TP4 AVD1 SMAEDGE L2 JP10 RED 1 JP7 S10 AVDD FERRITE AGND; 3,4,5 2 C64 JP8 3.3VQ + C68 22μF 0.1μF L14 16V TP5 VAL JP6 BLK L13 VAL CLKVDD_IN L10 TP6 CVD SMAEDGE L1 VAL RED S11 CLKVDD TP30 TP31 TP32 TP33 TP34 TP36 TP35 L7 FERRITE CGND;3,4,5 JP5 BLK BLK BLK BLK BLK VAL BLK BLK C63 2.5VQ + C69 22μF 0.1μF 16V TP7 BLK POWER INPUT FILTERS 03152-087 + AD9786 Figure 88. AD9786 Local Circuitry, Rev. F Evaluation Board Rev. B | Page 47 of 56 R2 R3 AVDD2 10kΩ 10kΩ CLKVDD AVDD C13 CLKVDD 0.1μF C62 C4 C18 C61 + C1 C12 C11 C42 C27 C49 C20 C55 0.1μF 0.1μF 0.001μF 0.001μF 10μF 0.1μF 0.1μF 0.1μF 1pF 0.1μF 0.001μF 0.001μF TP15 JP22 6.3V WHT 1 CLKVDD1 DNC2 80 6 1 2 LPF ADVDDP1 79 ADVDD 5 2 3 CLKVDD2 ACCOMP1 78 R1 4 3 + 50Ω T1 4 CLKCOM1 ACVDDP1 77 C14 C2 T1-1T 0.1μF 10μF R10 5 CLK+ ACOM2P1 76 C19 JP23 6.3V 49.9Ω 0.1μF ACLKX 6 CLK– AVDD2P1 75 R9 S1 7 CLKCOM2 ACOM2P12 74 49.9Ω CLK– CLK+ CGND; 3,4,5 8 DCOM1 AVDD1P2 73 DVDD 9 DVDD1 ACOM1P11 72 31 AD15 10 P1B15MSB IOUTA 71 + C10 C40 C26 P 10μF 0.1μF AD14 11 P1B14 IOUTB 70 0.001μF T3 6.3V 12 P1B13 ACOM1P21 69 AD13 C66 S 10μF 13 P1B12 AVDD1P1 68 AD12 AGND; 3,4,5 ACVDD 6.3V 46 AD11 14 P1B11 ACOM2P2 67 S3 OUT1 AD10 15 P1B10 AVDD2P2 66 C17 DRVDD 0.1μF R42 16 DCOM2 ACCOM2P2 65 DVDD 49.9Ω + 17 DVDD2 ACVDDP2 64 C15 C3 0.1μF 10μF AD09 18 P1B9 ADCOMP2 63 +C31 C33 +C9 C41 6.3V C54 C25 10μF 0.1μF 10μF 0.1μF AD08 19 P1B8 ADVDDP2 62 0.001μF 0.001μF 6.3V 6.3V T2B AD07 20 P1B7 DNC1 61 TP11 TP8 WHT WHT NC = 5 AD06 21 P1B6 FSADJ 60 TP10 4 3 AD05 22 P1B5 REFIO 59 WHT 5 R8 AD04 23 P1B4 RESET 58 RESET + C30 C16 2kΩ 6 S P 1 10V 0.1μF AD03 24 P1B3 SPI_CSB 57 SPCSB 0.01% TTWB-1-B 10μF TP14 25 DCOM3 SP-CLK 56 SPCLK AGND; 3,4,5 DVDD WHT S8 26 DVDD3 SP-SDI 55 SPSDI TP29 AD02 27 P1B2 SP-SDO 54 SPSDO + C8 C39 BLK S2 C24 10μF 0.1μF 28 P1B1 DCOM6 53 AD01 0.001μF 6.3V 29 P1B0LSB DVDD6 52 AD00 DVDD DGND; 3,4,5 30 DRVDD1 P2B0LSB 51 BD00 C38 +C5 DATACLK C21 0.1μF 10μF 31 DCLK-PLLL P2B1 50 BD01 0.001μF 6.3V BD15 32 P2B15MSB-IQSEL P2B2 49 BD02 BD14 3 33 P2B14-OPCLK P2B3 48 BD03 JP28 A 2 BD13 34 P2B13 P2B4 47 BD04 B 1 35 DCOM4 P2B5 46 BD05 OPCLK_3 DVDD JP27 36 DVDD4 DCOM5 45 S6 RESET DRVDD SW1 4 2 BD12 37 P2B12 DVDD5 44 DVDD +C7 C36 C23 3 1 + C37 C6 IQ 10μF 0.1μF BD11 38 P2B11 P2B6 43 BD06 S4 0.001μF 0.1μF 10μF 6.3V FLOAT; 5 C22 BD10 39 P2B10 P2B7 42 BD07 DGND; 3,4,5 6.3V 0.001μF OPCLK BD09 40 P2B9 P2B8 41 BD08 U1 OPCLK AD9786BTSP 03152-088 ADTL1-12 AD9786 R26 R30 100Ω 100Ω AX15 AX08 R31 100Ω R27 AX09 100Ω R32 AX14 JP3 100Ω R28 AX10 100Ω R33 AX13 JP12 100Ω R29 AX11 100Ω AX12 R1 R2 R3 R4 R5 R6 R7 R8 R9 R1 R2 R3 R4 R5 R6 R7 R8 R9 RP5 RP7 DNP DNP DATA-A 1 2 3 45 678 9 10 1 2 3 45 678 9 10 RP1 22 AX15 116 2 1 AD15 RP1 22 AX14 215 4 3 AD14 RP1 22 AX13 314 6 5 AD13 RP1 22 AX12 413 8 7 AD12 RP1 22 AX11 512 10 9 AD11 RP1 22 AX10 611 12 11 AD10 RP1 22 AX09 710 14 13 AD09 RP1 22 AX08 89 16 15 AD08 RP2 22 AX07 116 18 17 AD07 RP2 22 AX06 215 20 19 AD06 RP2 22 AX05 314 22 21 AD05 RP2 22 AX04 413 24 23 AD04 RP2 22 AX03 512 26 25 AD03 RP2 22 AX02 611 28 27 AD02 RP2 22 AX01 710 30 29 AD01 RP2 22 AX00 89 32 31 AD00 34 33 36 35 1 2 3 45 678 9 10 1 2 3 45 678 9 10 38 37 RP6 RP8 DNP DNP 40 39 R1 R2 R3 R4 R5 R6 R7 R8 R9 R1 R2 R3 R4 R5 R6 R7 R8 R9 RIBBON J1 AX00 JP21 R44 AX07 100Ω R38 AX01 100Ω JP19 R43 AX06 100Ω R39 AX02 Ω 100 R41 AX05 100Ω R40 AX03 100Ω R46 AX04 100Ω R34 100Ω Figure 89. Digital Data Port A Input Terminations, Rev. F Evaluation Board Rev. B | Page 48 of 56 RCOM RCOM RCOM RCOM 03152-089 AD9786 R62 R57 100Ω 100Ω BX15 BX08 R58 100Ω R61 BX09 100Ω R59 BX14 JP26 100Ω R60 BX10 100Ω R63 BX13 JP31 100Ω R64 BX11 100Ω BX12 R1 R2 R3 R4 R5 R6 R7 R8 R9 R1 R2 R3 R4 R5 R6 R7 R8 R9 RP12 RP9 DNP DNP DATA-B 1 2 3 45 67 8 9 10 1 2 3 4 567 89 10 RP3 22 BX15 116 2 1 BD15 RP3 22 BX14 215 4 3 BD14 RP3 22 BX13 314 6 5 BD13 RP3 22 BX12 413 8 7 BD12 RP3 22 BX11 512 10 9 BD11 RP3 22 BX10 611 12 11 BD10 RP3 22 BX09 710 14 13 BD09 RP3 22 BX08 89 16 15 BD08 RP4 22 BX07 116 18 17 BD07 RP4 22 BX06 215 20 19 BD06 RP4 22 BX05 314 22 21 BD05 RP4 22 BX04 413 24 23 BD04 RP4 22 BX03 512 26 25 BD03 RP4 22 BX02 611 28 27 BD02 RP4 22 BX01 710 30 29 BD01 RP4 22 BX00 89 32 31 BD00 34 33 SDO 36 35 CLK 1 2 3 45 67 8 9 10 1 2 3 4 567 89 10 38 37 SDI RP11 RP10 DNP DNP 40 39 CSB R1 R2 R3 R4 R5 R6 R7 R8 R9 R1 R2 R3 R4 R5 R6 R7 R8 R9 RIBBON J2 BX00 JP25 R51 BX07 100Ω R55 BX01 100Ω JP24 R49 BX06 100Ω R54 BX02 Ω 100 R47 BX05 100Ω R53 BX03 100Ω R52 BX04 100Ω R56 100Ω Figure 90. Digital Data Port B Input Terminations, Rev. F Evaluation Board Rev. B | Page 49 of 56 RCOM RCOM RCOM RCOM 03152-090 AD9786 DVDDS C52 + C53 4 4.7μF 0.1μF PRE 3 5 6.3V J Q OPCLK_3 OPCLK 1 CLK 2 6 K Q_ CLR 15 74LCX112 DGND;8 U7 DVDDS;16 10 11 PRE 9 J Q 13 CLK 12 7 K Q_ CLR 14 74LCX112 DGND;8 U7 DVDDS;16 SPI PORT P1 R50 1 U5 U5 9kΩ 21 12 13 2 SPCSB 3 74AC14 74AC14 R48 4 U5 U5 9kΩ 4 3 10 11 5 SPCLK 74AC14 74AC14 6 R45 U5 U5 9kΩ 6 5 8 9 SPSDI 74AC14 74AC14 U6 U6 12 13 12 SPSDO 74AC14 74AC14 DVDDS U6 U6 R20 3 4 11 10 R21 10kΩ 10kΩ 74AC14 74AC14++ C43 C50 C44 C51 4.7μF 0.1μF 4.7μF 0.1μF U6 U6 5 6 9 8 6.3V 6.3V 74AC14 74AC14 Figure 91. SPI and One-Port Clock Circuitry, Rev. F Evaluation Board Rev. B | Page 50 of 56 03152-091 AD9786 Figure 92. PCB Assembly, Primary Side, Rev. F Evaluation Board Figure 93. PCB Assembly, Secondary Side, Rev. F Evaluation Board Rev. B | Page 51 of 56 03152-093 03152-092 AD9786 Figure 94. PCB Assembly, Layer 1 Metal, Rev. F Evaluation Board Figure 95. PCB Assembly, Layer 6 Metal, Rev. F Evaluation Board Rev. B | Page 52 of 56 03152-095 03152-094 AD9786 Figure 96. PCB Assembly, Layer 2 Metal (Ground Plane),Rev. F Evaluation Board Figure 97. PCB Assembly, Layer 3 Metal (Power Plane),Rev. F Evaluation Board Rev. B | Page 53 of 56 03152-097 03152-096 AD9786 Figure 98. PCB Assembly, Layer 4 Metal (Power Plane), Rev. F Evaluation Board Figure 99. PCB Assembly, Layer 5 Metal (Ground Plane), Rev. F Evaluation Board Rev. B | Page 54 of 56 03152-099 03152-098 AD9786 OUTLINE DIMENSIONS 14.20 14.00 SQ 12.20 13.80 1.20 12.00 SQ 0.75 MAX 11.80 0.60 0.45 61 80 80 61 1 60 1 60 PIN 1 EXPOSED TOP VIEW 6.00 PAD (PINS DOWN) BSC SQ BOTTOM VIEW 0° MIN 1.05 (PINS UP) 0.20 1.00 0.09 20 41 41 20 0.95 7° 40 40 21 21 3.5° VIEW A 0.15 0.50 BSC 0.27 0° SEATING LEAD PITCH 0.05 0.08 MAX 0.22 PLANE COPLANARITY 0.17 VIEW A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-ADD-HD Figure 100. 80-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] (SV-80-1) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option AD9786BSV −40°C to +85°C 80-Lead TQFP_EP SV-80-1 AD9786BSVRL −40°C to +85°C 80-Lead TQFP_EP SV-80-1 1 AD9786BSVZ −40°C to +85°C 80-Lead TQFP_EP SV-80-1 1 AD9786BSVZRL −40°C to +85°C 80-Lead TQFP_EP SV-80-1 AD9786-EB Evaluation Board 1 Z = Pb-free part. Rev. B | Page 55 of 56 AD9786 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03152-0-10/05(B) Rev. B | Page 56 of 56