ANALOG DEVICES AD977A

16-Bit, 100 kSPS/200 kSPS a BiCMOS A/D Converter AD977/AD977A FEATURES FUNCTIONAL BLOCK DIAGRAM Fast 16-Bit ADC 100 kSPS Throughput Rate—AD977 V REF ANA AGND1 200 kSPS Throughput Rate—AD977A 4k� Single 5 V Supply Operation 2.5V AD977/ CAP REFERENCE Power Dissipation 100 mW Max AD977A 4R R1 IN Power-Down Mode 50 �W SYNC 2R Input Ranges: R2 SERIAL IN BUSY DATA SWITCHED R Unipolar; 0 V–10 V, 0 V–5 V and 0 V–4 V 4R DATACLK R3 INTERFACE IN CAP ADC DATA Bipolar; �10 V, �5 V and �3.3 V R = 5k� AD977 Choice of External or Internal 2.5 V Reference AGND2 R = 2.5k� AD977A High Speed Serial Interface CONTROL LOGIC & V DIG CLOCK On-Chip Clock INTERNAL CALIBRATION CIRCUITRY 20-Lead Skinny DIP or SOIC Package 28-Lead Skinny SSOP Package DGND PWRD R/CCS TAG SB/BTC EXT/INT GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD977/AD977A is a high speed, low power 16-bit A/D 1. Fast Throughput converter that operates from a single 5 V supply. The AD977A The AD977/AD977A is a high speed, 16-bit ADC based on has a throughput rate of 200 kSPS whereas the AD977 has a a factory calibrated switched capacitor architecture. throughput rate of 100 kSPS. Each part contains a successive 2. Single-Supply Operation approximation, switched capacitor ADC, an internal 2.5 V The AD977/AD977A operates from a single 5 V supply and reference, and a high speed serial interface. The ADC is factory dissipates only 100 mW max. calibrated to minimize all linearity errors. The AD977/AD977A is 3. Comprehensive DC and AC Specifications specified for full scale bipolar input ranges of ±10 V, ±5 V and In addition to the traditional specifications of offset, gain ±3.3 V, and unipolar ranges of 0 V to 10 V, 0 V to 5 V and and linearity, the AD977/AD977A is fully tested for SNR 0 V to 4 V. and THD. The AD977/AD977A is comprehensively tested for ac param- eters such as SNR and THD, as well as the more traditional dc parameters of offset, gain and linearity. REV. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: http://www.analog.com otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 2000 AD977/AD977A AD977–SPECIFICATIONS (–40�C to +85�C, F = 100 kHz, V = V = 5 V, unless otherwise noted) S DIG ANA A Grade B Grade C Grade Parameter Min Typ Max Min Typ Max Min Typ Max Unit RESOLUTION 16 16 16 Bits ANALOG INPUT Voltage Range ±10 V, 0 V to 5 V, . . . (See Table II) Impedance See Table II Sampling Capacitance 40 40 40 pF THROUGHPUT SPEED Complete Cycle 10 10 10 µs Throughput Rate 100 100 100 kHz DC ACCURACY 1 Integral Linearity Error ±3 ±2.0 ±3 LSB Differential Linearity Error –2 +3 –1 +1.75 ±2 LSB No Missing Codes 15 16 15 Bits 2 Transition Noise 1.0 1.0 1.0 LSB 3, 4 Full-Scale Error ±0.5 ±0.25 ±0.5 % Full-Scale Error Drift ±7 ±7 ±7 ppm/°C Full-Scale Error Ext. REF = 2.5 V ±0.5 ±0.25 ±0.5 % Full-Scale Error Drift Ext. REF = 2.5 V ±2 ±2 ±2 ppm/°C 3 Bipolar Zero Error Bipolar Ranges ±10 ±10 ±15 mV Bipolar Zero Error Drift Bipolar Ranges ±2 ±2 ±2 ppm/°C 3 Unipolar Zero Error Unipolar Ranges ±10 ±10 ±10 mV Unipolar Zero Error Drift Unipolar Ranges ±2 ±2 ±2 ppm/°C Recovery to Rated Accuracy 5 After Power-Down 2.2 µF to CAP 1 1 1 ms Power Supply Sensitivity V = V = V = 5 V ± 5% ±8 ±8 ±8 LSB ANA DIG D AC ACCURACY 6 7 Spurious Free Dynamic Range 90 96 90 dB 6 Total Harmonic Distortion –90 –96 –90 dB 6 Signal-to-(Noise+Distortion) 83 85 83 dB –60 dB Input 27 28 27 dB 6 Signal-to-Noise 83 85 83 dB 8 Full Power Bandwidth 700 700 700 kHz –3 dB Input Bandwidth 1.5 1.5 1.5 MHz SAMPLING DYNAMICS Aperture Delay 40 40 40 ns Transient Response, Full-Scale Step 2 2 2 µs 9 Overvoltage Recovery 150 150 150 ns REFERENCE Internal Reference Voltage 2.48 2.5 2.52 2.48 2.5 2.52 2.48 2.5 2.52 V Internal Reference Source Current 1 1 1 µA External Reference Voltage Range for Specified Linearity 2.3 2.5 2.7 2.3 2.5 2.7 2.3 2.5 2.7 V External Reference Current Drain Ext. REF = 2.5 V 100 100 100 µA NOTES 1 LSB means Least Significant Bit. With a ±10 V input, one LSB is 305 µV. 2 Typical rms noise at worst case transitions and temperatures. 3 Measured with fixed resistors as shown in Figures 11, 12 and 13. Adjustable to zero. Tested at room temperature. 4 Full-Scale Error is expressed as the % difference between the actual full-scale code transition voltage and the ideal full scale transition voltage, and includes the effect of offset error. For bipolar input ranges, the Full-Scale Error is the worst case of either the –Full Scale or +Full Scale code transition voltage errors. For unipolar input ranges, Full-Scale Error is with respect to the +Full-Scale code transition voltage. 5 External 2.5 V reference connected to REF. 6 f = 20 kHz, 0.5 dB down unless otherwise noted. IN 7 All specifications in dB are referred to a full scale ±10 V input. 8 Full-Power Bandwidth is defined as full-scale input frequency at which Signal-to-(Noise+Distortion) degrades to 60 dB, or 10 bits of accuracy. 9 Recovers to specified performance after a 2 × F input overvoltage. S Specifications subject to change without notice. –2– REV. D AD977/AD977A AD977A–SPECIFICATIONS (–40�C to +85�C, F = 200 kHz, V = V = 5 V, unless otherwise noted) S DIG ANA A Grade B Grade C Grade Parameter Min Typ Max Min Typ Max Min Typ Max Unit RESOLUTION 16 16 16 Bits ANALOG INPUT Voltage Range ±10 V, 0 V to 5 V, . . . (See Table II) Impedance See Table II Sampling Capacitance 40 40 40 pF THROUGHPUT SPEED Complete Cycle 5 5 5 µs Throughput Rate 200 200 200 kHz DC ACCURACY 1 Integral Linearity Error ±3 ±2.0 ±3 LSB Differential Linearity Error –2 +3 –1 +1.75 ±2LSB No Missing Codes 15 16 15 Bits 2 Transition Noise 1.0 1.0 1.0 LSB 3, 4 Full-Scale Error ±0.5 ±0.25 ±0.5 % Full-Scale Error Drift ±7 ±7 ±7 ppm/°C Full-Scale Error Ext. REF = 2.5 V ±0.5 ±0.25 ±0.5 % Full-Scale Error Drift Ext. REF = 2.5 V ±2 ±2 ±2 ppm/°C 3 Bipolar Zero Error Bipolar Ranges ±10 ±10 ±15 mV Bipolar Zero Error Drift Bipolar Ranges ±2 ±2 ±2 ppm/°C 3 Unipolar Zero Error Unipolar Ranges ±10 ±10 ±10 mV Unipolar Zero Error Drift Unipolar Ranges ±2 ±2 ±2 ppm/°C Recovery to Rated Accuracy 5 After Power-Down 2.2 µF to CAP 1 1 1 ms Power Supply Sensitivity V = V = V = 5 V ± 5% ±8 ±8 ±8LSB ANA DIG D AC ACCURACY 6 7 Spurious Free Dynamic Range 90 96 90 dB 6 Total Harmonic Distortion –90 –96 –90 dB 6 Signal-to-(Noise+Distortion) 83 85 83 dB –60 dB Input 27 28 27 dB 6 Signal-to-Noise 83 85 83 dB 8 Full Power Bandwidth 1 1 1 MHz –3 dB Input Bandwidth 2.7 2.7 2.7 MHz SAMPLING DYNAMICS Aperture Delay 40 40 40 ns Transient Response, Full-Scale Step 1 1 1 µs 9 Overvoltage Recovery 150 150 150 ns REFERENCE Internal Reference Voltage 2.48 2.5 2.52 2.48 2.5 2.52 2.48 2.5 2.52 V Internal Reference Source Current 1 1 1 µA External Reference Voltage Range for Specified Linearity 2.3 2.5 2.7 2.3 2.5 2.7 2.3 2.5 2.7 V External Reference Current Drain Ext. REF = 2.5 V 1.2 1.2 1.2 mA NOTES 1 LSB means Least Significant Bit. With a ±10 V input, one LSB is 305 µV. 2 Typical rms noise at worst case transitions and temperatures. 3 Measured with fixed resistors as shown in Figures 11, 12 and 13. Adjustable to zero. Tested at room temperature. 4 Full-Scale Error is expressed as the % difference between the actual full-scale code transition voltage and the ideal full scale transition voltage, and includes the effect of offset error. For bipolar input ranges, the Full-Scale Error is the worst case of either the –Full Scale or +Full Scale code transition voltage errors. For unipolar input ranges, Full-Scale Error is with respect to the +Full-Scale code transition voltage. 5 External 2.5 V reference connected to REF. 6 f = 20 kHz, 0.5 dB down unless otherwise noted. IN 7 All specifications in dB are referred to a full scale ±10 V input. 8 Full-Power Bandwidth is defined as full-scale input frequency at which Signal-to-(Noise+Distortion) degrades to 60 dB, or 10 bits of accuracy. 9 Recovers to specified performance after a 2 × F input overvoltage. S Specifications subject to change without notice. REV. D –3– AD977/AD977A–SPECIFICATIONS (Both Specs) A, B, C Grades Parameter Conditions Min Typ Max Unit DIGITAL INPUTS Logic Levels V –0.3 +0.8 V IL V 2.0 V + 0.3 V IH DIG I ±10 µA IL I ±10 µA IH DIGITAL OUTPUTS Data Format Serial 16-Bits Data Coding Binary Two’s Complement or Straight Binary Pipeline Delay Conversion Results Only Available after Completed Conversion V I = 1.6 mA 0.4 V OL SINK V I = 500 µA4 V OH SOURCE POWER SUPPLIES Specified Performance V 4.75 5 5.25 V DIG V 4.75 5 5.25 V ANA I 4mA DIG I 11 mA ANA Power Dissipation PWRD LOW 100 mW PWRD HIGH 50 µW TEMPERATURE RANGE Specified Performance T to T –40 +85 °C MIN MAX Specifications subject to change without notice. (AD977A: F = 200 kHz, AD977: F = 100 kHz, V = V = 5 V, –40�C to +85�C) TIMING SPECIFICATIONS S S DIG ANA AD977A AD977 Symbol Min Typ Max Min Typ Max Unit Convert Pulsewidth t 50 50 ns 1 R/C, CS to BUSY Delay t 83 83 ns 2 BUSY LOW Time t 4.0 8.0 µs 3 BUSY Delay after End of Conversion t 50 50 ns 4 Aperture Delay t 40 40 ns 5 Conversion Time t 3.8 4.0 7.6 8.0 µs 6 Acquisition Time t 1.0 2.0 µs 7 Throughput Time t + t 510 µs 6 7 R/C Low to DATACLK Delay t 220 350 ns 8 DATACLK Period t 220 450 ns 9 DATA Valid Setup Time t 50 100 ns 10 DATA Valid Hold Time t 20 20 ns 11 EXT. DATACLK Period t 66 100 ns 12 EXT. DATACLK HIGH t 20 20 ns 13 EXT. DATACLK LOW t 30 30 ns 14 R/C, CS to EXT. DATACLK Setup Time t 20 t + 5 20 t + 5 ns 15 12 12 R/C to CS Setup Time t 10 10 ns 16 EXT. DATACLK to SYNC Delay t 15 66 15 66 ns 17 EXT. DATACLK to DATA Valid Delay t 25 66 25 66 ns 18 CS to EXT. DATACLK Rising Edge Delay t 10 10 ns 19 Previous DATA Valid after CS, R/C Low t 3.5 7.5 µs 20 BUSY to EXT. DATACLK Setup Time t 55 ns 21 Final EXT. DATACLK to BUSY Rising Edge t 1.7 3.5 µs 22 TAG Valid Setup Time t 00 ns 23 TAG Valid Hold Time t 20 20 ns 24 Specifications subject to change without notice. –4– REV. D AD977/AD977A 1 PIN CONFIGURATIONS ABSOLUTE MAXIMUM RATINGS Analog Inputs SOIC and DIP SSOP R1 , R2 , R3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 V IN IN IN CAP . . . . . . . . . . . . . . . . .+V + 0.3 V to AGND2 – 0.3 V ANA 1 20 1 28 R1 V R1 V IN DIG IN DIG REF . . . . . . . . . . . . . . . . . . . . . Indefinite Short to AGND2, AGND1 2 27 V 2 19 AGND1 V ANA ANA . . . . . . . . . . . . . . . . . . . . . . . . . Momentary Short to V ANA R2 3 26 PWRD 3 18 IN R2 PWRD IN Ground Voltage Differences R3 4 25 BUSY IN R3 4 17 BUSY DGND, AGND1, AGND2 . . . . . . . . . . . . . . . . . . . ±0.3 V IN AD977 NC 5 24 CS CAP 5 AD977A 16 CS Supply Voltages CAP 6 23 NC TOP VIEW AD977 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V REF 6 15 ANA R/C (Not to Scale) REF 7 AD977A NC 22 V to V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±7 V DIG ANA AGND2 7 14 TAG TOP VIEW NC 8 21 R/C (Not to Scale) V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V DIG SB/BTC 8 13 DATA AGND2 9 20 NC Digital Inputs . . . . . . . . . . . . . . . . . . . –0.3 V to V + 0.3 V DIG EXT/INT 9 12 DATACLK NC 10 19 TAG 2 Internal Power Dissipation DGND 10 11 SYNC NC 11 18 NC PDIP (N), SOIC (R), SSOP (RS) . . . . . . . . . . . . . 700 mW SB/BTC 12 17 DATA Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C 13 16 DATACLK EXT/INT Storage Temperature Range N, R . . . . . . . . –65°C to +150°C DGND 14 15 SYNC Lead Temperature Range NC = NO CONNECT (Soldering 10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause perma- 1.6mA I OL nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating TO OUTPUT 1.4V conditions for extended periods may affect device reliability. PIN C 2 L Specification is for device in free air: 100pF 20-Lead PDIP: θ = 100°C/W, θ = 31°C/W, JA JC 20-Lead SOIC: θ = 75°C/W, θ = 24°C/W, JA JC 500�AI OH 28-Lead SSOP: θ = 109°C/W, θ = 39°C/W. JA JC Figure 1. Load Circuit for Digital Interface Timing ORDERING GUIDE Temperature Throughput Package Model Range Rate Max INL Min S/(N+D) Options* AD977AN –40°C to +85°C 100 kSPS ±3.0 LSB 83 dB N-20 AD977BN –40°C to +85°C 100 kSPS ±2.0 LSB 85 dB N-20 AD977CN –40°C to +85°C 100 kSPS 83 dB N-20 AD977AAN –40°C to +85°C 200 kSPS ±3.0 LSB 83 dB N-20 AD977ABN –40°C to +85°C 200 kSPS ±2.0 LSB 85 dB N-20 AD977ACN –40°C to +85°C 200 kSPS 83 dB N-20 AD977AR –40°C to +85°C 100 kSPS ±3.0 LSB 83 dB R-20 AD977BR –40°C to +85°C 100 kSPS ±2.0 LSB 85 dB R-20 AD977CR –40°C to +85°C 100 kSPS 83 dB R-20 AD977AAR –40°C to +85°C 200 kSPS ±3.0 LSB 83 dB R-20 AD977ABR –40°C to +85°C 200 kSPS ±2.0 LSB 85 dB R-20 AD977ACR –40°C to +85°C 200 kSPS 83 dB R-20 AD977ARS –40°C to +85°C 100 kSPS ±3.0 LSB 83 dB RS-28 AD977BRS –40°C to +85°C 100 kSPS ±2.0 LSB 85 dB RS-28 AD977CRS –40°C to +85°C 100 kSPS 83 dB RS-28 AD977AARS –40°C to +85°C 200 kSPS ±3.0 LSB 83 dB RS-28 AD977ABRS –40°C to +85°C 200 kSPS ±2.0 LSB 85 dB RS-28 AD977ACRS –40°C to +85°C 200 kSPS 83 dB RS-28 *N = 20-lead 300 mil plastic DIP; R = 20-lead SOIC; RS = 28-lead SSOP. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD977/AD977A feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD ESD SENSITIVE DEVICE precautions are recommended to avoid performance degradation or loss of functionality. REV. D –5– AD977/AD977A PIN FUNCTION DESCRIPTIONS Pin No. Pin No. DIP/SOIC SSOP Mnemonic Description 1, 3, 4 1, 3, 4 R1 , R2 , R3 Analog Input. Refer to Table I, Table II for input range configuration. IN IN IN 2 2 AGND1 Analog Ground. Used as the ground reference point for the REF pin. 5 6 CAP Reference buffer output. Connect a 2.2 µF tantalum capacitor between CAP and Analog Ground. 6 7 REF Reference Input/Output. The internal 2.5 V reference is available at this pin. Alternatively an external reference can be used to override the internal reference. In either case, connect a 2.2 µF tantalum capacitor between REF and Analog Ground. 7 9 AGND2 Analog Ground. 8 12 SB/BTC This digital input is used to select the data format of a conversion result. With SB/BTC tied LOW, conversion data will be output in Binary Two’s Complement format. With SB/BTC connected to a logic HIGH, data is output in Straight Binary format. 9 13 EXT/INT Digital select input for choosing the internal or an external data clock. With EXT/INT tied LOW, after initiating a conversion, 16 DATACLK pulses transmit the previous conversion result as shown in Figure 3. With EXT/INT set to a logic HIGH, output data is synchronized to an external clock signal connected to the DATACLK input. Data is output as indicated in Figure 4 through Figure 9. 10 14 DGND Digital Ground. 11 15 SYNC Digital output frame synchronization for use with an external data clock (EXT/INT = Logic HIGH). When a read sequence is initiated, a pulse one DATACLK period wide is output synchronous to the external data clock. 12 16 DATACLK Serial data clock input or output, dependent upon the logic state of the EXT/INT pin. When using the internal data clock (EXT/INT = Logic LOW), a conversion start sequence will initiate transmission of 16 DATACLK periods. Output data is synchronous to this clock and is valid on both its rising and falling edges (Figure 3). When using an external data clock (EXT/INT = Logic HIGH), the CS and R/C signals control how conversion data is accessed. 13 17 DATA The serial data output is synchronized to DATACLK. Conversion results are stored in an on-chip register. The AD977 provides the conversion result, MSB first, from its internal shift register. The DATA format is determined by the logic level of SB/BTC. When using the internal data clock (EXT/INT = Logic LOW), DATA is valid on both the rising and falling edges of DATACLK. Between conversions DATA will remain at the level of the TAG input when the conversion was started. Using an external data clock (EXT/INT = Logic HIGH) allows previous conversion data to be accessed during a conversion (Figures 5, 7 and 9) or the conversion result can be accessed after the completion of a conversion (Figures 4, 6 and 8). 14 19 TAG This digital input can be used with an external data clock, (EXT/INT = Logic HIGH) to daisy chain the conversion results from two or more AD977s onto a single DATA line. The digital data level on TAG is output on DATA with a delay of 16 or 17 external DATACLK periods after the initiation of the read sequence. Dependent on whether a SYNC is not present or present. 15 21 R/C Read/Convert Input. Is used to control the conversion and read modes of the AD977. With CS LOW; a falling edge on R/C holds the analog input signal inter- nally and starts a conversion, a rising edge enables the transmission of the conver- sion result. 16 24 CS Chip Select Input. With R/C LOW, a falling edge on CS will initiate a conversion. With R/C HIGH, a falling edge on CS will enable the serial data output sequence. 17 25 BUSY Busy Output. Goes LOW when a conversion is started, and remains LOW until the conversion is completed and the data is latched into the on-chip shift register. 18 26 PWRD Power-Down Input. When set to a logic HIGH power consumption is reduced and conversions are inhibited. The conversion result from the previous conversion is stored in the onboard shift register. 19 27 V Analog Power Supply. Nominally 5 V. ANA 20 28 V Digital Power Supply. Nominally 5 V. DIG –6– REV. D AD977/AD977A SPURIOUS FREE DYNAMIC RANGE DEFINITION OF SPECIFICATIONS The difference, in decibels (dB), between the rms amplitude of INTEGRAL NONLINEARITY ERROR (INL) the input signal and the peak spurious signal. Linearity error refers to the deviation of each individual code from a line drawn from “negative full scale” through “positive TOTAL HARMONIC DISTORTION (THD) full scale.” The point used as “negative full scale” occurs 1/2 LSB THD is the ratio of the rms sum of the first six harmonic com- before the first code transition. “Positive full scale” is defined as ponents to the rms value of a full-scale input signal and is a level 1 1/2 LSB beyond the last code transition. The deviation expressed in decibels. is measured from the middle of each particular code to the true straight line. SIGNAL TO (NOISE AND DISTORTION) (S/[N+D]) RATIO S/(N+D) is the ratio of the rms value of the measured input DIFFERENTIAL NONLINEARITY ERROR (DNL) signal to the rms sum of all other spectral components below the In an ideal ADC, code transitions are 1 LSB apart. Differential Nyquist frequency, including harmonics but excluding dc. The nonlinearity is the maximum deviation from this ideal value. It value for S/(N+D) is expressed in decibels. is often specified in terms of resolution for which no missing codes are guaranteed. FULL POWER BANDWIDTH The full power bandwidth is defined as the full-scale input fre- FULL-SCALE ERROR quency at which the S/(N+D) degrades to 60 dB, 10 bits of The last + transition (from 011 . . . 10 to 011 . . . 11 for two’s accuracy. complement format) should occur for an analog voltage 1 1/2 LSB below the nominal full scale (9.9995422 V for a ±10 V range). APERTURE DELAY The full-scale error is the deviation of the actual level of the last Aperture delay is a measure of the acquisition performance, and transition from the ideal level. is measured from the falling edge of the R/C input to when the input signal is held for a conversion. BIPOLAR ZERO ERROR Bipolar zero error is the difference between the ideal midscale TRANSIENT RESPONSE input voltage (0 V) and the actual voltage producing the The time required for the AD977/AD977A to achieve its rated midscale output code. accuracy after a full-scale step function is applied to its input. UNIPOLAR ZERO ERROR OVERVOLTAGE RECOVERY In unipolar mode, the first transition should occur at a level The time required for the ADC to recover to full accuracy after 1/2 LSB above analog ground. Unipolar zero error is the devia- an analog input signal 150% of full-scale is reduced to 50% of tion of the actual transition from that point. the full-scale value. REV. D –7– AD977/AD977A CONVERSION CONTROL INTERNAL DATA CLOCK MODE The AD977/AD977A is controlled by two signals: R/C and CS. The AD977/AD977A is configured to generate and provide the When R/C is brought low, with CS low, for a minimum of 50 ns, data clock when the EXT/INT pin is held low. Typically CS will the input signal will be held on the internal capacitor array and be tied low and R/C will be used to initiate a conversion “n.” a conversion “n” will begin. Once the conversion process does During the conversion the AD977/AD977A will output 16 bits of begin, the BUSY signal will go low until the conversion is com- data, MSB first, from conversion “n-1” on the DATA pin. This plete. Internally, the signals R/C and CS are OR’d together and data will be synchronized with 16 clock pulses provided on the there is no requirement on which signal is taken low first when DATACLK pin. The output data will be valid on both the initiating a conversion. The only requirement is that there be at rising and falling edge of the data clock as shown in Figure 3. least 10 ns of delay between the two signals being taken low. After the LSB has been presented, the DATA pin will assume After the conversion is complete the BUSY signal will return whatever state the TAG input was at during the start of con- high and the AD977/AD977A will again resume tracking the version, and the DATACLK pin will stay low until another input signal. Under certain conditions the CS pin can be tied conversion is initiated. Low and R/C will be used to determine whether you are initiat- ing a conversion or reading data. On the first conversion, after EXTERNAL DATA CLOCK MODE the AD977/AD977A is powered up, the DATA output will be The AD977/AD977A is configured to accept an externally sup- indeterminate. plied data clock when the EXT/INT pin is held high. This mode of operation provides several methods by which conversion Conversion results can be clocked serially out of the AD977/ results can be read from the AD977/AD977A. The output data AD977A using either an internal clock, generated by the from conversion “n-1” can be read during conversion “n,” or the AD977/AD977A, or by using an external clock. The AD977/ output data from conversion “n” can be read after the conver- AD977A is configured for the internal data clock mode by pull- sion is complete. The external clock can be either a continuous ing the EXT/INT pin low. It is configured for the external clock or discontinuous clock. A discontinuous clock can be either mode by pulling the EXT/INT pin high. t 1 CS, R/C t 3 BUSY t 2 t 4 t 5 MODE ACQUIRE CONVERT ACQUIRE CONVERT t t 6 7 Figure 2. Basic Conversion Timing t 8 R/C t 9 t 1 DATACLK 12 3 15 16 t t 10 11 BIT 14 BIT 13 BIT 1 DATA MSB VALID LSB VALID VALID VALID VALID t 2 t 6 BUSY Figure 3. Serial Data Timing for Reading Previous Conversion Results with Internal Clock (CS, EXT/INT and TAG Set to Logic Low) –8– REV. D AD977/AD977A normally low or normally high when inactive. In the case of the EXTERNAL DISCONTINUOUS CLOCK DATA READ discontinuous clock, the AD977/AD977A can be configured to AFTER CONVERSION NO SYNC OUTPUT GENERATED either generate or not generate a SYNC output (with a continu- Figure 4 illustrates the method by which data from conversion ous clock a SYNC output will always be produced). “n” can be read after the conversion is complete using a discon- tinuous external clock without the generation of a SYNC Each of the methods will be described in the following sections output. After a conversion is complete, indicated by BUSY and are illustrated in Figures 4 through 9. It should be noted returning high, the result of that conversion can be read while that all timing diagrams assume that the receiving device is CS is Low and R/C is high. In this mode CS can be tied low. latching data on the rising edge of the external clock. If the The MSB will be valid on the first falling edge and the second falling edge of DATACLK is used then, in the case of a discon- rising edge of DATACLK. The LSB will be valid on the 16th tinuous clock, one less clock pulse is required than shown in falling edge and the 17th rising edge of DATACLK. A mini- Figures 4 through 7 to latch in a 16-bit word. Note that data is mum of 16 clock pulses are required for DATACLK if the valid on the falling edge of a clock pulse (for t greater than t ) 13 18 receiving device will be latching data on the falling edge of and the rising edge of the next clock pulse. DATACLK. A minimum of 17 clock pulses are required for The AD977 provides error correction circuitry that can correct DATACLK if the receiving device will be latching data on the for an improper bit decision made during the first half of the rising edge of DATACLK. Approximately 40 ns after the 17th conversion cycle. Normally the occurrence of an incorrect bit rising edge of DATACLK (if provided) the DATA output pin decision during a conversion cycle is irreversible. This error will reflect the state of the TAG input pin during the first rising occurs as a result of noise during the time of the decision or due edge of DATACLK. to insufficient settling time. As the AD977/AD977A is perform- The advantage of this method of reading data is that it is not ing a conversion it is important that transitions not occur on being clocked out during a conversion and therefore conversion digital input/output pins or degradation of the conversion result performance is not degraded. could occur. This is particularly important during the second half of the conversion process. For this reason it is recommended When reading data after the conversion is complete, with the that when an external clock is being provided it be a discontinu- highest frequency permitted for DATACLK (15.15 MHz), and ous clock that is not toggling during the time that BUSY is low with the AD977A, the maximum possible throughput is approxi- or, more importantly, that it does not transition during the latter mately 195 kHz and not the rated 200 kHz. half of BUSY low. For details on use of the TAG input with this mode see the Use of the Tag Feature section. t 12 t t 13 14 EXT 0 12 3 14 15 16 DATACLK t 1 R/C t 2 BUSY t 21 SYNC t t 18 18 BIT 15 BIT 0 DATA BIT 14 BIT 13 BIT 1 TAG 0 TAG 1 (MSB) (LSB) t t 23 24 TAG 0 TAG 1 TAG 2 TAG 3 TAG 15 TAG 16 TAG 17 TAG 18 TAG Figure 4. Conversion and Read Timing Using an External Discontinuous Data Clock (EXT/INT Set to Logic High, CS Set to Logic Low) REV. D –9– AD977/AD977A EXTERNAL DISCONTINUOUS CLOCK DATA READ EXTERNAL DISCONTINUOUS CLOCK DATA READ DURING CONVERSION NO SYNC OUTPUT AFTER CONVERSION WITH SYNC OUTPUT GENERATED GENERATED Figure 6 illustrates the method by which data from conversion Figure 5 illustrates the method by which data from conversion “n” can be read after the conversion is complete using a discon- “n-1” can be read during conversion “n” while using a discon- tinuous external clock, with the generation of a SYNC output. tinuous external clock, without the generation of a SYNC out- What permits the generation of a SYNC output is a transition of put. After a conversion is initiated, indicated by BUSY going DATACLK while either CS is high or while both CS and R/C low, the result of the previous conversion can be read while CS are low. After a conversion is complete, indicated by BUSY is low and R/C is high. In this mode CS can be tied low. The returning high, the result of that conversion can be read while MSB will be valid on the 1st falling edge and the 2nd rising CS is Low and R/C is high. In this mode CS can be tied low. In edge of DATACLK. The LSB will be valid on the 16th falling Figure 6 clock pulse #0 is used to enable the generation of a edge and the 17th rising edge of DATACLK. A minimum of 16 SYNC pulse. The SYNC pulse is actually clocked out approxi- clock pulses are required for DATACLK if the receiving device mately 40 ns after the rising edge of clock pulse #1. The SYNC will be latching data on the falling edge of DATACLK. A mini- pulse will be valid on the falling edge of clock pulse #1 and the mum of 17 clock pulses are required for DATACLK if the rising edge of clock pulse #2. The MSB will be valid on the receiving device will be latching data on the rising edge of falling edge of clock pulse #2 and the rising edge of clock pulse DATACLK. Approximately 40 ns after the 17th rising edge of #3. The LSB will be valid on the falling edge of clock pulse #17 DATACLK (if provided) the DATA output pin will reflect the and the rising edge of clock pulse #18. Approximately 40 ns state of the TAG input pin during the first rising edge of after the rising edge of clock pulse #18 the DATA output pin DATACLK. will reflect the state of the TAG input pin during the rising edge of clock pulse #2. The advantage of this method of reading data For both the AD977 and the AD977A the data should be is that it is not being clocked out during a conversion and there- clocked out during the first half of BUSY so not to degrade fore conversion performance is not degraded. conversion performance. For the AD977 this requires use of a 4.8 MHz DATACLK or greater with data being read out as When reading data after the conversion is complete, with the soon as the conversion process begins. For the AD977A it highest frequency permitted for DATACLK (15.15 MHz), requires use of a 10 MHz DATACLK or greater. and with the AD977A, the maximum possible throughput is approximately 195 kHz and not the rated 200 kHz. It is not recommended that data be shifted through the TAG input in this mode as it will certainly result in clocking of data For details on use of the TAG input with this mode see the Use during the second half of the conversion. of the TAG Input section. t 12 t t 13 14 EXT 01 12516 DATACLK t t 22 15 R/C t 1 t 20 BUSY t t 2 21 SYNC t t 18 18 BIT 15 BIT 0 DATA BIT 14 (MSB) (LSB) Figure 5. Conversion and Read Timing for Reading Previous Conversion Results During A Conversion Using External Discontinuous Data Clock (EXT/INT Set to Logic High, CS Set to Logic Low) –10– REV. D AD977/AD977A t 12 t t 13 14 EXT 0 12 3 4 17 18 DATACLK t t t 15 15 15 R/C t 2 BUSY t 17 SYNC t 12 t t 18 18 BIT 15 BIT 0 DATA BIT 14 TAG 0 TAG 1 TAG 2 (MSB) (LSB) t 23 t 24 TAG 0 TAG 1 TAG 2 TAG 16 TAG 17 TAG 18 TAG 19 TAG Figure 6. Conversion and Read Timing Using An External Discontinuous Data Clock (EXT/INT Set to Logic High, CS Set to Logic Low) EXTERNAL DISCONTINUOUS CLOCK DATA READ began. Figure 7 shows R/C then going high and after a delay of DURING CONVERSION WITH SYNC OUTPUT greater than 15 ns (t ) clock pulse #1 can be taken high to 15 GENERATED request the SYNC output. The SYNC output will appear Figure 7 illustrates the method by which data from conversion approximately 40 ns after this rising edge and will be valid on “n-1” can be read during conversion “n” while using a discon- the falling edge of clock pulse #1 and the rising edge of clock tinuous external clock, with the generation of a SYNC output. pulse #2. The MSB will be valid approximately 40 ns after the What permits the generation of a SYNC output is a transition of rising edge of clock pulse #2 and can be latched off either the DATACLK while either CS is High or while both CS and R/C falling edge of clock pulse #2 or the rising edge of clock pulse are low. In Figure 7 a conversion is initiated by taking R/C low #3. The LSB will be valid on the falling edge of clock pulse #17 with CS tied low. While this condition exists a transition of and the rising edge of clock pulse #18. Approximately 40 ns DATACLK, clock pulse #0, will enable the generation of a after the rising edge of clock pulse #18, the DATA output SYNC pulse. Less then 83 ns after R/C is taken low the BUSY pin will reflect the state of the TAG input pin during the output will go low to indicate that the conversion process has rising edge of clock pulse #2. t 12 t t 13 14 EXT 0 12318 DATACLK t t t 15 15 22 R/C t 1 t 20 BUSY t 2 t 17 SYNC t 12 t t 18 18 BIT 0 BIT 15 BIT 14 TAG 0 DATA (LSB) (MSB) Figure 7. Conversion and Read Timing for Reading Previous Conversion Results During a Conversion Using External Discontinuous Data Clock (EXT/INT Set to Logic High, CS Set to Logic Low) REV. D –11– AD977/AD977A For both the AD977 and the AD977A the data should be After a conversion is complete, indicated by BUSY returning clocked out during the first half of BUSY so not to degrade high, the result of that conversion can be read while CS is low conversion performance. For the AD977 this requires use of a and R/C is high. In Figure 8 clock pulse #0 is used to enable the 4.8 MHz DATACLK or greater, with data being read out as generation of a SYNC pulse. The SYNC pulse is actually clocked soon as the conversion process begins. For the AD977A it out approximately 40 ns after the rising edge of clock pulse #1. requires use of a 10 MHz DATACLK or greater. The SYNC pulse will be valid on the falling edge of clock pulse #1 and the rising edge of clock pulse #2. The MSB will be valid It is not recommended that data be shifted through the TAG on the falling edge of clock pulse #2 and the rising edge of clock input in this mode as it will certainly result in clocking of data pulse #3. The LSB will be valid on the falling edge of clock during the second half of the conversion. pulse #17 and the rising edge of clock pulse #18. Approximately 50 ns after the rising edge of clock pulse #18 the DATA output EXTERNAL CONTINUOUS CLOCK DATA READ AFTER pin will reflect the state of the TAG input pin during the rising CONVERSION WITH SYNC OUTPUT GENERATED edge of clock pulse #2. Figure 8 illustrates the method by which data from conversion “n” can be read after the conversion is complete using a con- When reading data after the conversion is complete, with the tinuous external clock, with the generation of a SYNC output. highest frequency permitted for DATACLK (15.15 MHz) and, What permits the generation of a SYNC output is a transition of with the AD977A, the maximum possible throughput is approxi- DATACLK while either CS is high or while both CS and R/C are mately 195 kHz and not the rated 200 kHz. low. For details on use of the TAG input with this mode see the Use With a continuous clock the CS pin cannot be tied low as it of the TAG Input section. could be with a discontinuous clock. Use of a continuous clock, while a conversion is occurring, can increase the DNL and Transition Noise of the AD977/AD977A. t 12 t t 13 14 EXT 0 1 2 3 4 17 18 DATACLK t t 1 t 19 15 CS t 16 R/C t t 16 2 BUSY t 17 SYNC t 12 t t 18 18 BIT 0 BIT 15 DATA BIT 14 TAG 0 TAG 1 TAG 2 (LSB) (MSB) t 23 t 24 TAG TAG 16 TAG 17 TAG 18 TAG 19 TAG 0 TAG 1 TAG 2 Figure 8. Conversion and Read Timing Using an External Continuous Data Clock (EXT/INT Set to Logic High) –12– REV. D AD977/AD977A EXTERNAL CONTINUOUS CLOCK DATA READ DURING 15 ns (t ), clock pulse #1 can be taken high to request the 15 CONVERSION WITH SYNC OUTPUT GENERATED SYNC output. The SYNC output will appear approximately Figure 9 illustrates the method by which data from conversion 50 ns after this rising edge and will be valid on the falling edge “n-1” can be read during conversion “n” while using a continu- of clock pulse #1 and the rising edge of clock pulse #2. The ous external clock with the generation of a SYNC output. What MSB will be valid approximately 40 ns after the rising edge of permits the generation of a SYNC output is a transition of clock pulse #2 and can be latched off either the falling edge of DATACLK while either CS is high or while both CS and R/C clock pulse #2 or the rising edge of clock pulse #3. The LSB are low. will be valid on the falling edge of clock pulse #17 and the rising edge of clock pulse #18. Approximately 40 ns after the rising With a continuous clock the CS pin cannot be tied low as it edge of clock pulse #18, the DATA output pin will reflect the could be with a discontinuous clock. Use of a continuous clock state of the TAG input pin during the rising edge of clock while a conversion is occurring can increase the DNL and pulse #2. Transition Noise of the AD977/AD977A. For both the AD977 and the AD977A the data should be In Figure 9 a conversion is initiated by taking R/C low with CS clocked out during the 1st half of BUSY so as not to degrade held low. While this condition exists a transition of DATACLK, conversion performance. For the AD977 this requires use of a clock pulse #0, will enable the generation of a SYNC pulse. 4.8 MHz DATACLK or greater with data being read out as Less then 83 ns after R/C is taken low the BUSY output will go soon as the conversion process begins. For the AD977A it low to indicate that the conversion process has began. Figure 9 requires use of a 10 MHz DATACLK or greater. shows R/C then going high and after a delay of greater than t 12 t t 13 14 EXT 03 1 2 DATACLK 18 t 19 CS t t 15 16 R/C t 1 t 20 BUSY t 2 t 17 SYNC t 12 t t 18 18 BIT 15 BIT 0 DATA TAG 0 TAG 1 TAG 2 (MSB) (LSB) t t 23 24 TAG TAG 0 TAG 1 TAG 16 TAG 17 TAG 18 TAG 19 Figure 9. Conversion and Read Timing for Reading Previous Conversion Results During a Conversion Using An External Continuous Data Clock (EXT/INT Set to Logic High) REV. D –13– AD977/AD977A Table I. AD977A Analog Input Configuration Input Voltage Connect R1 Connect R2 Connect R3 Input IN IN IN Range via 200 � to via 100 � to to Impedance ±10 V V AGND 2.5 V 11.5 kΩ IN ±5 V AGND V 2.5 V 6.7 kΩ IN ±3.3 V V V 2.5 V 5.4 kΩ IN IN 0 V to 10 V AGND V AGND 6.7 kΩ IN 0 V to 5 V AGND AGND V 5.0 kΩ IN 0 V to 4 V V AGND V 5.4 kΩ IN IN Table II. AD977 Analog Input Configuration Input Voltage Connect R1 Connect R2 Connect R3 Input IN IN IN Range via 200 � to via 100 � to to Impedance ±10 V V AGND CAP 22.9 kΩ IN ±5 V AGND V CAP 13.3 kΩ IN ±3.3 V V V CAP 10.7 kΩ IN IN 0 V to 10 V AGND V AGND 13.3 kΩ IN 0 V to 5 V AGND AGND V 10.0 kΩ IN 0 V to 4 V V AGND V 10.7 kΩ IN IN ANALOG INPUTS that a single 5 V supply can be used to bias the hardware trim The AD977/AD977A is specified to operate with six full-scale circuitry. With the hardware adjust circuits shown in Figures 12 analog input ranges. Connections required for each of the three and 13, offset and full-scale error can be trimmed to zero. Refer analog inputs, R1 , R2 and R3 , and the resulting full-scale IN IN IN to the Offset and Gain Adjust section. ranges, are shown in Table I and Table II. The nominal input If larger offset and full-scale errors are permitted, or if soft- impedance for each analog input range is also shown. Table III ware calibration is used, the external resistors can be omit- shows the output codes for the ideal input voltages of each of the ted. Table IV shows the resultant input ranges and offset and six analog input ranges. full-scale errors. The analog input section has a ±25 V overvoltage protection on Using the AD977A with Bipolar Input Ranges R1 and R2 . Since the AD977/AD977A has two analog IN IN The connection diagrams in Figure 11 show a buffer amplifier grounds it is important to ensure that the analog input is refer- required for bipolar operation of the AD977A when using the enced to the AGND1 pin, the low current ground. This will internal reference. The buffer amplifier is required to isolate the minimize any problems associated with a resistive ground drop. CAP pin from the signal dependent current in the R3 pin. A IN It is also important to ensure that the analog input of the high speed op amp such as the AD8031 can be used with a AD977/AD977A is driven by a low impedance source. With its single 5 V power supply without degrading the performance of primarily resistive analog input circuitry, the ADC can be driven the AD977A. The buffer must have good settling characteristics by a wide selection of general purpose amplifiers. and provide low total noise within the input bandwidth of the To best match the low distortion requirements of the AD977/ AD977A. AD977A, care should be taken in the selection of the drive cir- AGND1 REF cuitry op amp. Figure 10 shows the simplified analog input section for the 4k 2.5V CAP REFERENCE AD977/AD977A. Since the AD977/AD977A can operate with 20k /10k an internal or external reference, and several different analog R1 SWITCHED IN input ranges, the full-scale analog input range is best represented CAP ADC 10k /5k R2 IN with a voltage that spans 0 V to V across the 40 pF sampling REF 5k /2.5k 40pF 20k /10k capacitor. The onboard resistors are laser trimmed to ratio R3 IN match for adjustment of offset and full-scale error using fixed AGND2 AD977/AD977A external resistors. The configurations shown in Figures 12 and 13 are required to obtain the data sheet specifications for offset and full-scale error. Figure 10. AD977/AD977A Simplified Analog Input The external fixed resistors are used during factory calibration so –14– REV. D AD977/AD977A Table III. Output Codes and Ideal Input Voltages Digital Output Two’s Complement Straight Binary Description Analog Input (SB/BTC LOW) (SB/BTC HIGH) Full-Scale Range ±10 V ±5 V ±3.33 V 0 V to 10 V 0 V to 5 V 0 V to 4 V Least Significant Bit 305 µV 153 µV 102 µV 153 µV 76 µV 61 µV +Full Scale (FS–1 LSB) 9.999695 V 4.999847 V 3.333231 V 9.999847 V 4.999924 V 3.999939 V 0111 1111 1111 1111 1111 1111 1111 1111 Midscale 0 V 0 V 0 V 5 V 2.5 V 2 V 0000 0000 0000 0000 1000 0000 0000 0000 One LSB Below Midscale –305 µV –153 µV –102 µV 4.999847 V 2.499924 V 1.999939 V 1111 1111 1111 1111 0111 1111 1111 1111 –Full Scale –10 V –5 V –3.333333 V 0 V 0 V 0 V 1000 0000 0000 0000 0000 0000 0000 0000 Table IV. Input Ranges, Offset and Full-Scale Errors Without External Resistors AD977 Offset Error Full-Scale Error AD977A Offset Error Full-Scale Error Input Range A/B/C Grade A/B/C Grade Input Range A/B/C Grade A/B/C Grade –9.890 V to 9.90 V ±25 mV/±25 mV ±0.75%/±0.50% –9.800 V to 9.970 V ±40 mV/±40 mV ±0.80%/±0.55% –4.943 V to 4.995 V ±25 mV/±25 mV ±0.75%/±0.50% –4.900 V to 4.985 V ±40 mV/±40 mV ±0.80%/±0.55% –3.295 V to 3.330 V ±25 mV/±25 mV ±0.75%/±0.50% –3.267 V to 3.323 V ±40 mV/±40 mV ±0.80%/±0.55% 0.008 V to 9.946 V ±10 mV/±10 mV ±0.75%/±0.50% 0.007 V to 9.893 V ±10 mV/±10 mV ±0.75%/±0.50% 0.004 V to 5.023 V ±10 mV/±10 mV ±0.75%/±0.50% 0.004 V to 5.039 V ±10 mV/±10 mV ±0.75%/±0.50% 0.003 V to 4.010 V ±10 mV/±10 mV ±0.75%/±0.50% 0.003 V to 4.016 V ±10 mV/±10 mV ±0.75%/±0.50% 200 200 200 V R1 R1 V R1 IN IN IN IN IN AGND1 AGND1 AGND1 100 100 100 V R2 R2 IN IN IN R2 IN R3 IN 33.2k 33.2k 33.2k R3 R3 IN IN AD8031 AD8031 CAP CAP CAP AD8031 2.2 F 2.2 F 2.2 F AD977A AD977A AD977A REF REF REF 2.2 F 2.2 F 2.2 F AGND2 AGND2 AGND2 a. b. c. Figure 11. AD977A Bipolar Input Configuration Using the Internal Reference; (a) V = ±10 V, (b) V = ±5 V, (c) V = ±3.33 V IN IN IN REV. D –15– AD977/AD977A BIPOLAR CONNECTION FOR AD977 INPUT STANDARD CONNECTION WITHOUT STANDARD CONNECTION WITH OFFSET AND GAIN ADJUST RANGE OFFSET AND GAIN ADJUST 200� 200� V R1 V R1 IN IN IN IN AGND1 AGND1 100� 100� R2 R2 IN IN 5V R3 IN 33.2k� R3 IN 33.2k� �10V CAP 50k� CAP 2.2�F 5V 2.2�F AD977 AD977 576k� 50k� REF REF 2.2�F 2.2�F AGND2 AGND2 200� 200� R1 R1 IN IN 5V AGND1 AGND1 33.2k� 50k� 100� V R2 IN IN 100� V R2 33.2k� IN IN R3 IN �5V R3 IN CAP CAP 2.2�F 5V 2.2�F AD977 AD977 576k� REF REF 50k� 2.2�F 2.2�F AGND2 AGND2 200� 200� V V R1 R1 IN IN IN IN AGND1 AGND1 100� 100� 5V R2 R2 IN IN 33.2k� R3 50k� IN 33.2k� R3 IN CAP �3.33V CAP 2.2�F 5V 2.2�F AD977 AD977 576k� REF 50k� REF 2.2�F 2.2�F AGND2 AGND2 Figure 12. AD977 Bipolar Analog Input Configuration –16– REV. D AD977/AD977A UNIPOLAR CONNECTION FOR AD977A AND AD977 INPUT STANDARD CONNECTION WITHOUT STANDARD CONNECTION WITH RANGE OFFSET AND GAIN ADJUST OFFSET AND GAIN ADJUST 200� 200� R1 R1 IN IN AGND1 AGND1 100� 100� V R2 V R2 IN IN IN IN 5V R3 IN R3 33.2k� IN 2.2�F 33.2k� 0V–10V CAP 50k� CAP AD977/ 5V 2.2�F AD977/ AD977A AD977A 576k� REF 50k� REF 2.2�F 2.2�F AGND2 AGND2 200� 200� R1 R1 IN IN 5V AGND1 AGND1 33.2k� 100� 100� 50k� R2 IN 33.2k� R2 IN V R3 IN IN V R3 IN 0V–5V IN CAP CAP 2.2�F 5V AD977/ AD977/ + AD977A AD977A 576k� 2.2�F – REF REF 50k� 2.2�F 2.2�F AGND2 AGND2 200� 200� V R1 V R1 IN IN IN IN AGND1 AGND1 100� 100� R2 IN R2 IN R3 IN R3 IN 5V CAP 33.2k� 33.2k� 0V–4V 2.2�F 50k� CAP AD977/ 5V 2.2�F AD977/ AD977A 576k� AD977A REF 50k� REF 2.2�F 2.2�F AGND2 AGND2 Figure 13. AD977/AD977A Unipolar Analog Input Configuration REV. D –17– AD977/AD977A VOLTAGE REFERENCE input dependent loads that will lead to increased distortion. The AD977/AD977A has an on-chip temperature compensated Any dc loads will simply act as a gain error. Although the typi- bandgap voltage reference that is factory trimmed to 2.5 V cal characteristic of Figure 15 shows that the AD977/AD977A ±20 mV. The accuracy of the AD977/AD977A over the speci- is capable of driving loads greater than 15 mA, it is recom- fied temperature ranges is dominated by the drift performance mended that the steady state current not exceed 2 mA. of the voltage reference. The on-chip voltage reference is laser- Using an External Reference trimmed to provide a typical drift of 7 ppm/°C. This typical drift In addition to the on-chip reference, an external 2.5 V refer- characteristic is shown in Figure 14, which is a plot of the ence can be applied. When choosing an external reference for a change in reference voltage (in mV) versus the change in tem- 16-bit application, however, careful attention should be paid to perature—notice the plot is normalized for zero error at 25°C. noise and temperature drift. These critical specifications can If improved drift performance is required, an external reference have a significant effect on the ADC performance. such as the AD780 should be used to provide a drift as low as 3 ppm/°C. In order to simplify the drive requirements of the Figures 16a and 16b show the AD977/AD977A used in bipolar voltage reference (internal or external), an onboard reference mode with the AD780 voltage reference applied to the REF buffer is provided. The output of this buffer is provided at the pin. It is important to note that in Figure 16a the R3 pin is IN CAP pin and is available to the user; however, when externally connected to the CAP pin whereas in Figure 16b the R3 pin IN loading the reference buffer, it is important to make sure that of the AD977A is returned to the output of the external refer- proper precautions are taken to minimize any degradation in the ence. The AD780 is a bandgap reference that exhibits ultralow ADC’s performance. Figure 15 shows the load regulation of the drift, low initial error and low output noise. In Figure 16b, reference buffer. Notice that this figure is also normalized so the value for C1 is only applicable to applications using the that there is zero error with no dc load. In the linear region, the AD780. In applications using a different external reference a output impedance at this point is typically 1 Ω. Because of this different value for C1 may be required. For low power applica- 1 Ω output impedance, it is important to minimize any ac or tions, the REF192 provides a low quiescent current, high accuracy and low temperature drift solution. 200� V R1 IN IN 100� R2 IN 33.2k� R3 IN 0.1�F 3 V 6 TEMP REF OUT C1 AD780 2.2�F 2 4 5V V GND AGND1 IN C3 C4 1�F AD977 0.1�F V ANA CAP C2 –55 25 125 2.2�F AGND2 DEGREES CELSIUS Figure 16a. AD780 External Reference to AD977 Config- Figure 14. Reference Drift ured for ±10 V Input Range 200� V R1 IN IN 100� R2 IN 33.2k� R3 IN 0.1�F 3 V 6 TEMP REF OUT C1 AD780 330�F* 2 4 5V V GND AGND1 IN C3 C4 AD977A 1�F 0.1�F V ANA *ESR AT 100kHz MUST BE LESS THAN 0.3�. CAP C2 RECOMMEND KEMET T495 SERIES OR 2.2�F SOURCE CAPABILITY SINK CAPABILITY SANYO 6SA330M. AGND2 LOAD CURRENT – 5mA/DIV Figure 16b. AD780 External Reference to AD977A Config- Figure 15. CAP Pin Load Regulation ured for ±10 V Input Range –18– REV. D dV ON CAP PIN – 10mV/DIV 1mV/DIV AD977/AD977A OFFSET AND GAIN ADJUSTMENT the AD977/AD977A could be oversampled by a factor of 2/4. The AD977/AD977A is factory trimmed to minimize gain, This would yield a 3/6 dB improvement in the effective SNR offset and linearity errors. In some applications, where the ana- performance. log input signal is required to meet the full dynamic range of the DC PERFORMANCE ADC, the gain and offset errors need to be externally trimmed The factory calibration scheme used for the AD977/AD977A to zero. Figures 12 and 13 show the required trim circuitry to compensates for bit weight errors that may exist in the capacitor correct for these offset and gain errors. array. The mismatch in capacitor values is adjusted (using the Where adjustment is required, offset error must be corrected calibration coefficients) during a conversion resulting in excel- before gain error. To achieve this in the bipolar input configura- lent dc linearity performance. Figures 18, 19, 20, 21, 22 and 23, tion, trim the offset potentiometer with the input voltage set to respectively, show typical INL, typical DNL, typical positive and 1/2 LSB below ground. Then adjust the potentiometer until the negative INL and DNL distribution plots for the AD977/AD977A major carry transition is located between 1111 1111 1111 1111 at 25°C. and 0000 0000 0000 0000. To adjust the gain error, an analog A histogram test is a statistical method for deriving an A/D signal should be input at either the first code transition (ADC converter’s differential nonlinearity. A ramp input is sampled by negative full scale) or the last code transition (ADC positive full the ADC and a large number of conversions are taken at each scale). Thus, to adjust for full-scale error, an input voltage of voltage level, averaged then stored. The effect of averaging is to FS/2 – 3/2 LSBs can be applied to V , and the gain potentiom- IN reduce the transition noise by 1/n. If 64 samples are averaged at eter should be adjusted until the output code flickers between each point, the effect of transition noise is reduced by a factor of the last positive code transition 0111 1111 1111 1111 and 0111 8, i.e., a transition noise of 0.8 LSBs rms is reduced to 1111 1111 1110. Should the first code transition need adjust- 0.1 LSBs rms. Theoretically the codes, during a test of DNL, ing, the trim procedure should consist of applying an analog would all be the same size and therefore have an equal number input signal of –FS/2 + 1/2 LSB to the V input and adjust- IN of occurrences. A code with an average number of occurrences ing the trim until the output code flickers between 1000 0000 would have a DNL of “0.” A code that is different from the 0000 0000 and 1000 0000 0000 0001. average would have a DNL that was either greater or less than AC PERFORMANCE zero LSB. A DNL of –1 LSB indicates that there is a missing The AD977/AD977A is fully specified and tested for dynamic code present at the 16-bit level and that the ADC exhibits 15- performance specifications. The ac parameters are required for bit performance. signal processing applications such as speech recognition and 100% spectrum analysis. These applications require information on 2.0 the ADC’s effect on the spectral content of the input signal. 1.5 Hence, the parameters for which the AD977/AD977A is specified include S/(N+D), THD and Spurious Free Dynamic Range. 1.0 These terms are discussed in greater detail in the following 0.5 sections. 0 As a general rule, it is recommended that the results from sev- eral conversions be averaged to reduce the effects of noise and –0.5 thus improve parameters such as S/(N+D) and THD. The ac performance of the AD977/AD977A can be optimized by operat- –1.0 ing the ADC at its maximum sampling rate of 100 kHz/200 kHz –1.5 and digitally filtering the resulting bit stream to the desired signal bandwidth. By distributing noise over a wider frequency range –2.0 06 5 1015 2025 3035 40 45 50 55 606 the noise density in the frequency band of interest can be OUTPUT CODE – K reduced. For example, if the required input bandwidth is 50 kHz, Figure 18. INL Plot 0 100% –10 5280 POINT FFT 2.0 F = 200kHz –20 SAMPLE F = 20kHz, 0dB IN 1.5 –30 SNRD = 86dB –40 THD = –101dB 1.0 –50 –60 0.5 –70 0 –80 –90 –0.5 –100 –110 –1.0 –120 –1.5 –130 05 1015 20253 3054 405 5055 6065 70758 805 90 95100 FREQUENCY – kHz –2.0 06 5 1015 2025 3035 40 45 50 55 606 OUTPUT CODE – K Figure 17. FFT Plot Figure 19. DNL Plot REV. D –19– AMPLITUDE – dB LSB LSB AD977/AD977A 90 50 45 80 40 70 35 60 30 50 25 40 20 30 15 20 10 10 5 0 0 POSITIVE INL – LSB NEGATIVE DNL – LSB Figure 20. Typical Positive INL Distribution (999 Units) Figure 23. Typical Negative DNL Distribution (999 Units) 90 60 SNR+D (dB) FOR AD977A 80 50 70 40 60 30 50 SNR+D (dB) FOR AD977 40 20 30 10 20 0 10 1 10 100 1000 INPUT SIGNAL FREQUENCY – kHz NEGATIVE INL – LSB Figure 21. Typical Negative INL Distribution (999 Units) Figure 24. S/(N+D) vs. Input Frequency 110 –80 120 SFDR 105 –85 100 100 –90 80 95 –95 60 THD 90 –100 40 85 –105 20 SNRD 80 –110 0 –75 –50 –25 0 25 50 75 100 125 150 TEMPERATURE – C POSITIVE DNL – LSB Figure 25. AC Parameters vs. Temperature Figure 22. Typical Positive DNL Distribution (999 Units) –20– REV. D NUMBER OF UNITS NUMBER OF UNITS NUMBER OF UNITS 0.02 –2.5 0 –2.4 0.2 0.10 –2.3 0.3 0.19 –2.2 0.4 0.27 –2.1 0.5 0.36 –2.0 0.6 0.44 –1.9 0.8 0.52 –1.8 0.9 0.61 1 0.69 –1.7 –1.6 1.1 0.77 0.86 –1.5 1.2 0.94 –1.4 1.4 1.02 –1.3 1.5 1.11 –1.2 1.6 1.7 1.19 –1.1 –1.0 1.8 1.27 1.36 –0.9 2 1.44 –0.8 2.1 1.53 –0.7 2.2 2.3 1.61 –0.6 2.4 1.69 –0.5 –0.4 2.6 1.78 2.7 1.86 –0.3 1.94 –0.2 2.8 2.03 –0.1 2.9 SFDR, S/N+D – dB SINAD (dB) FOR V = 0dB IN NUMBER OF UNITS –1.22 –1.17 –1.12 –1.07 –1.02 –0.97 –0.92 –0.87 –0.82 –0.78 –0.73 –0.68 –0.63 –0.58 –0.53 –0.48 –0.43 –0.38 –0.33 –0.28 –0.23 –0.18 –0.14 –0.09 –0.04 THD – dB AD977/AD977A DC CODE UNCERTAINTY to throw away the null bit if the sync input is toggled each time Ideally, a fixed dc input should result in the same output code the null bit appears. for repetitive conversions; however, as a consequence of unavoid- If the application does not require simultaneous sampling, the able circuit noise within the wideband circuits of the ADC, a null bit can be completely avoided by delaying the R/C signal range of output codes may occur for a given input voltage. of each upstream device by one clock cycle with respect to its Thus, when a dc signal is applied to the AD977/AD977A input immediate downstream device. This bit time delay can be accom- and 10,000 conversions are recorded, the result will be a distri- plished through a D-type flip-flop that delays the R/C signal at bution of codes as shown in Figure 26. This histogram shows a its D-input by one cycle of the serial data clock that is at its bell shaped curve consistent with the Gaussian nature of thermal clock input. noise. The histogram is approximately seven codes wide. The standard deviation of this Gaussian distribution results in a code AD977/AD977A AD977/AD977A transition noise of 1 LSB rms. #2 #1 (UPSTREAM) (DOWNSTREAM) 4000 TAG DATA OUT TAG DATA DATA 3500 CS CS R/C R/C 3000 DCLK DCLK 2500 DCLK IN 2000 R/ IN IN 1500 1000 Figure 27. Two AD977/AD977A’s Utilizing Tag It is not recommended that the TAG feature be used with the 500 read during convert mode because this will require data to be 0 clocked out during the second half of the conversion process. It –3 –2 –10 1 2 3 4 is recommended that the read after convert mode be used in an application that wants to take advantage of the TAG feature. To Figure 26. Histogram of 10,000 Conversions of a DC Input improve the data throughput a combination of the two data read methods can be used and is described as follows. USE OF THE TAG INPUT The AD977/AD977A provides a TAG input pin for cascading If two or more AD977/AD977As are to have their data output multiple converters together. This feature is useful for reducing concatenated together in a single data stream, and if data component count in systems where an isolation barrier must be throughput is to be maximized, a system could be designed such crossed and is also useful for systems with a limited capacity for that the upstream device data is read during the first half of its interfacing to a large number of converters. conversion process and the remainder of the downstream devices read during the time between conversions. Assume three AD977As The tag feature only works in the external clock mode and are to have their data concatenated. Assume the further most requires that the DATA output of a “upstream” device be con- downstream device is referred to as device #1 and the further nected to the TAG input of an “downstream” device. most upstream device as #3. Each device is driven from a com- An example of the concatenation of two devices is shown in mon DATACLK and R/C control signal, the CS input of each Figure 27 and their resultant output is shown in Figure 28. device is tied to ground. The three BUSY outputs should be In Figure 27, the paralleled R/C ensures that each AD977/ OR’d together to form a composite BUSY. After the conversion AD977A will simultaneously sample their inputs. In Figure 28, is complete, as indicated by the composite BUSY going high, an a “null” bit is shown between each 16-bit word associated with external, normally low, 15.15 MHz DATACLK can be toggled each ADC in the serial data output stream. This is the result of 34 times to first read the data first from device #3 and then a minimum value for “External Data Clock to Data Valid Delay” from device #2. When the composite BUSY goes low to indicate (t ) that is greater than the “TAG Valid Setup Time” (t ). In the beginning of the conversion process the external DATA- 18 23 other words, when you concatenate two or more AD977/AD977As CLK can be toggled 17 times to read the data from device #1 the MSB on the downstream device will not be present on the during the first half of the conversion process. Using this tech- TAG input of the upstream device in time to meet the setup nique it would be possible to read in the data from the three time requirement of the TAG input. devices in approximately 6.4 µs for a throughput of approxi- mately 156 kHz The receiving device would have to deal with If the serial data stream is going to a parallel port of a micro- the null bit between data from device #2 and #3. The receiving processor that is also providing the serial data clock, then the device would also have to be capable of starting and stopping microprocessor’s firmware can be written to “throw away” the the external DATACLK at the appropriate times. null bit. If the serial data stream is going to a serial port then external “glue” logic will have to be added to make the interface The TAG input, when unused, should always be tied either high work. If the serial port has a “sync” input then this can be used or low and not be allowed to float. REV. D –21– AD977/AD977A MICROPROCESSOR INTERFACING R/C The AD977/AD977A is ideally suited for traditional dc mea- surement applications supporting a microprocessor, and ac BUSY NULL BIT signal processing applications interfacing to a digital signal DATA 15 0 15 processor. The AD977/AD977A is designed to interface with a DEVICE DEVICE DATA #1 general purpose serial port or I/O ports on a microcontroller. A DATA #2 variety of external buffers can be used with the AD977/AD977A DCLK to prevent digital noise from coupling into the ADC. The following sections illustrate the use of the AD977/AD977A with Figure 28. TAG Timing Diagram for Two Concatenated an SPI equipped microcontroller and the ADSP-2181 signal AD977/AD977As processor. POWER-DOWN FEATURE SPI Interface The AD977/AD977A has analog and reference power-down Figure 29 shows a general interface diagram between the capability through the PWRD pin. When the PWRD pin is AD977/AD977A and an SPI equipped microcontroller. This taken high, the power consumption drops from a maximum interface assumes that the convert pulses will originate from the value of 100 mW to a typical value of 50 µW. When in the microcontroller and that the AD977/AD977A will act as the power-down mode the previous conversion results are still avail- slave device. The convert pulse could be initiated in response to able in the internal registers and can be read out providing it has an internal timer interrupt. The reading of output data, one byte not already been shifted out. at a time, if necessary, could be initiated in response to the end- of-conversion signal (BUSY going high). When used with an external reference, connected to the REF pin and a 2.2 µF capacitor, connected to the CAP pin, the SDI DATA power up recovery time is typically 1 ms. This typical value of SCK DATACLK 1 ms for recovery time depends on how much charge has decayed I/O PORT R/C from the external 2.2 µF capacitor on the CAP pin and assumes AD977/ IRQ AD977A BUSY that it has decayed to zero. The 1 ms recovery time has been specified such that settling to 16-bits has been achieved. +5V EXT/INT SPI CS When used with the internal reference, the dominant time con- TAG stant for power-up recovery is determined by the external capacitor on the REF pin and the internal 4K impedance seen at that pin. An external 2.2 µF capacitor is recommended for the Figure 29. AD977/AD977A to SPI Interface REF pin. ADSP-2181 Interface CONSIDERATIONS WHEN USING MULTIPLEXED Figure 30 shows an interface between the AD977/AD977A and INPUTS the ADSP-2181 Digital Signal Processor. The AD977/AD977A Consideration must be given to the effect on A/D performance is configured for the Internal Clock mode (EXT/INT = 0) and in applications that require the use of analog multiplexers or analog will therefore act as the master device. The convert command is switches to interface multiple signals to the AD977/AD977A. The shown generated from an external oscillator in order to provide nonzero “on” resistance of a multiplexer or switch, at the input a low jitter signal appropriate for both dc and ac measurements. to the AD977/AD977A, will increase the system offset and gain Because the SPORT, within the ADSP-2181, will be seeing a error. As an example, consider the AD977 configured for an input discontinuous external clock, some steps are required to ensure voltage range of ±10 V dc. For every 5 Ω of source impedance that the serial port is properly synchronized to this clock during (in addition to the required external 200 Ω input resistor) an each data read operation. The recommended procedure to ensure offset error of 1 LSB would be introduced and the positive this is as follows, gain error would increase by an added 0.00375% of full scale. – enable SPORT0 through the System Control register This error, due to nonzero source impedance, can be cor- – set the SCLK Divide register to zero rected through a hardware or software system level calibration, but will only be valid at the temperature and input voltage – setup PF0 and PF1 as outputs by setting bits 0 and 1 in present at the time of calibration. Another factor to consider is PFTYPE that most analog multiplexers and switches exhibit a nonlinear – force RFS0 low through PF0. The Receive Frame Sync signal relationship between input signal level and on resistance. This has been programmed active high will introduce added distortion products that will degrade THD, – enable AD977/AD977A by forcing CS = 0 through PF1 S/(N+D) and INL. For these reasons it is recommended that an appropriate buffer be used between the output of the multiplexer – enable SPORT0 Receive Interrupt through the IMASK register and the input of the AD977. – wait for at least one full conversion cycle of the AD977/AD977A When switching the input to the multiplexer, and subsequently and throw away the received data the input to the AD977, it is recommended that the transition – disable the AD977/AD977A by forcing CS = 1 through PF1 be made to occur either immediately after the current conver- – wait for a period of time equal to one conversion cycle sion is complete or shortly after the beginning of a conversion. – force RFS0 high through PF0 – enable the AD977/AD977A by forcing CS = 0 through PF1 –22– REV. D AD977/AD977A The ADSP-2181 SPORT0 will now remain synchronized to the connected with the least resistance back to the power supply. external discontinuous clock for all subsequent conversions. AGND1 is the low current analog supply ground and should be the analog common for the external reference, input op amp drive circuitry and the input resistor divider circuit. By applying DR0 DATA the inputs referenced to this ground, any ground variations will SCLK0 DATACLK be offset and have a minimal effect on the resulting analog input OSCILLATOR R/C AD977/ to the ADC. The digital ground pin, DGND, is the reference ADSP-2181 AD977A point for all of the digital signals that control the AD977/AD977A. PF1 CS RFS0 EXT/INT The AD977/AD977A can be powered with two separate power supplies or with a single analog supply. When the system digital PF0 TAG supply is noisy, or fast switching digital signals are present, it is SPORT0 CNTRL REG = 0x300F recommended to connect the analog supply to both the V ANA and V pins of the AD977/AD977A and the system supply to DIG Figure 30. AD977/AD977A to ADSP-2181 Interface the remaining digital circuitry. With this configuration, AGND1, AGND2 and DGND should be connected back at the ADC. POWER SUPPLIES AND DECOUPLING When there is significant bus activity on the digital output pins, The AD977/AD977A has two power supply input pins. V the digital and analog supply pins on the ADC should be ANA and V provide the supply voltages to the analog and digital separated. This would eliminate any high speed digital noise DIG portions, respectively. V is the 5 V supply for the on-chip from coupling back to the analog portion of the AD977/ ANA analog circuitry, and V is the 5 V supply for the on-chip AD977A. In this configuration, the digital ground pin DGND DIG digital circuitry. The AD977/AD977A is designed to be inde- should be connected to the system digital ground and be pendent of power supply sequencing and thus free from supply separate from the AGND pins. voltage induced latchup. BOARD LAYOUT With high performance linear circuits, changes in the power Designing with high resolution data converters requires careful supplies can result in undesired circuit performance. Optimally, attention to board layout. Trace impedance is a significant issue. well regulated power supplies should be chosen with less than A 1.22 mA current through a 0.5 Ω trace will develop a voltage 1% ripple. The ac output impedance of a power supply is a drop of 0.6 mV, which is 2 LSBs at the 16-bit level over the complex function of frequency and will generally increase with 20 volt full-scale range. Ground circuit impedances should be frequency. Thus, high frequency switching, such as that encoun- reduced as much as possible since any ground potential differ- tered with digital circuitry, requires the fast transient currents ences between the signal source and the ADC appear as an error that most power supplies cannot adequately provide. Such a voltage in series with the input signal. In addition to ground situation results in large voltage spikes on the supplies. To com- drops, inductive and capacitive coupling needs to be considered. pensate for the finite ac output impedance of most supplies, This is especially true when high accuracy analog input signals charge “reserves” should be stored in bypass capacitors. This share the same board with digital signals. Thus, to minimize input will effectively lower the supplies impedance presented to the noise coupling, the input signal leads to V and the signal IN AD977/AD977A V and V pins and reduce the magnitude ANA DIG return leads from AGND should be kept as short as possible. of these spikes. Decoupling capacitors, typically 0.1µF, should In addition, power supplies should also be decoupled to filter be placed close to the power supply pins of the AD977/AD977A out ac noise. to minimize any inductance between the capacitors and the V and V pins. Analog and digital signals should not share a common path. ANA DIG Each signal should have an appropriate analog or digital return The AD977/AD977A may be operated from a single 5 V routed close to it. Using this approach, signal loops enclose a supply. When separate supplies are used, however, it is benefi- small area, minimizing the inductive coupling of noise. Wide PC cial to have larger capacitors, 10µF, placed between the logic tracks, large gauge wire and ground planes are highly recom- supply (V ) and digital common (DGND) and between the DIG mended to provide low impedance signal paths. Separate analog analog supply (V ) and the analog common (AGND2). ANA and digital ground planes are also recommended with a single Additionally, 10 µF capacitors should be located in the vicinity interconnection point to minimize ground loops. Analog signals of the ADC to further reduce low frequency ripple. In systems should be routed as far as possible from high speed digital sig- where the device will be subjected to harsh environmental noise, nals and should only cross them, if absolutely necessary, at right additional decoupling may be required. angles. GROUNDING In addition, it is recommended that multilayer PC boards be used The AD977/AD977A has three ground pins; AGND1, AGND2 with separate power and ground planes. When designing the and DGND. The analog ground pins are the “high quality” separate sections, careful attention should be paid to the layout. ground reference points and should be connected to the system analog common. AGND2 is the ground to which most internal ADC analog signals are referenced. This ground is most sus- ceptible to current induced voltage drops and thus must be REV. D –23– AD977/AD977A OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 20-Lead Plastic DIP (N-20) 1.060 (26.90) 0.925 (23.50) 20 11 0.280 (7.11) 0.240 (6.10) 110 0.325 (8.25) 0.195 (4.95) 0.060 (1.52) 0.300 (7.62) PIN 1 0.115 (2.93) 0.015 (0.38) 0.210 (5.33) MAX 0.130 0.160 (4.06) (3.30) MIN 0.115 (2.93) 0.015 (0.381) SEATING 0.022 (0.558) 0.100 0.070 (1.77) 0.008 (0.204) PLANE (2.54) 0.045 (1.15) 0.014 (0.356) BSC 20-Lead Wide Body (SOIC) (R-20) 0.5118 (13.00) 0.4961 (12.60) 20 11 1 10 PIN 1 0.1043 (2.65) 0.0291 (0.74) x 45° 0.0926 (2.35) 0.0098 (0.25) 0.0500 (1.27) 8° 0.0118 (0.30) 0.0500 0.0192 (0.49) 0° 0.0157 (0.40) SEATING 0.0125 (0.32) (1.27) 0.0040 (0.10) 0.0138 (0.35) PLANE BSC 0.0091 (0.23) 28-Lead Shrink Small Outline Package (SSOP) (RS-28) 0.407 (10.34) 0.397 (10.08) 28 15 1 14 0.07 (1.79) 0.078 (1.98) PIN 1 0.066 (1.67) 0.068 (1.73) 0.03 (0.762) 8° 0.0256 0.015 (0.38) 0° 0.022 (0.558) 0.008 (0.203) SEATING 0.009 (0.229) (0.65) 0.010 (0.25) 0.002 (0.050) PLANE BSC 0.005 (0.127) –24– REV. D 0.311 (7.9) 0.301 (7.64) 0.2992 (7.60) 0.2914 (7.40) 0.4193 (10.65) 0.212 (5.38) 0.3937 (10.00) 0.205 (5.21) PRINTED IN U.S.A. C00913d–5–10/00 (rev. D)