ANALOG DEVICES AD9779

Dual 12-/14-/16-Bit, 1 GSPS, Digital-to-Analog Converters AD9776/AD9778/AD9779 FEATURES GENERAL DESCRIPTION Low power: 1.0 W @ 1 GSPS, 600 mW @ 500 MSPS, The AD9776/AD9778/AD9779 are dual, 12-/14-/16-bit, high full operating conditions dynamic range, digital-to-analog converters (DACs) that pro- SFDR = 78 dBc to f = 100 MHz OUT vide a sample rate of 1 GSPS, permitting multicarrier generation Single carrier WCDMA ACLR = 79 dBc @ 80 MHz IF up to the Nyquist frequency. They include features optimized Analog output: adjustable 8.7 mA to 31.7 mA, for direct conversion transmit applications, including complex R = 25 Ω to 50 Ω L digital modulation, and gain and offset compensation. The DAC Novel 2×, 4×, and 8× interpolator/coarse complex modulator outputs are optimized to interface seamlessly with analog quad- allows carrier placement anywhere in DAC bandwidth rature modulators such as the AD8349. A serial peripheral interface Auxiliary DACs allow control of external VGA and offset control (SPI®) provides for programming/readback of many internal Multiple chip synchronization interface parameters. Full-scale output current can be programmed over a High performance, low noise PLL clock multiplier range of 10 mA to 30 mA. The devices are manufactured on an Digital inverse sinc filter advanced 0.18 μm CMOS process and operate on 1.8 V and 100-lead, exposed paddle TQFP package 3.3 V supplies for a total power consumption of 1.0 W. They are APPLICATIONS enclosed in 100-lead TQFP packages. Wireless infrastructure PRODUCT HIGHLIGHTS WCDMA, CDMA2000, TD-SCDMA, WiMax, GSM 1. Ultralow noise and intermodulation distortion (IMD) Digital high or low IF synthesis enable high quality synthesis of wideband signals from Internal digital upconversion capability baseband to high intermediate frequencies. Transmit diversity 2. A proprietary DAC output switching technique enhances Wideband communications: LMDS/MMDS, point-to-point dynamic performance. 3. The current outputs are easily configured for various single-ended or differential circuit topologies. 4. CMOS data input interface with adjustable set up and hold. 5. Novel 2×, 4×, and 8× interpolator/coarse complex modulator allows carrier placement anywhere in DAC bandwidth. TYPICAL SIGNAL CHAIN QUADRATURE MODULATOR/ COMPLEX I AND Q MIXER/ AMPLIFIER LO DC DC DIGITAL INTERPOLATION FILTERS I DAC POST DAC FPGA/ASIC/DSP ANALOG FILTER Q DAC A AD9779 Figure 1. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2005–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 05361-114 AD9776/AD9778/AD9779 TABLE OF CONTENTS Features .............................................................................................. 1 SPI Register Map ............................................................................ 27 Applications....................................................................................... 1 Interpolation Filter Architecture.................................................. 31 General Description ......................................................................... 1 Interpolation Filter Minimum and Maximum Bandwidth Specifications .............................................................................. 35 Product Highlights ........................................................................... 1 Driving the REFCLK Input....................................................... 35 Typical Signal Chain......................................................................... 1 Internal PLL Clock Multiplier/Clock Distribution................ 36 Revision History ............................................................................... 2 Full-Scale Current Generation ................................................. 38 Functional Block Diagram .............................................................. 3 Power Dissipation....................................................................... 39 Specifications..................................................................................... 4 Power-Down and Sleep Modes................................................. 41 DC Specifications ......................................................................... 4 Interleaved Data Mode .............................................................. 41 Digital Specifications ................................................................... 6 Timing Information................................................................... 41 Digital Input Data Timing Specifications ................................. 7 Synchronization of Input Data to DATACLK AC Specifications.......................................................................... 7 Output (Pin 37)........................................................................... 43 Absolute Maximum Ratings............................................................ 8 Synchronization of Input Data to the REFCLK Input (Pin 5 and Pin 6) with PLL Enabled or Disabled............................... 43 Thermal Resistance ...................................................................... 8 Evaluation Board Operation ......................................................... 46 ESD Caution.................................................................................. 8 Modifying the Evaluation Board to Use the AD8349 On- Pin Configurations and Function Descriptions ........................... 9 Board Quadrature Modulator................................................... 48 Typical Performance Characteristics ........................................... 15 Evaluation Board Schematics ................................................... 49 Terminology .................................................................................... 24 Outline Dimensions ....................................................................... 56 Theory of Operation ...................................................................... 25 Ordering Guide .......................................................................... 56 Serial Peripheral Interface ......................................................... 25 MSB/LSB Transfers..................................................................... 26 REVISION HISTORY Added Table 19, Renumbered Tables Sequentially .................... 41 3/07—Rev. 0 to Rev. A Changes to Figure 92 and Figure 93............................................. 42 Changes to Features.......................................................................... 1 Changes to Figure 94...................................................................... 42 Changes to Applications .................................................................. 1 Added New Figure 95, Renumbered Figures Sequentially ....... 42 Changes to General Product Highlights........................................ 1 Changes to Synchronization of Input Data to the REFCLK Input Added Figure 1, Renumbered Figures Sequentially..................... 1 (Pin 5 and Pin 6) with PLL Enabled or Disabled Section ......... 43 Changes to Table 1............................................................................ 4 Added New Figure 96, Renumbered Figures Sequentially ....... 43 Changes to Table 2............................................................................ 5 Changes to Figure 106 ................................................................... 51 Changes to Table 3............................................................................ 5 Changes to Figure 53 and Figure 54............................................. 26 7/05—Revision 0: Initial Version Changes to Table 12........................................................................ 29 Changes to Power Dissipation Section ........................................ 39 Rev. A | Page 2 of 56 AD9776/AD9778/AD9779 FUNCTIONAL BLOCK DIAGRAM DELAY SYNC_O LINE CLOCK GENERATION/DISTRIBUTION SYNC_I CLOCK CLK+ DELAY MULTIPLIER DATACLK_OUT LINE 2×/4×/8× CLK– DATA ASSEMBLER 1 SYNC IOUT1_P 16-BIT IDAC I IOUT1_N P1D(15:0) LATCH 2× 2× 2× n × f /8 DAC n = 0, 1, 2 ... 7 Q IOUT2_P 16-BIT LATCH 2× 2× 2× P2D(15:0) QDAC IOUT2_N 1 SYNC VREF I120 DIGITAL CONTROLLER 10 GAIN 10 GAIN SERIAL POWER-ON PERIPHERAL RESET INTERFACE 10 AUX1_P GAIN AUX1_N 10 AUX2_P GAIN AUX2_N Figure 2. Functional Block Diagram Rev. A | Page 3 of 56 SDO SDIO SCLK CSB COMPLEX MODULATOR REFERENCE AND BIAS 05361-001 AD9776/AD9778/AD9779 SPECIFICATIONS DC SPECIFICATIONS T to T , AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 =1.8 V, I = 20 mA, maximum sample rate, unless MIN MAX OUTF S otherwise noted. Table 1. AD9776, AD9778, and AD9779 DC Specifications AD9776 AD9778 AD9779 Parameter Min Typ Max Min Typ Max Min Typ Max Unit RESOLUTION 12 14 16 Bits ACCURACY Differential Nonlinearity (DNL) ±0.1 ±0.65 ±2.1 LSB Integral Nonlinearity (INL) ±0.6 ±1 ±3.7 LSB MAIN DAC OUTPUTS Offset Error −0.001 0 +0.001 −0.001 0 +0.001 −0.001 0 +0.001 % FSR Gain Error (with Internal ±2 ±2 ±2 % FSR Reference) 1 Full-Scale Output Current 8.66 20.2 31.66 8.66 20.2 31.66 8.66 20.2 31.66 mA Output Compliance Range −1.0 +1.0 −1.0 +1.0 −1.0 +1.0 V Output Resistance 10 10 10 MΩ Gain DAC Monotonicity Guaranteed Guaranteed Guaranteed MAIN DAC TEMPERATURE DRIFT Offset 0.04 0.04 0.04 ppm/°C Gain 100 100 100 ppm/°C Reference Voltage 30 30 30 ppm/°C AUX DAC OUTPUTS Resolution 10 10 10 Bits 1 Full-Scale Output Current −1.998 +1.998 −1.998 +1.998 −1.998 +1.998 mA Output Compliance Range 0 1.6 0 1.6 0 1.6 V (Source) Output Compliance Range 0.8 1.6 0.8 1.6 0.8 1.6 V (Sink) Output Resistance 1 1 1 MΩ Aux DAC Monotonicity Guaranteed REFERENCE Internal Reference Voltage 1.2 1.2 1.2 V Output Resistance 5 5 5 kΩ ANALOG SUPPLY VOLTAGES AVDD33 3.13 3.3 3.47 3.13 3.3 3.47 3.13 3.3 3.47 V CVDD18 1.70 1.8 1.90 1.70 1.8 1.90 1.70 1.8 1.90 V DIGITAL SUPPLY VOLTAGES DVDD33 3.13 3.3 3.47 3.13 3.3 3.47 3.13 3.3 3.47 V DVDD18 1.70 1.8 1.90 1.70 1.8 1.90 1.70 1.8 1.90 V POWER CONSUMPTION 1× Mode, f = 100 MSPS, 250 300 250 300 250 300 mW DAC IF = 1 MHz 2× Mode, fDAC = 320 MSPS, 498 498 498 mW IF = 16 MHz, PLL Off 2× Mode, f = 320 MSPS, 588 588 588 mW DAC IF = 16 MHz, PLL On 4× Mode, f /4 Modulation, 572 572 572 mW DAC fDAC = 500 MSPS, IF = 137.5 MHz, Q DAC Off Rev. A | Page 4 of 56 AD9776/AD9778/AD9779 AD9776 AD9778 AD9779 Parameter Min Typ Max Min Typ Max Min Typ Max Unit 8× Mode, fDAC/4 Modulation, 980 980 980 mW f = 1 GSPS, IF = 262.5 MHz DAC Power-Down Mode 2 3.7 2 3.7 2 3.7 mW −0.3 +0.3 −0.3 +0.3 −0.3 +0.3 % FSR/V Power Supply Rejection Ratio, AVDD33 OPERATING RANGE −40 +25 +85 −40 +25 +85 −40 +25 +85 °C 1 Based on a 10 kΩ external resistor. Rev. A | Page 5 of 56 AD9776/AD9778/AD9779 DIGITAL SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, I = 20 mA, maximum sample rate, unless OUTF S otherwise noted. LVDS driver and receiver are compliant to the IEEE-1596 reduced range link, unless otherwise noted. Table 2. AD9776, AD9778, and AD9779 Digital Specifications Parameter Conditions Min Typ Max Unit CMOS INPUT LOGIC LEVEL Input V Logic High 2.0 V IN Input VIN Logic Low 0.8 V Maximum Input Data Rate at Interpolation 1× 300 MSPS 2× 250 MSPS 4× 200 MSPS 8× 125 MSPS 1 CMOS OUTPUT LOGIC LEVEL (DATACLK, PIN 37) Output V Logic High 2.4 V OUT Output V Logic Low 0.4 V OUT LVDS RECEIVER INPUTS (SYNC_I+, SYNC_I−) SYNC_I+ = V , SYNC_I− = V IA IB Input Voltage Range, V or V 825 1575 mV IA IB Input Differential Threshold, VIDTH −100 +100 mV Input Differential Hysteresis, VIDTHH − VIDTHL 20 mV 2 Receiver Differential Input Impedance, RIN 80 120 Ω LVDS Input Rate 125 MSPS Set-Up Time, SYNC_I to DAC Clock −0.2 ns Hold Time, SYNC_I to DAC Clock 1 ns LVDS DRIVER OUTPUTS (SYNC_O+, SYNC_O−) SYNC_O+ = V , SYNC_O− = V , 100 Ω termination OA OB Output Voltage High, V or V 825 1575 mV OA OB Output Voltage Low, V or V 1025 mV OA OB Output Differential Voltage, |VOD| 150 200 250 mV Output Offset Voltage, VOS 1150 1250 mV Output Impedance, RO Single-ended 80 100 120 Ω Maximum Clock Rate 1 GHz DAC CLOCK INPUT (CLK+, CLK−) 3 Differential Peak-to-Peak Voltage (CLK+, CLK−) 400 800 2000 mV Common-Mode Voltage 300 400 500 mV 4 Maximum Clock Rate 1 GSPS SERIAL PERIPHERAL INTERFACE Maximum Clock Rate (SCLK) 40 MHz Minimum Pulse Width High 12.5 ns Minimum Pulse Width Low 12.5 ns 1 Specification is at a DATACLK frequency of 100 MHz into a 1 kΩ load; maximum drive capability of 8 mA. At higher speeds or greater loads, best practice suggests using an external buffer for this signal. 2 Guaranteed at 25°C. Can drift above 120 Ω at temperatures above 25°C. 3 When using the PLL, a differential swing of 2 V p-p is recommended. 4 Typical maximum clock rate when DVDD18 = CVDD18 = 1.9 V. Rev. A | Page 6 of 56 AD9776/AD9778/AD9779 DIGITAL INPUT DATA TIMING SPECIFICATIONS Table 3. AD9776, AD9778, and AD9779 Digital Input Data Timing Specifications Parameter Min Typ Max Unit 1 INPUT DATA (ALL MODES, −40°C to +85°C) Set-Up Time, Input Data to DATACLK +2.5 ns Hold Time, Input Data to DATACLK −0.4 ns Set-Up Time, Input Data to REFCLK −0.8 ns Hold Time, Input Data to REFCLK +2.9 ns 1 Timing vs. temperature and data valid keep out windows are delineated in Table 19. AC SPECIFICATIONS T to T , AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, I = 20 mA, maximum sample rate, unless MIN MAX OUTF S otherwise noted. Table 4. AD9776, AD9778, and AD9779 AC Specifications AD9776 AD9778 AD9779 Parameter Min Typ Max Min Typ Max Min Typ Max Unit SPURIOUS FREE DYNAMIC RANGE (SFDR) f = 100 MSPS, f = 20 MHz 82 82 82 dBc DAC OUT f = 200 MSPS, f = 50 MHz 81 81 82 dBc DAC OUT fDAC = 400 MSPS, fOUT = 70 MHz 80 80 80 dBc fDAC = 800 MSPS, fOUT = 70 MHz 85 85 87 dBc TWO-TONE INTERMODULATION DISTORTION (IMD) fDAC = 200 MSPS, fOUT = 50 MHz 87 87 91 dBc fDAC = 400 MSPS, fOUT = 60 MHz 80 85 85 dBc f = 400 MSPS, f = 80 MHz 75 81 81 dBc DAC OUT f = 800 MSPS, f = 100 MHz 75 80 81 dBc DAC OUT NOISE SPECTRAL DENSITY (NSD) EIGHT-TONE, 500 kHz TONE SPACING f = 200 MSPS, f = 80 MHz −152 −155 −158 dBm/Hz DAC OUT fDAC = 400 MSPS, fOUT = 80 MHz −155 −159 −160 dBm/Hz fDAC = 800 MSPS, fOUT = 80 MHz −157.5 −160 −161 dBm/Hz WCDMA ADJACENT CHANNEL LEAKAGE RATIO (ACLR), SINGLE CARRIER fDAC = 491.52 MSPS, fOUT = 100 MHz 76 78 79 dBc fDAC = 491.52 MSPS, fOUT = 200 MHz 69 73 74 dBc WCDMA SECOND ADJACENT CHANNEL LEAKAGE RATIO (ACLR), SINGLE CARRIER f = 491.52 MSPS, f = 100 MHz 77.5 80 81 dBc DAC OUT f = 491.52 MSPS, f = 200 MHz 76 78 78 dBc DAC OUT Rev. A | Page 7 of 56 AD9776/AD9778/AD9779 ABSOLUTE MAXIMUM RATINGS Table 5. Stresses above those listed under Absolute Maximum Ratings With may cause permanent damage to the device. This is a stress Respect rating only; functional operation of the device at these or any Parameter To Rating other conditions above those indicated in the operational AVDD33, DVDD33 AGND, −0.3 V to +3.6 V section of this specification is not implied. Exposure to absolute DGND, maximum rating conditions for extended periods may affect CGND device reliability. DVDD18, CVDD18 AGND, −0.3 V to +1.98 V DGND, THERMAL RESISTANCE CGND AGND DGND, −0.3 V to +0.3 V 100-lead, thermally enhanced TQFP_EP package, θ = 19.1°C/W JA CGND with the bottom EPAD soldered to the PCB. With the bottom DGND AGND, −0.3 V to +0.3 V EPAD not soldered to the PCB, θ = 27.4°C/W. These JA CGND specifications are valid with no airflow movement. CGND AGND, −0.3 V to +0.3 V DGND ESD CAUTION I120, VREF, IPTAT AGND −0.3 V to AVDD33 + 0.3 V I , I , I , AGND −1.0 V to AVDD33 + 0.3 V OUT1-P OUT1-N OUT2-P I , Aux , Aux , OUT2-N 1-P 1-N Aux2-P, Aux2-N P1D15 to P1D0, DGND −0.3 V to DVDD33 + 0.3 V P2D15 to P2D0 DATACLK, TXENABLE DGND −0.3 V to DVDD33 + 0.3 V CLK+, CLK− CGND −0.3 V to CVDD18 + 0.3 V RESET, IRQ, PLL_LOCK, DGND −0.3 V to DVDD33 + 0.3 V SYNC_O+, SYNC_O−, SYNC_I+, SYNC_I−, CSB, SCLK, SDIO, SDO Junction Temperature +125°C Storage Temperature −65°C to +150°C Range Rev. A | Page 8 of 56 AD9776/AD9778/AD9779 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 75 CVDD18 I120 PIN 1 2 74 CVDD18 VREF CGND 3 73 IPTAT ANALOG DOMAIN CGND 4 72 AGND CLK+ 5 71 IRQ CLK– 6 DIGITAL DOMAIN 70 RESET CGND 7 69 CSB CGND 8 68 SCLK CVDD18 9 67 SDIO AD9776 CVDD18 10 66 SDO TOP VIEW (Not to Scale) 11 65 CGND PLL_LOCK 12 64 AGND DGND 13 63 SYNC_I+ SYNC_O+ 14 62 SYNC_I– SYNC_O– 15 61 DGND DVDD33 16 60 DVDD18 DVDD18 17 59 P1D<11> NC 18 58 P1D<10> NC 19 57 P1D<9> NC P1D<8> 20 56 NC P1D<7> 21 55 P2D<0> DGND 22 54 DGND DVDD18 23 53 DVDD18 P1D<6> 24 52 P2D<1> P1D<5> 25 51 P2D<2> 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC = NO CONNECT Figure 3. AD9776 Pin Configuration Table 6. AD9776 Pin Function Descriptions Pin Pin No. Mnemonic Description No. Mnemonic Description 1 CVDD18 1.8 V Clock Supply. 20 P1D<8> Port 1, Data Input D8. 2 CVDD18 1.8 V Clock Supply. 21 P1D<7> Port 1, Data Input D7. 3 CGND Clock Common. 22 DGND Digital Common. 4 CGND Clock Common. 23 DVDD18 1.8 V Digital Supply. 1 5 CLK+ Differential Clock Input. 24 P1D<6> Port 1, Data Input D6. 1 6 CLK− Differential Clock Input. 25 P1D<5> Port 1, Data Input D5. 7 CGND Clock Common. 26 P1D<4> Port 1, Data Input D4. 8 CGND Clock Common. 27 P1D<3> Port 1, Data Input D3. 9 CVDD18 1.8 V Clock Supply. 28 P1D<2> Port 1, Data Input D2. 10 CVDD18 1.8 V Clock Supply. 29 P1D<1> Port 1, Data Input D1. 11 CGND Clock Common. 30 P1D<0> Port 1, Data Input D0 (LSB). 12 AGND Analog Common. 31 NC No Connect. 13 SYNC_I+ Differential Synchronization Input. 32 DGND Digital Common. 14 SYNC_I− Differential Synchronization Input. 33 DVDD18 1.8 V Digital Supply. 15 DGND Digital Common. 34 NC No Connect. 16 DVDD18 1.8 V Digital Supply. 35 NC No Connect. 17 P1D<11> Port 1, Data Input D11 (MSB). 36 NC No Connect. 18 P1D<10> Port 1, Data Input D10. 37 DATACLK Data Clock Output. 19 P1D<9> Port 1, Data Input D9. 38 DVDD33 3.3 V Digital Supply. Rev. A | Page 9 of 56 P1D<4> AVDD33 P1D<3> AGND P1D<2> AVDD33 P1D<1> AGND P1D<0> AVDD33 NC AGND DGND AGND DVDD18 OUT1_P NC OUT1_N NC AGND NC AUX1_P DATACLK AUX1_N DVDD33 AGND TXENABLE AUX2_N P2D<11> AUX2_P P2D<10> AGND P2D<9> OUT2_N DVDD18 OUT2_P DGND AGND P2D<8> AGND P2D<7> AVDD33 P2D<6> AGND P2D<5> AVDD33 P2D<4> AGND P2D<3> AVDD33 05361-002 AD9776/AD9778/AD9779 Pin Pin No. Mnemonic Description No. Mnemonic Description 39 TXENABLE Transmit Enable. 73 IPTAT Factory Test Pin. Output current is proportional to absolute temperature, 40 P2D<11> Port 2, Data Input D11 (MSB). approximately 10 μA at 25°C with 41 P2D<10> Port 2, Data Input D10. approximately 20 nA/°C slope. This pin 42 P2D<9> Port 2, Data Input D9. should remain floating. 43 DVDD18 1.8 V Digital Supply. 74 VREF Voltage Reference Output. 44 DGND Digital Common. 75 I120 120 μA Reference Current. 45 P2D<8> Port 2, Data Input D8. 76 AVDD33 3.3 V Analog Supply. 46 P2D<7> Port 2, Data Input D7. 77 AGND Analog Common. 47 P2D<6> Port 2, Data Input D6. 78 AVDD33 3.3 V Analog Supply. 48 P2D<5> Port 2, Data Input D5. 79 AGND Analog Common. 49 P2D<4> Port 2, Data Input D4. 80 AVDD33 3.3 V Analog Supply. 50 P2D<3> Port 2, Data Input D3. 81 AGND Analog Common. 51 P2D<2> Port 2, Data Input D2. 82 AGND Analog Common. 52 P2D<1> Port 2, Data Input D1. 83 OUT2_P Differential DAC Current Output, Channel 2. 53 DVDD18 1.8 V Digital Supply. 84 OUT2_N Differential DAC Current Output, Channel 2. 54 DGND Digital Common. 85 AGND Analog Common. 55 P2D<0> Port 2, Data Input D0 (LSB). 86 AUX2_P Auxiliary DAC Current Output, Channel 2. 56 NC No Connect. 87 AUX2_N Auxiliary DAC Current Output, Channel 2. 57 NC No Connect. 88 AGND Analog Common. 58 NC No Connect. 89 AUX1_N Auxiliary DAC Current Output, Channel 1. 59 NC No Connect. 90 AUX1_P Auxiliary DAC Current Output, Channel 1. 60 DVDD18 1.8 V Digital Supply. 91 AGND Analog Common. 61 DVDD33 3.3 V Digital Supply. 92 OUT1_N Differential DAC Current Output, Channel 1. 62 SYNC_O− Differential Synchronization Output. 93 OUT1_P Differential DAC Current Output, Channel 1. 63 SYNC_O+ Differential Synchronization Output 94 AGND Analog Common. 64 DGND Digital Common 95 AGND Analog Common. 65 PLL_LOCK PLL Lock Indicator 96 AVDD33 3.3 V Analog Supply. 66 SDO SPI Port Data Output 97 AGND Analog Common. 67 SDIO SPI Port Data Input/Output 98 AVDD33 3.3 V Analog Supply. 68 SCLK SPI Port Clock 99 AGND Analog Common. 69 CSB SPI Port Chip Select Bar. 100 AVDD33 3.3 V Analog Supply. 70 RESET Reset, Active High. 1 The combined differential clock input at the CLK+ and CLK– pins are referred 71 IRQ Interrupt Request. to as REFCLK. 72 AGND Analog Common. Rev. A | Page 10 of 56 AD9776/AD9778/AD9779 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 CVDD18 1 75 I120 PIN 1 CVDD18 2 74 VREF 3 73 CGND IPTAT ANALOG DOMAIN 4 72 CGND AGND 5 71 CLK+ IRQ 6 70 CLK– DIGITAL DOMAIN RESET 7 69 CGND CSB 8 68 CGND SCLK CVDD18 9 67 SDIO AD9778 10 66 CVDD18 SDO TOP VIEW (Not to Scale) 11 65 CGND PLL_LOCK 12 64 AGND DGND SYNC_I+ 13 63 SYNC_O+ SYNC_I– 14 62 SYNC_O– DGND 15 61 DVDD33 DVDD18 16 60 DVDD18 P1D<13> 17 59 NC P1D<12> 18 58 NC P1D<11> 19 57 P2D<0> 20 56 P1D<10> P2D<1> 21 55 P1D<9> P2D<2> 22 54 DGND DGND 23 53 DVDD18 DVDD18 24 52 P1D<8> P2D<3> 25 51 P1D<7> P2D<4> 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC = NO CONNECT Figure 4. AD9778 Pin Configuration Table 7. AD9778 Pin Function Description Pin Pin No. Mnemonic Description No. Mnemonic Description 1 CVDD18 1.8 V Clock Supply. 21 P1D<9> Port 1, Data Input D9. 2 CVDD18 1.8 V Clock Supply. 22 DGND Digital Common. 3 CGND Clock Common. 23 DVDD18 1.8 V Digital Supply. 4 CGND Clock Common. 24 P1D<8> Port 1, Data Input D8. 1 5 CLK+ Differential Clock Input. 25 P1D<7> Port 1, Data Input D7. 1 6 CLK− Differential Clock Input. 26 P1D<6> Port 1, Data Input D6. 7 CGND Clock Common. 27 P1D<5> Port 1, Data Input D5. 8 CGND Clock Common. 28 P1D<4> Port 1, Data Input D4. 9 CVDD18 1.8 V Clock Supply. 29 P1D<3> Port 1, Data Input D3. 10 CVDD18 1.8 V Clock Supply. 30 P1D<2> Port 1, Data Input D2. 11 CGND Clock Common. 31 P1D<1> Port 1, Data Input D1. 12 AGND Analog Common. 32 DGND Digital Common. 13 SYNC_I+ Differential Synchronization Input. 33 DVDD18 1.8 V Digital Supply. 14 SYNC_I− Differential Synchronization Input. 34 P1D<0> Port 1, Data Input D0 (LSB). 15 DGND Digital Common. 35 NC No Connect. 16 DVDD18 1.8 V Digital Supply. 36 NC No Connect. 17 P1D<13> Port 1, Data Input D13 (MSB). 37 DATACLK Data Clock Output. 18 P1D<12> Port 1, Data Input D12. 38 DVDD33 3.3 V Digital Supply. 19 P1D<11> Port 1, Data Input D11. 39 TXENABLE Transmit Enable. 20 P1D<10> Port 1, Data Input D10. 40 P2D<13> Port 2, Data Input D13 (MSB). Rev. A | Page 11 of 56 P1D<6> AVDD33 P1D<5> AGND P1D<4> AVDD33 P1D<3> AGND P1D<2> AVDD33 P1D<1> AGND DGND AGND DVDD18 OUT1_P P1D<0> OUT1_N NC AGND NC AUX1_P DATACLK AUX1_N DVDD33 AGND TXENABLE AUX2_N P2D<13> AUX2_P P2D<12> AGND P2D<11> OUT2_N DVDD18 OUT2_P DGND AGND P2D<10> AGND P2D<9> AVDD33 P2D<8> AGND P2D<7> AVDD33 P2D<6> AGND P2D<5> AVDD33 05361-003 AD9776/AD9778/AD9779 Pin Pin No. Mnemonic Description No. Mnemonic Description 41 P2D<12> Port 2, Data Input D12. 74 VREF Voltage Reference Output. 42 P2D<11> Port 2, Data Input D11. 75 I120 120 μA Reference Current. 43 DVDD18 1.8 V Digital Supply. 76 AVDD33 3.3 V Analog Supply. 44 DGND Digital Common. 77 AGND Analog Common. 45 P2D<10> Port 2, Data Input D10. 78 AVDD33 3.3 V Analog Supply. 46 P2D<9> Port 2, Data Input D9. 79 AGND Analog Common. 47 P2D<8> Port 2, Data Input D8. 80 AVDD33 3.3 V Analog Supply. 48 P2D<7> Port 2, Data Input D7. 81 AGND Analog Common. 49 P2D<6> Port 2, Data Input D6. 82 AGND Analog Common. 50 P2D<5> Port 2, Data Input D5. 83 OUT2_P Differential DAC Current Output, Channel 2. 51 P2D<4> Port 2, Data Input D4. 84 OUT2_N Differential DAC Current Output, 52 P2D<3> Port 2, Data Input D3. Channel 2. 53 DVDD18 1.8 V Digital Supply. 85 AGND Analog Common. 54 DGND Digital Common. 86 AUX2_P Auxiliary DAC Current Output, 55 P2D<2> Port 2, Data Input D2. Channel 2. 56 P2D<1> Port 2, Data Input D1. 87 AUX2_N Auxiliary DAC Current Output, 57 P2D<0> Port 2, Data Input D0 (LSB). Channel 2. 58 NC No Connect. 88 AGND Analog Common. 59 NC No Connect. 89 AUX1_N Auxiliary DAC Current Output, 60 DVDD18 1.8 V Digital Supply. Channel 1. 61 DVDD33 3.3 V Digital Supply. 90 AUX1_P Auxiliary DAC Current Output, 62 SYNC_O− Differential Synchronization Output. Channel 1. 63 SYNC_O+ Differential Synchronization Output. 91 AGND Analog Common. 64 DGND Digital Common. 92 OUT1_N Differential DAC Current Output, Channel 1. 65 PLL_LOCK PLL Lock Indicator. 93 OUT1_P Differential DAC Current Output, 66 SDO SPI Port Data Output. Channel 1. 67 SDIO SPI Port Data Input/Output. 94 AGND Analog Common. 68 SCLK SPI Port Clock. 95 AGND Analog Common. 69 CSB SPI Port Chip Select Bar. 96 AVDD33 3.3 V Analog Supply. 70 RESET Reset, Active High. 97 AGND Analog Common. 71 IRQ Interrupt Request. 98 AVDD33 3.3 V Analog Supply. 72 AGND Analog Common. 99 AGND Analog Common. 73 IPTAT Factory Test Pin. Output current is 100 AVDD33 3.3 V Analog Supply. proportional to absolute temperature, approximately 10 μA at 25°C with 1 The combined differential clock input at the CLK+ and CLK– pins are referred approximately 20 nA/°C slope. This to as REFCLK. pin should remain floating. Rev. A | Page 12 of 56 AD9776/AD9778/AD9779 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 CVDD18 1 75 I120 PIN 1 CVDD18 2 74 VREF 3 73 CGND IPTAT ANALOG DOMAIN 4 72 CGND AGND 5 71 CLK+ IRQ 6 70 CLK– DIGITAL DOMAIN RESET 7 69 CGND CSB 8 68 CGND SCLK 9 67 CVDD18 SDIO AD9779 10 66 CVDD18 SDO TOP VIEW (Not to Scale) 11 65 CGND PLL_LOCK 12 64 AGND DGND 13 63 SYNC_I+ SYNC_O+ 14 62 SYNC_I– SYNC_O– DGND 15 61 DVDD33 DVDD18 16 60 DVDD18 P1D<15> 17 59 P2D<0> P1D<14> 18 58 P2D<1> P1D<13> 19 57 P2D<2> 20 56 P1D<12> P2D<3> 21 55 P1D<11> P2D<4> 22 54 DGND DGND 23 53 DVDD18 DVDD18 24 52 P1D<10> P2D<5> 25 51 P1D<9> P2D<6> 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Figure 5. AD9779 Pin Configuration Table 8. AD9779 Pin Function Descriptions Pin Pin No. Mnemonic Description No. Mnemonic Description 1 CVDD18 1.8 V Clock Supply. 22 DGND Digital Common. 2 CVDD18 1.8 V Clock Supply. 23 DVDD18 1.8 V Digital Supply. 3 CGND Clock Common. 24 P1D<10> Port 1, Data Input D10. 4 CGND Clock Common. 25 P1D<9> Port 1, Data Input D9. 1 5 CLK+ Differential Clock Input. 26 P1D<8> Port 1, Data Input D8. 1 6 CLK− Differential Clock Input. 27 P1D<7> Port 1, Data Input D7. 7 CGND Clock Common. 28 P1D<6> Port 1, Data Input D6. 8 CGND Clock Common. 29 P1D<5> Port 1, Data Input D5. 9 CVDD18 1.8 V Clock Supply. 30 P1D<4> Port 1, Data Input D4. 10 CVDD18 1.8 V Clock Supply. 31 P1D<3> Port 1, Data Input D3. 11 CGND Clock Common. 32 DGND Digital Common. 12 AGND Analog Common. 33 DVDD18 1.8 V Digital Supply. 13 SYNC_I+ Differential Synchronization Input. 34 P1D<2> Port 1, Data Input D2. 14 SYNC_I− Differential Synchronization Input. 35 P1D<1> Port 1, Data Input D1. 15 DGND Digital Common. 36 P1D<0> Port 1, Data Input D0 (LSB). DATACLK 16 DVDD18 1.8 V Digital Supply. 37 Data Clock Output. 17 P1D<15> Port 1, Data Input D15 (MSB). 38 DVDD33 3.3 V Digital Supply. 18 P1D<14> Port 1, Data Input D14. 39 TXENABLE Transmit Enable. 19 P1D<13> Port 1, Data Input D13. 40 P2D<15> Port 2, Data Input D15 (MSB). 20 P1D<12> Port 1, Data Input D12. 41 P2D<14> Port 2, Data Input D14. 21 P1D<11> Port 1, Data Input D11. 42 P2D<13> Port 2, Data Input D13. Rev. A | Page 13 of 56 P1D<8> AVDD33 P1D<7> AGND P1D<6> AVDD33 P1D<5> AGND P1D<4> AVDD33 P1D<3> AGND DGND AGND DVDD18 OUT1_P P1D<2> OUT1_N P1D<1> AGND P1D<0> AUX1_P DATACLK AUX1_N DVDD33 AGND TXENABLE AUX2_N P2D<15> AUX2_P P2D<14> AGND P2D<13> OUT2_N DVDD18 OUT2_P DGND AGND P2D<12> AGND P2D<11> AVDD33 P2D<10> AGND P2D<9> AVDD33 P2D<8> AGND P2D<7> AVDD33 05361-004 AD9776/AD9778/AD9779 Pin Pin No. Mnemonic Description No. Mnemonic Description 43 DVDD18 1.8 V Digital Supply. 74 VREF Voltage Reference Output. 44 DGND Digital Common. 75 I120 120 μA Reference Current. 45 P2D<12> Port 2, Data Input D12. 76 AVDD33 3.3 V Analog Supply. 46 P2D<11> Port 2, Data Input D11. 77 AGND Analog Common. 47 P2D<10> Port 2, Data Input D10. 78 AVDD33 3.3 V Analog Supply. 48 P2D<9> Port 2, Data Input D9. 79 AGND Analog Common. 49 P2D<8> Port 2, Data Input D8. 80 AVDD33 3.3 V Analog Supply. 50 P2D<7> Port 2, Data Input D7. 81 AGND Analog Common. 51 P2D<6> Port 2, Data Input D6. 82 AGND Analog Common. 52 P2D<5> Port 2, Data Input D5. 83 OUT2_P Differential DAC Current Output, Channel 2. 53 DVDD18 1.8 V Digital Supply. 84 OUT2_N Differential DAC Current Output, 54 DGND Digital Common. Channel 2. 55 P2D<4> Port 2, Data Input D4. 85 AGND Analog Common. 56 P2D<3> Port 2, Data Input D3. 86 AUX2_P Auxiliary DAC Current Output, Channel 2. 57 P2D<2> Port 2, Data Input D2. 87 AUX2_N Auxiliary DAC Current Output, Channel 2. 58 P2D<1> Port 2, Data Input D1. 88 AGND Analog Common. 59 P2D<0> Port 2, Data Input D0 (LSB). 89 AUX1_N Auxiliary DAC Current Output, Channel 1. 60 DVDD18 1.8 V Digital Supply. 90 AUX1_P Auxiliary DAC Current Output, Channel 1. 61 DVDD33 3.3 V Digital Supply. 91 AGND Analog Common. 62 SYNC_O− Differential Synchronization Output. 92 OUT1_N Differential DAC Current Output, 63 SYNC_O+ Differential Synchronization Output. Channel 1. 64 DGND Digital Common. 93 OUT1_P Differential DAC Current Output, 65 PLL_LOCK PLL Lock Indicator. Channel 1. 66 SPI_SDO SPI Port Data Output. 94 AGND Analog Common. 67 SPI_SDIO SPI Port Data Input/Output. 95 AGND Analog Common. 68 SCLK SPI Port Clock. 96 AVDD33 3.3 V Analog Supply. 69 SPI_CSB SPI Port Chip Select Bar. 97 AGND Analog Common. 70 RESET Reset, Active High. 98 AVDD33 3.3 V Analog Supply. 71 IRQ Interrupt Request. 99 AGND Analog Common. 72 AGND Analog Common. 100 AVDD33 3.3 V Analog Supply. 73 IPTAT Factory Test Pin. Output current is 1 proportional to absolute temperature, The combined differential clock input at the CLK+ and CLK– pins are referred to as REFCLK. approximately 10 μA at 25°C with approximately 20 nA/°C slope. This pin should remain floating. Rev. A | Page 14 of 56 AD9776/AD9778/AD9779 TYPICAL PERFORMANCE CHARACTERISTICS 4 100 3 f = 160MSPS DATA 2 90 f = 200MSPS DATA 1 0 80 –1 –2 70 f = 250MSPS DATA –3 –4 60 –5 –6 50 0 10k 20k 30k 40k 50k 60k 0 20 40 60 80 100 CODE f (MHz) OUT Figure 6. AD9779 Typical INL Figure 9. AD9779 In-Band SFDR vs. f , 2× Interpolation OUT 100 1.5 f = 100MSPS f = 200MSPS DATA DATA 1.0 90 0.5 80 0 f = 150MSPS DATA –0.5 70 –1.0 60 –1.5 50 –2.0 0 20 40 60 80 100 0 10k 20k 30k 40k 50k 60k f (MHz) CODE OUT Figure 10. AD9779 In-Band SFDR vs. f , 4× Interpolation Figure 7. AD9779 Typical DNL OUT 100 100 f = 100MSPS f = 50MSPS DATA DATA 90 f = 160MSPS 90 DATA f = 250MSPS DATA 80 80 f = 125MSPS DATA f = 200MSPS DATA 70 70 60 60 50 50 0 20 40 60 80 100 0 10 20 30 40 50 f (MHz) f (MHz) OUT OUT Figure 8. AD9779 In-Band SFDR vs. f , 1x Interpolation OUT Figure 11. AD9779 In-Band SFDR vs. fOUT, 8× Interpolation Rev. A | Page 15 of 56 INL (16-BIT LSB) SFDR (dBc) DNL (16-BIT LSB) 05361-007 05361-006 05361-005 SFDR (dBc) SFDR (dBc) SFDR (dBc) 05361-010 05361-009 05361-008 AD9776/AD9778/AD9779 100 100 90 90 PLL OFF f = 160MSPS DATA PLL ON 80 80 f = 200MSPS DATA 70 70 f = 250MSPS 60 DATA 60 50 50 0 20 40 60 80 100 04 10 20 300 f (MHz) f (MHz) OUT OUT Figure 12. AD9779 Out-of-Band SFDR vs. fOUT, 2× Interpolation Figure 15. AD9779 In-Band SFDR, 4× Interpolation, fDATA = 100 MSPS, PLL On/Off 100 100 0dBFS –3dBFS 90 90 80 80 f = 150MSPS –6dBFS DATA 70 70 f = 100MSPS DATA 60 60 f = 200MSPS DATA 50 50 0 20 40 60 80 100 08 20 40 600 f (MHz) f (MHz) OUT OUT Figure 13. AD9779 Out-of-Band SFDR vs. fOUT, 4× Interpolation Figure 16. AD9779 In-Band SFDR vs. Digital Full-Scale Input 100 100 10mA 90 90 20mA 80 f = 50MSPS DATA 80 f = 100MSPS DATA 70 70 30mA 60 f = 125MSPS 60 DATA 50 50 0 10 20 30 40 50 08 20 40 600 f (MHz) f (MHz) OUT OUT Figure 14. AD9779 Out-of-Band SFDR vs. f , 8× Interpolation OUT Figure 17. AD9779 In-Band SFDR vs. Output Full-Scale Current Rev. A | Page 16 of 56 SFDR (dBc) SFDR (dBc) SFDR (dBc) 05361-013 05361-012 05361-011 SFDR (dBc) SFDR (dBc) SFDR (dBc) 05361-016 05361-015 05361-014 AD9776/AD9778/AD9779 100 100 f = 160MSPS DATA f = 200MSPS DATA 90 90 f = 250MSPS 80 80 DATA f = 75MSPS DATA 70 70 f = 100MSPS DATA f = 50MSPS 60 60 DATA f = 125MSPS DATA 50 50 0 20 40 60 80 100 120 f (MHz) OUT f (MHz) OUT Figure 18. AD9779 Third-Order IMD vs. f , 1× Interpolation Figure 21. AD9779 Third-Order IMD vs. f , 8× Interpolation OUT OUT 100 100 f = 160MSPS DATA 90 90 80 80 PLL OFF f = 200MSPS DATA 70 70 PLL ON 60 f = 250MSPS 60 DATA 50 50 0 20 40 60 80 100 120 140 160 180 200 220 0 20 40 60 80 100 120 140 160 180 200 f (MHz) f (MHz) OUT OUT Figure 19. AD9779 Third-Order IMD vs. fOUT, 2× Interpolation Figure 22. AD9779 Third-Order IMD vs. fOUT, 4× Interpolation, fDATA = 100 MSPS, PLL On vs. PLL Off 100 100 95 90 90 85 80 80 f = 150MSPS DATA 75 70 70 f = 100MSPS DATA 65 60 60 f = 200MSPS DATA 55 50 50 0 40 80 120 160 200 240 280 320 360 400 0 40 80 120 160 200 240 280 320 360 400 f (MHz) f (MHz) OUT OUT Figure 20. AD9779 Third-Order IMD vs. f , 4× Interpolation Figure 23. AD9779 Third-Order IMD vs. f , over 50 Parts,4× Interpolation, OUT OUT f = 200 MSPS DATA Rev. A | Page 17 of 56 IMD (dBc) IMD (dBc) IMD (dBc) 05361-018 05361-019 05361-017 IMD (dBc) IMD (dBc) IMD (dBc) 0 25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400 425 450 05361-020 05361-022 05361-021 AD9776/AD9778/AD9779 100 REF 0dBm *ATTEN 20dB *PEAK 95 Log 10dB/ EXT REF 90 DC COUPLED 0dBFS 85 –3dBFS 80 75 –6dBFS LGAV 51 70 W1 S2 S3 FC 65 AA £(f): 60 FTUN SWP 55 50 0 40 80 120 160 200 240 280 320 360 400 START 1.0MHz STOP 400.0MHz f (MHz) OUT *RES BW 20kHz VBW 20kHz SWEEP 1.203s (601 pts) Figure 27. AD9779 Two-Tone Spectrum, 4× Interpolation, Figure 24. IMD Performance vs. Digital Full-Scale Input, 4× Interpolation, f = 100 MSPS, f = 30 MHz, 35 MHz fDATA = 200 MSPS DATA OUT 100 –142 95 90 –146 20mA 85 –150 10mA 80 –3dBFS –154 75 0dBFS 30mA 70 –158 65 –6dBFS –162 60 –166 55 50 –170 0 40 80 120 160 200 240 280 320 360 400 0 20 40 60 80 f (MHz) f (MHz) OUT OUT Figure 25. IMD Performance vs. Full-Scale Output Current, 4× Interpolation, Figure 28. AD9779 Noise Spectral Density vs. Digital Full-Scale of Single-Tone f = 200 MSPS Input, fDATA = 200 MSPS, 2× Interpolation DATA REF 0dBm *ATTEN 20dB –150 *PEAK Log 10dB/ EXT REF –154 DC COUPLED f = 400MSPS DAC –158 f = 200MSPS DAC LGAV 51 –162 W1 S2 f = 800MSPS DAC FC S3 AA £(f): –166 FTUN SWP –170 0 20 40 60 80 100 START 1.0MHz STOP 400.0MHz f (MHz) OUT *RES BW 20kHz VBW 20kHz SWEEP 1.203s (601 pts) Figure 29. AD9779 Noise Spectral Density vs. f , Eight-Tone Input DAC Figure 26. AD9779 Single Tone, 4× Interpolation, f = 100 MSPS, DATA with 500 kHz Spacing, f = 200 MSPS DATA f = 30 MHz OUT Rev. A | Page 18 of 56 IMD (dBc) IMD (dBc) 05361-118 05361-117 05361-023 NSD (dBm/Hz) NSD (dBm/Hz) 05361-025 05361-026 05361-024 AD9776/AD9778/AD9779 –150 –55 –60 –154 –65 f = 200MSPS DAC –158 –70 f = 400MSPS DAC 0dBFS – PLL ON –75 –162 –6dBFS f = 800MSPS DAC –80 –3dBFS –166 –85 0dBFS –170 –90 0 20 40 60 80 100 0 20 40 60 80 100 120 140 160 180 200 220 240 260 f (MHz) f (MHz) OUT OUT Figure 30. AD9779 Noise Spectral Density vs. fDAC, Figure 32. AD9779 ACLR for Second Adjacent Band WCDMA, 4× Single-Tone Input at −6 dBFS Interpolation, fDATA = 122.88 MSPS. On-Chip Modulation Translates Baseband Signal to IF –55 –55 –60 –60 0dBFS – PLL ON –65 –65 –3dBFS –70 –70 0dBFS 0dBFS – PLL ON –75 –75 –6dBFS –6dBFS –80 –80 –3dBFS –85 –85 0dBFS –90 –90 0 20 40 60 80 100 120 140 160 180 200 220 240 260 0 20 40 60 80 100 120 140 160 180 200 220 240 260 f (MHz) f (MHz) OUT OUT Figure 31. AD9779 ACLR for First Adjacent Band WCDMA, 4× Interpolation, Figure 33. AD9779 ACLR for Third Adjacent Band WCDMA, 4× Interpolation, f = 122.88 MSPS, On-Chip Modulation Translates Baseband Signal to IF f = 122.88 MSPS, On-Chip Modulation Translates Baseband Signal to IF DATA DATA Rev. A | Page 19 of 56 ACLR (dBc) NSD (dBm/Hz) 05361-028 05361-027 ACLR (dBc) ACLR (dBc) 05361-030 05361-029 AD9776/AD9778/AD9779 REF –25.28dBm *ATTEN 4dB 1.5 *AVG Log 10dB/ 1.0 EXT REF 0.5 0 –0.5 –1.0 PAVG 10 W1 S2 –1.5 0 2k 4k 6k 8k 10k CENTER 143.88MHz SPAN 50MHz CODE *RES BW 30kHz VBW 300kHz SWEEP 162.2ms (601 pts) LOWER UPPER RMS RESULTS FREQ OFFSET REF BW dBc dBm dBc dBm CARRIER POWER 5.000MHz 3.840MHz –76.75 –89.23 –77.42 –89.91 –12.49dBm/ 10.00MHz 3.840MHz –80.94 –93.43 –80.47 –92.96 3.84000MHz 15.00MHz 3.840MHz –79.95 –92.44 –78.96 –91.45 Figure 34. AD9779 WCDMA Signal, 4× Interpolation, Figure 36. AD9778 Typical INL fDATA =122.88 MSPS, fDAC/4 Modulation 0.6 REF –30.28dBm *ATTEN 4dB *AVG Log 0.4 10dB/ 0.2 EXT REF 0 –0.2 –0.4 –0.6 –0.8 PAVG 10 –1.0 W1 S2 0 2k 4k 6k 8k 10k 12k 14k 16k CENTER 151.38MHz SPAN 50MHz CODE *RES BW 30kHz VBW 300kHz SWEEP 162.2ms (601 pts) TOTAL CARRIER POWER –12.61dBm/15.3600MHz REF CARRIER POWER –17.87dBm/3.84000MHz LOWER UPPER FREQ OFFSET INTEG BW dBc dBm dBc dBm 1 –17.87dBm 5.000MHz 3.840MHz –67.70 –85.57 –67.70 –85.57 2 –20.65dBm 10.00MHz 3.840MHz –70.00 –97.87 –69.32 –87.19 3 –18.26dBm 15.00MHz 3.840MHz –71.65 –99.52 –71.00 –88.88 4 –18.23dBm Figure 35. AD9779 Multicarrier WCDMA Signal, 4× Interpolation, Figure 37. AD9778 Typical DNL f =122.88 MSPS, f /4 Modulation DAC DAC Rev. A | Page 20 of 56 05361-032 05361-031 INL (14-BIT LSB) DNL (14-BIT LSB) 05361-034 05361-033 AD9776/AD9778/AD9779 REF –25.39dBm *ATTEN 4dB *AVG 100 Log 10dB/ 90 4× 150MSPS 80 4× 200MSPS 70 4× 100MSPS PAVG 60 10 W1 S2 CENTER 143.88MHz SPAN 50MHz *RES BW 30kHz VBW 300kHz SWEEP 162.2ms (601 pts) 50 0 40 80 120 160 200 240 280 320 360 400 LOWER UPPER RMS RESULTS FREQ OFFSET REF BW dBc dBm dBc dBm f (MHz) OUT CARRIER POWER 5.000MHz 3.884MHz –76.49 –89.23 –76.89 –89.63 –12.74dBm/ 10.00MHz 3.840MHz –80.13 –92.87 –80.02 –92.76 3.84000MHz 15.00MHz 3.840MHz –80.90 –93.64 –79.53 –92.27 Figure 38. AD9778 IMD, 4× Interpolation Figure 41. AD9778 ACLR, fDATA = 122.88 MSPS, 4× Interpolation, fDAC/4 Modulation 100 –150 90 –154 f = 200MSPS DATA f = 160MSPS DATA f = 200MSPS DAC 80 –158 f = 400MSPS DAC f = 250MSPS DATA 70 –162 f = 800MSPS DAC 60 –166 50 –170 0 20 40 60 80 100 0 20 40 60 80 100 f (MHz) f (MHz) OUT OUT Figure 39. AD9778 In-Band SFDR, 2× Interpolation Figure 42. AD9778 Noise Spectral Density vs. f Eight-Tone Input DAC with 500 kHz Spacing, f = 200 MSPS DATA –150 –60 –154 f = 200MSPS DAC f = 400MSPS –158 DAC –70 1ST ADJ CHAN 3RD ADJ CHAN –162 f = 800MSPS –80 DAC –166 2ND ADJ CHAN –90 –170 0 25 50 75 100 125 150 175 200 225 250 0 20 40 60 80 100 f (MHz) OUT f (MHz) OUT Figure 40. AD9778 ACLR, Single-Carrier WCDMA, 4× Interpolation, Figure 43. AD9778 Noise Spectral Density vs. fDAC Single-Tone Input f = 122.88 MSPS, Amplitude = −3 dBFS DATA at −6 dBFS, fDATA = 200 MSPS Rev. A | Page 21 of 56 ACLR (dBc) SFDR (dBc) IMD (dBc) 05361-037 05361-036 05361-035 NSD (dBm/Hz) NSD (dBm/Hz) 05361-040 05361-039 05361-038 AD9776/AD9778/AD9779 0.4 100 0.3 90 0.2 f = 160MSPS DATA 0.1 80 0 f = 250MSPS DATA 70 –0.1 f = 200MSPS DATA –0.2 60 –0.3 –0.4 50 0 512 1024 1536 2048 2560 3072 3584 4096 0 20 40 60 80 100 CODE f (MHz) OUT Figure 44. AD9776 Typical INL Figure 47. AD9776 In-Band SFDR, 2× Interpolation 0.20 –55 0.15 –60 0.10 –65 1ST ADJ CHAN 0.05 –70 3RD ADJ CHAN 0 –75 –0.05 –80 –0.10 2ND ADJ CHAN –85 –0.15 –90 –0.20 0 512 1024 1536 2048 2560 3072 3584 4096 0 25 50 75 100 125 150 175 200 225 250 CODE F (MHz) OUT Figure 45. AD9776 Typical DNL Figure 48. AD9776 ACLR, fDATA = 122.88 MSPS, 4× Interpolation, fDAC/4 Modulation REF –25.29dBm *ATTEN 4dB *AVG 100 Log 10dB/ 95 90 85 80 75 4× 100MSPS 4× 200MSPS 70 65 60 PAVG 10 55 4× 150MSPS W1 S2 50 CENTER 143.88MHz SPAN 50MHz 0 40 80 120 160 200 240 280 320 360 400 *RES BW 30kHz VBW 300kHz SWEEP 162.2ms (601 pts) f (MHz) LOWER UPPER OUT RMS RESULTS FREQ OFFSET REF BW dBc dBm dBc dBm CARRIER POWER 5.000MHz 3.884MHz –75.00 –87.67 –75.30 –87.97 –12.67dBm/ 10.00MHz 3.840MHz –78.05 –90.73 –77.99 –90.66 3.84000MHz 15.00MHz 3.840MHz –77.73 –90.41 –77.50 –90.17 Figure 46. AD9776 IMD, 4× Interpolation Figure 49. AD9776, Single Carrier WCDMA, 4× Interpolation, f = 122.88 MSPS, Amplitude = −3 dBFS DATA Rev. A | Page 22 of 56 DNL (12-BIT LSB) INL (12-BIT LSB) IMD (dBc) 05361-043 05361-042 05361-041 ACLR (dBc) SFDR (dBc) 05361-045 05361-044 05361-046 AD9776/AD9778/AD9779 –150 –150 f = 200MSPS DAC f = 200MSPS DAC –154 f = 400MSPS –154 DAC f = 400MSPS DAC –158 –158 f = 800MSPS DAC f = 800MSPS DAC –162 –162 –166 –166 –170 0 10 20 30 40 50 60 70 80 90 100 –170 f (MHz) OUT 0 10 20 30 40 50 60 70 80 90 100 f (MHz) OUT Figure 50. AD9776 Noise Spectral Density vs. f , Eight-Tone Input Figure 51. AD9776 Noise Spectral Density vs. f , DAC DAC with 500 kHz Spacing, f = 200 MSPS Single-Tone Input at −6 dBFS, f = 200 MSPS DATA DATA Rev. A | Page 23 of 56 NSD (dBm/Hz) 05361-047 NSD (dBm/Hz) 05361-048 AD9776/AD9778/AD9779 TERMINOLOGY Integral Nonlinearity (INL) In-Band Spurious Free Dynamic Range (SFDR) The difference, in decibels, between the peak amplitude of the INL is defined as the maximum deviation of the actual analog output signal and the peak spurious signal between dc and the output from the ideal output, determined by a straight line frequency equal to half the input data rate. drawn from zero scale to full scale. Out-of-Band Spurious Free Dynamic Range (SFDR) Differential Nonlinearity (DNL) The difference, in decibels, between the peak amplitude of the DNL is the measure of the variation in analog value, normalized output signal and the peak spurious signal within the band that to full scale, associated with a 1 LSB change in digital input code. starts at the frequency of the input data rate and ends at the Monotonicity Nyquist frequency of the DAC output sample rate. Normally, A DAC is monotonic if the output either increases or remains energy in this band is rejected by the interpolation filters. This constant as the digital input increases. specification, therefore, defines how well the interpolation filters work and the effect of other parasitic coupling paths to Offset Error the DAC output. The deviation of the output current from the ideal of zero is called offset error. For I , 0 mA output is expected when the Total Harmonic Distortion (THD) OUTA inputs are all 0s. For I , 0 mA output is expected when all THD is the ratio of the rms sum of the first six harmonic com- OUTBB inputs are set to 1. ponents to the rms value of the measured fundamental. It is expressed as a percentage or in decibels. Gain Error The difference between the actual and ideal output span. The Signal-to-Noise Ratio (SNR) actual span is determined by the difference between the output SNR is the ratio of the rms value of the measured output signal when all inputs are set to 1 and the output when all inputs are to the rms sum of all other spectral components below the set to 0. Nyquist frequency, excluding the first six harmonics and dc. The value for SNR is expressed in decibels. Output Compliance Range The range of allowable voltage at the output of a current-output Interpolation Filter DAC. Operation beyond the maximum compliance limits can If the digital inputs to the DAC are sampled at a multiple rate of cause either output stage saturation or breakdown, resulting in fDATA (interpolation rate), a digital filter can be constructed that nonlinear performance. has a sharp transition band near fDATA/2. Images that typically appear around fDAC (output data rate) can be greatly suppressed. Temperature Drift Temperature drift is specified as the maximum change from the Adjacent Channel Leakage Ratio (ACLR) ambient (25°C) value to the value at either T or T . For The ratio in dBc between the measured power within a channel MIN MAX offset and gain drift, the drift is reported in ppm of full-scale relative to its adjacent channel. range (FSR) per degree Celsius. For reference drift, the drift is Complex Image Rejection reported in ppm per degree Celsius. In a traditional two-part upconversion, two images are created Power Supply Rejection (PSR) around the second IF frequency. These images have the effect of The maximum change in the full-scale output as the supplies wasting transmitter power and system bandwidth. By placing are varied from minimum to maximum specified voltages. the real part of a second complex modulator in series with the first complex modulator, either the upper or lower frequency Settling Time image near the second IF can be rejected. The time required for the output to reach and remain within a specified error band around its final value, measured from the start of the output transition. Rev. A | Page 24 of 56 AD9776/AD9778/AD9779 THEORY OF OPERATION ported, as well as MSB-first or LSB-first transfer formats. The The AD9776/AD9778/AD9779 combine many features that serial interface ports can be configured as a single pin I/O (SDIO) make them very attractive DACs for wired and wireless or two unidirectional pins for input/output (SDIO/SDO). communications systems. The dual digital signal path and dual DAC structure allow an easy interface with common General Operation of the Serial Interface quadrature modulators when designing single sideband There are two phases to a communication cycle with the transmitters. The speed and performance of the parts allow AD977x. Phase 1 is the instruction cycle (the writing of an wider bandwidths and more carriers to be synthesized than instruction byte into the device), coincident with the first eight in previously available DACs. The digital engine uses a break- SCLK rising edges. The instruction byte provides the serial port through filter architecture that combines the interpolation with controller with information regarding the data transfer cycle, a digital quadrature modulator. This allows the parts to conduct Phase 2 of the communication cycle. The Phase 1 instruction digital quadrature frequency upconversion. They also have byte defines whether the upcoming data transfer is a read or features that allow simplified synchronization with incoming write, the number of bytes in the data transfer, and the starting data and between multiple parts. register address for the first byte of the data transfer. The first eight SCLK rising edges of each communication cycle are used The serial port configuration is controlled by Register 0x00, to write the instruction byte into the device. Bits<6:7>. It is important to note that the configuration changes immediately upon writing to the last bit of the byte. For multi- A logic high on the CSB pin followed by a logic low resets the byte transfers, writing to this register can occur during the SPI port timing to the initial state of the instruction cycle. middle of a communication cycle. Care must be taken to From this state, the next eight rising SCLK edges represent the compensate for this new configuration for the remaining bytes instruction bits of the current I/O operation, regardless of the of the current communication cycle. state of the internal registers or the other signal levels at the inputs to the SPI port. If the SPI port is in an instruction cycle The same considerations apply to setting the software reset, or a data transfer cycle, none of the present data is written. RESET (Register 0x00, Bit 5) or pulling the RESET pin (Pin 70) high. All registers are set to their default values, except The remaining SCLK edges are for Phase 2 of the communica- Register 0x00 and Register 0x04, which remain unchanged. tion cycle. Phase 2 is the actual data transfer between the device and the system controller. Phase 2 of the communication cycle Use of only single-byte transfers when changing serial port is a transfer of one, two, three, or four data bytes as determined configurations or initiating a software reset is recommended to by the instruction byte. Using one multibyte transfer is preferred. prevent unexpected device behavior. Single-byte data transfers are useful in reducing CPU overhead As described in this section, all serial port data is transferred when register access requires only one byte. Registers change to/from the device in synchronization to the SCLK pin. If immediately upon writing to the last bit of each transfer byte. synchronization is lost, the device has the ability to asynchro- Instruction Byte nously terminate an I/O operation, putting the serial port controller into a known state and, thereby, regaining The instruction byte contains the information shown in synchronization. Table 9. Table 9. SPI Instruction Byte SERIAL PERIPHERAL INTERFACE MSB LSB SPI_SDO 66 I7 I6 I5 I4 I3 I2 I1 I0 SPI R/W N1 N0 A4 A3 A2 A1 A0 67 SPI_SDI PORT 68 SPI_SCLK R/W, Bit 7 of the instruction byte, determines whether a read or 69 SPI_CSB a write data transfer occurs after the instruction byte write. Logic high indicates a read operation. Logic 0 indicates a write Figure 52. SPI Port operation. The serial port is a flexible, synchronous serial communications N1 and N0, Bit 6 and Bit 5 of the instruction byte, determine port allowing easy interface to many industry-standard micro- the number of bytes to be transferred during the data transfer controllers and microprocessors. The serial I/O is compatible cycle. The bit decodes are listed in Table 10. with most synchronous transfer formats, including both the A4, A3, A2, A1, and A0—Bit 4, Bit 3, Bit 2, Bit 1, and Bit 0, respec- Motorola SPI® and Intel® SSR protocols. The interface allows tively, of the instruction byte determine the register that is accessed read/write access to all registers that configure the AD9776/ during the data transfer portion of the communication cycle. AD9778/AD9779. Single or multiple byte transfers are sup- Rev. A | Page 25 of 56 05361-049 AD9776/AD9778/AD9779 For multibyte transfers, this address is the starting byte address. When LSB-first = 1 (LSB-first) the instruction and data bit The remaining register addresses are generated by the device must be written from LSB to MSB. Multibyte data transfers in based on the LSB-first bit (Register 0x00, Bit 6). LSB-first format start with an instruction byte that includes the register address of the least significant data byte followed by mul- Table 10. Byte Transfer Count tiple data bytes. The serial port internal byte address generator N1 N0 Description increments for each byte of the multibyte communication cycle. 0 0 Transfer one byte 0 1 Transfer three bytes The serial port controller data address decrements from the 1 0 Transfer two bytes data address written toward 0x00 for multibyte I/O operations if 1 1 Transfer four bytes the MSB-first mode is active. The serial port controller address increments from the data address written toward 0x1F for Serial Interface Port Pin Descriptions multibyte I/O operations if the LSB-first mode is active. Serial Clock (SCLK) INSTRUCTION CYCLE DATA TRANSFER CYCLE The serial clock pin synchronizes data to and from the device CSB and to run the internal state machines. The maximum frequency of SCLK is 40 MHz. All data input is registered on the rising SCLK edge of SCLK. All data is driven out on the falling edge of SCLK. R/W N1 N0 A4 A3 A2 A1 A0 D7 D6 D5 D3 D2 D1 D0 N N 0 0 0 0 SDIO Chip Select (CSB) Active low input starts and gates a communication cycle. It D7 D6 D5 D3 D2 D1 D0 SDO N N 0 0 0 0 allows more than one device to be used on the same serial Figure 53. Serial Register Interface Timing MSB-First communications lines. The SDO and SDIO pins go to a high impedance state when this input is high. Chip select should INSTRUCTION CYCLE DATA TRANSFER CYCLE stay low during the entire communication cycle. CSB Serial Data I/O (SDIO) SCLK Data is always written into the device on this pin. However, this pin can be used as a bidirectional data line. The configuration A0 A1 A2 A3 A4 N0 N1 R/W D0 D1 D2 D4 D5 D6 D7 0 0 0 N N N N SDIO of this pin is controlled by Register 0x00, Bit 7. The default is Logic 0, configuring the SDIO pin as unidirectional. D0 D1 D2 D4 D5 D6 D7 0 0 0 N N N N SDO Figure 54. Serial Register Interface Timing LSB-First Serial Data Out (SDO) Data is read from this pin for protocols that use separate lines t DS for transmitting and receiving data. In the case where the device t SCLK operates in a single bidirectional I/O mode, this pin does not CSB output data and is set to a high impedance state. t t PWH PWL MSB/LSB TRANSFERS SCLK t DS The serial port can support both MSB-first and LSB-first data t DH formats. This functionality is controlled by Register Bit LSB_FIRST INSTRUCTION BIT 7 INSTRUCTION BIT 6 SDIO (Register 0x00, Bit 6). The default is MSB-first (LSB-first = 0). Figure 55. Timing Diagram for SPI Register Write When LSB-first = 0 (MSB-first) the instruction and data bit CSB must be written from MSB to LSB. Multibyte data transfers in MSB-first format start with an instruction byte that includes the register address of the most significant data byte. Subsequent data SCLK bytes should follow from high address to low address. In MSB-first t DV mode, the serial port internal byte address generator decrements SDIO DATA BIT n DATA BIT n–1 SDO for each data byte of the multibyte communication cycle. Figure 56. Timing Diagram for SPI Register Read Rev. A | Page 26 of 56 05361-053 05361-052 05361-051 05361-050 AD9776/AD9778/AD9779 SPI REGISTER MAP Table 11. Register Name Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Def. Comm 0x00 00 SDIO LSB/MSB First Software Power- Auto PLL Lock 0x00 Bidirectional Reset Down Power- Indicator Mode Down (Read Enable Only) Digital 0x01 01 Filter Interpolation Factor<1:0> Filter Modulation Mode<3:0> Zero 0x00 Control Stuffing Enable 0x02 02 Data Format Dual/Interleaved Real Mode Data Inverse DATACLK TxEnable Q First 0x00 Data Bus Mode Clock Sinc Invert Invert Delay Enable Enable Sync 0x03 03 Data Clock Delay Mode<1:0> Data Clock Divide Reserved 0x00 Control Ratio<1:0> 0x04 04 Data Clock Delay<3:0> Output Sync Pulse Divide<2:0> Sync Out 0x00 Delay<4> 0x05 05 Sync Out Delay<3:0> Input Sync Pulse Frequency Ratio<2:0> Sync Input 0x00 Delay<4> 0x06 06 Sync Input Delay<3:0> Input Sync Pulse Timing Error Tolerance<3:0> 0x00 0x07 07 Sync Sync Driver Sync DAC Clock Offset<4:0> 0x00 Receiver Enable Triggering Enable Edge PLL 0x08 08 PLL Band Select<5:0> PLL VCO AGC 0xCF Control Gain<1:0> 0x09 09 PLL Enable PLL VCO Divider Ratio<1:0> PLL Loop PLL Bias Setting<2:0> 0x37 Divide Ratio<1:0> Misc 0x0A 10 PLL Control Voltage Range<2:0> (Read Only) PLL Loop Bandwidth Adjustment<4:0> 0x38 Control I DAC 0x0B 11 I DAC Gain Adjustment<7:0> 0xF9 Control 0x0C 12 I DAC Sleep I DAC Power I DAC Gain 0x01 Register Down Adjustment<9:8> Aux DAC1 0x0D 13 Auxiliary DAC1 Data<7:0> 0x00 Control 0x0E 14 Auxiliary Auxiliary DAC1 Auxiliary Auxiliary DAC1 0x00 Register DAC1 Sign Current Direction DAC1 Data<9:8> Power- Down Q DAC 0x0F 15 Q DAC Gain Adjustment<7:0> 0xF9 Control 0x10 16 Q DAC Sleep Q DAC Power- Q DAC Gain 0x01 Register Down Adjustment<9:8> Aux DAC2 0x11 17 Auxiliary DAC2 Data<7:0> 0x00 Control 0x12 18 Auxiliary Auxiliary DAC2 Auxiliary Auxiliary DAC2 0x00 Register DAC2 Sign Current Direction DAC2 Data<9:8> Power- Down 0x13 19 to 24 Reserved to 0x18 Interrupt 0x19 25 Sync Delay IRQ Sync Internal 0x00 Register Delay Sync IRQ Loopback Enable 0x1A 26 to 31 Reserved to 0x1F Rev. A | Page 27 of 56 AD9776/AD9778/AD9779 Table 12. SPI Register Description Address Register Name Reg. No. Bits Description Function Default Comm Register 00 7 SDIO bidirectional 0: use SDIO pin as input data only 0 1: use SDIO as both input and output data 00 6 LSB/MSB first 0: first bit of serial data is MSB of data byte 0 1: first bit of serial data is LSB of data byte 00 5 Software reset Bit must be written with a 1, then 0 to soft 0 reset SPI register map 00 4 Power-down mode 0: all circuitry is active 1: disable all digital and analog circuitry, only SPI port is active 00 3 Auto power-down enable Controls auto power-down mode, see the 0 Power-Down and Sleep Modes section 00 1 PLL lock (read only) 0: PLL is not locked 1: PLL is locked 0 Digital Control Register 01 7:6 Filter interpolation factor 00: 1× interpolation 00 01: 2× interpolation 10: 4× interpolation 11: 8× interpolation 01 5:2 Filter modulation mode See Table 21 for filter modes 0000 01 0 Zero stuffing 0: zero stuffing off 0 1: zero stuffing on 02 7 Data format 0: signed binary 0 1: unsigned binary 02 6 Dual/interleaved data bus mode 0: both input data ports receive data 0 1: Data Port 1 only receives data 02 5 Real mode 0: enable Q path for signal processing 0 1: disable Q path data (internal Q channel clocks disabled, I and Q modulators disabled) 02 4 DATACLK delay enable See the Using Data Delay to Meet Timing Requirements section. 02 3 Inverse sinc enable 0: inverse sinc filter disabled 0 1: inverse sinc filter enabled 02 2 DATACLK invert 0: output DATACLK same phase as internal 0 capture clock 1: output DATACLK opposite phase as internal capture clock 02 1 TxEnable invert Inverts the function of TxEnable Pin 39, see 0 the Interleaved Data Mode section 02 0 Q first 0: first byte of data is always I data at beginning of transmit 1: first byte of data is always Q data at beginning of transmit Sync Control Register 03 7:6 Data clock delay mode 00: manual 00 03 5:4 Extra data clock divide ratio Data clock output divider (see Table 22 for 00 divider ratio) 03 3:0 Reserved 000 04 7:4 Data clock delay Sets delay of REFCLK in to DATACLK out 0000 04 3:1 Output sync pulse divide Sets frequency of SYNC_O pulses 000 04 0 Sync out delay Sync output delay, Bit 4 05 7:4 Sync out delay Sync output delay, Bits<3:0> 0 05 3:1 Input sync pulse frequency Input sync pulse frequency divider, see the 000 AN-822 application note 05 0 Sync input delay Sync input delay, Bit 4 0 Rev. A | Page 28 of 56 AD9776/AD9778/AD9779 Address Register Name Reg. No. Bits Description Function Default Sync Control Register 06 7:4 Sync input delay See the Multiple DAC Synchronization 0 section for details on using these registers to synchronize multiple DACs 06 3:0 Input sync pulse timing error 0 tolerance 07 7 Sync receiver enable 0 07 6 Sync driver enable 0 07 5 Sync triggering edge 0 07 4:0 SYNC_I to input data sampling 0 clock offset PLL Control 08 7:2 PLL band select VCO frequency range vs. PLL band select 111001 value (see Table 18) 08 1:0 VCO AGC gain control Lower number (low gain) is generally better 11 for performance 09 7 PLL enable 0 0: PLL off, DAC rate clock supplied by outside source 1: PLL on, DAC rate clock synthesized internally from external reference clock via PLL clock multiplier 09 6:5 PLL VCO divide ratio FVCO/f DAC 00 × 1 01 × 2 10 × 4 11 × 8 09 4:3 PLL loop divide ratio f /f DAC REF 00 × 2 01 × 4 10 × 8 11 × 16 09 2:0 PLL bias setting Always set to 010 010 Misc Control 0A 7:5 PLL control voltage range 000 to 111, proportional to voltage at PLL loop filter output, readback only 0A 4:0 PLL loop bandwidth adjustment See PLL Loop Filter Bandwidth section for details I DAC Control Register 0B 7:0 I DAC gain adjustment (7:0) LSB slice of 10-bit gain setting word 11111001 for I DAC 0C 7 I DAC sleep 0: I DAC on 0 1: I DAC off 0C 6 I DAC power-down 0: I DAC on 0 1: I DAC off 0C 1:0 I DAC gain adjustment (9:8) MSB slice of 10-bit gain setting word 01 for I DAC Aux DAC1 Control 0D 7:0 Aux DAC1 gain adjustment (7:0) LSB slice of 10-bit gain setting word for 00000000 Register Aux DAC1 0E 7 Aux DAC1 sign 0: positive 1: negative 0E 6 Aux DAC1 current direction 0: source 0 1: sink 0E 5 Aux DAC1 power-down 0: Aux DAC1 on 0 1: Aux DAC1 off 0E 1:0 Aux DAC1 gain adjustment (9:8) MSB slice of 10-bit gain setting word 00 for Aux DAC1 Rev. A | Page 29 of 56 AD9776/AD9778/AD9779 Address Register Name Reg. No. Bits Description Function Default Q DAC Control Register 0F 7:0 Q DAC gain adjustment (7:0) LSB slice of 10-bit gain setting word for 11111001 Q DAC 10 7 Q DAC sleep 0: Q DAC on 0 1: Q DAC off 10 6 Q DAC power-down 0: Q DAC on 0 1: Q DAC off 10 1:0 Q DAC gain adjustment (9:8) MSB slice of 10-bit gain setting word for Q DAC Aux DAC2 Control 11 7:0 Aux DAC2 gain adjustment (7:0) LSB slice of 10-bit gain setting word for 00000000 Register Aux DAC2 12 7 Aux DAC2 sign 0: positive 1: negative 12 6 Aux DAC2 current direction 0: source 0 1: sink 12 5 Aux DAC2 power-down 0: Aux DAC2 on 0 1: Aux DAC2 off 12 1:0 Aux DAC2 gain adjustment (9:8) MSB slice of 10-bit gain setting word 00 for Aux DAC2 Interrupt Register 19 7 0 19 6 Sync delay IRQ Readback, must write 0 to clear 0 19 5 0 19 3 0 19 2 Sync delay IRQ enable 0 19 1 0 19 0 Internal sync loopback 0 Rev. A | Page 30 of 56 AD9776/AD9778/AD9779 INTERPOLATION FILTER ARCHITECTURE Table 15. Half-Band Filter 3 The AD9776/AD9778/AD9779 can provide up to 8× interpola- Lower Coefficient Upper Coefficient Integer Value tion, or the interpolation filters can be entirely disabled. It is H(1) H(15) −39 important to note that the input signal should be backed off by H(2) H(14) 0 approximately 0.01 dB from full scale to avoid overflowing the H(3) H(13) +273 interpolation filters. The coefficients of the low-pass filters and H(4) H(12) 0 the inverse sinc filter are given in Table 13, Table 14, Table 15, H(5) H(11) −1102 and Table 16. Spectral plots for the filter responses are shown in H(6) H(10) 0 Figure 57, Figure 58, and Figure 59. H(7) H(9) +4964 Table 13. Half-Band Filter 1 H(8) +8192 Lower Coefficient Upper Coefficient Integer Value H(1) H(55) −4 Table 16. Inverse Sinc Filter H(2) H(54) 0 Lower Coefficient Upper Coefficient Integer Value H(3) H(53) +13 H(1) H(9) +2 H(4) H(52) 0 H(2) H(8) −4 H(5) H(51) −34 H(3) H(7) +10 H(6) H(50) 0 H(4) H(6) −35 H(7) H(49) +72 H(5) +401 H(8) H(48) 0 H(9) H(47) −138 10 H(10) H(46) 0 0 H(11) H(45) +245 –10 H(12) H(44) 0 –20 H(13) H(43) −408 –30 H(14) H(42) 0 –40 H(15) H(41) +650 –50 H(16) H(40) 0 –60 H(17) H(39) −1003 –70 H(18) H(38) 0 H(19) H(37) +1521 –80 H(20) H(36) 0 –90 H(21) H(35) −2315 –100 –4 –3 –2 –1 0123 4 H(22) H(34) 0 f (× Input Data Rate) OUT H(23) H(33) +3671 Figure 57. 2× Interpolation, Low-Pass Response to ±4× Input Data Rate H(24) H(32) 0 (Dotted Lines Indicate 1 dB Roll-Off) H(25) H(31) −6642 H(26) H(30) 0 10 H(27) H(29) +20,755 0 H(28) +32,768 –10 –20 Table 14. Half-Band Filter 2 –30 Lower Coefficient Upper Coefficient Integer Value –40 H(1) H(23) −2 –50 H(2) H(22) 0 –60 H(3) H(21) +17 –70 H(4) H(20) 0 H(5) H(19) −75 –80 H(6) H(18) 0 –90 H(7) H(17) +238 –100 –4 –3 –2 –1 0123 4 H(8) H(16) 0 f (× Input Data Rate) OUT H(9) H(15) −660 Figure 58. 4× Interpolation, Low-Pass Response to ±4× Input Data Rate H(10) H(14) 0 (Dotted Lines Indicate 1 dB Roll-Off) H(11) H(13) +2530 H(12) +4096 Rev. A | Page 31 of 56 ATTENUATION (dB) ATTENUATION (dB) 05361-055 05361-054 AD9776/AD9778/AD9779 10 10 0 0 –10 –10 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 –100 –4 –3 –2 –1 0123 4 –4 –3 –2 –1 0123 4 f (× Input Data Rate) f (× Input Data Rate) OUT OUT Figure 59. 8× Interpolation, Low-Pass Response to ±4× Input Data Rate Figure 62. Interpolation/Modulation Combination of −3 fDAC/8 Filter (Dotted Lines Indicate 1 dB Roll-Off) 10 With the interpolation filter and modulator combined, the 0 incoming signal can be placed anywhere within the Nyquist –10 region of the DAC output sample rate. When the input signal is –20 complex, this architecture allows modulation of the input signal –30 to positive or negative Nyquist regions (see Table 17). –40 –50 The Nyquist regions of up to 4× the input data rate can be seen –60 in Figure 60. –70 –8 –7 –6 –5 –4 –3 –2 –1 1 2 3 4 5 6 7 8 –80 –90 –4× –3× –2× –1× DC 1× 2× 3× 4× –100 –4 –3 –2 –1 0123 4 Figure 60. Nyquist Zones f (× Input Data Rate) OUT Figure 57, Figure 58, and Figure 59 show the low-pass response Figure 63. Interpolation/Modulation Combination of −2 fDAC/8 Filter of the digital filters with no modulation. By turning on the 10 modulation feature, the response of the digital filters can be 0 tuned to anywhere within the DAC bandwidth. As an example, –10 Figure 61 to Figure 67 show the nonshifted mode filter responses –20 (refer to Table 17 for shifted/nonshifted mode filter responses). –30 10 –40 0 –50 –10 –60 –20 –70 –30 –80 –40 –90 –50 –100 –60 –4 –3 –2 –1 0123 4 f (× Input Data Rate) –70 OUT –80 Figure 64. Interpolation/Modulation Combination of −1 f /8 Filter DAC –90 –100 –4 –3 –2 –1 0123 4 f (× Input Data Rate) OUT Figure 61. Interpolation/Modulation Combination of 4 f /8 Filter DAC Rev. A | Page 32 of 56 ATTENUATION (dB) ATTENUATION (dB) 05361-057 05361-058 05361-056 ATTENUATION (dB) ATTENUATION (dB) ATTENUATION (dB) 05361-061 05361-060 05361-059 AD9776/AD9778/AD9779 10 Shifted mode filter responses allow the pass band to be centered 0 around ±0.5 f , ±1.5 f , ±2.5 f , and ±3.5 f . Switching DATA DATA DATA DATA –10 to the shifted mode response does not modulate the signal. –20 Instead, the pass band is simply shifted. For example, picture –30 the response shown in Figure 67 and assume the signal in-band –40 is a complex signal over the bandwidth 3.2 fDATA to 3.3 fDATA. If –50 the even mode filter response is then selected, the pass band –60 becomes centered at 3.5 f . However, the signal remains at DATA the same place in the spectrum. The shifted mode capability –70 allows the filter pass band to be placed anywhere in the DAC –80 Nyquist bandwidth. –90 –100 The AD9776/AD9778/AD9779 are dual DACs with internal –4 –3 –2 –1 0123 4 f (× Input Data Rate) complex modulators built into the interpolating filter response. OUT In dual channel mode, the devices expect the real and the Figure 65. Interpolation/Modulation Combination of fDAC/8 Filter imaginary components of a complex signal at Digital Input 10 Port 1 and Digital Input Port 2 (I and Q, respectively). The DAC 0 outputs then represent the real and imaginary components of –10 the input signal, modulated by the complex carrier f /2, DAC –20 f /4, or f /8. DAC DAC –30 With Register 2, Bit 6 set, the device accepts interleaved data on –40 Port 1 in the I, Q, I, Q . . . sequence. Note that in interleaved –50 mode, the channel data rate at the beginning of the I and the Q –60 data paths are now half the input data rate because of the inter- –70 leaving. The maximum input data rate is still subject to the –80 maximum specification of the device. This limits the synthesis –90 bandwidth available at the input in interleaved mode. –100 –4 –3 –2 –1 0 1 2 3 4 With Register 0x02, Bit 5 (real mode) set, the Q channel and the f (× Input Data Rate) OUT internal I and Q digital modulation are turned off. The output Figure 66. Interpolation/Modulation Combination of spectrum at the I DAC then represents the signal at Digital 2 fDAC/8 Filter in Shifted Mode Input Port 1, interpolated by 1×, 2×, 4×, or 8×. 10 The general recommendation is that if the desired signal is 0 within ±0.4 × f , the odd filter mode should be used. Outside DATA –10 of this, the even filter mode should be used. In any situation, the –20 total bandwidth of the signal should be less than 0.8 × f . DATA –30 –40 –50 –60 –70 –80 –90 –100 –4 –3 –2 –1 0123 4 f (× Input Data Rate) OUT Figure 67. Interpolation/Modulation Combination of 3 fDAC/8 Filter in Shifted Mode Rev. A | Page 33 of 56 ATTENUATION (dB) ATTENUATION (dB) ATTENUATION (dB) 05361-064 05361-063 05361-062 AD9776/AD9778/AD9779 Table 17. Interpolation Filter Modes, (Register 0x01, Bits<5:2>) Nyquist Filter Zone Interpolation Mode Pass 1 1 1 Factor <7:6> <5:2> Modulation Band F_Low Center F_High Comments 8 0x00 DC 1 −0.05 0 +0.05 In 8× interpolation; BW (min) = 0.0375 × f DAC 8 0x01 DC shifted 2 0.0125 0.0625 0.1125 BW (max) = 0.1 × f DAC 8 0x02 F/8 3 0.075 0.125 0.175 8 0x03 F/8 shifted 4 0.1375 0.1875 0.2375 8 0x04 F/4 5 0.2 0.25 0.3 8 0x05 F/4 shifted 6 0.2625 0.3125 0.3625 8 0x06 3F/8 7 0.325 0.375 0.425 8 0x07 3F/8 shifted 8 0.3875 0.4375 0.4875 8 0x08 F/2 −8 −0.55 −0.5 −0.45 8 0x09 F/2 shifted −7 −0.4875 −0.4375 −0.3875 8 0x0A −3F/8 −6 −0.425 −0.375 −0.343 8 0x0B −3F/8 shifted −5 −0.3625 −0.3125 −0.2625 8 0x0C −F/4 −4 −0.3 −0.25 −0.2 8 0x0D −F/4 shifted −3 −0.2375 −0.1875 −0.1375 8 0x0E −F/8 −2 −0.175 −0.125 −0.075 8 0x0F −F/8 shifted −1 −0.1125 −0.0625 −0.0125 4 0x00 DC 1 −0.1 0 +0.1 In 4× interpolation; BW (min) = 0.075 × f DAC 4 0x01 DC shifted 2 0.025 0.125 0.225 BW (max) = 0.2 × fDAC 4 0x02 F/4 3 0.15 0.25 0.35 4 0x03 F/4 shifted 4 0.275 0.375 0.475 4 0x04 F/2 −4 −0.6 −0.5 −0.4 4 0x05 F/2 shifted −3 −0.475 −0.375 −0.275 4 0x06 −F/4 −2 −0.35 −0.25 −0.15 4 0x07 −F/4 shifted −1 −0.225 −0.125 −0.025 2 0x00 DC 1 −0.2 0 +0.2 In 2× interpolation; BW (min) = 0.15 × f DAC 2 0x01 DC shifted 2 0.05 0.25 0.45 BW (max) = 0.4 × fDAC 2 0x02 F/2 −2 −0.7 −0.5 −0.3 2 0x03 F/2 shifted −1 −0.45 −0.25 −0.05 1 Frequency normalized to fDAC. Rev. A | Page 34 of 56 AD9776/AD9778/AD9779 10 INTERPOLATION FILTER MINIMUM AND 0 MAXIMUM BANDWIDTH SPECIFICATIONS –10 The AD977x uses a novel interpolation filter architecture that allows DAC IF frequencies to be generated anywhere in the –20 spectrum. Figure 68 shows the traditional choice of DAC IF –30 output bandwidth placement. Note that there are no possible –40 filter modes in which the carrier can be placed near 0.5 × fDATA, 1.5 × fDATA, 2.5 × fDATA, and so on. –50 10 –60 0 –70 –10 –80 –4 –3 –2 –1 0 1 2 3 4 –20 f (× Input Data Rate), OUT ASSUMING 8× INTERPOLATION –30 Figure 70. Shifted Bandwidths Accessible with the Filter Architecture –40 With this filter architecture, a signal placed anywhere in the –50 spectrum is possible. However, the signal bandwidth is limited –60 by the input sample rate of the DAC and the specific placement of the carrier in the spectrum. The bandwidth restriction –70 resulting from the combination of filter response and input –80 sample rate is often referred to as the synthesis bandwidth, since –4 –3 –2 –1 0123 4 f (× Input Data Rate), this is the largest bandwidth that the DAC can synthesize. OUT ASSUMING 8× INTERPOLATION Figure 68. Traditional Bandwidth Options for TxDAC Output IF The maximum bandwidth condition exists if the carrier is placed directly in the center of one of the filter pass bands. In The filter architecture not only allows the interpolation filter this case, the total 0.1 dB bandwidth of the interpolation filters pass bands to be centered in the middle of the input Nyquist is equal to 0.8 × fDATA. As Table 17 shows, the synthesis band- zones (as explained in this section), but also allows the possi- width as a fraction of DAC output sample rate drops by a factor bility of a 3 × f /8 modulation mode. With all of these filter DAC of 2 for every doubling of interpolation rate. The minimum combinations, a carrier of given bandwidth can be placed bandwidth condition exists, for example, if a carrier is placed at anywhere in the spectrum and fall into a possible pass band of 0.25 × f . In this situation, if the nonshifted filter response is DATA the interpolation filters. The possible bandwidths accessible enabled, the high end of the filter response cuts off at 0.4 × fDATA, with the filter architecture are shown in Figure 69 and thus limiting the high end of the signal bandwidth. If the shifted Figure 70. Note that the shifted and nonshifted filter modes filter response is enabled instead, then the low end of the filter are all accessible by programming the filter mode for the response cuts off at 0.1 × fDATA, thus limiting the low end of the particular interpolation rate. signal bandwidth. The minimum bandwidth specification that 10 applies for a carrier at 0.25 × f is therefore 0.3 × f . The DATA DATA minimum bandwidth behavior is repeated over the spectrum 0 for carriers placed at (±n ± 0.25) × fDATA, where n is any integer. –10 DRIVING THE REFCLK INPUT –20 The REFCLK input requires a low jitter differential drive signal. –30 It is a PMOS input differential pair powered from –40 the 1.8 V supply, therefore, it is important to maintain the –50 specified 400 mV input common-mode voltage. Each input pin can safely swing from 200 mV p-p to 1 V p-p about the –60 400 mV common-mode voltage. While these input levels are –70 not directly LVDS-compatible, REFCLK can be driven by an –80 offset ac-coupled LVDS signal, as shown in Figure 71. –4 –3 –2 –1 0 1 2 3 4 f (× Input Data Rate), OUT ASSUMING 8× INTERPOLATION Figure 69. Nonshifted Bandwidths Accessible with the Filter Architecture Rev. A | Page 35 of 56 ATTENUATION (dB) ATTENUATION (dB) –f /2 –f /2 DAC DAC –3 × f /8 DAC –f /4 –f /4 DAC DAC –f /8 DAC –f /8 DAC BASEBAND BASEBAND +f /8 +f /8 DAC DAC +f /4 +f /4 DAC DAC +3 × f /8 DAC +f /2 +f /2 DAC DAC 05361-066 05361-065 ATTENUATION (dB) SHIFTED –3 × f /8 DAC SHIFTED –f /4 DAC SHIFTED –f /8 DAC SHIFTED –DC SHIFTED –DC SHIFTED –f /8 DAC SHIFTED –f /4 DAC SHIFTED –3 × f /8 DAC 05361-067 AD9776/AD9778/AD9779 0.1μF PLL Enabled (Register 0x09, Bit 7 = 1) LVDS_P_IN CLK+ 50Ω The PLL enable switch shown in Figure 74 is connected to the V = 400mV CM junction of the N1 dividers (PLL VCO divide ratio) and N2 50Ω dividers (PLL loop divide ratio). Divider N3 determines the LVDS_N_IN CLK– interpolation rate of the DAC, and the ratio N3/N2 determines 0.1μF the ratio of reference clock/input data rate. The VCO runs Figure 71. LVDS REFCLK Drive Circuit optimally over the range of 1.0 GHz to 2.0 GHz, so that N1 keeps the speed of the VCO within this range, although the If a clean sine clock is available, it can be transformer-coupled DAC sample rate can be lower. The loop filter components are to REFCLK, as shown in Figure 71. Use of a CMOS or TTL entirely internal and no external compensation is necessary. clock is also acceptable for lower sample rates. It can be routed through a CMOS to LVDS translator, then ac-coupled, as PLL Disabled (Register 0x09, Bit 7 = 0) described in this section. Alternatively, it can be transformer- The PLL enable switch shown in Figure 74 is connected to the coupled and clamped, as shown in Figure 72. reference clock input. The differential reference clock input is 0.1μF 50Ω TTL OR CMOS the same as the DAC output sample rate. N3 determines the CLK+ CLK INPUT interpolation rate. 0x0A (7:5) CLK– ADC PLL CONTROL VOLTAGE RANGE 50Ω BAV99ZXCT 0x0A (4:0) HIGH SPEED LOOP FILTER 0x08 (7:2) DUAL DIODE REFERENCE CLOCK VCO RANGE BANDWIDTH (PINS 5 AND 6) INTERNAL V = 400mV CM PHASE VCO LOOP DETECTION FILTER Figure 72. TTL or CMOS REFCLK Drive Circuit A simple bias network for generating VCM is shown in ÷N2 ÷N1 0x09 (4:3) 0x09 (6:5) DAC Figure 73. It is important to use CVDD18 and CGND for the PLL LOOP PLL VCO INTERPOLATION DIVIDE RATIO DIVIDE RATIO clock bias circuit. Any noise or other signal that is coupled onto RATE the clock is multiplied by the DAC digital input signal and can ÷N3 DATACLK OUT (PIN 37) degrade DAC performance. 0x01 (7:6) 0x09 (7) PLL ENABLE V = 400mV CM INTERNAL DAC SAMPLE CVDD18 RATE CLOCK 1kΩ Figure 74. Internal Clock Architecture 1nF 287Ω 0.1μF 1nF CGND Figure 73. REFCLK VCM Generator Circuit INTERNAL PLL CLOCK MULTIPLIER/CLOCK DISTRIBUTION The internal clock structure on the devices allows the user to drive the differential clock inputs with a clock at 1× or an integer multiple of the input data rate or at the DAC output sample rate. An internal PLL provides input clock multiplication and provides all the internal clocks required for the interpolation filters and data synchronization. The internal clock architecture is shown in Figure 74. The reference clock is the differential clock at Pin 5 and Pin 6. This clock input can be run differentially or singled-ended by driving Pin 5 with a clock signal and biasing Pin 6 to the midswing point of the signal at Pin 5. The clock architecture can be run in the following configurations: Rev. A | Page 36 of 56 05361-068 05361-070 05361-069 05361-071 AD9776/AD9778/AD9779 Table 18. VCO Frequency Range vs. PLL Band Select Value Typical PLL Lock Ranges Typical PLL Lock Ranges PLL Band Select VCO Frequency Range in MHz PLL Band Select VCO Frequency Range in MHz Typ at 25°C Typ over Temp Typ at 25°C Typ over Temp fLOW fHIGH fLOW fHIGH fLOW fHIGH fLOW fHIGH 111111 (63) Auto mode Auto mode 001110 (14) 1116 1184 1137 1170 111110 (62) 2056 2170 2105 2138 001101 (13) 1106 1171 1127 1157 111101 (61) 2002 2113 2048 2081 001100 (12) 1086 1152 1106 1138 111100 (60) 1982 2093 2029 2061 001011 (11) 1075 1138 1095 1124 111011 (59) 1964 2075 2010 2043 001010 (10) 1055 1119 1075 1106 111010 58) 1947 2057 1992 2026 001001 (9) 1045 1107 1065 1093 111001 (57) 1927 2037 1971 2006 001000 (8) 1027 1090 1047 1076 111000 (56) 1907 2016 1951 1986 000111 (7) 1016 1076 1034 1062 110111 (55) 1894 2003 1936 1972 000110 (6) 998 1059 1016 1046 110110 (54) 1872 1981 1913 1952 000101 (5) 987 1046 1005 1032 110101 (53) 1852 1960 1892 1931 000100 (4) 960 1017 977 1004 110100 (52) 1841 1948 1881 1920 000011 (3) 933 989 949 976 110011 (51) 1816 1923 1855 1895 000010 (2) 908 962 923 950 110010 (50) 1796 1903 1835 1874 000001 (1) 883 936 898 925 110001 (49) 1789 1895 1828 1867 000000 (0) 859 911 873 899 110000 (48) 1764 1871 1803 1844 101111 (47) 1746 1853 1784 1826 VCO Frequency Ranges 101110 (46) 1738 1842 1776 1815 Because the PLL band covers greater than a 2× frequency range, 101101 (45) 1714 1820 1752 1794 there can be two options for the PLL band select: one at the low 101100 (44) 1700 1804 1737 1779 end of the range and one at the high end of the range. Under 101011 (43) 1689 1790 1726 1764 these conditions, the VCO phase noise is optimal when the user 101010 (42) 1657 1757 1695 1734 selects the band select value corresponding to the high end of the 101001 (41) 1641 1738 1679 1714 frequency range. Figure 75 shows how the VCO bandwidth and 101000 (40) 1610 1707 1649 1684 the optimal VCO frequency varies with the band select value. 100111 (39) 1597 1689 1635 1666 100110 (38) 1568 1661 1607 1639 VCO Frequency Ranges over Temperature 100101 (37) 1553 1641 1592 1617 The specifications given over temperature in Table 18 are for a 100100 (36) 1525 1613 1562 1592 single part in a single lot. Part-to-part, and lot-to-lot, these 100011 (35) 1511 1595 1548 1572 specifications can exhibit a mean shift of several register 100010 (34) 1484 1570 1519 1549 settings. Systems should be designed to take this potential shift 100001 (33) 1470 1552 1506 1528 into account to maintain optimal PLL performance. 100000 (32) 1441 1525 1474 1504 011111 (31) 1429 1509 1463 1487 PLL Loop Filter Bandwidth 011110 (30) 1403 1485 1433 1464 The loop filter bandwidth of the PLL is programmed via SPI 011101 (29) 1390 1469 1422 1447 Register 0x0A, Bits<4:0>. Changing these values switches 011100 (28) 1362 1443 1391 1423 capacitors on the internal loop filter. No external loop filter 011011 (27) 1352 1429 1380 1407 components are required. This loop filter has a pole at 0 (P1), 011010 (26) 1325 1405 1352 1385 and then a zero (Z1) pole (P2) combination. Z1 and P2 occur 011001 (25) 1314 1390 1340 1369 within a decade of each other. The location of the zero pole is 011000 (24) 1290 1368 1315 1350 determined by Bits<4:0>. For a setting of 00000, the zero pole 010111 (23) 1276 1351 1302 1332 occurs near 10 MHz. By setting Bits<4:0> to 11111, the Z1/P2 010110 (22) 1253 1331 1277 1313 combination can be lowered to approximately 1 MHz. The 010101 (21) 1239 1313 1264 1295 relationship between Bits<4:0> and the position of the zero pole 010100 (20) 1183 1255 1205 1240 between 1 MHz and 10 MHz is linear. The internal components 010011 (19) 1204 1275 1227 1259 are not low tolerance, however, and can drift by as much as ±30%. 010010 (18) 1151 1221 1172 1207 010001 (17) 1171 1240 1193 1224 For optimal performance, the bandwidth adjustment 010000 (16) 1148 1218 1170 1204 (Register 0x0A, Bits<4:0>) should be set to 11111 for all 001111 (15) 1137 1204 1159 1189 operating modes with PLL enabled. The PLL bias settings Rev. A | Page 37 of 56 AD9776/AD9778/AD9779 (Register 0x09, Bits<2:0>) should be set to 111. The PLL control external resistor is 10 kΩ, which sets up an I in the REFERENCE voltage (Register 0x0A, Bits<7:5>) is read back and is propor- resistor of 120 μA, which in turn provides a DAC output full- tional to the dc voltage at the internal loop filter output. With scale current of 20 mA. Because the gain error is a linear the PLL bias settings given in this section, the readback from function of this resistor, a high precision resistor improves gain the PLL control voltage should typically be 010, or possibly 001 matching to the internal matching specification of the devices. or 011. Anything outside of this range indicates that the PLL is Internal current mirrors provide a current-gain scaling, where not operating correctly. I DAC or Q DAC gain is a 10-bit word in the SPI port register (Register 0x0A, Register 0x0B, Register 0x0E, and Register 0x0F). 60 The default value for the DAC gain registers gives an I of FS 56 52 approximately 20 mA, where I is equal to FS 48 44 1.2V ⎛ 27 6 ⎞ ⎛ ⎞ ×⎜ + × DAC gain ⎟×32 ⎜ ⎟ 40 R 12 1024 ⎝ ⎠ ⎝ ⎠ 36 32 28 AD9779 24 I DAC GAIN 20 I DAC 1.2V BAND GAP 16 VREF 12 DAC FULL-SCALE CURRENT REFERENCE I120 0.1μF SCALING 8 CURRENT 4 10kΩ 0 Q DAC Q DAC GAIN Figure 77. Reference Circuitry F (MHz) VCO Figure 75. Typical PLL Band Select vs. Frequency at 25°C 35 60 30 56 52 25 48 44 20 40 36 32 15 28 24 10 20 16 5 12 8 0 4 0 200 400 600 800 1000 0 DAC GAIN CODE Figure 78. I vs. DAC Gain Code FS F (MHz) VCO Application of Auxiliary DACs in Single Sideband Figure 76. Typical PLL Band Select vs. Frequency over Temperature Transmitter The AD977x has an autosearch feature that determines the Two auxiliary DACs are provided on the AD977x. The full-scale optimal settings for the PLL. To enable the autosearch mode, set output current on these DACs is derived from the 1.2 V band Register 0x08, Bits<7:2> to 11111b, and read back the value gap reference and external resistor. The gain scale from the ref- from Register 0x08, Bits<7:2>. Autosearch mode is intended to erence amplifier current I to the auxiliary DAC reference REFERENCE find the optimal PLL settings only, after which the same settings current is 16.67 with the auxiliary DAC gain set to full scale should be applied in manual mode. It is not recommended that (10-bit values, SPI Register 0x0D and SPI Register 0x11), this the PLL be set to autosearch mode during regular operation. gives a full-scale current of approximately 2 mA for auxiliary DAC1 and auxiliary DAC2. The auxiliary DAC outputs are not FULL-SCALE CURRENT GENERATION differential. Only one side of the auxiliary DAC (P or N) is Internal Reference active at one time. The inactive side goes into a high impedance Full-scale current on the I DAC and Q DAC can be set from state (>100 kΩ). In addition, the P or N outputs can act as 8.66 mA to 31.66 mA. Initially, the 1.2 V band gap reference is current sources or sinks. The control of the P and N side for used to set up a current in an external resistor connected to both auxiliary DACs is via Register 0x0E and Register 0x10, I120 (Pin 75). A simplified block diagram of the reference Bits<7:6>. When sourcing current, the output compliance circuitry is shown in Figure 77. The recommended value for the Rev. A | Page 38 of 56 PLL BAND PLL BAND 850 850 950 950 1050 1050 1150 1150 1250 1250 1350 1350 1450 1450 1550 1550 1650 1650 1750 1750 1850 1850 1950 1950 2050 2050 2150 2150 05361-113 05361-072 I (mA) FS 05361-074 05361-073 AD9776/AD9778/AD9779 voltage is 0 V to 1.6 V. When sinking current, the output of the 3.3 V supply (mode and speed independent) in single compliance voltage is 0.8 V to 1.6 V. DAC mode is 102 mW/31 mA. In dual DAC mode, this is 182 mW/55 mA. Furthermore, when the PLL is enabled, it adds The auxiliary DACs can be used for local oscillator (LO) cancella- 90 mW/50 mA to the 1.8 V clock supply regardless of the mode tion when the DAC output is followed by a quadrature modulator. of the AD9779. This LO feedthrough is caused by the input referred dc offset voltage of the quadrature modulator (and the DAC output offset 0.7 8× INTERPOLATION voltage mismatch) and can degrade system performance. Typical 0.6 DAC-to-quadrature modulator interfaces are shown in Figure 79 4× INTERPOLATION 4× INTERPOLATION, and Figure 80. Often, the input common-mode voltage for the 8× INTERPOLATION, ZERO STUFFING 0.5 ZERO STUFFING modulator is much higher than the output compliance range of 2× INTERPOLATION, the DAC, so that ac coupling or a dc level shift is necessary. If the 0.4 ZERO STUFFING required common-mode input voltage on the quadrature 2× INTERPOLATION 0.3 modulator matches that of the DAC, then the dc blocking 1× INTERPOLATION, ZERO STUFFING capacitors in Figure 79 can be removed. A low-pass or band-pass 0.2 passive filter is recommended when spurious signals from the 1× INTERPOLATION DAC (distortion and DAC images) at the quadrature modulator 0.1 inputs can affect the system performance. Placing the filter at the 0 location shown in Figure 79 and Figure 80 allows easy design of 0 25 50 75 100 125 150 175 200 225 250 the filter, as the source and load impedances can easily be f (MSPS) DATA designed close to 50 Ω. Figure 81. Total Power Dissipation, I Data Only, Real Mode QUADRATURE MODULATOR V+ 0.4 AD9779 AUX DAC1 8× INTERPOLATION 4× INTERPOLATION 0.3 QUADRATURE MODULATOR V+ 0.1μF AD9779 OPTIONAL AD9779 QUAD MOD AUX PASSIVE I DAC I INPUTS DAC2 FILTERING 0.2 2× INTERPOLATION 0.1μF 25Ω TO 50Ω 0.1μF OPTIONAL 0.1 AD9779 QUAD MOD PASSIVE Q DAC Q INPUTS FILTERING 1× INTERPOLATION 0.1μF 25Ω TO 50Ω 0 0 25 50 75 100 125 150 175 200 225 250 Figure 79. Typical Use of Auxiliary DACs AC Coupling to f (MSPS) DATA Quadrature Modulator Figure 82. Power Dissipation, Digital 1.8 V Supply, I Data Only, Real Mode, QUADRATURE Does Not Include Zero Stuffing MODULATOR V+ 0.08 AD9779 AUX QUAD MOD DAC1 OR 2 I OR Q INPUTS 0.06 8× INTERPOLATION 4× INTERPOLATION OPTIONAL AD9779 0.04 PASSIVE I OR Q DAC 2× INTERPOLATION FILTERING 25Ω TO 50Ω 25Ω TO 50Ω 0.02 1× INTERPOLATION Figure 80. Typical Use of Auxiliary DACs DC Coupling to Quadrature Modulator with DC Shift 0 0 25 50 75 100 125 150 175 200 225 250 POWER DISSIPATION f (MSPS) DATA Figure 81 to Figure 89 show the power dissipation of the 1.8 V Figure 83. Power Dissipation, Clock 1.8 V Supply, I Data Only, Real Mode, and 3.3 V digital and clock supplies in single DAC and dual Includes Modulation Modes, Does Not Include Zero Stuffing DAC modes. In addition to this, the power dissipation/current Rev. A | Page 39 of 56 05361-116 05361-115 POWER (W) POWER (W) POWER (W) 05361-079 05361-078 05361-076 AD9776/AD9778/AD9779 0.075 0.125 8× INTERPOLATION, f /8, DAC f /4, DAC f /2, DAC NO MODULATION 0.100 4× INTERPOLATION ALL INTERPOLATION MODES 0.050 0.075 2× INTERPOLATION 0.050 0.025 0.025 1× INTERPOLATION, NO MODULATION 0 0 0 25 50 75 100 125 150 175 200 225 250 0 25 50 75 100 125 150 175 200 225 250 f (MSPS) f (MSPS) DATA DATA Figure 87. Power Dissipation, Clock 1.8 V Supply, I and Q Data, Dual DAC Figure 84. Digital 3.3 V Supply, I Data Only, Real Mode, Includes Modulation Mode, Does Not Include Zero Stuffing Modes and Zero Stuffing 1.0 0.075 8× INTERPOLATION, ALL MODULATION MODES 8× INTERPOLATION, 0.9 ZERO STUFFING 4× INTERPOLATION, ALL MODULATION 0.8 MODES 0.7 ALL INTERPOLATION MODES 0.050 0.6 2× INTERPOLATION, 0.5 ALL MODULATION MODES 0.4 0.025 0.3 2× INTERPOLATION, 0.2 ZERO STUFFING 4× INTERPOLATION, 1× INTERPOLATION, ZERO STUFFING ZERO STUFFING 0.1 1× INTERPOLATION 0 0 0 25 50 75 100 125 150 175 200 225 250 275 300 0 25 50 75 100 125 150 175 200 225 250 f (MSPS) DATA f (MSPS) DATA Figure 88. Digital 3.3 V Supply, I and Q Data, Dual DAC Mode Figure 85. Total Power Dissipation, Dual DAC Mode 0.8 0.16 8× INTERPOLATION, f /8, DAC f /4, DAC 0.7 0.14 f /2, DAC NO MODULATION 4× INTERPOLATION 0.6 0.12 0.10 0.5 0.4 0.08 2× INTERPOLATION 0.06 0.3 0.2 0.04 1× INTERPOLATION, NO MODULATION 0.1 0.02 0 0 0 25 50 75 100 125 150 175 200 225 250 0 200 400 600 800 1000 1200 f (MSPS) f (MSPS) DATA DAC Figure 86. Power Dissipation, Digital 1.8 V Supply, I and Q Data, Dual DAC Figure 89. Power Dissipation of Inverse Sinc Filter Mode, Does Not Include Zero Stuffing Rev. A | Page 40 of 56 POWER (W) POWER (W) POWER (W) 05361-081 05361-077 05361-080 POWER (W) POWER (W) POWER (W) 05361-082 05361-083 05361-084 AD9776/AD9778/AD9779 POWER-DOWN AND SLEEP MODES INTERLEAVED DATA MODE The AD977x has a variety of power-down modes, so that the The TxEnable bit is dual function. In dual port mode, it is digital engine, main TxDACs, or auxiliary DACs can be powered simply used to power down the digital section of the devices. In down individually or together. Via the SPI port, the main TxDACs interleaved mode, the IQ data stream is synchronized to can be placed in sleep or power-down mode. In sleep mode, the TXENABLE. Therefore, to achieve IQ synchronization, TxDAC output is turned off, thus reducing power dissipation. TXENABLE should be held low until an I data word is present at The reference remains powered on, however, so that recovery the inputs to Data Port 1. If a DATACLK rising edge occurs from sleep mode is very fast. With the power-down mode bit while TXENABLE is at a high logic level, IQ data becomes set (Register 0x00, Bit 4), all analog and digital circuitry, including synchronized to the DATACLK output. TXENABLE can remain the reference, is powered down. The SPI port remains active in high and the input IQ data remains synchronized. To be this mode. This mode offers more substantial power savings backwards-compatible with previous DACs from Analog than sleep mode, but the turn-on time is much longer. The Devices, Inc. such as the AD9777 and AD9786, the user can auxiliary DACs also have the capability to be programmed into also toggle TXENABLE once during each data input cycle, thus sleep mode via the SPI port. The auto power-down enable bit continually updating the synchronization. If TXENABLE is (Register 0x00, Bit 3) controls the power-down function for the brought low and held low for multiple REFCLK cycles, then the digital section of the devices. The auto power-down function devices flush the data in the interpolation filters, and shut down works in conjunction with the TXENABLE pin (Pin 39) according the digital engine after the filters are flushed. The amount of to the following: REFCLK cycles it takes to go into this power-down mode is then a function of the length of the equivalent 2×, 4×, or 8× TXENABLE (Pin 39) = interpolation filter. The timing of TXENABLE, I/Q select, filter 0: autopower-down enable = flush, and digital power-down are shown in Figure 91. 0: flush data path with 0s 1: flush data for multiple REFCLK cycles; then INTERLEAVED I1 Q1 I2 Q2 INPUT DATA automatically place the digital engine in power-down state. DACs, reference, and SPI port are not affected. TxENABLE or TXENABLE (Pin 39) = TxENABLE CAN REMAIN FLUSHING POWER HIGH OR TOGGLE FOR INTERPOLATION DOWN DIGITAL 1: normal operation I/Q SYNCHRONIZATION FILTERS SECTION As shown in Figure 90, the power dissipation saved by using the Figure 91. TXENABLE Function power down mode is nearly proportional to the duty cycle of the signal at the TXENABLE pin. The TXENABLE function can be inverted by changing the 0.9 status of Register 0x02, Bit 1. The other bit that controls IQ 2× INT f = 50MSPS DATA ordering is the Q-first bit (Register 0x02, Bit 0). With the Q-first 2× INT f = 200MSPS 0.8 DATA 4× INT f = 50MSPS DATA bit reset to the default of 0, the IQ pairing that is latched is the 0.7 4× INT f = 200MSPS DATA I1Q1, I2Q2, and so on. With IQ first set to 1, the first I data is 8× INT f = 50MSPS DATA 0.6 8× INT f = 200MSPS DATA discarded and the pairing is I2Q1, I3Q2, and so on. Note that with IQ-first set, the I data is still routed to the internal I 0.5 channel, the Q data is routed to the internal Q channel, and 0.4 only the pairing changes. 0.3 TIMING INFORMATION 0.2 Figure 92 to Figure 95 show some of the various timing 0.1 possibilities when the PLL is enabled. The combination of the 0 settings of N2 and N3 from Figure 74 means that the reference 0 20 40 60 80 100 clock frequency can be a multiple of the actual input data rate. DUTY CYCLE (%) Figure 92 to Figure 95 show, respectively, what the timing looks Figure 90. Power Savings Based on Duty Cycle of TxEnable like when N2/N3 = 1 and 2. If the TxEnable invert bit (Register 0x02, Bit 1) is set, the function of this TXENABLE pin is inverted. In interleaved mode, set-up and hold times of DATACLK out to data in are the same as those shown in Figure 92 to Figure 95. It is recommended that any toggling of TXENABLE occur concurrently with the digital data input updating. In this way, timing margins between DATACLK, TXENABLE, and digital input data are optimized. Rev. A | Page 41 of 56 POWER SAVINGS 05361-119 05361-085 AD9776/AD9778/AD9779 REFERENCE CLOCK IN DATA CLOCK OUT t t SREFCLK HREFCLK t t SDATACLK HDATACLK INPUT DATA Figure 92. Timing Specifications, PLL Enabled or Disabled, Interpolation = 1× SYNC_IN t H_SYNC t S_SYNC REFERENCE CLOCK IN DATA CLOCK OUT t HREFCLK t SREFCLK t t SDATACLK HDATACLK INPUT DATA Figure 93. Timing Specifications, PLL Enabled or Disabled, Interpolation = 2× SYNC_IN t H_SYNC t S_SYNC REFERENCE CLOCK IN DATA CLOCK OUT t t SREFCLK HREFCLK t t SDATACLK HDATACLK INPUT DATA Figure 94. Timing Specifications, PLL Enabled or Disabled, Interpolation = 4× SYNC_IN t H_SYNC t S_SYNC REFERENCE CLOCK IN DATA CLOCK OUT t t SREFCLK HREFCLK t t SDATACLK HDATACLK INPUT DATA Figure 95. Timing Specifications, PLL Enabled or Disabled, Interpolation = 8× Rev. A | Page 42 of 56 05361-120 05361-122 05361-121 05361-123 AD9776/AD9778/AD9779 and must be no greater than DATACLK for proper Specifications are given in Table 19 for the drift of input data set synchronization. There is no limit on how slow the SYNC_I up and hold time vs. temperature, as well as the data keep out signal can be driven. As long as the set up and hold timing window (KOW). Note that although these specifications do relationship between SYNC_I and REFCLK given in Table 19 is drift, the length of the keep out window, where input data is met, the input data is latched on the immediate next rising edge invalid, changes very little over temperature. of REFCLK. Note that a rising edge of DATACLK out occurs concurrently with the next REFCLK rising edge, after a short Table 19. AD9779 Timing Specifications vs. Temperature propagation delay. Although this propagation delay is not Min Min Max specified, input data setup and hold timing information is given Timing t t KOW S H with respect to REFCLK in and DATACLK out in Figure 92 to Parameter Temperature (ns) (ns) (ns) Figure 95. Also, note that in 1× interpolation, because there is REFCLK to DATA −40°C −0.8 +2.2 +1.3 no phase ambiguity, there is no need to use the SYNC_I signal. +25°C −1.1 +2.5 +1.4 +85°C −1.3 +2.9 +1.5 Valid Timing Window DATACLK to DATA −40°C +1.8 −0.4 +1.3 In addition to the timing requirements of SYNC_I with respect +25°C +2.1 −0.7 +1.4 to REFCLK, it is important to understand that the valid timing +85°C +2.5 −0.9 +1.5 window for SYNC_I is limited by the internal DAC sample rate. SYNC_I to −40°C to +85°C −0.2 +1.0 +0.8 This is shown in Figure 96. When the t and t requirements are S H REFCLK met, the valid timing window for SYNC_I extends only as far as one period of the internal DAC sample rate (minus tS and tH). SYNCHRONIZATION OF INPUT DATA TO DATACLK Failure to meet this timing specification can potentially result in OUTPUT (PIN 37) erroneous data being latched into the AD9779 digital inputs. As an example, if the AD9779 input data rate is 122.88 MSPS Synchronizing the input data bus to the DATACLK out signal is and the REFCLK is the same, with the AD9779 in 4× interpola- achieved by meeting the timing relationships between DATACLK tion, the DAC sample rate is 1/491.52 MHz or about 2 ns. With and DATA timing specified in Table 19. If the user is synchro- a t of −0.2 ns and t of 1.0 ns, this gives a valid timing window nizing the input data to the DATACLK out, the sync input S H for SYNC_I of (SYNC_I) signal does not need to be applied and can be ignored (connect to GND). 2 ns − 0.8 ns = 1.2 ns SYNCHRONIZATION OF INPUT DATA TO THE The timing window of the digital input data to REFCLK can be REFCLK INPUT (PIN 5 AND PIN 6) WITH PLL moved in increments of one internal REFCLK cycle by using ENABLED OR DISABLED the REFCLK OFFSET register (Register 0x7, Bits<4:0>). Synchronizing the input data bus to the REFCLK input requires Because SYNC_I can be run at the same frequency as REFCLK the use of the SYNC_I input pins (Pin 13 and Pin 14). If the when the PLL is enabled, best practice suggests that in this con- SYNC_I input is not used, there is a phase ambiguity between dition, REFCLK and SYNC_I originate from the same source. the DATACLK out and the REFCLK in. This ambiguity matches This limits the variation in time between these two signals and the interpolation rate in which the AD9779, for example, is makes the overall timing budget easier to achieve. A slight delay currently operating. Because input data is latched on the rising may be necessary on the REFCLK path in this configuration to edge of DATACLK, it is impossible for the user to determine add more timing margin between REFCLK and SYNC_I (see onto which one of the multiple internal DACCLK edges (as an Table 19 for timing relationship). example, one of four edges in 4× interpolation) the input data actually latches. For the user to specifically determine the exact edge of REFCLK on which the data is being latched, a rising edge must be periodically applied to SYNC_I. The frequency of N the SYNC_I signal must be equal to f /2 , N being an integer, DAC REFCLK t t S H t DAC_SAMPLE t DAC_SAMPLE SYNC_I Figure 96. Valid Timing Relationship for SYNC_I to REFCLK Rev. A | Page 43 of 56 05361-124 AD9776/AD9778/AD9779 TEK RUN: 5.00GS/s SAMPLE Using Data Delay to Meet Timing Requirements Δ: 7.84nS To meet strict timing requirements at input data rates of up to @: 32.44nS 250 MSPS, the AD977x has a fine timing feature. Fine timing adjustments are made by programming values into the data clock delay register (Register 0x04, Bits<7:4>). This register can be used to add delay between the REFCLK in and the 2 DATACLK out. Figure 97 shows the default delay present when DATACLK delay is disabled. The disable function bit is found in Register 0x02, Bit 4. Figure 98 shows the delay present when DATACLK delay is enabled and set to 0000. Figure 99 indicates the delay when DATACLK delay is enabled and set to 1111. Note that the setup and hold times specified for data to 1 DATACLK are defined for DATACLK delay disabled. CH1 1.00VΩ CH2 500mVΩ M2.00ns CH1 420mV Figure 99. Delay from REFCLK to DATACLK Out with DATACLK Delay = 1111 TEK RUN: 5.00GS/s SAMPLE The difference between the minimum delay shown in Figure 98 Δ: 4.48nS @: 40.28nS and the maximum delay shown in Figure 99 is the range programmable using the DATACLK delay register. The delay (in absolute time) when programming DATACLK delay between 0000 and 1111 is a linear extrapolation between these 2 two figures. The typical delays per increment over temperature are shown in Table 20. Table 20. Data Delay Line Typical Delays Over Temperature Delays −40°C +25°C +85°C Unit Delay Between Disabled and 370 416 432 ps Enabled 1 Average Delay per Increment 171 183 197 ps CH1 1.00VΩ CH2 500mVΩ M2.00ns CH1 420mV The frequency of DATACLK out depends on several program- Figure 97. Delay from REFCLK to DATACLK with DATACLK Delay Disabled mable settings: interpolation, zero stuffing, and interleaved/ TEK RUN: 5.00GS/s SAMPLE dual port mode, all of which have an effect on the REFCLK Δ: 4.76nS frequency. The divisor function between REFCLK and @: 35.52nS DATACLK is equal to the values shown in Table 21. Table 21. REFCLK to DATACLK Divisor Ratio Interpolation Zero Stuffing Input Mode Divisor 2 1 Disabled Dual port 1 2 Disabled Dual port 2 4 Disabled Dual port 4 8 Disabled Dual port 8 1 Disabled Interleaved Invalid 2 Disabled Interleaved 1 4 Disabled Interleaved 2 1 8 Disabled Interleaved 4 CH1 1.00VΩ CH2 500mVΩ M2.00ns CH1 420mV 1 Enabled Dual port 2 Figure 98. Delay from REFCLK to DATACLK Out with DATACLK Delay = 0000 2 Enabled Dual port 4 4 Enabled Dual port 8 8 Enabled Dual port 16 1 Enabled Interleaved 1 2 Enabled Interleaved 2 4 Enabled Interleaved 4 8 Enabled Interleaved 8 Rev. A | Page 44 of 56 05361-090 05361-089 05361-091 AD9776/AD9778/AD9779 In addition to this divisor function, DATACLK can be divided Necessary corrections can be made by adjusting DATACLK by up to an additional factor of 4, according to the state of the delay and the DATACLK invert bit (Register 2, Bit 2). DATACLK divide register (Register 0x03, Bits<5:4>). For more DATACLK delay can then be swept to find the range over which details, see Table 22). the timing is valid. The final value for data delay should be the value that corresponds to the middle of the valid timing range. Table 22. Extra DATACLK Divisor Ratio If a valid timing range is not found during this sweep, the user Register 0x03, Bits<5:4> Divider Ratio should invert the DATACLK invert bit and repeat the process. 00 1 01 2 Multiple DAC Synchronization 10 4 The AD9779 has programmable features that allow the CMOS 11 1 digital data bus inputs and internal filters on multiple devices to The maximum divisor resulting from the combination of the be synchronized. This means that the DATACLK output signal values in Table 21, and the DATACLK divide register is 32. on one AD9779 can be used to register the output data for a data bus delivering data to multiple AD9779s. The details of this opera- Manual Input Timing Correction tion are given in the Analog Devices Application Note AN-822. Correction of input timing can be achieved manually. The correction function is controlled by Register 0x03, Bits<7:6>. The function is programmed as shown in Table 23. Table 23. Input Timing Correction Mode Register 0x03, Bits<7:6> Function 00 Error check disabled 01 Reserved 10 Reserved 11 Reserved Rev. A | Page 45 of 56 AD9776/AD9778/AD9779 EVALUATION BOARD OPERATION The AD977x evaluation board is designed to optimize the DAC The evaluation board comes with software that allows the user performance and the speed of the digital interface, yet remains to program the SPI port. Via the SPI port, the devices can be user friendly. To operate the board, the user needs a power programmed into any of its various operating modes. When source, a clock source, and a digital data source. The user also first operating the evaluation board, it is useful to start with a needs a spectrum analyzer or an oscilloscope to look at the DAC simple configuration, that is, a configuration in which the SPI output. The diagram in Figure 100 illustrates the test setup. A port settings are as close as possible to the default settings. The sine or square wave clock works well as a clock source. The dc default software window is shown in Figure 102. The arrows offset on the clock is not a problem, since the clock is ac-coupled indicate which settings need to be changed for an easy first time on the evaluation board before the REFCLK inputs. All evaluation. Note that this implies that the PLL is not being used necessary connections to the evaluation board are shown in and that the clock being used is at the speed of the DAC output more detail in Figure 101. sample rate. For a more detailed description of how to use the PLL, see the PLL Loop Filter Bandwidth section. CLOCK GENERATOR ADAPTER CABLES CLKIN SPI PORT SPECTRUM ANALYZER DIGITAL AD9779 PATTERN EVALUATION GENERATOR BOARD CLOCK IN 1.8V POWER SUPPLY DATACLK OUT 3.3V POWER SUPPLY Figure 100. Typical Test Setup AUX33 DVDD18 DVDD33 CVDD18 AVDD33 J2 5V Supply P4 Digital Input Connector J1 CLOCK IN MODULATOR OUTPUT JP4 JP15 S5 OUTPUT 1 JP8 JP14 +5V AD9779 AD8349 JP3 GND JP16 JP2 JP17 S6 OUTPUT 2 LOCAL OSC INPUT S7 DCLKOUT ANALOG DEVICES AD9779/8/6 REV D SPI PORT Figure 101. AD977x Evaluation Board Showing All Connections Rev. A | Page 46 of 56 05361-098 05361-097 AD9776/AD9778/AD9779 1. SET INTERPOLATION RATE 2. SET INTERPOLATION FILTER MODE 3. SET INPUT DATA FORMAT 4. SET DATACLK POLARITY TO MATCH INPUT TIMING Figure 102. SPI Port Software Window The default settings for the evaluation board allow the user to and common-mode transformers are installed on each DAC view the differential outputs through a transformer that output, so that the pairs can be set up in either order. As an converts the DAC output signal to a single-ended signal. On the example, for the frequency range of dc to 30 MHz, it is evaluation board, these transformers are designated T1A, T2A, recommended that the transformer be placed right after the T3A, and T4A. There are also four common-mode transformers DAC. Above DAC output frequencies of 30 MHz, it is on the board that are designated T1B, T2B, T3B, and T4B. The recommended that the common-mode transformer is placed recommended operating setup places the transformer and right after the DAC outputs, followed by the transformer. common-mode transformer in series. A pair of transformers Rev. A | Page 47 of 56 05361-099 AD9776/AD9778/AD9779 MODIFYING THE EVALUATION BOARD TO USE THE AD8349 ON-BOARD QUADRATURE MODULATOR The evaluation board contains an Analog Devices AD8349 quadrature modulator. The AD977x and AD8349 provide an easy-to-interface DAC/modulator combination that can be easily evaluated on the evaluation board. To route the DAC output signal to the quadrature modulator, the following jumper settings must be made: Unsoldered: JP14, JP15, JP16, JP17 Soldered: JP2, JP3, JP4, JP8 The DAC output area of the evaluation board is shown in Figure 103. The jumpers that need to be changed to use the AD8349 are circled. Also circled are the 5 V and GND connections for the AD8349. Figure 103. Photo of Evaluation Board, DAC Output Area Rev. A | Page 48 of 56 05361-100 AD9776/AD9778/AD9779 EVALUATION BOARD SCHEMATICS Figure 104. Evaluation Board, Rev. D, Power Supply Decoupling and SPI Interface Rev. A | Page 49 of 56 TP1 RED EXC-CL4532U1 EXC-CL4532U1 TP14 L1 L12 RED CVDD18_IN CVDD18 VDDM_IN VDDM U6 TP17 + + C77 C68 C69 C46 C67 C66 3 4 RED TP13 22μF 0.1μF 0.1μF 22μF 0.1μF 0.1μF RED 74AC14 16V L6 16V L16 U6 TP2 DGND2 DGND2 11 10 BLACK EXC-CL4532U1 TP15 EXC-CL4532U1 2 74AC14 BLACK TP3 U6 RED EXC-CL4532U1 9 8 L2 74AC14 DVDD18_IN DVDD18 U6 5 6 TP18 + C76 C71 C70 RED 74AC14 22μF 0.1μF 0.1μF S1 L7 16V SWSECMA TP4 CSB BLACK EXC-CL4532U1 R51 U5 U5 2 9kΩ 2 1 12 13 TP5 S2 RED 74AC14 74AC14 1 EXC-CL4532U1 SWSECMA 3 L3 SCLK AVDD33_IN AVDD33 R53 U5 U5 2 9kΩ TP19 4 3 10 11 + C20 C28 C26 RED 1 22μF 0.1μF 0.1μF L13 16V 3 S3 TP8 SWSECMA BLACK EXC-CL4532U1 SDI 74AC14 74AC14 R54 U5 U5 2 TP6 9kΩ 6 5 8 9 RED EXC-CL4532U1 3 74AC14 74AC14 1 L4 S4 SWSECMA DVDD33_IN DVDD33 SDO TP20 + C21 C45 C42 RED U6 U6 2 P1 22μF 0.1μF 0.1μF 1 2 13 12 1 16V L14 1 2 74AC14 74AC14 TP9 SPI_CSB BLACK 3 3 EXC-CL4532U1 SPI_CLK 4 SPI_SDI TP7 5 SPI_SDO RED EXC-CL4532U1 6 R55 R52 L5 10kΩ 10kΩ TJAK06RAP DPWR33_IN DPWR33 CLASS = IO TP21 + C22 C48 C49 FCI-68898 RED 22μF 0.1μF 0.1μF TP16 16V L15 RED TP10 BLACK EXC-CL4532U1 05361-101 AD9776/AD9778/AD9779 R10 T2B T1B 50Ω R7 T3A T4A S6 JP16 0Ω 1 6 1 6 3 4 3 4 2 2 2 P S P S R8 JP17 1 3 4 3 4 0Ω 1 6 1 6 R11 ADTL1-12 ADTL1-12 TC1-1T TC1-1T 50Ω R9 R6 T2A T1A 50Ω T3B T4B JP14 0Ω 6 1 6 1 4 3 4 3 2 2 R5 2 JP15 S P S P 0Ω 1 4 3 4 3 6 1 6 1 R11 S5 TC1-1T TC1-1T ADTL1-12 ADTL1-12 50Ω DGND;5 JP3 JP2 C62 C33 C34 D2N D2P DPWR33 0.1µF 1nF 1nF JP4 JP8 C40 0.1µF C61 D1P D1N C37 C38 1nF 0.1µF 0.1µF R63 10Ω C35 1nF C18 C60 C24 C25 1nF 0.1µF 1nF CR1 1nF VAL C39 0.1µF C59 C9 6.3V C10 1nF 0.1µF 0.1µF CR2 VAL C36 C8 1nF C1 C2 10µF VOLT R64 R64 VOLT 4.7µF 4.7µF R56 1kΩ 1kΩ 10Ω C27 AVDD33 1nF C58 C11 1nF 0.1µF DVDD33 C57 DVDD18 0.1µF C3 4.7µF VOLT C56 1nF C29 1nF C55 0.1µF C12 0.1µF C31 1nF C30 1nF C14 0.1µF C13 0.1µF + C6 C4 4.7µF VOLT 4.7µF C5 4.7µF VOLT CVDD18 DVDD33 DVDD18 CLK_N CLK_P JP7 P2D15 S15 1 6 R59 S16 1 22Ω 1 2 5 2 3 4 2 R58 22Ω S2 DPWR33 1 DPWR33 2 DATACLK U11 R26 U10 U10 R32 4 10 S7 22Ω C84 25Ω 1 4 3 3 5 11 9 JP18 PRE PRE 0.1µF Y GND J Q J Q 2 1 13 2 A JP13 5 1 2 6 12 7 VCC NC K Q_ K Q_ DPWR33 R26 CLR CLR 22Ω C78 15 14 SN74LVC1G34 4.7µF VOLT 74LCX112 74LCX112 C7 VOLT 4.7µF C15 1nF C32 0.1µF Figure 105. Evaluation Board, Rev. D, Circuitry Local to Devices Rev. A | Page 50 of 56 + + 1 100 VDDC18_1 VDDA33_100 99 2 VDDC18_2 VSSA_99 3 98 VSSC_3 VDDA33_98 4 97 VSSC_4 VSSA_97 96 5 CLK_P VDDA33_96 6 95 CLK_N VSSA_95 7 94 VSSC_7 VSSA_94 IOUT1_P 8 93 VSSC_8 IOUT1_P 92 9 VDDC18_9 IOUT1_N 10 91 IOUT1_N VDDC18_10 VSSA_91 11 90 VSSC_11 AUX1_P AUX1_P 89 12 + + VSS_12 AUX1_N AUX1_N 13 88 SYNC_1P VSSA_88 14 87 SYNC_1N AUX2_N AUX2_N 86 15 VSSD_15 AUX2_P AUX2_P 16 85 VDDD18 VSSA_85 IOUT2_N 17 84 P1D15 IOUT2_N 18 83 P1D14 IOUT2_P 82 19 IOUT2_P P1D13 VSSA_82 20 81 P1D12 VSSA_81 21 80 P1D11 VDDA33_80 79 22 VSSD_22 VSSA_79 23 78 VDDD18_23 VDDA33_78 24 77 P1D10 VSSA_77 25 76 P1D9 VDDA33_76 75 26 P1D8 I120 + 27 74 P1D7 VREF_74 TP11 RED 28 73 P1D6 IPTAT TP12 RED 72 29 P1D5 VSS_72 30 71 P1D4 IRQ 31 70 P1D3 RESET 32 69 VSSD_32 SPI_CSB SPI_CSB 68 33 VDDD18_33 SPI_CLK SPI_CLK 34 67 P1D2 SPI_SDI SPI_SDI SW1 35 66 4 2 P1D1 SPI_SDO SPI_SDO 65 36 3 1 P1D0 PLL_LOCK 37 64 DCLK VSSD_64 38 63 VDDD33_38 SYNC_OP 39 62 TX SYNC_ON 61 40 P2D15 VDDD33_61 41 60 P2D14 VDDD18_60 42 59 P2D13 P2D0 P2D0 58 43 VDD18_43 P2D1 P2D1 44 57 VSSD_44 P2D2 P2D2 45 56 P2D12 P2D3 P2D3 55 46 P2D11 P2D4 P2D4 47 54 P2D10 VSSD_54 48 53 P2D9 VDDD18_53 49 52 P2D8 P2D5 P2D5 51 50 P2D7 P2D6 P2D6 PAD PAD U1 9779TQFP + + + 05361-102 AD9776/AD9778/AD9779 R15 C80 20Ω 2.1pF D1N C53 C64 C50 R20 0.1µF 17.2pF 17.2pF 40Ω R17 150Ω L10 AUX1_N 55nH R4 R19 C81 JP13 150Ω 300Ω 2.1pF AUX1_P R12 150Ω C63 L11 C52 R21 R22 17.2pF 55nH 17.2pF 40Ω 147.5Ω D1P R16 20Ω MODULATED OUTPUT C47 J4 100pF 1 VDDM 2 2 + C41 C73 C72 10µF 0.1µF 0.1µF DGND2 DGND2 10V 2 DGND2 VDDM R14 1kΩ JP1 2 C51 DGND2 LOCAL OSC OUTPUT 0.1µF C74 T4 J5 100pF 1 1 5 2 2 S P 2 3 4 DGND2 DGND2 C75 2 ETC1-1-13 100pF DGND2 R24 C83 20Ω 2.1pF C54 D2N C44 C65 R60 0.1µF JP9 17.2pF 17.2pF 40Ω R25 150Ω L10 JP10 AUX2_N 55nH 2 R2 R27 C82 JP13 150Ω 300Ω 2.1pF DGND2 AUX2_P R3 150Ω C43 L11 C79 R61 R62 17.2pF 55nH 17.2pF 40Ω 147.5Ω D2P R23 20Ω Figure 106. Evaluation Board, Rev. D, AD8349 Quadrature Modulator CLK_P C19 T2 CVDD18 0.1μF J1 4 3 R28 R30 C16 25Ω 1kΩ DNB CLKIN 2 R13 P S VAL 5 1 C17 R29 R31 0.1μF 25Ω 300Ω C23 ETC1-1-13 0.1μF CLK_N Figure 107. Evaluation Board, Rev. D, DAC Clock Interface Rev. A | Page 51 of 56 ADTL1-12 T5 AD8349 6 1 3 4 1 16 IBBP QBBP P S S P 215 1 6 IBBN QBBN 4 3 3 14 G1A G4B 4 13 T3 ADTL1-12 G1B G4A 5 12 LOIN VPS2 6 11 LOIP VOUT 7 10 VPS1 G3 8 9 ENBL G2 U9 05361-104 05361-103 AD9776/AD9778/AD9779 P4 P4 P4 P4 P4 A1 B1 C1 CSB D1 E1 SCLK A2 B2 C2 SD1 D2 E2 SD0 A3 B3 C3 P2D0 D3 E3 P2D1 A4 B4 C4 P2D2 D4 E4 P2D3 A5 B5 C5 P2D4 D5 E5 P2D5 A6 B6 C6 P2D6 D6 E6 P2D7 A7 B7 C7 P2D8 D7 E7 P2D9 A8 B8 C8 P2D10 D8 E8 P2D11 A9 B9 C9 P2D12 D9 E9 P2D13 A10 B10 C10 P2D14 D10 E10 P2D15 A11 B11 C11 D11 E11 A15 B15 C15 D15 E15 A16 B16 C16 D16 E16 A17 B17 C17 P1D0 D17 E17 P1D1 A18 B18 C18 P1D2 D18 E18 P1D3 A19 B19 C19 P1D4 D19 E19 P1D5 A20 B20 C20 P1D6 D20 E20 P1D7 A21 B21 C21 P1D8 D21 E21 P1D9 A22 B22 C22 P1D10 D22 E22 P1D11 A23 B23 C23 P1D12 D23 E23 P1D13 A24 B24 C24 P1D14 D24 E24 P1D15 A25 B25 C25 D25 E25 PKG_TYPE = MOLEX110 PKG_TYPE = MOLEX110 PKG_TYPE = MOLEX110 PKG_TYPE = MOLEX110 PKG_TYPE = MOLEX110 VAL VAL VAL VAL VAL DGND DGND1 BLK BLK Figure 108. Evaluation Board, Rev. D, Digital Input Buffers 5V 1 J2 2 U2 1 2 4 CVDD18_IN 3 JP19 P2 C86 C85 ADP3339-1-8 1μF 1μF 1 2 VAL CNTERM_2P U3 1 2 4 DVDD18_IN 3 JP20 C89 C88 ADP3339-1-8 1μF 1μF U4 1 2 4 DVDD33_IN 3 JP21 C92 C91 1μF 1μF ADP3339-3-3 U7 1 2 4 AVDD33_IN 3 JP22 C93 C94 1μF 1μF ADP3339-3-3 U8 1 2 4 DPWR33_IN 3 JP23 C96 C97 1μF 1μF ADP3339-3-3 Figure 109. Evaluation Board, On-Board Voltage Regulators Rev. A | Page 52 of 56 05361-106 05361-105 AD9776/AD9778/AD9779 Figure 110. Evaluation Board, Rev. D, Top Silk Screen Figure 111. Evaluation Board, Rev. D, Top Layer Rev. A | Page 53 of 56 05361-108 05361-107 AD9776/AD9778/AD9779 Figure 112. Evaluation Board, Rev. D, Layer 2 Figure 113. Evaluation Board, Rev. D, Layer 3 Rev. A | Page 54 of 56 05361-110 05361-109 AD9776/AD9778/AD9779 Figure 114. Evaluation Board, Rev. D, Bottom Layer Figure 115. Evaluation Board, Rev. D, Bottom Silkscreen Rev. A | Page 55 of 56 05361-111 05361-112 AD9776/AD9778/AD9779 OUTLINE DIMENSIONS 1.20 16.00 BSC SQ 0.75 MAX 0.60 14.00 BSC SQ 0.45 100 76 76 100 1 75 75 1 SEATING PIN 1 BOTTOM VIEW PLANE (PINS UP) TOP VIEW (PINS DOWN) CONDUCTIVE HEAT SINK 51 51 25 25 26 50 50 26 0.20 1.05 6.50 0.09 NOM 1.00 7° 0.95 3.5° 0° 0.15 0.50 BSC 0.27 COPLANARITY 0.05 0.08 0.22 0.17 COMPLIANT TO JEDEC STANDARDS MS-026-AED-HD NOTES 1. CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED. 2. THE PACKAGE HAS A CONDUCTIVE HEAT SLUG TO HELP DISSIPATE HEAT AND ENSURE RELIABLE OPERATION OF THE DEVICE OVER THE FULL INDUSTRIAL TEMPERATURE RANGE. THE SLUG IS EXPOSED ON THE BOTTOM OF THE PACKAGE AND ELECTRICALLY CONNECTED TO CHIP GROUND. IT IS RECOMMENDED THAT NO PCB SIGNAL TRACES OR VIAS BE LOCATED UNDER THE PACKAGE THAT COULD COME IN CONTACT WITH THE CONDUCTIVE SLUG. ATTACHING THE SLUG TO A GROUND PLANE WILL REDUCE THE JUNCTION TEMPERATURE OF THE DEVICE WHICH MAY BE BENEFICIAL IN HIGH TEMPERATURE ENVIRONMENTS. Figure 116. 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] (SV-100-1) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option 1 AD9776BSVZ 100-lead TQFP_EP SV-100-1 −40°C to +85°C 1 AD9776BSVZRL 100-lead TQFP_EP SV-100-1 −40°C to +85°C 1 AD9778BSVZ 100-lead TQFP_EP SV-100-1 −40°C to +85°C 1 AD9778BSVZRL 100-lead TQFP_EP SV-100-1 −40°C to +85°C 1 AD9779BSVZ 100-lead TQFP_EP SV-100-1 −40°C to +85°C 1 AD9779BSVZRL 100-lead TQFP_EP SV-100-1 −40°C to +85°C AD9776-EB Evaluation Board AD9778-EB Evaluation Board 1 AD9779-EBZ Evaluation Board 1 Z = RoHS Compliant Part. ©2005–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05361-0-3/07(A) Rev. A | Page 56 of 56