ANALOG DEVICES AD9777

16-Bit, 160 MSPS 2x/4x/8x ® Interpolating Dual TxDAC+ D/A Converter AD9777 Versatile input data interface FEATURES Twos complement/straight binary data coding 16-bit resolution, 160 MSPS/400 MSPS input/output Dual-port or single-port interleaved input data data rate Single 3.3 V supply operation Selectable 2×/4×/8× interpolating filter Power dissipation: typical 1.2 W @ 3.3 V Programmable channel gain and offset adjustment On-chip 1.2 V reference fS/4, fS/8 digital quadrature modulation capability 80-lead thin quad flat package, exposed pad (TQFP_EP) Direct IF transmission mode for 70 MHz + IFs Enables image rejection architecture APPLICATIONS Fully compatible SPI® port Communications Excellent ac performance Analog quadrature modulation architecture SFDR −73 dBc @ 2 MHz to 35 MHz 3G, multicarrier GSM, TDMA, CDMA systems WCDMA ACPR 71 dB @ IF = 19.2 MHz Broadband wireless, point-to-point microwave radios Internal PLL clock multiplier Instrumentation/ATE Selectable internal clock divider Versatile clock input Differential/single-ended sine wave or TTL/CMOS/LVPECL compatible FUNCTIONAL BLOCK DIAGRAM IDAC COS AD9777 HALF- HALF- HALF- GAIN OFFSET BAND BAND BAND DAC DAC FILTER1* FILTER2* FILTER3* DATA SIN ASSEMBLER IMAGE 16 16 16 16 16 REJECTION/ I I/Q DAC DUAL DAC LATCH f /2, 4, 8 GAIN/OFFSET DAC MODE REGISTERS I AND Q BYPASS NONINTERLEAVED MUX OR INTERLEAVED SIN 16 DATA 16 16 16 Q LATCH 16 FILTER COS BYPASS WRITE MUX MUX CONTROL IDAC I SELECT OUT /2 (f ) DAC CLOCK OUT /2 /2 /2 SPI INTERFACE AND PRESCALER DIFFERENTIAL CONTROL REGISTERS CLK PHASE DETECTOR AND VCO * HALF-BAND FILTERS ALSO CAN BE CONFIGURED FOR ZERO STUFFING ONLY PLL CLOCK MULTIPLIER AND CLOCK DIVIDER Figure 1. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 © 2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. VREF IOFFSET 02706-001 AD9777 TABLE OF CONTENTS Features .............................................................................................. 1 Sleep/Power-Down Modes........................................................ 29 Applications....................................................................................... 1 Two Port Data Input Mode ....................................................... 29 General Description ......................................................................... 4 PLL Enabled, Two-Port Mode .................................................. 30 Product Highlights ....................................................................... 4 DATACLK Inversion.................................................................. 30 Specifications..................................................................................... 5 DATACLK Driver Strength....................................................... 30 DC Specifications ......................................................................... 5 PLL Enabled, One-Port Mode .................................................. 30 Dynamic Specifications ............................................................... 6 ONEPORTCLK Inversion......................................................... 31 Digital Specifications ................................................................... 7 ONEPORTCLK Driver Strength.............................................. 31 Digital Filter Specifications ......................................................... 8 IQ Pairing .................................................................................... 31 Absolute Maximum Ratings............................................................ 9 PLL Disabled, Two-Port Mode................................................. 31 Thermal Characteristics .............................................................. 9 PLL Disabled, One-Port Mode................................................. 32 ESD Caution.................................................................................. 9 Digital Filter Modes ................................................................... 32 Pin Configuration and Function Descriptions........................... 10 Amplitude Modulation.............................................................. 32 Terminology .................................................................................... 12 Modulation, No Interpolation .................................................. 34 Typical Performance Characteristics ........................................... 13 Modulation, Interpolation = 2× ............................................... 35 Mode Control (via SPI Port)..................................................... 18 Modulation, Intermodulation = 4× ......................................... 36 Register Description................................................................... 20 Modulation, Intermodulation = 8× ......................................... 37 Functional Description .................................................................. 22 Zero Stuffing ............................................................................... 38 Serial Interface for Register Control ........................................ 22 Interpolating (Complex Mix Mode)........................................ 38 General Operation of the Serial Interface ............................... 22 Operations on Complex Signals............................................... 38 Instruction Byte .......................................................................... 23 Complex Modulation and Image Rejection of Baseband Signals .......................................................................................... 39 R/W .............................................................................................. 23 Image Rejection and Sideband Suppressions of Modulated N1, N0.......................................................................................... 23 Carriers ........................................................................................ 41 A4, A3, A2, A1, A0..................................................................... 23 Applying the Output Configurations........................................... 46 Serial Interface Port Pin Descriptions ..................................... 23 Unbuffered Differential Output, Equivalent Circuit ............. 46 MSB/LSB Transfers..................................................................... 23 Differential Coupling Using a Transformer............................ 46 Notes on Serial Port Operation ................................................ 25 Differential Coupling Using an Op Amp................................ 47 DAC Operation........................................................................... 25 Interfacing with the AD8345 Quadrature Modulator........... 47 1R/2R Mode ................................................................................ 26 Evaluation Board ............................................................................ 48 CLOCK Input Configuration ................................................... 26 Outline Dimensions ....................................................................... 58 Programmable PLL .................................................................... 27 Ordering Guide .......................................................................... 58 Power Dissipation....................................................................... 29 Rev. C | Page 2 of 60 AD9777 REVISION HISTORY Edits to Register Description—Address 07h, 0Bh Section...... 16 1/06—Rev. B to Rev. C Edits to Equation 1........................................................................ 16 Updated Formatting .........................................................Universal Edits to MSB/LSB Transfers Section........................................... 18 Changes to Figure 32 .................................................................... 22 Changes to Figure 8 ...................................................................... 20 Changes to Figure 108 .................................................................. 54 Edits to Programmable PLL Section........................................... 21 Updated Outline Dimensions ..................................................... 58 Added new Figure 14.................................................................... 22 Changes to Ordering Guide......................................................... 58 Renumbered Figures 15 to 69...................................................... 22 Added Two-Port Data Input Mode Section............................... 23 6/04—Data Sheet Changed from Rev. A to Rev. B. Edits to PLL Enabled, Two-Port Mode Section ........................ 24 Changes to DC Specifications ....................................................... 5 Edits to Figure 19 ......................................................................... 24 Changes to Absolute Maximum Ratings...................................... 8 Edits to Figure 21 .......................................................................... 25 Changes to DAC Operation Section........................................... 25 Edits to PLL Disabled, Two-Port Mode Section ....................... 25 Changes to Figure 49, Figure 50, and Figure 51........................ 29 Edits to Figure 22 .......................................................................... 25 Changes to the PLL Enabled, One-Port Mode Section............ 30 Edits to Figure 23 .......................................................................... 26 Changes to the PLL Disabled, One-Port Mode Section........... 32 Edits to Figure 26a ........................................................................ 27 Changes to the Ordering Guide .................................................. 57 Changes to Figures 53 and 54...................................................... 38 Updated the Outline Dimensions ............................................... 57 Edits to Evaluation Board Section .............................................. 39 Changes to Figures 56 to 59......................................................... 40 3/03—Data Sheet Changed from Rev. 0 to Rev. A. Replaced Figures 60 to 69 ............................................................ 42 Edits to Features .............................................................................. 1 Updated Outline Dimensions...................................................... 49 Edits to DC Specifications ............................................................. 3 Edits to Dynamic Specifications.................................................... 4 7/02—Revision 0: Initial Version Edits to Pin Function Descriptions............................................... 7 Edits to Table I ............................................................................... 14 Edits to Register Description—Address 02h Section ............... 15 Edits to Register Description—Address 03h Section ............... 16 Rev. C | Page 3 of 60 AD9777 GENERAL DESCRIPTION 1 The AD9777 is the 16-bit member of the AD977x pin Targeted at wide dynamic range, multicarrier, and compatible, high performance, programmable 2×/4×/8× multistandard systems, the superb baseband performance of the interpolating TxDAC+ family. The AD977x family features a AD9777 is ideal for wideband CDMA, multicarrier CDMA, serial port interface (SPI) that provides a high level of multicarrier TDMA, multicarrier GSM, and high performance programmability, thus allowing for enhanced system level systems employing high-order QAM modulation schemes. The options. These options include selectable 2×/4×/8× interpola- image rejection feature simplifies and can help to reduce the tion filters; f /2, f /4, or f /8 digital quadrature modulation with number of signal band filters needed in a transmit signal chain. S S S image rejection; a direct IF mode; programmable channel gain The direct IF mode helps to eliminate a costly mixer stage for a and offset control; programmable internal clock divider; variety of communications systems. straight binary or twos complement data interface; and a single- PRODUCT HIGHLIGHTS port or dual-port data interface. 1. The AD9777 is the 16-bit member of the AD977x pin The selectable 2×/4×/8× interpolation filters simplify the compatible, high performance, programmable 2×/4×/8× requirements of the reconstruction filters while simultaneously interpolating TxDAC+ family. enhancing the TxDAC+ family’s pass-band noise/distortion 2. Direct IF transmission is possible for 70 MHz + IFs performance. The independent channel gain and offset adjust through a novel digital mixing process. registers allow the user to calibrate LO feedthrough and sideband suppression errors associated with analog quadrature modulators. 3. f /2, f /4, and f /8 digital quadrature modulation and user S S S The 6 dB of gain adjustment range can also be used to control the selectable image rejection simplify/remove cascaded SAW output power level of each DAC. filter stages. 4. A 2×/4×/8× user selectable interpolating filter eases data The AD9777 features the ability to perform fS/2, fS/4, and fS/8 rate and output signal reconstruction filter requirements. digital modulation and image rejection when combined with an analog quadrature modulator. In this mode, the AD9777 accepts I 5. User selectable twos complement/straight binary data and Q complex data (representing a single or multicarrier wave- coding. form), generates a quadrature modulated IF signal along with its 6. User programmable channel gain control over 1 dB range orthogonal representation via its dual DACs, and presents these in 0.01 dB increments. two reconstructed orthogonal IF carriers to an analog quadrature modulator to complete the image rejection upconversion process. 7. User programmable channel offset control ±10% over the Another digital modulation mode (that is, the direct IF mode) FSR. allows the original baseband signal representation to be fre- 8. Ultrahigh speed 400 MSPS DAC conversion rate. quency translated such that pairs of images fall at multiples of 9. Internal clock divider provides data rate clock for easy one-half the DAC update rate. interfacing. The AD977x family includes a flexible clock interface accepting 10. Flexible clock input with single-ended or differential input, differential or single-ended sine wave or digital logic inputs. An CMOS, or 1 V p-p LO sine wave input capability. internal PLL clock multiplier is included and generates the necessary on-chip high frequency clocks. It can also be disabled 11. Low power: Complete CMOS DAC operates on 1.2 W to allow the use of a higher performance external clock source. from a 3.1 V to 3.5 V single supply. The 20 mA full-scale An internal programmable divider simplifies clock generation current can be reduced for lower power operation, and in the converter when using an external clock source. A flexible several sleep functions are provided to reduce power during idle periods. data input interface allows for straight binary or twos comple- ment formats and supports single-port interleaved or dual-port 12. On-chip voltage reference: The AD9777 includes a 1.20 V data. temperature compensated band gap voltage reference. Dual high performance DAC outputs provide a differential 13. An 80-lead thin quad flat package, exposed pad current output programmable over a 2 mA to 20 mA range. The (TQFP_EP). AD9777 is manufactured on an advanced 0.35 micron CMOS process, operates from a single-supply of 3.1 V to 3.5 V, and consumes 1.2 W of power. 1 Protected by U.S. Patent Numbers, 5,568,145; 5,689,257; and 5,703,519. Other patents pending. Rev. C | Page 4 of 60 AD9777 SPECIFICATIONS DC SPECIFICATIONS T to T , AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 3.3 V, I = 20 mA, unless otherwise noted. MIN MAX OUTFS Table 1. Parameter Min Typ Max Unit RESOLUTION 16 Bits 1 DC Accuracy Integral Nonlinearity ±6 LSB Differential Nonlinearity −6.5 ±3 +6.5 LSB ANALOG OUTPUT (for 1R and 2R Gain Setting Modes) Offset Error −0.025 ±0.01 +0.025 % of FSR Gain Error (with Internal Reference) −1.0 +1.0 % of FSR Gain Matching −1 ±0.1 +1 % of FSR 2 Full-Scale Output Current 2 20 mA Output Compliance Range −1.0 +1.25 V Output Resistance 200 kΩ Output Capacitance 3 pF Gain, Offset Cal DACs, Monotonicity Guaranteed REFERENCE OUTPUT Reference Voltage 1.14 1.20 1.26 V 3 Reference Output Current 100 nA REFERENCE INPUT Input Compliance Range 0.1 1.25 V Reference Input Resistance 7 kΩ Small Signal Bandwidth 0.5 MHz TEMPERATURE COEFFICIENTS Offset Drift 0 ppm of FSR/°C Gain Drift (with Internal Reference) 50 ppm of FSR/°C Reference Voltage Drift ±50 ppm/°C POWER SUPPLY AVDD Voltage Range 3.1 3.3 3.5 V 4 Analog Supply Current (I ) 72.5 76 mA AVDD I in SLEEP Mode 23.3 26 mA AVDD CLKVDD (PLL OFF) Voltage Range 3.1 3.3 3.5 V 4 Clock Supply Current (ICLKVDD) 8.5 10.0 mA CLKVDD (PLL ON) Clock Supply Current (I) 23.5 mA CLKVDD DVDD Voltage Range 3.1 3.3 3.5 V 4 Digital Supply Current (IDVDD) 34 41 mA 4 Nominal Power Dissipation 380 410 mW 5 P 1.75 W DIS P in PWDN 6.0 mW DIS Power Supply Rejection Ratio—AVDD ±0.4 % of FSR/V OPERATING RANGE −40 +85 °C 1 Measured at I driving a virtual ground. OUTA 2 Nominal full-scale current, IOUTFS, is 32× the IREF current. 3 Use an external amplifier to drive any external load. 4 100 MSPS fDAC with fOUT = 1 MHz, all supplies = 3.3 V, no interpolation, no modulation. 5 400 MSPS f , f = 50 MSPS, f /2 modulation, PLL enabled. DAC DATA S Rev. C | Page 5 of 60 AD9777 DYNAMIC SPECIFICATIONS TMIN to TMAX, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 0 V, IOUTFS = 20 mA, Interpolation = 2×, differential transformer-coupled output, 50 Ω doubly terminated, unless otherwise noted. Table 2. Parameter Min Typ Max Unit DYNAMIC PERFORMANCE Maximum DAC Output Update Rate (fDAC) 400 MSPS Output Settling Time (tST) (to 0.025%) 11 ns 1 Output Rise Time (10% to 90%) 0.8 ns 1 Output Fall Time (10% to 90%) 0.8 ns Output Noise (I = 20 mA) 50 pA/√Hz OUTFS AC LINEARITY—BASEBAND MODE Spurious-Free Dynamic Range (SFDR) to Nyquist (f = 0 dBFS) OUT fDATA = 100 MSPS, fOUT = 1 MHz 71 85 dBc fDATA = 65 MSPS, fOUT = 1 MHz 85 dBc fDATA = 65 MSPS, fOUT = 15 MHz 84 dBc f = 78 MSPS, f = 1 MHz 85 dBc DATA OUT f = 78 MSPS, f = 15 MHz 83 dBc DATA OUT f = 160 MSPS, f = 1 MHz 85 dBc DATA OUT fDATA = 160 MSPS, fOUT = 15 MHz 83 dBc Spurious-Free Dynamic Range within a 1 MHz Window fOUT = 0 dBFS, fDATA = 100 MSPS, fOUT = 1 MHz 73 99.1 dBc Two-Tone Intermodulation (IMD) to Nyquist (f = f = −6 dBFS) OUT1 OUT2 f = 65 MSPS, f = 10 MHz; f = 11 MHz 85 dBc DATA OUT1 OUT2 f = 65 MSPS, f = 20 MHz; f = 21 MHz 78 dBc DATA OUT1 OUT2 fDATA = 78 MSPS, fOUT1 = 10 MHz; fOUT2 = 11 MHz 85 dBc fDATA = 78 MSPS, fOUT1 = 20 MHz; fOUT2 = 21 MHz 78 dBc f = 160 MSPS, f = 10 MHz; f = 11 MHz 85 dBc DATA OUT1 OUT2 f = 160 MSPS, f = 20 MHz; f = 21 MHz 84 dBc DATA OUT1 OUT2 Total Harmonic Distortion (THD) fDATA = 100 MSPS, fOUT = 1 MHz; 0 dBFS −71 −83 dB Signal-to-Noise Ratio (SNR) fDATA = 78 MSPS, fOUT = 5 MHz; 0 dBFS 79 dB f = 160 MSPS, f = 5 MHz; 0 dBFS 75 dB DATA OUT Adjacent Channel Power Ratio (ACPR) WCDMA with 3.84 MHz BW, 5 MHz Channel Spacing IF = Baseband, fDATA = 76.8 MSPS 73 dBc IF = 19.2 MHz, fDATA = 76.8 MSPS 73 dBc Four-Tone Intermodulation 21 MHz, 22 MHz, 23 MHz, and 24 MHz at −12 dBFS (f = MSPS, Missing Center) 76 dBFS DATA AC LINEARITY—IF MODE Four-Tone Intermodulation at IF = 200 MHz 201 MHz, 202 MHz, 203 MHz, and 204 MHz at −12 dBFS (f = 160 MSPS, f = 320 MHz) 72 dBFS DATA DAC 1 Measured single-ended into 50 Ω load. Rev. C | Page 6 of 60 AD9777 DIGITAL SPECIFICATIONS TMIN to TMAX, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, DVDD = 3.3 V, IOUTFS = 20 mA, unless otherwise noted. Table 3. Parameter Min Typ Max Unit DIGITAL INPUTS Logic 1 Voltage 2.1 3 V Logic 0 Voltage 0 0.9 V Logic 1 Current −10 +10 µA Logic 0 Current −10 +10 µA Input Capacitance 5 pF CLOCK INPUTS Input Voltage Range 0 3 V Common-Mode Voltage 0.75 1.5 2.25 V Differential Voltage 0.5 1.5 V SERIAL CONTROL BUS Maximum SCLK Frequency (f) 15 MHz SLCK Mimimum Clock Pulse Width High (tPWH) 30 ns Mimimum Clock Pulse Width Low (tPWL) 30 ns Maximum Clock Rise/Fall Time 1 ms Minimum Data/Chip Select Setup Time (t) 25 ns DS Minimum Data Hold Time (t) 0 ns DH Maximum Data Valid Time (t) 30 ns DV RESET Pulse Width 1.5 ns Inputs (SDI, SDIO, SCLK, CSB) Logic 1 Voltage 2.1 3 V Logic 0 Voltage 0 0.9 V Logic 1 Current −10 +10 µA Logic 0 Current −10 +10 µA Input Capacitance 5 pF SDIO Output Logic 1 Voltage DRVDD − 0.6 V Logic 0 Voltage 0.4 V Logic 1 Current 30 50 mA Logic 0 Current 30 50 mA Rev. C | Page 7 of 60 AD9777 DIGITAL FILTER SPECIFICATIONS 20 Table 4. Half-Band Filter No. 1 (43 Coefficients) Tap Coefficient 0 1, 43 8 –20 2, 42 0 3, 41 −29 –40 4, 40 0 5, 39 67 –60 6, 38 0 –80 7, 37 −134 8, 36 0 –100 9, 35 244 10, 34 0 –120 0 0.5 1.0 1.5 2.0 11, 33 −414 f (NORMALIZED TO INPUT DATA RATE) 12, 32 0 OUT 13, 31 673 Figure 2. 2× Interpolating Filter Response 14, 30 0 15, 29 −1,079 20 16, 28 0 0 17, 27 1,772 18, 26 0 –20 19, 25 −3,280 20, 24 0 –40 21, 23 10,364 –60 22 16,384 –80 Table 5. Half-Band Filter No. 2 (19 Coefficients) –100 Tap Coefficient 1, 19 19 –120 0 0.5 1.0 1.5 2.0 2, 18 0 f (NORMALIZED TO INPUT DATA RATE) OUT 3, 17 −120 4, 16 0 Figure 3. 4× Interpolating Filter Response 5, 15 438 6, 14 0 20 7, 13 −1,288 0 8, 12 0 9, 11 5,047 –20 10 8,192 –40 Table 6. Half-Band Filter No. 3 (11 Coefficients) –60 Tap Coefficient –80 1, 11 7 2, 10 0 –100 3, 9 −53 4, 8 0 –120 04 2 68 5, 7 302 f (NORMALIZED TO INPUT DATA RATE) OUT 6 512 Figure 4. 8× Interpolating Filter Response Rev. C | Page 8 of 60 ATTENUATION (dBFS) ATTENUATION (dBFS) ATTENUATION (dBFS) 02706-005 02706-004 02706-003 AD9777 ABSOLUTE MAXIMUM RATINGS Table 7. Parameter With Respect To Min Max Unit AVDD, DVDD, CLKVDD AGND, DGND, CLKGND −0.3 +4.0 V AVDD, DVDD, CLKVDD AVDD, DVDD, CLKVDD −4.0 +4.0 V AGND, DGND, CLKGND AGND, DGND, CLKGND −0.3 +0.3 V REFIO, FSADJ1/FSADJ2 AGND −0.3 AVDD + 0.3 V IOUTA, IOUTB AGND −1.0 AVDD + 0.3 V P1B15 to P1B0, P2B15 to P2B0, RESET DGND −0.3 DVDD + 0.3 V DATACLK/PLL_LOCK DGND −0.3 DVDD + 0.3 V CLK+, CLK− CLKGND −0.3 CLKVDD + 0.3 V LPF CLKGND −0.3 CLKVDD + 0.3 V SPI_CSB, SPI_CLK, SPI_SDIO, SPI_SDO DGND −0.3 DVDD + 0.3 V Junction Temperature 125 °C Storage Temperature −65 +150 °C Lead Temperature (10 sec) 300 °C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. THERMAL CHARACTERISTICS Thermal Resistance 80-lead thin quad flat package, exposed pad [TQFP_EP] θ = 23.5°C/W (With thermal pad soldered to PCB) JA ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. C | Page 9 of 60 AD9777 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 1 60 FSADJ1 CLKVDD PIN 1 2 59 LPF FSADJ2 3 58 CLKVDD REFIO 4 57 CLKGND RESET CLK+ 5 56 SPI_CSB CLK– 6 55 SPI_CLK CLKGND 7 54 SPI_SDIO AD9777 DATACLK/PLL_LOCK 8 53 SPI_SDO TxDAC+ 9 52 DGND DGND TOP VIEW (Not to Scale) 10 51 DVDD DVDD 11 50 P1B15 (MSB) P2B0 (LSB) 12 49 P1B14 P2B1 P1B13 13 48 P2B2 P1B12 14 47 P2B3 P1B11 15 46 P2B4 16 45 P2B5 P1B10 17 44 DGND DGND 18 43 DVDD DVDD 19 42 P1B9 P2B6 20 41 P1B8 P2B7 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 NC = NO CONNECT Figure 5. Pin Configuration Rev. C | Page 10 of 60 P1B7 AVDD P1B6 AGND P1B5 AVDD P1B4 AGND DGND AVDD DVDD AGND P1B3 AGND P1B2 I OUTA1 P1B1 I OUTB1 AGND P1B0 (LSB) IQSEL/P2B15 (MSB) AGND ONEPORTCLK/P2B14 I OUTA2 P2B13 I OUTB2 P2B12 AGND DGND AGND DVDD AVDD P2B11 AGND P2B10 AVDD P2B9 AGND P2B8 AVDD 02706-002 AD9777 Table 8. Pin Function Description Pin No. Mnemonic Description 1, 3 CLKVDD Clock Supply Voltage. 2 LPF PLL Loop Filter. 4, 7 CLKGND Clock Supply Common. 5 CLK+ Differential Clock Input. 6 CLK− Differential Clock Input. 8 DATACLK/PLL_LOCK With the PLL enabled, this pin indicates the state of the PLL. A read of a Logic 1 indicates the PLL is in the locked state. Logic 0 indicates the PLL has not achieved lock. This pin may also be programmed to act as either an input or output (Address 02h, Bit 3) DATACLK signal running at the input data rate. 9, 17, 25, DGND Digital Common. 35, 44, 52 10, 18, 26, DVDD Digital Supply Voltage. 36, 43, 51 11 to 16, 19 P1B15 (MSB) to P1B0 (LSB) Port 1 Data Inputs. to 24, 27 to 30 31 IQSEL/P2B15 (MSB) In one-port mode, IQSEL = 1 followed by a rising edge of the differential input clock latches the data into the I channel input register. IQSEL = 0 latches the data into the Q channel input register. In two-port mode, this pin becomes the Port 2 MSB. 32 ONEPORTCLK/P2B14 With the PLL disabled and the AD9777 in one-port mode, this pin becomes a clock output that runs at twice the input data rate of the I and Q channels. This allows the AD9777 to accept and demux interleaved I and Q data to the I and Q input registers. 33, 34, 37 to P2B13 to P2B0 (LSB) Port 2 Data Inputs. 42, 45 to 50 53 SPI_SDO In the case where SDIO is an input, SDO acts as an output. When SDIO becomes an output, SDO enters a High-Z state. This pin can also be used as an output for the data rate clock. For more information, see the Two Port Data Input Mode section. 54 SPI_SDIO Bidirectional Data Pin. Data direction is controlled by Bit 7 of Register Address 00h. The default setting for this bit is 0, which sets SDIO as an input. 55 SPI_CLK Data input to the SPI port is registered on the rising edge of SPI_CLK. Data output on the SPI port is registered on the falling edge. 56 SPI_CSB Chip Select/SPI Data Synchronization. On momentary logic high, resets SPI port logic and initializes instruction cycle. 57 RESET Logic 1 resets all of the SPI port registers, including Address 00h, to their default values. A software reset can also be done by writing a Logic 1 to SPI Register 00h, Bit 5. However, the software reset has no effect on the bits in Address 00h. 58 REFIO Reference Output, 1.2 V Nominal. 59 FSADJ2 Full-Scale Current Adjust, Q Channel. 60 FSADJ1 Full-Scale Current Adjust, I Channel. 61, 63, 65, AVDD Analog Supply Voltage. 76, 78, 80 62, 64, 66, 67, AGND Analog Common. 70, 71, 74, 75, 77, 79 68, 69 IOUTB2, IOUTA2 Differential DAC Current Outputs, Q Channel. 72, 73 IOUTB1, IOUTA1 Differential DAC Current Outputs, I Channel. Rev. C | Page 11 of 60 AD9777 TERMINOLOGY Adjacent Channel Power Ratio (ACPR) Monotonicity A ratio in dBc between the measured power within a channel A DAC is monotonic if the output either increases or remains relative to its adjacent channel. constant as the digital input increases. Complex Image Rejection Offset Error In a traditional two-part upconversion, two images are created The deviation of the output current from the ideal of 0 is called around the second IF frequency. These images are redundant and offset error. For I , 0 mA output is expected when the inputs OUTA have the effect of wasting transmitter power and system bandwidth. are all 0. For I , 0 mA output is expected when all inputs are OUTB By placing the real part of a second complex modulator in series set to 1. with the first complex modulator, either the upper or lower Output Compliance Range frequency image near the second IF can be rejected. The range of allowable voltage at the output of a current-output Complex Modulation DAC. Operation beyond the maximum compliance limits may The process of passing the real and imaginary components of a cause either output stage saturation or breakdown, resulting in jωt signal through a complex modulator (transfer function = e = nonlinear performance. cosωt + jsinωt) and realizing real and imaginary components Pass Band on the modulator output. Frequency band in which any input applied therein passes Differential Nonlinearity (DNL) unattenuated to the DAC output. DNL is the measure of the variation in analog value, normalized to Power Supply Rejection full scale, associated with a 1 LSB change in digital input code. The maximum change in the full-scale output as the supplies Gain Error are varied from minimum to maximum specified voltages. The difference between the actual and ideal output span. The Signal-to-Noise Ratio (SNR) actual span is determined by the output when all inputs are set SNR is the ratio of the rms value of the measured output signal to 1 minus the output when all inputs are set to 0. to the rms sum of all other spectral components below the Glitch Impulse Nyquist frequency, excluding the first six harmonics and dc. The value for SNR is expressed in decibels. Asymmetrical switching times in a DAC give rise to undesired output transients that are quantified by a glitch impulse. It is Spurious-Free Dynamic Range specified as the net area of the glitch in pV-s. The difference, in dB, between the rms amplitude of the Group Delay output signal and the peak spurious signal over the specified Number of input clocks between an impulse applied at the bandwidth. device input and the peak DAC output current. A half-band FIR Settling Time filter has constant group delay over its entire frequency range. The time required for the output to reach and remain within a Impulse Response specified error band about its final value, measured from the Response of the device to an impulse applied to the input. start of the output transition. Interpolation Filter Stop-Band Rejection If the digital inputs to the DAC are sampled at a multiple rate of The amount of attenuation of a frequency outside the pass band f (interpolation rate), a digital filter can be constructed that applied to the DAC, relative to a full-scale signal applied at the DATA has a sharp transition band near f /2. Images that would DAC input within the pass band. DATA typically appear around f (output data rate) can be greatly DAC Temperature Drift suppressed. It is specified as the maximum change from the ambient (25°C) Linearity Error value to the value at either TMIN or TMAX. For offset and gain (Also called integral nonlinearity or INL) Linearity error is drift, the drift is reported in ppm of full-scale range (FSR) per defined as the maximum deviation of the actual analog output °C. For reference drift, the drift is reported in ppm per °C. from the ideal output, determined by a straight line drawn from Total Harmonic Distortion (THD) zero to full scale. THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured fundamental. It is expressed as a percentage or in decibels (dB). Rev. C | Page 12 of 60 AD9777 TYPICAL PERFORMANCE CHARACTERISTICS T = 25°C, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, IOUTFS = 20 mA, Interpolation = 2×, differential transformer-coupled output, 50 Ω doubly terminated, unless otherwise noted. 10 10 0 0 –10 –10 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 0 65 130 0 50 100 150 FREQUENCY (MHz) FREQUENCY (MHz) Figure 6. Single-Tone Spectrum @ fDATA = 65 MSPS with fOUT = fDATA/3 Figure 9. Single-Tone Spectrum @ fDATA = 78 MSPS with fOUT = fDATA/3 90 90 0dBFS 0dBFS 85 85 –6dBFS 80 80 75 75 –6dBFS 70 70 –12dBFS –12dBFS 65 65 60 60 55 55 50 50 0 5 10 15 20 25 30 0 5 10 15 20 25 30 FREQUENCY (MHz) FREQUENCY (MHz) Figure 7. In-Band SFDR vs. f @ f = 65 MSPS Figure 10. In-Band SFDR vs. f @ f = 78 MSPS OUT DATA OUT DATA 90 90 0dBFS 85 85 –12dBFS 0dBFS –12dBFS 80 80 75 75 70 70 –6dBFS –6dBFS 65 65 60 60 55 55 50 50 0 5 10 15 20 25 30 0 5 10 15 20 25 30 FREQUENCY (MHz) FREQUENCY (MHz) Figure 8. Out-of-Band SFDR vs. f @ f = 65 MSPS Figure 11. Out-of-Band SFDR vs. f @ f = 78 MSPS OUT DATA OUT DATA Rev. C | Page 13 of 60 SFDR (dBc) SFDR (dBc) AMPLITUDE (dBm) 02706-008 02706-007 02706-006 SFDR (dBc) SFDR (dBc) AMPLITUDE (dBm) 02706-011 02706-010 02706-009 AD9777 10 90 0dBFS 0 85 –10 80 –20 –3dBFS 75 –30 –6dBFS –40 70 –50 65 –60 60 –70 55 –80 50 –90 0 100 200 300 0 5 10 15 20 25 30 FREQUENCY (MHz) FREQUENCY (MHz) Figure 12. Single-Tone Spectrum @ f = 160 MSPS with f = f /3 Figure 15. Third-Order IMD Products vs. Two-Tone f @ f = 65 MSPS DATA OUT DATA OUT DATA 90 90 0dBFS 0dBFS 85 85 80 80 75 75 –6dBFS –3dBFS 70 70 –6dBFS –12dBFS 65 65 60 60 55 55 50 50 010 20 30 40 50 0 5 10 15 20 25 30 FREQUENCY (MHz) FREQUENCY (MHz) Figure 13. In-Band SFDR vs. fOUT @ fDATA = 160 MSPS Figure 16. Third-Order IMD Products vs. Two-Tone fOUT @ fDATA = 78 MSPS 90 90 0dBFS 85 85 80 80 –3dBFS 75 75 –6dBFS –12dBFS –6dBFS 70 70 65 65 0dBFS 60 60 55 55 50 50 010 20 30 40 50 0 10 20 30 405060 FREQUENCY (MHz) FREQUENCY (MHz) Figure 14. Out-of-Band SFDR vs. fOUT @ fDATA = 160 MSPS Figure 17. Third-Order IMD Products vs. Two-Tone fOUT @ fDATA = 160 MSPS Rev. C | Page 14 of 60 SFDR (dBc) SFDR (dBc) AMPLITUDE (dBm) 02706-014 02706-013 02706-012 IMD (dBc) IMD (dBc) IMD (dBc) 02706-017 02706-016 02706-015 AD9777 90 90 4× 0dBFS 85 85 –3dBFS 80 80 –6dBFS 8× 75 75 1× 70 70 2× 65 65 60 60 55 55 50 50 0 10 20 30 405060 3.1 3.2 3.3 3.4 3.5 FREQUENCY (MHz) AVDD (V) Figure 18. Third-Order IMD Products vs. Two-Tone fOUT and Interpolation Figure 21. Third-Order IMD Products vs. AVDD @ f = 10 MHz, OUT Rate, 1× fDATA = 160 MSPS, 2× fDATA = 160 MSPS, f = 320 MSPS, f = 160 MSPS DAC DATA 4× fDATA = 80 MSPS, 8× fDATA = 50 MSPS 90 90 8× 85 85 PLL OFF 80 80 4× 75 75 1× 70 70 2× PLL ON 65 65 60 60 55 55 50 50 –15 –10 –5 0 0 50 100 150 A (dBFS) INPUT DATA RATE (MSPS) OUT Figure 19. Third-Order IMD Products vs. Two-Tone A and Interpolation Figure 22. SNR vs. Data Rate for fOUT = 5 MHz OUT Rate, f = 50 MSPS in All Cases, 1× f = 50 MSPS, 2× f = 100 MSPS, DATA DAC DAC 4× f = 200 MSPS, 8× f = 400 MSPS DAC DAC 90 90 78MSPS 85 0dBFS 85 80 80 –6dBFS 75 75 f = 65MSPS DATA 160MSPS –12dBFS 70 70 65 65 60 60 55 55 50 50 3.1 3.2 3.3 3.4 3.5 –50 0 50 100 AVDD (V) TEMPERATURE (°C) Figure 20. SFDR vs. AVDD f = 10 MHz, f = 320 MSPS, f = 160 MSPS OUT DAC DATA Figure 23. SFDR vs. Temperature @ fOUT = fDATA/11 Rev. C | Page 15 of 60 SFDR (dBc) IMD (dBc) IMD (dBc) 02706-020 02706-019 02706-018 SNR (dB) SFDR (dBc) IMD (dBc) 02706-023 02706-022 02706-021 AD9777 0 0 –10 –20 –20 –30 –40 –40 –50 –60 –60 –70 –80 –80 –90 –100 –100 0 50 100 150 0 5 10 15 20 25 30 35 40 45 FREQUENCY (MHz) FREQUENCY (MHz) Figure 27. Two-Tone IMD Performance, f = 90 MSPS, Interpolation = 4× Figure 24. Single-Tone Spurious Performance, f = 10 MHz, DATA OUT f = 150 MSPS, No Interpolation DATA 0 0 –10 –20 –20 –30 –40 –40 –50 –60 –60 –70 –80 –80 –90 –100 –100 0 50 100 150 200 250 300 010 20 30 40 50 FREQUENCY (MHz) FREQUENCY (MHz) Figure 25. Two-Tone IMD Performance, Figure 28. Single-Tone Spurious Performance, f = 10 MHz, OUT f = 150 MSPS, No Interpolation f = 80 MSPS, Interpolation = 4× DATA DATA 0 0 –10 –20 –20 –30 –40 –40 –50 –60 –60 –70 –80 –80 –90 –100 –100 0 50 100 150 200 250 300 0 5 10 15 20 25 FREQUENCY (MHz) FREQUENCY (MHz) Figure 26. Single-Tone Spurious Performance, f = 10 MHz, Figure 29. Two-Tone IMD Performance, f = 10 MHz, OUT OUT f = 150 MSPS, Interpolation = 2× f = 50 MSPS, Interpolation = 8× DATA DATA Rev. C | Page 16 of 60 AMPLITUDE (dBm) AMPLITUDE (dBm) AMPLITUDE (dBm) 02706-026 02706-025 02706-024 AMPLITUDE (dBm) AMPLITUDE (dBm) AMPLITUDE (dBm) 02706-029 02706-028 02706-027 AD9777 0 0 –10 –10 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 –100 0 100 200 300 400 04 2006080 FREQUENCY (MHz) FREQUENCY (MHz) Figure 30. Single-Tone Spurious Performance, f = 10 MHz, Figure 31. Eight-Tone IMD Performance, f = 160 MSPS, Interpolation = 8x OUT DATA f = 50 MSPS, Interpolation = 8× DATA Rev. C | Page 17 of 60 AMPLITUDE (dBm) 02706-030 AMPLITUDE (dBm) 02706-031 AD9777 MODE CONTROL (VIA SPI PORT) 1 Table 9. Mode Control via SPI Port Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 00h SDIO LSB, MSB First Software Sleep Mode Power-Down 1R/2R Mode PLL_LOCK Bidirectional 0 = MSB Reset on Logic 1 Mode Logic 1 DAC Output Indicator 0 = Input 1 = LSB Logic 1 Shuts Down Shuts Down All Current Set by 1 = I/O the DAC Digital and One or Two Output Analog External Currents Functions Resistors 0 = 2R, 1 = 1R −jωt 01h Filter Filter Modulation Modulation 0 = e DATACLK/ 0 = No Zero 1 = Real Mix +jωt 2 Interpolation Interpolation Mode Mode Stuffing on Mode 1 = e PLL_LOCK Rate Rate (None, fS/2, (None, fS/2, Interpolation 0 = Complex Select (1×, 2×, (1×, 2×, f /4, f /8) f /4, f /8) Mix Mode 0 = S S S S Filters, Logic 1 4×, 8×) 4×, 8×) PLL_LOCK Enables Zero Stuffing 1 = DATACLK 02h DATACLK DATACLK ONEPORTCLK IQSEL Q First 0 = Signed 0 = Two-Port Input Data Mode Driver Invert Invert Invert 0 = I First 1 = 1 = One-Port Strength 0 = No 0 = No Invert 0 = No 1 = Q First Unsigned Mode Invert 1 = Invert Invert 1 = Invert 1 = Invert 2 03h Data Rate PLL Divide PLL Divide Clock (Prescaler) (Prescaler) Output Ratio Ratio 04h 0 = PLL 0 = Automatic PLL PLL PLL 2 Charge Charge Charge OFF Charge Pump Pump Pump Pump 1 = PLL ON Control 1 = Control Control Control Programmable 05h IDAC IDAC IDAC IDAC IDAC IDAC IDAC IDAC Fine Gain Fine Gain Fine Gain Fine Gain Fine Gain Fine Gain Fine Gain Fine Gain Adjustment Adjustment Adjustment Adjustment Adjustment Adjustment Adjustment Adjustment 06h IDAC IDAC IDAC IDAC Coarse Gain Coarse Gain Coarse Gain Coarse Gain Adjustment Adjustment Adjustment Adjustment 07h IDAC Offset IDAC Offset IDAC Offset IDAC Offset IDAC Offset IDAC Offset IDAC Offset IDAC Offset Adjustment Adjustment Adjustment Adjustment Adjustment Adjustment Adjustment Adjustment Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 08h IDAC I IDAC Offset IDAC Offset OFFSET Direction Adjustment Adjustment Bit 1 Bit 0 0 = IOFFSET on IOUTA 1 = I on OFFSET I B OUT 09h QDAC QDAC QDAC QDAC QDAC QDAC QDAC QDAC Fine Gain Fine Gain Fine Gain Fine Gain Fine Gain Fine Gain Fine Gain Fine Gain Adjustment Adjustment Adjustment Adjustment Adjustment Adjustment Adjustment Adjustment Rev. C | Page 18 of 60 AD9777 Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0Ah QDAC QDAC QDAC QDAC Coarse Gain Coarse Gain Coarse Gain Coarse Gain Adjustment Adjustment Adjustment Adjustment 0Bh QDAC Offset QDAC Offset QDAC QDAC Offset QDAC Offset QDAC Offset QDAC QDAC Adjustment Adjustment Offset Adjustment Adjustment Adjustment Offset Offset Bit 9 Bit 8 Adjustment Bit 6 Bit 5 Bit 4 Adjustment Adjustment Bit 7 Bit 3 Bit 2 0Ch QDAC IOFFSET QDAC QDAC Direction Offset Offset 0 = I on Adjustment Adjustment OFFSET Bit 1 Bit 0 IOUTA 1 = IOFFSET on I OUTB 0Dh Version Version Version Version Register Register Register Register 1 Default values are shown in bold. 2 For more information, see the Two Port Data Input Mode section. Rev. C | Page 19 of 60 AD9777 Bit 3: Logic 1 enables zero stuffing mode for interpolation filters. REGISTER DESCRIPTION Address 00h Bit 2: Default (1) enables the real mix mode. The I and Q data channels are individually modulated by f /2, f /4, or f /8 after S S S Bit 7: Logic 0 (default) causes the SPI_SDIO pin to act as an the interpolation filters. However, no complex modulation is input during the data transfer (Phase 2) of the communications done. In the complex mix mode (Logic 0), the digital cycle. When set to 1, SPI_SDIO can act as an input or output, modulators on the I and Q data channels are coupled to create a depending on Bit 7 of the instruction byte. digital complex modulator. When the AD9777 is applied in Bit 6: Logic 0 (default). Determines the direction (LSB/MSB conjunction with an external quadrature modulator, rejection can be achieved of either the higher or lower frequency image first) of the communications and data transfer communications around the second IF frequency (that is, the LO of the analog cycles. Refer to the MSB/LSB Transfers section for more details. quadrature modulator external to the AD9777) according to the Bit 5: Writing a 1 to this bit resets the registers to their default bit value of Register 01h, Bit 1. values and restarts the chip. The RESET bit always reads back 0. Bit 1: Logic 0 (default) causes the complex modulation to be of Register Address 00h bits are not cleared by this software reset. −jωt the form e , resulting in the rejection of the higher frequency However, a high level at the RESET pin forces all registers, image when the AD9777 is used with an external quadrature including those in Address 00h, to their default state. modulator. A Logic 1 causes the modulation to be of the form +jωt Bit 4: Sleep Mode. A Logic 1 to this bit shuts down the DAC e , which causes rejection of the lower frequency image. output currents. Bit 0: In two-port mode, a Logic 0 (default) causes Pin 8 to act as a lock indicator for the internal PLL. A Logic 1 in this register Bit 3: Power-Down. Logic 1 shuts down all analog and digital causes Pin 8 to act as a DATACLK. For more information, see functions except for the SPI port. the Two Port Data Input Mode section. Bit 2: 1R/2R Mode. The default (0) places the AD9777 in two resistor mode. In this mode, the I currents for the I and Q Address 02h REF DAC references are set separately by the R resistors on SET Bit 7: Logic 0 (default) causes data to be accepted on the inputs FSADJ2 and FSADJ1 (Pins 59 and 60). In 2R mode, assuming as twos complement binary. Logic 1 causes data to be accepted the coarse gain setting is full scale and the fine gain setting is 0, as straight binary. IFULLSCALE1 = 32 × VREF/FSADJ1 and IFULLSCALE2 = 32 × VREF/FSADJ2. With this bit set to 1, the reference currents for Bit 6: Logic 0 (default) places the AD9777 in two-port mode. I both I and Q DACs are controlled by a single resistor on Pin 60. and Q data enters the AD9777 via Ports 1 and 2, respectively. A I in one resistor mode for both the I and Q DACs is half FULLSCALE Logic 1 places the AD9777 in one-port mode in which of what it would be in 2R mode, assuming all other conditions interleaved I and Q data is applied to Port 1. See Table 8 for (R , register settings) remain unchanged. The full-scale SET detailed information on how to use the DATACLK/PLL_LOCK, current of each DAC can still be set to 20 mA by choosing a IQSEL, and ONEPORTCLK modes. resistor of half the value of the RSET value used in 2R mode. Bit 5: DATACLK Driver Strength. With the internal PLL Bit 1: PLL_LOCK Indicator. When the PLL is enabled, reading disabled and this bit set to Logic 0, it is recommended that this bit gives the status of the PLL. A Logic 1 indicates the PLL DATACLK be buffered. When this bit is set to Logic 1, is locked. A Logic 0 indicates an unlocked state. DATACLK acts as a stronger driver capable of driving small Address 01h capacitive loads. Bit 7, Bit 6: This is the filter interpolation rate according to the Bit 4: Logic 0 (default). A value of 1 inverts DATACLK at Pin 8. following table. Bit 2: Logic 0 (default). A value of 1 inverts ONEPORTCLK 00 1× at Pin 32. 01 2× 10 4× Bit 1: Logic 0 (default) causes IQSEL = 0 to direct input data to the I channel, while IQSEL = 1 directs input data to the Q 11 8× channel. Bit 5 and Bit 4: This is the modulation mode according to the following table. Bit 0: Logic 0 (default) defines IQ pairing as IQ, IQ…, while 00 none programming a Logic 1 causes the pair ordering to 01 f /2 S be QI, QI… 10 fS/4 11 fS/8 Rev. C | Page 20 of 60 AD9777 Address 03h Address 05h, 09h Bit 7: This allows the data rate clock (divided down from the Bit 7, Bit 6, Bit 5, Bit 4, Bit 3, Bit 2, Bit 1, and Bit 0: These bits DAC clock) to be output at either the DATACLK/PLL_LOCK represent an 8-bit binary number (Bit 7 MSB) that defines the pin (Pin 8) or at the SPI_SDO pin (Pin 53). The default of 0 in fine gain adjustment of the I (05h) and Q (09h) DAC according this register enables the data rate clock at DATACLK/ to Equation 1. PLL_LOCK, while a 1 in this register causes the data rate clock Address 06h, 0Ah to be output at SPI_SDO. For more information, see the Two Port Data Input Mode section. Bit 3, Bit 2, Bit 1, and Bit 0: These bits represent a 4-bit binary number (Bit 3 MSB) that defines the coarse gain adjustment of Bit 1, Bit 0: Setting this divide ratio to a higher number allows the I (06h) and Q (0Ah) DACs according to Equation 1. the VCO in the PLL to run at a high rate (for best performance) while the DAC input and output clocks run substantially slower. Address 07h, 0Bh The divider ratio is set according to the following table. Bit 7, Bit 6, Bit 5, Bit 4, Bit 3, Bit 2, Bit 1, and Bit 0: These bits 00 ÷1 are used in conjunction with Address 08h, 0Ch, Bits 1, 0. 01 ÷2 Address 08h, 0Ch 10 ÷4 Bit 1 and Bit 0: The 10 bits from these two address pairs (07h, 08h and 0Bh, 0Ch) represent a 10-bit binary number that 11 ÷8 defines the offset adjustment of the I and Q DACs according to Address 04h Equation 1. (07h, 0Bh–Bit 7 MSB/08h, 0Ch–Bit 0 LSB). Bit 7: Logic 0 (default) disables the internal PLL. Logic 1 Address 08h, 0Ch enables the PLL. Bit 7: This bit determines the direction of the offset of the I Bit 6: Logic 0 (default) sets the charge pump control to (08h) and Q (0Ch) DACs. A Logic 0 applies a positive offset automatic. In this mode, the charge pump bias current is current to IOUTA, while a Logic 1 applies a positive offset current controlled by the divider ratio defined in Address 03h, Bits 1 to IOUTB. The magnitude of the offset current is defined by the and 0. Logic 1 allows the user to manually define the charge bits in Addresses 07h, 0Bh, 08h, 0Ch according to Equation 1. pump bias current using Address 04h, Bits 2, 1, and 0. Adjusting Equation 1 shows I and I as a function of fine gain, OUTA OUTB the charge pump bias current allows the user to optimize the coarse gain, and offset adjustment when using 2R mode. In 1R noise/settling performance of the PLL. mode, the current I is created by a single FSADJ resistor REF (Pin 60). This current is divided equally into each channel so that Bit 2, Bit 1, Bit 0: With the charge pump control set to manual, a scaling factor of one-half must be added to these equations for these bits define the charge pump bias current according to the full-scale currents for both DACs and the offset. following table. 000 50 µA 001 100 µA 010 200 µA 011 400 µA 111 800 µA ⎡ 6× I COARSE +1 3× I FINE ⎤ ⎡ 1024 DATA ⎤ ⎛ ⎞ ⎛ ⎞ ⎛ REF⎞ ⎛ REF⎞⎛ ⎞ ⎛ ⎞ I = − × (A) ⎜ ⎟ ⎜ ⎟ ⎜ ⎟ ⎜ ⎟⎜ ⎟ ⎜ ⎟ OUTA ⎢ ⎥ ⎢ 16 ⎥ 8 16 32 256 24 2 ⎝ ⎠ ⎝ ⎠ ⎝ ⎠⎝ ⎠ ⎝ ⎠ ⎝ ⎠ ⎣ ⎦ ⎣ ⎦ 16 ⎡ ⎤ 6× I COARSE +1 3× I FINE 1024 ⎛ 2 − DATA −1⎞ ⎡ ⎤ ⎛ REF⎞⎛ ⎞ ⎛ REF⎞⎛ ⎞ ⎛ ⎞ ⎜ ⎟ I = − × (A) (1) ⎜ ⎟⎜ ⎟ ⎜ ⎟⎜ ⎟ ⎢⎜ ⎟ ⎥ OUTB 16 ⎢ ⎥ ⎜ ⎟ 8 16 32 256 24 2 ⎝ ⎠⎝ ⎠ ⎝ ⎠⎝ ⎠ ⎝ ⎠ ⎣ ⎦ ⎢ ⎥ ⎝ ⎠ ⎣ ⎦ OFFSET ⎛ ⎞ I = 4× I (A) ⎜ ⎟ OFFSET REF 1024 ⎝ ⎠ Rev. C | Page 21 of 60 AD9777 FUNCTIONAL DESCRIPTION The AD9777 dual interpolating DAC consists of two data SDO (PIN 53) channels that can be operated independently or coupled to form SDIO (PIN 54) a complex modulator in an image reject transmit architecture. AD9777 SPI PORT INTERFACE SPI_CLK (PIN 55) Each channel includes three FIR filters, making the AD9777 capable of 2×, 4×, or 8× interpolation. High speed input and CSB (PIN 56) output data rates can be achieved within the following limitations. Figure 32. SPI Port Interface Interpolation Rate Input Data Rate DAC Sample Rate SERIAL INTERFACE FOR REGISTER CONTROL (MSPS) (MSPS) (MSPS) The AD9777 serial port is a flexible, synchronous serial 1× 160 160 communications port that allows easy interface to many 2× 160 320 industry-standard microcontrollers and microprocessors. The 4× 100 400 serial I/O is compatible with most synchronous transfer 8× 50 400 formats, including both the Motorola SPI® and Intel® SSR Both data channels contain a digital modulator capable of protocols. The interface allows read/write access to all registers mixing the data stream with an LO of f /2, f /4, or f /8, DAC DAC DAC that configure the AD9777. Single- or multiple-byte transfers where fDAC is the output data rate of the DAC. A zero stuffing are supported as well as MSB first or LSB first transfer formats. feature is also included and can be used to improve pass-band The AD9777’s serial interface port can be configured as a single flatness for signals being attenuated by the SIN(x)/x pin I/O (SDIO) or two unidirectional pins for I/O (SDIO/SDO). characteristic of the DAC output. The speed of the AD9777, combined with its digital modulation capability, enables direct GENERAL OPERATION OF THE SERIAL INTERFACE IF conversion architectures at 70 MHz and higher. There are two phases to a communication cycle with the AD9777. Phase 1 is the instruction cycle, which is the writing of The digital modulators on the AD9777 can be coupled to form an instruction byte into the AD9777 coincident with the first a complex modulator. By using this feature with an external eight SCLK rising edges. The instruction byte provides the analog quadrature modulator, such as the Analog Devices AD9777 serial port controller with information regarding the AD8345, an image rejection architecture can be enabled. To data transfer cycle, which is Phase 2 of the communication optimize the image rejection capability, as well as LO feed- cycle. The Phase 1 instruction byte defines whether the upcom- through in this architecture, the AD9777 offers programmable ing data transfer is read or write, the number of bytes in the (via the SPI port) gain and offset adjust for each DAC. data transfer, and the starting register address for the first byte of the data transfer. The first eight SCLK rising edges of each Also included on the AD9777 are a phase-locked loop (PLL) communication cycle are used to write the instruction byte into clock multiplier and a 1.20 V band gap voltage reference. With the AD9777. the PLL enabled, a clock applied to the CLK+/CLK− inputs is frequency multiplied internally and generates all necessary A Logic 1 on the SPI_CSB pin, followed by a logic low, resets internal synchronization clocks. Each 16-bit DAC provides two the SPI port timing to the initial state of the instruction cycle. complementary current outputs whose full-scale currents can This is true regardless of the present state of the internal be determined either from a single external resistor or inde- registers or the other signal levels present at the inputs to the pendently from two separate resistors (see the 1R/2R Mode SPI port. If the SPI port is in the middle of an instruction cycle section). The AD9777 features a low jitter, differential clock or a data transfer cycle, none of the present data is written. input that provides excellent noise rejection while accepting a sine or square wave input. Separate voltage supply inputs are The remaining SCLK edges are for Phase 2 of the provided for each functional block to ensure optimum noise communication cycle. Phase 2 is the actual data transfer and distortion performance. between the AD9777 and the system controller. Phase 2 of the communication cycle is a transfer of one to four data bytes, as Sleep and power-down modes can be used to turn off the DAC determined by the instruction byte. Normally, using one multi- output current (sleep) or the entire digital and analog sections byte transfer is the preferred method. However, single byte data (power-down) of the chip. A SPI-compliant serial port is used transfers are useful to reduce CPU overhead when register to program the many features of the AD9777. Note that in access requires one byte only. Registers change immediately power-down mode, the SPI port is the only section of the chip upon writing to the last bit of each transfer byte. still active. Rev. C | Page 22 of 60 02706-032 AD9777 INSTRUCTION BYTE SPI_CSB (Pin 56)—Chip Select The instruction byte contains the information shown below. Active low input starts and gates a communication cycle. It allows more than one device to be used on the same serial N1 N0 Description 0 0 Transfer 1 Byte communications lines. The SPI_SDO and SPI_SDIO pins go to a high impedance state when this input is high. Chip select 0 1 Transfer 2 Bytes should stay low during the entire communication cycle. 1 0 Transfer 3 Bytes 1 1 Transfer 4 Bytes SPI_SDIO (Pin 54)—Serial Data I/O R/W Data is always written into the AD9777 on this pin. However, Bit 7 of the instruction byte determines whether a read or a this pin can be used as a bidirectional data line. Bit 7 of Register write data transfer occurs after the instruction byte write. Logic Address 00h controls the configuration of this pin. The default 1 indicates read operation. Logic 0 indicates a write operation. is Logic 0, which configures the SPI_SDIO pin as unidirectional. N1, N0 SPI_SDO (Pin 53)—Serial Data Out Bit 6 and Bit 5 of the instruction byte determine the number of bytes to be transferred during the data transfer cycle. The bit Data is read from this pin for protocols that use separate lines decodes are shown in the following table. for transmitting and receiving data. In the case where the MSB LSB AD9777 operates in a single bidirectional I/O mode, this pin I7 I6 I5 I4 I3 I2 I1 I0 does not output data and is set to a high impedance state. R/W N1 N0 A4 A3 A2 A1 A0 MSB/LSB TRANSFERS A4, A3, A2, A1, A0 The AD9777 serial port can support both most significant bit Bit 4, Bit 3, Bit 2, Bit 1, and Bit 0 of the instruction byte (MSB) first or least significant bit (LSB) first data formats. This determine which register is accessed during the data transfer functionality is controlled by the LSB first bit in Register 0. The portion of the communications cycle. For multibyte transfers, default is MSB first. this address is the starting byte address. The remaining register addresses are generated by the AD9777. When this bit is set active high, the AD9777 serial port is in LSB first format. In LSB first mode, the instruction byte and data SERIAL INTERFACE PORT PIN DESCRIPTIONS bytes must be written from LSB to MSB. In LSB first mode, the SPI_CLK (Pin 55)—Serial Clock serial port internal byte address generator increments for each byte of the multibyte communication cycle. The serial clock pin is used to synchronize data to and from the AD9777 and to run the internal state machines. SPI_CLK When this bit is set default low, the AD9777 serial port is in maximum frequency is 15 MHz. All data input to the AD9777 MSB first format. In MSB first mode, the instruction byte and is registered on the rising edge of SPI_CLK. All data is driven data bytes must be written from MSB to LSB. In MSB first out of the AD9777 on the falling edge of SCLK. mode, the serial port internal byte address generator decre- ments for each byte of the multibyte communication cycle. When incrementing from 1Fh, the address generator changes to 00h. When decrementing from 00h, the address generator changes to 1Fh. Rev. C | Page 23 of 60 AD9777 INSTRUCTION CYCLE DATA TRANSFER CYCLE CS SCLK SDIO R/W I6 I5 I4 I3 I2 I1 I0 D7 D6 D2 D1 D0 (N) (N) N N 0 0 0 D7 D6 D2 D1 D0 SDO N N 0 0 0 Figure 33. Serial Register Interface Timing MSB First INSTRUCTION CYCLE DATA TRANSFER CYCLE CS SCLK SDIO I0 I1 I2 I3 I4 I5 I6 R/W D0 D1 D2 D6 D7 (N) (N) 0 0 0 N N SDO D0 D1 D2 D6 D7 0 0 0 N N Figure 34. Serial Register Interface Timing LSB First t t DS SCLK CS t t PWH PWL SCLK t t DS DH T SDIO INSTRUCTION BIT 7 INSTRUCTION BIT 6 Figure 35. Timing Diagram for Register Write to AD9777 CS SCLK t DV SDIO DATA BIT N DATA BIT N–1 SDO Figure 36. Timing Diagram for Register Read from AD9777 Rev. C | Page 24 of 60 02706-036 02706-035 02706-033 02706-034 AD9777 The offset control defines a small current that can be added to NOTES ON SERIAL PORT OPERATION I or I (not both) on the IDAC and QDAC. The selection OUTA OUTB The AD9777 serial port configuration bits reside in Bit 6 and of which I this offset current is directed toward is program- OUT Bit 7 of Register Address 00h. It is important to note that the mable via Register 08h, Bit 7 (IDAC) and Register 0Ch, Bit 7 configuration changes immediately upon writing to the last bit (QDAC). Figure 42 shows the scale of the offset current that can of the register. For multibyte transfers, writing to this register be added to one of the complementary outputs on the IDAC may occur during the middle of the communication cycle. Care and QDAC. Offset control can be used for suppression of LO must be taken to compensate for this new configuration for the leakage resulting from modulation of dc signal components. If remaining bytes of the current communication cycle. the AD9777 is dc-coupled to an external modulator, this feature can be used to cancel the output offset on the AD9777 as well as The same considerations apply to setting the reset bit in the input offset on the modulator. Figure 42 shows a typical Register Address 00h. All other registers are set to their default values, but the software reset does not affect the bits in Register example of the effect that the offset control has on LO Address 00h. suppression. OFFSET It is recommended to use only single byte transfers when OFFSET CONTROL FINE DAC REGISTERS changing serial port configurations or initiating a software GAIN GAIN DAC reset. CONTROL REGISTERS FINE I IDAC OUTA1 A write to Bit 1, Bit 2, and Bit 3 of Address 00h with the same GAIN DAC 1.2VREF logic levels as for Bit 7, Bit 6, and Bit 5 (bit pattern: XY1001YX I OUTB1 REFIO binary) allows the user to reprogram a lost serial port configu- COARSE COARSE QDAC I OUTA2 GAIN GAIN 0.1µF ration and to reset the registers to their default values. A second DAC DAC I OUTB2 write to Address 00h with reset bit low and serial port configu- FSADJ1 ration as specified above (XY) reprograms the OSC IN OFFSET FSADJ2 OFFSET RSET1 CONTROL multiplier setting. A changed f frequency is stable after a SYSCLK DAC GAIN RSET2 REGISTERS CONTROL maximum of 200 f cycles (equals wake-up time). MCLK REGISTERS Figure 37. DAC Outputs, Reference Current Scaling, and Gain/Offset Adjust DAC OPERATION The dual 16-bit DAC output of the AD9777, along with the AVDD reference circuitry, gain, and offset registers, is shown in Figure 84µA 37 and Figure 38. Note that an external reference can be used by simply overdriving the internal reference with the external REFIO reference. Referring to the transfer functions in Equation 1, a 7kΩ reference current is set by the internal 1.2 V reference, the external R resistor, and the values in the coarse gain register. SET 0.7V The fine gain DAC subtracts a small amount from this and the result is input to IDAC and QDAC, where it is scaled by an Figure 38. Internal Reference Equivalent Circuit amount equal to 1024/24. Figure 39 and Figure 40 show the scaling effect of the coarse and fine adjust DACs. IDAC and 25 QDAC are PMOS current source arrays, segmented in a 5-4-7 configuration. The five MSB control an array of 31 current 20 sources. The next four bits consist of 15 current sources whose values are all equal to 1/16 of an MSB current source. The 7 2R MODE LSBs are binary weighted fractions of the middle bits’ current 15 sources. All current sources are switched to either I or I , OUTA OUTB depending on the input code. 10 The fine adjustment of the gain of each channel allows for im- 1R MODE proved balance of QAM modulated signals, resulting in improved 5 modulation accuracy and image rejection. In the Interfacing with the AD8345 Quadrature Modulator section, the performance 0 data shows to what degree image rejection can be improved when 01 5 01520 the AD9777 is used with an AD8345 quadrature modulator from COARSE GAIN REGISTER CODE Ω) (ASSUMING RSET1, RSET2 = 1.9k Analog Devices, Inc. Figure 39. Coarse Gain Effect on I FULLSCALE Rev. C | Page 25 of 60 COARSE REFERENCE CURRENT (mA) 02706-038 02706-039 02706-037 AD9777 0 0 –0.5 –10 1R MODE OFFSET REGISTER 1 ADJUSTED –20 –1.0 –30 2R MODE –1.5 –40 –50 –2.0 –60 –2.5 OFFSET REGISTER 2 ADJUSTED, WITH OFFSET –70 REGISTER 1 SET TO OPTIMIZED VALUE –3.0 –80 0 200 400 600 800 1000 –1024 –768 –512 –256 0 256 512 768 1024 FINE GAIN REGISTER CODE DAC1, DAC2 (OFFSET REGISTER CODES) (ASSUMING RSET1, RSET2 = 1.9kΩ) Figure 42. Offset Adjust Control, Effect on LO Suppression Figure 40. Fine Gain Effect on IFULLSCALE In Figure 42, the negative scale represents an offset added to 1R/2R MODE IOUTB, while the positive scale represents an offset added to IOUTA In 2R mode, the reference current for each channel is set of the respective DAC. Offset Register 1 corresponds to IDAC, independently by the FSADJ resistor on that channel. The while Offset Register 2 corresponds to QDAC. Figure 42 AD9777 can be programmed to derive its reference current represents the AD9777 synthesizing a complex signal that is from a single resistor on Pin 60 by putting the part into 1R then dc-coupled to an AD8345 quadrature modulator with an mode. The transfer functions in Equation 1 are valid for 2R LO of 800 MHz. The dc coupling allows the input offset of the mode. In 1R mode, the current developed in the single FSADJ AD8345 to be calibrated out as well. The LO suppression at the resistor is split equally between the two channels. The result is AD8345 output was optimized first by adjusting Offset that in 1R mode, a scale factor of 1/2 must be applied to the Register 1 in the AD9777. When an optimal point was found formulas in Equation 1. The full-scale DAC current in 1R mode (roughly Code 54), this code was held in Offset Register 1, and can still be set to as high as 20 mA by using the internal 1.2 V Offset Register 2 was adjusted. The resulting LO suppression is reference and a 950 Ω resistor instead of the 1.9 kΩ resistor 70 dBFS. These are typical numbers, and the specific code for typically used in 2R mode. optimization varies from part to part. CLOCK INPUT CONFIGURATION 5 The clock inputs to the AD9777 can be driven differentially or single-ended. The internal clock circuitry has supply and 4 ground (CLKVDD, CLKGND) separate from the other supplies on the chip to minimize jitter from internal noise sources. 3 Figure 43 shows the AD9777 driven from a single-ended clock 2R MODE source. The CLK+/CLK− pins form a differential input 2 (CLKIN) so that the statically terminated input must be dc- biased to the midswing voltage level of the clock driven input. 1R MODE 1 AD9777 R SERIES 0 0 200 400 600 800 1000 CLK+ 0 COARSE GAIN REGISTER CODE (ASSUMING RSET1, RSET2 = 1.9kΩ) CLKVDD Figure 41. DAC Output Offset Current V CLK– THRESHOLD 0.1µF CLKGND Figure 43. Single-Ended Clock Driving Clock Inputs Rev. C | Page 26 of 60 OFFSET CURRENT (mA) FINE REFERENCE CURRENT (mA) 02706-041 02706-040 LO SUPPRESSION (dBFS) 02706-043 02706-042 AD9777 A configuration for differentially driving the clock inputs is PROGRAMMABLE PLL given in Figure 44. DC-blocking capacitors can be used to CLKIN can function either as an input data rate clock (PLL couple a clock driver output whose voltage swings exceed enabled) or as a DAC data rate clock (PLL disabled) according CLKVDD or CLKGND. If the driver voltage swings are within to the state of Address 02h, Bit 7 in the SPI port register. The the supply range of the AD9777, the dc-blocking capacitors and internal operation of the AD9777 clock circuitry in these two bias resistors are not necessary. modes is illustrated in Figure 45 and Figure 46. AD9777 The PLL clock multiplier and distribution circuitry produce the 1kΩ 0.1µF necessary internal synchronized 1×, 2×, 4×, and 8× clocks for CLK+ the rising edge triggered latches, interpolation filters, 1kΩ modulators, and DACs. This circuitry consists of a phase ECL/PECL 0.1µF CLKVDD 1kΩ detector, charge pump, voltage controlled oscillator (VCO), 0.1µF CLK– prescaler, clock distribution, and SPI port control. The charge 1kΩ pump, VCO, differential clock input buffer, phase detector, CLKGND prescaler, and clock distribution are all powered from CLKVDD. PLL lock status is indicated by the logic signal at the Figure 44. Differential Clock Driving Clock Inputs PLL_LOCK pin, as well as by the status of Bit 1, Register 00h. To ensure optimum phase noise performance from the PLL A transformer, such as the T1-1T from Mini-Circuits, can also clock multiplier and distribution, CLKVDD should originate be used to convert a single-ended clock to differential. This from a clean analog supply. Table 10 defines the minimum method is used on the AD9777 evaluation board so that an input data rates versus the interpolation and PLL divider external sine wave with no dc offset can be used as a differential setting. If the input data rate drops below the defined minimum clock. under these conditions, VCO phase noise can increase significantly. The VCO speed is a function of the input data PECL/ECL drivers require varying termination networks, the rate, the interpolation rate, and the VCO prescaler, according to details of which are left out of Figure 43 and Figure 44 but can the following function: be found in application notes such as AND8020/D from On Semiconductor. These networks depend on the assumed VCO Speed() MHz = transmission line impedance and power supply voltage of the Input Data Rate() MHz × Interpolation Rate × Prescaler clock driver. Optimum performance of the AD9777 is achieved when the driver is placed very close to the AD9777 clock inputs, CLK+ CLK– thereby negating any transmission line effects such as reflec- PLLVDD tions due to mismatch. PLL_LOCK 1 = LOCK AD9777 0 = NO LOCK The quality of the clock and data input signals is important in achieving optimum performance. The external clock driver INTERPOLATION PHASE CHARGE circuitry should provide the AD9777 with a low jitter clock FILTERS, DETECTOR PUMP LPF MODULATORS, input that meets the minimum/maximum logic levels while AND DACS providing fast edges. Although fast clock edges help minimize 2 48 any jitter that manifests itself as phase noise on a reconstructed 1 CLOCK waveform, the high gain bandwidth product of the AD9777’s PRESCALER VCO INPUT DISTRIBUTION DATA clock input comparator can tolerate differential sine wave inputs CIRCUITRY LATCHES as low as 0.5 V p-p with minimal degradation of the output PLL DIVIDER INTERNAL SPI (PRESCALER) noise floor. CONTROL CONTROL REGISTERS INTERPOLATION PLL RATE CONTROL MODULATION CONTROL RATE (PLL ON) SPI PORT CONTROL Figure 45. PLL and Clock Circuitry with PLL Enabled Rev. C | Page 27 of 60 02706-044 02706-045 AD9777 Table 11. Required PLL Prescaler Ration vs. f DATA CLK+ CLK– f (MSPS) PLL Prescaler Ratio DATA PLL_LOCK 1 = LOCK 125 Disabled AD9777 0 = NO LOCK 125 Enabled Div 1 100 Enabled Div 2 INTERPOLATION PHASE CHARGE 75 Enabled Div 2 FILTERS, DETECTOR PUMP MODULATORS, 50 Enabled Div 4 AND DACS 2 48 0 1 CLOCK –10 PRESCALER VCO INPUT DISTRIBUTION DATA CIRCUITRY –20 LATCHES PLL DIVIDER –30 INTERNAL SPI (PRESCALER) CONTROL CONTROL –40 REGISTERS INTERPOLATION PLL RATE –50 MODULATION CONTROL CONTROL RATE (PLL ON) –60 SPI PORT CONTROL –70 Figure 46. PLL and Clock Circuitry with PLL Disabled –80 –90 In addition, if the zero stuffing option is enabled, the VCO doubles its speed again. Phase noise can be slightly higher with the PLL enabled. –100 Figure 47 illustrates typical phase noise performance of the AD9777 –110 012 3 45 with 2× interpolation and various input data rates. The signal FREQUENCY OFFSET (MHz) synthesized for the phase noise measurement was a single carrier at a Figure 47. Phase Noise Performance frequency of f /4. The repetitive nature of this signal eliminates DATA quantization noise and distortion spurs as a factor in the measure- ment. Although the curves blend in Figure 47, the different conditions are given for clarity in the table preceding Figure 47. Figure 47 also contains a table detailing PLL divider settings vs. interpolation rate and maximum and minimum f rates. Note that DATA maximum f rates of 160 MSPS are due to the maximum input DATA data rate of the AD9777. However, maximum rates of less than 160 MSPS and all minimum f rates are due to maximum and mini- DATA mum speeds of the internal PLL VCO. Figure 48 shows typical performance of the PLL lock signal (Pin 8 or Pin 53) when the PLL is in the process of locking. Table 10. PLL Optimization Interpolation Divider Minimum Maximum Rate Setting f f DATA DATA Figure 48. PLL_LOCK Output Signal (Pin 8) in the Process of Locking 1 1 32 160 (Typical Lock Time) 1 2 16 160 1 4 8 112 It is important to note that the resistor/capacitor needed for the 1 8 4 56 PLL loop filter is internal on the AD9777. This suffices unless 2 1 24 160 the input data rate is below 10 MHz, in which case an external 2 2 12 112 series RC is required between the LPF and CLKVDD pins. 2 4 6 56 2 8 3 28 4 1 24 100 4 2 12 56 4 4 6 28 4 8 3 14 8 1 24 50 8 2 12 28 8 4 6 14 8 8 3 7 Rev. C | Page 28 of 60 02706-046 PHASE NOISE (dBFS) 02706-047 02706-048 AD9777 35 POWER DISSIPATION 8× 30 The AD9777 has three voltage supplies: DVDD, AVDD, and 4× CLKVDD. Figure 49, Figure 50, and Figure 51 show the current 2× 25 required from each of these supplies when each is set to the 3.3 V nominal specified for the AD9777. Power dissipation (P ) D 20 can easily be extracted by multiplying the given curves by 3.3. As Figure 49 shows, I is very dependent on the input data 15 DVDD 1× rate, the interpolation rate, and the activation of the internal 10 digital modulator. IDVDD, however, is relatively insensitive to the modulation rate by itself. In Figure 50, IAVDD shows the same 5 type of sensitivity to data, interpolation rate, and the modulator function but to a much lesser degree (<10%). In Figure 51, 0 0 50 100 150 200 I varies over a wide range yet is responsible for only a CLKVDD f (MHz) DATA small percentage of the overall AD9777 supply current requirement. Figure 51. ICLKVDD vs. fDATA vs. Interpolation Rate, PLL Disabled 400 SLEEP/POWER-DOWN MODES 8×, (MOD. ON) 2×, (MOD. ON) 350 (Control Register 00h, Bit 3 and Bit 4) 4×, (MOD. ON) 300 The AD9777 provides two methods for programmable 8× 4× reduction in power savings. The sleep mode, when activated, 250 2× turns off the DAC output currents but the rest of the chip 200 remains functioning. When coming out of sleep mode, the 150 AD9777 immediately returns to full operation. Power-down mode, on the other hand, turns off all analog and digital 100 1× circuitry in the AD9777 except for the SPI port. When 50 returning from power-down mode, enough clock cycles must be allowed to flush the digital filters of random data acquired 0 during the power-down cycle. Note that optimal performance 0 50 100 150 200 with the PLL enabled is achieved with the UCO in the PLL f (MHz) DATA control loop running at 450 MHz to 550 MHz. Figure 49. I vs. f vs. Interpolation Rate, PLL Disabled DVDD DATA TWO PORT DATA INPUT MODE 76.0 4×, (MOD. ON) 8×, (MOD. ON) The digital data input ports can be configured as two 75.5 independent ports or as a single (one-port mode) port. In the 2×, (MOD. ON) 75.0 two-port mode, data at the two input ports is latched into the AD9777 on every rising edge of the data rate clock (DATACLK). 74.5 4× In addition, in the two-port mode, the AD9777 can be 8× 74.0 programmed to generate an externally available DATACLK for the purpose of data synchronization. This data rate clock can be 73.5 2× programmed to be available at either Pin 8 (DATACLK/ 73.0 PLL_LOCK) or Pin 53 (SPI_SDO). Because Pin 8 can also 1× function as a PLL lock indicator when the PLL is enabled, there 72.5 are several options for configuring Pin 8 and Pin 53. The 72.0 following information describes these options. 0 50 100 150 200 f (MHz) DATA PLL Off (Register 4, Bit 7 = 0) Figure 50. I vs. f vs. Interpolation Rate, PLL Disabled AVDD DATA Register 3, Bit 7 = 0; DATACLK out of Pin 8. Register 3, Bit 7 = 1; DATACLK out of Pin 53. PLL On (Register 4, Bit 7 = 1) Register 3, Bit 7 = 0, Register 1, Bit 0 = 0; PLL lock indicator out of Pin 8. Rev. C | Page 29 of 60 I (mA) I (mA) AVDD DVDD 02706-050 02706-049 I (mA) CLKVDD 02706-051 AD9777 t OD Register 3, Bit 7 = 1, Register 1, Bit 0 = 0; PLL lock indicator out of Pin 53. Register 3, Bit 7 = 0, Register 1, Bit 0 = 1; DATACLK out of Pin 8. CLKIN Register 3, Bit 7 = 1, Register 1, Bit 0 = 1; DATACLK out of Pin 53. In one-port mode, P2B14 and P2B15 from input data port two are redefined as IQSEL and ONEPORTCLK, respectively. The DATACLK input data in one-port mode is steered to one of the two inter- nal data channels based on the logic level of IQSEL. A clock signal, ONEPORTCLK, is generated by the AD9777 in this mode for the purpose of data synchronization. ONEPORTCLK runs at the input interleaved data rate, which is 2× the data rate DATA AT PORTS 1 AND 2 at the internal input to either channel. t = 0.0ns (MAX) S Test configurations showing the various clocks that are required t = 2.5ns (MAX) H t t S H and generated by the AD9777 with the PLL enabled/disabled and in the one-port/two-port modes are given in Figure 101 to Figure 52. Timing Requirements in Two-Port Input Mode with PLL Enabled Figure 104. Jumper positions needed to operate the AD9777 DATACLK DRIVER STRENGTH evaluation board in these modes are given as well. (Control Register 02h, Bit 5) PLL ENABLED, TWO-PORT MODE The DATACLK output driver strength is capable of driving (Control Register 02h, Bits 6 to 0 and 04h, Bits 7 to 1) >10 mA into a 330 Ω load while providing a rise time of 3 ns. With the phase-locked loop (PLL) enabled and the AD9777 in Figure 53 shows DATACLK driving a 330 Ω resistive load at a two-port mode, the speed of CLKIN is inherently that of the frequency of 50 MHz. By enabling the drive strength option input data rate. In two-port mode, Pin 8 (DATACLK/PLL_ (Control Register 02h, Bit 5), the amplitude of DATACLK under LOCK) can be programmed (Control Register 01h, Bit 0) to these conditions increases by approximately 200 mV. function as either a lock indicator for the internal PLL or as a 3.0 clock running at the input data rate. When Pin 8 is used as a clock output (DATACLK), its frequency is equal to that of 2.5 CLKIN. Data at the input ports is latched into the AD9777 on 2.0 the rising edge of the CLKIN. Figure 52 shows the delay, t , OD inherent between the rising edge of CLKIN and the rising edge 1.5 of DATACLK, as well as the setup and hold requirements for the data at Ports 1 and 2. The setup and hold times given in Figure 1.0 52 are the input data transitions with respect to CLKIN. Note 0.5 that in two-port mode (PLL enabled or disabled), the data rate at the interpolation filter inputs is the same as the input data 0 rate at Port 1 and Port 2. DELTA APPROX. 2.8ns –0.5 The DAC output sample rate in two-port mode is equal to the 0 102030 40 50 clock input rate multiplied by the interpolation rate. If zero TIME (ns) stuffing is used, another factor of 2 must be included to Figure 53. DATACLK Driver Capability into 330 Ω at 50 MHz calculate the DAC sample rate. PLL ENABLED, ONE-PORT MODE DATACLK INVERSION (Control Register 02h, Bits 6 to 1 and 04h, Bits 7 to 1) (Control Register 02h, Bit 4) In one-port mode, the I and Q channels receive their data from By programming this bit, the DATACLK signal shown in Figure 53 an interleaved stream at digital input Port 1. The function of can be inverted. With inversion enabled, tOD refers to the time Pin 32 is defined as an output (ONEPORTCLK) that generates a between the rising edge of CLKIN and the falling edge of clock at the interleaved data rate, which is 2× the internal input DATACLK. No other effect on timing occurs. data rate of the I and Q channels. The frequency of CLKIN is equal to the internal input data rate of the I and Q channels. Rev. C | Page 30 of 60 AMPLITUDE (V) 02706-053 02706-052 AD9777 IQ PAIRING The selection of the data for the I or Q channel is determined by the state of the logic level at Pin 31 (IQSEL when the AD9777 is (Control Register 02h, Bit 0) in one-port mode) on the rising edge of ONEPORTCLK. In one-port mode, the interleaved data is latched into the Under these conditions, IQSEL = 0 latches the data into the I AD9777 internal I and Q channels in pairs. The order of how channel on the clock rising edge, while IQSEL = 1 latches the the pairs are latched internally is defined by this control register. data into the Q channel. It is possible to invert the I and Q The following is an example of the effect this has on incoming selection by setting Control Register 02h, Bit 1 to the invert interleaved data. state (Logic 1). Figure 54 illustrates the timing requirements for Given the following interleaved data stream, where the data the data inputs as well as the IQSEL input. Note that the 1× indicates the value with respect to full scale: interpolation rate is not available in one-port mode. I Q I Q I Q I Q I Q The DAC output sample rate in one-port mode is equal to 0.5 0.5 1 1 0.5 0.5 0 0 0.5 0.5 CLKIN multiplied by the interpolation rate. If zero stuffing is With the control register set to 0 (I first), the data appears at the used, another factor of 2 must be included to calculate the DAC internal channel inputs in the following order in time: sample rate. I Channel 0.5 1 0.5 0 0.5 ONEPORTCLK INVERSION Q Channel 0.5 1 0.5 0 0.5 (Control Register 02h, Bit 2) With the control register set to 1 (Q first), the data appears at the internal channel inputs in the following order in time: By programming this bit, the ONEPORTCLK signal shown in Figure 54 can be inverted. With inversion enabled, tOD refers to I Channel 0.5 1 0.5 0 0.5 x the delay between the rising edge of the external clock and the Q Channel y 0.5 1 0.5 0 0.5 falling edge of ONEPORTCLK. The setup and hold times, t S The values x and y represent the next I value and the previous Q and t , are with respect to the falling edge of ONEPORTCLK. H value in the series. There is no other effect on timing. PLL DISABLED, TWO-PORT MODE ONEPORTCLK DRIVER STRENGTH With the PLL disabled, a clock at the DAC output rate must be The drive capability of ONEPORTCLK is identical to that of applied to CLKIN. Internal clock dividers in the AD9777 syn- DATACLK in the two-port mode. Refer to Figure 53 for thesize the DATACLK signal at Pin 8, which runs at the input performance under load conditions. data rate and can be used to synchronize the input data. Data is t latched into input Port 1 and Port 2 of the AD9777 on the rising OD edge of DATACLK. DATACLK speed is defined as the speed of t = 4.0ns (MIN) OD CLKIN divided by the interpolation rate. With zero stuffing en- TO 5.5ns (MAX) CLKIN t = 3.0ns (MAX) S abled, this division increases by a factor of 2. Figure 55 illustrates t = –0.5ns (MAX) H t = 3.5ns (MAX) IQS the delay between the rising edge of CLKIN and the rising edge t = –1.5ns (MAX IQH of DATACLK, as well as t and t in this mode. S H ONEPORTCLK The programmable modes DATACLK inversion and DATACLK driver strength described in the PLL Enabled, Two-Port Mode section have identical functionality with the PLL disabled. The data rate CLK created by dividing down the DAC clock in I AND Q INTERLEAVED INPUT DATA AT PORT 1 this mode can be programmed (via Register x03h, Bit 7) to be output from the SPI_SDO pin, rather than the DATACLK pin. In some applications, this may improve complex image rejec- t t S H increases by 1.6 ns when SPI_SDO is used as data rate tion. tOD clock out. IQSEL t t IQS IQH Figure 54. Timing Requirements in One-Port Input Mode, with the PLL Enabled Rev. C | Page 31 of 60 02706-054 AD9777 t OD t OD CLKIN CLKIN DATACLK ONEPORTCLK DATA AT PORTS 1 AND 2 I AND Q INTERLEAVED INPUT DATA AT PORT 1 t = 6.5ns (MIN) TO 8.0ns (MAX) OD t t S H t = 5.0ns (MAX) S t = –3.2ns (MAX) H Figure 55. Timing Requirements in Two-Port Input Mode, with PLL Disabled t t S H PLL DISABLED, ONE-PORT MODE IQSEL t = 4.0ns (MIN) OD In one-port mode, data is received into the AD9777 as an TO 5.5ns (MAX) t = 4.7ns (MAX) OD interleaved stream on Port 1. A clock signal (ONEPORTCLK), t = 3.0ns (MAX) S t t IQS IQH t = –1.0ns (MAX) H running at the interleaved data rate, which is 2× the input data t = 3.5ns (MAX) IQS t = –1.5ns (MAX) IQH rate of the internal I and Q channels, is available for data (TYP SPECS) synchronization at Pin 32. Figure 56. Timing Requirements in One-Port Input Mode, with PLL Disabled With PLL disabled, a clock at the DAC output rate must be applied DIGITAL FILTER MODES to CLKIN. Internal dividers synthesize the ONEPORTCLK signal The I and Q data paths of the AD9777 have their own at Pin 32. The selection of the data for the I or Q channel is deter- independent half-band FIR filters. Each data path consists of mined by the state of the logic level applied to Pin 31 (IQSEL when three FIR filters, providing up to 8× interpolation for each the AD9777 is in one-port mode) on the rising edge of channel. The rate of interpolation is determined by the state of ONEPORTCLK. Under these conditions, IQSEL = 0 latches the Control Register 01h, Bit 7 and Bit 6. Figure 2 to Figure 4 show data into the I channel on the clock rising edge, while IQSEL = 1 the response of the digital filters when the AD9777 is set to 2×, latches the data into the Q channel. It is possible to invert the I and 4×, and 8× modes. The frequency axes of these graphs have Q selection by setting Control Register 02h, Bit 1 to the invert state been normalized to the input data rate of the DAC. As the (Logic 1). Figure 56 illustrates the timing requirements for the data graphs show, the digital filters can provide greater than 75 dB of inputs as well as the IQSEL input. Note that the 1× interpolation out-of-band rejection. rate is not available in the one-port mode. An online tool is available for quick and easy analysis of the One-port mode is very useful when interfacing with devices, AD9777 interpolation filters in the various modes. The link can be such as the Analog Devices AD6622 or AD6623 transmit signal accessed at http://www.analog.com/Analog_Root/static/ processors, in which two digital data channels have been inter- techsupport/designtools/interactiveTools/dac/ad9777image.html. leaved (multiplexed). The programmable modes’ ONEPORTCLK inversion, ONEPORTCLK driver strength, and IQ pairing AMPLITUDE MODULATION described in the PLL Enabled, One-Port Mode section have Given two sine waves at the same frequency but with a 90° identical functionality with the PLL disable. phase difference, a point of view in time can be taken such that the waveform that leads in phase is cosinusoidal and the waveform that lags is sinusoidal. Analysis of complex variables states that the cosine waveform can be defined as having real positive and negative frequency components, while the sine waveform consists of imaginary positive and negative frequency images. This is shown graphically in the frequency domain in Figure 57. Rev. C | Page 32 of 60 02706-055 02706-056 AD9777 –jωt e /2j The phase relationship of the modulated signals is dependent on whether the modulating carrier is sinusoidal or cosinusoidal, SINE again with respect to the reference point of the viewer. DC –jωt e /2j Examples of sine and cosine modulation are given in Figure 58. –jωt Ae /2j –jωt –jωt e /2 e /2 SINUSOIDAL MODULATION COSINE DC DC –jωt Figure 57. Real and Imaginary Components of Ae /2j Sinusoidal and Cosinusoidal Waveforms –jωt –jωt Ae /2 Ae /2 COSINUSOIDAL Amplitude modulating a baseband signal with a sine or a cosine MODULATION convolves the baseband signal with the modulating carrier in DC the frequency domain. Amplitude scaling of the modulated signal reduces the positive and negative frequency images by a Figure 58. Baseband Signal, Amplitude Modulated with Sine and Cosine Carriers factor of 2. This scaling is very important in the discussion of the various modulation modes. Rev. C | Page 33 of 60 02706-057 02706-058 AD9777 By comparing the digital domain spectrum to the DAC MODULATION, NO INTERPOLATION SIN(x)/x roll-off, an estimate can be made for the characteris- With Control Register 01h, Bit 7 and Bit 6 set to 00, the tics required for the DAC reconstruction filter. Note also, per interpolation function on the AD9777 is disabled. Figure 59 to the previous discussion on amplitude modulation, that the Figure 62 show the DAC output spectral characteristics of the spectral components (where modulation is set to fS/4 or fS/8) are AD9777 in the various modulation modes, all with the scaled by a factor of 2. In the situation where the modulation is interpolation filters disabled. The modulation frequency is fS/2, the modulated spectral components add constructively, determined by the state of Control Register 01h, Bits 5 and 4. and there is no scaling effect. The tall rectangles represent the digital domain spectrum of a baseband signal of narrow bandwidth. The Effects of Digital Modulation on DAC Output Spectrum, Interpolation Disabled 0 0 –20 –20 –40 –40 –60 –60 –80 –80 –100 –100 0 0.2 0.4 0.6 0.8 1.0 0 0.2 0.4 0.6 0.8 1.0 f (×f ) f (×f ) OUT DATA OUT DATA Figure 59. No Interpolation, Modulation Disabled Figure 61. No Interpolation, Modulation = f /4 DAC 0 0 –20 –20 –40 –40 –60 –60 –80 –80 –100 –100 0 0.2 0.4 0.6 0.8 1.0 0 0.2 0.4 0.6 0.8 1.0 f (×f ) f (×f ) OUT DATA OUT DATA Figure 60. No Interpolation, Modulation = f /2 Figure 62. No Interpolation, Modulation = f /8 DAC DAC Rev. C | Page 34 of 60 AMPLITUDE (dBFS) AMPLITUDE (dBFS) 02706-060 02706-059 AMPLITUDE (dBFS) AMPLITUDE (dBFS) 02706-062 02706-061 AD9777 MODULATION, INTERPOLATION = 2× For this reason, as Figure 63 to Figure 66 show, the pass band of the interpolation filters can be frequency shifted, giving the With Control Register 01h, Bit 7 and Bit 6 set to 01, the equivalent of a high-pass digital filter. interpolation rate of the AD9777 is 2×. Modulation is achieved by multiplying successive samples at the interpolation filter Note that when using the fS/4 modulation mode, there is no output by the sequence (+1, −1). Figure 63 to Figure 66 true stop band as the band edges coincide with each other. In represent the spectral response of the AD9777 DAC output with the fS/8 modulation mode, amplitude scaling occurs over only a 2× interpolation in the various modulation modes to a narrow portion of the digital filter pass band due to constructive band baseband signal (again, the tall rectangles in the graphic). addition over just that section of the band The advantage of interpolation becomes clear in Figure 63 to Figure 66, where it can be seen that the images that would normally appear in the spectrum around the significant point is that the interpolation filtering is done prior to the digital modulator. The Effects of Digital Modulation on DAC Output Spectrum, Interpolation = 2x 0 0 –20 –20 –40 –40 –60 –60 –80 –80 –100 –100 0 0.5 1.0 1.5 2.0 0 0.5 1.0 1.5 2.0 f (×f ) f (×f ) OUT DATA OUT DATA Figure 63. 2× Interpolation, Modulation = Disabled Figure 65. 2× Interpolation, Modulation = f /4 DAC 0 0 –20 –20 –40 –40 –60 –60 –80 –80 –100 –100 0 0.5 1.0 1.5 2.0 0 0.5 1.0 1.5 2.0 f (×f ) f (×f ) OUT DATA OUT DATA Figure 64. 2× Interpolation, Modulation = f /2 Figure 66. 2× Interpolation, Modulation = f /8 DAC DAC Rev. C | Page 35 of 60 AMPLITUDE (dBFS) AMPLITUDE (dBFS) 02706-064 02706-063 AMPLITUDE (dBFS) AMPLITUDE (dBFS) 02706-066 02706-065 AD9777 MODULATION, INTERMODULATION = 4× Figure 67 to Figure 70 represent the spectral response of the AD9777 DAC output with 4× interpolation in the various With Control Register 01h, Bit 7 and Bit 6 set to 10, the modulation modes to a narrow band baseband signal. interpolation rate of the AD9777 is 4×. Modulation is achieved by multiplying successive samples at the interpolation filter output by the sequence (0, +1, 0, −1). The Effects of Digital Modulation on DAC Output Spectrum, Interpolation = 4x 0 0 –20 –20 –40 –40 –60 –60 –80 –80 –100 –100 02 1 34 02 1 34 f (×f ) f (×f ) OUT DATA OUT DATA Figure 67. 4x Interpolation, Modulation Disabled Figure 69. 4x Interpolation, Modulation = f /4 DAC 0 0 –20 –20 –40 –40 –60 –60 –80 –80 –100 –100 02 1 34 02 1 34 f (×f ) f (×f ) OUT DATA OUT DATA Figure 68. 4x Interpolation, Modulation = f /2 Figure 70. 4x Interpolation, Modulation = f /8 DAC DAC Rev. C | Page 36 of 60 AMPLITUDE (dBFS) AMPLITUDE (dBFS) 02706-068 02706-067 AMPLITUDE (dBFS) AMPLITUDE (dBFS) 02706-070 02706-069 AD9777 MODULATION, INTERMODULATION = 8× Looking at Figure 59 to Figure 75, the user can see how higher interpolation rates reduce the complexity of the reconstruction With Control Register 01h, Bits 7 and 6, set to 11, the filter needed at the DAC output. It also becomes apparent that interpolation rate of the AD9777 is 8×. Modulation is achieved the ability to modulate by fS/2, fS/4, or fS/8 adds a degree of by multiplying successive samples at the interpolation filter flexibility in frequency planning output by the sequence (0, +0.707, +1, +0.707, 0, –0.707, −1, +0.707). Figure 71 to Figure 74 represent the spectral response of the AD9777 DAC output with 8× interpolation in the various modulation modes to a narrow band baseband signal. The Effects of the Digital Modulation on the DAC Output Spectrum, Interpolation = 8× 0 0 –20 –20 –40 –40 –60 –60 –80 –80 –100 –100 05 12 3 4678 02 1 34 f (×f ) f (×f ) OUT DATA OUT DATA Figure 71. 8× Interpolation, Modulation Disabled Figure 73. 8x Interpolation, Modulation = fDAC/4 0 0 –20 –20 –40 –40 –60 –60 –80 –80 –100 –100 05 12 3 4678 02 1 34 f (×f ) f (×f ) OUT DATA OUT DATA Figure 74. 8x Interpolation, Modulation = f /8 DAC Figure 72. 8x Interpolation, Modulation = fDAC/2 Rev. C | Page 37 of 60 AMPLITUDE (dBFS) AMPLITUDE (dBFS) 02706-072 02706-071 AMPLITUDE (dBFS) AMPLITUDE (dBFS) 02706-074 02706-073 AD9777 The net effect is to increase the DAC output sample rate by a ZERO STUFFING factor of 2× with the 0 in the SIN(x)/x DAC transfer function (Control Register 01h, Bit 3) occurring at twice the original frequency. A 6 dB loss in amplitude at low frequencies is also evident, as can be seen in As shown in Figure 75, a 0 or null in the output frequency Figure 76. response of the DAC (after interpolation, modulation, and DAC reconstruction) occurs at the final DAC sample rate (f ). This DAC It is important to realize that the zero stuffing option by itself is due to the inherent SIN(x)/x roll-off response in the digital- does not change the location of the images but rather their to-analog conversion. In applications where the desired fre- amplitude, pass-band flatness, and relative weighting. For quency content is below fDAC/2, this may not be a problem. Note instance, in the previous example, the pass-band amplitude that at fDAC/2 the loss due to SIN(x)/x is 4 dB. In direct RF appli- flatness of the image at 3× f /4 is now improved to 0.59 dB DATA cations, this roll-off may be problematic due to the increased while the signal level has increased slightly from −10.5 dBFS to pass-band amplitude variation as well as the reduced amplitude –8.1 dBFS. of the desired signal. INTERPOLATING (COMPLEX MIX MODE) Consider an application where the digital data into the AD9777 (Control Register 01h, Bit 2) represents a baseband signal around f /4 with a pass band of DAC f /10. The reconstructed signal out of the AD9777 would DAC In the complex mix mode, the two digital modulators on the experience only a 0.75 dB amplitude variation over its pass AD9777 are coupled to provide a complex modulation function. band. However, the image of the same signal occurring at 3× In conjunction with an external quadrature modulator, this fDAC/4 suffers from a pass-band flatness variation of 3.93 dB. complex modulation can be used to realize a transmit image This image may be the desired signal in an IF application using rejection architecture. The complex modulation function can be one of the various modulation modes in the AD9777. This roll- +jωt −jωt programmed for e or e to give upper or lower image off of image frequencies can be seen in Figure 59 to Figure 74, rejection. As in the real modulation mode, the modulation where the effect of the interpolation and modulation rate is frequency ω can be programmed via the SPI port for f /2, DAC apparent as well. f /4, and f /8, where f represents the DAC output rate. DAC DAC DAC 10 OPERATIONS ON COMPLEX SIGNALS ZERO STUFFING Truly complex signals cannot be realized outside of a computer 0 ENABLED simulation. However, two data channels, both consisting of real –10 data, can be defined as the real and imaginary components of a complex signal. I (real) and Q (imaginary) data paths are often –20 defined this way. By using the architecture defined in Figure 76, a system that operates on complex signals can be realized, ZERO STUFFING –30 giving a complex (real and imaginary) output. DISABLED +jωt If a complex modulation function (e ) is desired, the real and –40 imaginary components of the system correspond to the real and +jωt imaginary components of e or cosωt and sinωt. As Figure 77 –50 0 0.5 1.0 1.5 2.0 shows, the complex modulation function can be realized by f , NORMALIZED TO f WITH ZERO STUFFING DISABLED (Hz) OUT DATA applying these components to the structure of the complex system defined in Figure 76. Figure 75. Effect of Zero Stuffing on DAC’s SIN(x)/x Response To improve upon the pass-band flatness of the desired image, a(t) c(t) × b(t) + d × b(t) INPUT OUTPUT the zero stuffing mode can be enabled by setting the control COMPLEX FILTER = (c + jd) register bit to a Logic 1. This option increases the ratio of IMAGINARY f /f by a factor of 2 by doubling the DAC sample rate and DAC DATA b(t) INPUT OUTPUT b(t) × a(t) + c × b(t) inserting a midscale sample (that is, 1000 0000 0000 0000) after every data sample originating from the interpolation filter. This Figure 76. Realization of a Complex System is important as it affects the PLL divider ratio needed to keep the VCO within its optimum speed range. Note that the zero stuffing takes place in the digital signal chain at the output of the digital modulator, before the DAC. Rev. C | Page 38 of 60 SIN (X)/X ROLL-OFF (dBFS) 02706-075 02706-076 AD9777 INPUT INPUT (REAL) (REAL) OUTPUT OUTPUT (REAL) INPUT INPUT (IMAGINARY) (IMAGINARY) SINωt 90° 90° COSωt Figure 78. Quadrature Modulation OUTPUT (IMAGINARY) The entire upconversion from baseband to transmit frequency is represented graphically in Figure 79. The resulting spectrum –jωt e = COSωt + jSINωt shown in Figure 79 represents the complex data consisting of Figure 77. Implementation of a Complex Modulator the baseband real and imaginary channels, now modulated onto orthogonal (cosine and negative sine) carriers at the transmit COMPLEX MODULATION AND IMAGE REJECTION frequency. It is important to remember that in this application OF BASEBAND SIGNALS (two baseband data channels), the image rejection is not In traditional transmit applications, a two-step upconversion is dependent on the data at either of the AD9777 input channels. done in which a baseband signal is modulated by one carrier to In fact, image rejection still occurs with either one or both of an IF (intermediate frequency) and then modulated a second the AD9777 input channels active. Note that by changing the time to the transmit frequency. Although this approach has sign of the sinusoidal multiplying term in the complex several benefits, a major drawback is that two images are created modulator, the upper sideband image could have been near the transmit frequency. Only one image is needed, the other suppressed while passing the lower one. This is easily done in being an exact duplicate. Unless the unwanted image is filtered, +jωt typically with analog components, transmit power is wasted and the AD9777 by selecting the e bit (Register 01h, Bit 1). In the usable bandwidth available in the system is reduced. purely complex terms, Figure 79 represents the two-stage upconversion from complex baseband to carrier. A more efficient method of suppressing the unwanted image can be achieved by using a complex modulator followed by a quadrature modulator. Figure 78 is a block diagram of a quadrature modulator. Note that it is in fact the real output half of a complex modulator. The complete upconversion can actually be referred to as two complex upconversion stages, the real output of which becomes the transmitted signal. Rev. C | Page 39 of 60 02706-077 02706-078 AD9777 REAL CHANNEL (OUT) A/2 A/2 1 –F F C C REAL CHANNEL (IN) A –B/2J B/2J DC –F F C C COMPLEX TO QUADRATURE IMAGINARY CHANNEL (OUT) MODULATOR MODULATOR –A/2J A/2J IMAGINARY CHANNEL (IN) –F –F C C B DC B/2 B/2 –F F C C A/4 + B/4J A/4 – B/4J A/4 + B/4J A/4 – B/4J 2 –F F Q Q –F – F –F + F F – F F + F Q C Q C Q C Q C OUT REAL –A/4 – B/4J A/4 – B/4J A/4 + B/4J –A/4 + B/4J QUADRATURE MODULATOR –F F Q Q IMAGINARY REJECTED IMAGES A/2 + B/2J A/2 – B/2J –F F Q Q 1 F = COMPLEX MODULATION FREQUENCY C 2 F = QUADRATURE MODULATION FREQUENCY Q Figure 79. Two-Stage Upconversion and Resulting Image Rejection Rev. C | Page 40 of 60 02706-079 AD9777 COMPLEX BASEBAND A system in which multiple baseband signals are complex SIGNAL modulated and then applied to the AD9777 real and imaginary 1 inputs, followed by a quadrature modulator, is shown in Figure 82, j(ω1 + ω2)t OUTPUT = REAL × e which also describes the transfer function of this system and the spectral output. Note the similarity of the transfer functions 1/2 1/2 given in Figure 82 and Figure 80. Figure 82 adds an additional = REAL –ω1– ω2DC ω1 + ω2 complex modulator stage for summing multiple carriers at the FREQUENCY AD9777 inputs. In addition, as in Figure 79, the image rejection Figure 80. Two-Stage Complex Upconversion is not dependent on the real or imaginary baseband data on any channel. Image rejection on a channel occurs if either the real IMAGE REJECTION AND SIDEBAND or imaginary data, or both, is present on the baseband channel. SUPPRESSIONS OF MODULATED CARRIERS It is important to remember that the magnitude of a complex As shown in Figure 79, image rejection can be achieved by signal can be 1.414× the magnitude of its real or imaginary applying baseband data to the AD9777 and following the components. Due to this 3 dB increase in signal amplitude, the AD9777 with a quadrature modulator. To process multiple real and imaginary inputs to the AD9777 must be kept at least carriers while still maintaining image reject capability, each 3 dB below full scale when operating with the complex carrier must be complex modulated. As Figure 80 shows, single modulator. Overranging in the complex modulator results in or multiple complex modulators can be used to synthesize severe distortion at the DAC output. complex carriers. These complex carriers are then summed and applied to the real and imaginary inputs of the AD9777. BASEBAND CHANNEL 1 R(1) REAL INPUT COMPLEX MULTICARRIER MODULATOR 1 REAL OUTPUT = R(1) IMAGINARY INPUT R(1) + R(2) + . . .R(N) (TO REAL INPUT OF AD9777) BASEBAND CHANNEL 2 R(2) REAL INPUT COMPLEX MODULATOR 2 MULTICARRIER IMAGINARY INPUT R(2) IMAGINARY OUTPUT = I(1) + I(2) + . . .I(N) (TO IMAGINARY INPUT OF AD9777) R(N) = REAL OUTPUT OF N BASEBAND CHANNEL N R(N) I(N) = IMAGINARY OUTPUT OF N REAL INPUT COMPLEX MODULATOR N IMAGINARY INPUT R(N) Figure 81. Synthesis of Multicarrier Complex Signal MULTIPLE BASEBAND CHANNELS REAL REAL REAL REAL MULTIPLE AD9777 QUADRATURE COMPLEX COMPLEX MODULATOR MODULATORS MODULATOR FREQUENCY = ω IMAGINARY IMAGINARY IMAGINARY Q FREQUENCY = ω , ω ...ω 1 2 N FREQUENCY = ω C COMPLEX BASEBAND SIGNAL OUTPUT = REAL × j(ω + ω + ω )t e N C Q –ω – ω – ω DC ω + ω + ω 1 C Q 1 C Q REJECTED IMAGES Figure 82. Image Rejection with Multicarrier Signals Rev. C | Page 41 of 60 02706-080 02706-081 02706-082 AD9777 The complex carrier synthesized in the AD9777 digital Region C modulator is accomplished by creating two real digital carriers Region C is most accurately described as a down conversion, as in quadrature. Carriers in quadrature cannot be created with jωt the modulating carrier is −e . If viewed as a complex signal, the modulator running at fDAC/2. As a result, complex modula- only the images in Region C remains. This image appears on tion only functions with modulation rates of fDAC/4 and fDAC/8. the real and imaginary outputs of the AD9777, as well as on the Region A and Region B of Figure 83 to Figure 88 are the result output of the quadrature modulator, where the center of the of the complex signal described previously, when complex spectral plot now represents the quadrature modulator LO and jωt modulated in the AD9777 by +e . Region C and Region D are the horizontal scale represents the frequency offset from this the result of the complex signal described previously, again with LO. positive frequency components only, modulated in the AD9777 Region D jωt by −e . The analog quadrature modulator after the AD9777 jωt inherently modulates by +e . Region D is the image (complex conjugate) of Region C. If a spectrum analyzer is used to view the real or imaginary DAC Region A outputs of the AD9777, Region D appears in the spectrum. Region A is a direct result of the upconversion of the complex However, on the output of the quadrature modulator, Region D signal near baseband. If viewed as a complex signal, only the is rejected. images in Region A remains. The complex Signal A, consisting Figure 89 to Figure 96 show the measured response of the of positive frequency components only in the digital domain, AD9777 and AD8345 given the complex input signal to the has images in the positive odd Nyquist zones (1, 3, 5, and so AD9777 in Figure 89. The data in these graphs was taken with a on), as well as images in the negative even Nyquist zones. The data rate of 12.5 MSPS at the AD9777 inputs. The interpolation appearance and rejection of images in every other Nyquist zone rate of 4× or 8× gives a DAC output data rate of 50 MSPS or becomes more apparent at the output of the quadrature 100 MSPS. As a result, the high end of the DAC output modulator. The A images appear on the real and the imaginary spectrum in these graphs is the first null point for the SIN(x)/x outputs of the AD9777, as well as on the output of the roll-off, and the asymmetry of the DAC output images is quadrature modulator, where the center of the spectral plot now representative of the SIN(x)/x roll-off over the spectrum. The represents the quadrature modulator LO and the horizontal scale internal PLL was enabled for these results. In addition, a now represents the frequency offset from this LO. 35 MHz third-order low-pass filter was used at the AD9777/ Region B AD8345 interface to suppress DAC images. Region B is the image (complex conjugate) of Region A. If a An important point can be made by looking at Figure 91 and spectrum analyzer is used to view the real or imaginary DAC Figure 93. Figure 91 represents a group of positive frequencies outputs of the AD9777, Region B appears in the spectrum. modulated by complex +fDAC/4, while Figure 93 represents a However, on the output of the quadrature modulator, Region B group of negative frequencies modulated by complex −f /4. DAC is rejected. When looking at the real or imaginary outputs of the AD9777, as shown in Figure 91 and Figure 93, the results look identical. However, the spectrum analyzer cannot show the phase relationship of these signals. The difference in phase between the two signals becomes apparent when they are applied to the AD8345 quadrature modulator, with the results shown in Figure 92 and Figure 94. Rev. C | Page 42 of 60 AD9777 0 0 –20 –20 D A BC D A BC –40 –40 DA B CD A B C –60 –60 –80 –80 –100 –100 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 (LO) (LO) f (×f ) f (×f ) OUT DATA OUT DATA Figure 83. 2× Interpolation, Complex f /4 Modulation Figure 86. 2× Interpolation, Complex f /8 Modulation DAC DAC 0 0 –20 –20 D A B C DA BC –40 –40 DA B C D A B C –60 –60 –80 –80 –100 –100 –4.0 –3.0 –2.0 –1.0 0 1.0 2.0 3.0 4.0 –4.0 –3.0 –2.0 –1.0 0 1.0 2.0 3.0 4.0 (LO) (LO) f (×f ) f (×f ) OUT DATA OUT DATA Figure 84. 4× Interpolation, Complex f /4 Modulation DAC Figure 87. 4× Interpolation, Complex fDAC/8 Modulation 0 0 –20 –20 DA B C DA B C DA BC D A BC –40 –40 –60 –60 –80 –80 –100 –100 –8.0 –6.0 –4.0 –2.0 0 2.0 4.0 6.0 8.0 –8.0 –6.0 –4.0 –2.0 0 2.0 4.0 6.0 8.0 (LO) (LO) f (×f ) f (×f ) OUT DATA OUT DATA Figure 85. 8× Interpolation, Complex f /4 Modulation DAC Figure 88. 8× Interpolation, Complex fDAC/8 Modulation Rev. C | Page 43 of 60 02706-085 02706-084 02706-083 02706-088 02706-087 02706-086 AD9777 0 0 –10 –10 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 –100 010 20 30 40 50 750 760 770 780 790 800 810 820 830 840 850 FREQUENCY (MHz) FREQUENCY (MHz) Figure 89. AD9777, Real DAC Output of Complex Input Signal Near Baseband Figure 92. AD9777 Complex Output from Figure 91, Now Quadrature (Positive Frequencies Only), Interpolation = 4×, No Modulation in AD9777 Modulated by AD8345 (LO = 800 MHz) 0 0 –10 –10 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 0 102030 40 50 –100 750 760 770 780 790 800 810 820 830 840 850 FREQUENCY (MHz) FREQUENCY (MHz) Figure 93. AD9777, Real DAC Output of Complex Input Signal Near Figure 90. AD9777 Complex Output from Figure 89, Now Quadrature Baseband (Negative Frequencies Only), Interpolation = 4×, Modulated by AD8345 (LO = 800 MHz) Complex Modulation in AD9777 = −f /4 DAC 0 0 –10 –10 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 –100 750 760 770 780 790 800 810 820 830 840 850 0 102030 40 50 FREQUENCY (MHz) FREQUENCY (MHz) Figure 91. AD9777, Real DAC Output of Complex Input Signal Near Figure 94. AD9777 Complex Output from Figure 93, Now Quadrature Baseband (Positive Frequencies Only), Interpolation = 4×, Modulated by AD8345 (LO = 800 MHz) Complex Modulation in AD9777 = +fDAC/4 Rev. C | Page 44 of 60 AMPLITUDE (dBm) AMPLITUDE (dBm) AMPLITUDE (dBm) 02706-091 02706-090 02706-089 AMPLITUDE (dBm) AMPLITUDE (dBm) AMPLITUDE (dBm) 02706-094 02706-093 02706-092 AD9777 0 0 –10 –20 –20 –30 –40 –40 –50 –60 –60 –70 –80 –80 –90 –100 –100 700 720 740 760 780 800 820 840 860 880 900 0 20 40 60 80 100 FREQUENCY (MHz) FREQUENCY (MHz) Figure 95. AD9777, Real DAC Output of Complex Input Signal Near Figure 96. AD9777 Complex Output from Figure 95, Now Quadrature Baseband (Positive Frequencies Only), Interpolation = 8×, Modulated by AD8345 (LO = 800 MHz) Complex Modulation in AD9777 = +f /8 DAC Rev. C | Page 45 of 60 AMPLITUDE (dBm) 02706-095 AMPLITUDE (dBm) 02706-096 AD9777 APPLYING THE OUTPUT CONFIGURATIONS The following sections illustrate typical output configurations For the typical situation, where IOUTFS = 20 mA and RA and RB for the AD9777. Unless otherwise noted, it is assumed that both equal 50 Ω, the equivalent circuit values become IOUTFS is set to a nominal 20 mA. For applications requiring VSOURCE = 2 VP-P optimum dynamic performance, a differential output configu- ROUT = 100 Ω ration is suggested. A simple differential output may be achieved by converting I and I to a voltage output by Note that the output impedance of the AD9777 DAC itself is OUTA OUTB terminating them to AGND via equal value resistors. This type greater than 100 kΩ and typically has no effect on the of configuration may be useful when driving a differential impedance of the equivalent output circuit. voltage input device such as a modulator. If a conversion to a DIFFERENTIAL COUPLING USING A single-ended signal is desired and the application allows for ac TRANSFORMER coupling, an RF transformer may be useful; if power gain is required, an op amp may be used. The transformer configura- An RF transformer can be used to perform a differential-to- tion provides optimum high frequency noise and distortion single-ended signal conversion, as shown in Figure 98. A performance. The differential op amp configuration is suitable differentially coupled transformer output provides the optimum for applications requiring dc coupling, signal gain, and/or level distortion performance for output signals whose spectral shifting within the bandwidth of the chosen op amp. content lies within the transformer’s pass band. An RF transformer, such as the Mini-Circuits T1-1T, provides excellent A single-ended output is suitable for applications requiring a rejection of common-mode distortion (that is, even-order unipolar voltage output. A positive unipolar output voltage harmonics) and noise over a wide frequency range. It also results if IOUTA and/or IOUTB is connected to a load resistor, RLOAD, provides electrical isolation and the ability to deliver twice the referred to AGND. This configuration is most suitable for a power to the load. Transformers with different impedance ratios single-supply system requiring a dc-coupled, ground referred may also be used for impedance matching purposes. output voltage. Alternatively, an amplifier could be configured MINI-CIRCUITS as an I-V converter, thus converting I or I into a OUTA OUTB T1-1T I OUTA negative unipolar voltage. This configuration provides the best DAC R LOAD DAC dc linearity as IOUTA or IOUTB are maintained at ground or I OUTB virtual ground. Figure 98. Transformer-Coupled Output Circuit UNBUFFERED DIFFERENTIAL OUTPUT, EQUIVALENT CIRCUIT The center tap on the primary side of the transformer must be In many applications, it may be necessary to understand the connected to AGND to provide the necessary dc current path equivalent DAC output circuit. This is especially useful when for both I and I . The complementary voltages appearing OUTA OUTB designing output filters or when driving inputs with finite input at I and I (that is, V and V ) swing symmetrically OUTA OUTB OUTA OUTB around AGND and should be maintained within the specified impedances. Figure 97 illustrates the output of the AD9777 and the equivalent circuit. A typical application where this output compliance range of the AD9777. A differential resistor, information may be useful is when designing an interface filter RDIFF, can be inserted in applications where the output of the between the AD9777 and the Analog Devices AD8345 transformer is connected to the load, RLOAD, via a passive quadrature modulator. reconstruction filter or cable. RDIFF is determined by the transformer’s impedance ratio and provides the proper source I V + termination that results in a low VSWR. Note that approxi- OUTA OUT mately half the signal power dissipates across R . DIFF I OUTB V – OUT R + R A B V = SOURCE V OUT I × (R + R ) OUTFS A B (DIFFERENTIAL) p-p Figure 97. DAC Output Equivalent Circuit Rev. C | Page 46 of 60 02706-097 02706-098 AD9777 Gain/Offset Adjust DIFFERENTIAL COUPLING USING AN OP AMP The matching of the DAC output to the common-mode input An op amp can also be used to perform a differential-to-single of the AD8345 allows the two components to be dc-coupled, ended conversion, as shown in Figure 99. This has the added with no level shifting necessary. The combined voltage offset of benefit of providing signal gain as well. In Figure 99, the the two parts can therefore be compensated via the AD9777 AD9777 is configured with two equal load resistors, R , of LOAD programmable offset adjust. This allows excellent LO 25 Ω. The differential voltage developed across I and I is OUTA OUTB cancellation at the AD8345 output. The programmable gain converted to a single-ended signal via the differential op amp adjust allows for optimal image rejection as well. configuration. An optional capacitor can be installed across IOUTA and IOUTB, forming a real pole in a low-pass filter. The The AD9777 evaluation board includes an AD8345 and addition of this capacitor also enhances the op amp’s distortion recommended interface (Figure 105 and Figure 106). On the performance by preventing the DAC’s fast slewing output from output of the AD9777, R9 and R10 convert the DAC output overloading the input of the op amp. current to a voltage. R16 can be used to do a slight common- 500Ω mode shift if necessary. The (now voltage) signal is applied to a 225Ω low-pass reconstruction filter to reject DAC images. The I OUTA components installed on the AD9777 provide a 35 MHz cutoff AD8021 DAC I but can be changed to fit the application. A balun (Mini- OUTB C OPT 225Ω Circuits ADTL1-12) is used to cross the ground plane boundary AVDD R OPT to the AD8345. Another balun (Mini-Circuits ETC1-1-13) is 25Ω 25Ω 500Ω 225Ω used to couple the LO input of the AD8345. The interface requires a low ac impedance return path from the AD8345, Figure 99. Op Amp-Coupled Output Circuit therefore a single connection between the AD9777 and AD8345 The common-mode (and second-order distortion) rejection of ground planes is recommended. this configuration is typically determined by the resistor The performance of the AD9777 and AD8345 in an image matching. The op amp used must operate from a dual supply reject transmitter, reconstructing three WCDMA carriers, can since its output is approximately ±1.0 V. A high speed amplifier, be seen in Figure 100. The LO of the AD8345 in this application such as the AD8021, capable of preserving the differential is 800 MHz. Image rejection (50 dB) and LO feedthrough performance of the AD9777 while meeting other system level (−78 dBFS) have been optimized with the programmable objectives (for example, cost, power) is recommended. The op features of the AD9777. The average output power of the digital amp’s differential gain, gain setting resistor values, and full-scale waveform for this test was set to −15 dBFS to account for the output swing capabilities should all be considered when peak-to-average ratio of the WCDMA signal. optimizing this circuit. R is necessary only if level shifting is OPT required on the op amp output. In Figure 99, AVDD, which is 0 the positive analog supply for both the AD9777 and the op amp, –10 is also used to level shift the differential output of the AD9777 –20 to midsupply (that is, AVDD/2). –30 INTERFACING WITH THE AD8345 QUADRATURE –40 MODULATOR –50 The AD9777 architecture was defined to operate in a transmit –60 signal chain using an image reject architecture. A quadrature –70 modulator is also required in this application and should be –80 designed to meet the output characteristics of the DAC as much –90 as possible. The AD8345 from Analog Devices meets many of the requirements for interfacing with the AD9777. As with any –100 762.5 782.5 802.5 822.5 842.5 DAC output interface, there are a number of issues that have to FREQUENCY (MHz) be resolved. The following sections list some of the major issues. Figure 100. AD9777/AD8345 Synthesizing a Three-Carrier WCDMA Signal at an LO of 800 MHz DAC Compliance Voltage/Input Common-Mode Range The dynamic range of the AD9777 is optimal when the DAC outputs swing between ±1.0 V. The input common-mode range of the AD8345, at 0.7 V, allows optimum dynamic range to be achieved in both components. Rev. C | Page 47 of 60 02706-099 AMPLITUDE (dBm) 02706-100 AD9777 EVALUATION BOARD DAC Differential Outputs The AD9777 evaluation board allows easy configuration of the various modes, programmable via the SPI port. Software is Transformers T2 and T3 should be in place. Note that the lower available for programming the SPI port from Windows® 95, band of operation for these transformers is 300 kHz to 500 kHz. Windows 98, or Windows NT®/2000. The evaluation board also Jumpers 4, 8, 13 to 17, and 28 to 30 should remain unsoldered. contains an AD8345 quadrature modulator and support The outputs are taken from S3 and S4. circuitry that allows the user to optimally configure the AD9777 Using the AD8345 in an image reject transmit signal chain. Remove Transformers T2 and T3. Jumpers JP4 and 28 to 30 Figure 101 to Figure 104 describe how to configure the should remain unsoldered. Jumpers 13 to 16 should be evaluation board in the one-port and two-port input modes with soldered. The desired components for the low-pass interface the PLL enabled and disabled. Refer to Figure 105 to Figure 114, filters L6, L7, C55, and C81 should be in place. The LO drive is the schematics, and the layout for the AD9777 evaluation board connected to the AD8345 via J10 and the balun T4, and the for the jumper locations described below. The AD9777 outputs AD8345 output is taken from J9. can be configured for various applications by referring to the following instructions. DAC Single-Ended Outputs Remove Transformers T2 and T3. Solder jumper link JP4 or JP28 to look at the DAC1 outputs. Solder jumper link JP29 or JP30 to look at the DAC2 outputs. Jumpers 8 and 13 to 17 should remain unsoldered. Jumpers JP35 to JP38 may be used to ground one of the DAC outputs while the other is measured single-ended. Optimum single-ended distortion performance is typically achieved in this manner. The outputs are taken from S3 and S4. Rev. C | Page 48 of 60 AD9777 LECROY SIGNAL GENERATOR PULSE TRIG GENERATOR INP DATACLK CLK+/CLK– INPUT CLOCK AWG2021 40-PIN RIBBON CABLE OR DAC1, DB15–DB0 DG2020 DAC2, DB15–DB0 AD9777 JUMPER CONFIGURATION FOR TWO PORT MODE PLL ON SOLDERED/IN UNSOLDERED/OUT JP1 – × JP2 – × JP3 – × JP5 – × JP6 – × JP12 – × JP24 – × JP25 – × JP26 – × JP27 – × JP31 – × JP32 – × JP33 – × NOTES 1. TO USE PECL CLOCK DRIVER (U8), SOLDER JP41 AND JP42 AND REMOVE TRANSFORMER T1. 2. IN TWO-PORT MODE, IF DATACLK/PLL_LOCK IS PROGRAMMED TO OUTPUT PIN 8, JP25 AND JP39 SHOULD BE SOLDERED. IF DATACLK/PLL_LOCK IS PROGRAMMED TO OUTPUT PIN 53, JP46 AND JP47 SHOULD BE SOLDERED. SEE THE TWO PORT DATA INPUT MODE SECTION FOR MORE INFORMATION. Figure 101. Test Configuration for AD9777 in Two-Port Mode with PLL Enabled Signal Generator Frequency = Input Data Rate, DAC Output Data Rate = Signal Generator Frequency × Interpolation Rate LECROY SIGNAL GENERATOR TRIG PULSE INP GENERATOR ONEPORTCLK CLK+/CLK– INPUT CLOCK AWG2021 OR DAC1, DB15–DB0 DG2020 DAC2, DB15–DB0 AD9777 JUMPER CONFIGURATION FOR ONE PORT MODE PLL ON SOLDERED/IN UNSOLDERED/OUT JP1 – × JP2 – × JP3 – × JP5 – × JP6 – × JP12 – × JP24 – × JP25 – × JP26 – × JP27 – × JP31 – × JP32 – × JP33 – × NOTES 1. TO USE PECL CLOCK DRIVER (U8), SOLDER JP41 AND JP42 AND REMOVE TRANSFORMER T1. Figure 102. Test Configuration for AD9777 in One-Port Mode with PLL Enabled, Signal Generator Frequency = One-Half Interleaved Input Data Rate, ONEPORTCLK = Interleaved Input Data Rate, DAC Output Data Rate = Signal Generator Frequency × Interpolation Rate Rev. C | Page 49 of 60 02706-102 02706-101 AD9777 LECROY SIGNAL GENERATOR PULSE TRIG GENERATOR INP DATACLK CLK+/CLK– INPUT CLOCK AWG2021 40-PIN RIBBON CABLE OR DAC1, DB15–DB0 DG2020 DAC2, DB15–DB0 AD9777 JUMPER CONFIGURATION FOR TWO PORT MODE PLL OFF SOLDERED/IN UNSOLDERED/OUT JP1 – × JP2 – × JP3 – × JP5 – × JP6 – × JP12 – × JP24 – × JP25 – × JP26 – × JP27 – × JP31 – × JP32 – × JP33 – × NOTES 1. TO USE PECL CLOCK DRIVER (U8), SOLDER JP41 AND JP42 AND REMOVE TRANSFORMER T1. 2. IN TWO-PORT MODE, IF DATACLK/PLL_LOCK IS PROGRAMMED TO OUTPUT PIN 8, JP25 AND JP39 SHOULD BE SOLDERED. IF DATACLK/PLL_LOCK IS PROGRAMMED TO OUTPUT PIN 53, JP46 AND JP47 SHOULD BE SOLDERED. SEE THE TWO PORT DATA INPUT MODE SECTION FOR MORE INFORMATION. Figure 103. Test Configuration for AD9777 in Two-Port Mode with PLL Disabled, DAC Output Data Rate = Signal Generator Frequency, DATACLK = Signal Generator Frequency/Interpolation Rate LECROY SIGNAL GENERATOR PULSE TRIG GENERATOR INP ONEPORTCLK CLK+/CLK– INPUT CLOCK AWG2021 OR DAC1, DB15–DB0 DG2020 AD9777 DAC2, DB15–DB0 JUMPER CONFIGURATION FOR ONE PORT MODE PLL OFF SOLDERED/IN UNSOLDERED/OUT JP1 – × JP2 – × JP3 – × JP5 – × JP6 – × JP12 – × JP24 – × JP25 – × JP26 – × JP27 – × JP31 – × JP32 – × JP33 – × NOTES 1. TO USE PECL CLOCK DRIVER (U8), SOLDER JP41 AND JP42 AND REMOVE TRANSFORMER T1. Figure 104. Test Configuration for AD9777 in One-Port Mode with PLL Disabled, DAC Output Data Rate = Signal Generator Frequency, ONEPORTCLK = Interleaved Input Data Rate = 2× Signal Generator Frequency/Interpolation Rate. Rev. C | Page 50 of 60 02706-104 02706-103 AD9777 Figure 105. AD8345 Circuitry on AD9777 Evaluation Board Rev. C | Page 51 of 60 L6 R32 C79 DNP 51Ω DNP O2N LC0805 RC0603 CC0603 POWER INPUT FILTERS C55 C81 CC0805 CC0805 JP19 DNP DNP L8 LC0805 RC0603 RC0603 FERRITE VDDMIN O2P W11 VDDM LC1210 L7 R33 R34 1 3 JP45 DNP 51Ω DNP P C28 + C32 DCASE CC0805 16V JP43 JP44 T5 0.1µF 22µF MODULATED OUTPUT S DGND2 C74 R23 W12 DGND2; 3, 4, 5 64 100pF 0Ω VDDM 2 J9 CC0603 RC0603 L3 TP2 2 C72 C35 C75 + JP9 FERRITE RED BCASE CC0603 16 15 14 13 12 11 10 9 DVDD_IN 10V 100pF CC0603 0.1µF 2 J8 DVDD LC1210 10µF C65 C66 + + VDDM C67 DCASE CC0805 DCASE 16V 16V 0.1µF AD8345 U2 2 22µF 22µF R26 DGND J5 1kΩ TP3 1 2 3 4 5 6 7 8 BLK JP18 L2 TP4 FERRITE JP10 RED 2 AVDD_IN LOCAL OSC INPUT C78 J4 AVDD C76 LC1210 0.1µF R28 100pF DGND2; 3, 4, 5 ETC1-1-13 0Ω 3 4 C64 C61 + + C68 J10 RC0603 CC0603 DCASE CC0805 DCASE 16V 16V R30 0.1µF SP 22µF 22µF 2 2 DNP CC0603 AGND 1 5 T4 J6 C77 2 TP5 JP7 100pF BLK 4 6 L1 TP6 S JP21 FERRITE JP11 RED CLKVDD_IN T6 J3 CLKVDD LC1210 2 P C63 C62 + + 31 C69 DCASE CC0805 DCASE 16V 16V 0.1µF 22µF 22µF R35 C80 L4 CGND DNP 51Ω DNP J7 O1N c TP7 LC0805 RC0603 CC0603 BLK C54 C73 CC0805 JP20 DNP L5 R36 DNP DNP 51Ω RC0603 O1P LC0805 RC0603 R37 DNP 02706-105 CC0805 ADTL1-12 CC0603 ADTL1-12 IBBP QBBP IBBN QBBN G1A G4B G1B G4A LOIN VPS2 LOIP VOUT VPS1 G3 ENBL G2 RC0603 RC0603 AD9777 Figure 106. AD9777 Clock, Power Supplies, and Output Circuitry Rev. C | Page 52 of 60 R2 R3 JP8 1kΩ 1kΩ DVDD R10 C70 51kΩ 0.1µF RC0603 RC0603 C36 C37 C38 C39 C40 C41 CLKVDD C1 C12 C11 C42 C27 CC0805 CC0805 CC0805 CC0805 CC0805 CC0805 RC0603 + CC0603 BCASE CC0603 CC0603 CC0603 CC0603 10µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF R9 R16 6.3V 0.1µF 0.1µF 0.1µF 1pF RC0603 RC0603 51kΩ 10kΩ TP15 C13 JP4 JP22 c WHT 0.1µF c 1 80 VDDC1 VDDA6 AVDD 6 1 JP28 2 LF VSSA10 79 5 2 C20 C19 C14 C2 + 3 VDDC2 VDDA5 78 J37 CLKP AGND; 3, 4, 5 CC0603 CC0603 CC0603 BCASE 10µF T2 4 3 R1 4 77 VSSC1 VSSA9 0.1µF 0.1µF 0.1µF 6.3V OUT1 JP23 CLKN 3 4 200Ω JP1 S3 5 CLKP VDDA4 76 T1 2 5 6 75 T1-1T CLKN VSSA8 JP2 RC1206 1 6 J35 C58 R42 JP33 7 74 VSSC2 VSSA7 ADCLK R38 10kΩ DNP 49.9kΩ 8 DCLK-PLLL IOUT1P 73 c T1-1T CLKIN 9 72 VSSD1 IOUT1N C58 O1N JP39 CC0603 S1 DNP 10 71 JP13 VDDD1 VSSA6 C57 DVDD O1P DNP c 11 P1D15 VSSA5 70 JP15 ACLKX CGND; 3, 4, 5 C10 C26 + AD15 O2N BCASE CC0603 10µF 12 IOUT2P 69 P1D14 JP16 AD14 O2P 6.3V 0.001µF JP24 13 P1D13 IOUT2N 68 JP14 C59 AD13 CC0603 DNP 14 P1D12 VSSA4 67 AVDD JP36 AD12 74VCX86 CX3 15 66 P1D11 VSSA3 AD11 12 JP25 JP38 JP29 CX2 11 16 P1D10 VDDA3 65 U3 AD10 13 C18 C17 C15 C3 + CX1 17 VSSD2 VSSA2 64 CC0805 CC0603 CC0603 BCASE 10µF JP30 DVDD; 14 18 VDDD2 63 U1 VDDA2 0.1µF 0.1µF 0.1µF 6.3V DGND; 7 DVDD JP12 19 P1D9 VSSA1 62 T3 AGND; 3, 4, 5 C25 C9 + TP14 AD09 R40 BCASE CC0603 10µF OUT 2 20 VDDA1 61 3 4 DVDD P1D8 TP11 TP10 TP9 TP8 WHT 5kΩ AD08 S4 6.3V 0.001µF WHT WHT WHT WHT FSADJ1 DGND; 3, 4, 5 21 P1D7 60 2 5 AD07 DATACLK RC0603 22 P1D6 FSADJ2 59 1 6 AD06 R43 R5 S2 23 P1D5 REFOUT 58 49.9kΩ 49.9Ω AD05 T1-1T JP3 24 P1D4 57 JP17 RESET AD04 R7 R8 R12 C70 25 VSSD3 SP-CSB 56 C16 C4 2kΩ 1kΩ + SPCSP 51kΩ 0.1µF C29 CC0603 BCASE 10µF 0.01% 0.01% 26 55 VDDD3 SP-CLK 0.1µF R6 RC0603 CC0603 DVDD SPCLK 0.1µF 6.3V 27 P1D3 SP-SDI 54 1kΩ C8 C24 R11 R17 + AD03 SPSDI BCASE CC0603 RC0603 RC0603 10µF 28 P1D2 SP-SDO 53 51kΩ 10kΩ AD02 SPSDO 6.3V 0.001µF 29 52 P1D1 VSSD6 AD01 30 VDDD6 51 P1D0 JP5 AD00 DVDD DVDD 31 P2D15-IQSEL P2D0 50 BD15 BD00 32 P2D14-OPCLK P2D1 49 C21 C5 + BD01 JP27 CC0603 BCASE 10µF 33 P2D13 P2D2 48 R39 OPCLK_3 BD13 BD02 0.001µF 6.3V JP32 34 47 1kΩ P2D12 P2D3 BD12 BD03 DGND; 3, 4, 5 35 VSSD4 P2D4 46 JP40 BD04 JP26 36 VDDD4 45 S6 P2D5 DVDD BD05 BD14 IQ 74VCX86 JP47 37 44 P2D11 VSSD5 9 C7 C23 IQ + BD11 JP46 8 74VCX86 JP31 BCASE CC0603 SPSDO 10µF 38 P2D10 VDDD5 43 12 IQ U4 10 BD10 DVDD 11 6.3V 0.001µF 39 P2D9 42 OPCLK U4 P2D6 13 BD09 BD06 DVDD; 14 41 JP34 40 P2D8 P2D7 C6 C22 + BD08 BD07 DVDD; 14 BCASE DGND; 7 CC0603 10µF OPCLK 6.3V DGND; 7 0.001µF AD9777+TSP S5 C45 0.01µF AGND; 3, 4, 5 02706-106 CC0805 CC0603 CC0605 RC0603 RC0603 CC0603 RC1206 CC0603 AD9777 Figure 107. AD9777 Evaluation Board Input (A Channel) and Clock Buffer Circuitry Rev. C | Page 53 of 60 R1 R2 R3 R4 R5 R6 R7 R8 R9 R1 R2 R3 R4 R5 R6 R7 R8 R9 RCOM RCOM RP5 RP7 50Ω DNP DATA-A 1 2 345 67 89 10 1 2 3 45 678 9 10 74VCX86 RP1 22Ω 2 1 AD15 1 DVDD 116 CX1 3 RP1 22Ω U3 2 4 3 AD14 215 DVDD; 14 RP1 22Ω C30 + 6 5 AD13 AGND; 7 C33 314 ACASE CC0805 4.7µF RP1 22Ω 0.1µF 8 7 AD12 74VCX86 6.3V 413 4 RP1 22Ω 6 10 9 AD11 512 U3 5 RP1 22Ω DVDD; 14 12 11 AD10 611 AGND; 7 RP1 22Ω 14 13 AD09 710 RP1 22Ω 74VCX86 16 15 AD08 9 89 8 RP2 22Ω U3 CX3 10 18 17 AD07 116 CX2 DVDD; 14 RP2 22Ω 20 19 AD06 AGND; 7 215 RP2 22Ω 22 21 AD05 314 RP2 22Ω 24 23 AD04 413 RP2 22Ω 26 25 AD03 512 RP2 22Ω 28 27 AD02 611 DVDD RP2 22Ω 30 29 AD01 710 74VCX86 RP2 22Ω 4 32 31 AD00 6 C31 89 + C34 5 U4 4.7µF ACASE CC0805 34 33 DVDD; 14 0.1µF 6.3V AGND; 7 36 35 RP6 1 2 345 67 89 10 1 2 3 45 678 9 10 38 37 RP8 50Ω DNP 40 39 RCOM RCOM R1 R2 R3 R4 R5 R6 R7 R8 R9 R1 R2 R3 R4 R5 R6 R7 R8 R9 RIBBON J1 R15 220Ω ADCLK DVDD RC1206 4 10 DVDD PRE PRE 3 J Q 5 OPCLK_2 11 J Q 9 C52 + C53 74VCX86 OPCLK 1 CLK 12 CLK 4.7µF ACASE CC0805 OPCLK_3 1 0.1µF 6.3V 3 2 K Q 6 2 U4 13 K Q 7 CLR DVDD; 14 CLR AGND; 7 15 14 74LCX112 74LCX112 AGND; 8 U7 U7 DVDD; 16 02706-107 AD9777 Figure 108. AD9777 Evaluation Board Input (B Channel) and SPI Port Circuitry Rev. C | Page 54 of 60 R21 CLKVDD R14 C47 DNP RC0805 200Ω 1nF c RC0805 R20 R1 R2 R3 R4 R5 R6 R7 R8 R9 R1 R2 R3 R4 R5 R6 R7 R8 R9 c CC805 RCOM RCOM RC0805 R4 DNP CLKVDD RP12 RP9 120Ω RC0805 MC100EPT22 C46 JP42 50Ω DNP DATA-B 1 2 3 45 67 8 9 10 1 2 3 4 567 89 10 0.1µF 1 CLKP 7 R19 U8 JP41 2 100Ω CC805 CLKN CGND; 5 RP3 22Ω R22 2 1 BD15 R13 CLKVDD; 8 116 DNP C48 RP3 22Ω RC0805 CLKVDD 120Ω ACLKX RC0805 4 3 BD14 1nF 215 R24 RC0805 RP3 22Ω DNP RC0805 6 5 BD13 314 c c CC805 R18 RP3 22Ω c 8 7 BD12 200Ω 413 CLKDD RP3 22Ω MC100EPT22 10 9 BD11 512 3 RP3 22Ω 6 12 11 BD10 U8 611 +C49 CC805 C60 ACASE 4 RP3 22Ω c 4.7µF 14 13 BD09 0.1µF 710 CLKVDD; 8 6.3V RP3 22Ω 16 15 BD08 CGND; 5 89 RP4 22Ω 18 17 BD07 c 116 RP4 22Ω 20 19 BD06 215 RP4 22Ω 22 21 BD05 314 RP4 22Ω 24 23 BD04 413 RP4 22Ω 26 25 BD03 512 RP4 22Ω 28 27 BD02 611 RP4 22Ω 30 29 R50 BD01 710 12 13 9kΩ RP4 22Ω 2 1 32 31 BD00 U5 U5 RC0805 89 DGND; 7 DGND; 7 74AC14 74AC14 34 33 DVDD; 14 DVDD; 14 36 35 R48 SPI PORT 1 2 3 45 67 8 9 10 RP11 1 2 3 4 567 89 10 10 9kΩ 38 37 43 11 P1 RP10 U5 U5 50Ω RC0805 RCOM DNP 1 40 39 RCOM DGND; 7 DGND; 7 74AC14 74AC14 R1 R2 R3 R4 R5 R6 R7 R8 R9 R1 R2 R3 R4 R5 R6 R7 R8 R9 DVDD; 14 DVDD; 14 2 RIBBON J2 R45 3 65 89 9kΩ 4 SPCSB U5 U5 RC0805 DGND; 7 DGND; 7 5 74AC14 74AC14 DVDD; 14 DVDD; 14 SPCLK 6 SPSDI 2 13 1 12 SPSDO U6 U6 DGND; 7 DGND; 7 DVDD; 14 DVDD; 14 74AC14 74AC14 4 10 3 11 U6 U6 DVDD DVDD DGND; 7 DGND; 7 DVDD; 14 74AC14 DVDD; 14 74AC14 C43 C44 + + CC805 C50 C51 ACASE CC805 ACASE 4.7µF 4.7µF 0.1µF 0.1µF 6.3V 6 8 5 9 6.3V U6 U6 DGND; 7 DGND; 7 DVDD; 14 74AC14 DVDD; 14 74AC14 02706-108 AD9777 Figure 109. AD9777 Evaluation Board Components, Top Side Figure 110. AD9777 Evaluation Board Components, Bottom Side Rev. C | Page 55 of 60 02706-110 02706-109 AD9777 Figure 111. AD9777 Evaluation Board Layout, Layer One (Top) Figure 112. AD9777 Evaluation Board Layout, Layer Two (Ground Plane) Rev. C | Page 56 of 60 02706-111 02706-112 AD9777 Figure 113. AD9777 Evaluation Board Layout, Layer Three (Power Plane) Figure 114. AD9777 Evaluation Board Layout, Layer Four (Bottom) Rev. C | Page 57 of 60 02706-114 02706-113 AD9777 OUTLINE DIMENSIONS 14.20 14.00 SQ 12.20 13.80 1.20 12.00 SQ 0.75 MAX 11.80 0.60 0.45 61 80 80 61 1 60 1 60 PIN 1 EXPOSED TOP VIEW 6.00 PAD (PINS DOWN) BSC SQ BOTTOM VIEW 0° MIN 1.05 (PINS UP) 0.20 1.00 0.09 20 41 41 20 0.95 7° 40 40 21 21 3.5° VIEW A 0.15 0.50 BSC 0.27 0° SEATING LEAD PITCH 0.05 0.08 MAX 0.22 PLANE COPLANARITY 0.17 VIEW A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-ADD-HD Figure 115. 80-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] (SV-80-1) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option AD9777BSV −40°C to +85°C 80-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] SV-80-1 AD9777BSVRL −40°C to +85°C 80-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] SV-80-1 1 AD9777BSVZ −40°C to +85°C 80-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] SV-80-1 1 AD9777BSZVRL −40°C to +85°C 80-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] SV-80-1 AD9777-EB Evaluation Board 1 Z = Pb-free part. Rev. C | Page 58 of 60 AD9777 NOTES Rev. C | Page 59 of 60 AD9777 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C02706-0-1/06(C) Rev. C | Page 60 of 60