ANALOG DEVICES AD9775

14-Bit, 160 MSPS, 2×/4×/8× Interpolating ® Dual TxDAC+ Digital-to-Analog Converter AD9775 FEATURES Versatile input data interface Twos complement/straight binary data coding 14-bit resolution, 160 MSPS/400 MSPS input/output Dual-port or single-port interleaved input data data rate Single 3.3 V supply operation Selectable 2×/4×/8× interpolating filter Power dissipation: 1.2 W @ 3.3 V typical Programmable channel gain and offset adjustment On-chip, 1.2 V reference f /4, f /8 digital quadrature modulation capability S S 80-lead, thin quad flat package, exposed pad (TQFP_EP) Direct IF transmission mode for 70 MHz + IFs Enables image rejection architecture APPLICATIONS Fully compatible SPI® port Communications Excellent ac performance Analog quadrature modulation architecture SFDR: −71 dBc @ 2 MHz to 35 MHz 3G, multicarrier GSM, TDMA, CDMA systems W-CDMA ACPR: −71 dB @ IF = 19.2 MHz Broadband wireless, point-to-point microwave radios Internal PLL clock multiplier Instrumentation/ATE Selectable internal clock divider Versatile clock input Differential/single-ended sine wave or TTL/CMOS/LVPECL compatible FUNCTIONAL BLOCK DIAGRAM IDAC COS AD9775 HALF- HALF- HALF- GAIN OFFSET BAND BAND BAND DAC DAC FILTER1* FILTER2* FILTER3* DATA SIN ASSEMBLER IMAGE 14 16 16 16 16 REJECTION/ I I/Q DAC DUAL DAC LATCH f /2, 4, 8 DAC GAIN/OFFSET MODE REGISTERS I AND Q BYPASS NONINTERLEAVED MUX OR INTERLEAVED SIN DATA 16 16 16 16 Q LATCH 14 FILTER BYPASS COS WRITE MUX MUX CONTROL I SELECT IDAC OUT /2 (f ) DAC CLOCK OUT /2 /2 /2 SPI INTERFACE AND PRESCALER DIFFERENTIAL CONTROL REGISTERS CLK PHASE DETECTOR AND VCO * HALF-BAND FILTERS ALSO CAN BE CONFIGURED FOR ZERO STUFFING ONLY PLL CLOCK MULTIPLIER AND CLOCK DIVIDER Figure 1. Rev. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. VREF IOFFSET 02858-001 AD9775 TABLE OF CONTENTS Features .............................................................................................. 1 1R/2R Mode ................................................................................ 25 Applications....................................................................................... 1 Clock Input Configurations...................................................... 25 Functional Block Diagram .............................................................. 1 Programmable PLL .................................................................... 26 Revision History ............................................................................... 3 Power Dissipation....................................................................... 27 General Description ......................................................................... 4 Sleep/Power-Down Modes........................................................ 28 Product Highlights ....................................................................... 4 Two-Port Data Input Mode ...................................................... 28 Specifications..................................................................................... 5 PLL Enabled, Two-Port Mode .................................................. 28 DC Specifications ......................................................................... 5 DATACLK Inversion.................................................................. 29 Dynamic Specifications ............................................................... 6 DATACLK Driver Strength....................................................... 29 Digital Specifications ................................................................... 7 PLL Enabled, One-Port Mode .................................................. 29 Digital Filter Specifications ......................................................... 8 ONEPORTCLK Inversion......................................................... 29 Absolute Maximum Ratings............................................................ 9 ONEPORTCLK Driver Strength.............................................. 30 ESD Caution.................................................................................. 9 IQ Pairing .................................................................................... 30 Thermal Resistance ...................................................................... 9 PLL Disabled, Two-Port Mode................................................. 30 Pin Configuration and Function Descriptions........................... 10 PLL Disabled, One-Port Mode................................................. 30 Typical Performance Characteristics ........................................... 12 Digital Filter Modes ................................................................... 31 Terminology .................................................................................... 17 Amplitude Modulation.............................................................. 31 Mode Control (via SPI Port) ......................................................... 18 Modulation, No Interpolation .................................................. 32 Register Descriptions ..................................................................... 19 Modulation, Interpolation = 2× ............................................... 33 Address 0x00 ............................................................................... 19 Modulation, Interpolation = 4× ............................................... 34 Address 0x01 ............................................................................... 19 Modulation, Interpolation = 8× ............................................... 35 Address 0x02 ............................................................................... 19 Zero Stuffing ............................................................................... 36 Address 0x03 ............................................................................... 20 Interpolating (Complex Mix Mode)........................................ 36 Address 0x04 ............................................................................... 20 Operations on Complex Signals............................................... 36 Address 0x05, Address 0x09 ..................................................... 20 Complex Modulation and Image Rejection of Baseband Signals .......................................................................................... 37 Address 0x06, Address 0x0A..................................................... 20 Image Rejection and Sideband Suppression of Modulated Address 0x07, Address 0x0B ..................................................... 20 Carriers ........................................................................................ 38 Address 0x08, Address 0x0C..................................................... 20 Applying the Output Configurations........................................... 42 Address 0x08, Address 0x0C..................................................... 20 Unbuffered Differential Output, Equivalent Circuit ............. 42 Functional Description .................................................................. 21 Differential Coupling Using a Transformer............................ 42 Serial Interface for Register Control ........................................ 21 Differential Coupling Using an Op Amp................................ 43 General Operation of the Serial Interface ............................... 21 Interfacing the AD9775 with the AD8345 Quadrature Instruction Byte .......................................................................... 22 Modulator.................................................................................... 43 Serial Interface Port Pin Descriptions ..................................... 22 Evaluation Board ............................................................................ 44 MSB/LSB Transfers..................................................................... 22 Outline Dimensions....................................................................... 54 Notes on Serial Port Operation ................................................ 22 Ordering Guide .......................................................................... 54 DAC Operation........................................................................... 24 Rev. E | Page 2 of 56 AD9775 REVISION HISTORY 2/03—Rev. 0 to Rev. A 12/06—Rev. D to Rev. E Edits to Features ...............................................................................1 Changes to Figure 52, Figure 54, Figure 55, and Figure 56 .......29 Edits to DC Specifications ..............................................................3 1/06—Rev. C to Rev. D Edits to Dynamic Specifications ....................................................4 Updated Formatting..........................................................Universal Edits to Pin Function Descriptions ...............................................8 Changes to Figure 32 .................................................................... 22 Edits to Table I ............................................................................... 14 Changes to Figure 108 .................................................................. 55 Edits to Register Description—Address 02h............................. 15 Updated Outline Dimensions...................................................... 58 Edits to Register Description—Address 03h............................. 16 Changes to Ordering Guide......................................................... 58 Edits to Register Description—Address 07h, 0Bh.................... 16 6/04—Rev. B to Rev. C Edits to Equation 1........................................................................ 16 Updated Layout .................................................................Universal Edits to MSB/LSB Transfers......................................................... 18 Changes to DC Specifications ....................................................... 5 Edits to Programmable PLL......................................................... 21 Changes to Absolute Maximum Ratings...................................... 9 Added New Figure 14 ................................................................... 22 Changes to the DAC Operation Section .................................... 25 Renumbered Figures 15–69......................................................... 22 Inserted Figure 38.......................................................................... 25 Added Two-Port Data Input Mode Section............................... 23 Changes to Figure 40 .................................................................... 26 Edits to PLL Enabled, Two-Port Mode ...................................... 24 Changes to Table 11 ...................................................................... 28 Edits to Figure 19 .......................................................................... 24 Changes to Programmable PLL Section..................................... 28 Edits to Figure 21 .......................................................................... 25 Changes to Figures 49, 50, and 51............................................... 29 Edits to PLL Disabled, Two-Port Mode ..................................... 25 Changes to the PLL Enabled, One-Port Mode Section............ 30 Edits to Figure 22 .......................................................................... 25 Changes to the PLL Disabled, One-Port Mode Section........... 31 Edits to Figure 23 .......................................................................... 26 Changes to the Ordering Guide .................................................. 57 Edits to Figure 26a ........................................................................ 27 Updated Outline Dimensions...................................................... 57 Edits to Complex Modulation and Image Rejection of Baseband Signals............................................................................................. 31 3/03—Rev. A to Rev. B Edits to Evaluation Board ............................................................ 39 Changes to Register Description—Address 04h ....................... 16 Edits to Figures 56–59 .................................................................. 40 Changes to Equation 1.................................................................. 16 Replaced Figures 60–69................................................................ 42 Changes to Figure 8....................................................................... 20 Updated Outline Dimensions...................................................... 49 Rev. E | Page 3 of 56 AD9775 GENERAL DESCRIPTION 1 The AD9775 is the 14-bit member of the AD977x pin- The AD9775 is manufactured on an advanced 0.35 micron compatible, high performance, programmable 2×/4×/8× CMOS process, operates from a single supply of 3.1 V to 3.5 V, interpolating TxDAC+ family. The AD977x family features a and consumes 1.2 W of power. serial port interface (SPI) that provides a high level of Targeted at wide dynamic range, multicarrier and multistandard programmability, thus allowing for enhanced system-level systems, the superb baseband performance of the AD9775 is options. These options include selectable 2×/4×/8× ideal for wideband CDMA, multicarrier CDMA, multicarrier interpolation filters; f /2, f /4, or f /8 digital quadrature S S S TDMA, multicarrier GSM, and high performance systems modulation with image rejection; a direct IF mode; employing high order QAM modulation schemes. The image programmable channel gain and offset control; programmable rejection feature simplifies and can help reduce the number of internal clock divider; straight binary or twos complement data signal band filters needed in a transmit signal chain. The direct interface; and a single-port or dual-port data interface. IF mode helps to eliminate a costly mixer stage for a variety of The selectable 2×/4×/8× interpolation filters simplify the communications systems. requirements of the reconstruction filters while simultaneously PRODUCT HIGHLIGHTS enhancing the pass-band noise/distortion performance of 1. The AD9775 is the 14-bit member of the AD977x pin- TxDAC+ devices. The independent channel gain and offset compatible, high performance, programmable 2×/4×/8× adjust registers allow the user to calibrate LO feedthrough and interpolating TxDAC+ family. sideband suppression errors associated with analog quadrature 2. Direct IF transmission capability for 70 MHz + IFs through modulators. The 6 dB of gain adjustment range can also be used a novel digital mixing process. to control the output power level of each DAC. 3. f /2, f /4, and f /8 digital quadrature modulation and user- S S S The AD9775 can perform f /2, f /4, and f /8 digital modulation S S S selectable image rejection to simplify/remove cascaded and image rejection when combined with an analog quadrature SAW filter stages. modulator. In this mode, the AD9775 accepts I and Q complex 4. A 2×/4×/8× user-selectable, interpolating filter eases data data (representing a single or multicarrier waveform), generates rate and output signal reconstruction filter requirements. a quadrature modulated IF signal along with its orthogonal 5. User-selectable, twos complement/straight binary data representation via its dual DACs, and presents these two coding. reconstructed orthogonal IF carriers to an analog quadrature 6. User-programmable, channel gain control over 1 dB range modulator to complete the image rejection upconversion in 0.01 dB increments. process. Another digital modulation mode (that is, the direct IF 7. User programmable channel offset control ±10% over the mode) allows the original baseband signal representation to be FSR. frequency translated such that pairs of images fall at multiples 8. Ultrahigh speed 400 MSPS DAC conversion rate. of one-half the DAC update rate. 9. Internal clock divider provides data rate clock for easy interfacing. The AD977x family includes a flexible clock interface that 10. Flexible clock input with single-ended or differential input, accepts differential or single-ended sine wave or digital logic CMOS, or 1 V p-p LO sine wave input capability. inputs. An internal PLL clock multiplier is included and 11. Low power: complete CMOS DAC operates on 1.2 W from generates the necessary on-chip high frequency clocks. It can a 3.1 V to 3.5 V single supply. The 20 mA full-scale current also be disabled to allow the use of a higher performance can be reduced for lower power operation and several sleep external clock source. An internal programmable divider functions are provided to reduce power during idle simplifies clock generation in the converter when using an periods. external clock source. A flexible data input interface allows for 12. On-chip voltage reference. The AD9775 includes a 1.20 V straight binary or twos complement formats and supports temperature compensated band gap voltage reference. single-port interleaved or dual-port data. 13. 80-lead, thin quad flat package, exposed pad (TQFP_EP). Dual high performance DAC outputs provide a differential current output programmable over a 2 mA to 20 mA range. 1 Protected by U.S. Patent Numbers 5,568,145; 5,689,257; and 5,703,519. Other patents pending. Rev. E | Page 4 of 56 AD9775 SPECIFICATIONS DC SPECIFICATIONS T to T , AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 3.3 V, I = 20 mA, unless otherwise noted. MIN MAX OUTFS Table 1. Parameter Min Typ Max Unit RESOLUTION 14 Bits 1 DC Accuracy Integral Nonlinearity −5 ±1.5 +5 LSB Differential Nonlinearity −3 ±1.0 +3 LSB ANALOG OUTPUT (for 1R and 2R Gain Setting Modes) Offset Error −0.02 ±0.01 +0.02 % of FSR Gain Error (with Internal Reference) −1.0 +1.0 % of FSR Gain Matching −1.0 ±0.1 +1.0 % of FSR 2 Full-Scale Output Current 2 20 mA Output Compliance Range −1.0 +1.25 V Output Resistance 200 kΩ Output Capacitance 3 pF Gain, Offset Cal DACs, Monotonicity Guaranteed REFERENCE OUTPUT Reference Voltage 1.14 1.20 1.26 V 3 Reference Output Current 100 nA REFERENCE INPUT Input Compliance Range 0.1 1.25 V Reference Input Resistance 7 kΩ Small Signal Bandwidth 0.5 MHz TEMPERATURE COEFFICIENTS Offset Drift 0 ppm of FSR/°C Gain Drift (with Internal Reference) 50 ppm of FSR/°C Reference Voltage Drift ±50 ppm/°C POWER SUPPLY AVDD Voltage Range 3.1 3.3 3.5 V 4 Analog Supply Current (I ) 72.5 76 mA AVDD I in SLEEP Mode 23.3 26 mA AVDD CLKVDD Voltage Range 3.1 3.3 3.5 V 4 Clock Supply Current (ICLKVDD) 8.5 10.0 mA CLKVDD (PLL ON) Clock Supply Current (I ) 23.5 mA CLKVDD DVDD Voltage Range 3.1 3.3 3.5 V 4 Digital Supply Current (IDVDD) 34 41 mA Nominal Power Dissipation 380 410 mW 5 P 1.75 W DIS P IN PWDN 6.0 mW DIS Power Supply Rejection Ratio—AVDD ±0.4 % of FSR/V OPERATING RANGE −40 +85 °C 1 Measured at I driving a virtual ground. OUTA 2 Nominal full-scale current, IOUTFS, is 32 × the IREF current. 3 Use an external amplifier to drive any external load. 4 100 MSPS fDAC with fOUT = 1 MHz, all supplies = 3.3 V, no interpolation, no modulation. 5 400 MSPS f = 50 MSPS, f /2 modulation, PLL enabled. DAC S Rev. E | Page 5 of 56 AD9775 DYNAMIC SPECIFICATIONS TMIN to TMAX, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 0 V, IOUTFS = 20 mA, interpolation = 2×, differential transformer-coupled output, 50 Ω doubly terminated, unless otherwise noted. Table 2. Parameter Min Typ Max Unit DYNAMIC PERFORMANCE Maximum DAC Output Update Rate (fDAC) 400 MSPS Output Settling Time (tST) to 0.025% 11 ns 1 Output Rise Time 10% to 90% 0.8 ns 1 Output Fall Time 10% to 90% 0.8 ns Output Noise, IOUTFS = 20 mA 50 pA/√Hz AC LINEARITY—BASEBAND MODE Spurious-Free Dynamic Range (SFDR) to Nyquist (f = 0 dBFS) OUT fDATA = 100 MSPS, fOUT = 1 MHz 71 84.5 dBc fDATA = 65 MSPS, fOUT = 1 MHz 84 dBc fDATA = 65 MSPS, fOUT = 15 MHz 80 dBc f = 78 MSPS, f = 1 MHz 84 dBc DATA OUT f = 78 MSPS, f = 15 MHz 80 dBc DATA OUT f = 160 MSPS, f = 1 MHz 82 dBc DATA OUT fDATA = 160 MSPS, fOUT = 15 MHz 80 dBc Spurious-Free Dynamic Range Within a 1 MHz Window fOUT = 0 dBFS, fDATA = 100 MSPS, fOUT = 1 MHz 73 91.3 dBc Two-Tone Intermodulation (IMD) to Nyquist (f = f = −6 dBFS) OUT1 OUT2 f = 65 MSPS, f = 10 MHz; f = 11 MHz 81 dBc DATA OUT1 OUT2 fDATA = 65 MSPS, fOUT1 = 20 MHz; fOUT2 = 21 MHz 76 dBc fDATA = 78 MSPS, fOUT1 = 10 MHz; fOUT2 = 11 MHz 81 dBc fDATA = 78 MSPS, fOUT1 = 20 MHz; fOUT2 = 21 MHz 76 dBc f = 160 MSPS, f = 10 MHz; f = 11 MHz 81 dBc DATA OUT1 OUT2 f = 160 MSPS, f = 20 MHz; f = 21 MHz 76 dBc DATA OUT1 OUT2 Total Harmonic Distortion (THD) fDATA = 100 MSPS, fOUT = 1 MHz; 0 dBFS −71 −82.5 dB Signal-to-Noise Ratio (SNR) fDATA = 78 MSPS, fOUT = 5 MHz; 0 dBFS 76 dB f = 160 MSPS, f = 5 MHz; 0 dBFS 74 dB DATA OUT Adjacent Channel Power Ratio (ACPR) W-CDMA with 3.84 MHz BW, 5 MHz Channel Spacing IF = Baseband, fDATA = 76.8 MSPS 71 dBc IF = 19.2 MHz, fDATA = 76.8 MSPS 71 dBc Four-Tone Intermodulation 21 MHz, 22 MHz, 23 MHz, and 24 MHz at −12 dBFS (f = MSPS, Missing Center) 75 dBFS DATA AC LINEARITY—IF MODE Four-Tone Intermodulation at IF = 200 MHz 201 MHz, 202 MHz, 203 MHz, and 204 MHz at −12 dBFS (f = 160 MSPS, f = 320 MHz) 72 dBFS DATA DAC 1 Measured single-ended into 50 Ω load. Rev. E | Page 6 of 56 AD9775 DIGITAL SPECIFICATIONS TMIN to TMAX, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, DVDD = 3.3 V, IOUTFS = 20 mA, unless otherwise noted. Table 3. Parameter Min Typ Max Unit DIGITAL INPUTS Logic 1 Voltage 2.1 3 V Logic 0 Voltage 0 0.9 V Logic 1 Current −10 +10 μA Logic 0 Current −10 +10 μA Input Capacitance 5 pF CLOCK INPUTS Input Voltage Range 0 3 V Common-Mode Voltage 0.75 1.5 2.25 V Differential Voltage 0.5 1.5 V SERIAL CONTROL BUS Maximum SCLK Frequency (f ) 15 MHz SLCK Minimum Clock Pulse Width High (tPWH) 30 ns Minimum Clock Pulse Width Low (tPWL) 30 ns Maximum Clock Rise/Fall Time 1 ms Minimum Data/Chip Select Setup Time (t ) 25 ns DS Minimum Data Hold Time (t ) 0 ns DH Maximum Data Valid Time (tDV) 30 ns RESET Pulse Width 1.5 ns Inputs (SDI, SDIO, SCLK, CSB) Logic 1 Voltage 2.1 3 V Logic 0 Voltage 0 0.9 V Logic 1 Current −10 +10 μA Logic 0 Current −10 +10 μA Input Capacitance 5 pF SDIO Output Logic 1 Voltage DRVDD − 0.6 V Logic 0 Voltage 0.4 V Logic 1 Current 30 50 mA Logic 0 Current 30 50 mA Rev. E | Page 7 of 56 AD9775 DIGITAL FILTER SPECIFICATIONS 20 Table 4. Half-Band Filter No. 1 (43 Coefficients) Tap Coefficient 0 1, 43 8 –20 2, 42 0 3, 41 −29 –40 4, 40 0 5, 39 67 –60 6, 38 0 –80 7, 37 −134 8, 36 0 –100 9, 35 244 10, 34 0 –120 0 0.5 1.0 1.5 2.0 11, 33 −414 f (NORMALIZED TO INPUT DATA RATE) OUT 12, 32 0 13, 31 673 Figure 2. 2× Interpolating Filter Response 14, 30 0 20 15, 29 −1079 16, 28 0 0 17, 27 1772 18, 26 0 –20 19, 25 −3280 –40 20, 24 0 21, 23 10,364 –60 22 16,384 –80 Table 5. Half-Band Filter No. 2 (19 Coefficients) –100 Tap Coefficient 1, 19 19 –120 2, 18 0 0 0.5 1.0 1.5 2.0 3, 17 −120 f (NORMALIZED TO INPUT DATA RATE) OUT 4, 16 0 5, 15 438 Figure 3. 4× Interpolating Filter Response 6, 14 0 20 7, 13 −1288 8, 12 0 0 9, 11 5,047 –20 10 8,192 –40 Table 6. Half-Band Filter No. 3 (11 Coefficients) Tap Coefficient –60 1, 11 7 –80 2, 10 0 3, 9 −53 –100 4, 8 0 5, 7 302 –120 04 2 68 6 512 f (NORMALIZED TO INPUT DATA RATE) OUT Figure 4. 8× Interpolating Filter Response Rev. E | Page 8 of 56 ATTENUATION (dBFS) ATTENUATION (dBFS) ATTENUATION (dBFS) 02858-004 02858-003 02858-002 AD9775 ABSOLUTE MAXIMUM RATINGS Table 7. Parameter With Respect To Rating AVDD, DVDD, CLKVDD AGND, DGND, CLKGND −0.3 V to +4.0 V AVDD, DVDD, CLKVDD AVDD, DVDD, CLKVDD −4.0 V to +4.0 V AGND, DGND, CLKGND AGND, DGND, CLKGND −0.3 V to +0.3 V REFIO, FSADJ1/FSADJ2 AGND −0.3 V to AVDD + 0.3 V IOUTA, IOUTB AGND −1.0 V to AVDD + 0.3 V P1B13 to P1B0, P2B13 to P2B0, RESET DGND −0.3 V to DVDD + 0.3 V DATACLK, PLL_LOCK DGND −0.3 V to DVDD + 0.3 V CLK+, CLK– CLKGND −0.3 V to CLKVDD + 0.3 V LPF CLKGND −0.3 V to CLKVDD + 0.3 V SPI_CSB, SPI_CLK, SPI_SDIO, SPI_SDO DGND −0.3 V to DVDD + 0.3 V Junction Temperature 125°C Storage Temperature −65°C to +150°C Lead Temperature (10 sec) 300°C Stresses above those listed under Absolute Maximum Ratings THERMAL RESISTANCE may cause permanent damage to the device. This is a stress θJA is specified for the worst-case conditions, that is, a device rating only; functional operation of the device at these or any soldered in a circuit board for surface-mount packages. other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute Table 8. Thermal Resistance maximum rating conditions for extended periods may affect Package Type θJA Unit device reliability. 80-Lead Thin Quad Flat Package 23.5 °C/W (TQFP_EP), Exposed Pad ESD CAUTION Rev. E | Page 9 of 56 AD9775 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 1 CLKVDD 60 FSADJ1 PIN 1 LPF 2 59 FSADJ2 CLKVDD 3 58 REFIO CLKGND 4 57 RESET 5 56 CLK+ SPI_CSB 6 55 CLK– SPI_CLK 7 54 CLKGND SPI_SDIO AD9775 DATACLK/PLL_LOCK 8 53 SPI_SDO TxDAC+ DGND 9 52 DGND TOP VIEW (Not to Scale) DVDD 10 51 DVDD P1B13 (MSB) 11 50 NC 12 49 P1B12 NC 13 48 P1B11 P2B0 (LSB) 14 47 P1B10 P2B1 15 46 P1B9 P2B2 16 45 P1B8 P2B3 17 44 DGND DGND DVDD 18 43 DVDD P1B7 19 42 P2B4 P1B6 20 41 P2B5 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 NC = NO CONNECT Figure 5. Pin Configuration Rev. E | Page 10 of 56 P1B5 AVDD P1B4 AGND P1B3 AVDD AGND P1B2 AVDD DGND DVDD AGND P1B1 AGND P1B0 (LSB) I OUTA1 NC I OUTB1 AGND NC IQSEL/P2B13 (MSB) AGND ONEPORTCLK/P2B12 I OUTA2 P2B11 I OUTB2 P2B10 AGND DGND AGND DVDD AVDD P2B9 AGND P2B8 AVDD P2B7 AGND P2B6 AVDD 02858-005 AD9775 Table 9. Pin Function Descriptions Pin No. Mnemonic Description 1, 3 CLKVDD Clock Supply Voltage. 2 LPF PLL Loop Filter. 4, 7 CLKGND Clock Supply Common. 5 CLK+ Differential Clock Input. 6 CLK− Differential Clock Input. 8 DATACLK/PLL_LOCK With the PLL enabled, this pin indicates the state of the PLL. A read of a Logic 1 indicates the PLL is in the locked state. Logic 0 indicates the PLL has not achieved lock. This pin may also be programmed to act as either an input or output (Address 02h, Bit 3) DATACLK signal running at the input data rate. 9, 17, 25, 35, 44, 52 DGND Digital Common. 10, 18, 26, 36, 43, 51 DVDD Digital Supply Voltage. 11 to 16, 19 to 24, 27, 28 P1B13 (MSB) to P1B0 Port 1 Data Inputs. (LSB) 29, 30, 49, 50 NC No Connect. 31 IQSEL/P2B13 (MSB) In one-port mode, IQSEL = 1 followed by a rising edge of the differential input clock latches the data into the I channel input register. IQSEL = 0 latches the data into the Q channel input register. In two-port mode, this pin becomes the Port 2 MSB. 32 ONEPORTCLK/P2B12 With the PLL disabled and the AD9775 in one-port mode, this pin becomes a clock output that runs at twice the input data rate of the I and Q channels. This allows the AD9775 to accept and demux interleaved I and Q data to the I and Q input registers. 33, 34, 37 to 42, 45 to 48 P2B11 to P2B0 (LSB) Port 2 Data Inputs. 53 SPI_SDO In the case where SDIO is an input, SDO acts as an output. When SDIO becomes an output, SDO enters a High-Z state. This pin can also be used as an output for the data rate clock. For more information, see the Two-Port Data Input Mode section. 54 SPI_SDIO Bidirectional Data Pin. Data direction is controlled by Bit 7 of Register Address 0x00. The default setting for this bit is 0, which sets SDIO as an input. 55 SPI_CLK Data input to the SPI port is registered on the rising edge of SPI_CLK. Data output on the SPI port is registered on the falling edge. 56 SPI_CSB Chip Select/SPI Data Synchronization. On momentary logic high, resets SPI port logic and initializes instruction cycle. 57 RESET Logic 1 resets all of the SPI port registers, including Address 0x00, to their default values. A software reset can also be done by writing a Logic 1 to SPI Register 00h, Bit 5. However, the software reset has no effect on the bit in Address 0x00. 58 REFIO Reference Output, 1.2 V Nominal. 59 FSADJ2 Full-Scale Current Adjust, Q Channel. 60 FSADJ1 Full-Scale Current Adjust, I Channel. 61, 63, 65, 76, 78, 80 AVDD Analog Supply Voltage. 62, 64, 66, 67, 70, 71, AGND Analog Common. 74, 75, 77, 79 68, 69 I , I Differential DAC Current Outputs, Q Channel. OUTB2 OUTA2 72, 73 I , I Differential DAC Current Outputs, I Channel. OUTB1 OUTA1 Rev. E | Page 11 of 56 AD9775 TYPICAL PERFORMANCE CHARACTERISTICS T = 25°C, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, IOUTFS = 20 mA, interpolation = 2×, differential transformer-coupled output, 50 Ω doubly terminated, unless otherwise noted. 10 10 0 0 –10 –10 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 0 65 130 0 50 100 150 FREQUENCY (MHz) FREQUENCY (MHz) Figure 6. Single-Tone Spectrum @ fDATA = 65 MSPS with fOUT = fDATA/3 Figure 9. Single-Tone Spectrum @ fDATA = 78 MSPS with fOUT = fDATA/3 90 90 0dBFS 0dBFS 85 85 –6dBFS 80 80 75 75 –12dBFS –12dBFS 70 70 –6dBFS 65 65 60 60 55 55 50 50 0 5 10 15 20 25 30 0 5 10 15 20 25 30 FREQUENCY (MHz) FREQUENCY (MHz) Figure 7. In-Band SFDR vs. f @ f = 65 MSPS Figure 10. In-Band SFDR vs. f @ f = 78 MSPS OUT DATA OUT DATA 90 90 –6dBFS 85 85 –6dBFS 0dBFS 0dBFS 80 80 75 75 70 70 –12dBFS –12dBFS 65 65 60 60 55 55 50 50 0 5 10 15 20 25 30 0 5 10 15 20 25 30 FREQUENCY (MHz) FREQUENCY (MHz) Figure 8. Out-of-Band SFDR vs. fOUT @ fDATA = 65 MSPS Figure 11. Out-of-Band SFDR vs. f @ f = 78 MSPS OUT DATA Rev. E | Page 12 of 56 SFDR (dBc) SFDR (dBc) AMPLITUDE (dBm) 02858-008 02858-007 02858-006 SFDR (dBc) SFDR (dBc) AMPLITUDE (dBm) 02858-011 02858-010 02858-009 AD9775 10 90 –6dBFS –3dBFS 0 85 –10 80 –20 75 –30 0dBFS –40 70 –50 65 –60 60 –70 55 –80 –90 50 0 100 200 300 0 5 10 15 20 25 30 FREQUENCY (MHz) FREQUENCY (MHz) Figure 12. Single-Tone Spectrum @ fDATA = 160 MSPS with fOUT = fDATA/3 Figure 15. Third-Order IMD Products vs. f @ f = 65 MSPS OUT DATA 90 90 –6dBFS –6dBFS 0dBFS 85 85 0dBFS 80 80 75 75 70 70 –12dBFS –3dBFS 65 65 60 60 55 55 50 50 0 102030 40 50 0 5 10 15 20 25 30 FREQUENCY (MHz) FREQUENCY (MHz) Figure 13. In-Band SFDR vs. f @ f = 160 MSPS OUT DATA Figure 16. Third-Order IMD Products vs. fOUT @ fDATA = 78 MSPS 90 90 85 85 –6dBFS 80 80 –6dBFS 75 75 0dBFS –3dBFS 70 70 0dBFS 65 65 60 60 –12dBFS 55 55 50 50 0 102030 40 50 0 10 20 30 405060 FREQUENCY (MHz) FREQUENCY (MHz) Figure 14. Out-of-Band SFDR vs. fOUT @ fDATA = 160 MSPS Figure 17. Third-Order IMD Products vs. fOUT @ fDATA = 160 MSPS Rev. E | Page 13 of 56 SFDR (dBc) SFDR (dBc) AMPLITUDE (dBm) 02858-014 02858-013 02858-012 IMD (dBc) IMD (dBc) IMD (dBc) 02858-017 02858-016 02858-015 AD9775 90 90 –3dBFS 8× 85 85 80 80 0dBFS 75 75 –6dBFS 4× 2× 70 70 1× 65 65 60 60 55 55 50 50 0 10 20 30 405060 3.1 3.2 3.3 3.4 3.5 FREQUENCY (MHz) AVDD (V) Figure 18. Third-Order IMD Products vs. fOUT and Interpolation Rate, Figure 21. Third-Order IMD Products vs. AVDD @ fOUT = 10 MHz, 1× fDATA = 160 MSPS, 2× fDATA = 160 MSPS, 4× fDATA = 80 MSPS, fDAC = 320 MSPS, fDATA = 160 MSPS 8× fDATA = 50 MSPS 90 90 4× 8× 85 85 80 80 75 75 2× 1× PLL OFF 70 70 65 65 60 60 PLL ON 55 55 50 50 –15 –10 –5 0 0 50 100 150 A (dBFS) OUT INPUT DATA RATE (MSPS) Figure 19. Third-Order IMD Products vs. A and Interpolation Rate, OUT Figure 22. SNR vs. Data Rate for fOUT = 5 MHz f = 50 MSPS for All Cases, 1× f = 50 MSPS, 2× f = 100 MSPS, DATA DAC DAC 4× f = 200 MSPS, 8× f = 400 MSPS DAC DAC 90 90 78MSPS 0dBFS 85 85 80 80 75 75 f = 65MSPS DATA 160MSPS 70 70 –12dBFS –6dBFS 65 65 60 60 55 55 50 50 –50 0 50 100 3.1 3.2 3.3 3.4 3.5 TEMPERATURE (°C) AVDD (V) Figure 20. SFDR vs. AVDD @ f = 10 MHz, f = 320 MSPS, f = 160 MSPS Figure 23. SFDR vs. Temperature @ fOUT = fDATA/11 OUT DAC DATA Rev. E | Page 14 of 56 IMD (dBc) SFDR (dBc) IMD (dBc) 02858-020 02858-019 02858-018 SFDR (dBc) SNR (dB) SFDR (dBc) 02858-023 02858-022 02858-021 AD9775 0 0 –10 –10 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 –100 0 50 100 150 0 5 10 15 20 25 30 35 40 45 50 FREQUENCY (MHz) FREQUENCY (MHz) Figure 24. Single-Tone Spurious Performance, f = 10 MHz, Figure 27. Two-Tone IMD Performance, fDATA = 150 MSPS, Interpolation = 4× OUT f = 150 MSPS, No Interpolation DATA 0 0 –10 –20 –20 –30 –40 –40 –50 –60 –60 –70 –80 –80 –90 –100 –100 0 50 100 150 200 250 300 010 20 30 40 50 FREQUENCY (MHz) FREQUENCY (MHz) Figure 25. Two-Tone IMD Performance, f = 150 MSPS, No Interpolation DATA Figure 28. Single-Tone Spurious Performance, fOUT = 10 MHz, fDATA = 80 MSPS, Interpolation = 4× 0 0 –10 –10 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 –100 0 5 10 15 20 25 0 50 100 150 200 250 300 FREQUENCY (MHz) FREQUENCY (MHz) Figure 29. Two-Tone IMD Performance, fOUT = 10 MHz, Figure 26. Single-Tone Spurious Performance, fOUT = 10 MHz, fDATA = 50 MSPS, Interpolation = 8× fDATA = 150 MSPS, Interpolation = 2× Rev. E | Page 15 of 56 AMPLITUDE (dBm) AMPLITUDE (dBm) AMPLITUDE (dBm) 02858-026 02858-025 02858-024 AMPLITUDE (dBm) AMPLITUDE (dBm) AMPLITUDE (dBm) 02858-029 02858-028 02858-027 AD9775 0 0 –10 –20 –20 –30 –40 –40 –60 –50 –60 –80 –70 –80 –100 –90 –120 –100 0 100 200 300 400 04 2006080 FREQUENCY (MHz) FREQUENCY (MHz) Figure 30. Single-Tone Spurious Performance, fOUT = 10 MHz, Figure 31. Eight-Tone IMD Performance, fDATA = 160 MSPS, fDATA = 50 MSPS, Interpolation = 8× Interpolation = 8× Rev. E | Page 16 of 56 AMPLITUDE (dBm) 02858-030 AMPLITUDE (dBm) 02858-031 AD9775 TERMINOLOGY Monotonicity Adjacent Channel Power Ratio (ACPR) A DAC is monotonic if the output either increases or remains A ratio in dBc between the measured power within a channel constant as the digital input increases. relative to its adjacent channel. Offset Error Complex Image Rejection The deviation of the output current from the ideal of 0 is called In a traditional two-part upconversion, two images are created offset error. For I , 0 mA output is expected when the inputs OUTA around the second IF frequency. These images are redundant are all 0. For I , 0 mA output is expected when all inputs are OUTB and have the effect of wasting transmitter power and system set to 1. bandwidth. By placing the real part of a second complex modulator in series with the first complex modulator, either the Output Compliance Range upper or lower frequency image near the second IF can be The range of allowable voltage at the output of a current output rejected. DAC. Operation beyond the maximum compliance limits may cause either output stage saturation or breakdown, resulting in Complex Modulation nonlinear performance. The process of passing the real and imaginary components of a jωt signal through a complex modulator (transfer function = e = Pass Band cosωt + jsinωt) and realizing real and imaginary components Frequency band in which any input applied therein passes on the modulator output. unattenuated to the DAC output. Differential Nonlinearity (DNL) Power Supply Rejection DNL is the measure of the variation in analog value, normalized The maximum change in the full-scale output as the supplies to full scale, associated with a 1 LSB change in digital input are varied from minimum to maximum specified voltages. code. Settling Time Gain Error The time required for the output to reach and remain within a The difference between the actual and ideal output span. The specified error band about its final value, measured from the actual span is determined by the output when all inputs are set start of the output transition. to 1 minus the output when all inputs are set to 0. Signal-to-Noise Ratio (SNR) Glitch Impulse SNR is the ratio of the rms value of the measured output signal Asymmetrical switching times in a DAC give rise to undesired to the rms sum of all other spectral components below the output transients that are quantified by a glitch impulse. It is Nyquist frequency, excluding the first six harmonics and dc. specified as the net area of the glitch in pV-s. The value for SNR is expressed in decibels. Group Delay Spurious-Free Dynamic Range Number of input clocks between an impulse applied at the The difference, in dB, between the rms amplitude of the output device input and the peak DAC output current. A half-band FIR signal and the peak spurious signal over the specified filter has constant group delay over its entire frequency range. bandwidth. Impulse Response Stop-Band Rejection Response of the device to an impulse applied to the input. The amount of attenuation of a frequency outside the pass band applied to the DAC, relative to a full-scale signal applied at the Interpolation Filter DAC input within the pass band. If the digital inputs to the DAC are sampled at a multiple rate of f (interpolation rate), a digital filter can be constructed with Temperature Drift DATA a sharp transition band near fDATA/2. Images that would Temperature drift is specified as the maximum change from the typically appear around fDAC (output data rate) can be greatly ambient (25°C) value to the value at either TMIN or TMAX. For suppressed. offset and gain drift, the drift is reported in ppm of full-scale range (FSR) per °C. For reference drift, the drift is reported in Linearity Error ppm per °C. (Also called integral nonlinearity or INL.) It is defined as the maximum deviation of the actual analog output from the ideal Total Harmonic Distortion (THD) output, determined by a straight line drawn from zero scale to THD is the ratio of the rms sum of the first six harmonic full scale. components to the rms value of the measured fundamental. It is expressed as a percentage or in decibels (dB). Rev. E | Page 17 of 56 AD9775 MODE CONTROL (VIA SPI PORT) 1 Table 10. Mode Control via SPI Port Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x00 SDIO LSB, MSB Software Sleep Mode Power-Down 1R/2R Mode PLL_LOCK Bidirectional First, 0 = MSB Reset on Logic 1 Mode Logic 1 DAC Output Indicator Logic 1 Shuts Down Shuts Down All Current Set 0 = Input 1 = LSB 1 = I/O the DAC Digital and by One or Output Analog Two External Currents Functions Resistors 0 = 2R, 1 = 1R −jωt 0x 01 Filter Filter Modulation Modulation 0 = No Zero 1 = Real 0 = e DATACLK/ +jωt 2 Interpolation Interpolation Mode Mode 1 = e Stuffing on Mix Mode PLL_LOCK Rate (1×, 2×, Rate (1×, 2×, 4×, (None, f /2, (None, f /2, Interpolation S S 0 = Complex Select 4×, 8×) 8×) fS/4, fS/8) fS/4, fS/8) Filters, Logic 1 0 = PLLLOCK Mix Mode Enables Zero 1 = DATACLK Stuffing. 0x 02 DATACLK DATACLK ONEPORTCLK IQSEL Invert Q First 0 = Signed 0 = Two-Port Input Data Mode Driver Invert Invert 0 = No Invert 0 = I First 1 = Unsigned 1 = One-Port Strength 0 = No Invert 0 = No Invert 1 = Invert 1 = Q First 1 = Invert 1 = Invert Mode 0x 03 Data Rate PLL Divide PLL Divide 2 Clock Output (Prescaler) (Prescaler) Ratio Ratio 2 0x 04 0 = PLL OFF 0 = Automatic PLL Charge PLL Charge PLL Charge 1 = PLL ON Charge Pump Pump Pump Pump Control Control Control Control, 1 = Programmable 0x 05 IDAC Fine Gain Adjustment 0x 06 IDAC Coarse Gain Adjustment 0x 07 IDAC Offset IDAC Offset IDAC Offset IDAC Offset IDAC Offset IDAC Offset IDAC Offset IDAC Offset Adjustment Adjustment Adjustment Adjustment Adjustment Adjustment Adjustment Adjustment Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 0x 08 IDAC IOFFSET IDAC Offset IDAC Offset Direction Adjustment Adjustment 0 = I Bit 1 Bit 0 OFFSET on I OUTA 1 = IOFFSET on I OUTB 0x 09 QDAC Fine Gain Adjustment 0x 0A QDAC Coarse Gain Adjustment 0x 0B QDAC Offset QDAC Offset QDAC Offset QDAC Offset QDAC Offset QDAC Offset QDAC Offset QDAC Offset Adjustment Adjustment Adjustment Adjustment Adjustment Adjustment Adjustment Adjustment Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 0x 0C QDAC IOFFSET QDAC Offset QDAC Offset Direction Adjustment Adjustment 0 = IOFFSET Bit 1 Bit 0 on IOUTA 1 = I OFFSET on IOUTB 0x 0D Version Register 1 Default values are shown in bold. 2 See the Two-Port Data Input Mode section. Rev. E | Page 18 of 56 AD9775 REGISTER DESCRIPTIONS ADDRESS 0x00 Bit 3: Logic 1 enables zero-stuffing mode for interpolation filters. Bit 7: Logic 0 (default) causes the SPI_SDIO pin to act as an Bit 2: Default (1) enables the real mix mode. The I and Q data input during the data transfer (Phase 2) of the communications channels are individually modulated by fS/2, fS/4, or fS/8 after cycle. When set to 1, SPI_SDIO can act as an input or output, the interpolation filters. However, no complex modulation is depending on Bit 7 of the instruction byte. done. In the complex mix mode (Logic 0), the digital modulators on the I and Q data channels are coupled to create a Bit 6: Logic 0 (default) determines the direction (LSB/MSB digital complex modulator. When the AD9775 is applied in first) of the communications and data transfer communications conjunction with an external quadrature modulator, rejection cycles. Refer to the MSB/LSB Transfers section for more details. can be achieved of either the higher or lower frequency image Bit 5: Writing 1 to this bit resets the registers to their default around the second IF frequency (that is, the LO of the analog values and restarts the chip. The RESET bit always reads back 0. quadrature modulator external to the AD9775) according to the Register Address 0x00 bits are not cleared by this software reset. bit value of Register 0x01, Bit 1. However, a high level at the RESET pin forces all registers, Bit 1: Logic 0 (default) causes the complex modulation to be of including those in Address 0x00, to their default state. − jωt the form e , resulting in the rejection of the higher frequency Bit 4: Sleep Mode. A Logic 1 to this bit shuts down the DAC image when the AD9775 is used with an external quadrature output currents. modulator. A Logic 1 causes the modulation to be of the form Bit 3: Power Down. Logic 1 shuts down all analog and digital +jωt e , which causes rejection of the lower frequency image. functions except for the SPI port. Bit 0: In two-port mode, a Logic 0 (default) causes Pin 8 to act Bit 2: 1R/2R Mode. The default (0) places the AD9775 in two- as a lock indicator for the internal PLL. A Logic 1 in this register resistor mode. In this mode, the I currents for the I and Q REF causes Pin 8 to act as a DATACLK. For more information, see DAC references are set separately by the R resistors on FSADJ1 SET the Two-Port Data Input Mode section. and FSADJ2 (Pin 60 and Pin 59). In 2R mode, assuming the coarse ADDRESS 0x02 gain setting is full scale and the fine gain setting is zero, IFULLSCALE1 = 32 × VREF/FSADJ1 and IFULLSCALE2 = 32 × VREF/FSADJ2. Bit 7: Logic 0 (default) causes data to be accepted on the inputs With this bit set to 1, the reference currents for both I and Q as twos complement binary. Logic 1 causes data to be accepted DACs are controlled by a single resistor on Pin 60. I in as straight binary. FULLSCALE one-resistor mode for both of the I and Q DACs is half of what Bit 6: Logic 0 (default) places the AD9775 in two-port mode. it would be in 2R mode, assuming all other conditions (R , SET I and Q data enters the AD9775 via Ports 1 and 2, respectively. register settings) remain unchanged. The full-scale current of A Logic 1 places the AD9775 in one-port mode in which each DAC can still be set to 20 mA by choosing a resistor of half interleaved I and Q data is applied to Port 1. See Table 9 for the value of the RSET value used in 2R mode. detailed information on how to use the DATACLK/PLL_LOCK, Bit 1: PLL_LOCK Indicator. When the PLL is enabled, reading IQSEL, and ONEPORTCLK modes. this bit gives the status of the PLL. A Logic 1 indicates the PLL Bit 5: DATACLK Driver Strength. With the internal PLL is locked. A Logic 0 indicates an unlocked state. disabled and this bit set to Logic 0, it is recommended that DATACLK be buffered. When this bit is set to Logic 1, ADDRESS 0x01 DATACLK acts as a stronger driver capable of driving small Bit 7 and Bit 6: This is the filter interpolation rate according to capacitive loads. the following table. Bit 4: Logic 0 (default). A value of 1 inverts DATACLK at Pin 8. Table 11. Bit 2: Logic 0 (default). A value of 1 inverts ONEPORTCLK at 00 1× Pin 32. 01 2× 10 4× Bit 1: Logic 0 (default) causes IQSEL = 0 to direct input data to 11 8× the I channel, while IQSEL = 1 directs input data to the Q channel. Bit 5 and Bit 4: This is the modulation mode according to the following table. Bit 0: Logic 0 (default) defines IQ pairing as IQ, IQ… while programming a Logic 1 causes the pair ordering to be QI, QI… Table 12. 00 None 01 f /2 S 10 fS/4 11 fS/8 Rev. E | Page 19 of 56 AD9775 ADDRESS 0x03 ADDRESS 0x05, ADDRESS 0x09 Bit 7: Allows the data rate clock (divided down from the DAC Bit 7 to Bit 0: These bits represent an 8-bit binary number clock) to be output at either the DATACLK/PLL_LOCK pin (Bit 7 MSB) that defines the fine gain adjustment of the I (0x05) (Pin 8) or at the SPI_SDO pin (Pin 53). The default of 0 in this and Q (0x09) DAC, according to Equation 1. register enables the data rate clock at DATACLK/ PLL_LOCK, ADDRESS 0x06, ADDRESS 0x0A while a 1 in this register causes the data rate clock to be output Bit 3 to Bit 0: These bits represent a 4-bit binary number (Bit 3 at SPI_SDO. For more information, see the Two-Port Data MSB) that defines the coarse gain adjustment of the I (0x06) Input Mode section. and Q (0x0A) DACs, according to Equation 1. Bit 1 and Bit 0: Setting this divide ratio to a higher number ADDRESS 0x07, ADDRESS 0x0B allows the VCO in the PLL to run at a high rate (for best performance) while the DAC input and output clocks run Bit 7 to Bit 0: These bits are used in conjunction with Address substantially slower. The divider ratio is set according to the 0x08, 0x0C, Bit 1 and Bit 0. following table. ADDRESS 0x08, ADDRESS 0x0C Table 13. Bit 1 and Bit 0: The 10 bits from these two address pairs 00 ÷1 (0x07, 0x08 and 0x0B, 0x0C) represent a 10-bit binary number 01 ÷2 that defines the offset adjustment of the I and Q DACs, 10 ÷4 according to Equation 1 (0x07, 0x0B—Bit 7 MSB/0x08, 0x0C— 11 ÷8 Bit 0 LSB). ADDRESS 0x04 ADDRESS 0x08, ADDRESS 0x0C Bit 7: Logic 0 (default) disables the internal PLL. Logic 1 Bit 7: This bit determines the direction of the offset of the enables the PLL. I (0x08) and Q (0x0C) DACs. A Logic 0 applies a positive offset current to I , while a Logic 1 applies a positive offset current Bit 6: Logic 0 (default) sets the charge pump control to OUTA to I . The magnitude of the offset current is defined by the automatic. In this mode, the charge pump bias current is OUTB bits in Addresses 0x07, 0x0B, 0x08, and 0x0C, according to controlled by the divider ratio defined in Address 0x03, Bits 1 and 0. Logic 1 allows the user to manually define the charge Equation 1. pump bias current using Address 0x04, Bits 2, 1, and 0. Equation 1 shows IOUTA and IOUTB as a function of fine gain, Adjusting the charge pump bias current allows the user to coarse gain, and offset adjustment when using the 2R mode. In optimize the noise/settling performance of the PLL. 1R mode, the current IREF is created by a single FSADJ resistor Bit 2 to Bit 0: With the charge pump control set to manual, (Pin 60). This current is divided equally into each channel so that a scaling factor of one-half must be added to these these bits define the charge pump bias current according to the equations for full-scale currents for both DACs and the offset. following table. Table 14. 000 50 μA 001 100 μA 010 200 μA 011 400 μA 111 800 μA ⎡ 6× I COARSE+ 1 3× I ⎤ ⎛ ⎞⎛ ⎞ ⎛ ⎞ FINE ⎡ 1024 DATA ⎤ REF REF ⎛ ⎞ ⎛ ⎞⎛ ⎞ I = ⎜ ⎟⎜ ⎟−⎜ ⎟⎜ ⎟ × (A) ⎜ ⎟⎜ ⎟ ⎢ ⎥ ⎢ ⎥ OUTA ⎜ ⎟⎜ ⎟ ⎜ ⎟ 14 8 16 32 ⎝ 256 ⎠ ⎝ 24 ⎠⎝ 2 ⎠ ⎢⎝ ⎠⎝ ⎠ ⎝ ⎠ ⎥ ⎣ ⎦ ⎣ ⎦ 14 ⎡ ⎤ ⎡ 6× I COARSE+ 1 3× I ⎤ ⎛ 2 − DATA− 1⎞ ⎛ ⎞ FINE 1024 ⎛ ⎞ ⎛ ⎞⎛ ⎞ ⎛ ⎞ REF REF ⎜ ⎟ I = ⎜ ⎟⎜ ⎟−⎜ ⎟ ×⎢ ⎥ (A) (1) ⎜ ⎟ ⎜ ⎟ ⎢ ⎥ OUTB ⎜ ⎟ ⎜ ⎟ ⎜ ⎟ 14 ⎜ ⎟ 8 16 32 256 ⎢ 24 2 ⎥ ⎢⎝ ⎠⎝ ⎠ ⎝ ⎠⎝ ⎠⎥ ⎝ ⎠ ⎣ ⎦ ⎝ ⎠ ⎣ ⎦ OFFSET ⎛ ⎞ I = 4× I ⎜ ⎟ (A) OFFSET REF ⎝ 1024 ⎠ Rev. E | Page 20 of 56 AD9775 FUNCTIONAL DESCRIPTION The AD9775 dual interpolating DAC consists of two data SDO (PIN 53) channels that can be operated independently or coupled to form SDIO (PIN 54) a complex modulator in an image reject transmit architecture. AD9775 SPI PORT INTERFACE Each channel includes three FIR filters, making the AD9775 SPI_CLK (PIN 55) capable of 2×, 4×, or 8× interpolation. High speed input and CSB (PIN 56) output data rates can be achieved within the following limitations. Figure 32. SPI Port Interface Table 15. SERIAL INTERFACE FOR REGISTER CONTROL Interpolation Rate Input Data Rate DAC Sample Rate (MSPS) (MSPS) (MSPS) The AD9775 serial port is a flexible, synchronous serial 1× 160 160 communications port that allows easy interface to many 2× 160 320 industry-standard microcontrollers and microprocessors. 4× 100 400 The serial I/O is compatible with most synchronous transfer 8× 50 400 formats, including both the Motorola SPI and Intel SSR protocols. The interface allows read/write access to all registers Both data channels contain a digital modulator capable of that configure the AD9775. Single- or multiple-byte transfers mixing the data stream with an LO of f /2, f /4, or f /8, DAC DAC DAC are supported, as well as MSB-first or LSB-first transfer formats. where f is the output data rate of the DAC. A zero-stuffing DAC The AD9775 serial interface port can be configured as a single feature is also included and can be used to improve pass-band pin I/O (SDIO) or two unidirectional pins for I/O (SDIO/SDO). flatness for signals being attenuated by the sin(x)/x characteristic of the DAC output. The speed of the AD9775, GENERAL OPERATION OF THE SERIAL INTERFACE combined with the digital modulation capability, enables direct There are two phases to a communication cycle with the IF conversion architectures at 70 MHz and higher. AD9775. Phase 1 is the instruction cycle, which is the writing of The digital modulators on the AD9775 can be coupled to form an instruction byte into the AD9775 coincident with the first a complex modulator. By using this feature with an external eight SCLK rising edges. The instruction byte provides the analog quadrature modulator, such as the Analog Devices AD9775 serial port controller with information regarding the AD8345, an image rejection architecture can be enabled. To data transfer cycle, which is Phase 2 of the communication optimize the image rejection capability, as well as LO feed- cycle. The Phase 1 instruction byte defines whether the through in this architecture, the AD9775 offers programmable upcoming data transfer is read or write, the number of bytes in (via the SPI port) gain and offset adjust for each DAC. the data transfer, and the starting register address for the first byte of the data transfer. The first eight SCLK rising edges of Also included on the AD9775 are a phase-locked loop (PLL) each communication cycle are used to write the instruction byte clock multiplier and a 1.20 V band gap voltage reference. With into the AD9775. the PLL enabled, a clock applied to the CLK+/CLK− inputs is frequency multiplied internally and generates all necessary A Logic 1 on the SPI_CSB pin, followed by a logic low, resets internal synchronization clocks. Each 14-bit DAC provides two the SPI port timing to the initial state of the instruction cycle. complementary current outputs whose full-scale currents can This is true regardless of the present state of the internal be determined either from a single external resistor or registers or the other signal levels present at the inputs to the independently from two separate resistors (see the 1R/2R Mode SPI port. If the SPI port is in the middle of an instruction cycle section). The AD9775 features a low jitter, differential clock or a data transfer cycle, none of the present data is written. input that provides excellent noise rejection while accepting a The remaining SCLK edges are for Phase 2 of the sine or square wave input. Separate voltage supply inputs are communication cycle. Phase 2 is the actual data transfer provided for each functional block to ensure optimum noise between the AD9775 and the system controller. Phase 2 of the and distortion performance. communication cycle is a transfer of one to four data bytes as Sleep and power-down modes can be used to turn off the DAC determined by the instruction byte. Typically, using one output current (sleep) or the entire digital and analog sections multibyte transfer is the preferred method. However, single byte (power-down) of the chip. An SPI-compliant serial port is used data transfers are useful to reduce CPU overhead when register to program the many features of the AD9775. Note that in access requires one byte only. Registers change immediately power-down mode, the SPI port is the only section of the chip upon writing to the last bit of each transfer byte. still active. Rev. E | Page 21 of 56 02858-032 AD9775 SPI_SDO (Pin 53)—Serial Data Out INSTRUCTION BYTE Data is read from this pin for protocols that use separate lines The instruction byte contains the information shown next for transmitting and receiving data. In the case where the Table 16. AD9775 operates in a single bidirectional I/O mode, this pin N1 N0 Description does not output data and is set to a high impedance state. 0 0 Transfer 1 Byte MSB/LSB TRANSFERS 0 1 Transfer 2 Bytes The AD9775 serial port can support both most significant bit 1 0 Transfer 3 Bytes (MSB) first or least significant bit (LSB) first data formats. This 1 1 Transfer 4 Bytes functionality is controlled by the LSB-first bit in Register 0. The R/W default is MSB first. Bit 7 of the instruction byte determines whether a read or a When this bit is set active high, the AD9775 serial port is in write data transfer occurs after the instruction byte write. LSB-first format. In LSB-first mode, the instruction byte and Logic 1 indicates read operation. Logic 0 indicates a write data bytes must be written from LSB to MSB. In LSB-first mode, operation. the serial port internal byte address generator increments for each byte of the multibyte communication cycle. N1, N0 Bit 6 and Bit 5 of the instruction byte determine the number of When this bit is set default low, the AD9775 serial port is in bytes to be transferred during the data transfer cycle. The bit MSB-first format. In MSB-first mode, the instruction byte and decodes are shown next. data bytes must be written from MSB to LSB. In MSB-first mode, the serial port internal byte address generator Table 17. decrements for each byte of the multibyte communication cycle. MSB LSB I7 I6 I5 I4 I3 I2 I1 I0 When incrementing from 0x1F, the address generator changes to 0x00. When decrementing from 0x00, the address generator R/W N1 N0 A4 A3 A2 A1 A0 changes to 0x1F. A4, A3, A2, A1, A0 NOTES ON SERIAL PORT OPERATION Bit 4 to Bit 0 of the instruction byte determine which register is The AD9775 serial port configuration bits reside in Bit 6 and accessed during the data transfer portion of the communications Bit 7 of Register Address 0x00. It is important to note that the cycle. For multibyte transfers, this address is the starting byte configuration changes immediately upon writing to the last bit address. The remaining register addresses are generated by of the register. For multibyte transfers, writing to this register the AD9775. may occur during the middle of the communication cycle. Care SERIAL INTERFACE PORT PIN DESCRIPTIONS must be taken to compensate for this new configuration for the remaining bytes of the current communication cycle. SPI_CLK (Pin 55)—Serial Clock The serial clock pin is used to synchronize data to and from the The same considerations apply to setting the reset bit in AD9775 and to run the internal state machines. SPI_CLK Register Address 0x00. All other registers are set to their maximum frequency is 15 MHz. All data input to the AD9775 default values, but the software reset does not affect the bits in is registered on the rising edge of SPI_CLK. All data is driven Register Address 0x00. out of the AD9775 on the falling edge of SPI_CLK. It is recommended to use only single-byte transfers when SPI_CSB (Pin 56)—Chip Select changing serial port configurations or initiating a software reset. Active low input starts and gates a communication cycle. It A write to Bit 1, Bit 2, and Bit 3 of Address 0x00 with the same allows more than one device to be used on the same serial logic levels as for Bit 7, Bit 6, and Bit 5 (bit pattern is XY1001YX communications lines. The SDO and SDIO pins go to a high binary) allows the user to reprogram a lost serial port impedance state when this input is high. Chip select should stay configuration and to reset the registers to their default values. A low during the entire communication cycle. second write to Address 0x00 with reset bit low and serial port SPI_SDIO (Pin 54)—Serial Data I/O configuration as specified above (XY) reprograms the OSC IN Data is always written into the AD9775 on this pin. However, multiplier setting. A changed f frequency is stable after a SYSCLK this pin can be used as a bidirectional data line. The maximum of 200 fMCLK cycles (equals wake-up time). configuration of this pin is controlled by Bit 7 of Register Address 0x00. The default is Logic 0, which configures the SDIO pin as unidirectional. Rev. E | Page 22 of 56 AD9775 INSTRUCTION CYCLE DATA TRANSFER CYCLE CS SCLK SDIO R/W I6 I5 I4 I3 I2 I1 I0 D7 D6 D2 D1 D0 (N) (N) N N 0 0 0 D7 D6 D2 D1 D0 SDO N N 0 0 0 Figure 33. Serial Register Interface Timing MSB First INSTRUCTION CYCLE DATA TRANSFER CYCLE CS SCLK SDIO I0 I1 I2 I3 I4 I5 I6 R/W D0 D1 D2 D6 D7 (N) (N) 0 0 0 N N SDO D0 D1 D2 D6 D7 0 0 0 N N Figure 34. Serial Register Interface Timing LSB First t t DS SCLK CS t t PWH PWL SCLK t t DS DH SDIO INSTRUCTION BIT 7 INSTRUCTION BIT 6 T Figure 35. Timing Diagram for Register Write to AD9775 CS SCLK t DV SDIO DATA BIT N–1 DATA BIT N SDO Figure 36. Timing Diagram for Register Read from AD9775 Rev. E | Page 23 of 56 02858-036 02858-035 02858-033 02858-034 AD9775 25 DAC OPERATION The dual, 14-bit DAC output of the AD9775, along with the 20 reference circuitry, gain, and offset registers, is shown in Figure 37. Note that an external reference can be used by simply overdriving 2R MODE 15 the internal reference with the external reference. Referring to the transfer functions in Equation 1, a reference current is set by the internal 1.2 V reference, the external R resistor, and the values SET 10 in the coarse gain register. The fine gain DAC subtracts a small 1R MODE amount from this and the result is input to IDAC and QDAC, 5 where it is scaled by an amount equal to 1024/24. Figure 38 and Figure 39 show the scaling effect of the coarse and fine adjust 0 DACs. IDAC and QDAC are PMOS current source arrays, 01 5 01520 segmented in a 5-4-5 configuration. The 5 MSBs control an array COARSE GAIN REGISTER CODE (ASSUMING RSET1, RSET2 = 1.9kΩ) of 31 current sources. The next four bits consist of 15 current Figure 38. Coarse Gain Effect on IFULLSCALE sources whose values are all equal to 1/16 of an MSB current 0 source. The 5 LSBs are binary weighted fractions of the middle bits’ current sources. All current sources are switched to either –0.5 IOUTA or IOUTB, depending on the input code. 1R MODE The fine adjustment of the gain of each channel allows for –1.0 improved balance of QAM modulated signals, resulting in improved modulation accuracy and image rejection. 2R MODE –1.5 In the section Interfacing the AD9775 with the AD8345 Quadrature Modulator, the performance data shows to what –2.0 degree image rejection can be improved when the AD9775 is used with an AD8345 quadrature modulator from Analog –2.5 Devices, Inc. AVDD –3.0 0 200 400 600 800 1000 84μA FINE GAIN REGISTER CODE (ASSUMING RSET1, RSET2 = 1.9kΩ) REFIO Figure 39. Fine Gain Effect on IFULLSCALE 7kΩ 0.7V Figure 37. Equivalent Internal Reference Circuit OFFSET OFFSET CONTROL FINE DAC REGISTERS GAIN GAIN DAC CONTROL REGISTERS FINE I GAIN IDAC OUTA1 DAC 1.2VREF I OUTB1 REFIO COARSE COARSE QDAC I OUTA2 GAIN GAIN 0.1μF DAC DAC I OUTB2 FSADJ1 OFFSET FSADJ2 OFFSET RSET1 CONTROL DAC GAIN REGISTERS RSET2 CONTROL REGISTERS Figure 40. DAC Outputs, Reference Current Scaling, and Gain/Offset Adjust Rev. E | Page 24 of 56 02858-038 FINE REFERENCE CURRENT (mA) COARSE REFERENCE CURRENT (mA) 02858-037 02858-039 02858-040 AD9775 0 The offset control defines a small current that can be added to I or I (not both) on the IDAC and QDAC. The selection OUTA OUTB –10 of which I this offset current is directed toward is programmable OUT OFFSET REGISTER 1 ADJUSTED –20 via Register 0x08, Bit 7 (IDAC) and Register 0x0C, Bit 7 (QDAC). Figure 41 shows the scale of the offset current that can be added –30 to one of the complementary outputs on the IDAC and QDAC. –40 Offset control can be used for suppression of LO leakage resulting from modulation of dc signal components. If the AD9775 is dc- –50 coupled to an external modulator, this feature can be used to –60 cancel the output offset on the AD9775 as well as the input offset OFFSET REGISTER 2 ADJUSTED, WITH OFFSET on the modulator. Figure 42 shows a typical example of the effect –70 REGISTER 1 SET that the offset control has on LO suppression. TO OPTIMIZED VALUE –80 –1024 –768 –512 –256 0 256 512 768 1024 In Figure 42, the negative scale represents an offset added to IOUTB, DAC1, DAC2 (OFFSET REGISTER CODES) while the positive scale represents an offset added to IOUTA of the Figure 42. Offset Adjust Control, Effect on LO Suppression respective DAC. Offset Register 1 corresponds to IDAC, while Offset Register 2 corresponds to QDAC. Figure 42 represents the CLOCK INPUT CONFIGURATIONS AD9775 synthesizing a complex signal that is then dc-coupled to The clock inputs to the AD9775 can be driven differentially an AD8345 quadrature modulator with an LO of 800 MHz. The or single-ended. The internal clock circuitry has supply and dc coupling allows the input offset of the AD8345 to be calibrated ground (CLKVDD, CLKGND) separate from the other supplies out as well. The LO suppression at the AD8345 output was opti- on the chip to minimize jitter from internal noise sources. mized first by adjusting Offset Register 1 in the AD9775. When Figure 43 shows the AD9775 driven from a single-ended an optimal point was found (roughly Code 54), this code was held in Offset Register 1, and Offset Register 2 was adjusted. The clock source. The CLK+/CLK− pins form a differential input resulting LO suppression is 70 dBFS. These are typical numbers; (CLKIN) so that the statically terminated input must be dc- the specific code for optimization varies from part to part. biased to the midswing voltage level of the clock driven input. 1R/2R MODE AD9775 In 2R mode, the reference current for each channel is set R SERIES CLK+ independently by the FSADJ resistor on that channel. The AD9775 can be programmed to derive its reference current CLKVDD from a single resistor on Pin 60 by placing the part into 1R CLK– mode. The transfer functions in Equation 1 are valid for 2R V THRESHOLD 0.1μF mode. In 1R mode, the current developed in the single FSADJ CLKGND resistor is split equally between the two channels. The result is that in 1R mode, a scale factor of 1/2 must be applied to the Figure 43. Single-Ended Clock Driving Clock Inputs formulas in Equation 1. The full-scale DAC current in 1R mode can still be set to as high as 20 mA by using the internal 1.2 V A configuration for differentially driving the clock inputs is reference and a 950 Ω resistor instead of the 1.9 kΩ resistor given in Figure 44. DC-blocking capacitors can be used to typically used in the 2R mode. couple a clock driver output whose voltage swings exceed 5 CLKVDD or CLKGND. If the driver voltage swings are within the supply range of the AD9775, the dc-blocking capacitors and bias resistors are not necessary. 4 AD9775 3 1kΩ 0.1μF CLK+ 2R MODE 1kΩ 2 ECL/PECL 0.1μF CLKVDD 1kΩ 1R MODE 0.1μF CLK– 1 1kΩ CLKGND 0 0 0 200 400 600 800 1000 COARSE GAIN REGISTER CODE Figure 44. Differential Clock Driving Clock Inputs (ASSUMING RSET1, RSET2 = 1.9kΩ) Figure 41. DAC Output Offset Current Rev. E | Page 25 of 56 OFFSET CURRENT (mA) 02858-041 LO SUPPRESSION (dBFS) 02858-043 02858-044 02858-042 AD9775 A transformer, such as the T1-1T from Mini-Circuits®, can also CLK+ CLK– be used to convert a single-ended clock to differential. This PLLVDD PLL_LOCK method is used on the AD9775 evaluation board so that an external 1 = LOCK AD9775 0 = NO LOCK sine wave with no dc offset can be used as a differential clock. PECL/ECL drivers require varying termination networks, INTERPOLATION PHASE CHARGE the details of which are left out of Figure 43 and Figure 44 but FILTERS, DETECTOR PUMP LPF MODULATORS, can be found in application notes such as AND8020/D from AND DACS ON Semiconductor®. These networks depend on the assumed 2 48 transmission line impedance and power supply voltage of the 1 CLOCK clock driver. PRESCALER VCO INPUT DISTRIBUTION DATA CIRCUITRY Optimum performance of the AD9775 is achieved when the LATCHES PLL DIVIDER driver is placed very close to the AD9775 clock inputs, thereby INTERNAL SPI (PRESCALER) CONTROL CONTROL negating any transmission line effects such as reflections due to REGISTERS INTERPOLATION PLL RATE mismatch. CONTROL MODULATION CONTROL RATE (PLL ON) SPI PORT CONTROL The quality of the clock and data input signals is important in achieving optimum performance. The external clock driver Figure 45. PLL and Clock Circuitry with PLL Enabled circuitry should provide the AD9775 with a low jitter clock input that meets the minimum/maximum logic levels while CLK+ CLK– providing fast edges. Although fast clock edges help minimize PLL_LOCK 1 = LOCK any jitter that manifests itself as phase noise on a reconstructed AD9775 0 = NO LOCK waveform, the high gain bandwidth product of the AD9775 clock input comparator can tolerate differential sine wave INTERPOLATION PHASE CHARGE inputs as low as 0.5 V p-p with minimal degradation of the FILTERS, DETECTOR PUMP MODULATORS, output noise floor. AND DACS PROGRAMMABLE PLL 2 48 1 CLKIN can function either as an input data rate clock (PLL CLOCK PRESCALER VCO INPUT DISTRIBUTION enabled) or as a DAC data rate clock (PLL disabled) according DATA CIRCUITRY LATCHES to the state of Address 0x02, Bit 7 in the SPI port register. The PLL DIVIDER INTERNAL SPI (PRESCALER) internal operation of the AD9775 clock circuitry in these two CONTROL CONTROL REGISTERS INTERPOLATION modes is illustrated in Figure 45 and Figure 46. PLL RATE MODULATION CONTROL CONTROL RATE (PLL ON) The PLL clock multiplier and distribution circuitry produce the SPI PORT CONTROL necessary internal synchronized 1×, 2×, 4×, and 8× clocks for Figure 46. PLL and Clock Circuitry with PLL Disabled the rising edge triggered latches, interpolation filters, modulators, and DACs. This circuitry consists of a phase Table 18. PLL Optimization detector, charge pump, voltage controlled oscillator (VCO), Interpolation Divider Minimum Maximum prescaler, clock distribution, and SPI port control. Rate Setting f f DATA DATA The charge pump, VCO, differential clock input buffer, phase 1 1 32 160 1 2 16 160 detector, prescaler, and clock distribution are all powered from 1 4 8 112 CLKVDD. PLL lock status is indicated by the logic signal at the 1 8 4 56 DATACLK_PLL_LOCK pin, as well as by the status of Bit 1, 2 1 24 160 Register 0x00. To ensure optimum phase noise performance 2 2 12 112 from the PLL clock multiplier and distribution, CLKVDD 2 4 6 56 should originate from a clean analog supply. Table 18 defines 2 8 3 28 the minimum input data rates vs. the interpolation and PLL 4 1 24 100 divider setting. If the input data rate drops below the defined 4 2 12 56 minimum under these conditions, VCO noise may increase 4 4 6 28 significantly. The VCO speed is a function of the input data 4 8 3 14 rate, the interpolation rate, and the VCO prescaler, according to 8 1 24 50 the following function: 8 2 12 28 VCO Speed (MHz) = 8 4 6 14 Input Data Rate (MHz) × Interpolation Rate × Prescaler 8 8 3 7 Rev. E | Page 26 of 56 02858-046 02858-045 AD9775 In addition, if the zero-stuffing option is enabled, the VCO It is important to note that the resistor/capacitor needed for the doubles its speed again. Phase noise may be slightly higher with PLL loop filter is internal on the AD9775. This suffices unless the the PLL enabled. Figure 47 illustrates typical phase noise perform- input data rate is below 10 MHz, in which case an external series RC is required between the LPF pin and CLKVDD pins. ance of the AD9775 with 2× interpolation and various input data rates. The signal synthesized for the phase noise measurement POWER DISSIPATION was a single carrier at a frequency of fDATA/4. The repetitive The AD9775 has three voltage supplies: DVDD, AVDD, and nature of this signal eliminates quantization noise and distortion CLKVDD. Figure 49 through Figure 51 show the current spurs as a factor in the measurement. Although the curves blend required from each of these supplies when each is set to the 3.3 V together in Figure 47, the different conditions are given for clarity nominal specified for the AD9775. Power dissipation (PD) can in Table 19. Figure 47 also contains a table detailing the maximum easily be extracted by multiplying the given curves by 3.3. As and minimum f rates for each combination of interpolation DATA Figure 49 shows, IDVDD is very dependent on the input data rate, rate and PLL divider setting. These rates are guaranteed over the interpolation rate, and the activation of the internal digital the entire supply and operating temperature range. Figure 48 modulator. I , however, is relatively insensitive to the DVDD shows typical performance of the PLL lock signal (Pin 8 or modulation rate by itself. In Figure 50, I shows the same type AVDD Pin 53) when the PLL is in the process of locking. of sensitivity to the data, the interpolation rate, and the modu- Table 19. Required PLL Prescaler Ratio vs. f DATA lator function but to a much lesser degree (<10%). In Figure 51, fDATA PLL Prescaler Ratio ICLKVDD varies over a wide range yet is responsible for only a small 125 MSPS Disabled percentage of the overall AD9775 supply current requirements. 125 MSPS Enabled Div 1 400 100 MSPS Enabled Div 2 8×, (MOD. ON) 2×, (MOD. ON) 350 75 MSPS Enabled Div 2 4×, (MOD. ON) 50 MSPS Enabled Div 4 300 0 8× 4× 250 –10 2× –20 200 –30 150 –40 100 –50 1× –60 50 –70 0 –80 0 50 100 150 200 –90 f (MHz) DATA –100 Figure 49. I vs. f vs. Interpolation Rate, PLL Disabled DVDD DATA –110 012 3 45 76.0 FREQUENCY OFFSET (MHz) 4×, (MOD. ON) 8×, (MOD. ON) 75.5 Figure 47. Phase Noise Performance 2×, (MOD. ON) 75.0 74.5 4× 8× 74.0 73.5 2× 73.0 1× 72.5 72.0 0 50 100 150 200 f (MHz) DATA Figure 50. IAVDD vs. fDATA vs. Interpolation Rate, PLL Disabled Figure 48. PLL_LOCK Output Signal (Pin 8) in the Process of Locking (Typical Lock Time) Rev. E | Page 27 of 56 PHASE NOISE (dBFS) 02858-047 02858-048 I (mA) I (mA) AVDD DVDD 02858-050 02858-049 AD9775 35 PLL On (Register 4, Bit 7 = 1) 8× Register 3, Bit 7 = 0, Register 1, Bit 0 = 0; PLL lock indicator out 30 of Pin 8. 4× 2× 25 Register 3, Bit 7 = 1, Register 1, Bit 0 = 0; PLL lock indicator out of Pin 53. 20 Register 3, Bit 7 = 0, Register 1, Bit 0 = 1; DATACLK out of Pin 8. Register 3, Bit 7 = 1, Register 1, Bit 0 = 1; DATACLK out of Pin 53. 15 1× In one-port mode, P2B14 and P2B15 from Input Data Port 2 10 are redefined as IQSEL and ONEPORTCLK, respectively. The input data in one-port mode is steered to one of the two inter- 5 nal data channels based on the logic level of IQSEL. A clock 0 signal, ONEPORTCLK, is generated by the AD9775 in this 0 50 100 150 200 mode for the purpose of data synchronization. ONEPORTCLK f (MHz) DATA runs at the input interleaved data rate, which is 2× the data rate Figure 51 I vs. f vs. Interpolation Rate, PLL Disabled at the internal input to either channel. CLKVDD DATA Figure 101 through Figure 104 illustrate the test configurations SLEEP/POWER-DOWN MODES showing the various clocks that are required and generated by (Control Register 0x00, Bit 3 and Bit 4) the AD9775 with the PLL enabled/disabled and in the one- The AD9775 provides two methods for programmable port/two-port modes. Jumper positions needed to operate the reduction in power savings. The sleep mode, when activated, AD9775 evaluation board in these modes are given as well. turns off the DAC output currents but the rest of the chip PLL ENABLED, TWO-PORT MODE remains functioning. When coming out of sleep mode, the AD9775 immediately returns to full operation. Power-down (Control Register 0x02, Bit 6 to Bit 0 and Control Register 0x04, Bit 7 to Bit 1) mode, on the other hand, turns off all analog and digital circuitry in the AD9775 except for the SPI port. When With the phase-locked loop (PLL) enabled and the AD9775 in returning from power-down mode, enough clock cycles must two-port mode, the speed of CLKIN is inherently that of the be allowed to flush the digital filters of random data acquired input data rate. In two-port mode, Pin 8 (DATACLK/PLL_ during the power-down cycle. LOCK) can be programmed (Control Register 0x01, Bit 0) to function as either a lock indicator for the internal PLL or as a TWO-PORT DATA INPUT MODE clock running at the input data rate. When Pin 8 is used as a The digital data input ports can be configured as two independ- clock output (DATACLK), its frequency is equal to that of ent ports or as a single (one-port mode) port. In two-port mode, CLKIN. Data at the input ports is latched into the AD9775 on data at the two input ports is latched into the AD9775 on every the rising edge of the CLKIN. Figure 52 shows the delay, t , OD rising edge of the data rate clock (DATACLK). Also, in two-port inherent between the rising edge of CLKIN and the rising edge mode, the AD9775 can be programmed to generate an externally of DATACLK, as well as the setup and hold requirements for available DATACLK for the purpose of data synchronization. the data at Ports 1 and 2. The setup and hold times given in This data rate clock can be programmed to be available at either Figure 52 are the input data transitions with respect to CLKIN. Pin 8 (DATACLK/PLL_LOCK) or Pin 53 (SPI_SDO). Because Note that in two-port mode (PLL enabled or disabled), the data Pin 8 can also function as a PLL lock indicator when the PLL is rate at the interpolation filter inputs is the same as the input enabled, there are several options for configuring Pin 8 and data rate at Port 1 and Port 2. Pin 53. The following sections describe the options. The DAC output sample rate in two-port mode is equal to the PLL Off (Register 4, Bit 7 = 0) clock input rate multiplied by the interpolation rate. If zero stuffing is used, another factor of 2 must be included to Register 3, Bit 7 = 0; DATACLK out of Pin 8. calculate the DAC sample rate. Register 3, Bit 7 = 1; DATACLK out of Pin 53. Rev. E | Page 28 of 56 I (mA) CLKVDD 02858-051 AD9775 DATACLK INVERSION PLL ENABLED, ONE-PORT MODE (Control Register 0x02, Bit 4) (Control Register 0x02, Bit 6 to Bit 1 and Control Register 0x04, Bit 7 to Bit 1) By programming this bit, the DATACLK signal shown in Figure 52 can be inverted. With inversion enabled, t refers to In one-port mode, the I and Q channels receive their data from an OD the time between the rising edge of CLKIN and the falling edge interleaved stream at digital input Port 1. The function of Pin 32 is of DATACLK. No other effect on timing occurs. defined as an output (ONEPORTCLK) that generates a clock at the interleaved data rate, which is 2× the internal input data rate of the I t OD and Q channels. The frequency of CLKIN is equal to the internal input data rate of the I and Q channels. The selection of the data for the I or the Q channel is determined by the state of the logic level at CLKIN Pin 31 (IQSEL when the AD9775 is in one-port mode) on the rising edge of ONEPORTCLK. Under these conditions, IQSEL = 0 latches the data into the I channel on the clock rising edge, while IQSEL = 1 latches the data into the Q channel. It is possible to DATACLK invert the I and Q selection by setting Control Register 0x02, Bit 1 to the invert state (Logic 1). Figure 54 illustrates the timing requirements for the data inputs as well as the IQSEL input. Note that the 1× interpolation rate is not available in the one-port mode. DATA AT PORTS 1 AND 2 The DAC output sample rate in one-port mode is equal to CLKIN multiplied by the interpolation rate. If zero stuffing is t = 1.5ns (MIN) TO 2.5ns (MAX) OD t = 0.0ns (MIN) S t t used, another factor of 2 must be included to calculate the DAC S H t = 2.5ns (MIN) H sample rate. Figure 52. Timing Requirements in Two-Port Input Mode, with PLL Enabled ONEPORTCLK INVERSION DATACLK DRIVER STRENGTH (Control Register 0x02, Bit 2) (Control Register 0x02, Bit 5) By programming this bit, the ONEPORTCLK signal shown in The DATACLK output driver strength is capable of driving Figure 54 can be inverted. With inversion enabled, t refers to OD >10 mA into a 330 Ω load while providing a rise time of 3 ns. the delay between the rising edge of the external clock and the Figure 53 shows DATACLK driving a 330 Ω resistive load at a falling edge of ONEPORTCLK. The setup and hold times, t S frequency of 50 MHz. By enabling the drive strength option and tH, are with respect to the falling edge of ONEPORTCLK. (Control Register 0x02, Bit 5), the amplitude of DATACLK There is no other effect on timing. under these conditions increases by approximately 200 mV. t OD 3.0 t = 4.0ns (MIN) OD TO 5.5ns (MAX) CLKIN 2.5 t = 3.0ns (MIN) S t = –0.5ns (MIN) H t = 3.5ns (MIN) IQS 2.0 t = –1.5ns (MIN) IQH 1.5 ONEPORTCLK 1.0 0.5 I AND Q INTERLEAVED 0 INPUT DATA AT PORT 1 DELTA APPROX. 2.8ns –0.5 0 102030 40 50 t t S H TIME (ns) Figure 53. DATACLK Driver Capability into 330 Ω at 50 MHz IQSEL t t IQS IQH Figure 54. Timing Requirements in One-Port Input Mode with the PLL Enabled Rev. E | Page 29 of 56 AMPLITUDE (V) 02858-053 02858-052 02858-054 AD9775 t OD ONEPORTCLK DRIVER STRENGTH The drive capability of ONEPORTCLK is identical to that of DATACLK in the two-port mode. Refer to Figure 53 for CLKIN performance under load conditions. IQ PAIRING DATACLK (Control Register 0x02, Bit 0) In one-port mode, the interleaved data is latched into the AD9775 internal I and Q channels in pairs. The order of how the pairs are latched internally is defined by this control register. DATA AT PORTS 1 AND 2 The following is an example of the effect that this has on incoming interleaved data. t = 6.5ns (MIN) TO 8.0ns (MAX) OD t t S H t = 5.0ns (MIN) S Given the following interleaved data stream, where the data t = –3.2ns (MIN) H indicates the value with respect to full scale: Figure 55. Timing Requirements in Two-Port Input Mode with PLL Disabled Table 20. t OD I Q I Q I Q I Q I Q 0.5 0.5 1 1 0.5 0.5 0 0 0.5 0.5 CLKIN With the control register set to 0 (I first), the data appears at the internal channel inputs in the following order in time: Table 21. I Channel 0.5 1 0.5 0 0.5 ONEPORTCLK Q Channel 0.5 1 0.5 0 0.5 With the control register set to 1 (Q first), the data appears at the internal channel inputs in the following order in time: Table 22. I AND Q INTERLEAVED INPUT DATA AT PORT 1 I Channel 0.5 1 0.5 0 0.5 x Q Channel y 0.5 1 0.5 0 0.5 t t The values x and y represent the next I value and the previous S H Q value in the series. IQSEL PLL DISABLED, TWO-PORT MODE t = 4.0ns (MIN) OD TO 5.5ns (MAX) t = 3.0ns (MIN) With the PLL disabled, a clock at the DAC output rate must be S t = –1.0ns (MIN) t t H IQS IQH t = 3.5ns (MIN) applied to CLKIN. Internal clock dividers in the AD9775 IQS t = –1.5ns (MIN) IQH synthesize the DATACLK signal at Pin 8, which runs at the Figure 56. Timing Requirements in One-Port Input Mode with PLL Disabled input data rate and can be used to synchronize the input data. Data is latched into input Port 1 and Port 2 of the AD9775 on PLL DISABLED, ONE-PORT MODE the rising edge of DATACLK. DATACLK speed is defined as the In one-port mode, data is received into the AD9775 as an speed of CLKIN divided by the interpolation rate. With zero interleaved stream on Port 1. A clock signal (ONEPORTCLK) stuffing enabled, this division increases by a factor of 2. Figure 55 running at the interleaved data rate, which is 2× the input data illustrates the delay between the rising edge of CLKIN and the rate of the internal I and Q channels, is available for data rising edge of DATACLK, as well as tS and tH in this mode. synchronization at Pin 32. The programmable modes DATACLK inversion and DATACLK With PLL disabled, a clock at the DAC output rate must be driver strength described in the previous section (PLL Enabled, applied to CLKIN. Internal dividers synthesize the Two-Port Mode) have identical functionality with the PLL ONEPORTCLK signal at Pin 32. The selection of the data for disabled. the I or Q channel is determined by the state of the logic level The data rate clock created by dividing down the DAC clock in applied to Pin 31 (IQSEL when the AD9775 is in one-port this mode can be programmed (via Register 0x03, Bit 7) to be mode) on the rising edge of ONEPORTCLK. Under these output from the SPI_SDO pin rather than the DATACLK/ conditions, IQSEL = 0 latches the data into the I channel on the PLL_LOCK pin. In some applications, this may improve clock rising edge, while IQSEL = 1 latches the data into the Q complex image rejection. When SPI_SDO is used as data rate channel. clock out, tOD increases by 1.6 ns. Rev. E | Page 30 of 56 02858-056 02858-055 AD9775 It is possible to invert the I and Q selection by setting control frequency images. This is shown graphically in the frequency Register 0x02, Bit 1 to the invert state (Logic 1). Figure 56 domain in Figure 57. illustrates the timing requirements for the data inputs as well as –jωt e /2j the IQSEL input. Note that the 1× interpolation rate is not SINE available in the one-port mode. DC –jωt One-port mode is very useful when interfacing with devices e /2j such as the Analog Devices AD6622 or AD6623 transmit signal processors, in which two digital data channels have been –jωt –jωt e /2 e /2 interleaved (multiplexed). COSINE The programmable modes’ ONEPORTCLK inversion, DC ONEPORTCLK driver strength, and IQ pairing described in Figure 57. Real and Imaginary Components of the PLL Enabled, One-Port Mode section have identical Sinusoidal and Cosinusoidal Waveforms functionality with the PLL disabled. Amplitude modulating a baseband signal with a sine or a cosine DIGITAL FILTER MODES convolves the baseband signal with the modulating carrier in The I and Q datapaths of the AD9775 have their own the frequency domain. Amplitude scaling of the modulated independent half-band FIR filters. Each datapath consists of signal reduces the positive and negative frequency images by a three FIR filters, providing up to 8× interpolation for each factor of 2. channel. The rate of interpolation is determined by the state of This scaling is very important in the discussion of the various Control Register 0x01, Bit 7 and Bit 6. Figure 2 to Figure 4 show modulation modes. The phase relationship of the modulated the response of the digital filters when the AD9775 is set to 2×, signals is dependent on whether the modulating carrier is 4×, and 8× modes. The frequency axes of these graphs are sinusoidal or cosinusoidal, again with respect to the reference normalized to the input data rate of the DAC. As the graphs point of the viewer. Examples of sine and cosine modulation are show, the digital filters can provide greater than 75 dB of given in Figure 58. out-of-band rejection. –jωt Ae /2j An online tool is available for quick and easy analysis of the SINUSOIDAL MODULATION AD9775 interpolation filters in the various modes. The link can be accessed at www.analog.com/ad9777image. DC AMPLITUDE MODULATION –jωt /2j Ae Given two sine waves at the same frequency, but with a –jωt –jωt Ae /2 Ae /2 90 degree phase difference, a point of view in time can be taken COSINUSOIDAL MODULATION such that the waveform that leads in phase is cosinusoidal and the waveform that lags is sinusoidal. Analysis of complex DC variables states that the cosine waveform can be defined as Figure 58. Baseband Signal, Amplitude Modulated having real positive and negative frequency components, while with Sine and Cosine Carriers the sine waveform consists of imaginary positive and negative Rev. E | Page 31 of 56 02858-057 02858-058 AD9775 domain spectrum to the DAC sin(x)/x roll-off, an estimate can MODULATION, NO INTERPOLATION be made for the characteristics required for the DAC recon- With Control Register 0x01, Bit 7 and Bit 6 set to 00, the struction filter. interpolation function on the AD9775 is disabled. Figure 59 through Figure 62 show the DAC output spectral characteristics Note also, per the previous discussion on amplitude of the AD9775 in the various modulation modes, all with the modulation, that the spectral components (where modulation is interpolation filters disabled. The modulation frequency is set to fS/4 or fS/8) are scaled by a factor of 2. In the situation determined by the state of Control Register 0x01, Bit 5 and Bit 4. where the modulation is fS/2, the modulated spectral components add constructively, and there is no The tall rectangles represent the digital domain spectrum of a scaling effect. baseband signal of narrow bandwidth. By comparing the digital The Effects of the Digital Modulation on the DAC Output Spectrum, Interpolation Disabled 0 0 –20 –20 –40 –40 –60 –60 –80 –80 –100 –100 0 0.2 0.4 0.6 0.8 1.0 0 0.2 0.4 0.6 0.8 1.0 f (×f ) f (×f ) OUT DATA OUT DATA Figure 59. No Interpolation, Modulation Disabled Figure 61. No Interpolation, Modulation = f /4 DAC 0 0 –20 –20 –40 –40 –60 –60 –80 –80 –100 –100 0 0.2 0.4 0.6 0.8 1.0 0 0.2 0.4 0.6 0.8 1.0 f (×f ) f (×f ) OUT DATA OUT DATA Figure 60. No Interpolation, Modulation = f /2 Figure 62. No Interpolation, Modulation = f /8 DAC DAC Rev. E | Page 32 of 56 AMPLITUDE (dBFS) AMPLITUDE (dBFS) 02858-060 02858-059 AMPLITUDE (dBFS) AMPLITUDE (dBFS) 02858-062 02858-061 AD9775 MODULATION, INTERPOLATION = 2× With Control Register 0x01, Bit 7 and Bit 6 set to 01, the Another significant point is that the interpolation filtering is interpolation rate of the AD9775 is 2×. Modulation is achieved done previous to the digital modulator. For this reason, as by multiplying successive samples at the interpolation filter Figure 63 through Figure 66 show, the pass band of the output by the sequence (+1, −1). Figure 63 through Figure 66 interpolation filters can be frequency shifted, giving the equivalent represent the spectral response of the AD9775 DAC output with of a high-pass digital filter. 2× interpolation in the various modulation modes to a narrow- Note that when using the f /4 modulation mode, there is no S band baseband signal (the tall rectangles in the graphic). The true stop band as the band edges coincide with each other. In advantage of interpolation becomes clear in Figure 63 through the fS/8 modulation mode, amplitude scaling occurs over only a Figure 66, where the images that would normally appear in the portion of the digital filter pass band due to constructive spectrum around the input data rate frequency are suppressed addition over just that section of the band. by >70 dB. The Effects of the Digital Modulation on the DAC Output Spectrum, Interpolation = 2× 0 0 –20 –20 –40 –40 –60 –60 –80 –80 –100 –100 0 0.5 1.0 1.5 2.0 0 0.5 1.0 1.5 2.0 f (×f ) f (×f ) OUT DATA OUT DATA Figure 63. 2× Interpolation, Modulation = Disabled Figure 65. 2× Interpolation, Modulation = f /4 DAC 0 0 –20 –20 –40 –40 –60 –60 –80 –80 –100 –100 0 0.5 1.0 1.5 2.0 0 0.5 1.0 1.5 2.0 f (×f ) f (×f ) OUT DATA OUT DATA Figure 64. 2× Interpolation, Modulation = f /2 Figure 66. 2× Interpolation, Modulation = f /8 DAC DAC Rev. E | Page 33 of 56 AMPLITUDE (dBFS) AMPLITUDE (dBFS) 02858-064 02858-063 AMPLITUDE (dBFS) AMPLITUDE (dBFS) 02858-066 02858-065 AD9775 MODULATION, INTERPOLATION = 4× With Control Register 0x01, Bit 7 and Bit 6 set to 10, the Figure 67 through Figure 70 represent the spectral response of interpolation rate of the AD9775 is 4×. Modulation is achieved the AD9775 DAC output with 4× interpolation in the various by multiplying successive samples at the interpolation filter modulation modes to a narrow-band baseband signal. output by the sequence (0, +1, 0, −1). The Effects of the Digital Modulation on the DAC Output Spectrum, Interpolation = 4× 0 0 –20 –20 –40 –40 –60 –60 –80 –80 –100 –100 02 1 34 02 1 34 f (×f ) f (×f ) OUT DATA OUT DATA Figure 67. 4× Interpolation, Modulation Disabled Figure 69. 4× Interpolation, Modulation = f /2 DAC 0 0 –20 –20 –40 –40 –60 –60 –80 –80 –100 –100 02 1 34 02 1 34 f (×f ) f (×f ) OUT DATA OUT DATA Figure 70. 4× Interpolation, Modulation = f /8 Figure 68. 4× Interpolation, Modulation = f /4 DAC DAC Rev. E | Page 34 of 56 AMPLITUDE (dBFS) AMPLITUDE (dBFS) 02858-068 02858-067 AMPLITUDE (dBFS) AMPLITUDE (dBFS) 02858-070 02858-069 AD9775 MODULATION, INTERPOLATION = 8× With Control Register 0x01, Bit 7 and Bit 6 set to 11, the Looking at Figure 63 through Figure 74, the user can see how interpolation rate of the AD9775 is 8×. Modulation is achieved higher interpolation rates reduce the complexity of the recon- by multiplying successive samples at the interpolation filter struction filter needed at the DAC output. It also becomes output by the sequence (0, +0.707, +1, +0.707, 0, −0.707, −1, apparent that the ability to modulate by f /2, f /4, or f /8 adds a S S S +0.707). Figure 71 through Figure 74 represent the spectral degree of flexibility in frequency planning. response of the AD9775 DAC output with 8× interpolation in the various modulation modes to a narrow-band baseband signal. The Effects of the Digital Modulation on the DAC Output Spectrum, Interpolation = 8× 0 0 –20 –20 –40 –40 –60 –60 –80 –80 –100 –100 0 12 3 4 567 8 02 1 34 f (×f ) f (×f ) OUT DATA OUT DATA Figure 73. 8× Interpolation, Modulation = fDAC/4 Figure 71. 8× Interpolation, Modulation Disabled 0 0 –20 –20 –40 –40 –60 –60 –80 –80 –100 –100 0 12 3 4 567 8 02 1 34 f (×f ) OUT DATA f (×f ) OUT DATA Figure 74. 8× Interpolation, Modulation = fDAC/8 Figure 72. 8× Interpolation, Modulation = fDAC/2 Rev. E | Page 35 of 56 AMPLITUDE (dBFS) AMPLITUDE (dBFS) 02858-072 02858-071 AMPLITUDE (dBFS) AMPLITUDE (dBFS) 02858-074 02858-073 AD9775 Note that the zero-stuffing option by itself does not change the ZERO STUFFING location of the images but rather their amplitude, pass-band (Control Register 0x01, Bit 3) flatness, and relative weighting. For instance, in the previous As shown in Figure 75, a 0 or null in the output frequency example, the pass-band amplitude flatness of the image at response of the DAC (after interpolation, modulation, and DAC 3 × fDATA/4 improved to +0.59 dB while the signal level increased reconstruction) occurs at the final DAC sample rate (f ). This DAC slightly from −10.5 dBFS to −8.1 dBFS. is due to the inherent sin(x)/x roll-off response in the digital-to- analog conversion. In applications where the desired frequency INTERPOLATING (COMPLEX MIX MODE) content is below fDAC/2, this may not be a problem. Note that at (Control Register 0x01, Bit 2) fDAC/2 the loss due to sin(x)/x is 4 dB. In direct RF applications, In the complex mix mode, the two digital modulators on the this roll-off may be problematic due to the increased pass-band AD9775 are coupled to provide a complex modulation function. amplitude variation as well as the reduced amplitude of the In conjunction with an external quadrature modulator, this desired signal. complex modulation can be used to realize a transmit image Consider an application where the digital data into the AD9775 rejection architecture. The complex modulation function can be +jωt −jωt represents a baseband signal around fDAC/4 with a pass band of programmed for e or e to give upper or lower image fDAC/10. The reconstructed signal out of the AD9775 would rejection. As in the real modulation mode, the modulation experience only a 0.75 dB amplitude variation over its pass band. frequency ω can be programmed via the SPI port for fDAC/2, However, the image of the same signal occurring at 3 × fDAC/4 fDAC/4, and fDAC/8, where fDAC represents the DAC output rate. suffers from a pass-band flatness variation of 3.93 dB. This image OPERATIONS ON COMPLEX SIGNALS may be the desired signal in an IF application using one of the Truly complex signals cannot be realized outside of a computer various modulation modes in the AD9775. This roll-off of image simulation. However, two data channels, both consisting of real frequencies can be seen in Figure 59 to Figure 74, where the effect data, can be defined as the real and imaginary components of a of the interpolation and modulation rate is apparent as well. complex signal. I (real) and Q (imaginary) datapaths are often 10 defined this way. By using the architecture defined in Figure 76, a system can be realized that operates on complex signals, ZERO STUFFING 0 ENABLED giving a complex (real and imaginary) output. +jωt –10 If a complex modulation function (e ) is desired, the real and imaginary components of the system correspond to the real and +jωt –20 imaginary components of e or cosωt and sinωt. As Figure 77 shows, the complex modulation function can be realized by ZERO STUFFING –30 applying these components to the structure of the complex DISABLED system defined in Figure 76. –40 a(t) INPUT OUTPUT c(t)× b(t) + d× b(t) –50 COMPLEX FILTER 0 0.5 1.0 1.5 2.0 = (c + jd) f , NORMALIZED TO f WITH ZERO STUFFING DISABLED (Hz) OUT DATA IMAGINARY b(t) INPUT OUTPUT b(t)× a(t) + c× b(t) Figure 75. Effect of Zero Stuffing on DAC’s sin(x)/x Response Figure 76. Realization of a Complex System To improve upon the pass-band flatness of the desired image, the zero stuffing mode can be enabled by setting the control INPUT (REAL) OUTPUT register bit to Logic 1. This option increases the ratio of (REAL) INPUT f /f by a factor of 2 by doubling the DAC sample rate and DAC DATA (IMAGINARY) inserting a midscale sample (that is, 1000 0000 0000 0000) after every data sample originating from the interpolation filter. This 90° is important as it affects the PLL divider ratio needed to keep the VCO within its optimum speed range. Note that the zero stuffing takes place in the digital signal chain at the output of OUTPUT (IMAGINARY) the digital modulator before the DAC. The net effect is to increase the DAC output sample rate by a –jωt e = COSωt + jSINωt factor of 2× with the 0 in the sin(x)/x DAC transfer function Figure 77. Implementation of a Complex Modulator occurring at twice the original frequency. A 6 dB loss in amplitude at low frequencies is also evident (see Figure 75). Rev. E | Page 36 of 56 SIN (X)/X ROLL-OFF (dBFS) 02858-075 02858-076 02858-077 AD9775 the baseband real and imaginary channels, now modulated onto COMPLEX MODULATION AND IMAGE REJECTION orthogonal (cosine and negative sine) carriers at the transmit OF BASEBAND SIGNALS frequency. It is important to remember that in this application In traditional transmit applications, a two-step upconversion is (two baseband data channels) the image rejection is not done in which a baseband signal is modulated by one carrier to dependent on the data at either of the AD9775 input channels. an intermediate frequency (IF) and then modulated a second In fact, image rejection still occurs with either one or both of time to the transmit frequency. Although this approach has the AD9775 input channels active. Note that by changing the several benefits, a major drawback is that two images are sign of the sinusoidal multiplying term in the complex created near the transmit frequency. Only one image is needed, modulator, the upper sideband image could have been the other being an exact duplicate. Unless the unwanted image suppressed while passing the lower one. This is easily done in is filtered, typically with analog components, transmit power is +jωt the AD9775 by selecting the e bit (Register 0x01, Bit 1). In wasted and the usable bandwidth available in the system is reduced. purely complex terms, Figure 79 represents the two-stage A more efficient method of suppressing the unwanted image upconversion from complex baseband to carrier. can be achieved by using a complex modulator followed by a INPUT (REAL) quadrature modulator. Figure 78 is a block diagram of a OUTPUT quadrature modulator. Note that it is in fact the real output half INPUT (IMAGINARY) of a complex modulator. The complete upconversion can actually be referred to as two complex upconversion stages, the SINωt 90° COSωt real output of which becomes the transmitted signal. The entire upconversion, from baseband to transmit frequency, is represented graphically in Figure 79. The resulting spectrum Figure 78. Quadrature Modulator shown in Figure 79 represents the complex data consisting of REAL CHANNEL (OUT) A/2 A/2 1 –F F C C REAL CHANNEL (IN) A –B/2J B/2J DC –F F C C COMPLEX TO QUADRATURE IMAGINARY CHANNEL (OUT) MODULATOR MODULATOR –A/2J A/2J IMAGINARY CHANNEL (IN) –F –F C C B DC B/2 B/2 –F F C C A/4 + B/4J A/4 – B/4J A/4 + B/4J A/4 – B/4J 2 –F F Q Q –F – F –F + F F – F F + F Q C Q C Q C Q C OUT REAL –A/4 – B/4J A/4 – B/4J A/4 + B/4J –A/4 + B/4J QUADRATURE MODULATOR –F F Q Q IMAGINARY REJECTED IMAGES A/2 + B/2J A/2 – B/2J –F F Q Q 1 F = COMPLEX MODULATION FREQUENCY C 2 F = QUADRATURE MODULATION FREQUENCY Q Figure 79. Two-Stage Upconversion and Resulting Image Rejection Rev. E | Page 37 of 56 02858-079 02858-078 AD9775 data on any channel. Image rejection on a channel occurs if IMAGE REJECTION AND SIDEBAND SUPPRESSION either the real or imaginary data, or both, is present on the OF MODULATED CARRIERS baseband channel. As shown in Figure 79, image rejection can be achieved by It is important to remember that the magnitude of a complex applying baseband data to the AD9775 and following the signal can be 1.414× the magnitude of its real or imaginary AD9775 with a quadrature modulator. To process multiple components. Due to this 3 dB increase in signal amplitude, the carriers while still maintaining image reject capability, each real and imaginary inputs to the AD9775 must be kept at least carrier must be complex modulated. As Figure 80 shows, single 3 dB below full scale when operating with the complex modu- or multiple complex modulators can be used to synthesize lator. Overranging in the complex modulator results in severe complex carriers. These complex carriers are then summed and distortion at the DAC output. applied to the real and imaginary inputs of the AD9775. COMPLEX BASEBAND A system in which multiple baseband signals are complex SIGNAL modulated and then applied to the AD9775 real and imaginary 1 inputs followed by a quadrature modulator is shown in Figure 82, × j(ω1 +ω2)t OUTPUT = REAL e which also describes the transfer function of this system and the spectral output. Note the similarity of the transfer functions 1/2 1/2 given in Figure 82 and Figure 80. Figure 82 adds an additional = REAL –ω1–ω2DC ω1 +ω2 complex modulator stage for the purpose of summing multiple FREQUENCY carriers at the AD9775 inputs. Also, as in Figure 79, the image Figure 80. Two-Stage Complex Upconversion rejection is not dependent on the real or imaginary baseband BASEBAND CHANNEL 1 R(1) REAL INPUT COMPLEX MULTICARRIER MODULATOR 1 REAL OUTPUT = IMAGINARY INPUT R(1) R(1) + R(2) + . . .R(N) (TO REAL INPUT OF AD9775) BASEBAND CHANNEL 2 R(2) REAL INPUT COMPLEX MODULATOR 2 MULTICARRIER IMAGINARY INPUT R(2) IMAGINARY OUTPUT = I(1) + I(2) + . . .I(N) (TO IMAGINARY INPUT OF AD9775) BASEBAND CHANNEL N R(N) = REAL OUTPUT OF N R(N) REAL INPUT I(N) = IMAGINARY OUTPUT OF N COMPLEX MODULATOR N IMAGINARY INPUT R(N) Figure 81. Synthesis of Multicarrier Complex Signal MULTIPLE BASEBAND CHANNELS REAL REAL REAL REAL MULTIPLE AD9775 QUADRATURE COMPLEX COMPLEX MODULATOR MODULATORS MODULATOR FREQUENCY =ω IMAGINARY IMAGINARY IMAGINARY Q FREQUENCY =ω ,ω ...ω 1 2 N FREQUENCY =ω C COMPLEX BASEBAND SIGNAL × OUTPUT = REAL j(ω +ω +ω )t e N C Q –ω –ω –ω ω +ω +ω DC 1 C Q 1 C Q REJECTED IMAGES Figure 82. Image Rejection with Multicarrier Signals Rev. E | Page 38 of 56 02858-081 02858-080 02858-082 AD9775 The complex carrier synthesized in the AD9775 digital the high end of the DAC output spectrum in these graphs is the modulator is accomplished by creating two real digital carriers first null point for the sin(x)/x roll-off, and the asymmetry of the in quadrature. Carriers in quadrature cannot be created with DAC output images is representative of the sin(x)/x roll-off over the spectrum. The internal PLL was enabled for these results. In the modulator running at fDAC/2. As a result, complex modula- tion only functions with modulation rates of fDAC/4 and fDAC/8. addition, a 35 MHz third-order low-pass filter was used at the AD9775/AD8345 interface to suppress DAC images. Regions A and B of Figure 83 to Figure 88 are the result of the complex signal described previously, when complex modulated An important point can be made by looking at Figure 91 and jωt in the AD9775 by +e . Regions C and D are the result of the Figure 93. Figure 91 represents a group of positive frequencies complex signal described previously, again with positive modulated by complex +fDAC/4, while Figure 93 represents a jωt frequency components only, modulated in the AD9775 by –e . group of negative frequencies modulated by complex −fDAC/4. The analog quadrature modulator after the AD9775 inherently When looking at the real or imaginary outputs of the AD9775, jωt modulates by +e . as shown in Figure 91 and Figure 93, the results look identical. However, the spectrum analyzer cannot show the phase Region A relationship of these signals. The difference in phase between Region A is a direct result of the upconversion of the complex the two signals becomes apparent when they are applied to the signal near baseband. If viewed as a complex signal, only the AD8345 quadrature modulator, with the results shown in images in Region A remain. The complex Signal A, consisting Figure 92 and Figure 94. of positive frequency components only in the digital domain, has images in the positive odd Nyquist zones (1, 3, 5, …), as 0 well as images in the negative even Nyquist zones. The appearance and rejection of images in every other Nyquist zone –20 becomes more apparent at the output of the quadrature D A BC D A BC modulator. The A images appear on the real and the imaginary –40 outputs of the AD9775, as well as on the output of the quadrature modulator, where the center of the spectral plot now represents –60 the quadrature modulator LO, and the horizontal scale now represents the frequency offset from this LO. –80 Region B Region B is the image (complex conjugate) of Region A. If a –100 spectrum analyzer is used to view the real or imaginary DAC –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 outputs of the AD9775, Region B appears in the spectrum. (LO) f (×f ) OUT DATA However, on the output of the quadrature modulator, Region B is rejected. Figure 83. 2× Interpolation, Complex f /4 Modulation DAC Region C Region C is most accurately described as a downconversion, as jωt 0 the modulating carrier is –e . If viewed as a complex signal, only the images in Region C remain. This image appears on the real –20 and imaginary outputs of the AD9775, as well as on the output of the quadrature modulator, where the center of the spectral plot DA B C D A B C now represents the quadrature modulator LO and the horizontal –40 scale represents the frequency offset from this LO. Region D –60 Region D is the image (complex conjugate) of Region C. If a –80 spectrum analyzer is used to view the real or imaginary DAC outputs of the AD9775, Region D appears in the spectrum. However, on the output of the quadrature modulator, Region D –100 –4.0 –3.0 –2.0 –1.0 0 1.0 2.0 3.0 4.0 is rejected. (LO) f (×f ) Figure 89 to Figure 96 show the measured response of the AD9775 OUT DATA and AD8345 given the complex input signal to the AD9775 in Figure 84. 4× Interpolation, Complex fDAC/4 Modulation Figure 89. The data in these graphs was taken with a data rate of 12.5 MSPS at the AD9775 inputs. The interpolation rate of 4× or 8× gives a DAC output data rate of 50 MSPS or 100 MSPS. As a result, Rev. E | Page 39 of 56 02858-084 02858-083 AD9775 0 0 –20 –20 DA B C DA B C DA BC D A B C –40 –40 –60 –60 –80 –80 –100 –100 –8.0 –6.0 –4.0 –2.0 0 2.0 4.0 6.0 8.0 –8.0 –6.0 –4.0 –2.0 0 2.0 4.0 6.0 8.0 (LO) (LO) f (×f ) f (×f ) OUT DATA OUT DATA Figure 85. 8× Interpolation, Complex f /4 Modulation Figure 88. 8× Interpolation, Complex f /8 Modulation DAC DAC 0 0 –10 –20 –20 –30 –40 –40 –50 DA B CD A B C –60 –60 –70 –80 –80 –90 –100 –100 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 010 20 30 40 50 (LO) FREQUENCY (MHz) f (×f ) OUT DATA Figure 86. 2× Interpolation, Complex f /8 Modulation Figure 89. AD9775 Real DAC Output of Complex Input Signal Near Baseband DAC (Positive Frequencies Only), Interpolation = 4×, No Modulation in AD9775 0 0 –10 –20 –20 –30 –40 –40 –50 DA B C D A B C –60 –60 –70 –80 –80 –90 –100 –100 –4.0 –3.0 –2.0 –1.0 0 1.0 2.0 3.0 4.0 750 760 770 780 790 800 810 820 830 840 850 (LO) FREQUENCY (MHz) f (×f ) OUT DATA Figure 87. 4× Interpolation, Complex fDAC/8 Modulation Figure 90. AD9775 Complex Output from Figure 89, Now Quadrature Modulated by AD8345 (LO = 800 MHz) Rev. E | Page 40 of 56 02858-087 02858-086 02858-085 AMPLITUDE (dBm) AMPLITUDE (dBm) 02858-088 02858-090 02858-089 AD9775 0 0 –10 –10 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 –100 0 102030 40 50 750 760 770 780 790 800 810 820 830 840 850 FREQUENCY (MHz) FREQUENCY (MHz) Figure 91. AD9775 Real DAC Output of Complex Input Signal Near Figure 94. AD9775 Complex Output from Figure 93, Baseband (Positive Frequencies Only), Interpolation = 4×, Now Quadrature Modulated by AD8345 (LO = 800 MHz) Complex Modulation in AD9775 = +fDAC/4 0 0 –10 –10 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 –100 750 760 770 780 790 800 810 820 830 840 850 0 20 40 60 80 100 FREQUENCY (MHz) FREQUENCY (MHz) Figure 92. AD9775 Complex Output from Figure 91, Figure 95. AD9775 Real DAC Output of Complex Input Signal Near Now Quadrature Modulated by AD8345 (LO = 800 MHz) Baseband (Positive Frequencies Only), Interpolation = 8×, Complex Modulation in AD9775 = +fDAC/8 0 0 –10 –10 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 –100 0 102030 40 50 700 720 740 760 780 800 820 840 860 880 900 FREQUENCY (MHz) FREQUENCY (MHz) Figure 93. AD9775 Real DAC Output of Complex Input Signal Near Figure 96. AD9775 Complex Output from Figure 95, Baseband (Negative Frequencies Only), Interpolation = 4×, Now Quadrature Modulated by AD8345 (LO = 800 MHz) Complex Modulation in AD9775 = −fDAC/4 Rev. E | Page 41 of 56 AMPLITUDE (dBm) AMPLITUDE (dBm) AMPLITUDE (dBm) 02858-093 02858-092 02858-091 AMPLITUDE (dBm) AMPLITUDE (dBm) AMPLITUDE (dBm) 02858-096 02858-095 02858-094 AD9775 APPLYING THE OUTPUT CONFIGURATIONS For the typical situation, where IOUTFS = 20 mA and RA and RB The following sections illustrate typical output configurations both equal 50 Ω, the equivalent circuit values become for the AD9775. Unless otherwise noted, it is assumed that IOUTFS is set to a nominal 20 mA. For applications requiring V = 2 V p-p SOURCE optimum dynamic performance, a differential output configu- R = 100 Ω OUT ration is suggested. A simple differential output may be achieved by converting IOUTA and IOUTB to a voltage output Note that the output impedance of the AD9775 DAC itself is by terminating them to AGND via equal value resistors. This greater than 100 kΩ and typically has no effect on the type of configuration may be useful when driving a differential impedance of the equivalent output circuit. voltage input device such as a modulator. If a conversion to a DIFFERENTIAL COUPLING USING A single-ended signal is desired and the application allows for ac TRANSFORMER coupling, an RF transformer may be useful, or if power gain is An RF transformer can be used to perform a differential-to- required, an op amp may be used. The transformer configu- single-ended signal conversion, as shown in Figure 98. A dif- ration provides optimum high frequency noise and distortion ferentially coupled transformer output provides the optimum performance. The differential op amp configuration is suitable distortion performance for output signals whose spectral content for applications requiring dc coupling, signal gain, and/or level lies within the transformer’s pass band. An RF transformer, such shifting within the bandwidth of the chosen op amp. as the Mini-Circuits T1-1T, provides excellent rejection of A single-ended output is suitable for applications requiring a common-mode distortion (that is, even-order harmonics) and unipolar voltage output. A positive unipolar output voltage noise over a wide frequency range. It also provides electrical results if IOUTA and/or IOUTB is connected to a load resistor, RLOAD, isolation and the ability to deliver twice the power to the load. referred to AGND. This configuration is most suitable for a Transformers with different impedance ratios can also be used for single-supply system requiring a dc-coupled, ground-referred impedance matching purposes. output voltage. Alternatively, an amplifier could be configured MINI-CIRCUITS as an I-V converter, thus converting I or I into a OUTA OUTB T1-1T I OUTA negative unipolar voltage. This configuration provides the best DAC R LOAD DAC dc linearity as IOUTA or IOUTB are maintained at ground or I OUTB virtual ground. Figure 98. Transformer-Coupled Output Circuit UNBUFFERED DIFFERENTIAL OUTPUT, EQUIVALENT CIRCUIT The center tap on the primary side of the transformer must be connected to AGND to provide the necessary dc current path In many applications, it may be necessary to understand the for both I and I . The complementary voltages appearing OUTA OUTB equivalent DAC output circuit. This is especially useful when at I and I (that is, V and V ) swing symmetrically OUTA OUTB OUTA OUTB designing output filters or when driving inputs with finite input around AGND and should be maintained within the specified impedances. Figure 97 illustrates the output of the AD9775 and output compliance range of the AD9775. A differential resistor, the equivalent circuit. A typical application where this RDIFF, can be inserted in applications where the output of the information may be useful is when designing an interface filter transformer is connected to the load, R , via a passive LOAD between the AD9775 and Analog Devices’ AD8345 quadrature reconstruction filter or cable. R is determined by the DIFF modulator. transformer’s impedance ratio and provides the proper source I V + termination that results in a low VSWR. Note that approxi- OUTA OUT mately half the signal power dissipates across RDIFF. I OUTB V – OUT R + R A B V = SOURCE V OUT I × (R + R ) OUTFS A B (DIFFERENTIAL) p-p Figure 97. DAC Output Equivalent Circuit Rev. E | Page 42 of 56 02858-097 02858-098 AD9775 Gain/Offset Adjust DIFFERENTIAL COUPLING USING AN OP AMP The matching of the DAC output to the common-mode input An op amp can also be used to perform a differential-to-single- of the AD8345 allows the two components to be dc-coupled, ended conversion, as shown in Figure 99. This has the added with no level shifting necessary. The combined voltage offset of benefit of providing signal gain as well. In Figure 99, the the two parts can therefore be compensated for via the AD9775 AD9775 is configured with two equal load resistors, R , of LOAD programmable offset adjust. This allows excellent LO cancella- 25 Ω. The differential voltage developed across I and I is OUTA OUTB tion at the AD8345 output. The programmable gain adjust converted to a single-ended signal via the differential op amp allows for optimal image rejection as well. configuration. An optional capacitor can be installed across IOUTA and IOUTB, forming a real pole in a low-pass filter. The The AD9775 evaluation board includes an AD8345 and addition of this capacitor also enhances the op amp distortion recommended interface (Figure 104 and Figure 105). On the performance by preventing the DAC fast slewing output from output of the AD9775, R9 and R10 convert the DAC output overloading the input of the op amp. current to a voltage. R16 may be used to do a slight common- 500Ω mode shift if necessary. The (now voltage) signal is applied to a 225Ω low-pass reconstruction filter to reject DAC images. The I OUTA components installed on the AD9775 provide a 35 MHz cutoff AD8021 DAC but may be changed to fit the application. A balun (Mini- I OUTB C OPT 225Ω Circuits ADTL1-12) is used to cross the ground plane boundary AVDD R OPT to the AD8345. Another balun (Mini-Circuits ETC1-1-13) is 25Ω 25Ω 500Ω 225Ω used to couple the LO input of the AD8345. The interface requires a low ac impedance return path from the AD8345, so a Figure 99. Op Amp-Coupled Output Circuit single connection between the AD9775 and AD8345 ground The common-mode (and second-order distortion) rejection of planes is recommended. this configuration is typically determined by the resistor The performance of the AD9775 and AD8345 in an image reject matching. The op amp used must operate from a dual supply transmitter, reconstructing three W-CDMA carriers, can be seen in because its output is approximately ±1.0 V. A high speed Figure 100. The LO of the AD8345 in this application is 800 MHz. amplifier, such as the AD8021, capable of preserving the Image rejection (50 dB) and LO feedthrough (−78 dBFS) have been differential performance of the AD9775 while meeting other optimized with the programmable features of the AD9775. The system level objectives (such as cost and power) is average output power of the digital waveform for this test was set recommended. The op amp differential gain, its gain setting to −15 dBFS to account for the peak-to-average ratio of the resistor values, and full-scale output swing capabilities should W-CDMA signal. all be considered when optimizing this circuit. R is only OPT 0 necessary if level shifting is required on the op amp output. In Figure 99, AVDD, which is the positive analog supply for both –10 the AD9775 and the op amp, is also used to level shift the –20 differential output of the AD9775 to midsupply, that is, –30 AVDD/2. –40 INTERFACING THE AD9775 WITH THE AD8345 –50 QUADRATURE MODULATOR –60 The AD9775 architecture was defined to operate in a transmit –70 signal chain using an image reject architecture. A quadrature –80 modulator is also required in this application and should be –90 designed to meet the output characteristics of the DAC as much as possible. The AD8345 from Analog Devices meets many of –100 762.5 782.5 802.5 822.5 842.5 the requirements for interfacing with the AD9775. As with any FREQUENCY (MHz) DAC output interface, there are a number of issues that have to Figure 100. AD9775/AD8345 Synthesizing a Three-Carrier be resolved. The following sections list some of these issues. W-CDMA Signal at an LO of 800 MHz DAC Compliance Voltage/Input Common-Mode Range The dynamic range of the AD9775 is optimal when the DAC outputs swing between ±1.0 V. The input common-mode range of the AD8345, at 0.7 V, allows optimum dynamic range to be achieved in both components. Rev. E | Page 43 of 56 02858-099 AMPLITUDE (dBm) 02858-100 AD9775 EVALUATION BOARD DAC Differential Outputs The AD9775 evaluation board allows easy configuration of the Transformers T2 and T3 should be in place. Note that the lower various modes, programmable via the SPI port. Software is band of operation for these transformers is 300 kHz to 500 kHz. available for programming the SPI port from PCs running Jumper 4, Jumper 8, Jumper 13 to Jumper 17, and Jumper 28 to Windows® 95, Windows 98, or Windows NT®/2000. The Jumper 30 should remain unsoldered. The outputs are taken evaluation board also contains an AD8345 quadrature from S3 and S4. modulator and support circuitry that allows the user to optimally configure the AD9775 in an image reject transmit Using the AD8345 signal chain. Remove Transformers T2 and T3. Jumper JP4 and Jumper 28 to Figure 101 to Figure 104 show how to configure the evaluation Jumper 30 should remain unsoldered. Jumper 13 to Jumper 16 board in the one-port and two-port input modes with the PLL should be soldered. The desired components for the low-pass enabled and disabled. Refer to Figure 105 to Figure 114, the interface filter L6, L7, C55, and C81 should be in place. The LO schematics, and the layout for the AD9775 evaluation board for drive is connected to the AD8345 via J10 and the balun T4, and the jumper locations described in the DAC Single-Ended the AD8345 output is taken from J9. Outputs section. The AD9775 outputs can be configured for various applications by referring to the following instructions. DAC Single-Ended Outputs Remove Transformers T2 and T3. Solder jumper links JP4 or JP28 to look at the DAC1 outputs. Solder jumper links JP29 or JP30 to look at the DAC2 outputs. Jumper 8 and Jumper 13 to Jumper 17 should remain unsoldered. Jumper JP35 to Jumper JP38 can be used to ground one of the DAC outputs while the other is measured single ended. Optimum single-ended distortion performance is typically achieved in this manner. The outputs are taken from S3 and S4. Rev. E | Page 44 of 56 AD9775 LECROY SIGNAL GENERATOR PULSE TRIG GENERATOR INP DATACLK CLK+/CLK– INPUT CLOCK AWG2021 40-PIN RIBBON CABLE OR DAC1, DB13–DB0 DG2020 DAC2, DB13–DB0 AD9775 JUMPER CONFIGURATION FOR TWO-PORT MODE PLL ON SOLDERED/IN UNSOLDERED/OUT JP1 – × JP2 – × JP3 – × JP5 – × JP6 – × JP12 – × JP24 – × JP25 – × JP26 – × JP27 – × JP31 – × JP32 – × JP33 – × NOTES 1. TO USE PECL CLOCK DRIVER, SOLDER JP41 AND JP42 AND REMOVE TRANSFORMER T1. 2. IN TWO-PORT MODE, IF DATACLK/PLL_LOCK IS PROGRAMMED TO OUTPUT PIN 8, JP25 AND JP39 SHOULD BE SOLDERED. IF DATACLK/PLL_LOCK IS PROGRAMMED TO OUTPUT PIN 53, JP46 AND JP47 SHOULD BE SOLDERED. SEE THE TWO-PORT DATA INPUT MODE FOR MORE INFORMATION. Figure 101. Test Configuration for AD9775 in Two-Port Mode with PLL Enabled, Signal Generator Frequency = Input Data Rate, DAC Output Data Rate = Signal Generator Frequency × Interpolation Rate LECROY SIGNAL GENERATOR TRIG PULSE INP GENERATOR ONEPORTCLK CLK+/CLK– INPUT CLOCK AWG2021 OR DAC1, DB13–DB0 DG2020 DAC2, DB13–DB0 AD9775 JUMPER CONFIGURATION FOR ONE-PORT MODE PLL ON SOLDERED/IN UNSOLDERED/OUT JP1 – × JP2 – × JP3 – × JP5 – × JP6 – × JP12 – × JP24 – × JP25 – × JP26 – × JP27 – × JP31 – × JP32 – × JP33 – × NOTES 1. TO USE PECL CLOCK DRIVER, SOLDER JP41 AND JP42 AND REMOVE TRANSFORMER T1. Figure 102. Test Configuration for AD9775 in One-Port Mode with PLL Enabled, Signal Generator Frequency = One-Half Interleaved Input Data Rate, ONEPORTCLK = Interleaved Input Data Rate, DAC Output Data Rate = Signal Generator Frequency × Interpolation Rate Rev. E | Page 45 of 56 02858-102 02858-101 AD9775 LECROY SIGNAL GENERATOR PULSE TRIG GENERATOR INP DATACLK CLK+/CLK– INPUT CLOCK AWG2021 40-PIN RIBBON CABLE OR DAC1, DB13–DB0 DG2020 DAC2, DB13–DB0 AD9775 JUMPER CONFIGURATION FOR TWO-PORT MODE PLL OFF SOLDERED/IN UNSOLDERED/OUT JP1 – × JP2 – × JP3 – × JP5 – × JP6 – × JP12 – × JP24 – × JP25 – × JP26 – × JP27 – × JP31 – × JP32 – × JP33 – × NOTES 1. TO USE PECL CLOCK DRIVER, SOLDER JP41 AND JP42 AND REMOVE TRANSFORMER T1. 2. IN TWO-PORT MODE, IF DATACLK/PLL_LOCK IS PROGRAMMED TO OUTPUT PIN 8, JP25 AND JP39 SHOULD BE SOLDERED. IF DATACLK/PLL_LOCK IS PROGRAMMED TO OUTPUT PIN 53, JP46 AND JP47 SHOULD BE SOLDERED. SEE THE TWO-PORT DATA INPUT MODE FOR MORE INFORMATION. Figure 103. Test Configuration for AD9775 in Two-Port Mode with PLL Disabled, DAC Output Data Rate = Signal Generator Frequency, DATACLK = Signal Generator Frequency/Interpolation Rate LECROY SIGNAL GENERATOR TRIG PULSE INP GENERATOR ONEPORTCLK CLK+/CLK– INPUT CLOCK AWG2021 OR DAC1, DB13–DB0 DG2020 DAC2, DB13–DB0 AD9775 JUMPER CONFIGURATION FOR ONE-PORT MODE PLL OFF SOLDERED/IN UNSOLDERED/OUT JP1 – × JP2 – × JP3 – × JP5 – × JP6 – × JP12 – × JP24 – × JP25 – × JP26 – × JP27 – × JP31 – × JP32 – × JP33 – × NOTES 1. TO USE PECL CLOCK DRIVER, SOLDER JP41 AND JP42 AND REMOVE TRANSFORMER T1. Figure 104. Test Configuration for AD9775 in One-Port Mode with PLL Disabled, DAC Output Data Rate = Signal Generator Frequency, ONEPORTCLK = Interleaved Input Data Rate = 2× Signal Generator Frequency/Interpolation Rate Rev. E | Page 46 of 56 02858-104 02858-103 AD9775 Figure 105. AD8345 Circuitry on AD9775 Evaluation Board Rev. E | Page 47 of 56 L6 R32 C79 DNP 51Ω DNP O2N LC0805 RC0603 CC0603 POWER INPUT FILTERS C55 C81 CC0805 CC0805 JP19 DNP DNP L8 LC0805 RC0603 RC0603 FERRITE VDDMIN O2P W11 VDDM LC1210 L7 R33 R34 1 3 JP45 DNP 51Ω DNP P C28 + C32 DCASE CC0805 16V JP43 JP44 T5 0.1μF 22μF MODULATED OUTPUT S DGND2 C74 R23 W12 DGND2; 3, 4, 5 64 100pF 0Ω VDDM 2 J9 CC0603 RC0603 L3 TP2 2 C72 C35 C75 + JP9 FERRITE RED BCASE CC0603 16 15 14 13 12 11 10 9 DVDD_IN 10V 100pF CC0603 0.1μF 2 J8 DVDD LC1210 10μF C65 C66 + + VDDM C67 DCASE CC0805 DCASE 16V 16V 0.1μF AD8345 U2 2 22μF 22μF R26 DGND J5 1kΩ TP3 1 2 3 4 5 6 7 8 BLK JP18 L2 TP4 FERRITE JP10 RED 2 AVDD_IN LOCAL OSC INPUT C78 J4 AVDD C76 LC1210 0.1μF R28 100pF DGND2; 3, 4, 5 ETC1-1-13 0Ω 3 4 C64 C61 + + C68 J10 RC0603 CC0603 DCASE 16V CC0805 DCASE 16V R30 0.1μF SP 22μF 22μF 2 2 DNP CC0603 AGND 1 5 T4 J6 C77 2 TP5 JP7 100pF BLK 4 6 L1 TP6 S JP21 FERRITE JP11 RED CLKVDD_IN T6 J3 CLKVDD LC1210 2 P C63 C62 + + 31 C69 DCASE CC0805 DCASE 16V 16V 0.1μF 22μF 22μF R35 C80 L4 CGND 51Ω DNP DNP J7 O1N c TP7 LC0805 RC0603 CC0603 BLK C54 C73 CC0805 JP20 DNP L5 DNP R36 DNP 51Ω RC0603 O1P LC0805 RC0603 R37 DNP 02858-105 CC0805 ADTL1-12 CC0603 ADTL1-12 IBBP QBBP IBBN QBBN G1A G4B G1B G4A LOIN VPS2 LOIP VOUT VPS1 G3 ENBL G2 RC0603 RC0603 AD9775 Figure 106. AD9775 Clock, Power Supplies, and Output Circuitry Rev. E | Page 48 of 56 R2 R3 JP8 1kΩ 1kΩ DVDD R10 C70 51kΩ 0.1μF RC0603 RC0603 C36 C37 C38 C39 C40 C41 CLKVDD C1 C12 C11 C42 C27 CC0805 CC0805 CC0805 CC0805 CC0805 CC0805 RC0603 + CC0603 BCASE CC0603 CC0603 CC0603 CC0603 10μF 0.1μF 0.1μF 0.1μF 0.1μF 0.1μF 0.1μF R9 R16 6.3V 0.1μF 0.1μF 0.1μF 1pF RC0603 RC0603 51kΩ 10kΩ TP15 C13 JP4 JP22 c WHT 0.1μF c 1 80 VDDC1 VDDA6 AVDD 6 1 JP28 2 LF VSSA10 79 5 2 C20 C19 C14 C2 + 3 VDDC2 VDDA5 78 J37 CLKP AGND; 3, 4, 5 CC0603 CC0603 CC0603 BCASE 10μF T2 4 3 R1 4 77 VSSC1 VSSA9 0.1μF 0.1μF 0.1μF 6.3V OUT1 JP23 CLKN 3 4 200Ω JP1 S3 5 CLKP VDDA4 76 T1 2 5 6 75 T1-1T CLKN VSSA8 JP2 RC1206 1 6 J35 C58 R42 JP33 7 74 VSSC2 VSSA7 ADCLK R38 10kΩ DNP 49.9kΩ 8 DCLK-PLLL IOUT1P 73 c T1-1T CLKIN 9 72 VSSD1 IOUT1N C58 O1N JP39 CC0603 S1 DNP 10 71 JP13 VDDD1 VSSA6 C57 DVDD O1P DNP c 11 P1D15 VSSA5 70 JP15 ACLKX CGND; 3, 4, 5 C10 C26 + AD15 O2N BCASE CC0603 10μF 12 IOUT2P 69 P1D14 JP16 AD14 O2P 6.3V 0.001μF JP24 13 P1D13 IOUT2N 68 JP14 C59 AD13 CC0603 DNP 14 P1D12 VSSA4 67 AVDD JP36 AD12 74VCX86 CX3 15 66 P1D11 VSSA3 AD11 12 JP25 JP38 JP29 CX2 11 16 P1D10 VDDA3 65 U3 AD10 13 C18 C17 C15 C3 + CX1 17 VSSD2 VSSA2 64 CC0805 CC0603 CC0603 BCASE 10μF JP30 DVDD; 14 18 VDDD2 63 U1 VDDA2 0.1μF 0.1μF 0.1μF 6.3V DGND; 7 DVDD JP12 19 P1D9 VSSA1 62 T3 AGND; 3, 4, 5 C25 C9 + TP14 AD09 R40 BCASE CC0603 10μF OUT 2 20 P1D8 VDDA1 61 3 4 DVDD TP11 TP10 TP9 TP8 WHT 5kΩ AD08 S4 6.3V 0.001μF WHT WHT WHT WHT FSADJ1 DGND; 3, 4, 5 21 P1D7 60 2 5 AD07 DATACLK RC0603 22 P1D6 FSADJ2 59 1 6 AD06 R43 R5 S2 23 P1D5 REFOUT 58 49.9kΩ 49.9Ω AD05 T1-1T JP3 24 P1D4 57 JP17 RESET AD04 R7 R8 R12 C70 25 VSSD3 SP-CSB 56 C16 C4 2kΩ 1kΩ + SPCSP 51kΩ 0.1μF C29 CC0603 BCASE 10μF 0.01% 0.01% 26 55 VDDD3 SP-CLK 0.1μF R6 RC0603 CC0603 DVDD SPCLK 0.1μF 6.3V 27 P1D3 SP-SDI 54 1kΩ C8 C24 R11 R17 + AD03 SPSDI BCASE CC0603 RC0603 RC0603 10μF 28 P1D2 SP-SDO 53 51kΩ 10kΩ AD02 SPSDO 6.3V 0.001μF 29 52 P1D1 VSSD6 AD01 30 VDDD6 51 P1D0 AD00 JP5 DVDD DVDD 31 P2D15-IQSEL P2D0 50 BD15 BD00 32 P2D14-OPCLK P2D1 49 C21 C5 + BD01 JP27 CC0603 BCASE 10μF 33 P2D13 P2D2 48 R39 OPCLK_3 BD13 BD02 0.001μF 6.3V JP32 34 47 1kΩ P2D12 P2D3 BD12 BD03 DGND; 3, 4, 5 35 VSSD4 P2D4 46 JP40 BD04 JP26 36 VDDD4 45 S6 P2D5 DVDD BD05 BD14 IQ 74VCX86 JP47 37 44 P2D11 VSSD5 9 C7 C23 IQ + BD11 JP46 8 74VCX86 JP31 BCASE CC0603 SPSDO 10μF 38 P2D10 VDDD5 43 12 IQ U4 10 BD10 DVDD 11 6.3V 0.001μF 39 P2D9 42 OPCLK U4 P2D6 13 BD09 BD06 DVDD; 14 40 41 JP34 P2D8 P2D7 C6 C22 + BD08 BD07 DVDD; 14 BCASE DGND; 7 CC0603 10μF OPCLK 6.3V DGND; 7 0.001μF AD9775+TSP S5 C45 0.01μF AGND; 3, 4, 5 02858-106 CC0805 CC0603 CC0605 RC0603 RC0603 CC0603 RC1206 CC0603 AD9775 Figure 107. AD9775 Evaluation Board Input (A Channel) and Clock Buffer Circuitry Rev. E | Page 49 of 56 R1 R2 R3 R4 R5 R6 R7 R8 R9 R1 R2 R3 R4 R5 R6 R7 R8 R9 RCOM RCOM RP5 RP7 50Ω DNP DATA-A 1 2 345 67 89 10 1 2 3 45 678 9 10 74VCX86 RP1 22Ω 2 1 AD15 1 DVDD 116 CX1 3 RP1 22Ω U3 2 4 3 AD14 215 DVDD; 14 RP1 22Ω C30 + 6 5 AD13 AGND; 7 C33 314 ACASE CC0805 4.7μF RP1 22Ω 0.1μF 8 7 AD12 74VCX86 6.3V 413 4 RP1 22Ω 6 10 9 AD11 512 U3 5 RP1 22Ω DVDD; 14 12 11 AD10 611 AGND; 7 RP1 22Ω 14 13 AD09 710 RP1 22Ω 74VCX86 16 15 AD08 9 89 8 RP2 22Ω U3 CX3 10 18 17 AD07 116 CX2 DVDD; 14 RP2 22Ω 20 19 AD06 AGND; 7 215 RP2 22Ω 22 21 AD05 314 RP2 22Ω 24 23 AD04 413 RP2 22Ω 26 25 AD03 512 RP2 22Ω 28 27 AD02 611 DVDD RP2 22Ω 30 29 AD01 710 74VCX86 RP2 22Ω 4 32 31 AD00 6 C31 89 + C34 5 U4 4.7μF ACASE CC0805 34 33 DVDD; 14 0.1μF 6.3V AGND; 7 36 35 RP6 1 2 345 67 89 10 1 2 3 45 678 9 10 38 37 RP8 50Ω DNP 40 39 RCOM RCOM R1 R2 R3 R4 R5 R6 R7 R8 R9 R1 R2 R3 R4 R5 R6 R7 R8 R9 RIBBON J1 R15 220Ω ADCLK DVDD RC1206 4 10 DVDD PRE PRE 3 J Q 5 OPCLK_2 11 J Q 9 C52 + C53 74VCX86 OPCLK 1 CLK 12 CLK 4.7μF ACASE CC0805 OPCLK_3 1 0.1μF 6.3V 3 2 K Q 6 2 U4 13 K Q 7 CLR DVDD; 14 CLR AGND; 7 15 14 74LCX112 74LCX112 AGND; 8 U7 U7 DVDD; 16 02858-107 AD9775 Figure 108. AD9775 Evaluation Board Input (B Channel) and SPI Port Circuitry Rev. E | Page 50 of 56 R21 CLKVDD R14 C47 DNP RC0805 200Ω 1nF c RC0805 R20 R1 R2 R3 R4 R5 R6 R7 R8 R9 R1 R2 R3 R4 R5 R6 R7 R8 R9 c CC805 RCOM RCOM RC0805 R4 DNP CLKVDD RP12 RP9 120Ω RC0805 MC100EPT22 C46 JP42 50Ω DNP DATA-B 1 2 3 45 67 8 9 10 1 2 34 567 89 10 0.1μF 1 CLKP 7 R19 U8 JP41 2 100Ω CC805 CLKN CGND; 5 RP3 22Ω R22 2 1 BD15 R13 CLKVDD; 8 116 DNP C48 RP3 22Ω RC0805 120Ω CLKVDD RC0805 ACLKX 4 3 BD14 1nF 215 R24 RC0805 RP3 22Ω DNP RC0805 6 5 BD13 c 314 c CC805 R18 RP3 22Ω c 8 7 BD12 200Ω 413 CLKDD RP3 22Ω MC100EPT22 10 9 BD11 512 3 RP3 22Ω 6 12 11 BD10 U8 C49 611 + CC805 C60 4 RP3 22Ω ACASE c 4.7μF 14 13 BD09 0.1μF 710 CLKVDD; 8 6.3V RP3 22Ω 16 15 CGND; 5 BD08 89 RP4 22Ω 18 17 BD07 c 116 RP4 22Ω 20 19 BD06 215 RP4 22Ω 22 21 BD05 314 RP4 22Ω 24 23 BD04 413 RP4 22Ω 26 25 BD03 512 RP4 22Ω 28 27 BD02 611 RP4 22Ω 30 29 R50 BD01 710 12 13 9kΩ RP4 22Ω 2 1 32 31 BD00 U5 U5 RC0805 89 DGND; 7 DGND; 7 74AC14 74AC14 34 33 DVDD; 14 DVDD; 14 36 35 R48 SPI PORT 1 2 3 45 67 8 9 10 RP11 1 2 34 567 89 10 10 9kΩ 38 37 43 11 P1 RP10 U5 U5 50Ω RC0805 RCOM DNP 1 40 39 RCOM DGND; 7 DGND; 7 74AC14 74AC14 R1 R2 R3 R4 R5 R6 R7 R8 R9 R1 R2 R3 R4 R5 R6 R7 R8 R9 DVDD; 14 DVDD; 14 2 RIBBON J2 R45 3 65 89 9kΩ 4 SPCSB U5 U5 RC0805 DGND; 7 DGND; 7 5 74AC14 74AC14 DVDD; 14 DVDD; 14 SPCLK 6 SPSDI 1 2 13 12 SPSDO U6 U6 DGND; 7 DGND; 7 DVDD; 14 DVDD; 14 74AC14 74AC14 4 10 3 11 U6 U6 DVDD DVDD DGND; 7 DGND; 7 DVDD; 14 DVDD; 14 74AC14 C43 74AC14 C44 + + CC805 C50 C51 ACASE 4.7μF CC805 ACASE 4.7μF 0.1μF 0.1μF 6.3V 6 8 6.3V 5 9 U6 U6 DGND; 7 DGND; 7 DVDD; 14 74AC14 DVDD; 14 74AC14 02858-108 AD9775 Figure 109. AD9775 Evaluation Board Components, Top Side Figure 110. AD9775 Evaluation Board Components, Bottom Side Rev. E | Page 51 of 56 02858-110 02858-109 AD9775 Figure 111. AD9775 Evaluation Board Layout, Layer One (Top) Figure 112. AD9775 Evaluation Board Layout, Layer Two (Ground Plane) Rev. E | Page 52 of 56 02858-111 02858-112 AD9775 Figure 113. AD9775 Evaluation Board Layout, Layer Three (Power Plane) Figure 114. AD9775 Evaluation Board Layout, Layer Four (Bottom) Rev. E | Page 53 of 56 02858-114 02858-113 AD9775 OUTLINE DIMENSIONS 14.20 14.00 SQ 12.20 13.80 1.20 12.00 SQ 0.75 MAX 11.80 0.60 0.45 61 80 80 61 1 60 1 60 PIN 1 EXPOSED 6.00 TOP VIEW PAD BSC SQ (PINS DOWN) BOTTOM VIEW 0° MIN 1.05 (PINS UP) 0.20 1.00 0.09 20 41 41 20 0.95 7° 40 40 21 21 3.5° VIEW A 0.15 0.50 BSC 0.27 0° SEATING LEAD PITCH 0.05 0.08 MAX 0.22 PLANE COPLANARITY 0.17 VIEW A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-ADD-HD Figure 115. 80-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] (SV-80-1) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option AD9775BSV −40°C to +85°C 80-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] SV-80-1 AD9775BSVRL −40°C to +85°C 80-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] SV-80-1 1 AD9775BSVZ −40°C to +85°C 80-Lead, Thin Quad Flat Package, Exposed Pad [TQFP_EP] SV-80-1 1 AD9775BSVZRL −40°C to +85°C 80-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] SV-80-1 AD9775-EB Evaluation Board 1 Z = Pb-free part. Rev. E | Page 54 of 56 AD9775 NOTES Rev. E | Page 55 of 56 AD9775 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C02858-0-12/06(E) Rev. E | Page 56 of 56