ANALOG DEVICES AD9774

14-Bit, 32 MSPS TxDAC+™ a with 43 Interpolation Filters AD9774 FEATURES FUNCTIONAL BLOCK DIAGRAM Single 3 V or 5 V Supply PLL PLL VCO ENABLE IN/EXT DIVIDE CLK43IN PLLLOCK 14-Bit DAC Resolution and Input Data Width 32 MSPS Input Data Rate at 5 V PLLCOM 13.5 MHz Reconstruction Bandwidth AD9774 12 ENOBS @ 1 MHz LPF PLL CLOCK CLK IN/OUT MULTIPLIER 77 dBc SFDR @ 5 MHz 13 23 43 PLLVDD 43 Interpolation Filter 43 69 dB Image Rejection 14 14 14 14 DATA EDGE IOUTA 14-BIT INPUTS TRIGGERED 23 23 84% Passband to Nyquist Ratio DAC LATCHES IOUTB (DB13-DB0) 0.002 dB Passband Ripple 23 3/4 Cycle Latency SNOOZE REFIO +1.2V REFERENCE Internal 43 Clock Multiplier SLEEP AND CONTROL AMP FSADJ On-Chip 1.20 V Reference DCOM DVDD ICOMP ACOM AVDD REFLO REFCOMP 44-Lead MQFP Package APPLICATIONS Edge-triggered input latches, a 4· clock multiplier, and a tem- Communication Transmit Channel: perature compensated bandgap reference have also been inte- Wireless Basestations grated to provide a complete monolithic DAC solution. Flexible ADSL/HFC Modems supply options support +3 V and +5 V CMOS logic families. Direct Digital Synthesis (DDS) TTL logic levels can also be accommodated by reducing the AD9774 digital supply. PRODUCT DESCRIPTION The on-chip reference and control amplifier are configured for The AD9774 is a single supply, oversampling, 14-bit digital-to- maximum accuracy and flexibility. The AD9774 can be driven analog converter (DAC) optimized for waveform reconstruction by the on-chip reference or by a variety of external reference applications requiring exceptional dynamic range. Manufac- voltages. The full-scale current of the AD9774 can be adjusted tured on an advanced CMOS process, it integrates a complete, over a 2 mA to 20 mA range, thus providing additional gain low distortion 14-bit DAC with a 4· digital interpolation filter ranging capabilities. and clock multiplier. The two-stage, 4· digital interpolation The AD9774 is available in a 44-lead MQFP package. It is filter provides more than a six-fold reduction in the complexity specified for operation over the industrial temperature range. of the analog reconstruction-filter. It does so by multiplying the input data rate by a factor of four while simultaneously suppressing PRODUCT HIGHLIGHTS the original inband images by more than 69 dB. The on-chip 1. On-Chip 4· interpolation filter eases analog reconstruction clock multiplier provides all the necessary clocks. The AD9774 filter requirements by suppressing the first three images by 69 dB. can reconstruct full-scale waveforms having bandwidths as high 2. Low glitch and fast settling time provide outstanding dynamic as 13.5 MHz when operating at an input data rate of 32 MSPS performance for waveform reconstruction or digital synthesis and a DAC output rate of 128 MSPS. requirements, including communications. The 14-bit DAC provides differential current outputs to support 3. On-chip, edge-triggered input CMOS latches interface readily differential or single-ended applications. A segmented current to CMOS and TTL logic families. The AD9774 can support source architecture is combined with a proprietary switching tech- input data rates up to 32 MSPS. nique to reduce spurious components and enhance dynamic per- 4. A temperature compensated, 1.20 V bandgap reference is formance. Matching between the two current outputs ensures included on-chip, providing a complete DAC solution. An enhanced dynamic performance in a differential output configura- external reference may also be used. tion. The differential current outputs may be fed into a transformer or tied directly to an output resistor to provide two complementary, 5. The current output(s) of the AD9774 can easily be configured single-ended voltage outputs. A differential op amp topology can for various single-ended or differential circuit topologies. also be used to obtain a single-ended output voltage. The output 6. On-chip clock multiplier generates all the high-speed clocks voltage compliance range is nominally 1.25 V. required by the internal interpolation filters. Both 2· and 4· clocks are generated from the lower rate data clock supplied TxDAC+ is a trademark of Analog Devices, Inc. by the user. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: http://www.analog.com otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 1998 AD9774–SPECIFICATIONS DC SPECIFICATIONS (T to T , AVDD = +5 V, PLLVDD = +5 V, DVDD = +5 V, I = 20 mA, unless otherwise noted) MIN MAX OUTFS Parameter Min Typ Max Units RESOLUTION 14 Bits 1 DC ACCURACY Integral Linearity Error (INL) T = +25°C–4 LSB A T to T MIN MAX Differential Nonlinearity (DNL) T = +25°C–3 LSB A T to T MIN MAX Monotonicity (12-Bit) GUARANTEED OVER RATED SPECIFICATION TEMPERATURE RANGE ANALOG OUTPUT Offset Error –0.025 +0.025 % of FSR Gain Error (Without Internal Reference) –7–1 +7 % of FSR Gain Error (With Internal Reference) +7.5–1 +7.5 % of FSR 2 Full-Scale Output Current 20 mA Output Compliance Range 1.25 V Output Resistance 100 kW Output Capacitance 5 pF REFERENCE OUTPUT Reference Voltage 1.14 1.20 1.26 V 3 Reference Output Current 1mA REFERENCE INPUT Input Compliance Range 0.1 1.25 V Reference Input Resistance 1 MW TEMPERATURE COEFFICIENTS Unipolar Offset Drift 0 ppm of FSR/°C Gain Drift (Without Internal Reference)–50 ppm of FSR/°C Gain Drift (With Internal Reference)–100 ppm of FSR/°C Reference Voltage Drift–100 ppm of FSR/°C POWER SUPPLY AVDD 4 Voltage Range 2.7 5.0 5.5 V Analog Supply Current (I ) 26.5 32 mA AVDD Analog Supply Current in SLEEP Mode (I ) 3.2 5 mA AVDD PLLVDD Voltage Range 2.7 5.0 5.5 V Clock Multiplier Supply Current (I)1317 mA PLLVDD DVDD Voltage Range 2.7 5.0 5.5 V 5 Digital Supply Current at 5 V (I ) 123.0 140.0 mA DVDD Digital Supply Current at 5 V in SNOOZE Mode (I ) 42.0 50.0 mA DVDD 5 Digital Supply Current at 3 V (I ) 62.0 mA DVDD Nominal Power Dissipation 6 AVDD and DVDD at 3 V 415 mW 6 AVDD and DVDD at 5 V 1125 mW 7 Power Supply Rejection Ratio (PSRR) – AVDD –0.2 +0.2 % of FSR/V 7 Power Supply Rejection Ratio (PSRR) – PLLVDD –0.025 +0.025 % of FSR/V 7 Power Supply Rejection Ratio (PSRR) – DVDD –0.025 +0.025 % of FSR/V OPERATING RANGE –40 +85 °C NOTES 1 Measured at IOUTA driving a virtual ground. 2 Nominal full-scale current, IOUTFS, is 32 · the I current. REF 3 Use an external amplifier to drive any external load. 4 For operation below 3 V, it is recommended that the output current be reduced to 12 mA or less to maintain optimum performance. 5 Measured at f = 25 MSPS and f = 1.01 MHz. CLOCK OUT 6 Measured as unbuffered voltage output into 50W R at IOUTA and IOUTB, f = 32 MSPS and f = 12.8 MHz. LOAD CLOCK OUT 7 –5% power supply variation. Specifications subject to change without notice. –2– REV. B AD9774 (T to T , AVDD = +5 V, PLLVDD = +5 V, DVDD = +5 V, I = 20 mA, Differential Transformer MIN MAX OUTFS DYNAMIC SPECIFICATIONS Coupled Output, 50 V Doubly Terminated, unless otherwise noted) Parameter Min Typ Max Units DYNAMIC PERFORMANCE Maximum Output Update Rate w/DVDD = 5 V 128 MSPS Maximum Output Update Rate w/DVDD = 3 V 100 128 MSPS Output Settling Time (t ) (to 0.025%) 35 ns ST 1 Output Propagation Delay (t ) 55 Clocks PD Glitch Impulse 5 pV-s 1 Output Rise Time (10% to 90%) 2.5 ns 1 Output Fall Time (10% to 90%) 2.5 ns 2 Output Noise (I = 20 mA) 50 pA/√Hz OUTFS AC LINEARITY TO NYQUIST Spurious-Free Dynamic Range (SFDR) to Nyquist f = 25 MSPS; f = 1.01 MHz CLOCK OUT 0 dBFS Output 79 dB –6 dBFS Output 86 dB –12 dBFS Output 75 dB –18 dBFS Output 75 dB f = 32 MSPS; f = 1.01 MHz 78 dB CLOCK OUT f = 32 MSPS; f = 5.01 MHz 77 dB CLOCK OUT f = 32 MSPS; f = 10.01 MHz 79 dB CLOCK OUT f = 32 MSPS; f = 13.01 MHz 78 dB CLOCK OUT Total Harmonic Distortion (THD) f = 25 MSPS; f = 1.01 MHz; 0 dBFS –75 dB CLOCK OUT Signal-to-Noise Ratio (SNR) f = 25 MSPS; f = 1.01 MHz; 0 dBFS 76 dB CLOCK OUT NOTES 1 Propagation delay is delay from data input to DAC update. 2 Measured single-ended into 50W load. Specifications subject to change without notice. (T to T , AVDD = +5 V, PLLVDD = +5 V, DVDD = +5 V, I = 20 mA unless otherwise noted) DIGITAL SPECIFICATIONS MIN MAX OUTFS Parameter Min Typ Max Units DIGITAL INPUTS Logic “1” Voltage @ DVDD = +5 V 3.5 5 V Logic “1” Voltage @ DVDD = +3 V 2.1 3 V Logic “0” Voltage @ DVDD = +5 V 0 1.3 V Logic “0” Voltage @ DVDD = +3 V 0 0.9 V Logic “1” Current –10 +10mA Logic “0” Current –10 +10mA Input Capacitance 5 pF ) 2.5 ns Input Setup Time (t S Input Hold Time (t ) 1.5 ns H Latch Pulsewidth (t)4 ns LPW DB0–DB11 t t S H CLOCK t LPW t PD t ST IOUTA OR 0.025% IOUTB 0.025% Figure 1. Timing Diagram REV. B –3– AD9774–SPECIFICATIONS (T to T , AVDD = +2.7 V to +5.5 V, DVDD = +2.7 V to +5.5 V, I = 20 mA unless MIN MAX OUTFS DIGITAL FILTER SPECIFICATIONS otherwise noted) Parameter Min Typ Max Units MAXIMUM INPUT CLOCK RATE (f ) CLOCK DVDD = 5 V 32 MSPS DVDD = 3 V 25 32 MSPS DIGITAL FILTER CHARACTERISTICS 1 Passband Width : 0.005 dB 0.410 f /f OUT CLOCK Passband Width: 0.01 dB 0.414 f /f OUT CLOCK Passband Width: 0.1 dB 0.420 f /f OUT CLOCK Passband Width: –3 dB 0.482 f /f OUT CLOCK LINEAR PHASE (FIR IMPLEMENTATION) STOPBAND REJECTION 0.591 f to 3.419 f –69.5 dB CLOCK CLOCK 0.591 f to 1.409 f –79.5 dB CLOCK CLOCK 2 GROUP DELAY 38 Input Clocks IMPULSE RESPONSE DURATION –40 dB 53 Input Clocks –60 dB 62 Input Clocks NOTES 1 Excludes sinx/x characteristic of DAC. 2 Defined as the number of data clock cycles between impulse input and peak of output response. Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS* ORDERING GUIDE With Temperature Package Package Respect Model Range Description Option* Parameter to Min Max Units AD9774AS –40°C to +85°C 44-Lead MQFP S-44 AVDD ACOM –0.3 +6.5 V AD9774EB Evaluation Board DVDD DCOM –0.3 +6.5 V *S = Metric Quad Flatpack. PLLVDD PLLCOM –0.3 +6.5 V ACOM DCOM –0.3 +0.3 V THERMAL CHARACTERISTIC PLLCOM ACOM –0.3 +0.3 V Thermal Resistance PLLCOM DCOM –0.3 +0.3 V 44-Lead MQFP AVDD DVDD –6.5 +6.5 V q = 53.2°C/W JA PLLVDD DVDD –0.3 +6.5 V q = 19°C/W JC PLLVDD AVDD –0.3 +6.5 V CLKIN, CLK4·IN DVDD –0.3 +6.5 V SLEEP, SNOOZE DCOM –0.3 DVDD + 0.3 V Digital Inputs DCOM –0.3 DVDD + 0.3 V PLL DIVIDE, LPF ACOM –0.3 PLLVDD + 0.3 V PLLLOCK ACOM –0.3 PLLVDD + 0.3 V VCO IN/EXT ACOM –0.3 PLLVDD + 0.3 V IOUTA/IOUTB ACOM –0.3 AVDD + 0.3 V REFIO, FSADJ ACOM –0.3 AVDD + 0.3 V FSADJ ACOM –0.3 AVDD + 0.3 V ICOMP ACOM –0.3 AVDD + 0.3 V REFCOM ACOM –0.3 +0.3 V Junction Temperature +150 °C Storage Temperature –65 +150 °C Lead Temperature +300 °C (10 sec) *Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may effect device reliability. –4– REV. B AD9774 0 Table I. Integer Filter Coefficients for First Stage Interpola- tion Filter (55-Tap Halfband FIR Filter) –20 –40 Lower Upper Integer Coefficient Coefficient Value –60 H(1) H(55) –1 –80 H(2) H(54) 0 –100 H(3) H(53) 3 H(4) H(52) 0 –120 H(5) H(51) –7 –140 H(6) H(50) 0 H(7) H(49) 15 –160 H(8) H(48) 0 –180 0 0.5 1.0 2.0 H(9) H(47) –28 1.5 FREQUENCY – DC TO 23 f H(10) H(46) 0 CLOCK H(11) H(45) 49 Figure 2a. FIR Filter Frequency Response H(12) H(44) 0 H(13) H(43) –81 H(14) H(42) 0 1.0 H(15) H(41) 128 H(16) H(40) 0 0.8 H(17) H(39) –196 H(18) H(38) 0 0.6 H(19) H(37) 295 0.4 H(20) H(36) 0 H(21) H(35) –447 0.2 H(22) H(34) 0 H(23) H(33) 706 0.0 H(24) H(32) 0 H(25) H(31) –1274 –0.2 H(26) H(30) 0 H(27) H(29) 3976 –0.4 0 10 20 30 40 50 60 70 80 H(28) 6276 TIME – Samples Figure 2b. FIR Filter Impulse Response Table II. Integer Filter Coefficients for Second Stage Inter- polation Filter (23-Tap Halfband FIR Filter) Lower Upper Integer Coefficient Coefficient Value H(1) H(23) –6 H(2) H(22) 0 H(3) H(21) 37 H(4) H(20) 0 H(5) H(19) –125 H(6) H(18) 0 H(7) H(17) 316 H(8) H(16) 0 H(9) H(15) –736 H(10) H(14) 0 H(11) H(13) 2562 H(12) 4096 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD9774 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD ESD SENSITIVE DEVICE precautions are recommended to avoid performance degradation or loss of functionality. REV. B –5– OUTPUT – dBFS NORMALIZED OUTPUT AD9774 PIN FUNCTION DESCRIPTIONS Pin No. Name Description 1, 19, 40, 44 DCOM Digital Common. 2 DB13 Most Significant Data Bit (MSB). 3–14 DB12–DB1 Data Bits 1–12. 15 DB0 Least Significant Data Bit (LSB). 16, 17, 42 NC No Internal Connection. 18, 41 DVDD Digital Supply Voltage (+2.7 V to +5.5 V). 20 CLK IN/OUT Clock Input when PLL Clock Multiplier enabled. Clock Output when PLL Clock Multiplier disabled. Data latched on rising edge. 21 PLLLOCK Phase Lock Loop Lock Signal. Active High indicates PLL is locked to input clock. 22 CLK4·IN External 4· Clock Input when PLL is disabled. No Connect when internal PLL is active. 23 PLLDIVIDE PLL Range Control Pin. Connect to PLLCOM if CLKIN is above 10 MSPS. Connect to PLLVDD if CLKIN is between 10 MSPS and 5.5 MSPS. 24 VCO IN/EXT Internal Voltage Controlled Oscillator (VCO) Enable/Disable Pin. Connect to PLLVDD to enable VCO. Connect to PLLCOM to disable VCO and drive CLK4·IN with external VCO output. 25 LPF PLL Loop Filter Node. Connect to external VCO control input if internal VCO disabled. 26 PLLVDD Phase Lock Loop (PLL) Supply Voltage (+2.7 V to +5.5 V). Must be set to similar voltage as DVDD. 27 PLLCOM Phase Lock Loop Common. 28 PLLENABLE Phase Lock Loop Enable. Connect to PLLVDD to enable. Connect to PLLCOM to disable. 29 UNUSED Factory Test. Leave Open. 30 REFLO Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal reference. 31 REFIO Reference Input/Output. Serves as reference input when internal reference disabled (i.e., tie REFLO to AVDD). Serves as 1.2 V reference output when internal reference activated (i.e., tie REFLO to ACOM). Requires 0.1 mF capacitor to ACOM when internal reference activated. 32 FSADJ Full-Scale Current Output Adjust. 33 REFCOMP Noise Reduction Node. Add 0.1 mF to AVDD. 34 ACOM Analog Common. 35 AVDD Analog Supply Voltage (+2.7 V to +5.5 V). 36 IOUTB Complementary DAC Current Output. Full-scale current when all data bits are 0s. 37 IOUTA DAC Current Output. Full-scale current when all data bits are 1s. 38 ICOMP Internal bias node for switch driver circuitry. Decouple to ACOM with 0.1 mF capacitor. 39 SLEEP Power-Down Control Input. Active High. Connect to DCOM if not used. 43 SNOOZE SNOOZE Control Input. Deactivates 4· interpolation filter to reduce digital power consumption only. Active High. Connect to DCOM if not used. PIN CONFIGURATION 44 43 42 41 40 39 38 37 36 35 34 DCOM 1 33 REFCOMP PIN 1 IDENTIFIER 32 DB13 2 FSADJ DB12 3 31 REFIO 30 DB11 4 REFLO DB10 5 29 UNUSED AD9774 28 DB9 6 TOP VIEW PLLENABLE (Not to Scale) DB8 7 27 PLLCOM 26 DB7 8 PLLVDD DB6 9 25 LPF DB5 10 24 VCO IN/EXT DB4 11 23 PLLDIVIDE 12 13 14 15 16 17 18 19 20 21 22 NC = NO CONNECT –6– REV. B DB3 DCOM DB2 SNOOZE DB1 NC DB0 DVDD NC DCOM NC SLEEP DVDD ICOMP IOUTA DCOM CLK IN/OUT IOUTB PLLLOCK AVDD CLK43IN ACOM TEKTRONIX AWG-2021 OPTION 4 AD9774 DEFINITIONS OF SPECIFICATIONS Settling Time Linearity Error (Also Called Integral Nonlinearity or INL) The time required for the output to reach and remain within a Linearity error is defined as the maximum deviation of the actual specified error band about its final value, measured from the analog output from the ideal output, determined by a straight start of the output transition. line drawn from zero to full scale. Glitch Impulse Differential Nonlinearity (or DNL) Asymmetrical switching times in a DAC give rise to undesired DNL is the measure of the variation in analog value, normalized output transients that are quantified by a glitch impulse. It is to full scale, associated with a 1 LSB change in digital input code. specified the net area of the glitch in pV-s. Monotonicity Spurious-Free Dynamic Range A D/A converter is monotonic if the output either increases or The difference, in dB, between the rms amplitude of the output remains constant as the digital input increases. signal and the peak spurious signal over the specified bandwidth. Offset Error Total Harmonic Distortion The deviation of the output current from the ideal of zero is THD is the ratio of the rms sum of the first six harmonic com- called offset error. For IOUTA, 0 mA output is expected when ponents to the rms value of the measured input signal. It is the inputs are all 0s. For IOUTB, 0 mA output is expected expressed as a percentage or in decibels (dB). when all inputs are set to 1s. Signal-to-Noise Ratio (SNR) Gain Error S/N is the ratio of the rms value of the measured output signal The difference between the actual and ideal output span. The to the rms sum of all other spectral components below the actual span is determined by the output when all inputs are set Nyquist frequency, excluding the first six harmonics and dc. to 1s, minus the output when all inputs are set to 0s. The value for SNR is expressed in decibels. Output Compliance Range Passband The range of allowable voltage at the output of a current-output Frequency band in which any input applied therein passes DAC. Operation beyond the maximum compliance limits may unattenuated to the DAC output. cause either output stage saturation or breakdown, resulting in Stopband Rejection nonlinear performance. The amount of attenuation of a frequency outside the passband Temperature Drift applied to the DAC, relative to a full-scale signal applied at the Temperature drift is specified as the maximum change from the DAC input within the passband. ambient (+25°C) value to the value at either T or T . For MIN MAX Group Delay offset and gain drift, the drift is reported in ppm of full-scale Number of input clocks between an impulse applied at the range (FSR) per degree C. For reference drift, the drift is re- device input and peak DAC output current. ported in ppm per degree C. Impulse Response Power Supply Rejection Response of the device to an impulse applied to the input. The maximum change in the full-scale output as the supplies are varied from nominal to minimum and maximum specified voltages. +3V D CLK43IN PLLLOCK PLL VCO PLL CLK ENABLE PLLCOM TO HP3589A IN/EXT DIVIDE IN/OUT SPECTRUM / NETWORK LPF PLL CLOCK ANALYZER MULTIPLIER 50V INPUT 1.5kV 0.01mF MINI-CIRCUITS 13 23 43 +3V PLLVDD D 43 T1-1T IOUTA 14 14 14 EDGE DIGITAL TRIGGERED 14-BIT DAC 100V DATA 23 23 IOUTB LATCHES 14 0.1mF 50V 50V REFIO SNOOZE 20pF 20pF +1.2V REFERENCE AD9774 AND CONTROL AMP SLEEP FSADJ DCOM DVDD ICOMP ACOM AVDD REFCOMP REFLO 1.91kV 0.1mF 0.1mF +3V +5V D A Figure 3. Basic AC Characterization Test Setup REV. B –7– AD9774 Typical AC Characterization Curves (AVDD = +5 V, PLLVDD = +3 V, DVDD = +3 V, I = 20 mA, 50 V Doubly Terminated Load, Differential Output, T = +258C, unless otherwise OUTFS A noted. Note: PLLVDD = +5 V and DVDD = +5 V for Figures 4, 5 and 6.) “INBAND” 10 90 85 0 80 85 –10 75 0dBFS –20 70 80 –6dBFS –30 65 –40 75 0dBFS 60 –12dBFS –50 55 –6dBFS 70 –60 50 –12dBFS –18dBFS –70 45 65 –18dBFS –80 40 –90 60 35 0 25.6 51.2 76.8 102.4 128.0 02 468 10 12 14 0 21 4 6 8 10 124 MHz f – MHz f – MHz OUT OUT Figure 5. “Inband” SFDR vs. f Figure 4. Single Tone Spectral Plot Figure 6. “Out-of-Band” SFDR vs. f OUT OUT @ 32 MSPS (DC to CLKIN/2) @ 32 MSPS w/f = 12.8 MHz (DC to @ 32 MSPS (CLKIN/2 to 3 1/2 CLKIN) OUT 4 · CLKIN) “INBAND” 10 85 90 0 80 85 –10 75 0dBFS –20 70 80 –30 65 –6dBFS –6dBFS –40 75 60 –12dBFS –12dBFS –50 0dBFS 55 –18dBFS 70 –60 50 –18dBFS –70 45 65 –80 40 –90 60 35 0 0 0 12.8 25.6 38.4 51.2 64.0 17 23456 17 23456 MHz f – MHz f – MHz OUT OUT Figure 7. Single Tone Spectral Plot Figure 8. “Inband” SFDR vs. f Figure 9. “Out-of-Band” SFDR vs. OUT @ 16 MSPS w/f = 6.4 MHz (DC to @ 16 MSPS (DC to CLKIN/2) f @ 16 MSPS (CLKIN/2 to 3 1/2 OUT OUT 4 · CLKIN) CLKIN) 10 90 85 –6dBFS 0 80 0dBFS 85 –10 75 0dBFS –20 70 –12dBFS 80 –30 –6dBFS 65 –18dBFS –40 75 60 –50 55 –12dBFS 70 –60 50 –18dBFS –70 45 65 –80 40 –90 60 35 0 0 6.4 12.8 19.2 25.6 32.0 0.5 1 1.5 2 2.5 3 3.5 0 0.5 1 1.5 2 2.5 3 3.5 MHz f – MHz OUT f – MHz OUT Figure 10. Single Tone Spectral Plot Figure 11. “Inband” SFDR vs. f Figure 12. “Out-of-Band” SFDR vs. OUT f @ 8 MSPS w/f = 3.2 MHz (DC @ 8 MSPS (DC to CLKIN/2) f @ 8 MSPS (CLKIN/2 to 3 1/2 OUT OUT OUT to 4 · CLKIN) CLKIN) REV. B –8– 10dB – DIV 10dB – DIV 10dB – DIV SFDR – dBc SFDR – dBc SFDR – dBc SFDR – dBc SFDR – dBc SFDR – dBc AD9774 10 85 90 0 80 0dBFS 85 –10 75 –20 70 –6dBFS 80 0dBFS –30 65 –12dBFS –6dBFS –40 75 60 –18dBFS –50 55 –12dBFS 70 –60 50 –18dBFS –70 45 65 –80 40 60 –90 35 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.2 0.3 0.4 0.5 0.6 0.7 0.8 MHz f – MHz f – MHz OUT OUT Figure 13. Single Tone Spectral Plot Figure 14. “Inband” SFDR vs. f Figure 15. “Out-of-Band” SFDR OUT @ 2 MSPS w/f = 800 kHz (DC to @ 2 MSPS (DC to CLKIN/2) vs. f @ 2 MSPS (CLKIN/2 to OUT OUT 4 · CLKIN) 3 1/2 CLKIN) 90 85 80 80 85 75 363kHz @ 4MSPS 2.9MHz @ 32MSPS 75 70 727kHz @ 8MSPS 80 DVDD = 3.3V 727kHz @ 8MSPS 65 1.45MHz @ 16MSPS DVDD = 5.0V 60 70 75 55 70 50 363kHz @ 4MSPS 2.9MHz @ 32MSPS 65 1.45MHz @ 16MSPS 45 65 40 60 35 60 –18 –16 –14 –12 –10 –8 –6 –4 –2 0 0 10 20 30 –18 –16 –14 –12 –10 –8 –6 –4 –2 A – dBFS A – dBFS f – MSPS IN IN CLK Figure 16. “In-Band” Single Tone Figure 17. Out-of-Band Single Tone Figure 18. SNR vs. f @ f = CLKIN OUT SFDR vs. A @ f = f /7 SFDR vs. A @ f = f /7 2 MHz (DC to CLKIN/2) IN OUT CLOCK IN OUT CLOCK (DC to CLKIN/2) (DC to 3 1/2 CLKIN) 85 –10 80 2.8/3.2MHz @ 8MSPS –20 11.2/12.8MHz @ 32MSPS 80 75 1.4/1.6MHz @ 4MSPS –30 75 –40 70 70 2.8/3.2MHz @ 8MSPS –50 65 5.6/6.4MHz @ 16MSPS 65 60 –60 5.6/6.4MHz @ 16MSPS –70 55 1.4/1.6MHz @ 4MSPS 60 11.2/12.8MHz @ 32MSPS 50 –80 –90 45 55 40 –100 35 –110 50 0 0 0 25.6 51.2 76.8 102.4 128.0 –18 –16 –14 –12 –10 –8 –6 –4 –2 –18 –16 –14 –12 –10 –8 –6 –4 –2 A – dBFS A – dBFS OUT OUT Figure 19. “In-Band” Two Tone Figure 20. “Out-of-Band” Two Tone Figure 21. Multitone Spectral Plot SFDR vs. A @ f = f /2.7 SFDR vs. A @ f = f /2.7 @ 32 MSPS (DC to 4 · CLKIN) OUT OUT CLOCK OUT OUT CLOCK (DC to CLKIN/2) (DC to 3 1/2 CLKIN) REV. B –9– 10dB – DIV SFDR – dBc SFDR – dBc SFDR – dBc SFDR – dBc SFDR – dBc 10dB – DIV SFDR – dBc SNR – dB AD9774 FUNCTIONAL DESCRIPTION coefficients for each of the filter stages. The interpolation filters Figure 22 shows a simplified block diagram of the AD9774. The essentially multiply the input data rate to the DAC by a factor of AD9774 is a complete, 4· oversampling, 14-bit DAC that in- four relative to its original input data rate while simultaneously cludes two cascaded 2· interpolation filters, a phase-locked loop reducing the magnitude of the images associated with the origi- (PLL) clock multiplier, and a 1.20 Volt bandgap voltage refer- nal input data rate. ence. The 14-bit DAC provides two complementary current The benefits of an interpolation filter are clearly seen in Figure outputs whose full-scale current is determined by an external 23, which shows an example of the frequency and time domain resistor. Input data that is latched into the edge-triggered input representation of a discrete time sine wave signal before and latches is first interpolated by a factor of four by the interpolation after it is applied to a digital interpolation filter. Images of the filters before updating the 14-bit DAC. A PLL clock multiplier sine wave signal appear around multiples of the DAC’s input produces the necessary internally synchronized 1·, 2· and 4· data rate as predicted by sampling theory. These undesirable clocks from an external reference. The AD9774 can support images will also appear at the output of a reconstruction DAC, input data rates as high as 32 MSPS, corresponding to a DAC although modified by the DAC’s sin(x)/(x) roll-off response. update rate of 128 MSPS. In many bandlimited applications, these images must be sup- The analog and digital sections of the AD9774 have separate pressed by an analog filter following the DAC. The complexity power supply inputs (i.e., AVDD and DVDD) that can operate of this analog filter is typically determined by the proximity of over a 2.7 V to 5.5 V range. A separate supply input (i.e., the desired fundamental to the first image and the required PLLVDD) having a similar operating range is also provided for amount of image suppression. Adding to the complexity of this the PLL clock multiplier. To maintain optimum noise and dis- analog filter may be the requirement of compensating for the tortion performance, PLLVDD should be maintained at the DAC’s sin(x)/x response. same voltage level as DVDD. Referring to Figure 23, the “new” first image associated with the DAC’s higher data rate after interpolation is “pushed” out fur- PLL PLL VCO ENABLE IN/EXT DIVIDE CLK43IN PLLLOCK ther relative to the input signal. The “old” first image associated with the lower DAC data rate before interpolation is suppressed PLLCOM AD9774 by the digital filter. As a result, the transition band for the ana- LPF PLL CLOCK log reconstruction filter is increased, thus reducing the complex- CLK IN/OUT MULTIPLIER ity of the analog filter. Furthermore, the sin(x)/x roll-off over the 13 23 43 PLLVDD effective passband (i.e., dc to f /2) is significantly reduced. CLOCK 43 14 14 14 14 DATA EDGE IOUTA The AD9774 includes a PLL clock multiplier that produces the 14-BIT INPUTS TRIGGERED 23 DAC 23 LATCHES IOUTB (DB13–DB0) necessary internally synchronized 1·, 2· and 4· clocks for the edge triggered latches, interpolation filters and DACs. The SNOOZE REFIO PLL clock multiplier typically accepts an input data clock, +1.2V REFERENCE SLEEP AND CONTROL AMP FSADJ CLK IN/OUT, as its reference source. Alternatively, it can also be configured using an external 4· clock via CLK4·IN. The DCOM DVDD ICOMP ACOM AVDD REFCOMP REFLO PLLDIVIDE, VCO IN/EXT, PLLENABLE, and PLLLOCK Figure 22. Functional Block Diagram are control inputs/outputs used in the PLL clock generator. Refer to the PLL CLOCK MULTIPLIER OPERATION sec- Preceding the 14-bit DAC are two cascaded 2· digital interpola- tion for a detailed discussion on its operation. tion filter stages based on a 55- and 23-tap halfband symmetric FIR topology. Edge triggered latches are used to latch the input The digital section of the AD9774 also includes several other data on the rising edge of CLK IN/OUT. The composite fre- control inputs and outputs. The SLEEP and SNOOZE inputs quency and impulse response of both filters are shown in Fig- provide different power-saving modes as discussed in the ures 2a and 2b. Table I and Table II list the idealized filter SLEEP and SNOOZE section. 1 4f CLOCK TIME DOMAIN 1 f CLOCK ST FUNDAMENTAL 1 IMAGE FUNDAMENTAL "NEW" "SINX" DIGITAL DACs 1ST IMAGE FILTER X FREQUENCY DOMAIN SUPPRESSED 2f 4f 2f 4f 2f 4f CLOCK CLOCK CLOCK CLOCK CLOCK CLOCK "OLD" ST 1 IMAGE 4x INTERPOLATION FILTER INPUT DATA LATCH DAC 4x f CLOCK 43f CLOCK Figure 23. Time and Frequency Domain Example of Digital Interpolation Filter –10– REV. B AD9774 PLL CLOCK MULTIPLIER OPERATION There are two cases in which a user may consider or be required The Phase Lock Loop (PLL) Clock Multiplier is intrinsic to the to disable the internal PLL Clock Multiplier and supply the operation of the AD9774 in that it produces the necessary inter- AD9774 with an external 4· system clock. Applications already nally synchronized 1·, 2· and 4· clocks for the edge triggered containing a system clock operating at four (i.e., 4·) the input latches, interpolation filters and DACs. Figure 24 shows a func- data rate may consider using it as the master clock source. Ap- tional block diagram of the PLL Clock Multiplier, which con- plications with input data rates less than 5.5 MSPS must use a sists of a phase detector, a charge pump, a voltage controlled master 4· clock. oscillator (VCO), a divide-by-N circuit and some control inputs/ In any of these cases, the clock source is applied to CLK4·IN outputs. It produces the required internal clocks for the AD9774 and the PLL is partially disabled by typing PLLENABLE and by using one of two possible externally applied reference clock VCO IN/EXT to PLLCOM as shown in Figure 25. LPF may sources applied to either CLKIN or CLK4·IN. PLLENABLE remain open since this portion of the PLL circuitry is disabled. and VCO IN/EXT are active HIGH control inputs used to The divide-by-N circuit still remains enabled providing a 1· or enable the charge pump and VCO respectively. 2· internal clock at CLOCK IN/OUT depending on the state of To maintain optimum noise and distortion performance, PLLDIVIDE. Since the digital input data is latched into the PLLVDD and DVDD should be set to similar voltage levels. If AD9774 on the rising edge of the 1· clock, PLLDIVIDE should a separate supply cannot be provided for PLLVDD, PLLVDD be tied to PLLCOM such that the 1· clock appears as an output can be tied to DVDD using an LC filter network similar to that at CLOCK IN/OUT. The input data should be stable 5 ns (i.e., shown in Figure 41. data set-up) before the rising edge of the 1· clock appearing at CLOCK IN/OUT and remain stable for 1 ns after the rising Many applications will select a reference clock operating at the edge (i.e., data hold) to ensure proper latching. Note, the rising data input rate as shown in Figure 24. In this case, the external edge of the 1· clock occurs approximately 9 ns to 15 ns relative clock source is applied to CLKIN and the PLL Clock Multiplier to the falling edge of the CLK4· input. If a data timing issue is fully enabled by tying PLLENABLE and VCO IN/EXT to exists between the AD9774 and its external driver device, the PLLVDD. Note, CLKIN must adhere to the timing require- CLK4· input can be inverted via an external gate to ensure ments shown in Figure 1. A 1.5 kW resistor and 0.01 mF ceramic proper set-up and hold time. capacitor connected in series from LPF to PLLVDD are re- quired to optimize the phase noise vs. settling/acquisition time characteristics of the PLL. PLLLOCK is a control output, ac- tive HIGH, which may be monitored upon system power-up to PLLLOCK indicate that the PLL is successfully “locked” to CLKIN. Note, PLL CLK PLL DIVIDE IN/OUT ENABLE applications employing multiple AD9774 devices will benefit from the PLL Clock Multiplier’s ability to ensure precise simul- PHASE CHARGE LPF taneous updating/phase synchronization of these devices when DETECTOR PUMP driven by the same input clock source. AD9774 PLLDIVIDE is used to preset the “lock-in” range of the PLL. It PLL 48 VDD should be tied to PLLCOM if CLKIN is greater than 10 MHz +2.7 TO +5.5 V D 44 VCO DIVIDE- PLL and to PLLVDD if CLKIN is between 5.5 MHz and 10 MHz. BY-N VCO 42 COM For operation below 5.5 MHz (i.e., input data rates less than 41 5.5 MSPS), the internal charge pump and VCO should be VCO CLK IN/EXT disabled by tying PLLENABLE and VCO IN/EXT LOW. In DCOM DVDD 43IN this case, the user MUST supply a system clock operating at 4· the input data rate as discussed below. +2.7 TO +5.5 V D Figure 25. Clock Divider with PLL Disabled CONNECT TO CONNECT TO PLLCOM PLLVDD CLK PLLLOCK IN/OUT DAC OPERATION PLL PLL The 14-bit DAC along with the 1.2 V reference and reference DIVIDE ENABLE control amplifier is shown in Figure 26. The DAC consists of a LPF large PMOS current source array capable of providing up to PHASE CHARGE DETECTOR PUMP 20 mA of full-scale current, I . The array is divided into 31 OUTFS 1.5kV equal currents which make up the five most significant bits AD9774 0.01mF (MSBs). The next four bits or middle bits consist of 15 equal PLL 48 VDD current sources whose values are 1/16th of an MSB current 44 VCO DIVIDE- +2.7 TO PLL source. The remaining LSBs are binary weighted fractions of the BY-N VCO 42 +5.5 V COM D 41 middle-bits current sources. All of these current sources are switched to one or the other of two output nodes (i.e., IOUTA CLK VCO DCOM DVDD 43IN IN/EXT or IOUTB) via PMOS differential current switches. Implement- ing the middle and lower bits with current sources, instead of an R-2R ladder, enhances its dynamic performance for multitone +2.7 TO +5.5 V D or low amplitude signals and helps maintain the DAC’s high output impedance (i.e., > 100 kW). Figure 24. Clock Multiplier with PLL Enabled REV. B –11– AD9774 +2.7 TO +5.5V A Substituting the values of IOUTA, IOUTB and I ; V can REF DIFF 0.1mF be expressed as: REFLO REFCOMP AVDD ACOM V = {(2 DAC CODE – 16383)/16384} ·DIFF 50pF V = {(32 R /R ) · V (8) DIFF LOAD SET REFIO 1.20V REF ICOMP 0.1mF CURRENT REFIO SOURCE These last two equations highlight some of the advantages of ARRAY operating the AD9774 differentially. First, the differential FS ADJ 1.91kV IOUTA operation will help cancel common-mode error sources associ- SEGMENTED LSB ated with IOUTA and IOUTB such as noise, distortion and dc SWITCHES SWITCHES IOUTB 0.1mF offsets. Second, the differential code-dependent current and AD9774 subsequent voltage, V , is twice the value of the single-ended DIFF voltage output (i.e., V or V ), thus providing twice the OUTA OUTB signal power to the load. Figure 26. Block Diagram of Internal DAC, 1.2 V Reference, and Reference Control Circuits Note that the gain drift temperature performance for a single- ended (VOUTA and VOUTB) or differential output (V ) of DIFF The full-scale output current is regulated by the reference con- the AD9774 can be enhanced by selecting temperature tracking trol amplifier and can be set from 2 mA to 20 mA via an exter- resistors for R and R due to their ratiometric relation- LOAD SET nal resistor, R . The external resistor,␣ in combination with SET ship as shown in Equation 8. both the reference control amplifier and voltage reference, REFIO, sets the reference current, I , which is mirrored over REF REFERENCE OPERATION to the segmented current sources with the proper scaling factor. The AD9774 contains an internal 1.20 V bandgap reference The full-scale current, I , is exactly thirty-two times the OUTFS that can be easily disabled and overridden by an external value of I . REF reference. REFIO serves as either an input or output, depending on whether the internal or external reference is selected. If DAC TRANSFER FUNCTION REFLO is tied to ACOM, as shown in Figure 27, the internal The AD9774 provides complementary current outputs, IOUTA reference is activated, and REFIO provides a 1.20 V output. In and IOUTB. IOUTA will provide a near full-scale current out- this case, the internal reference must be compensated externally put, I , when all bits are high (i.e., DAC CODE = 16383) OUTFS with a ceramic chip capacitor of 0.1mF or greater from REFIO while IOUTB, the complementary output, provides no current. to REFLO. If any additional loading is required, REFIO should The current output appearing at IOUTA and IOUTB is a func- be buffered with an external amplifier having an input bias cur- tion of both the input code and I and can be expressed as: OUTFS rent less than 100 nA. IOUTA = (DAC CODE/16384) · I (1) OUTFS +2.7 TO +5.5V A IOUTB = (16383 – DAC CODE)/16384 · I (2) OUTFS OPTIONAL where DAC CODE = 0 to 16383 (i.e., Decimal Representation). 0.1mF EXTERNAL REF BUFFER REFLO REFCOMP AVDD As previously mentioned, I is a function of the reference OUTFS +1.2V REF current I , which is nominally set by a reference voltage REF 50pF V and external resistor R . It can be expressed as: REFIO SET REFIO CURRENT ADDITIONAL SOURCE FSADJ I = 32 · I (3) OUTFS REF 0.1mF LOAD ARRAY 2kV where I = V /R (4) REF REFIO SET AD9774 The two current outputs will typically drive a resistive load directly or via a transformer. If dc coupling is required, IOUTA Figure 27. Internal Reference Configuration and IOUTB should be directly connected to matching resistive The internal reference can be disabled by connecting REFLO to loads, R , that are tied to analog common, ACOM. Note LOAD AVDD. In this case, an external reference may then be applied that R may represent the equivalent load resistance seen by LOAD to REFIO as shown in Figure 28. The external reference may IOUTA or IOUTB as would be the case in a doubly terminated provide either a fixed reference voltage to enhance accuracy and 50W or 75W cable. The single-ended voltage output appearing drift performance or a varying reference voltage for gain control. at the IOUTA and IOUTB nodes is simply: Note that the 0.1mF compensation capacitor is not required V = IOUTA · R (5) OUTA LOAD since the internal reference is disabled, and the high input im- pedance (i.e., 1 MW) of REFIO minimizes any loading of the V = IOUTB · R (6) OUTB LOAD external reference. Note that the full-scale value of V and V should not OUTA OUTB exceed the specified output compliance range to maintain speci- fied distortion and linearity performance. The differential voltage, V , appearing across IOUTA and DIFF IOUTB is: V = (IOUTA – IOUTB) · R (7) DIFF LOAD –12– REV. B AD9774 +2.7 TO +5.5V A varied by an external voltage, V , applied to R via an ampli- GC SET fier. An example of this method is shown in Figure 29 in which 0.1mF the internal reference is used to set the common-mode voltage REFCOMP of the control amplifier to 1.20 V. The external voltage, V , is GC REFLO AVDD AVDD referenced to ACOM and should not exceed 1.2 V. The value of +1.2V REF 50pF R is such that I and I do not exceed 62.5mA SET REFMAX REFMIN V REFIO REFIO and 625mA, respectively. The associated equations in Figure 29 EXTERNAL CURRENT REF SOURCE can be used to determine the value of R . FS ADJ SET ARRAY R I = SET REF +2.7 TO +5.5V A V /R REFERENCE REFIO SET AD9774 CONTROL AMPLIFIER 0.1mF REFLO REFCOMP AVDD Figure 28. External Reference Configuration +1.2V REF 50pF REFIO CURRENT REFERENCE CONTROL AMPLIFIER FSADJ SOURCE 1mF ARRAY The AD9774 also contains an internal control amplifier that is R SET I AD9774 REF used to regulate the DAC’s full-scale output current, I . OUTFS The control amplifier is configured as a V-I converter, as shown I = (1.2–V )/R REF GC SET V GC in Figure 28, such that its current output, I , is determined by REF WITH V , V AND 62.5 mA # I # 625A GC REFIO REF the ratio of the V and an external resistor, R , as stated REFIO SET Figure 29. Dual Supply Gain Control Circuit in Equation 4. I is copied over to the segmented current REF sources with the proper scaling factor to set I as stated in OUTFS ANALOG OUTPUTS Equation 3. The AD9774 produces two complementary current outputs, The control amplifier allows a wide (10:1) adjustment span of IOUTA and IOUTB, which may be configured for single-end or I over a 2 mA to 20 mA range by setting I between OUTFS REF differential operation. IOUTA and IOUTB can be converted 62.5mA and 625mA. The wide adjustment span of I OUTFS into complementary single-ended voltage outputs, V and OUTA provides several application benefits. The first benefit relates V , via a load resistor, R , as described in the DAC OUTB LOAD directly to the power dissipation of the AD9774, which is pro- Transfer Function section by Equations 5 through 8. The portional to I (refer to the Power Dissipation section). The OUTFS differential voltage, V , existing between V and V , DIFF OUTA OUTB second benefit relates to the 20 dB adjustment, which is useful can also be converted to a single-ended voltage via a transformer for system gain control purposes. or differential amplifier configuration. There are two methods by which I can be varied for a fixed REF Figure 31 shows the equivalent analog output circuit of the R . The first method is suitable for a single-supply system in SET AD9774 consisting of a parallel combination of PMOS differen- which the internal reference is disabled, and the common-mode tial current switches associated with each segmented current voltage of REFIO is varied over its compliance range of 1.25 V source. The output impedance of IOUTA and IOUTB is deter- to 0.10 V. REFIO can be driven by a single-supply amplifier or mined by the equivalent parallel combination of the PMOS DAC, thus allowing I to be varied for a fixed R . Since the REF SET switches and is typically 100 kW in parallel with 5 pF. Due to input impedance of REFIO is approximately 1 MW, a simple, the nature of a PMOS device, the output impedance is also low cost R-2R ladder DAC configured in the voltage mode slightly dependent on the output voltage (i.e., V and V ) OUTA OUTB topology may be used to control the gain. This circuit is shown and, to a lesser extent, the analog supply voltage, AVDD, and in Figure 30 using the AD7524 and an external 1.2 V reference, full-scale current, I . Although the output impedance’s OUTFS the AD1580. signal dependency can be a source of dc nonlinearity and ac linear- ity (i.e., distortion), its effects can be limited if certain precau- The second method may be used in a dual-supply system in tions are noted. which the common-mode voltage of REFIO is fixed, and I is REF +2.7 TO +5.5V A AVDD 0.1mF REFLO REFCOMP AVDD +1.2V REF R V FB DD 50pF 1.2V OUT1 0.1V TO 1.2V REFIO AD7524 V CURRENT REF OUT2 SOURCE FSADJ AD1580 ARRAY AGND R I = SET AD9774 REF V /R REF SET DB7–DB0 Figure 30. Single Supply Gain Control Circuit REV. B –13– AD9774 The distortion and noise performance of the AD9774 is also slightly dependent on the analog and digital supply as well as the AD9774 full-scale current setting, I . Operating the analog supply at OUTFS AVDD 5.0 V ensures maximum headroom for its internal PMOS current sources and differential switches leading to improved distortion performance. Although I can be set between 2 mA and OUTFS 20 mA, selecting an I of 20 mA will provide the best dis- OUTFS tortion and noise performance. The noise performance of the AD9774 is affected by the digital supply (DVDD), output fre- quency, and increases with increasing clock rate. Operating the IOUTA IOUTB AD9774 with low voltage logic levels between 3 V and 3.3 V will slightly reduce the amount of on-chip digital noise. R R LOAD LOAD In summary, the AD9774 achieves the optimum distortion and noise performance under the following conditions: Figure 31. Equivalent Analog Output Circuit (1) Differential Operation. IOUTA and IOUTB also have a negative and positive voltage (2) Positive voltage swing at IOUTA and IOUTB limited to compliance range. The negative output compliance range of +0.5 V. –1.0 V is set by the breakdown limits of the CMOS process. (3) IOUTFS set to 20 mA. Operation beyond this maximum limit may result in a break- down of the output stage and affect the reliability of the AD9774. (4) Analog Supply (AVDD) set at 5.0 V. The positive output compliance range is slightly dependent on (5) Digital Supply (DVDD) and Phase Lock Loop Supply the full-scale output current, I . It degrades slightly from its OUTFS (PLLVDD) set at 3.0 V to 3.3 V with appropriate logic nominal 1.25 V for an I = 20 mA to 1.00 V for an I = OUTFS OUTFS levels. 2 mA. Operation beyond the positive compliance range will induce clipping of the output signal, which severely degrades Note that the ac performance of the AD9774 is characterized the AD9774’s linearity and distortion performance. under the above-mentioned operating conditions. For applications requiring the optimum dc linearity, IOUTA DIGITAL INPUTS/OUTPUTS and/or IOUTB should be maintained at a virtual ground via an The digital input of the AD9774 consists of 14 data input pins I-V op amp configuration. Maintaining IOUTA and/or IOUTB and a clock input pin, and several control input pins. Since at a virtual ground keeps the output impedance of the AD9774 some of the internal logic is operated from DVDD and PLLVDD, fixed, significantly reducing its effect on linearity. However, it they must be set to the same or similar levels to ensure proper does not necessarily lead to the optimum distortion perfor- compatibility with any external logic/drivers. The two digital mance due to limitations of the I-V op amp. Note that the outputs of the AD9774, PLL LOCK and CLK OUT originate INL/DNL specifications for the AD9774 are measured in this from the internal PLL circuitry and thus its output logic levels manner using IOUTA. In addition, these dc linearity specifi- will be set by PLLVDD. cations remain virtually unaffected over the specified power supply range of 2.7 V to 5.5 V. The 14-bit parallel data inputs follow standard positive binary coding where DB13 is the most significant bit (MSB), and DB0 Operating the AD9774 with reduced voltage output swings at is the least significant bit (LSB). IOUTA produces a full-scale IOUTA and IOUTB in a differential or single-ended output output current when all data bits are at Logic 1. IOUTB pro- configuration reduces the signal dependency of its output im- duces a complementary output with the full-scale current split pedance thus enhancing distortion performance. Although the between the two outputs as a function of the input code. voltage compliance range of IOUTA and IOUTB extends from –1.0 V to +1.25 V, optimum distortion performance is achieved The digital interface is implemented using an edge-triggered when the maximum full-scale signal at IOUTA and IOUTB master slave latch and is designed to support a clock and input does not exceed approximately 0.5 V. A properly selected trans- data rate as high as 32 MSPS. The clock can be operated at any former with a grounded center-tap will allow the AD9774 to duty cycle that meets the specified latch pulsewidth as shown in provide the required power and voltage levels to different loads Figure 1. The setup and hold times can also be varied within the while maintaining reduced voltage swings at IOUTA and clock cycle as long as the specified minimum times are met. IOUTB. DC-coupled applications requiring a differential or The digital inputs are CMOS-compatible with logic thresholds, single-ended output configuration should size R accord- V set to approximately half the digital positive supply LOAD THRESHOLD, ingly. Refer to Applying the AD9774 section for examples of (i.e., DVDD or PLLVDD) or various output configurations. V = DVDD/2 (–20%) THRESHOLD The most significant improvement in the AD9774’s distortion The internal digital circuitry of the AD9774 is capable of operating and noise performance is realized using a differential output over a digital supply range of 2.7 V to 5.5 V. As a result, the configuration. The common-mode error sources of both IOUTA digital inputs can also accommodate TTL levels when DVDD is and IOUTB can be substantially reduced by the common-mode set to accommodate the maximum high level voltage of the TTL rejection of a transformer or differential amplifier. These drivers V . A DVDD of 3 V to 3.3 V will typically ensure OH(MAX) common-mode error sources include even-order distortion proper compatibility with most TTL logic families. Figure 32 products and noise. The enhancement in distortion performance shows the equivalent digital input circuit for the data and clock becomes more significant as the reconstructed waveform’s inputs. frequency content increases and/or its amplitude decreases. –14– REV. B AD9774 DVDD DVDD = 3 V, respectively. Note, how I is reduced by more DVDD than a factor of 2 when DVDD is reduced from 5 V to 3 V. DIGITAL 30 INPUT 25 20 Figure 32. Equivalent Digital Input 15 Since the AD9774 is capable of being updated up to 32 MSPS, the quality of the clock and data input signals are important in 10 achieving the optimum performance. Operating the AD9774 with reduced logic swings and a corresponding digital supply 5 (DVDD) will result in the lowest data feedthrough and on-chip digital noise. The drivers of the digital data interface circuitry 0 should be specified to meet the minimum setup and hold times 22 4 6 8 1012 1416180 of the AD9774 as well as its required min/max input logic level I – mA OUTFS thresholds. Figure 33. I vs. I AVDD OUTFS Digital signal paths should be kept short and run lengths matched to avoid propagation delay mismatch. The insertion of a low 200 value resistor network (i.e., 20W to 100W) between the AD9774 180 digital inputs and driver outputs may be helpful in reducing any 32MSPS overshooting and ringing at the digital inputs that contribute to 160 data feedthrough. 140 The external clock driver circuitry should provide the AD9774 120 with a low jitter clock input meeting the min/max logic levels 100 while providing fast edges. Fast clock edges will help minimize 16MSPS 80 any jitter that will manifest itself as phase noise on a recon- structed waveform. Thus, the clock input should be driven by 60 8MSPS the fastest logic family suitable for the application. 40 4MSPS 20 SLEEP AND SNOOZE MODE OPERATION 0 The AD9774 has a SLEEP function that turns off the output 0.01 0.10 1.0 current and reduces the supply current to less than 5 mA over RATIO – f /f OUT CLOCK the specified supply range of 2.7 V to 5.5 V and temperature Figure 34. I vs. Ratio @ DVDD = 5 V DVDD range. This mode can be activated by applying a logic level “1” to the SLEEP pin. The AD9774 takes less than 0.1ms to power down and approximately 6.4ms to power back up. 100 The SNOOZE mode should be considered as an alternative 90 32MSPS power-savings option if the power-up characteristics of the 80 SLEEP mode are unsuitable. This mode, which is also activated 70 by applying a logic level “1” to the SNOOZE pin, disables the 60 AD9774’s digital filters only, resulting in significant power savings. Both the SLEEP and SNOOZE pins should be tied to 50 DCOM if power savings is not required. 16MSPS 40 30 POWER DISSIPATION 20 The power dissipation, P , of the AD9774 is dependent on D 8MSPS several factors, including: (1) AVDD, PLLVDD, and DVDD, 10 4MSPS the power supply voltages; (2) I , the full-scale current OUTFS 0 0.01 output; (3) f , the update rate; and (4) the reconstructed 0.10 1.0 CLOCK RATIO – f /f OUT CLOCK digital input waveform. The power dissipation is directly pro- portional to the analog supply current, I , and the digital AVDD Figure 35. I vs. Ratio @ DVDD = 3 V DVDD supply current, I . I is directly proportional to I DVDD AVDD OUTFS, For those applications requiring the AD9774 to operate under the as shown in Figure 33, and is insensitive to f . CLOCK following conditions: (1) AVDD, PLLVDD and DVDD = +5 V; Conversely, I is dependent on both the digital input wave- DVDD (2) f > 25 MSPS; and (3) ambient temperatures > 70°C; CLOCK form, f , and digital supply DVDD. Figures 34 and 35 CLOCK proper thermal management via a heatsink or thermal epoxy is show I as a function of full-scale sine wave output ratios DVDD recommended. (f /f ) for various update rates with DVDD = 5 V and OUT CLOCK REV. B –15– I – mA I – mA I – mA AVDD DVDD DVDD AD9774 DIFFERENTIAL USING AN OP AMP APPLYING THE AD9774 An op amp can also be used to perform a differential-to-single- OUTPUT CONFIGURATIONS ended conversion as shown in Figure 37. The AD9774 is The following sections illustrate some typical output configura- configured with two equal load resistors, R , of 25 W. The tions for the AD9774. Unless otherwise noted, it is assumed LOAD differential voltage developed across IOUTA and IOUTB is that I is set to a nominal 20 mA. For applications requir- OUTFS converted to a single-ended signal via the differential op amp ing the optimum dynamic performance, a differential output configuration. An optional capacitor can be installed across configuration is suggested. A differential output configuration may consist of either an RF transformer or a differential op amp IOUTA and IOUTB, forming a real pole in a low-pass filter. The addition of this capacitor also enhances the op amp’s distor- configuration. The transformer configuration provides the opti- tion performance by preventing the DAC’s high slewing output mum high frequency performance and is recommended for any application allowing for ac coupling. The differential op amp from overloading the op amp’s input. configuration is suitable for applications requiring dc coupling, a 500V bipolar output, signal gain and/or level shifting. AD9774 A single-ended output is suitable for applications requiring a 225V 22 IOUTA unipolar voltage output. A positive unipolar output voltage will AD8055 result if IOUTA and/or IOUTB is connected to an approximately 225V 21 IOUTB sized load resistor, R , referred to ACOM. This configura- LOAD C OPT tion may be more suitable for a single-supply system requiring a 500V dc-coupled, ground referred output voltage. Alternatively, an 25V 25V amplifier could be configured as an I-V converter, thus convert- ing IOUTA or IOUTB into a negative unipolar voltage. This Figure 37. DC Differential Coupling Using an Op Amp configuration provides the best dc linearity since IOUTA or The common-mode rejection of this configuration is typically IOUTB is maintained at a virtual ground. determined by the resistor matching. In this circuit, the differ- ential op amp circuit using the AD8055 is configured to provide DIFFERENTIAL COUPLING USING A TRANSFORMER some additional signal gain. The op amp must operate from a An RF transformer can be used to perform a differential-to- single-ended signal conversion as shown in Figure 36. A dual supply since its output is approximately –1.0 V. A high speed amplifier capable of preserving the differential perform- differentially coupled transformer output provides the optimum ance of the AD9774 while meeting other system level objectives distortion performance for output signals whose spectral content lies within the transformer’s passband. An RF transformer such (i.e., cost, power) should be selected. The op amps differential gain, its gain setting resistor values and full-scale output swing as the Mini-Circuits T1-1T provides excellent rejection of capabilities should all be considered when optimizing this circuit. common-mode distortion (i.e., even-order harmonics) and noise over a wide frequency range. It also provides electrical isolation The differential circuit shown in Figure 38 provides the neces- and the ability to deliver twice the power to the load. Trans- sary level-shifting required in a single supply system. In this case, formers with different impedance ratios may also be used for AVDD, which is the positive analog supply for both the AD9774 impedance matching purposes. Note that the transformer and the op amp, is also used to level-shift the differential output provides ac coupling only. of the AD9774 to midsupply (i.e., AVDD/2). The AD8041 is a suitable op amp for this application. MINI-CIRCUITS T1-1T 22 IOUTA 500 R AD9774 LOAD AD9774 225 22 IOUTA 21 IOUTB AD8041 OPTIONAL R DIFF 225 21 IOUTB C OPT 1k AVDD Figure 36. Differential Output Using a Transformer 25 25 1k The center tap on the primary side of the transformer must be connected to ACOM to provide the necessary dc current path for both IOUTA and IOUTB. The complementary voltages Figure 38. Single-Supply DC Differential Coupled Circuit appearing at IOUTA and IOUTB (i.e., V and V ) OUTA OUTB swing symmetrically around ACOM and should be maintained SINGLE-ENDED UNBUFFERED VOLTAGE OUTPUT with the specified output compliance range of the AD9774. A Figure 39 shows the AD9774 configured to provide a unipolar differential resistor, R , may be inserted in applications in DIFF output range of approximately 0 V to +0.5 V for a doubly termi- which the output of the transformer is connected to the load, nated 50W cable since the nominal full-scale current, I , of OUTFS R , via a passive reconstruction filter or cable. R is deter- LOAD DIFF 20 mA flows through the equivalent R of 25W. In this case, LOAD mined by the transformer’s impedance ratio and provides the R represents the equivalent load resistance seen by IOUTA. LOAD proper source termination that results in a low VSWR. Note that The unused output (IOUTB) can be connected to ACOM di- approximately half the signal power will be dissipated across R . DIFF rectly. Different values of I and R can be selected as OUTFS LOAD –16– REV. B AD9774 to ACOM, the analog common, as close to the chip as physi- long as the positive compliance range is adhered to. One addi- cally possible. Similarly, DVDD, the digital supply, should be tional consideration in this mode is the integral nonlinearity decoupled to DCOM and PLLVDD, the Phase Lock Loop (INL) as discussed in the Analog Output section of this data Supply, should be decoupled to PLLCOM. sheet. For optimum INL performance, the single-ended, buff- ered voltage output configuration is suggested. For those applications requiring a single +5 V or +3 V supply for both the analog, digital supply and Phase Lock Loop supply, a clean AVDD and/or PLLVDD may be generated using the AD9774 I = 20mA OUTFS V = 0 TO +0.5V OUTA circuit shown in Figure 41. The circuit consists of a differential IOUTA 22 LC filter with separate power supply and return lines. Lower 50V 50V noise can be attained using low ESR type electrolytic and tanta- IOUTB 21 lum capacitors. FERRITE BEADS Figure 39. 0 V to +0.5 V Unbuffered Voltage Output TTL/CMOS AVDD LOGIC 100mF 10-22mF 0.1mF CIRCUITS ELECT. TANT. CER. SINGLE-ENDED BUFFERED VOLTAGE OUTPUT ACOM CONFIGURATION Figure 40 shows a buffered single-ended output configuration in which the op amp U1 performs an I-V conversion on the AD9774 +5V OR +3V output current. U1 maintains IOUTA (or IOUTB) at a virtual POWER SUPPLY ground, thus minimizing the nonlinear output impedance effect on the DAC’s INL performance as discussed in the Analog Figure 41. Differential LC Filter for Single +5 V or +3 V Output section. Although this single-ended configuration typi- Applications cally provides the best dc linearity performance, its ac distortion Maintaining low noise on power supplies and ground is critical performance at higher DAC update rates may be limited by to obtain optimum results from the AD9774. If properly U1’s slewing capabilities. U1 provides a negative unipolar output implemented, ground planes can perform a host of functions on voltage and its full-scale output voltage is simply the product of high speed circuit boards: bypassing, shielding current trans- R and I . The full-scale output should be set within U1’s FB OUTFS port, etc. In mixed signal design, the analog and digital portions voltage output swing capabilities by scaling I and/or R . OUTFS FB of the board should be distinct from each other, with the analog An improvement in ac distortion performance may result with a ground plane confined to the areas covering the analog signal reduced I since the signal current U1 will be required to OUTFS traces, and the digital ground plane confined to areas covering sink will be subsequently reduced. the digital interconnects. All analog ground pins of the DAC, reference and other analog C OPT components should be tied directly to the analog ground plane. R The two ground planes should be connected by a path 1/8 to FB 200V 1/4 inch wide underneath or within 1/2 inch of the DAC to I = 10mA OUTFS AD9774 maintain optimum performance. Care should be taken to ensure IOUTA 22 that the ground plane is uninterrupted over crucial signal paths. U1 V = I 3 R On the digital side, this includes the digital input lines running OUT OUTFS FB 21 IOUTB to the DAC as well as any clock signals. On the analog side, this 200V includes the DAC output signal, reference signal and the supply feeders. The use of wide runs or planes in the routing of power lines is Figure 40. Unipolar Buffered Voltage Output also recommended. This serves the dual role of providing a low series impedance power supply to the part, as well as providing POWER AND GROUNDING CONSIDERATIONS some “free” capacitive decoupling to the appropriate ground In systems seeking to simultaneously achieve high speed and plane. It is essential that care be taken in the layout of signal and high performance, the implementation and construction of the power ground interconnects to avoid inducing extraneous volt- printed circuit board design is often as important as the circuit age drops in the signal ground paths. It is recommended that all design. Proper RF techniques must be used in device selection, connections be short, direct and as physically close to the pack- placement and routing and supply bypassing and grounding. age as possible in order to minimize the sharing of conduction Figures 44–49 illustrate the recommended printed circuit board paths between different currents. When runs exceed an inch in ground, power and signal plane layouts that are implemented on length, strip line techniques with proper termination resistors the AD9774 evaluation board. should be considered. The necessity and value of this resistor Proper grounding and decoupling should be a primary objective will be dependent upon the logic family used. in any high speed, high resolution system. The AD9774 features For a more detailed discussion of the implementation and con- separate analog and digital supply and ground pins to optimize struction of high speed, mixed signal printed circuit boards, the management of analog and digital ground currents in a refer to Analog Devices’ application notes AN-280 and AN-333. system. In general, AVDD, the analog supply, should be decoupled REV. B –17– AD9774 MULTITONE PERFORMANCE CONSIDERATIONS AND tones) centered around one-half the Nyquist bandwidth (i.e., CHARACTERIZATION f /4). This particular multitone vector, has a peak-to-rms CLOCK The frequency domain performance of high speed DACs has ratio of 13.5 dB compared to a sine waves peak-to-rms ratio of traditionally been characterized by analyzing the spectral output 3 dB. A “snapshot” of this reconstructed multitone vector in the of a reconstructed full-scale (i.e., 0 dBFS), single-tone sine wave time domain as shown in Figure 43b reveals the higher signal at a particular output frequency and update rate. Although this content around the midscale value. As a result, a DAC’s “small- characterization data is useful, it is often insufficient to reflect a scale” dynamic and static linearity becomes increasingly critical in DAC’s performance for a reconstructed multitone or spread- obtaining low intermodulation distortion and maintaining spectrum waveform. In fact, evaluating a DAC’s spectral sufficient carrier-to-noise ratios for a given modulation scheme. performance using a full-scale, single tone at the highest specified A DAC’s small-scale linearity performance is also an important frequency (i.e., f ) of a bandlimited waveform is typically H consideration in applications where additive dynamic range is indicative of a DAC’s “worst-case” performance for that given required for gain control purposes or “predistortion” signal waveform. In the time domain, this full-scale sine wave repre- conditioning. For instance, a DAC with sufficient dynamic sents the lowest peak-to-rms ratio or crest factor (i.e., V / PEAK range can be used to provide additional gain control of its V rms) that this bandlimited signal will encounter. reconstructed signal. In fact, the gain can be controlled in 6 dB increments by simply performing a shift left or right on the 0 DAC’s digital input word. Other applications may intentionally –10 predistort a DAC’s digital input signal to compensate for –20 nonlinearities associated with the subsequent analog compo- nents in the signal chain. For example, the signal compression –30 associated with a power amplifier can be compensated for by –40 predistorting the DAC’s digital input with the inverse nonlinear –50 transfer function of the power amplifier. In either case, the –60 DAC’s performance at reduced signal levels should be carefully evaluated. –70 –80 A full-scale single tone will induce all of the dynamic and static nonlinearities present in a DAC that contribute to its distortion –90 and hence SFDR performance. As the frequency of this recon- –100 26481012 14 16 structed full-scale, single-tone waveform increases, the dynamic 0 nonlinearities of any DAC (i.e., AD9774) tend to dominate thus Figure 42a. Multitone Spectral Plot contributing to the roll-off in its SFDR performance. However, unlike most DACs, which employ an R-2R ladder for the lower 1.0000 bit current segmentation, the AD9774 (as well as other TxDAC 0.8000 members) exhibits an improvement in distortion performance as 0.6000 the amplitude of a single tone is reduced from its full-scale level. This improvement in distortion performance at reduced signal 0.4000 levels is evident if one compares the SFDR performance vs. 0.2000 frequency at different amplitudes (i.e., 0 dBFS, –6 dBFS and 0.0000 –12 dBFS) and sample rates as shown in Figures 4 through 15. –0.2000 Maintaining decent “small-scale” linearity across the full span of a DAC transfer function is also critical in maintaining excellent –0.4000 multitone performance. –0.6000 Although characterizing a DAC’s multitone performance tends –0.8000 to be application-specific, much insight into the potential per- –1.0000 formance of a DAC can also be gained by evaluating the DAC’s TIME swept power (i.e., amplitude) performance for single, dual and Figure 42b. Time Domain “Snapshot” of the Multitone multitone test vectors at different clock rates and carrier frequen- Waveform cies. The DAC is evaluated at different clock rates when recon- However, the inherent nature of a multitone, spread spectrum, structing a specific waveform whose amplitude is decreased in or QAM waveform, in which the spectral energy of the wave- 3 dB increments from full-scale (i.e., 0 dBFS). For each specific form is spread over a designated bandwidth, will result in a waveform, a graph showing the SFDR (over Nyquist) perfor- higher peak-to-rms ratio when compared to the case of a simple mance vs. amplitude can be generated at the different tested sine wave. As the reconstructed waveform’s peak-to-average clock rates as shown in Figures 19 and 20. Note that the ratio increases, an increasing amount of the signal energy is carrier(s)-to-clock ratio remains constant in each figure. concentrated around the DAC’s midscale value. Figure 42a is just one example of a bandlimited multitone vector (i.e., eight –18– REV. B VOLTS 10dB – DIV AD9774 80 A multitone test vector may consist of several equal amplitude, spaced carriers each representative of a channel within a defined 75 bandwidth as shown in Figure 42a. In many cases, one or more tones are removed so the intermodulation distortion performance 70 of the DAC can be evaluated. Nonlinearities associated with the 65 DAC will create spurious tones of which some may fall back into the “empty” channel thus limiting a channel’s carrier-to-noise 60 ratio. Other spurious components falling outside the band of 55 interest may also be important, depending on the system’s spectral mask and filtering requirements. 50 This particular test vector was centered around one-half the 45 Nyquist bandwidth (i.e., f /4) with a passband of f /16. CLOCK CLOCK Centering the tones at a much lower region (i.e., f /10) CLOCK 40 –18 –16 –14 –12 –10 –8 –6 –4 –2 0 would lead to an improvement in performance while centering A – dBFS OUT the tones at a higher region (i.e., f /2.5) would result in a CLOCK Figure 43a. Multitone SFDR vs. A @ 32 MSPS OUT degradation in performance. Figure 43a shows the SFDR vs. (Up to Nyquist) amplitude at 32 MSPS up to the Nyquist frequency while Fig- ure 43b shows the SFDR vs. amplitude within the passband of 80 the test vector. In assessing a DAC’s multitone performance, it 8MSPS is also recommended that several units be tested under exactly 75 16MSPS the same conditions to determine any performance variability. 70 32MSPS AD9774 EVALUATION BOARD General Description 65 The AD9774-EB is an evaluation board for the AD9774 14-bit DAC converter. Careful attention to layout and circuit design, 60 combined with a prototyping area, allows the user to easily and effectively evaluate the AD9774 in signal reconstruction applica- 55 tions, where high resolution, high speed conversion is required. This board allows the user the flexibility to operate the AD9774 50 –18 –16 –14 –12 –10 –8 –6 –4 –2 0 in various configurations. The digital inputs are designed to be A – dBFS OUT driven directly from various word generators with the onboard Figure 43b. Multitone SFDR vs. A @ 32 MSPS option to add a resistor network for proper load termination. OUT (Within Multitone Passband) Provisions are also made to operate the AD9774 with either the internal or external reference or to exercise the SLEEP or SNOOZE power-savings feature. REV. B –19– SFDR – dBc SFDR – dBc AD9774 DVDD DGND DGND AVDD AGND TP TP TP C2 C3 TP14 TP15 TP17 TP16 10mF 10mF C1 0.1mF R2 IA C4 50V 20pF IDIFF 3 4 C12 R10 U7 U3 5 2 0.1mF 100V TP 6 1 C5 R3 IB 20pF 50V 50V TP 50V TP C13 0.1mF TP C6 0.1mF AGND TP TP TP TP 44 43 42 41 40 39 38 37 36 35 34 REFCOMP DCOM 33 1 U2,U4 33 FSADJ DB13 32 2 1 TP R1 REFIO DB12 31 3 1.91kV REFLO C7 DB11 30 4 J4 0.1mF UNUSED DB10 29 5 AD9774 PLLENABLE TOP VIEW DB9 28 6 C10 (Not to Scale) 0.1mF PLLCOM DB8 27 TP19 7 P PLLVDD PLLVDD DB7 26 8 R5 C9 C8 S3 TP 1.5kV 10mF LPF 0.01mF DB6 25 9 TP18 VCO IN/EXT DB5 24 PLLGND 10 S2 P PLLDIVIDE DB4 23 11 S1 12 13 14 15 16 17 18 19 20 21 22 33 P PLLGND TP TP TP C11 0.1mF P DVDD AVDD PLLVDD DGND J2 P J1 J8 EXT CLK TP13 R4 50V 40 NC = NO CONNECT U8 U6 Figure 44. Evaluation Board Schematic –20– REV. B EDGE_40 DCOM DB3 DB2 SNOOZE DB1 NC DB0 DCOM NC DGND NC SLEEP DVDD ICOMP DGND IOUTA CLK IN/OUT IOUTB PLLLOCK AVDD CLK43IN ACOM X9 AD9774 Figure 45. Silkscreen Layer—Top Figure 46. Component Side PCB Layout (Layer 1) REV. B –21– AD9774 Figure 47. Ground Plane PCB Layout (Layer 2) Figure 48. Power Plane PCB Layout (Layer 3) –22– REV. B AD9774 Figure 49. Solder Side PCB Layout (Layer 4) Figure 50. Silkscreen Layer—Bottom REV. B –23– AD9774 OUTLINE DIMENSIONS Dimensions shown in millimeters and (inches). 44-Lead Metric Quad Flatpack (S-44) 13.45 (0.529) 12.95 (0.510) 2.45 (0.096) 10.10 (0.398) MAX 9.90 (0.390) 1.03 (0.041) 0° 0.73 (0.029) 44 34 MIN 1 33 SEATING PLANE 8.45 (0.333) TOP VIEW (PINS DOWN) 8.30 (0.327) 11 23 0.25 (0.01) 12 22 MIN 0.23 (0.009) 0.13 (0.005) 0.80 (0.031) 0.45 (0.018) BSC 2.10 (0.083) 0.30 (0.012) 1.95 (0.077) –24– REV. B PRINTED IN U.S.A. C3198b–0–11/98