ANALOG DEVICES AD9773

12-Bit, 160 MSPS, 2×/4×/8× Interpolating Dual TxDAC D/A Converter AD9773 FEATURES Versatile input data interface Twos complement/straight binary data coding 12-bit resolution, 160 MSPS/400 MSPS Dual-port or single-port interleaved input data input/output data rate Single 3.3 V supply operation Selectable 2×/4×/8× interpolating filter Power dissipation: typical 1.2 W @ 3.3 V Programmable channel gain and offset adjustment On-chip 1.2 V reference f /2, f /4, f /8 digital quadrature modulation capability S S S 80-lead thin quad flat package, exposed pad (TQFP_EP) Direct IF transmission mode for 70 MHz + IFs Enables image rejection architecture APPLICATIONS Fully compatible SPI port Communications Excellent ac performance Analog quadrature modulation architecture SFDR −69 dBc @ 2 MHz to 35 MHz 3G, multicarrier GSM, TDMA, CDMA systems WCDMA ACPR −69 dB @ IF = 19.2 MHz Broadband wireless, point-to-point microwave radios Internal PLL clock multiplier Instrumentation/ATE Selectable internal clock divider Versatile clock input Differential/single-ended sine wave or TTL/CMOS/LVPECL compatible FUNCTIONAL BLOCK DIAGRAM IDAC COS AD9773 HALF- HALF- HALF- GAIN OFFSET BAND BAND BAND DAC DAC FILTER1* FILTER2* FILTER3* DATA SIN ASSEMBLER IMAGE 12 16 16 16 16 REJECTION/ I I/Q DAC f /2, 4, 8 DUAL DAC LATCH GAIN/OFFSET DAC MODE REGISTERS I AND Q BYPASS NONINTERLEAVED MUX OR INTERLEAVED SIN 16 16 16 16 DATA Q LATCH 12 FILTER COS BYPASS WRITE MUX MUX CONTROL IDAC I SELECT OUT /2 (f ) DAC CLOCK OUT /2 /2 /2 SPI INTERFACE AND PRESCALER DIFFERENTIAL CONTROL REGISTERS CLK PHASE DETECTOR AND VCO * HALF-BAND FILTERS ALSO CAN BE CONFIGURED FOR ZERO STUFFING ONLY PLL CLOCK MULTIPLIER AND CLOCK DIVIDER Figure 1. Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. VREF IOFFSET 02857-001 AD9773 TABLE OF CONTENTS Features .............................................................................................. 1 Two-Port Data Input Mode ...................................................... 30 Applications....................................................................................... 1 One-/Two-Port Input Modes.................................................... 30 Functional Block Diagram .......................................................... 1 PLL Enabled, Two-Port Mode .................................................. 30 Table of Contents.............................................................................. 2 DATACLK Inversion.................................................................. 31 Revision History ........................................................................... 2 DATACLK Driver Strength....................................................... 31 General Description ......................................................................... 4 PLL Enabled, One-Port Mode .................................................. 31 Product Highlights ....................................................................... 4 ONEPORTCLK Inversion......................................................... 31 Specifications..................................................................................... 5 ONEPORTCLK Driver Strength.............................................. 32 DC Specifications ......................................................................... 5 IQ Pairing .................................................................................... 32 Dynamic Specifications ............................................................... 6 PLL Disabled, Two-Port Mode................................................. 32 Digital Specifications ................................................................... 7 PLL Disabled, One-Port Mode................................................. 32 Digital Filter Specifications ......................................................... 8 Digital Filter Modes ................................................................... 33 Absolute Maximum Ratings............................................................ 9 Amplitude Modulation.............................................................. 33 Thermal Characteristics .............................................................. 9 Modulation, No Interpolation .................................................. 34 ESD Caution.................................................................................. 9 Modulation, Interpolation = 2× ............................................... 35 Pin Configuration and Function Descriptions........................... 10 Modulation, Interpolation = 4× ............................................... 36 Typical Performance Characteristics ........................................... 12 Modulation, Interpolation = 8× ............................................... 37 Terminology .................................................................................... 17 Zero Stuffing ............................................................................... 38 Mode Control (Via SPI Port) .................................................... 18 Interpolating (Complex Mix Mode)........................................ 38 Register Description................................................................... 20 Operations on Complex Signals............................................... 38 Functional Description .................................................................. 22 Complex Modulation and Image Rejection of Baseband Signals .......................................................................................... 39 Serial Interface for Register Control ........................................ 22 Image Rejection and Sideband Suppression of Modulated General Operation of the Serial Interface ............................... 22 Carriers ........................................................................................ 41 Instruction Byte .......................................................................... 23 Applying the Output Configurations........................................... 46 Serial Interface Port Pin Descriptions ..................................... 23 Unbuffered Differential Output, Equivalent Circuit ............. 46 MSB/LSB Transfers..................................................................... 23 Differential Coupling Using a Transformer............................ 46 Notes on Serial Port Operation ................................................ 25 Differential Coupling Using an Op Amp................................ 47 DAC Operation........................................................................... 25 Interfacing the AD9773 with the AD8345 Quadrature 1R/2R Mode ................................................................................ 26 Modulator.................................................................................... 47 Clock Input Configurations ...................................................... 27 Evaluation Board ............................................................................ 48 Programmable PLL .................................................................... 27 Outline Dimensions....................................................................... 58 Power Dissipation....................................................................... 29 Ordering Guide .......................................................................... 58 Sleep/Power-Down Modes........................................................ 29 REVISION HISTORY Changes to Figure 108 .................................................................. 54 10/07—Rev. C to Rev. D Updated Outline Dimensions ..................................................... 58 Updated Formatting ........................................................ Universal Changes to Ordering Guide......................................................... 58 Changes to Figure 32 ....................................................................22 Rev. D | Page 2 of 60 AD9773 1/06—Rev. B to Rev. C 3/03—Data Sheet Changed from Rev. 0 to Rev. A. Updated Formatting .........................................................Universal Edits to Features ...............................................................................1 Changes to Figure 32 .................................................................... 22 Edits to DC Specifications ..............................................................3 Changes to Figure 108 .................................................................. 55 Edits to Dynamic Specifications ....................................................4 Updated Outline Dimensions ..................................................... 58 Edits to Pin Function Descriptions ...............................................7 Changes to Ordering Guide......................................................... 58 Edits to Table I ............................................................................... 14 Edits to Register Description—Address 02h Section............... 15 Edits to Register Description—Address 03h Section............... 16 4/04—Data Sheet Changed from Rev. A to Rev. B. Edits to Register Description—Address 07h, 0Bh Section...... 16 Update Layout....................................................................Universal Edits to Equation 1........................................................................ 16 Changes to DC Specifications ....................................................... 5 Edits to MSB/LSB Transfers Section........................................... 18 Changes to Absolute Maximum Ratings...................................... 9 Changes to Figure 8 ...................................................................... 20 Changes to DAC Operation Section........................................... 25 Edits to Programmable PLL Section........................................... 21 Inserted Figure 38.......................................................................... 25 Added New Figure 14 ................................................................... 22 Changes to Figure 40 .................................................................... 26 Renumbered Figures 15 through 69 ........................................... 22 Changes to Table 11 ...................................................................... 28 Add Two-Port Data Input Mode Section................................... 23 Changes to Programmable PLL Section..................................... 29 Edits to PLL Enabled, Two-Port Mode Section ........................ 24 Changes to Power Dissipation Section....................................... 29 Edits to Figure 19 .......................................................................... 24 Changes to Figures 49, 50, and 51............................................... 29 Edits to Figure 21 .......................................................................... 25 Changes to PLL Enabled, One-Port Mode Section .................. 31 Edits to PLL Disabled, Two-Port Mode Section ....................... 25 Changes to PLL Disabled, One-Port Mode Section ................. 32 Edits to Figure 22 .......................................................................... 25 Changes to Figure 102 .................................................................. 49 Edits to Figure 23 .......................................................................... 26 Changes to Figure 104 .................................................................. 50 Edits to Figure 26a ........................................................................ 27 Updated Ordering Guide ............................................................. 58 Edits to Complex Modulation and Image Rejection of Updated Outline Dimensions...................................................... 58 Baseband Signals Section ............................................................. 31 Changes to Figures 53 and 54...................................................... 38 Edits to Evaluation Board Section .............................................. 39 Changes to Figures 56 through 59 .............................................. 40 Replaced Figures 60 through 69.................................................. 42 Updated Outline Dimensions...................................................... 49 Rev. D | Page 3 of 60 AD9773 GENERAL DESCRIPTION 1 Dual high performance DAC outputs provide a differential The AD9773 is the 12-bit member of the AD977x pin- current output programmable over a 2 mA to 20 mA range. The compatible, high performance, programmable 2×/4×/8× AD9773 is manufactured on an advanced 0.35 micron CMOS interpolating TxDAC+® family. The AD977x family features process, operates from a single supply of 3.1 V to 3.5 V, and a serial port interface (SPI) that provides a high level of consumes 1.2 W of power. programmability, thus allowing for enhanced system-level options. These options include selectable 2×/4×/8× interpo- Targeted at a wide dynamic range, multicarrier, and multi- lation filters; f /2, f /4, or f /8 digital quadrature modulation standard systems, the superb baseband performance of the S S S with image rejection; a direct IF mode; programmable channel AD9773 is ideal for wide band CDMA, multicarrier CDMA, gain and offset control; programmable internal clock divider; multicarrier TDMA, multicarrier GSM, and high performance straight binary or twos complement data interface; and a single- systems employing high order QAM modulation schemes. The port or dual-port data interface. image rejection feature simplifies and can help to reduce the number of signal band filters needed in a transmit signal chain. The selectable 2×/4×/8× interpolation filters simplify the The direct IF mode helps to eliminate a costly mixer stage for a requirements of the reconstruction filters while simultaneously variety of communications systems. enhancing the TxDAC+ family’s pass-band noise/distortion performance. The independent channel gain and offset adjust PRODUCT HIGHLIGHTS registers allow the user to calibrate LO feedthrough and side- 1. The AD9773 is the 12-bit member of the AD977x pin band suppression errors associated with analog quadrature compatible, high performance, programmable 2×/4×/8× modulators. The 6 dB of gain adjustment range can also be interpolating TxDAC+ family. used to control the output power level of each DAC. 2. Direct IF transmission is possible for 70 MHz + IFs The AD9773 features the ability to perform fS/2, fS/4, and fS/8 through a novel digital mixing process. digital modulation and image rejection when combined with an 3. fS/2, fS/4, and fS/8 digital quadrature modulation and user analog quadrature modulator. In this mode, the AD9773 selectable image rejection simplify/remove cascaded SAW accepts I and Q complex data (representing a single or multi- filter stages. carrier waveform), generates a quadrature modulated IF signal 4. A 2×/4×/8× user selectable interpolating filter eases data along with its orthogonal representation via its dual DACs, and rate and output signal reconstruction filter requirements. presents these two reconstructed orthogonal IF carriers to an 5. User selectable twos complement/straight binary analog quadrature modulator to complete the image rejection data coding. upconversion process. Another digital modulation mode (for 6. User programmable channel gain control over 1 dB range example, the direct IF mode) allows the original baseband in 0.01 dB increments. signal representation to be frequency translated such that pairs 7. User programmable channel offset control ±10% over of images fall at multiples of one-half the DAC update rate. the FSR. The AD977x family includes a flexible clock interface accepting 8. Ultrahigh speed 400 MSPS DAC conversion rate. differential or single-ended sine wave or digital logic inputs. 9. Internal clock divider provides data rate clock for An internal PLL clock multiplier is included and generates the easy interfacing. necessary on-chip high frequency clocks. It can also be disabled to allow the use of a higher performance external clock source. 10. Flexible clock input with single-ended or differential input, An internal programmable divider simplifies clock generation CMOS, or 1 V p-p LO sine wave input capability. in the converter when using an external clock source. A flexible 11. Low power: Complete CMOS DAC operates on 1.2 W from a data input interface allows for straight binary or twos complement 3.1 V to 3.5 V single supply. The 20 mA full-scale current can formats and supports single-port interleaved or dual-port data. be reduced for lower power operation, and several sleep functions reduce power during idle periods. 1 Protected by U.S. Patent Numbers 5,568,145; 5,689,257; and 5,703,519. Other 12. On-chip voltage reference: The AD9773 includes a 1.20 V patents pending. temperature compensated band gap voltage reference. 13. 80-lead thin quad flat package, exposed pad (TQFP_EP). Rev. D | Page 4 of 60 AD9773 SPECIFICATIONS DC SPECIFICATIONS T to T , AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 3.3 V, I = 20 mA, unless otherwise noted. MIN MAX OUTFS Table 1. Parameter Min Typ Max Unit RESOLUTION 12 Bits 1 DC Accuracy Integral Nonlinearity −1.5 ±0.4 +1.5 LSB Differential Nonlinearity −1 ±0.2 +1 LSB Monotonicity Guaranteed over specified temperature range ANALOG OUTPUT (for IR and 2R Gain Setting Modes) Offset Error −0.02 ±0.01 +0.02 % of FSR Gain Error (with Internal Reference) −1.0 +1.0 % of FSR Gain Matching −1.0 ±0.1 +1.0 % of FSR 2 Full-Scale Output Current 2 20 mA Output Compliance Range −1.0 +1.25 V Output Resistance 200 kΩ Output Capacitance 3 pF Gain, Offset Cal DACs, Monotonicity Guaranteed REFERENCE OUTPUT Reference Voltage 1.14 1.20 1.26 V 3 Reference Output Current 100 nA REFERENCE INPUT Input Compliance Range 0.1 1.25 V Reference Input Resistance 7 kΩ Small Signal Bandwidth 0.5 MHz TEMPERATURE COEFFICIENTS Offset Drift 0 ppm of FSR/°C Gain Drift (With Internal Reference) 50 ppm of FSR/°C Reference Voltage Drift ±50 ppm/°C POWER SUPPLY AVDD Voltage Range 3.1 3.3 3.5 V 4 Analog Supply Current (I ) 72.5 76 mA AVDD IAVDD in Sleep Mode 23.3 26 mA CLKVDD Voltage Range 3.1 3.3 3.5 V 4 Clock Supply Current (I ) 8.5 10.0 mA CLKVDD CLKVDD (PLL ON) Clock Supply Current (I ) 23.5 mA CLKVDD DVDD Voltage Range 3.1 3.3 3.5 V 4 Digital Supply Current (IDVDD) 34 41 mA Nominal Power Dissipation 380 410 mW 5 P 1.75 W DIS PDIS in PWDN 6.0 mW Power Supply Rejection Ratio—AVDD ±0.4 % of FSR/V OPERATING RANGE −40 +85 °C 1 Measured at I driving a virtual ground. OUTA 2 Nominal full-scale current, IOUTFS, is 32× the IREF current. 3 Use an external amplifier to drive any external load. 4 100 MSPS fDAC with fOUT = 1 MHz, all supplies = 3.3 V, no interpolation, no modulation. 5 400 MSPS f , f = 50 MSPS, f /2 modulation, PLL enabled. DAC DATA S Rev. D | Page 5 of 60 AD9773 DYNAMIC SPECIFICATIONS TMIN to TMAX, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 0 V, IOUTFS = 20 mA, interpolation = 2×, differential transformer-coupled output, 50 Ω doubly terminated, unless otherwise noted. Table 2. Parameter Min Typ Max Unit DYNAMIC PERFORMANCE Maximum DAC Output Update Rate (fDAC) 400 MSPS Output Settling Time (tST) (to 0.025%) 11 ns 1 Output Rise Time (10% to 90%) 0.8 ns 1 Output Fall Time (10% to 90%) 0.8 ns Output Noise (IOUTFS = 20 mA) 50 pA√Hz AC LINEARITY—BASEBAND MODE Spurious-Free Dynamic Range (SFDR) to Nyquist (f = 0 dBFS) OUT fDATA = 100 MSPS, fOUT = 1 MHz 70 84.5 dBc fDATA = 65 MSPS, fOUT = 1 MHz 83 dBc fDATA = 65 MSPS, fOUT = 15 MHz 79 dBc f = 78 MSPS, f = 1 MHz 83 dBc DATA OUT f = 78 MSPS, f = 15 MHz 77 dBc DATA OUT f = 160 MSPS, f = 1 MHz 75 dBc DATA OUT fDATA = 160 MSPS, fOUT = 15 MHz 77 dBc Spurious-Free Dynamic Range Within a 1 MHz Window fOUT = 0 dBFS, fDATA = 100 MSPS, fOUT = 1 MHz 72 92.6 dBc Two-Tone Intermodulation (IMD) to Nyquist (f = f = −6 dBFS) OUT1 OUT2 f = 65 MSPS, f = 10 MHz; f = 11 MHz 80 dBc DATA OUT1 OUT2 fDATA = 65 MSPS, fOUT1 = 20 MHz; fOUT2 = 21 MHz 75 dBc fDATA = 78 MSPS, fOUT1 = 10 MHz; fOUT2 = 11 MHz 80 dBc fDATA = 78 MSPS, fOUT1 = 20 MHz; fOUT2 = 21 MHz 75 dBc f = 160 MSPS, f = 10 MHz; f = 11 MHz 80 dBc DATA OUT1 OUT2 f = 160 MSPS, f = 20 MHz; f = 21 MHz 75 dBc DATA OUT1 OUT2 Total Harmonic Distortion (THD) fDATA = 100 MSPS, fOUT = 1 MHz; 0 dBFS −70 −82.4 dB Signal-to-Noise Ratio (SNR) fDATA = 78 MSPS, fOUT = 5 MHz; 0 dBFS 70 dB f = 160 MSPS, f = 5 MHz; 0 dBFS 69 dB DATA OUT Adjacent Channel Power Ratio (ACPR) WCDMA with 3.84 MHz BW, 5 MHz Channel Spacing IF = Baseband, fDATA = 76.8 MSPS 69 dBc IF = 19.2 MHz, fDATA = 76.8 MSPS 69 dBc Four-Tone Intermodulation 21 MHz, 22 MHz, 23 MHz, and 24 MHz at −12 dBFS (f = MSPS, Missing Center) 73 dBFS DATA AC LINEARITY—IF MODE Four-Tone Intermodulation at IF = 200 MHz 201 MHz, 202 MHz, 203 MHz, and 204 MHz at −12 dBFS (f = 160 MSPS, f = 320 MHz) 69 dBFS DATA DAC 1 Measured single-ended into 50 Ω load. Rev. D | Page 6 of 60 AD9773 DIGITAL SPECIFICATIONS TMIN to TMAX, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, DVDD = 3.3 V, IOUTFS = 20 mA, unless otherwise noted. Table 3. Parameter Min Typ Max Unit DIGITAL INPUTS Logic 1 Voltage 2.1 3 V Logic 0 Voltage 0 0.9 V Logic 1 Current −10 +10 μA Logic 0 Current −10 +10 μA Input Capacitance 5 pF CLOCK INPUTS Input Voltage Range 0 3 V Common-Mode Voltage 0.75 1.5 2.25 V Differential Voltage 0.5 1.5 V SERIAL CONTROL BUS Maximum SCLK Frequency (f ) 15 MHz SLCK Minimum Clock Pulse Width High (tPWH) 30 ns Minimum Clock Pulse Width Low (tPWL) 30 ns Maximum Clock Rise/Fall Time 1 ms Minimum Data/Chip Select Setup Time (t ) 25 ns DS Minimum Data Hold Time (t ) 0 ns DH Maximum Data Valid Time (tDV) 30 ns RESET Pulse Width 1.5 ns Inputs (SDI, SDIO, SCLK, CSB) Logic 1 Voltage 2.1 3 V Logic 0 Voltage 0 0.9 V Logic 1 Current −10 +10 μA Logic 0 Current −10 +10 μA Input Capacitance 5 pF SDIO Output Logic 1 Voltage DRVDD − 0.6 V Logic 0 Voltage 0.4 V Logic 1 Current 30 50 mA Logic 0 Current 30 50 mA Rev. D | Page 7 of 60 AD9773 20 DIGITAL FILTER SPECIFICATIONS Table 4. Half-Band Filter No. 1 (43 Coefficients) 0 Tap Coefficient –20 1, 43 8 2, 42 0 –40 3, 41 −29 4, 40 0 –60 5, 39 67 –80 6, 38 0 7, 37 −134 –100 8, 36 0 9, 35 244 –120 0 0.5 1.0 1.5 2.0 10, 34 0 f (NORMALIZED TO INPUT DATA RATE) OUT 11, 33 −414 12, 32 0 Figure 2. 2× Interpolating Filter Response 13, 31 673 20 14, 30 0 15, 29 −1079 0 16, 28 0 –20 17, 27 1772 18, 26 0 –40 19, 25 −3280 20, 24 0 –60 21, 23 10,364 –80 22 16,384 –100 Table 5. Half-Band Filter No. 2 (19 Coefficients) –120 0 0.5 1.0 1.5 2.0 Tap Coefficient f (NORMALIZED TO INPUT DATA RATE) OUT 1, 19 19 2, 18 0 Figure 3. 4× Interpolating Filter Response 3, 17 −120 20 4, 16 0 5, 15 438 0 6, 14 0 –20 7, 13 −1288 8, 12 0 –40 9, 11 5047 10 8192 –60 –80 Table 6. Half-Band Filter No. 3 (11 Coefficients) –100 Tap Coefficient 1, 11 7 –120 04 2 68 2, 10 0 f (NORMALIZED TO INPUT DATA RATE) OUT 3, 9 −53 4, 8 0 Figure 4. 8× Interpolating Filter Response 5, 7 302 6 512 Rev. D | Page 8 of 60 ATTENUATION (dBFS) ATTENUATION (dBFS) ATTENUATION (dBFS) 02857-004 02857-003 02857-002 AD9773 ABSOLUTE MAXIMUM RATINGS Table 7. Parameter With Respect To Min Max Unit AVDD, DVDD, CLKVDD AGND, DGND, CLKGND −0.3 +4.0 V AVDD, DVDD, CLKVDD AVDD, DVDD, CLKVDD −4.0 +4.0 V AGND, DGND, CLKGND AGND, DGND, CLKGND −0.3 +0.3 V REFIO, FSADJ1/FSADJ2 AGND −0.3 AVDD + 0.3 V IOUTA, IOUTB AGND −1.0 AVDD + 0.3 V P1B11 to P1B0, P2B11 to P2B0, RESET DGND −0.3 DVDD + 0.3 V DATACLK, PLL_LOCK DGND −0.3 DVDD + 0.3 V CLK+, CLK− CLKGND −0.3 CLKVDD + 0.3 V LPF CLKGND −0.3 CLKVDD + 0.3 V SPI_CSB, SPI_CLK, SPI_SDIO, SPI_SDO DGND −0.3 DVDD + 0.3 V Junction Temperature 125 °C Storage Temperature −65 +150 °C Lead Temperature (10 sec) 300 °C Stresses above those listed under Absolute Maximum Ratings THERMAL CHARACTERISTICS may cause permanent damage to the device. This is a stress Thermal Resistance rating only; functional operation of the device at these or any 80-lead thin quad flat package, exposed pad (TQFP_EP) other conditions above those indicated in the operational θJA = 23.5°C/W (with thermal pad soldered to PCB) sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect ESD CAUTION device reliability. Rev. D | Page 9 of 60 AD9773 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 CLKVDD 1 60 FSADJ1 PIN 1 LPF 2 59 FSADJ2 CLKVDD 3 58 REFIO 4 57 CLKGND RESET 5 56 CLK+ SPI_CSB 6 55 CLK– SPI_CLK CLKGND 7 54 SPI_SDIO AD9773 DATACLK/PLL_LOCK 8 53 SPI_SDO TxDAC+ DGND 9 52 DGND TOP VIEW (Not to Scale) DVDD 10 51 DVDD 11 50 P1B11 (MSB) NC 12 49 P1B10 NC 13 48 P1B9 NC 14 47 P1B8 NC P1B7 15 46 P2B0 (LSB) P1B6 16 45 P2B1 DGND 17 44 DGND DVDD 18 43 DVDD 19 42 P1B5 P2B2 20 41 P1B4 P2B3 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 NC = NO CONNECT Figure 5. Pin Configuration Rev. D | Page 10 of 60 P1B3 AVDD P1B2 AGND P1B1 AVDD P1B0 (LSB) AGND DGND AVDD DVDD AGND NC AGND NC I OUTA1 NC I OUTB1 NC AGND IQSEL/P2B11 (MSB) AGND ONEPORTCLK/P2B10 I OUTA2 P2B9 I OUTB2 P2B8 AGND DGND AGND DVDD AVDD P2B7 AGND P2B6 AVDD P2B5 AGND P2B4 AVDD 02857-005 AD9773 Table 8. Pin Function Descriptions Pin No. Mnemonic Description 1, 3 CLKVDD Clock Supply Voltage. 2 LPF PLL Loop Filter. 4, 7 CLKGND Clock Supply Common. 5 CLK+ Differential Clock Input. 6 CLK− Differential Clock Input. 8 DATACLK/PLL_LOCK With the PLL enabled, this pin indicates the state of the PLL. A read of a Logic 1 indicates the PLL is in the locked state. Logic 0 indicates the PLL has not achieved lock. This pin can also be programmed to act as either an input or output (Address 02h, Bit 3) DATACLK signal running at the input data rate. 9, 17, 25, DGND Digital Common. 35, 44, 52 10, 18, 26, DVDD Digital Supply Voltage. 36, 43, 51 11 to 16, P1B11 (MSB) to P1B0 (LSB) Port 1 Data Inputs. 19 to 24, 27 to 30, NC No Connect. 47 to 50 31 IQSEL/P2B11 (MSB) In one-port mode, IQSEL = 1 followed by a rising edge of the differential input clock latches the data into the I channel input register. IQSEL = 0 latches the data into the Q channel input register. In two-port mode, this pin becomes the Port 2 MSB. 32 ONEPORTCLK/P2B10 With the PLL disabled and the AD9773 in one-port mode, this pin becomes a clock output that runs at twice the input data rate of the I and Q channels. This allows the AD9773 to accept and demux interleaved I and Q data to the I and Q input registers. 33, 34, 37 to P2B9 to P2B0 (LSB) Port 2 Data Inputs. 42, 45, 46 53 SPI_SDO In the case where SDIO is an input, SDO acts as an output. When SDIO becomes an output, SDO enters a high-Z state. This pin can also be used as an output for the data rate clock. For more information, see the Two-Port Data Input Mode section. 54 SPI_SDIO Bidirectional Data Pin. Data direction is controlled by Bit 7 of Register Address 00h. The default setting for this bit is 0, which sets SDIO as an input. 55 SPI_CLK Data input to the SPI port is registered on the rising edge of SPI_CLK. Data output on the SPI port is registered on the falling edge. 56 SPI_CSB Chip Select/SPI Data Synchronization. On momentary logic high, resets SPI port logic and initializes instruction cycle. 57 RESET Logic 1 resets all of the SPI port registers, including Address 00h, to their default values. A software reset can also be done by writing a Logic 1 to SPI Register 00h, Bit 5. However, the software reset has no effect on the bits in Address 00h. 58 REFIO Reference Output, 1.2 V Nominal. 59 FSADJ2 Full-Scale Current Adjust, Q Channel. 60 FSADJ1 Full-Scale Current Adjust, I Channel. 61, 63, 65, AVDD Analog Supply Voltage. 76, 78, 80 62, 64, 66, AGND Analog Common. 67, 70, 71, 74, 75, 77, 79 68, 69 IOUTB2, IOUTA2 Differential DAC Current Outputs, Q Channel. 72, 73 I , I Differential DAC Current Outputs, I Channel. OUTB1 OUTA1 Rev. D | Page 11 of 60 AD9773 TYPICAL PERFORMANCE CHARACTERISTICS T = 25°C, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, IOUTFS = 20 mA, interpolation = 2×, differential transformer-coupled output, 50 Ω doubly terminated, unless otherwise noted. 10 10 0 0 –10 –10 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 0 65 130 0 50 100 150 FREQUENCY (MHz) FREQUENCY (MHz) Figure 6. Single-Tone Spectrum @ fDATA = 65 MSPS with fOUT = fDATA/3 Figure 9. Single-Tone Spectrum @ fDATA = 78 MSPS with fOUT = fDATA/3 90 90 85 85 0dBFS 0dBFS 80 80 75 75 –6dBFS –6dBFS 70 70 –12dBFS –12dBFS 65 65 60 60 55 55 50 50 02 100 30 02 100 30 FREQUENCY (MHz) FREQUENCY (MHz) Figure 7. In-Band SFDR vs. fOUT @ fDATA = 65 MSPS Figure 10. In-Band SFDR vs. fOUT @ fDATA = 78 MSPS 90 90 0dBFS 85 85 –6dBFS 0dBFS 80 80 –6dBFS 75 75 70 70 –12dBFS –12dBFS 65 65 60 60 55 55 50 50 02 100 30 02 100 30 FREQUENCY (MHz) FREQUENCY (MHz) Figure 8. Out-of-Band SFDR vs. fOUT @ fDATA = 65 MSPS Figure 11. Out-of-Band SFDR vs. fOUT @ fDATA = 78 MSPS Rev. D | Page 12 of 60 SFDR (dBc) SFDR (dBc) AMPLITUDE (dBm) 02857-008 02857-007 02857-006 SFDR (dBc) SFDR (dBc) AMPLITUDE (dBm) 02857-011 02857-010 02857-009 AD9773 10 90 –3dBFS –6dBFS 0 85 –10 80 –20 75 –30 0dBFS 70 –40 –50 65 –60 60 –70 55 –80 50 –90 0 100 200 300 02 100 30 FREQUENCY (MHz) FREQUENCY (MHz) Figure 15. Third-Order IMD Products vs. f @ f = 65 MSPS Figure 12. Single-Tone Spectrum @ fDATA = 160 MSPS with fOUT = fDATA/3 OUT DATA 90 90 –6dBFS 85 85 0dBFS 0dBFS –12dBFS 80 80 75 75 –3dBFS 70 70 –6dBFS 65 65 60 60 55 55 50 50 02 100 30 010 20 30 40 50 FREQUENCY (MHz) FREQUENCY (MHz) Figure 13. In-Band SFDR vs. f @ f = 160 MSPS Figure 16. Third-Order IMD Products vs. f @ f = 78 MSPS OUT DATA OUT DATA 90 90 85 85 –3dBFS –6dBFS 80 80 –6dBFS 75 75 0dBFS 0dBFS 70 70 65 65 60 60 –12dBFS 55 55 50 50 010 20 30 40 50 04 200 60 FREQUENCY (MHz) FREQUENCY (MHz) Figure 14. Out-of-Band SFDR vs. f @ f = 160 MSPS OUT DATA Figure 17. Third-Order IMD Products vs. fOUT @ fDATA = 160 MSPS Rev. D | Page 13 of 60 SFDR (dBc) AMPLITUDE (dBm) SFDR (dBc) 02857-014 02857-013 02857-012 IMD (dBc) IMD (dBc) IMD (dBc) 02857-017 02857-016 02857-015 AD9773 90 90 –3dBFS –6dBFS 8× 85 85 4× 80 80 0dBFS 75 75 1× 70 70 2× 65 65 60 60 55 55 50 50 04 200 60 3.1 3.2 3.3 3.4 3.5 FREQUENCY (MHz) AVDD (V) Figure 21. Third-Order IMD Products vs. AVDD @ f = 10 MHz, Figure 18. Third-Order IMD Products vs. f and Interpolation Rate, OUT OUT f = 320 MSPS, f = 160 MSPS 1× f = 160 MSPS, 2× f = 160 MSPS, 4× f = 80 MSPS, DAC DATA DATA DATA DATA 8× f = 50 MSPS DATA 90 4× 8× 90 85 85 80 PLL OFF 80 75 2× 1× 75 70 70 65 PLL ON 65 60 60 55 55 50 –15 –10 –5 0 50 0 0 50 100 150 150 A (dBFS) OUT INPUT DATA RATE (MSPS) Figure 19. Third-Order IMD Products vs. A and Interpolation Rate, OUT Figure 22. SNR vs. Data Rate for fOUT = 5 MHz f = 50 MSPS for All Cases, 1× f = 50 MSPS, 2× f = 100 MSPS, DATA DAC DAC 4× f = 200 MSPS, 8× f = 400 MSPS DAC DAC 90 90 85 85 0dBFS –12dBFS 80 80 f = 65MSPS DATA 78MSPS 75 75 160MSPS 70 70 –6dBFS 65 65 60 60 55 55 50 50 3.1 3.2 3.3 3.4 3.5 –50 0 50 100 AVDD (V) TEMPERATURE (°C) Figure 20. SFDR vs. AVDD @ f = 10 MHz, OUT f = 320 MSPS, f = 160 MSPS Figure 23. SFDR vs. Temperature @ fOUT = fDATA/11 DAC DATA Rev. D | Page 14 of 60 SFDR (dBc) IMD (dBc) IMD (dBc) 02857-020 02857-019 02857-018 SFDR (dBc) SFDR (dBc) SNR (dB) 02857-023 02857-022 02857-021 AD9773 0 0 –10 –20 –20 –30 –40 –40 –50 –60 –60 –70 –80 –80 –90 –100 –100 0 50 100 02 510 15 205303540 FREQUENCY (MHz) FREQUENCY (MHz) Figure 27. Two-Tone IMD Performance, f = 150 MSPS, Interpolation = 4× Figure 24. Single-Tone Spurious Performance, f = 10 MHz, DATA OUT f = 150 MSPS, No Interpolation DATA 0 0 –10 –10 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 –100 0 50 100 150 200 250 02 1003040 FREQUENCY (MHz) FREQUENCY (MHz) Figure 25. Two-Tone IMD Performance, fDATA = 150 MSPS, No Interpolation Figure 28. Single-Tone Spurious Performance, f = 10 MHz, OUT f = 80 MSPS, Interpolation = 4× DATA 0 –10 0 –20 –30 –20 –40 –50 –40 –60 –70 –60 –80 –90 –80 –100 0 50 100 150 200 250 –100 FREQUENCY (MHz) 0 5 10 15 20 25 FREQUENCY (MHz) Figure 29. Two-Tone IMD Performance, f = 10 MHz, f = 50 MSPS, Figure 26. Single-Tone Spurious Performance, fOUT = 10 MHz, OUT DATA Interpolation = 8× fDATA = 150 MSPS, Interpolation = 2× Rev. D | Page 15 of 60 AMPLITUDE (dBm) AMPLITUDE (dBm) AMPLITUDE (dBm) 02857-026 02857-025 02857-024 AMPLITUDE (dBm) AMPLITUDE (dBm) AMPLITUDE (dBm) 02857-029 02857-028 02857-027 AD9773 0 0 –10 –10 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 –100 04 200 60 0 100 200 300 FREQUENCY (MHz) FREQUENCY (MHz) Figure 31. Eight-Tone IMD Performance, f = 160 MSPS, Figure 30. Single-Tone Spurious Performance, fOUT = 10 MHz, DATA Interpolation = 8× fDATA = 50 MSPS, Interpolation = 8× Rev. D | Page 16 of 60 AMPLITUDE (dBm) 02857-030 AMPLITUDE (dBm) 02857-031 AD9773 TERMINOLOGY Adjacent Channel Power Ratio (ACPR) Offset Error A ratio, in dBc, between the measured power within a channel The deviation of the output current from the ideal of 0 is called relative to its adjacent channel. offset error. For IOUTA, 0 mA output is expected when the inputs are all 0s. For IOUTB, 0 mA output is expected when all inputs are Complex Image Rejection set to 1. In a traditional two-part upconversion, two images are created around the second IF frequency. These images are redundant Output Compliance Range and have the effect of wasting transmitter power and system The range of allowable voltage at the output of a current output bandwidth. By placing the real part of a second complex DAC. Operation beyond the maximum compliance limits may modulator in series with the first complex modulator, either cause either output stage saturation or breakdown, resulting in the upper or lower frequency image near the second IF can be nonlinear performance. rejected. Pass Band Complex Modulation Frequency band in which any input applied therein passes The process of passing the real and imaginary components of a unattenuated to the DAC output. jωt signal through a complex modulator (transfer function = e = Power Supply Rejection cosωt + jsinωt) and realizing real and imaginary components The maximum change in the full-scale output as the supplies on the modulator output. are varied from minimum to maximum specified voltages. Differential Nonlinearity (DNL) Settling Time DNL is the measure of the variation in analog value, normalized The time required for the output to reach and remain within a to full scale, associated with a 1 LSB change in digital input code. specified error band about its final value, measured from the Gain Error start of the output transition. The difference between the actual and ideal output span. The Signal-to-Noise Ratio (SNR) actual span is determined by the output when all inputs are set SNR is the ratio of the rms value of the measured output signal to 1 minus the output when all inputs are set to 0. to the rms sum of all other spectral components below the Glitch Impulse Nyquist frequency, excluding the first six harmonics and dc. Asymmetrical switching times in a DAC give rise to undesired The value for SNR is expressed in decibels. output transients that are quantified by a glitch impulse. It is Spurious-Free Dynamic Range specified as the net area of the glitch in pV-s. The difference, in dB, between the rms amplitude of the output Group Delay signal and the peak spurious signal over the specified bandwidth. Number of input clocks between an impulse applied at the Stop-Band Rejection device input and the peak DAC output current. A half-band FIR The amount of attenuation of a frequency outside the pass band filter has constant group delay over its entire frequency range. applied to the DAC, relative to a full-scale signal applied at the Impulse Response DAC input within the pass band. Response of the device to an impulse applied to the input. Temperature Drift Interpolation Filter It is specified as the maximum change from the ambient (25°C) If the digital inputs to the DAC are sampled at a multiple rate of value to the value at either T or T . For offset and gain MIN MAX f (interpolation rate), a digital filter can be constructed with drift, the drift is reported in ppm of full-scale range (FSR) per DATA a sharp transition band near f /2. Images that would typically °C. For reference drift, the drift is reported in ppm per °C. DATA appear around f (output data rate) can be greatly suppressed. DAC Total Harmonic Distortion (THD) Linearity Error THD is the ratio of the rms sum of the first six harmonic com- Also called integral nonlinearity (INL), linearity error is defined ponents to the rms value of the measured fundamental. It is as the maximum deviation of the actual analog output from the expressed as a percentage or in decibels (dB). ideal output, determined by a straight line drawn from 0 to full scale. Monotonicity A DAC is monotonic if the output either increases or remains constant as the digital input increases. Rev. D | Page 17 of 60 AD9773 MODE CONTROL (VIA SPI PORT) 1 Table 9. Mode Control via SPI Port Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 00h SDIO LSB, MSB First Software Sleep Power-Down 1R/2R Mode PLL_LOCK Bidirectional 0 = MSB Reset Mode Mode Logic 1 DAC Output Indicator 0 = Input 1 = LSB on Logic 1 Logic 1 Shuts Down Current Set by 1 = I/O Shuts All Digital and One or Two Down the Analog External DAC Functions Resistors Output 0 = 2R, 1 = 1R Currents –jωt 01h Filter Filter Modulation Modulation 0 = No Zero 1 = Real Mix 0 = e DATACLK/ 2 +jωt Interpolation Interpolation Mode Mode PLL_LOCK Stuffing on Mode 1 = e Rate Rate (None, fS/2, (None, fS/2, Interpolation 0 = Complex Select (1×, 2×, 4×, 8×) (1×, 2×, 4×, 8×) fS/4, fS/8) fS/4, fS/8) Filters, Logic 1 Mix Mode 0 = PLLLOCK Enables Zero 1 = Stuffing DATACLK 02h 0 = Signed 0 = Two-Port DATACLK DATACLK ONEPORTCLK IQSEL Q First Input Data Mode Driver Invert Invert Invert 0 = I First 1 = Unsigned 1 = One-Port Strength 0 = No 0 = No Invert 0 = No 1 = Q First Mode Invert 1 = Invert Invert 1 = Invert 1 = Invert 2 03h Data Rate PLL Divide PLL Divide Output Clock (Prescaler) (Prescaler) Ratio Ratio 2 04h 0 = PLL OFF 0 = Automatic PLL Charge PLL Charge PLL Charge 1 = PLL ON Pump Pump Pump Charge Pump Control Control Control Control 1 = Programmable 05h IDAC IDAC IDAC IDAC IDAC IDAC IDAC IDAC Fine Gain Fine Gain Fine Gain Fine Gain Fine Gain Fine Gain Fine Gain Fine Gain Adjustment Adjustment Adjustment Adjustment Adjustment Adjustment Adjustment Adjustment 06h IDAC IDAC IDAC IDAC Coarse Gain Coarse Gain Coarse Coarse Adjustment Adjustment Gain Gain Adjustment Adjustment 07h IDAC Offset IDAC Offset IDAC Offset IDAC Offset IDAC Offset IDAC Offset IDAC Offset IDAC Offset Adjustment Adjustment Adjustment Adjustment Adjustment Adjustment Adjustment Adjustment Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 08h IDAC I IDAC Offset IDAC Offset OFFSET Direction Adjustment Adjustment 0 = IOFFSET Bit 1 Bit 0 on IOUTA 1 = I OFFSET on I OUTB 09h QDAC QDAC QDAC QDAC QDAC QDAC QDAC QDAC Fine Gain Fine Gain Fine Gain Fine Gain Fine Gain Fine Gain Fine Gain Fine Gain Adjustment Adjustment Adjustment Adjustment Adjustment Adjustment Adjustment Adjustment Rev. D | Page 18 of 60 AD9773 Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0Ah QDAC QDAC QDAC QDAC Coarse Gain Coarse Gain Coarse Gain Coarse Gain Adjustment Adjustment Adjustment Adjustment 0Bh QDAC QDAC QDAC QDAC QDAC QDAC QDAC QDAC Offset Offset Offset Offset Offset Offset Offset Offset Adjustment Adjustment Adjustment Adjustment Adjustment Adjustment Adjustment Adjustment Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 0Ch QDAC IOFFSET QDAC QDAC Direction Offset Offset Adjustment Adjustment 0 = IOFFSET on IOUTA Bit 1 Bit 0 1 = IOFFSET on I OUTB 0Dh Version Version Version Version Register Register Register Register 1 Default values are shown in bold. 2 See the Two-Port Data Input Mode section for more information. Rev. D | Page 19 of 60 AD9773 Bit 3: Logic 1 enables zero stuffing mode for interpolation REGISTER DESCRIPTION filters. Address 00h Bit 2: Default (1) enables the real mix mode. The I and Q data Bit 7: Logic 0 (default) causes the SPI_SDIO pin to act as an channels are individually modulated by fS/2, fS/4, or fS/8 after input during the data transfer (Phase 2) of the communications the interpolation filters. However, no complex modulation is cycle. When set to 1, SPI_SDIO can act as an input or output, done. In the complex mix mode (Logic 0), the digital modu- depending on Bit 7 of the instruction byte. lators on the I and Q data channels are coupled to create a Bit 6: Logic 0 (default) determines the direction (LSB/MSB digital complex modulator. When the AD9773 is applied in first) of the communications and data transfer communications conjunction with an external quadrature modulator, rejection cycles. Refer to the MSB/LSB Transfers section for more details. can be achieved of either the higher or lower frequency image around the second IF frequency (that is, the LO of the analog Bit 5: Writing a 1 to this bit resets the registers to their default values and restarts the chip. The RESET bit always reads back 0. quadrature modulator external to the AD9773) according to the Register Address 00h bits are not cleared by this software reset. bit value of Register 01h, Bit 1. However, a high level at the RESET pin forces all registers, Bit 1: Logic 0 (default) causes the complex modulation to be of including those in Address 00h, to their default state. −jωt the form e , resulting in the rejection of the higher frequency Bit 4: Sleep Mode. A Logic 1 to this bit shuts down the DAC image when the AD9773 is used with an external quadrature modulator. A Logic 1 causes the modulation to be of the form output currents. +jωt e , which causes rejection of the lower frequency image. Bit 3: Power-Down Mode. Logic 1 shuts down all analog and digital functions except for the SPI port. Bit 0: In two-port mode, a Logic 0 (default) causes Pin 8 to act as a lock indicator for the internal PLL. A Logic 1 in this register Bit 2: 1R/2R Mode. The default (0) places the AD9773 in two- causes Pin 8 to act as a DATACLK. For more information, see resistor mode. In this mode, the I currents for the I and Q REF the Two-Port Data Input Mode section. DAC references are set separately by the R resistors on SET FSADJ1 and FSADJ2 (Pin 59 and Pin 60). In 2R mode, Address 02h assuming the coarse gain setting is full scale and the fine gain Bit 7: Logic 0 (default) causes data to be accepted on the inputs setting is zero, IFULLSCALE1 = 32 × VREF/FSADJ1 and IFULLSCALE2 = as twos complement. Logic 1 causes data to be accepted as 32 × VREF/FSADJ2. With this bit set to 1, the reference currents straight binary. for both I and Q DACs are controlled by a single resistor on Bit 6: Logic 0 (default) places the AD9773 in two-port mode. I Pin 60. IFULLSCALE in one-resistor mode for both I and Q DACs is and Q data enters the AD9773 via Port 1 and Port 2, half of what it would be in 2R mode, assuming all other respectively. A Logic 1 places the AD9773 in one-port mode in conditions (R , register settings) remain unchanged. The full- SET which interleaved I and Q data is applied to Port 1. See Table 8 scale current of each DAC can still be set to 20 mA by choosing for detailed information on the DATACLK/PLL_LOCK, IQSEL, a resistor of half the value of the R value used in 2R mode. SET and ONEPORTCLK modes. Bit 1: PLL_LOCK Indicator. When the PLL is enabled, reading Bit 5: DATACLK Driver Strength. With the internal PLL this bit gives the status of the PLL. A Logic 1 indicates the PLL disabled and this bit set to Logic 0, it is recommended that is locked. A Logic 0 indicates an unlocked state. DATACLK be buffered. When this bit is set to Logic 1, Address 01h DATACLK acts as a stronger driver capable of driving small Bit 7 and Bit 6: This is the filter interpolation rate according to capacitive loads. Table 10. Bit 4: Logic 0 (default). A value of 1 inverts DATACLK at Pin 8. Table 10. Bit 2: Logic 0 (default). A value of 1 inverts ONEPORTCLK at Pin 32. 00 1× 01 2× Bit 1: The Logic 0 (default) causes IQSEL = 0 to direct input 10 4× data to the I channel, while IQSEL = 1 directs input data to the 11 8× Q channel. Bit 5 and Bit 4: This is the modulation mode according to Bit 0: The Logic 0 (default) defines IQ pairing as IQ, IQ, ... Table 11. while programming a Logic 1 causes the pair ordering to be QI, QI, .... Table 11. 00 none 01 fS/2 10 fS/4 11 fS/8 Rev. D | Page 20 of 60 AD9773 Address 03h Address 05h, 09h Bit 7: Allows the data rate clock (divided down from the DAC Bit 7, Bit 6, Bit 5, Bit 4, Bit 3, Bit 2, Bit 1, and Bit 0: These bits clock) to be output at either the DATACLK pin (Pin 8) or at the represent an 8-bit binary number (Bit 7 MSB) that defines the SPI_SDO pin (Pin 53). The default of 0 in this bit enables the fine gain adjustment of the I (05h) and Q (09h) DAC according data rate clock at DATACLK, while a 1 in this bit causes the data to Equation 1. rate clock to be output at SPI_SDO. For more information, see Address 06h, 0Ah the Two-Port Data Input Mode section. Bit 3, Bit 2, Bit 1, and Bit 0: These bits represent a 4-bit binary Bit 1 and Bit 0: Setting this divide ratio to a higher number number (Bit 3 MSB) that defines the coarse gain adjustment of allows the VCO in the PLL to run at a high rate (for best perform- the I (06h) and Q (0Ah) DACs according to Equation 1. ance), while the DAC input and output clocks run substantially Address 07h, 0Bh slower. The divider ratio is set according to Table 12. Bit 7, Bit 6, Bit 5, Bit 4, Bit 3, Bit 2, Bit 1, and Bit 0: These bits Table 12. are used in conjunction with Address 08h, Address 0Ch, Bits [1:0]. 00 ÷1 Address 08h, 0Ch 01 ÷2 10 ÷4 Bit 1 and Bit 0: The 10 bits from these two address pairs (07h, 11 ÷8 08h and 0Bh, 0Ch) represent a 10-bit binary number that defines the offset adjustment of the I and Q DACs according to Address 04h Equation 1: (07h, 0Bh: Bit 7 MSB; 08h, 0Ch: Bit 0 LSB). Bit 7: Logic 0 (default) disables the internal PLL. Logic 1 Address 08h, 0Ch enables the PLL. Bit 7: This bit determines the direction of the offset of the I (08h) Bit 6: Logic 0 (default) sets the charge pump control to and Q (0Ch) DACs. A Logic 0 applies a positive offset current to automatic. In this mode, the charge pump bias current is IOUTA, while a Logic 1 applies a positive offset current to IOUTB. controlled by the divider ratio defined in Address 03h, Bits 1 The magnitude of the offset current is defined by the bits in and 0. Logic 1 allows the user to manually define the charge Addresses 07h, 0Bh, 08h, and 0Ch according to Equation 1. pump bias current using Address 04h, Bits 2, 1, and 0. Adjusting the charge pump bias current allows the user to optimize the Equation 1 shows I and I as a function of fine gain, OUTA OUTB noise/settling performance of the PLL. coarse gain, and offset adjustment when using 2R mode. In 1R mode, the current I is created by a single FSADJ1 resistor REF Bit 2, Bit 1, and Bit 0: With the charge pump control set to (Pin 60). This current is divided equally into each channel so manual, these bits define the charge pump bias current that a scaling factor of one-half must be added to these according to Table 13. equations for full-scale currents for both DACs and the offset. Table 13. 000 50 μA 001 100 μA 010 200 μA 011 400 μA 111 800 μA ⎡ 6× I COARSE+1 3× I FINE ⎤ ⎡ 1024 DATA ⎤ ⎛ ⎞ ⎛ REF⎞⎛ ⎞ ⎛ REF⎞⎛ ⎞ ⎛ ⎞ = − × I ⎜ ⎟ (A) ⎜ ⎟⎜ ⎟ ⎜ ⎟⎜ ⎟ ⎜ ⎟ OUTA ⎢ ⎥ ⎢ 12 ⎥ 8 16 32 256 24 ⎝ ⎠ 2 ⎝ ⎠⎝ ⎠ ⎝ ⎠⎝ ⎠ ⎝ ⎠ ⎣ ⎦ ⎣ ⎦ 12 ⎡ ⎤ ⎛ ⎞ ⎡ 6× I COARSE+1 3× I FINE ⎤ 1024 2 − DATA−1 ⎛ REF⎞⎛ ⎞ ⎛ REF⎞⎛ ⎞ ⎛ ⎞ ⎜ ⎟ I = − × (A) (1) ⎜ ⎟⎜ ⎟ ⎜ ⎟⎜ ⎟ ⎢⎜ ⎟ ⎥ OUTB ⎢ ⎥ 12 ⎜ ⎟ 8 16 32 256 24 2 ⎝ ⎠⎝ ⎠ ⎝ ⎠⎝ ⎠ ⎝ ⎠ ⎣ ⎦ ⎢ ⎥ ⎝ ⎠ ⎣ ⎦ OFFSET ⎛ ⎞ I = 4× I (A) ⎜ ⎟ OFFSET REF 1024 ⎝ ⎠ Rev. D | Page 21 of 60 AD9773 FUNCTIONAL DESCRIPTION The AD9773 dual interpolating DAC consists of two data SDO (PIN 53) channels that can be operated completely independently or coupled to form a complex modulator in an image reject SDIO (PIN 54) AD9773 SPI PORT INTERFACE transmit architecture. Each channel includes three FIR filters, SPI_CLK (PIN 55) making the AD9773 capable of 2×, 4×, or 8× interpolation. CSB (PIN 56) High speed input and output data rates can be achieved within the limitations shown in Table 14. Figure 32. SPI Port Interface Table 14. SERIAL INTERFACE FOR REGISTER CONTROL Interpolation Rate Input Data Rate DAC Sample Rate The AD9773 serial port is a flexible, synchronous serial (MSPS) (MSPS) (MSPS) communications port that allows an easy interface to many 1× 160 160 industry-standard microcontrollers and microprocessors. 2× 160 320 The serial I/O is compatible with most synchronous transfer 4× 100 400 formats, including both the Motorola SPI and Intel® SSR 8× 50 400 protocols. The interface allows read/write access to all registers Both data channels contain a digital modulator capable of that configure the AD9773. Single- or multiple-byte transfers mixing the data stream with an LO of fDAC/2, fDAC/4, or fDAC/8, are supported as well as MSB first or LSB first transfer formats. where fDAC is the output data rate of the DAC. A zero stuffing The AD9773’s serial interface port can be configured as a single feature is also included and can be used to improve pass-band pin I/O (SDIO) or two unidirectional pins for I/O (SDIO/SDO). flatness for signals being attenuated by the SIN(x)/x charac- GENERAL OPERATION OF THE SERIAL INTERFACE teristic of the DAC output. The speed of the AD9773, combined There are two phases to a communication cycle with the with its digital modulation capability, enables direct IF AD9773. Phase 1 is the instruction cycle, which is the writing of conversion architectures at 70 MHz and higher. an instruction byte into the AD9773 coincident with the first The digital modulators on the AD9773 can be coupled to form eight SCLK rising edges. The instruction byte provides the a complex modulator. By using this feature with an external AD9773 serial port controller with information regarding the analog quadrature modulator, such as Analog Devices’ AD8345, data transfer cycle, which is Phase 2 of the communication an image rejection architecture can be enabled. To optimize the cycle. The Phase 1 instruction byte defines whether the upcom- image rejection capability, as well as LO feedthrough in this ing data transfer is read or write, the number of bytes in the architecture, the AD9773 offers programmable (via the SPI data transfer, and the starting register address for the first byte port) gain and offset adjust for each DAC. of the data transfer. The first eight SCLK rising edges of each Also included on the AD9773 are a phase-locked loop (PLL) communication cycle are used to write the instruction byte into clock multiplier and a 1.20 V band gap voltage reference. With the AD9773. the PLL enabled, a clock applied to the CLK+/CLK− inputs is A Logic 1 on the SPI_CSB pin, followed by a logic low, resets frequency multiplied internally and generates all necessary the SPI port timing to the initial state of the instruction cycle. internal synchronization clocks. Each 12-bit DAC provides two This is true regardless of the present state of the internal complementary current outputs whose full-scale currents can registers or the other signal levels present at the inputs to the be determined either from a single external resistor or inde- SPI port. If the SPI port is in the middle of an instruction cycle pendently from two separate resistors (see the 1R/2R Mode or a data transfer cycle, none of the present data is written. section). The AD9773 features a low jitter, differential clock The remaining SCLK edges are for Phase 2 of the communication input that provides excellent noise rejection while accepting a cycle. Phase 2 is the actual data transfer between the AD9773 and sine or square wave input. Separate voltage supply inputs are the system controller. Phase 2 of the communication cycle is a provided for each functional block to ensure optimum noise transfer of one to four data bytes, as determined by the instruction and distortion performance. byte. Normally, using one multibyte transfer is the preferred Sleep and power-down modes can be used to turn off the DAC method. However, single byte data transfers are useful to reduce output current (sleep) or the entire digital and analog sections CPU overhead when register access requires one byte only. (power-down) of the chip. An SPI-compliant serial port is used Registers change immediately upon writing to the last bit of each to program the many features of the AD9773. Note that in transfer byte. power-down mode, the SPI port is the only section of the chip still active. Rev. D | Page 22 of 60 02857-032 AD9773 The SPI_SDO and SPI_SDIO pins go to a high impedance state INSTRUCTION BYTE when this input is high. Chip select should stay low during the The instruction byte contains the information shown in entire communication cycle. Table 15. SPI_SDIO (Pin 54)—Serial Data I/O Table 15. Data is always written into the AD9773 on this pin. However, N1 N0 Description this pin can be used as a bidirectional data line. The configura- 0 0 Transfer 1 Byte tion of this pin is controlled by Bit 7 of Register Address 00h. 0 1 Transfer 2 Bytes The default is Logic 0, which configures the SDIO pin as 1 0 Transfer 3 Bytes unidirectional. 1 1 Transfer 4 Bytes SPI_SDO (Pin 53)—Serial Data Out R/W Data is read from this pin for protocols that use separate lines Bit 7 of the instruction byte determines whether a read or a for transmitting and receiving data. In the case where the write data transfer occurs after the instruction byte write. AD9773 operates in a single bidirectional I/O mode, this pin Logic 1 indicates read operation. Logic 0 indicates a write does not output data and is set to a high impedance state. operation. MSB/LSB TRANSFERS N1, N0 The AD9773 serial port can support both most significant bit Bits 6 and 5 of the instruction byte determine the number of (MSB) first or least significant bit (LSB) first data formats. This bytes to be transferred during the data transfer cycle. The bit functionality is controlled by the first LSB bit in Register 0. The decodes are shown in the following table. default is MSB first. MSB LSB When this bit is set active high, the AD9773 serial port is in LSB I7 I6 I5 I4 I3 I2 I1 I0 first format. In LSB first mode, the instruction byte and data R/W N1 N0 A4 A3 A2 A1 A0 bytes must be written from LSB to MSB. In LSB first mode, the serial port internal byte address generator increments for each A4, A3, A2, A1, and A0 byte of the multibyte communication cycle. Bits 4, 3, 2, 1, and 0 of the instruction byte determine which When this bit is set default low, the AD9773 serial port is register is accessed during the data transfer portion of the in MSB first format. In MSB first mode, the instruction byte communications cycle. For multibyte transfers, this address is and data bytes must be written from MSB to LSB. In MSB the starting byte address. The remaining register addresses are first mode, the serial port internal byte address generator generated by the AD9773. decrements for each byte of the multibyte communication cycle. SERIAL INTERFACE PORT PIN DESCRIPTIONS When incrementing from 1Fh, the address generator changes to SPI_CLK (Pin 55)—Serial Clock 00h. When decrementing from 00h, the address generator The serial clock pin is used to synchronize data to and from the changes to 1Fh. AD9773 and to run the internal state machines. The SPI_CLK maximum frequency is 15 MHz. All data input to the AD9773 is registered on the rising edge of SPI_CLK. All data is driven out of the AD9773 on the falling edge of SPI_CLK. SPI_CSB (Pin 56)—Chip Select Active low input starts and gates a communication cycle. It allows more than one device to be used on the same serial communications lines. Rev. D | Page 23 of 60 AD9773 INSTRUCTION CYCLE DATA TRANSFER CYCLE CS SCLK SDIO R/W I6 I5 I4 I3 I2 I1 I0 D7 D6 D2 D1 D0 (N) (N) N N 0 0 0 D7 D6 D2 D1 D0 SDO N N 0 0 0 Figure 33. Serial Register Interface Timing MSB First INSTRUCTION CYCLE DATA TRANSFER CYCLE CS SCLK SDIO I0 I1 I2 I3 I4 I5 I6 R/W D0 D1 D2 D6 D7 (N) (N) 0 0 0 N N SDO D0 D1 D2 D6 D7 0 0 0 N N Figure 34. Serial Register Interface Timing LSB First t t DS SCLK CS t t PWH PWL SCLK t t DS DH INSTRUCTION BIT 7 INSTRUCTION BIT 6 T SDIO Figure 35. Timing Diagram for Register Write to AD9773 CS SCLK t DV SDIO DATA BIT N DATA BIT N–1 SDO Figure 36. Timing Diagram for Register Read from AD9773 Rev. D | Page 24 of 60 02857-036 02857-035 02857-033 02857-034 AD9773 NOTES ON SERIAL PORT OPERATION OFFSET OFFSET CONTROL FINE DAC REGISTERS The AD9773 serial port configuration bits reside in Bits 6 and 7 GAIN GAIN DAC of Register Address 00h. It is important to note that the config- CONTROL REGISTERS uration changes immediately upon writing to the last bit of the FINE I IDAC OUTA1 GAIN register. For multibyte transfers, writing to this register can DAC 1.2VREF I OUTB1 occur during the middle of the communication cycle. Care REFIO must be taken to compensate for this new configuration for the COARSE COARSE QDAC I OUTA2 0.1μF GAIN GAIN remaining bytes of the current communication cycle. DAC DAC I OUTB2 The same considerations apply to setting the reset bit in FSADJ1 FSADJ2 OFFSET OFFSET Register Address 00h. All other registers are set to their default R 1 CONTROL SET DAC GAIN R 2 REGISTERS SET values, but the software reset does not affect the bits in CONTROL REGISTERS Register Address 00h. Figure 37. DAC Outputs, Reference Current Scaling, It is recommended to use only single-byte transfers when changing and Gain/Offset Adjust serial port configurations or initiating a software reset. A write to Bit 1, Bit 2, and Bit 3 of Address 00h with the same AVDD logic levels as for Bit 7, Bit 6, and Bit 5 (bit pattern: XY1001YX binary) allows the user to reprogram a lost serial port config- 84μA uration and to reset the registers to their default values. A REFIO second write to Address 00h with reset bit low and serial port configuration as previously specified (XY) reprograms the OSC 7kΩ IN multiplier setting. A changed f frequency is stable after SYSCLK 0.7V a maximum of 200 f cycles (equals wake-up time). MCLK DAC OPERATION Figure 38. Internal Reference Equivalent Circuit The dual 12-bit DAC output of the AD9773, along with the reference circuitry, gain, and offset registers, is shown in Figure 37 and Figure 38. Note that an external reference can be used by 25 simply overdriving the internal reference with the external reference. Referring to the transfer functions in Equation 1, a reference current is set by the internal 1.2 V reference, the 20 external RSET resistor, and the values in the coarse gain register. 2R MODE The fine gain DAC subtracts a small amount from this and the 15 result is input to IDAC and QDAC, where it is scaled by an amount equal to 1024/24. Figure 39 and Figure 40 show the 10 scaling effect of the coarse and fine adjust DACs. IDAC and QDAC are PMOS current source arrays, segmented in a 5-4-3 1R MODE configuration. The five most significant bits control an array of 5 31 current sources. The next four bits consist of 15 current sources whose values are all equal to 1/16 of an MSB current 0 source. The three LSBs are binary weighted fractions of the 01 501520 middle bits’ current sources. All current sources are switched to COARSE GAIN REGISTER CODE (ASSUMING R 1, R 2 = 1.9kΩ) SET SET either I or I , depending on the input code. OUTA OUTB Figure 39. Coarse Gain Effect on IFULLSCALE The fine adjustment of the gain of each channel allows for improved balance of QAM modulated signals, resulting in improved modulation accuracy and image rejection. In the Interfacing the AD9773 with the AD8345 Quadrature Modulator section, the performance data shows to what degree image rejection can be improved when the AD9773 is used with an AD8345 quadrature modulator from Analog Devices Inc. Rev. D | Page 25 of 60 COARSE REFERENCE CURRENT (mA) 02857-038 02857-039 02857-037 AD9773 0 5 –0.5 4 1R MODE –1.0 3 2R MODE –1.5 2R MODE 2 –2.0 1R MODE 1 –2.5 –3.0 0 0 200 400 600 800 1000 0 200 400 600 800 1000 0 COARSE GAIN REGISTER CODE FINE GAIN REGISTER CODE (ASSUMING RSET1, RSET2 = 1.9kΩ) 1, R 2 = 1.9kΩ) (ASSUMING R SET SET Figure 40. Fine Gain Effect on I Figure 41. DAC Output Offset Current FULLSCALE 0 The offset control defines a small current that can be added to I or I (not both) on the IDAC and QDAC. The OUTA OUTB –10 selection in which I for this offset current is directed toward OFFSET REGISTER 1 ADJUSTED OUT –20 is programmable via Register 08h, Bit 7 (IDAC) and Register 0Ch, Bit 7 (QDAC). Figure 41 shows the scale of the offset –30 current that can be added to one of the complementary outputs –40 on the IDAC and QDAC. Offset control can be used for suppression of LO leakage resulting from modulation of dc –50 signal components. If the AD9773 is dc-coupled to an external –60 modulator, this feature can be used to cancel the output offset OFFSET REGISTER 2 ADJUSTED, WITH OFFSET on the AD9773 as well as the input offset on the modulator. –70 REGISTER 1 SET TO OPTIMIZED VALUE Figure 42 shows a typical example of the effect that the offset –80 control has on LO suppression. –1024 –768 –512 –256 0 256 512 768 1024 DAC1, DAC2 (OFFSET REGISTER CODES) In Figure 42, the negative scale represents an offset added to Figure 42. Offset Adjust Control, Effect on LO Suppression IOUTB, while the positive scale represents an offset added to IOUTA of the respective DAC. Offset Register 1 corresponds to IDAC, 1R/2R MODE while Offset Register 2 corresponds to QDAC. Figure 42 In 2R mode, the reference current for each channel is set represents the AD9773 synthesizing a complex signal that is independently by the FSADJ resistor on that channel. The then dc-coupled to an AD8345 quadrature modulator with an AD9773 can be programmed to derive its reference current LO of 800 MHz. The dc coupling allows the input offset of the from a single resistor on Pin 60 by putting the part into 1R AD8345 to be calibrated out as well. The LO suppression at the mode. The transfer functions in Equation 1 are valid for 2R AD8345 output was optimized first by adjusting Offset Register 1 mode. In 1R mode, the current developed in the single FSADJ in the AD9773. When an optimal point was found (roughly resistor is split equally between the two channels. The result is Code 54), this code was held in Offset Register 1, and Offset that in 1R mode, a scale factor of 1/2 must be applied to the Register 2 was adjusted. The resulting LO suppression is formulas in Equation 1. The full-scale DAC current in 1R mode 70 dBFS. These are typical numbers, and the specific code for can still be set to as high as 20 mA by using the internal 1.2 V optimization varies from part to part. reference and a 950 Ω resistor instead of the 1.9 kΩ resistor typically used in 2R mode. Rev. D | Page 26 of 60 FINE REFERENCE CURRENT (mA) 02857-040 LO SUPPRESSION (dBFS) OFFSET CURRENT (mA) 02857-042 02857-041 AD9773 These networks depend on the assumed transmission line CLOCK INPUT CONFIGURATIONS impedance and power supply voltage of the clock driver. The clock inputs to the AD9773 can be driven differentially or Optimum performance of the AD9773 is achieved when the single-ended. The internal clock circuitry has supply and driver is placed very close to the AD9773 clock inputs, thereby ground (CLKVDD, CLKGND) separate from the other supplies negating any transmission line effects such as reflections due to on the chip to minimize jitter from internal noise sources. mismatch. Figure 43 shows the AD9773 driven from a single-ended clock The quality of the clock and data input signals is important in source. The CLK+/CLK− pins form a differential input achieving optimum performance. The external clock driver (CLKIN) so that the statically terminated input must be dc- circuitry should provide the AD9773 with a low jitter clock biased to the midswing voltage level of the clock driven input. input that meets the minimum/maximum logic levels while providing fast edges. Although fast clock edges help minimize AD9773 any jitter that manifests itself as phase noise on a reconstructed R SERIES waveform, the high gain bandwidth product of the AD9773’s CLK+ clock input comparator can tolerate differential sine wave inputs CLKVDD as low as 0.5 V p-p, with minimal degradation of the output noise floor. CLK– V THRESHOLD 0.1μF PROGRAMMABLE PLL CLKGND CLKIN can function either as an input data rate clock (PLL enabled) or as a DAC data rate clock (PLL disabled) according Figure 43. Single-Ended Clock Driving Clock Inputs to the state of Address 02h, Bit 7 in the SPI port register. The internal operation of the AD9773 clock circuitry in these two A configuration for differentially driving the clock inputs is modes is illustrated in Figure 45 and Figure 46. given in Figure 44. DC-blocking capacitors can be used to couple a clock driver output whose voltage swings exceed The PLL clock multiplier and distribution circuitry produce the CLKVDD or CLKGND. If the driver voltage swings are within necessary internal synchronized 1×, 2×, 4×, and 8× clocks for the supply range of the AD9773, the dc-blocking capacitors and the rising edge triggered latches, interpolation filters, modu- bias resistors are not necessary. lators, and DACs. This circuitry consists of a phase detector, charge pump, voltage controlled oscillator (VCO), prescaler, AD9773 clock distribution, and SPI port control. The charge pump, 1kΩ 0.1μF VCO, differential clock input buffer, phase detector, prescaler, CLK+ and clock distribution are all powered from CLKVDD. PLL lock 1kΩ status is indicated by the logic signal at the DATACLK_PLL_LOCK ECL/PECL 0.1μF CLKVDD 1kΩ pin, as well as by the status of Bit 1, Register 00h. To ensure 0.1μF CLK– optimum phase noise performance from the PLL clock 1kΩ multiplier and distribution, CLKVDD should originate from a CLKGND clean analog supply. The VCO speed is a function of the input data rate, the interpolation rate, and the VCO prescaler, Figure 44. Differential Clock Driving Clock Inputs according to the following function: VCO Speed(MHz)= A transformer, such as the T1-1T from Mini-Circuits®, can also be used to convert a single-ended clock to differential. This method is Input Data Rate() MHz × Interpolation Rate× Prescaler used on the AD9773 evaluation board so that an external sine wave Table 16 defines the minimum input data rates vs. the with no dc offset can be used as a differential clock. interpolation and PLL divider setting. If the input data rate PECL/ECL drivers require varying termination networks, the drops below the defined minimum rates under these details of which are left out of Figure 43 and Figure 44 but can conditions, VCO phase noise may increase significantly. be found in application notes such as the AND8020/D from On Semiconductor®. Rev. D | Page 27 of 60 02857-043 02857-044 AD9773 However, maximum rates of less than 160 MSPS and all CLK+ CLK– minimum f rates are due to the maximum and minimum DATA PLLVDD PLL_LOCK speeds of the internal PLL VCO. Figure 48 shows typical 1 = LOCK AD9773 0 = NO LOCK performance of the PLL lock signal (Pin 8 or Pin 53) when the PLL is in the process of locking. INTERPOLATION PHASE CHARGE Table 16. PLL Optimization FILTERS, DETECTOR PUMP LPF MODULATORS, Interpolation Divider Minimum Maximum AND DACS Rate Setting fDATA fDATA 2 48 1 1 32 160 1 CLOCK PRESCALER VCO 1 2 16 160 INPUT DISTRIBUTION DATA CIRCUITRY 1 4 8 112 LATCHES PLL DIVIDER 1 8 4 56 INTERNAL SPI (PRESCALER) CONTROL CONTROL 2 1 24 160 REGISTERS INTERPOLATION PLL RATE 2 2 12 112 MODULATION CONTROL CONTROL RATE (PLL ON) 2 4 6 56 SPI PORT CONTROL 2 8 3 28 Figure 45. PLL and Clock Circuitry with PLL Enabled 4 1 24 100 4 2 12 56 4 4 6 28 CLK+ CLK– 4 8 3 14 PLL_LOCK 1 = LOCK AD9773 8 1 24 50 0 = NO LOCK 8 2 12 28 8 4 6 14 INTERPOLATION PHASE CHARGE 8 8 3 7 FILTERS, DETECTOR PUMP MODULATORS, AND DACS 2 48 1 Table 17. Required PLL Prescaler Ratio vs. f DATA CLOCK PRESCALER VCO INPUT DISTRIBUTION fDATA PLL Prescaler Ratio DATA CIRCUITRY LATCHES 125 MSPS Disabled PLL DIVIDER INTERNAL SPI (PRESCALER) 125 MSPS Enabled Div 1 CONTROL CONTROL REGISTERS INTERPOLATION 100 MSPS Enabled Div 2 PLL RATE MODULATION CONTROL 75 MSPS Enabled Div 2 CONTROL RATE (PLL ON) SPI PORT CONTROL 50 MSPS Enabled Div 4 Figure 46. PLL and Clock Circuitry with PLL Disabled 0 In addition, if the zero stuffing option is enabled, the VCO –10 doubles its speed again. Phase noise may be slightly higher with –20 the PLL enabled. Figure 47 illustrates typical phase noise –30 performance of the AD9773 with 2× interpolation and various input data rates. The signal synthesized for the phase noise –40 measurement was a single carrier at a frequency of f /4. The DATA –50 repetitive nature of this signal eliminates quantization noise and –60 distortion spurs as a factor in the measurement. Although the –70 curves blend together in Figure 47, the different conditions are –80 given for clarity in Table 17. Table 16 details PLL divider –90 settings vs. interpolation rate and maximum and minimum –100 fDATA rates. Note that the maximum fDATA rates of 160 MSPS are –110 due to the maximum input data rate of the AD9773. 012 3 45 FREQUENCY OFFSET (MHz) Figure 47. Phase Noise Performance Rev. D | Page 28 of 60 02857-045 02857-046 PHASE NOISE (dBFS) 02857-047 AD9773 76.0 8×, (MOD. ON) 4×, (MOD. ON) 75.5 2×, (MOD. ON) 75.0 74.5 4× 8× 74.0 73.5 2× 73.0 1× 72.5 72.0 0 50 100 150 200 Figure 48. PLL_LOCK Output Signal (Pin 8) in the f (MHz) DATA Process of Locking (Typical Lock Time) Figure 50. IAVDD vs. fDATA vs. Interpolation Rate, PLL Disabled It is important to note that the resistor/capacitor needed for the 35 PLL loop filter is internal on the AD9773. This suffices unless the 8× input data rate is below 10 MHz, in which case an external series 30 RC is required between the LPF and CLKVDD pins. 4× 2× 25 POWER DISSIPATION The AD9773 has three voltage supplies: DVDD, AVDD, and 20 CLKVDD. Figure 49, Figure 50, and Figure 51 show the current 15 required from each of these supplies when each is set to the 1× 3.3 V nominal specified for the AD9773. Power dissipation (P ) D 10 can easily be extracted by multiplying the given curves by 3.3. As Figure 49 shows, I is very dependent on the input data DVDD 5 rate, the interpolation rate, and the activation of the internal 0 digital modulator. IDVDD, however, is relatively insensitive to the 0 50 100 150 200 modulation rate by itself. In Figure 50, IAVDD shows the same f (MHz) DATA type of sensitivity to the data, the interpolation rate, and the Figure 51. ICLKVDD vs. fDATA vs. Interpolation Rate, PLL Disabled modulator function but to a much lesser degree (<10%). In Figure 51, I varies over a wide range yet is responsible for CLKVDD SLEEP/POWER-DOWN MODES only a small percentage of the overall AD9773 supply current (Control Register 00h, Bit 3 and Bit 4) requirements. The AD9773 provides two methods for programmable 400 8×, (MOD. ON) 2×, (MOD. ON) reduction in power savings. The sleep mode, when activated, 350 4×, (MOD. ON) turns off the DAC output currents but the rest of the chip remains functioning. When coming out of sleep mode, the 300 AD9773 immediately returns to full operation. Power-down 8× 4× 250 mode, on the other hand, turns off all analog and digital 2× circuitry in the AD9773 except for the SPI port. When 200 returning from power-down mode, enough clock cycles must 150 be allowed to flush the digital filters of random data acquired 100 during the power-down cycle. 1× 50 0 0 50 100 150 200 f (MHz) DATA Figure 49. I vs. f vs. Interpolation Rate, PLL Disabled DVDD DATA Rev. D | Page 29 of 60 I (mA) DVDD 02857-049 02857-048 I (mA) I (mA) CLKVDD AVDD 02857-050 02857-051 AD9773 TWO-PORT DATA INPUT MODE ONE-PORT/TWO-PORT INPUT MODES The digital data input ports can be configured as two The digital data input ports can be configured as two independent ports or as a single (one-port mode) port. In the independent ports or as a single (one-port mode) port. In two- two-port mode, data at the two input ports is latched into the port mode, the AD9773 can be programmed to generate an AD9773 on every rising edge of the data rate clock (DATACLK). externally available data rate clock (DATACLK) for the purpose Also, in the two-port mode, the AD9773 can be programmed to of data synchronization. Data at the two input ports can be generate an externally available DATACLK for the purpose of latched into the AD9773 on every rising clock edge of data synchronization. This data rate clock can be programmed to DATACLK. In one-port mode, P2B10 and P2B11 from Input be available at either Pin 8 (DATACLK/PLL_LOCK) or Pin 53 Data Port 2 are redefined as IQSEL and ONEPORTCLK, (SPI_SDO). Because Pin 8 can also function as a PLL lock respectively. The input data in one-port mode is steered to one indicator when the PLL is enabled, there are several options for of the two internal data channels based on the logic level of configuring Pin 8 and Pin 53. The following information IQSEL. A clock signal, ONEPORTCLK, is generated by the describes the options. AD9773 in this mode for the purpose of external data synchronization. ONEPORTCLK runs at the input interleaved PLL Off (Register 4, Bit 7 = 0) data rate, which is 2× the data rate at the internal input to either Register 4, Bit 7 = 0; DATACLK out of Pin 8. channel. Register 4, Bit 7 = 1; DATACLK out of Pin 53. Test configurations showing the various clocks required and PLL On (Register 4, Bit 7 = 1) produced by the AD9773 in the PLL and one-port/two-port Register 4, Bit 7 = 0, Register 1, Bit 0 = 0; PLL lock indicator out modes are given in Figure 101 to Figure 104. Jumper positions of Pin 8. needed to operate the AD9773 evaluation board in these modes Register 4, Bit 7 = 1, Register 1, Bit 0 = 0; PLL lock indicator out are given as well. of Pin 53. PLL ENABLED, TWO-PORT MODE Register4, Bit 7 = 0, Register 1, Bit 0 = 1; DATACLK out of Pin 8. (Control Register 02h, Bits [6:0] and 04h, Bits [7:1] Register 4, Bit 7 = 1, Register 1, Bit 0 = 1; DATACLK out of Pin 53. With the phase-locked loop (PLL) enabled and the AD9773 in In one-port mode, P2B14 and P2B15 from input data port two two-port mode, the speed of CLKIN is inherently that of the are redefined as IQSEL and ONEPORTCLK, respectively. The input data rate. In two-port mode, Pin 8 (DATACLK/PLL_ input data in one-port mode is steered to one of the two internal LOCK) can be programmed (Control Register 01h, Bit 0) to data channels based on the logic level of IQSEL. A clock signal, function as either a lock indicator for the internal PLL or as a ONEPORTCLK, is generated by the AD9773 in this mode for clock running at the input data rate. When Pin 8 is used as a the purpose of data synchronization. ONEPORTCLK runs at clock output (DATACLK), its frequency is equal to that of the input interleaved data rate, which is 2× the data rate at the CLKIN. Data at the input ports is latched into the AD9773 on internal input to either channel. the rising edge of the CLKIN. Figure 52 shows the delay, t , OD Test configurations showing the various clocks that are required inherent between the rising edge of CLKIN and the rising edge and generated by the AD9773 with the PLL enabled/disabled of DATACLK, as well as the setup and hold requirements for and in the one-port/two-port modes are given in Figure 101 to the data at Ports 1 and 2. The setup and hold times given in Figure 104. Jumper positions needed to operate the AD9773 Figure 52 are the input data transitions with respect to CLKIN. evaluation board in these modes are given as well. Note that in two-port mode (PLL enabled or disabled), the data rate at the interpolation filter inputs is the same as the input data rate at Ports 1 and 2. The DAC output sample rate in two-port mode is equal to the clock input rate multiplied by the interpolation rate. If zero stuffing is used, another factor of 2 must be included to calculate the DAC sample rate. Rev. D | Page 30 of 60 AD9773 DATACLK INVERSION PLL ENABLED, ONE-PORT MODE (Control Register 02h, Bit 4) (Control Register 02h, Bits [6:1] and 04h, Bits [7:1] By programming this bit, the DATACLK signal shown in In one-port mode, the I and Q channels receive their data from Figure 52 can be inverted. With inversion enabled, t refers to OD an interleaved stream at Digital Input Port 1. The function of the time between the rising edge of CLKIN and the falling edge Pin 32 is defined as an output (ONEPORTCLK) that generates a of DATACLK. No other effect on timing occurs. clock at the interleaved data rate, which is 2× the internal input data rate of the I and Q channels. The frequency of CLKIN is t OD equal to the internal input data rate of the I and Q channels. The selection of the data for the I or Q channel is determined by the state of the logic level at Pin 31 (IQSEL when the AD9773 is CLKIN in one-port mode) on the rising edge of ONEPORTCLK. Under these conditions, IQSEL = 0 latches the data into the I channel on the clock rising edge, while IQSEL = 1 latches the data into the Q channel. It is possible to invert the I and Q selection by DATACLK setting Control Register 02h, Bit 1 to the invert state (Logic 1). Figure 54 illustrates the timing requirements for the data inputs as well as the IQSEL input. Note that the 1× interpolation rate is not available in the one-port mode. DATA AT PORTS 1 AND 2 The DAC output sample rate in one port mode is equal to t = 0.0ns (MAX) CLKIN multiplied by the interpolation rate. If zero stuffing is S t = 2.5ns (MAX) H used, another factor of 2 must be included to calculate the DAC t t S H sample rate. Figure 52. Timing Requirements in Two-Port Input Mode with PLL Enabled ONEPORTCLK INVERSION (Control Register 02h, Bit 2) DATACLK DRIVER STRENGTH By programming this bit, the ONEPORTCLK signal shown in (Control Register 02h, Bit 5) Figure 54 can be inverted. With inversion enabled, t refers to OD The DATACLK output driver strength is capable of driving the delay between the rising edge of the external clock and the >10 mA into a 330 Ω load while providing a rise time of 3 ns. falling edge of ONEPORTCLK. The setup and hold times, tS Figure 53 shows DATACLK driving a 330 Ω resistive load at a and tH, are with respect to the falling edge of ONEPORTCLK. frequency of 50 MHz. By enabling the drive strength option There is no other effect on timing. (Control Register 02h, Bit 5), the amplitude of DATACLK under these conditions increases by approximately 200 mV. 3.0 2.5 2.0 1.5 1.0 0.5 0 DELTA APPROX. 2.8ns –0.5 0 102030 40 50 TIME (ns) Figure 53. DATACLK Driver Capability into 330 Ω at 50 MHz Rev. D | Page 31 of 60 AMPLITUDE (V) 02857-053 02857-052 AD9773 ONEPORTCLK DRIVER STRENGTH PLL DISABLED, TWO-PORT MODE The drive capability of ONEPORTCLK is identical to that of With the PLL disabled, a clock at the DAC output rate must be DATACLK in the two-port mode. Refer to Figure 53 for applied to CLKIN. Internal clock dividers in the AD9773 performance under load conditions. synthesize the DATACLK signal at Pin 8, which runs at the input data rate and can be used to synchronize the input data. t OD Data is latched into input Ports 1 and 2 of the AD9773 on the rising edge of DATACLK. DATACLK speed is defined as the t = 4.0ns (MIN) OD TO 5.5ns (MAX) CLKIN speed of CLKIN divided by the interpolation rate. With zero t = 3.0ns (MAX) S t = –0.5ns (MAX) H stuffing enabled, this division increases by a factor of 2. Figure 55 t = 3.5ns (MAX) IQS t = –1.5ns (MAX) IQH illustrates the delay between the rising edge of CLKIN and the rising edge of DATACLK, as well as tS and tH in this mode. ONEPORTCLK The programmable modes DATACLK inversion and DATACLK driver strength described in the previous section (PLL Enabled, Two-Port Mode) have identical functionality with the PLL disabled. I AND Q INTERLEAVED INPUT DATA AT PORT 1 The data rate clock created by dividing down the DAC clock in this mode can be programmed (via Register 03h, Bit 7) to be output from the SPI_SDO pin, rather than the DATACLK pin. t t S H In some applications, this may improve complex image rejection. When SPI_SDO is used as data rate clock out, t OD IQSEL increases by 1.6 ns. t OD t t IQS IQH Figure 54. Timing Requirements in One-Port Input Mode with the PLL Enabled CLKIN IQ PAIRING (Control Register 02h, Bit 0) DATACLK In one-port mode, the interleaved data is latched into the AD9773 internal I and Q channels in pairs. The order of how the pairs are latched internally is defined by this control register. DATA AT PORTS 1 AND 2 The following is an example of the effect this has on incoming interleaved data. t = 6.5ns (MIN) TO 8.0ns (MAX) OD t t S H t = 5.0ns (MAX) Given the following interleaved data stream, where the data S t = –3.2ns (MAX) H indicates the value with respect to full scale: Figure 55. Timing Requirements in Two-Port I Q I Q I Q I Q I Q Input Mode with PLL Disabled 0.5 0.5 1 1 0.5 0.5 0 0 0.5 0.5 PLL DISABLED, ONE-PORT MODE With the control register set to 0 (I first), the data appears at the In one-port mode, data is received into the AD9773 as an internal channel inputs in the following order in time: interleaved stream on Port 1. A clock signal (ONEPORTCLK), I Channel 0.5 1 0.5 0 0.5 running at the interleaved data rate, which is 2× the input data Q Channel 0.5 1 0.5 0 0.5 rate of the internal I and Q channels, is available for data synchronization at Pin 32. With the control register set to 1 (Q first), the data appears at the internal channel inputs in the following order in time: With PLL disabled, a clock at the DAC output rate must be applied to CLKIN. Internal dividers synthesize the ONEPORTCLK I Channel 0.5 1 0.5 0 0.5 x signal at Pin 32. The selection of the data for the I or Q channel Q Channel y 0.5 1 0.5 0 0.5 is determined by the state of the logic level applied to Pin 31 The values x and y represent the next I value and the previous (IQSEL when the AD9773 is in one-port mode) on the rising Q value in the series. edge of ONEPORTCLK. Rev. D | Page 32 of 60 02857-054 02857-055 AD9773 Under these conditions, IQSEL = 0 latches the data into the I AMPLITUDE MODULATION channel on the clock rising edge, while IQSEL = 1 latches the Given two sine waves at the same frequency, but with a 90° data into the Q channel. It is possible to invert the I and Q phase difference, a point of view in time can be taken such that selection by setting Control Register 02h, Bit 1 to the invert the waveform that leads in phase is cosinusoidal and the state (Logic 1). Figure 56 illustrates the timing requirements for waveform that lags is sinusoidal. Analysis of complex variables the data inputs as well as the IQSEL input. Note that the states that the cosine waveform can be defined as having real 1× interpolation rate is not available in the one-port mode. positive and negative frequency components, while the sine One-port mode is very useful when interfacing with devices waveform consists of imaginary positive and negative frequency such as the Analog Devices AD6622 or AD6623 transmit signal images. This is shown graphically in the frequency domain in processors, in which two digital data channels have been Figure 57. interleaved (multiplexed). –jωt e /2j The programmable modes’ ONEPORTCLK inversion, SINE ONEPORTCLK driver strength and IQ pairing described in the DC PLL Enabled, Two-Port Mode section have identical –jωt e /2j functionality with the PLL disabled. t –jωt –jωt OD e /2 e /2 COSINE CLKIN DC Figure 57. Real and Imaginary Components of Sinusoidal and Cosinusoidal Waveforms Amplitude modulating a baseband signal with a sine or a cosine ONEPORTCLK convolves the baseband signal with the modulating carrier in the frequency domain. Amplitude scaling of the modulated signal reduces the positive and negative frequency images by a factor of 2. This scaling is very important in the discussion of I AND Q INTERLEAVED the various modulation modes. The phase relationship of the INPUT DATA AT PORT 1 modulated signals is dependent on whether the modulating carrier is sinusoidal or cosinusoidal, again with respect to the t t S H reference point of the viewer. Examples of sine and cosine modulation are given in Figure 58. IQSEL –jωt t = 4.0ns (MIN) Ae /2j OD TO 5.5ns (MAX) SINUSOIDAL t = 3.0ns (MAX) S MODULATION t = –1.0ns (MAX) t t H IQS IQH t = 3.5ns (MAX) IQS t = –1.5ns (MAX) IQH DC Figure 56. Timing Requirements in One-Port –jωt Ae /2j Input Mode with DLL Disabled –jωt –jωt Ae /2 Ae /2 DIGITAL FILTER MODES COSINUSOIDAL MODULATION The I and Q data paths of the AD9773 have their own independent half-band FIR filters. Each data path consists of DC three FIR filters, providing up to 8× interpolation for each Figure 58. Baseband Signal, Amplitude Modulated channel. The rate of interpolation is determined by the state of with Sine and Cosine Carriers Control Register 01h, Bits 7 and 6. Figure 2 to Figure 4 show the response of the digital filters when the AD9773 is set to 2×, 4×, and 8× modes. The frequency axes of these graphs have been normalized to the input data rate of the DAC. As the graphs show, the digital filters can provide greater than 75 dB of out-of-band rejection. An online tool is available for quick and easy analysis of the AD9773 interpolation filters in the various modes. Rev. D | Page 33 of 60 02857-056 02857-057 02857-058 AD9773 By comparing the digital domain spectrum to the DAC SIN(x)/x MODULATION, NO INTERPOLATION roll-off, an estimate can be made for the characteristics required With Control Register 01h, Bit 7 and Bit 6 set to 00, the for the DAC reconstruction filter. Note also, per the previous interpolation function on the AD9773 is disabled. Figure 59 to discussion on amplitude modulation, that the spectral com- Figure 62 show the DAC output spectral characteristics of the ponents (where modulation is set to fS/4 or fS/8) are scaled by a AD9773 in the various modulation modes, all with the factor of 2. In the situation where the modulation is fS/2, the interpolation filters disabled. The modulation frequency is modulated spectral components add constructively, and there is determined by the state of Control Register 01h, Bits 5 and 4. no scaling effect. The tall rectangles represent the digital domain spectrum of a baseband signal of narrow bandwidth. The Effects of the Digital Modulation on the DAC Output Spectrum, Interpolation Disabled 0 0 –20 –20 –40 –40 –60 –60 –80 –80 –100 –100 0 0.2 0.4 0.6 0.8 1.0 0 0.2 0.4 0.6 0.8 1.0 f (×f ) f (×f ) OUT DATA OUT DATA Figure 59. No Interpolation, Modulation Disabled Figure 61. No Interpolation, Modulation = f /4 DAC 0 0 –20 –20 –40 –40 –60 –60 –80 –80 –100 –100 0 0.2 0.4 0.6 0.8 1.0 0 0.2 0.4 0.6 0.8 1.0 f (×f ) f (×f ) OUT DATA OUT DATA Figure 60. No Interpolation, Modulation = f /2 Figure 62. No Interpolation, Modulation = f /8 DAC DAC Rev. D | Page 34 of 60 AMPLITUDE (dBFS) AMPLITUDE (dBFS) 02857-060 02857-059 AMPLITUDE (dBFS) AMPLITUDE (dBFS) 02857-062 02857-061 AD9773 Another significant point is that the interpolation filtering is MODULATION, INTERPOLATION = 2× done previous to the digital modulator. For this reason, as With Control Register 01h, Bit 7 and Bit 6 set to 01, the inter- Figure 63 to Figure 66 show, the pass band of the interpolation polation rate of the AD9773 is 2×. Modulation is achieved by filters can be frequency shifted, giving the equivalent of a high- multiplying successive samples at the interpolation filter output pass digital filter. by the sequence (+1, −1). Figure 63 to Figure 66 represent the spectral response of the AD9773 DAC output with 2× Note that when using the fS/4 modulation mode, there is no interpolation in the various modulation modes to a narrow true stop band as the band edges coincide with each other. In the f /8 modulation mode, amplitude scaling occurs over only band baseband signal (again, the tall rectangles in the graphic). S a portion of the digital filter pass band due to constructive The advantage of interpolation becomes clear in Figure 63 to addition over just that section of the band. Figure 66, where it can be seen that the images that would normally appear in the spectrum around the input data rate frequency are suppressed by >70 dB. The Effects of the Digital Modulation on the DAC Output Spectrum, Interpolation = 2× 0 0 –20 –20 –40 –40 –60 –60 –80 –80 –100 –100 0 0.5 1.0 1.5 2.0 0 0.5 1.0 1.5 2.0 f (×f ) f (×f ) OUT DATA OUT DATA Figure 63. 2x Interpolation, Modulation = Disabled Figure 65. 2x Interpolation, Modulation = fDAC/4 0 0 –20 –20 –40 –40 –60 –60 –80 –80 –100 –100 0 0.5 1.0 1.5 2.0 0 0.5 1.0 1.5 2.0 f (×f ) f (×f ) OUT DATA OUT DATA Figure 64. 2x Interpolation, Modulation = f /2 Figure 66. 2x Interpolation, Modulation = f /8 DAC DAC Rev. D | Page 35 of 60 AMPLITUDE (dBFS) AMPLITUDE (dBFS) 02857-064 02857-063 AMPLITUDE (dBFS) AMPLITUDE (dBFS) 02857-066 02857-065 AD9773 Figure 67 to Figure 70 represent the spectral response of the MODULATION, INTERPOLATION = 4× AD9773 DAC output with 4× interpolation in the various With Control Register 01h, Bit 7 and Bit 6 set to 10, the inter- modulation modes to a narrow band baseband signal. polation rate of the AD9773 is 4×. Modulation is achieved by multiplying successive samples at the interpolation filter output by the sequence (0, +1, 0, −1). The Effects of the Digital Modulation on the DAC Output Spectrum Interpolation = 4× 0 0 –20 –20 –40 –40 –60 –60 –80 –80 –100 –100 02 1 34 02 1 34 f (×f ) f (×f ) OUT DATA OUT DATA Figure 67. 4x Interpolation, Modulation Disabled Figure 69. 4x Interpolation, Modulation = fDAC/4 0 0 –20 –20 –40 –40 –60 –60 –80 –80 –100 –100 02 1 34 02 1 34 f (×f ) OUT DATA f (×f ) OUT DATA Figure 68. 4x Interpolation, Modulation = f /2 DAC Figure 70. 4x Interpolation, Modulation = fDAC/8 Rev. D | Page 36 of 60 AMPLITUDE (dBFS) AMPLITUDE (dBFS) 02857-068 02857-067 AMPLITUDE (dBFS) AMPLITUDE (dBFS) 02857-070 02857-069 AD9773 Looking at Figure 63 to Figure 74, the user can see how higher MODULATION, INTERPOLATION = 8× interpolation rates reduce the complexity of the reconstruction With Control Register 01h, Bit 7 and Bit 6 set to 11, the filter needed at the DAC output. It also becomes apparent that interpolation rate of the AD9773 is 8×. Modulation is achieved the ability to modulate by fS/2, fS/4, or fS/8 adds a degree of by multiplying successive samples at the interpolation filter flexibility in frequency planning. output by the sequence (0, +0.707, +1, +0.707, 0, −0.707, −1, +0.707). Figure 71 to Figure 74 represent the spectral response of the AD9773 DAC output with 8× interpolation in the various modulation modes to a narrow band baseband signal. The Effects of the Digital Modulation on the DAC Output Spectrum, Interpolation = 8× 0 0 –20 –20 –40 –40 –60 –60 –80 –80 –100 –100 05 12 3 4678 02 1 34 f (×f ) f (×f ) OUT DATA OUT DATA Figure 71. 8x Interpolation, Modulation Disabled Figure 73. 8x Interpolation, Modulation = fDAC/4 0 0 –20 –20 –40 –40 –60 –60 –80 –80 –100 –100 02 1 34 0 12 3 4 567 8 f (×f ) OUT DATA f (×f ) OUT DATA Figure 72. 8x Interpolation, Modulation = fDAC/2 Figure 74. 8x Interpolation, Modulation = f /8 DAC Rev. D | Page 37 of 60 AMPLITUDE (dBFS) AMPLITUDE (dBFS) 02857-072 02857-071 AMPLITUDE (dBFS) AMPLITUDE (dBFS) 02857-074 02857-073 AD9773 The net effect is to increase the DAC output sample rate by a ZERO STUFFING factor of 2× with the 0 in the SIN(x)/x DAC transfer function (Control Register 01h, Bit 3) occurring at twice the original frequency. A 6 dB loss in As shown in Figure 75, a 0 or null in the output frequency amplitude at low frequencies is also evident, as can be seen in response of the DAC (after interpolation, modulation, and DAC Figure 76. reconstruction) occurs at the final DAC sample rate (f ). This DAC It is important to realize that the zero stuffing option by itself is due to the inherent SIN(x)/x roll-off response in the digital- does not change the location of the images but rather their to-analog conversion. In applications where the desired amplitude, pass-band flatness, and relative weighting. For frequency content is below fDAC/2, this may not be a problem. instance, in the previous example, the pass-band amplitude Note that at fDAC/2, the loss due to SIN(x)/x is 4 dB. In direct RF flatness of the image at 3 × f /4 is now improved to 0.59 dB DATA applications, this roll-off may be problematic due to the while the signal level has increased slightly from −10.5 dBFS to increased pass-band amplitude variation as well as the reduced −8.1 dBFS. amplitude of the desired signal. INTERPOLATING (COMPLEX MIX MODE) Consider an application where the digital data into the AD9773 represents a baseband signal around f /4 with a pass band of (Control Register 01h, Bit 2) DAC f /10. The reconstructed signal out of the AD9773 would DAC In the complex mix mode, the two digital modulators on the experience only a 0.75 dB amplitude variation over its pass AD9773 are coupled to provide a complex modulation function. band. However, the image of the same signal occurring at In conjunction with an external quadrature modulator, this 3 × fDAC/4 suffers from a pass-band flatness variation of 3.93 dB. complex modulation can be used to realize a transmit image This image may be the desired signal in an IF application using rejection architecture. The complex modulation function can one of the various modulation modes in the AD9773. This roll- +jωt −jωt be programmed for e or e to give upper or lower image off of image frequencies can be seen in Figure 59 to Figure 74, rejection. As in the real modulation mode, the modulation where the effect of the interpolation and modulation rate is frequency ω can be programmed via the SPI port for f /2, DAC apparent as well. f /4, and f /8, where f represents the DAC output rate. DAC DAC DAC 10 OPERATIONS ON COMPLEX SIGNALS Truly complex signals cannot be realized outside of a computer ZERO STUFFING 0 ENABLED simulation. However, two data channels, both consisting of real data, can be defined as the real and imaginary components of a –10 complex signal. I (real) and Q (imaginary) data paths are often defined this way. By using the architecture defined in Figure 76, –20 a system can be realized that operates on complex signals, giving a complex (real and imaginary) output. ZERO STUFFING –30 DISABLED +jωt If a complex modulation function (e ) is desired, the real and –40 imaginary components of the system correspond to the real and +jωt imaginary components of e or cosωt and sinωt. As Figure 77 –50 shows, the complex modulation function can be realized by 0 0.5 1.0 1.5 2.0 applying these components to the structure of the complex f , NORMALIZED TO f WITH ZERO STUFFING DISABLED (Hz) OUT DATA system defined in Figure 76. Figure 75. Effect of Zero Stuffing on DAC’s SIN(x)/x Response a(t) c(t)× b(t) + d× b(t) INPUT OUTPUT To improve upon the pass-band flatness of the desired image, COMPLEX FILTER the zero stuffing mode can be enabled by setting the control = (c + jd) register bit to Logic 1. This option increases the ratio of IMAGINARY b(t) INPUT OUTPUT b(t)× a(t) + c× b(t) f /f by a factor of 2 by doubling the DAC sample rate and DAC DATA inserting a midscale sample (that is, 1000 0000 0000 0000) after Figure 76. Realization of a Complex System every data sample originating from the interpolation filter. This is important as it affects the PLL divider ratio needed to keep the VCO within its optimum speed range. Note that the zero stuffing takes place in the digital signal chain at the output of the digital modulator, before the DAC. Rev. D | Page 38 of 60 SIN (X)/X ROLL-OFF (dBFS) 02857-075 02857-076 AD9773 INPUT INPUT (REAL) (REAL) OUTPUT OUTPUT (REAL) INPUT INPUT (IMAGINARY) (IMAGINARY) SINωt 90° 90° COSωt Figure 78. Quadrature Modulator OUTPUT (IMAGINARY) The entire upconversion from baseband to transmit frequency is represented graphically in Figure 79. The resulting spectrum –jωt e = COSωt + jSINωt shown in Figure 79 represents the complex data consisting of the Figure 77. Implementation of a Complex Modulator baseband real and imaginary channels, now modulated onto orthogonal (cosine and negative sine) carriers at the transmit COMPLEX MODULATION AND IMAGE REJECTION frequency. It is important to remember that in this application (two OF BASEBAND SIGNALS baseband data channels) the image rejection is not dependent on In traditional transmit applications, a two-step upconversion is the data at either of the AD9773 input channels. In fact, image done in which a baseband signal is modulated by one carrier to rejection still occurs with either one or both of the AD9773 input an intermediate frequency (IF) and then modulated a second channels active. Note that by changing the sign of the sinusoidal time to the transmit frequency. Although this approach has multiplying term in the complex modulator, the upper sideband several benefits, a major drawback is that two images are image could be suppressed while passing the lower one. This is created near the transmit frequency. Only one image is needed, +jωt easily done in the AD9773 by selecting the e bit (Register 01h, Bit the other being an exact duplicate. Unless the unwanted image 1). In purely complex terms, Figure 79 represents the two-stage is filtered, typically with analog components, transmit power is upconversion from complex baseband to carrier. wasted and the usable bandwidth available in the system is reduced. A more efficient method of suppressing the unwanted image can be achieved by using a complex modulator followed by a quadrature modulator. Figure 78 is a block diagram of a quadrature modulator. Note that it is in fact the real output half of a complex modulator. The complete upconversion can actually be referred to as two complex upconversion stages, the real output of which becomes the transmitted signal. Rev. D | Page 39 of 60 02857-077 02857-078 AD9773 REAL CHANNEL (OUT) A/2 A/2 1 –f f C C REAL CHANNEL (IN) A –B/2J B/2J DC –f f C C COMPLEX TO QUADRATURE IMAGINARY CHANNEL (OUT) MODULATOR MODULATOR –A/2J A/2J IMAGINARY CHANNEL (IN) –f –f C C B DC B/2 B/2 –f f C C A/4 + B/4J A/4 – B/4J A/4 + B/4J A/4 – B/4J 2 –f f Q Q –f – f –f + f f – f f + f Q C Q C Q C Q C OUT REAL –A/4 – B/4J A/4 – B/4J A/4 + B/4J –A/4 + B/4J QUADRATURE MODULATOR –f f Q Q IMAGINARY REJECTED IMAGES A/2 + B/2J A/2 – B/2J –f f Q Q 1 f = COMPLEX MODULATION FREQUENCY C 2 f = QUADRATURE MODULATION FREQUENCY Q Figure 79. Two-Stage Upconversion and Resulting Image Rejection Rev. D | Page 40 of 60 02857-079 AD9773 COMPLEX BASEBAND A system in which multiple baseband signals are complex SIGNAL modulated and then applied to the AD9773 real and imaginary 1 inputs followed by a quadrature modulator is shown in j(ω1 +ω2)t OUTPUT = REAL × e Figure 82, which also describes the transfer function of this system and the spectral output. Note the similarity of the 1/2 1/2 transfer functions given in Figure 82 and Figure 80. Figure 82 = REAL adds an additional complex modulator stage for the purpose of –ω1–ω2DC ω1 +ω2 FREQUENCY summing multiple carriers at the AD9773 inputs. Also, as in Figure 79, the image rejection is not dependent on the real or Figure 80. Two-Stage Complex Upconversion imaginary baseband data on any channel. Image rejection on a IMAGE REJECTION AND SIDEBAND SUPPRESSION channel occurs if either the real or imaginary data, or both, is OF MODULATED CARRIERS present on the baseband channel. As shown in Figure 79, image rejection can be achieved by It is important to remember that the magnitude of a complex applying baseband data to the AD9773 and following the signal can be 1.414× the magnitude of its real or imaginary AD9773 with a quadrature modulator. To process multiple components. Due to this 3 dB increase in signal amplitude, the carriers while still maintaining image reject capability, each real and imaginary inputs to the AD9773 must be kept at least carrier must be complex modulated. As Figure 81 shows, single 3 dB below full scale when operating with the complex or multiple complex modulators can be used to synthesize modulator. Overranging in the complex modulator results in complex carriers. These complex carriers are then summed and severe distortion at the DAC output. applied to the real and imaginary inputs of the AD9773. BASEBAND CHANNEL 1 R(1) REAL INPUT COMPLEX MULTICARRIER MODULATOR 1 REAL OUTPUT = IMAGINARY INPUT R(1) R(1) + R(2) + . . .R(N) (TO REAL INPUT OF AD9773) BASEBAND CHANNEL 2 R(2) REAL INPUT COMPLEX MODULATOR 2 MULTICARRIER IMAGINARY INPUT R(2) IMAGINARY OUTPUT = I(1) + I(2) + . . .I(N) (TO IMAGINARY INPUT OF AD9773) BASEBAND CHANNEL N R(N) = REAL OUTPUT OF N R(N) REAL INPUT I(N) = IMAGINARY OUTPUT OF N COMPLEX MODULATOR N IMAGINARY INPUT R(N) Figure 81. Synthesis of Multicarrier Complex Signal MULTIPLE BASEBAND CHANNELS REAL REAL REAL REAL MULTIPLE AD9773 QUADRATURE COMPLEX COMPLEX MODULATOR MODULATORS MODULATOR FREQUENCY =ω IMAGINARY IMAGINARY IMAGINARY Q FREQUENCY =ω ,ω ...ω 1 2 N FREQUENCY =ω C COMPLEX BASEBAND SIGNAL × OUTPUT = REAL j(ω +ω +ω )t e N C Q –ω –ω –ω ω +ω +ω DC 1 C Q 1 C Q REJECTED IMAGES Figure 82. Image Rejection with Multicarrier Signals Rev. D | Page 41 of 60 02857-080 02857-081 02857-082 AD9773 The complex carrier synthesized in the AD9773 digital modu- Region C lator is accomplished by creating two real digital carriers in Region C is most accurately described as a downconversion, as quadrature. Carriers in quadrature cannot be created with the jωt the modulating carrier is −e . If viewed as a complex signal, only modulator running at fDAC/2. As a result, complex modulation the images in Region C remain. This image appears on the real only functions with modulation rates of fDAC/4 and fDAC/8. and imaginary outputs of the AD9773, as well as on the output of Regions A and B of Figure 83 to Figure 88 are the result of the the quadrature modulator, where the center of the spectral plot complex signal described previously, when complex modulated now represents the quadrature modulator LO and the horizontal jωt in the AD9773 by +e . Regions C and D are the result of the scale represents the frequency offset from this LO. complex signal described previously, again with positive fre- Region D jωt quency components only, modulated in the AD9773 by −e . Region D is the image (complex conjugate) of Region C. If a The analog quadrature modulator after the AD9773 inherently spectrum analyzer is used to view the real or imaginary DAC jωt modulates by +e . outputs of the AD9773, Region D appears in the spectrum. Region A However, on the output of the quadrature modulator, Region D Region A is a direct result of the upconversion of the complex is rejected. signal near baseband. If viewed as a complex signal, only the Figure 89 to Figure 96 show the measured response of the AD9773 images in Region A remain. The complex Signal A, consisting and AD8345 given the complex input signal to the AD9773 in of positive frequency components only in the digital domain, Figure 89. The data in these graphs was taken with a data rate of has images in the positive odd Nyquist zones (1, 3, 5, …), as 12.5 MSPS at the AD9773 inputs. The interpolation rate of 4× or 8× well as images in the negative even Nyquist zones. The gives a DAC output data rate of 50 MSPS or 100 MSPS. As a result, appearance and rejection of images in every other Nyquist the high end of the DAC output spectrum in these graphs is the zone becomes more apparent at the output of the quadrature first null point for the SIN(x)/x roll-off, and the asymmetry of the modulator. The A images appear on the real and the imaginary DAC output images is representative of the SIN(x)/x roll-off over outputs of the AD9773, as well as on the output of the quadrature the spectrum. The internal PLL was enabled for these results. In modulator, where the center of the spectral plot now represents addition, a 35 MHz third-order low-pass filter was used at the the quadrature modulator LO and the horizontal scale now AD9773/AD8345 interface to suppress DAC images. represents the frequency offset from this LO. An important point can be made by looking at Figure 91 and Region B Figure 93. Figure 91 represents a group of positive frequencies Region B is the image (complex conjugate) of Region A. If a modulated by complex +fDAC/4, while Figure 93 represents a spectrum analyzer is used to view the real or imaginary DAC group of negative frequencies modulated by complex −fDAC/4. outputs of the AD9773, Region B appears in the spectrum. When looking at the real or imaginary outputs of the AD9773, However, on the output of the quadrature modulator, Region B as shown in Figure 91 and Figure 93, the results look identical. is rejected. However, the spectrum analyzer cannot show the phase relationship of these signals. The difference in phase between the two signals becomes apparent when they are applied to the AD8345 quadrature modulator, with the results shown in Figure 92 and Figure 94. Rev. D | Page 42 of 60 AD9773 0 0 –20 –20 D A BC D A BC –40 –40 DA B CD A B C –60 –60 –80 –80 –100 –100 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 (LO) (LO) f (×f ) f (×f ) OUT DATA OUT DATA Figure 83. 2x Interpolation, Complex f /4 Modulation Figure 86. 2x Interpolation, Complex f /8 Modulation DAC DAC 0 0 –20 –20 DA B C D A B C –40 –40 DA B C D A B C –60 –60 –80 –80 –100 –100 –4.0 –3.0 –2.0 –1.0 0 1.0 2.0 3.0 4.0 –4.0 –3.0 –2.0 –1.0 0 1.0 2.0 3.0 4.0 (LO) (LO) f (×f ) f (×f ) OUT DATA OUT DATA Figure 84. 4x Interpolation, Complex f /4 Modulation DAC Figure 87. 4x Interpolation, Complex fDAC/8 Modulation 0 0 –20 –20 DA B C DA B C DA BC D A BC –40 –40 –60 –60 –80 –80 –100 –100 –8.0 –6.0 –4.0 –2.0 0 2.0 4.0 6.0 8.0 –8.0 –6.0 –4.0 –2.0 0 2.0 4.0 6.0 8.0 (LO) (LO) f (×f ) f (×f ) OUT DATA OUT DATA Figure 85. 8x Interpolation, Complex f /4 Modulation DAC Figure 88. 8x Interpolation, Complex fDAC/8 Modulation Rev. D | Page 43 of 60 02857-085 02857-084 02857-083 02857-088 02857-087 02857-086 AD9773 0 0 –10 –10 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 –100 02 1003040 02 1003040 FREQUENCY (MHz) FREQUENCY (MHz) Figure 91. AD9773 Real DAC Output of Complex Input Signal Near Figure 89. AD9773 Real DAC Output of Complex Input Signal Near Baseband Baseband (Positive Frequencies Only), Interpolation = 4x, (Positive Frequencies Only), Interpolation = 4x, No Modulation in AD9773 Complex Modulation in AD9773 = +f /4 DAC 0 0 –10 –10 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 –100 750 760 770 780 790 800 810 820 830 750 760 770 780 790 800 810 820 830 FREQUENCY (MHz) FREQUENCY (MHz) Figure 90. AD9773 Complex Output from Figure 89, Now Quadrature Modulated Figure 92. AD9773 Complex Output from Figure 91, Now Quadrature Modulated by AD8345 (LO = 800 MHz) by AD8345 (LO = 800 MHz) Rev. D | Page 44 of 60 AMPLITUDE (dBm) AMPLITUDE (dBm) 02857-090 02857-089 AMPLITUDE (dBm) AMPLITUDE (dBm) 02857-092 02857-091 AD9773 0 0 –10 –10 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 –100 02 1003040 04 2006080 FREQUENCY (MHz) FREQUENCY (MHz) Figure 95. AD9773 Real DAC Output of Complex Input Signal Near Figure 93. AD9773 Real DAC Output of Complex Input Signal Near Baseband (Positive Frequencies Only), Interpolation = 8x, Baseband (Negative Frequencies Only), Interpolation = 4x, Complex Modulation in AD9773 = +f /8 Complex Modulation in AD9773 = −fDAC/4 DAC 0 0 –10 –10 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 –100 700 720 740 760 780 800 820 840 860 750 760 770 780 790 800 810 820 830 FREQUENCY (MHz) FREQUENCY (MHz) Figure 96. AD9773 Complex Output from Figure 95, Now Quadrature Modulated Figure 94. AD9773 Complex Output from Figure 93, Now Quadrature Modulated by AD8345 (LO = 800 MHz) by AD8345 (LO = 800 MHz) Rev. D | Page 45 of 60 AMPLITUDE (dBm) AMPLITUDE (dBm) 02857-094 02857-093 AMPLITUDE (dBm) AMPLITUDE (dBm) 02857-096 02857-095 AD9773 APPLYING THE OUTPUT CONFIGURATIONS For the typical situation, where IOUTFS = 20 mA and RA and RB The following sections illustrate typical output configurations both equal 50 Ω, the equivalent circuit values become for the AD9773. Unless otherwise noted, it is assumed that IOUTFS is set to a nominal 20 mA. For applications requiring VSOURCE = 2 V p-p optimum dynamic performance, a differential output ROUT = 100 Ω configuration is suggested. A simple differential output can be Note that the output impedance of the AD9773 DAC itself achieved by converting I and I to a voltage output by OUTA OUTB is greater than 100 kΩ and typically has no effect on the terminating them to AGND via equal value resistors. This type of impedance of the equivalent output circuit. configuration may be useful when driving a differential voltage DIFFERENTIAL COUPLING USING A input device such as a modulator. If a conversion to a single- TRANSFORMER ended signal is desired and the application allows for ac coupling, an RF transformer may be useful, or if power gain is required, an An RF transformer can be used to perform a differential-to- op amp may be used. The transformer configuration provides single-ended signal conversion, as shown in Figure 98. A optimum high frequency noise and distortion performance. The differentially coupled transformer output provides the optimum differential op amp configuration is suitable for applications distortion performance for output signals whose spectral content requiring dc coupling, signal gain, and/or level shifting within the lies within the transformer’s pass band. An RF transformer such as bandwidth of the chosen op amp. the Mini-Circuits T1-1T provides excellent rejection of common- mode distortion (that is, even-order harmonics) and noise over a A single-ended output is suitable for applications requiring a wide frequency range. It also provides electrical isolation and the unipolar voltage output. A positive unipolar output voltage ability to deliver twice the power to the load. Transformers with results if IOUTA and/or IOUTB is connected to a load resistor, RLOAD, different impedance ratios may also be used for impedance referred to AGND. This configuration is most suitable for a matching purposes. single-supply system requiring a dc-coupled, ground-referred output voltage. Alternatively, an amplifier could be configured MINI-CIRCUITS T1-1T as an I-V converter, thus converting I or I into a OUTA OUTB I OUTA R negative unipolar voltage. This configuration provides the best DAC LOAD I OUTB DAC dc linearity as IOUTA or IOUTB are maintained at ground or virtual ground. Figure 98. Transformer-Coupled Output Circuit UNBUFFERED DIFFERENTIAL OUTPUT, EQUIVALENT CIRCUIT The center tap on the primary side of the transformer must be connected to AGND to provide the necessary dc current path In many applications, it may be necessary to understand the for both I and I . The complementary voltages appearing OUTA OUTB equivalent DAC output circuit. This is especially useful when at IOUTA and IOUTB (that is, VOUTA and VOUTB) swing symmetrically designing output filters or when driving inputs with finite input around AGND and should be maintained within the specified impedances. Figure 97 illustrates the output of the AD9773 and output compliance range of the AD9773. A differential resistor, the equivalent circuit. A typical application where this information RDIFF, may be inserted in applications where the output of the may be useful is when designing an interface filter between transformer is connected to the load, R , via a passive LOAD the AD9773 and the Analog Devices AD8345 quadrature reconstruction filter or cable. R is determined by the DIFF modulator. transformer’s impedance ratio and provides the proper source AD9773 termination that results in a low VSWR. Note that approximately I V + OUTA OUT half the signal power dissipates across RDIFF. I V – OUTB OUT R R B A R + R A B V = SOURCE V OUT I × (R + R ) OUTFS A B (DIFFERENTIAL) p-p Figure 97. DAC Output Equivalent Circuit Rev. D | Page 46 of 60 02857-097 02857-098 AD9773 DAC Compliance Voltage/Input Common-Mode Range DIFFERENTIAL COUPLING USING AN OP AMP The dynamic range of the AD9773 is optimal when the DAC An op amp can also be used to perform a differential-to-single- outputs swing between ±1.0 V. The input common-mode range ended conversion, as shown in Figure 99. This has the added of the AD8345, at 0.7 V, allows optimum dynamic range to be benefit of providing signal gain as well. In Figure 99, the achieved in both components. AD9773 is configured with two equal load resistors, R , of LOAD 25 Ω. The differential voltage developed across I and I is OUTA OUTB Gain/Offset Adjust converted to a single-ended signal via the differential op amp The matching of the DAC output to the common-mode input configuration. An optional capacitor can be installed across of the AD8345 allows the two components to be dc-coupled, IOUTA and IOUTB, forming a real pole in a low-pass filter. The with no level shifting necessary. The combined voltage offset of addition of this capacitor also enhances the op amp’s distortion the two parts can therefore be compensated via the AD9773 performance by preventing the DAC’s fast slewing output from programmable offset adjust. This allows excellent LO cancel- overloading the input of the op amp. lation at the AD8345 output. The programmable gain adjust 500Ω allows for optimal image rejection as well. 225Ω I The AD9773 evaluation board includes an AD8345 and OUTA AD8021 DAC recommended interface (Figure 105 and Figure 106). On the I OUTB output of the AD9773, R9 and R10 convert the DAC output C OPT 225Ω AVDD current to a voltage. R16 may be used to execute a slight R OPT 25Ω 25Ω 500Ω 225Ω common-mode shift if necessary. The (now voltage) signal is applied to a low-pass reconstruction filter to reject DAC images. Figure 99. Op Amp-Coupled Output Circuit The components installed on the AD9773 provide a 35 MHz cutoff but may be changed to fit the application. A balun (Mini- The common-mode (and second-order distortion) rejection of Circuits ADTL1-12) is used to cross the ground plane boundary this configuration is typically determined by the resistor to the AD8345. Another balun (Mini-Circuits ETC1-1-13) is matching. The op amp used must operate from a dual supply used to couple the LO input of the AD8345. The interface since its output is approximately ±1.0 V. A high speed amplifier, requires a low ac impedance return path from the AD8345, so a such as the AD8021, capable of preserving the differential single connection between the AD9773 and AD8345 ground performance of the AD9773 while meeting other system level planes is recommended. objectives (for example, cost, power) is recommended. The op The performance of the AD9773 and AD8345 in an image amp’s differential gain, its gain setting resistor values, and full- reject transmitter, reconstructing three WCDMA carriers, can scale output swing capabilities should all be considered when be seen in Figure 100. The LO of the AD8345 in this application optimizing this circuit. R is necessary only if level shifting is OPT is 800 MHz. Image rejection (50 dB) and LO feedthrough required on the op amp output. In Figure 99, AVDD, which is (−78 dBFS) have been optimized with the programmable the positive analog supply for both the AD9773 and the op amp, features of the AD9773. The average output power of the digital is also used to level shift the differential output of the AD9773 waveform for this test was set to −15 dBFS to account for the to midsupply (for example, AVDD/2). peak-to-average ratio of the WCDMA signal. INTERFACING THE AD9773 WITH THE AD8345 0 QUADRATURE MODULATOR –10 The AD9773 architecture was defined to operate in a transmit –20 signal chain using an image reject architecture. A quadrature –30 modulator is also required in this application and should be designed to meet the output characteristics of the DAC as much –40 as possible. The AD8345 from Analog Devices meets many of –50 the requirements for interfacing with the AD9773. As with any –60 DAC output interface, there are a number of issues that have to –70 be resolved. The following sections list some of these major issues. –80 –90 –100 762.5 782.5 802.5 822.5 842.5 FREQUENCY (MHz) Figure 100. AD9773/AD8345 Synthesizing a Three-Carrier WCDMA Signal at an LO of 800 MHz Rev. D | Page 47 of 60 02857-099 AMPLITUDE (dBm) 02857-100 AD9773 EVALUATION BOARD DAC DIFFERENTIAL OUTPUTS The AD9773 evaluation board allows easy configuration of the various modes, programmable via the SPI port. Software is Transformers T2 and T3 should be in place. Note that the lower available for programming the SPI port from Windows 95®, band of operation for these transformers is 300 kHz to 500 kHz. Windows 98®, or Windows NT®/2000. The evaluation board Jumpers 4, 8, 13 to 17, and 28 to 30 should remain unsoldered. also contains an AD8345 quadrature modulator and support The outputs are taken from S3 and S4. circuitry that allows the user to optimally configure the AD9773 USING THE AD8345 in an image reject transmit signal chain. Remove Transformers T2 and T3. Jumpers JP4 and Jumpers 28 Figure 101 through Figure 104 describe how to configure the to 30 should remain unsoldered. Jumpers 13 to 16 should be evaluation board in the one-port and two-port input modes soldered. The desired components for the low-pass interface with the PLL enabled and disabled. Refer to Figure 105 through filters L6, L7, C55, and C81 should be in place. The LO drive is Figure 114, the schematics, and the layout for the AD9773 connected to the AD8345 via J10 and the balun T4; AD8345 evaluation board for the jumper locations described below. The output is taken from J9. AD9773 outputs can be configured for various applications by referring to the following instructions. DAC SINGLE-ENDED OUTPUTS Remove transformers T2 and T3. Solder jumper link JP4 or JP28 to look at the DAC1 outputs. Solder jumper link JP29 or JP30 to look at the DAC2 outputs. Jumper 8 and Jumpers 13 to 17 should remain unsoldered. Jumpers JP35 to JP38 may be used to ground one of the DAC outputs while the other is measured single-ended. Optimum single-ended distortion performance is typically achieved in this manner. The outputs are taken from S3 and S4. Rev. D | Page 48 of 60 AD9773 LECROY SIGNAL GENERATOR PULSE TRIG INP GENERATOR DATACLK CLK+/CLK– INPUT CLOCK AWG2021 40-PIN RIBBON CABLE OR DAC1, DB11–DB0 DG2020 DAC2, DB11–DB0 AD9773 JUMPER CONFIGURATION FOR TWO-PORT MODE, PLL ON SOLDERED/IN UNSOLDERED/OUT × JP1 – JP2 – × JP3 – × JP5 – × JP6 – × × JP12 – JP24 – × JP25 – × JP26 – × JP27 – × × JP31 – JP32 – × JP33 – × NOTES 1. TO USE PECL DRIVER (U8), SOLDER JP41 AND JP42 AND REMOVE TRANSFORMER T1. 2. IN TWO-PORT MODE, IF DATACLK/PLL_LOCK IS PROGRAMMED TO OUTPUT PIN 8, JP25 AND JP39 SHOULD BE SOLDERED. IF DATACLK/PLL_LOCK IS PROGRAMMED TO OUTPUT PIN 53, JP46 AND JP47 SHOULD BE SOLDERED. FOR MORE INFORMATION, SEE THE TWO-PORT DATA INPUT MODE SECTION. Figure 101. Test Configuration for AD9773 in Two-Port Mode with PLL Enabled, Signal Generator Frequency = Input Data Rate, DAC Output Data Rate = Signal Generator Frequency × Interpolation Rate LECROY SIGNAL GENERATOR TRIG PULSE INP GENERATOR ONEPORTCLK CLK+/CLK– INPUT CLOCK AWG2021 OR DAC1, DB11–DB0 DG2020 DAC2, DB11–DB0 AD9773 JUMPER CONFIGURATION FOR ONE-PORT MODE, PLL ON SOLDERED/IN UNSOLDERED/OUT JP1 – × JP2 – × JP3 – × JP5 – × JP6 – × JP12 – × JP24 – × JP25 – × JP26 – × JP27 – × JP31 – × JP32 – × JP33 – × NOTES 1. TO USE PECL DRIVER (U8), SOLDER JP41 AND JP42 AND REMOVE TRANSFORMER T1. Figure 102. Test Configuration for AD9773 in One-Port Mode with PLL Enabled, Signal Generator Frequency = One-Half Interleaved Input Data Rate, ONEPORTCLK = Interleaved Input Data Rate, DAC Output Data Rate = Signal Generator Frequency × Interpolation Rate Rev. D | Page 49 of 60 02857-102 02857-101 AD9773 LECROY SIGNAL GENERATOR PULSE TRIG INP GENERATOR DATACLK CLK+/CLK– INPUT CLOCK AWG2021 40-PIN RIBBON CABLE OR DAC1, DB11–DB0 DG2020 DAC2, DB11–DB0 AD9773 JUMPER CONFIGURATION FOR TWO-PORT MODE, PLL OFF SOLDERED/IN UNSOLDERED/OUT JP1 – × JP2 – × JP3 – × JP5 – × JP6 – × JP12 – × JP24 – × JP25 – × JP26 – × JP27 – × JP31 – × JP32 – × JP33 – × NOTES 1. TO USE PECL DRIVER (U8), SOLDER JP41 AND JP42 AND REMOVE TRANSFORMER T1. 2. IN TWO-PORT MODE, IF DATACLK/PLL_LOCK IS PROGRAMMED TO OUTPUT PIN 8, JP25 AND JP39 SHOULD BE SOLDERED. IF DATACLK/PLL_LOCK IS PROGRAMMED TO OUTPUT PIN 53, JP46 AND JP47 SHOULD BE SOLDERED. FOR MORE INFORMATION, SEE THE TWO-PORT DATA INPUT MODE SECTION. Figure 103. Test Configuration for AD9773 in Two-Port Mode with PLL Disabled, DAC Output Data Rate = Signal Generator Frequency, DATACLK = Signal Generator Frequency/Interpolation Rate LECROY SIGNAL GENERATOR PULSE TRIG GENERATOR INP ONEPORTCLK CLK+/CLK– INPUT CLOCK AWG2021 OR DAC1, DB11–DB0 DG2020 AD9773 DAC2, DB11–DB0 JUMPER CONFIGURATION FOR ONE-PORT MODE, PLL OFF SOLDERED/IN UNSOLDERED/OUT JP1 – × JP2 – × JP3 – × JP5 – × JP6 – × JP12 – × JP24 – × JP25 – × JP26 – × JP27 – × JP31 – × JP32 – × JP33 – × NOTES 1. TO USE PECL DRIVER (U8), SOLDER JP41 AND JP42 AND REMOVE TRANSFORMER T1. Figure 104. Test Configuration for AD9773 in One-Port Mode with PLL Disabled, DAC Output Data Rate = Signal Generator Frequency, ONEPORTCLK = Interleaved Input Data Rate = 2x Signal Generator Frequency/Interpolation Rate Rev. D | Page 50 of 60 02857-104 02857-103 AD9773 Figure 105. AD8345 Circuitry on AD9773 Evaluation Board Rev. D | Page 51 of 60 L6 R32 C79 DNP 51Ω DNP O2N LC0805 RC0603 CC0603 POWER INPUT FILTERS C55 C81 CC0805 CC0805 JP19 DNP DNP L8 LC0805 RC0603 RC0603 FERRITE VDDMIN O2P VDDM W11 LC1210 L7 R33 R34 1 3 JP45 DNP 51Ω DNP P C28 + C32 DCASE CC0805 16V JP43 JP44 T5 0.1μF 22μF MODULATED OUTPUT S DGND2 C74 R23 W12 DGND2; 3, 4, 5 64 100pF 0Ω VDDM 2 J9 CC0603 RC0603 L3 TP2 2 C72 C35 C75 + JP9 FERRITE RED BCASE CC0603 16 15 14 13 12 11 10 9 DVDD_IN 10V 100pF CC0603 0.1μF 2 J8 DVDD LC1210 10μF C65 C66 + + VDDM C67 DCASE CC0805 DCASE 16V 16V 0.1μF AD8345 U2 2 22μF 22μF R26 DGND J5 1kΩ TP3 1 2 3 4 5 6 7 8 BLK JP18 L2 TP4 FERRITE JP10 RED 2 AVDD_IN LOCAL OSC INPUT C78 J4 AVDD C76 LC1210 0.1μF R28 100pF DGND2; 3, 4, 5 ETC1-1-13 0Ω 3 4 C64 C61 + + C68 J10 RC0603 CC0603 DCASE 16V CC0805 DCASE 16V R30 0.1μF SP 22μF 22μF 2 2 DNP CC0603 AGND 1 5 T4 J6 C77 2 TP5 JP7 100pF BLK 4 6 L1 TP6 S JP21 FERRITE JP11 RED CLKVDD_IN T6 J3 CLKVDD LC1210 2 P C63 C62 + + 31 C69 DCASE CC0805 DCASE 16V 16V 0.1μF 22μF 22μF R35 C80 L4 CGND 51Ω DNP DNP J7 O1N c TP7 LC0805 RC0603 CC0603 BLK C54 C73 CC0805 JP20 DNP L5 DNP R36 DNP 51Ω RC0603 O1P LC0805 RC0603 R37 DNP 02857-105 CC0805 ADTL1-12 CC0603 ADTL1-12 IBBP QBBP IBBN QBBN G1A G4B G1B G4A LOIN VPS2 LOIP VOUT VPS1 G3 ENBL G2 RC0603 RC0603 AD9773 Figure 106. AD9773 Clock, Power Supplies, and Output Circuitry Rev. D | Page 52 of 60 R2 R3 JP8 1kΩ 1kΩ DVDD R10 C70 51kΩ 0.1μF RC0603 RC0603 C36 C37 C38 C39 C40 C41 CLKVDD CC0805 CC0805 CC0805 CC0805 CC0805 CC0805 RC0603 C1+ C12 C11 C42 C27 CC0603 BCASE CC0603 CC0603 CC0603 CC0603 10μF 0.1μF 0.1μF 0.1μF 0.1μF 0.1μF 0.1μF R9 R16 6.3V 0.1μF 0.1μF 0.1μF 1pF RC0603 RC0603 51kΩ 10kΩ TP15 C13 JP4 JP22 c WHT 0.1μF c 1 80 VDDC1 VDDA6 AVDD 6 1 JP28 2 LF VSSA10 79 5 2 C20 C19 C14 C2 + 3 VDDC2 VDDA5 78 J37 CLKP AGND; 3, 4, 5 CC0603 CC0603 CC0603 BCASE 10μF T2 4 3 R1 4 77 VSSC1 VSSA9 0.1μF 0.1μF 0.1μF 6.3V JP23 OUT1 CLKN 3 4 200Ω JP1 S3 5 CLKP VDDA4 76 T1 2 5 6 75 T1-1T CLKN VSSA8 JP2 RC1206 1 6 J35 C58 R42 JP33 7 74 VSSC2 VSSA7 ADCLK R38 10kΩ DNP 49.9kΩ 8 DCLK-PLLL IOUT1P 73 c T1-1T CLKIN 9 72 VSSD1 IOUT1N C58 O1N JP39 CC0603 S1 DNP 71 JP13 10 VDDD1 VSSA6 C57 O1P DVDD DNP c 11 VSSA5 70 JP15 P1D15 ACLKX CGND; 3, 4, 5 C10 C26 + AD15 O2N BCASE CC0603 10μF 12 IOUT2P 69 P1D14 JP16 AD14 O2P 6.3V 0.001μF JP24 13 P1D13 IOUT2N 68 JP14 C59 AD13 CC0603 DNP 14 P1D12 VSSA4 67 AVDD JP36 AD12 74VCX86 CX3 15 66 P1D11 VSSA3 AD11 12 JP25 JP38 JP29 CX2 11 16 P1D10 VDDA3 65 U3 AD10 13 C18 C17 C15 C3 + CX1 17 VSSD2 VSSA2 64 CC0805 CC0603 CC0603 BCASE 10μF JP30 DVDD; 14 18 VDDD2 63 U1 VDDA2 0.1μF 0.1μF 0.1μF 6.3V DGND; 7 DVDD JP12 19 P1D9 VSSA1 62 T3 AGND; 3, 4, 5 C9 C25 + TP14 AD09 R40 BCASE CC0603 10μF OUT 2 20 VDDA1 61 3 4 DVDD P1D8 TP11 TP10 TP9 TP8 WHT 5kΩ AD08 S4 6.3V 0.001μF WHT WHT WHT WHT 21 FSADJ1 60 DGND; 3, 4, 5 P1D7 2 5 AD07 DATACLK RC0603 22 P1D6 FSADJ2 59 1 6 R43 R5 AD06 S2 23 P1D5 REFOUT 58 49.9kΩ 49.9Ω AD05 T1-1T JP3 24 57 P1D4 JP17 RESET AD04 R7 R8 R12 C70 25 VSSD3 SP-CSB 56 C16 C4 2kΩ 1kΩ + SPCSP 51kΩ 0.1μF C29 CC0603 BCASE 10μF 0.01% 0.01% 26 55 VDDD3 SP-CLK 0.1μF R6 RC0603 CC0603 DVDD SPCLK 0.1μF 6.3V 54 27 P1D3 SP-SDI 1kΩ C8 C24 R11 R17 + SPSDI AD03 BCASE CC0603 RC0603 RC0603 10μF 28 P1D2 SP-SDO 53 51kΩ 10kΩ AD02 SPSDO 6.3V 0.001μF 29 52 P1D1 VSSD6 AD01 30 VDDD6 51 P1D0 AD00 JP5 DV DVDD DD 31 P2D15-IQSEL P2D0 50 BD15 BD00 32 49 P2D14-OPCLK P2D1 C21 C5 + BD01 JP27 CC0603 BCASE 10μF 33 P2D13 P2D2 48 R39 OPCLK_3 BD13 BD02 6.3V 0.001μF JP32 34 47 1kΩ P2D12 P2D3 BD12 BD03 DGND; 3, 4, 5 35 46 VSSD4 P2D4 JP40 BD04 JP26 36 VDDD4 P2D5 45 S6 DVDD BD05 BD14 IQ 74VCX86 JP47 37 44 P2D11 VSSD5 C7 C23 9 IQ + BD11 JP46 8 74VCX86 JP31 BCASE CC0603 SPSDO 10μF 43 38 P2D10 VDDD5 12 U4 IQ 10 BD10 DVDD 11 6.3V 0.001μF OPCLK 39 P2D9 42 U4 13 P2D6 BD06 BD09 DVDD; 14 40 41 JP34 P2D8 P2D7 C22 C6 + BD08 BD07 DVDD; 14 CC0603 BCASE DGND; 7 10μF OPCLK DGND; 7 0.001μF 6.3V AD9773+TSP S5 C45 0.01μF AGND; 3, 4, 5 02857-106 CC0805 CC0603 CC0605 RC0603 RC0603 CC0603 RC1206 CC0603 AD9773 Figure 107. AD9773 Evaluation Board Input (A Channel) and Clock Buffer Circuitry Rev. D | Page 53 of 60 R1 R2 R3 R4 R5 R6 R7 R8 R9 R1 R2 R3 R4 R5 R6 R7 R8 R9 RCOM RCOM RP5 RP7 50Ω DNP DATA-A 1 2 345 67 89 10 1 2 3 45 678 9 10 74VCX86 RP1 22Ω 2 1 AD15 1 DVDD 116 CX1 3 RP1 22Ω U3 2 4 3 AD14 215 DVDD; 14 RP1 22Ω C30 + 6 5 AD13 AGND; 7 C33 314 ACASE CC0805 4.7μF RP1 22Ω 0.1μF 8 7 AD12 74VCX86 6.3V 413 4 RP1 22Ω 6 10 9 AD11 512 U3 5 RP1 22Ω DVDD; 14 12 11 AD10 611 AGND; 7 RP1 22Ω 14 13 AD09 710 RP1 22Ω 74VCX86 16 15 AD08 9 89 8 RP2 22Ω U3 CX3 10 18 17 AD07 116 CX2 DVDD; 14 RP2 22Ω 20 19 AD06 AGND; 7 215 RP2 22Ω 22 21 AD05 314 RP2 22Ω 24 23 AD04 413 RP2 22Ω 26 25 AD03 512 RP2 22Ω 28 27 AD02 611 DVDD RP2 22Ω 30 29 AD01 710 74VCX86 RP2 22Ω 4 32 31 AD00 6 C31 89 + C34 5 U4 4.7μF ACASE CC0805 34 33 DVDD; 14 0.1μF 6.3V AGND; 7 36 35 RP6 1 2 345 67 89 10 1 2 3 45 678 9 10 38 37 RP8 50Ω DNP 40 39 RCOM RCOM R1 R2 R3 R4 R5 R6 R7 R8 R9 R1 R2 R3 R4 R5 R6 R7 R8 R9 RIBBON J1 R15 220Ω ADCLK DVDD RC1206 4 10 DVDD PRE PRE 3 J Q 5 OPCLK_2 11 J Q 9 C52 + C53 74VCX86 OPCLK 1 CLK 12 CLK 4.7μF ACASE CC0805 OPCLK_3 1 0.1μF 6.3V 3 2 K Q 6 2 U4 13 K Q 7 CLR DVDD; 14 CLR AGND; 7 15 14 74LCX112 74LCX112 AGND; 8 U7 U7 DVDD; 16 02857-107 AD9773 Figure 108. AD9773 Evaluation Board Input (B Channel) and SPI Port Circuitry Rev. D | Page 54 of 60 R21 CLKVDD R14 C47 DNP RC0805 200Ω 1nF c RC0805 R20 R1 R2 R3 R4 R5 R6 R7 R8 R9 R1 R2 R3 R4 R5 R6 R7 R8 R9 c CC805 RCOM RCOM RC0805 R4 DNP CLKVDD RP12 RP9 120Ω RC0805 MC100EPT22 C46 JP42 50Ω DNP DATA-B 1 2 3 45 67 8 9 10 1 2 34 567 89 10 0.1μF 1 CLKP 7 R19 U8 JP41 2 100Ω CC805 CLKN CGND; 5 RP3 22Ω R22 2 1 BD15 R13 CLKVDD; 8 116 DNP C48 RP3 22Ω RC0805 CLKVDD 120Ω ACLKX RC0805 4 3 BD14 1nF 215 R24 RC0805 RP3 22Ω DNP RC0805 6 5 BD13 314 c c CC805 R18 RP3 22Ω c 8 7 BD12 200Ω 413 CLKDD RP3 22Ω MC100EPT22 10 9 BD11 512 3 RP3 22Ω 6 12 11 BD10 U8 611 +C49 CC805 C60 ACASE 4 RP3 22Ω c 4.7μF 14 13 BD09 0.1μF 710 CLKVDD; 8 6.3V RP3 22Ω 16 15 BD08 CGND; 5 89 RP4 22Ω 18 17 BD07 c 116 RP4 22Ω 20 19 BD06 215 RP4 22Ω 22 21 BD05 314 RP4 22Ω 24 23 BD04 413 RP4 22Ω 26 25 BD03 512 RP4 22Ω 28 27 BD02 611 RP4 22Ω 30 29 R50 BD01 710 12 13 9kΩ RP4 22Ω 2 1 32 31 BD00 U5 U5 RC0805 89 DGND; 7 DGND; 7 74AC14 74AC14 34 33 DVDD; 14 DVDD; 14 36 35 R48 SPI PORT 1 2 3 45 67 8 9 10 RP11 1 2 34 567 89 10 10 9kΩ 38 37 43 11 P1 RP10 U5 U5 50Ω RC0805 RCOM DNP 1 40 39 RCOM DGND; 7 DGND; 7 74AC14 74AC14 R1 R2 R3 R4 R5 R6 R7 R8 R9 R1 R2 R3 R4 R5 R6 R7 R8 R9 DVDD; 14 DVDD; 14 2 RIBBON J2 R45 3 65 89 9kΩ 4 SPCSB U5 U5 RC0805 DGND; 7 DGND; 7 5 74AC14 74AC14 DVDD; 14 DVDD; 14 SPCLK 6 SPSDI 2 13 1 12 SPSDO U6 U6 DGND; 7 DGND; 7 DVDD; 14 DVDD; 14 74AC14 74AC14 4 10 3 11 U6 U6 DVDD DVDD DGND; 7 DGND; 7 DVDD; 14 74AC14 DVDD; 14 74AC14 C43 C44 + + CC805 C50 C51 ACASE CC805 ACASE 4.7μF 4.7μF 0.1μF 0.1μF 6.3V 6 8 5 9 6.3V U6 U6 DGND; 7 DGND; 7 DVDD; 14 74AC14 DVDD; 14 74AC14 02857-108 AD9773 Figure 109. AD9773 Evaluation Board Components, Top Side Figure 110. AD9773 Evaluation Board Components, Bottom Side Rev. D | Page 55 of 60 02857-110 02857-109 AD9773 Figure 111. AD9773 Evaluation Board Layout, Layer One (Top) Figure 112. AD9773 Evaluation Board Layout, Layer Two (Ground Plane) Rev. D | Page 56 of 60 02857-111 02857-112 AD9773 Figure 113. AD9773 Evaluation Board Layout, Layer Three (Power Plane) Figure 114. AD9773 Evaluation Board Layout, Layer Four (Bottom) Rev. D | Page 57 of 60 02857-114 02857-113 AD9773 OUTLINE DIMENSIONS 14.20 14.00 SQ 12.20 13.80 12.00 SQ 1.20 0.75 MAX 11.80 0.60 0.45 61 80 80 61 1 60 60 1 PIN 1 EXPOSED 6.00 TOP VIEW PAD BSC SQ (PINS DOWN) BOTTOM VIEW 0° MIN 1.05 (PINS UP) 0.20 1.00 0.09 20 41 41 20 0.95 7° 40 40 21 21 3.5° VIEW A 0.15 0.50 BSC 0° SEATING 0.27 LEAD PITCH 0.05 0.08 MAX PLANE 0.22 COPLANARITY 0.17 VIEW A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-ADD-HD ` Figure 115. 80-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] (SV-80-1) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option AD9773BSV −40°C to +85°C 80-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] SV-80-1 AD9773BSVRL −40°C to +85°C 80-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] SV-80-1 1 AD9773BSVZ −40°C to +85°C 80-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] SV-80-1 1 AD9773BSVZRL −40°C to +85°C 80-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] SV-80-1 AD9773-EB Evaluation Board 1 Z = RoHS Compliant Part. Rev. D | Page 58 of 60 060806-A AD9773 NOTES Rev. D | Page 59 of 60 AD9773 NOTES ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02857-0-10/07(D) Rev. D | Page 60 of 60