ANALOG DEVICES AD9772A

14-Bit, 160 MSPS TxDAC+ with 2× Interpolation Filter AD9772A FEATURES FUNCTIONAL BLOCK DIAGRAM CLKCOM CLKVDD MOD0 MOD1 RESET PLLLOCK DIV0 DIV1 Single 3.1 V to 3.5 V supply AD9772A 14-bit DAC resolution and input data width CLK+ PLLCOM CLOCK DISTRIBUTION PLL CLOCK 160 MSPS input data rate CLK– AND MODE SELECT MULTIPLIER LPF 67.5 MHz reconstruction pass band @ 160 MSPS FILTER MUX PLLVDD 1× 1×/2× 2×/4× CONTROL CONTROL 74 dBc SFDR @ 25 MHz 2× interpolation filter with high- or low-pass response I DATA ZERO- OUTA 2× FIR EDGE- STUFF 14-BIT DAC INPUTS INTER- 73 dB image rejection with 0.005 dB pass-band ripple TRIGGERED I (DB13 TO MUX OUTB POLATION LATCHES DB0) FILTER Zero-stuffing option for enhanced direct IF performance REFIO 1.2V REFERENCE Internal 2×/4× clock multiplier SLEEP FSADJ AND CONTROL AMP 250 mW power dissipation; 13 mW with power-down mode 48-lead LQFP package DCOM DVDD ACOM AVDD REFLO Figure 1. APPLICATIONS Communication transmit channel W-CDMA base stations, multicarrier base stations, direct IF synthesis, wideband cable systems Instrumentation GENERAL DESCRIPTION The AD9772A is a single-supply, oversampling, 14-bit digital- The AD9772A can reconstruct full-scale waveforms with band- to-analog converter (DAC) optimized for baseband or IF widths of up to 67.5 MHz while operating at an input data rate of 160 MSPS. The 14-bit DAC provides differential current waveform reconstruction applications requiring exceptional outputs to support differential or single-ended applications. dynamic range. Manufactured on an advanced CMOS process, it integrates a complete, low distortion 14-bit DAC with a 2× A segmented current source architecture is combined with a digital interpolation filter and clock multiplier. The on-chip PLL proprietary switching technique to reduce spurious components clock multiplier provides all the necessary clocks for the digital and enhance dynamic performance. Matching between the two filter and the 14-bit DAC. A flexible differential clock input current outputs ensures enhanced dynamic performance in a allows for a single-ended or differential clock driver for differential output configuration. The differential current optimum jitter performance. outputs can be fed into a transformer or a differential op amp topology to obtain a single-ended output voltage using an For baseband applications, the 2× digital interpolation filter appropriate resistive load. provides a low-pass response, thus providing as much as a threefold reduction in the complexity of the analog reconstruc- The on-chip band gap reference and control amplifier are con- tion filter. It does so by multiplying the input data rate by a figured for maximum accuracy and flexibility. The AD9772A factor of 2 while suppressing the original upper in-band image can be driven by the on-chip reference or by a variety of by more than 73 dB. For direct IF applications, the 2× digital external reference voltages. The full-scale current of the interpolation filter response can be reconfigured to select the AD9772A can be adjusted over a 2 mA to 20 mA range, thus upper in-band image (that is, the high-pass response) while providing additional gain-ranging capabilities. suppressing the original baseband image. To increase the signal The AD9772A is available in a 48-lead LQFP package and is level of the higher IF images and their pass-band flatness in specified for operation over the industrial temperature range of direct IF applications, the AD9772A also features a zero-stuffing –40°C to +85°C. option in which the data following the 2× interpolation filter is upsampled by a factor of 2 by inserting midscale data samples. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 02253-001 AD9772A TABLE OF CONTENTS Features .............................................................................................. 1 DAC Transfer Function ............................................................. 22 Applications....................................................................................... 1 Reference Operation .................................................................. 22 Functional Block Diagram .............................................................. 1 Reference Control Amplifier .................................................... 23 General Description ......................................................................... 1 Analog Outputs .......................................................................... 23 Revision History ............................................................................... 2 Digital Inputs/Outputs .............................................................. 24 Product Highlights ........................................................................... 3 Sleep Mode Operation............................................................... 25 Specifications..................................................................................... 4 Power Dissipation....................................................................... 25 DC Specifications ......................................................................... 4 Applying the AD9772A ................................................................. 26 Dynamic Specifications ............................................................... 6 Output Configurations .............................................................. 26 Digital Specifications ................................................................... 7 Differential Coupling Using a Transformer ............................... 26 Digital Filter Specifications ......................................................... 8 Differential Coupling Using an Op Amp................................ 26 Absolute Maximum Ratings............................................................ 9 Single-Ended, Unbuffered Voltage Output............................. 26 Thermal Characteristics .............................................................. 9 Single-Ended, Buffered Voltage Output.................................. 27 ESD Caution.................................................................................. 9 Power and Grounding Considerations.................................... 27 Pin Configuration and Function Descriptions........................... 10 Applications Information .............................................................. 29 Terminology .................................................................................... 12 Multicarrier ................................................................................. 29 Typical Performance Characteristics ........................................... 14 Baseband Single-Carrier Applications .................................... 30 Theory of Operation ...................................................................... 17 Direct IF....................................................................................... 30 Functional Description.............................................................. 17 AD9772A Evaluation Board ......................................................... 32 Digital Modes of Operation ...................................................... 17 Schematics................................................................................... 33 PLL Clock Multiplier Operation .............................................. 19 Evaluation Board Layout........................................................... 35 Synchronization of Clock/Data Outline Dimensions ....................................................................... 38 Using Reset with PLL Disabled................................................. 21 Ordering Guide .......................................................................... 38 DAC Operation........................................................................... 22 Change to Digital Filter Specifications ...........................................5 REVISION HISTORY Ordering Guide Updated .................................................................6 2/08—Rev. B to Rev. C Change to Pin Function Descriptions ............................................7 Changes to DVDD Parameter......................................................... 4 Change to Figure 13a and Figure 13b.......................................... 15 Changes to PLL Clock Enabled Parameter ................................... 7 Change to Digital Inputs/Outputs................................................ 18 Changes to PLL Clock Disabled Parameter .................................. 7 Change to Sleep Mode Operation ................................................ 19 Changes to Table 8.......................................................................... 10 Change to Figure 22 ....................................................................... 19 Changes to Functional Description ............................................. 17 Change to Figure 23 ....................................................................... 19 Change to Power Dissipation Section.......................................... 25 Change to Power and Ground Considerations .......................... 21 Changes to Power and Grounding Considerations Section ..... 27 Change to Figure 29 ....................................................................... 21 Change to Figure 53 ....................................................................... 29 Update to Outline Dimensions..................................................... 30 Change to Direct IF Section.......................................................... 30 Changes to Figure 61...................................................................... 34 3/02—Rev. 0 to Rev. A Updated Outline Dimensions ....................................................... 38 Edits to Digital Specifications..........................................................4 Changes to Ordering Guide .......................................................... 38 Edits to Absolute Maximum Ratings..............................................6 Change to TPC 11 .......................................................................... 10 6/03—Rev. A to Rev. B Change to Figure 9 Caption .......................................................... 14 Change to Features .......................................................................... 1 Change to Figure 13a and Figure 13b.......................................... 15 Change to DC Specifications .......................................................... 2 Rev. C | Page 2 of 40 AD9772A 4. The AD9772A digital interface, consisting of edge-triggered PRODUCT HIGHLIGHTS latches and a flexible differential or single-ended clock input, 1. A flexible, low power 2× interpolation filter supporting can support input data rates up to 160 MSPS. reconstruction bandwidths of up to 67.5 MHz can be 5. An on-chip PLL clock multiplier generates all of the configured for a low- or high-pass response with 73 dB internal high speed clocks required by the interpolation of image rejection for traditional baseband or direct IF filter and DAC. applications. 6. The current output(s) of the AD9772A can easily be 2. A zero-stuffing option enhances direct IF applications. configured for various single-ended or differential circuit 3. A low glitch, fast settling 14-bit DAC provides exceptional topologies. dynamic range for both baseband and direct IF waveform reconstruction applications. Rev. C | Page 3 of 40 AD9772A SPECIFICATIONS DC SPECIFICATIONS T to T , AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, DVDD = 3.3 V, I = 20 mA, unless otherwise noted. MIN MAX OUTFS Table 1. Parameter Min Typ Max Unit RESOLUTION 14 Bits 1 DC ACCURACY Integral Linearity Error (INL) ±3.5 LSB Differential Nonlinearity (DNL) ±2.0 LSB Monotonicity (12-Bit) Guaranteed over specified temperature range ANALOG OUTPUT Offset Error −0.025 +0.025 % of FSR Gain Error Without Internal Reference −2 ±0.5 +2 % of FSR With Internal Reference −5 ±1.5 +5 % of FSR 2 Full-Scale Output Current 20 mA Output Compliance Range −1.0 +1.25 V Output Resistance 200 kΩ Output Capacitance 3 pF REFERENCE OUTPUT Reference Voltage 1.14 1.20 1.26 V 3 Reference Output Current 1 μA REFERENCE INPUT Input Compliance Range 0.1 1.25 V Reference Input Resistance (REFLO = 3 V) 10 MΩ Small-Signal Bandwidth 0.5 MHz TEMPERATURE COEFFICIENTS Unipolar Offset Drift 0 ppm of FSR/°C Gain Drift Without Internal Reference ±50 ppm of FSR/°C With Internal Reference ±100 ppm of FSR/°C Reference Voltage Drift ±50 ppm/°C POWER SUPPLY AVDD Voltage Range 3.1 3.3 3.5 V Analog Supply Current (I) 34 37 mA AVDD Analog Supply Current in Sleep Mode (IAVDD) 4.3 6 mA DVDD Voltage Range 3.1 3.3 3.5 V Digital Supply Current (I) 37 40 mA DVDD 4 CLKVDD, PLLVDD (PLLVDD = 3.3 V) Voltage Range 3.1 3.3 3.5 V Clock Supply Current (ICLKVDD + IPLLVDD) 25 30 mA Rev. C | Page 4 of 40 AD9772A Parameter Min Typ Max Unit CLKVDD (PLLVDD = 0 V) Voltage Range 3.1 3.3 3.5 V Clock Supply Current (I) 6.0 mA CLKVDD 5 Nominal Power Dissipation 253 272 mW 6 Power Supply Rejection Ratio (PSRR) PSRR − AVDD −0.6 +0.6 % of FSR/V PSRR − DVDD −0.025 +0.025 % of FSR/V OPERATING RANGE −40 +85 °C 1 Measured at IOUTA driving a virtual ground. 2 Nominal full-scale current, IOUTFS, is 32× the IREF current. 3 Use an external amplifier to drive any external load. 4 Measured at fDATA = 100 MSPS and fOUT = 1 MHz with DIV1 and DIV0 = 0 V. 5 Measured with PLL enabled at f = 50 MSPS and f = 1 MHz. DATA OUT 6 Measured over a 3.0 V to 3.6 V range. Rev. C | Page 5 of 40 AD9772A DYNAMIC SPECIFICATIONS TMIN to TMAX, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 3.3 V, IOUTFS = 20 mA, differential transformer-coupled output, 50 Ω doubly terminated, unless otherwise noted. Table 2. Parameter Min Typ Max Unit DYNAMIC PERFORMANCE Maximum DAC Output Update Rate (fDAC) 400 MSPS Output Settling Time (tST) (to 0.025%) 11 ns 1 Output Propagation Delay (t) 17 ns PD 2 Output Rise Time (10% to 90%) 0.8 ns Output Fall Time (10% to 90%) 0.8 ns Output Noise (IOUTFS = 20 mA) 50 pA√Hz AC LINEARITY—BASEBAND MODE Spurious-Free Dynamic Range (SFDR) to Nyquist (fOUT = 0 dBFS) fDATA = 65 MSPS; fOUT = 1.01 MHz 82 dBc fDATA = 65 MSPS; fOUT = 10.01 MHz 75 dBc f = 65 MSPS; f = 25.01 MHz 73 dBc DATA OUT f = 160 MSPS; f = 5.02 MHz 82 dBc DATA OUT f = 160 MSPS; f = 20.02 MHz 75 dBc DATA OUT fDATA = 160 MSPS; fOUT = 50.02 MHz 65 dBc Two-Tone Intermodulation (IMD) to Nyquist (fOUT1 = fOUT2 = −6 dBFS) fDATA = 65 MSPS; fOUT1 = 5.01 MHz; fOUT2 = 6.01 MHz 85 dBc f = 65 MSPS; f = 15.01 MHz; f = 17.51 MHz 75 dBc DATA OUT1 OUT2 f = 65 MSPS; f = 24.1 MHz; f = 26.2 MHz 68 dBc DATA OUT1 OUT2 fDATA = 160 MSPS; fOUT1 = 10.02 MHz; fOUT2 = 12.02 MHz 85 dBc fDATA = 160 MSPS; fOUT1 = 30.02 MHz; fOUT2 = 35.02 MHz 70 dBc fDATA = 160 MSPS; fOUT1 = 48.2 MHz; fOUT2 = 52.4 MHz 65 dBc Total Harmonic Distortion (THD) f = 65 MSPS; f = 1.0 MHz; 0 dBFS −80 dB DATA OUT f = 78 MSPS; f = 10.01 MHz; 0 dBFS −74 dB DATA OUT Signal-to-Noise Ratio (SNR) fDATA = 65 MSPS; fOUT = 16.26 MHz; 0 dBFS 71 dB fDATA = 100 MSPS; fOUT = 25.1 MHz; 0 dBFS 71 dB Adjacent Channel Power Ratio (ACPR) WCDMA with 4.1 MHz BW, 5 MHz Channel Spacing IF = 16 MHz, f = 65.536 MSPS 78 dBc DATA IF = 32 MHz, fDATA = 131.072 MSPS 68 dBc Four-Tone Intermodulation 15.6 MHz, 15.8 MHz, 16.2 MHz, and 16.4 MHz at −12 dBFS 88 dBFS f = 65 MSPS, Missing Center DATA AC LINEARITY—IF MODE Four-Tone Intermodulation at IF = 70 MHz 68.1 MHz, 69.3 MHz, 71.2 MHz, and 72.0 MHz at −20 dBFS 77 dBFS f = 52 MSPS, f = 208 MHz DATA DAC 1 Propagation delay is delay from the CLK+/CLK− input to the DAC update. 2 Measured single-ended into 50 Ω load. Rev. C | Page 6 of 40 AD9772A DIGITAL SPECIFICATIONS TMIN to TMAX, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, DVDD = 3.3 V, IOUTFS = 20 mA, unless otherwise noted. Table 3. Parameter Min Typ Max Unit DIGITAL INPUTS Logic 1 Voltage 2.1 3 V Logic 0 Voltage 0 0.9 V 1 Logic 1 Current −10 +10 μA Logic 0 Current −10 +10 μA Input Capacitance 5 pF CLOCK INPUTS Input Voltage Range 0 3 V Common-Mode Voltage 0.75 1.5 2.25 V Differential Voltage 0.5 1.5 V PLL CLOCK ENABLED (SEE Figure 2) Input Setup Time (t) S TA = 25°C 1.5 ns TA = −40 to +85°C 2.1 ns Input Hold Time (tH) T = 25°C 1.3 ns A T = −40 to +85°C 1.6 ns A Latch Pulse Width (tLPW), TA = 25°C 1.5 ns PLL CLOCK DISABLED (SEE Figure 3) Input Setup Time (t) S TA = 25°C −0.7 ns TA = −40 to +85°C −0.4 ns Input Hold Time (tH) T = 25°C 3.3 ns A T = −40 to +85°C 3.7 ns A Latch Pulse Width (t ), T = 25°C 1.5 ns LPW A CLK+/CLK− to PLLLOCK Delay (tOD) TA = 25°C 1.9 2.8 ns TA = −40 to +85°C 1.8 3.3 ns PLLLOCK (V ), T = 25°C 3.0 V OH A PLLLOCK (V ), T = 25°C 0.3 V OL A 1 MOD0, MOD1, DIV0, DIV1, SLEEP, RESET have typical input currents of 15 μA. DB0 TO DB13 DB0 TO DB13 t t H H t t S S PLLLOCK t OD t CLK+ – CLK– LPW CLK+ – CLK– t t t LPW ST PD 0.025% I OUTA OR I OUTB 0.025% t t PD ST 0.025% I OUTA OR Figure 2. Timing Diagram—PLL Clock Multiplier Enabled I OUTB 0.025% Figure 3. Timing Diagram—PLL Clock Multiplier Disabled Rev. C | Page 7 of 40 02253-002 02253-003 AD9772A DIGITAL FILTER SPECIFICATIONS TMIN to TMAX, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, DVDD = 3.3 V, IOUTFS = 20 mA, differential transformer-coupled output, 50 Ω doubly terminated, unless otherwise noted. Table 4. Parameter Min Typ Max Unit MAXIMUM INPUT DATA RATE (fDATA) 150 MSPS DIGITAL FILTER CHARACTERISTICS 1 Pass-Bandwidth : 0.005 dB 0.401 f /f OUT DATA Pass-Bandwidth: 0.01 dB 0.404 fOUT/fDATA Pass-Bandwidth: 0.1 dB 0.422 fOUT/fDATA Pass-Bandwidth: −3 dB 0.479 fOUT/fDATA LINEAR PHASE (FIR IMPLEMENTATION) STOP BAND REJECTION 73 dB 0.606 fCLOCK to 1.394 fCLOCK 11 Input clocks 2 GROUP DELAY IMPULSE RESPONSE DURATION −40 dB 36 Input clocks −60 dB 42 Input clocks 1 Excludes sin(x)/x characteristic of DAC. 2 Defined as the number of data clock cycles between impulse input and peak of output response. 0 Table 5. Integer Filter Coefficients for Interpolation Filter (43-Tap Half-Band FIR Filter) –20 Lower Upper Integer Coefficient Coefficient Value –40 H(1) H(43) 10 –60 H(2) H(42) 0 H(3) H(41) −31 –80 H(4) H(40) 0 H(5) H(39) 69 –100 H(6) H(38) 0 H(7) H(37) −138 –120 H(8) H(36) 0 –140 H(9) H(35) 248 0 0. 1 0.2 0.3 0. 4 0.5 0.6 0.7 0.8 0.9 1.0 FREQUENCY (DC TO f ) DATA H(10) H(34) 0 Figure 4. FIR Filter Frequency Response—Baseband Mode H(11) H(33) −419 H(12) H(32) 0 1.0 H(13) H(31) 678 0.8 H(14) H(30) 0 H(15) H(29) −1083 0.6 H(16) H(28) 0 H(17) H(27) 1776 0.4 H(18) H(26) 0 0.2 H(19) H(25) −3282 H(20) H(24) 0 0 H(21) H(23) 10,364 H(22) 16,384 –0.2 –0.4 0 5 10 15 20 25 30 35 40 45 TIME (Samples) Figure 5. FIR Filter Impulse Response—Baseband Mode Rev. C | Page 8 of 40 NORMALIZED OUTPUT OUTPUT (dB) 02253-005 02253-004 AD9772A ABSOLUTE MAXIMUM RATINGS Table 6. Stresses above those listed under Absolute Maximum Ratings Parameter With Respect to Rating may cause permanent damage to the device. This is a stress AVDD, DVDD, CLKVDD, ACOM, DCOM, −0.3 V to +4.0 V rating only; functional operation of the device at these or any PLLVDD CLKCOM, PLLCOM other conditions above those indicated in the operational −4.0 V to +4.0 V AVDD, DVDD, CLKVDD, AVDD, DVDD, section of this specification is not implied. Exposure to absolute PLLVDD CLKVDD, PLLVDD maximum rating conditions for extended periods may affect ACOM, DCOM, ACOM, DCOM, −0.3 V to +0.3 V device reliability. CLKCOM, PLLCOM CLKCOM, PLLCOM REFIO, REFLO, FSADJ, ACOM −0.3 V to THERMAL CHARACTERISTICS SLEEP AVDD + 0.3 V θ is specified for the worst-case conditions, that is, a device JA IOUTA, IOUTB ACOM −1.0 V to soldered in a circuit board for surface-mount packages. AVDD + 0.3 V DB0 to DB13, MOD0, DCOM −0.3 V to Table 7. Thermal Resistance MOD1, PLLLOCK DVDD + 0.3 V Package Type θ θ Unit JA JC CLK+, CLK− CLKCOM −0.3 V to CLKVDD + 0.3 V 48-Lead LQFP 91 28 °C/W DIV0, DIV1, RESET CLKCOM −0.3 V to CLKVDD + 0.3 V ESD CAUTION LPF PLLCOM −0.3 V to PLLVDD + 0.3 V Junction Temperature 125°C Storage Temperature −65°C to +150°C Lead Temperature 300°C (10 sec) Rev. C | Page 9 of 40 AD9772A PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 48 47 46 45 44 43 42 41 40 39 38 37 1 DCOM 36 SLEEP PIN 1 2 DCOM IDENTIFIER 35 LPF (MSB) DB13 3 34 PLLVDD DB12 4 33 PLLCOM 5 DB11 32 CLKVDD AD9772A 6 DB10 31 CLKCOM TOP VIEW 7 DB9 30 CLK– (Not to Scale) 8 DB8 29 CLK+ DB7 9 28 DIV0 DB6 10 27 DIV1 11 DB5 26 RESET 12 DB4 25 PLLLOCK 13 14 15 16 17 18 19 20 21 22 23 24 NC = NO CONNECT Figure 6. Pin Configuration Table 8. Pin Function Descriptions Pin No. Mnemonic Description 1, 2, 19, 20 DCOM Digital Common. 3 DB13 Most Significant Data Bit (MSB). 4 to 15 DB12 to DB1 Data Bit 1 to Data Bit 12. 16 DB0 Least Significant Data Bit (LSB). 17 MOD0 Digital High-Pass Filter Response. Active high. This pin invokes the digital high-pass filter response (that is, half-wave digital mixing mode). Note that quarter-wave digital mixing occurs if this pin and the MOD1 pin are set high. 18 MOD1 Zero-Stuffing Mode. Active high. This pin invokes zero-stuffing mode. Note that quarter-wave digital mixing occurs if this pin and the MOD0 pin are set high. 23, 24 NC No Connect. Leave open. 21, 22, 47, 48 DVDD Digital Supply Voltage (3.1 V to 3.5 V). 25 PLLLOCK Lock Signal of the Phase-Lock Loop. This pin provides the lock signal of the phase-lock loop when the PLL clock multiplier is enabled, and provides the 1× clock output when the PLL clock multiplier is disabled. High indicates that PLL is locked to the input clock. The maximum fanout is 1 (that is, <10 pF). 26 RESET Internal Divider Reset. This pin can reset the internal driver to synchronize the internal 1× clock to the input data and/or multiple AD9772A devices. The reset is initiated if this pin is momentarily brought high when PLL is disabled. 27, 28 DIV1, DIV0 PLL Prescaler Divide Ratio. DIV1 and DIV0 set the prescaler divide ratio of the PLL (refer to Table 10). 29 CLK+ Noninverting Input to Differential Clock. Bias this pin to the midsupply (that is, CLKVDD/2). 30 CLK− Inverting Input to Differential Clock. Bias this pin to the midsupply (that is, CLKVDD/2). 31 CLKCOM Clock Input Common. 32 CLKVDD Clock Input Supply Voltage (3.1 V to 3.5 V). 33 PLLCOM Phase-Lock Loop Common. 34 PLLVDD Phase-Lock Loop (PLL) Supply Voltage (3.1 V to 3.5 V). To disable the PLL clock multiplier, connect PLLVDD to PLLCOM. 35 LPF PLL Loop Filter Node. This pin should be left as a no connect (open) unless the DAC update rate is less than 10 MSPS, in which case a series RC should be connected from LPF to PLLVDD as indicated in Figure 61. 36 SLEEP Power-Down Control Input. Active high. When this pin is not used, connect it to ACOM. 37, 41, 44 ACOM Analog Common. 38 REFLO Reference Ground When Internal 1.2 V Reference Is Used. Connect this pin to AVDD to disable the internal reference. Rev. C | Page 10 of 40 DVDD DB3 DVDD DB2 AVDD DB1 AVDD (LSB) DB0 ACOM MOD0 MOD1 I OUTA DCOM IOUTB DCOM ACOM DVDD FSADJ DVDD REFIO REFLO NC ACOM NC 02253-006 AD9772A Pin No. Mnemonic Description 39 REFIO Reference Input/Output. This pin serves as the reference input when the internal reference is disabled (that is, when REFLO is tied to AVDD), or it serves as the 1.2 V reference output when the internal reference is activated (that is, when REFLO is tied to ACOM). If the internal reference is activated, a 0.1 μ F capacitor to ACOM is required. 40 FSADJ Full-Scale Current Output Adjust. 42 I Complementary DAC Current Output. Full-scale current is selected when all data bits are 0s. OUTBB 43 IOUTA DAC Current Output. Full-scale current is selected when all data bits are 1s. 45, 46 AVDD Analog Supply Voltage (3.1 V to 3.5 V). Rev. C | Page 11 of 40 AD9772A TERMINOLOGY Settling Time Linearity Error (Also Called Integral Nonlinearity or INL) Settling time is the time required for the output to reach and Linearity error is defined as the maximum deviation of the remain within a specified error band about its final value. It is actual analog output from the ideal output and is determined by measured from the start of the output transition. a straight line drawn from zero to full scale. Glitch Impulse Differential Nonlinearity (DNL) Asymmetrical switching times in a DAC give rise to undesired DNL is the measure of the variation in analog value, normalized to output transients that are quantified by a glitch impulse. It is full scale that is associated with a 1 LSB change in digital input code. specified as the net area of the glitch in pV-s. Monotonicity Spurious-Free Dynamic Range A DAC is monotonic if the output either increases or remains Spurious-free dynamic range is the difference, in decibels, constant as the digital input increases. between the rms amplitude of the output signal and the peak Offset Error spurious signal over the specified bandwidth. Offset error is the deviation of the output current from the ideal Total Harmonic Distortion (THD) of zero. For I , 0 mA output is expected when the inputs are all OUTA THD is the ratio of the rms sum of the first six harmonic 0s. For I , 0 mA output is expected when all inputs are set to 1s. OUTBB components to the rms value of the measured fundamental. It is Gain Error expressed as a percentage or in decibels. Gain error is the difference between the actual and ideal output Signal-to-Noise Ratio (SNR) span. The actual span is determined by the output when all inputs SNR is the ratio of the rms value of the measured output signal are set to 1s minus the output when all inputs are set to 0s. to the rms sum of all other spectral components below the Output Compliance Range Nyquist frequency, excluding the first six harmonics and dc. The output compliance range is the range of allowable voltage The value for SNR is expressed in decibels. at the output of a current-output DAC. Operation beyond the Pass Band maximum compliance limits may cause either output stage Pass band is the frequency band in which any input applied saturation or breakdown, resulting in nonlinear performance. therein passes unattenuated to the DAC output. Temperature Drift Stop-Band Rejection Temperature drift is specified as the maximum change from the Stop-band rejection is the amount of attenuation of a frequency ambient (25°C) value to the value at either TMIN or TMAX. For offset outside the pass band applied to the DAC relative to a full-scale and gain drift, the drift is reported in ppm of full-scale range (FSR) signal applied at the DAC input within the pass band. per °C. For reference drift, the drift is reported in ppm per °C. Group Delay Power Supply Rejection Group delay is the number of input clocks between an impulse Power supply rejection is the maximum change in the full-scale applied at the device input and the peak DAC output current. output as the supplies are varied from minimum to maximum specified voltages. Impulse Response Impulse response is the response of the device to an impulse applied to the input. Adjacent-Channel Power Ratio (ACPR) ACPR is a ratio, in dBc, between the measured power within a channel relative to its adjacent channel. Rev. C | Page 12 of 40 AD9772A CH1 HP8130 FROM HP8644A PULSE GENERATOR CH2 SIGNAL GENERATOR EXTERNAL INPUT 3.3V 1kΩ 1kΩ CLKVDD CLKCOM AD9772A PLLCOM CLK+ LPF CLOCK DISTRIBUTION PLLCLOCK AND MODE SELECT MULTIPLIER CLK– PLLVDD FILTER 1× 1×/2× TO FSEA30 MUX CONTROL 2×/4× SPECTRUM CONTROL MINI-CIRCUITS AWG2021 ANALYZER I T1-1T OUTA OR DG2020 ZERO EDGE- 2× FIR 100Ω DIGITAL 14-BIT DAC STUFF TRIGGERED INTERPOLATION I DATA EXTERNAL OUTB MUX LATCHES FILTER CLOCK 0.1µF REFIO 50Ω 50Ω 20pF 1.2V REFERENCE SLEEP 20pF AND CONTROL AMP FSADJ DCOM DVDD ACOM AVDD REFLO 1.91kΩ 3.3V 3.3V Figure 7. Basic AC Characterization Test Setup Rev. C | Page 13 of 40 MOD0 MOD1 RESET PLLLOCK DIV0 DIV1 02253-007 AD9772A TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 3.3 V, CLKDD = 3.3 V, PLLVDD = 0 V, DVDD = 3.3 V, IOUTFS = 20 mA. PLL disabled. IN-BAND OUT-OF-BAND IN-BAND OUT-OF-BAND 0 0 –20 –20 –40 –40 –60 –60 –80 –80 –100 –100 0 20 40 60 80 100 120 0 50 100 150 f (MHz) f (MHz) OUT OUT Figure 8. Single-Tone Spectral Characteristics @ f = 65 MSPS with f = f /3 DATA OUT DATA Figure 11. Single-Tone Spectral Characteristics @ f = 78 MSPS with f = f /3 DATA OUT DATA 90 90 0dBFS 85 –6dBFS 85 –6dBFS 80 80 75 75 70 70 –12dBFS –12dBFS 0dBFS 65 65 60 60 55 55 50 50 0 5 10 15 20 25 30 35 02 5 10 15025 30 f (MHz) f (MHz) OUT OUT Figure 9. In-Band SFDR vs. f @ f = 65 MSPS Figure 12. In-Band SFDR vs. fOUT @ fDATA = 78 MSPS OUT DATA 70 70 –6dBFS –6dBFS 65 65 0dBFS 60 60 0dBFS –12dBFS –12dBFS 55 55 50 50 45 45 40 40 35 35 30 30 0 5 10 15 20 25 30 0 510 15 20 25 30 35 f (MHz) f (MHz) OUT OUT Figure 10. Out-of-Band SFDR vs. f @ f = 65 MSPS OUT DATA Figure 13. Out-of-Band SFDR vs. fOUT @ fDATA = 78 MSPS Rev. C | Page 14 of 40 SFDR (dBc) SFDR (dBc) AMPLITUDE (dBm) 02253-008 02253-010 02253-009 AMPLITUDE (dBm) SFDR (dBc) AMPLITUDE (dBm) 02253-012 02253-011 02253-013 AD9772A 90 0 IN-BAND OUT-OF- –6dBFS BAND 85 –20 80 –3dBFS 75 0dBFS –40 70 –60 65 60 –80 55 –100 50 0 50 100 150 200 250 300 0 5 10 15202530 f (MHz) OUT f (MHz) OUT Figure 14. Single-Tone Spectral Characteristics @ fDATA = 160 MSPS Figure 17. Third-Order IMD Products vs. fOUT @ fDATA = 65 MSPS with fOUT = fDATA/3 90 90 –6dBFS 85 85 0dBFS 80 80 –3dBFS –6dBFS 75 75 0dBFS 70 70 –12dBFS 65 65 60 60 55 55 50 50 0 10 20 30 40 50 60 0 5 1015202530 35 f (MHz) f (MHz) OUT OUT Figure 15. In-Band SFDR vs. fOUT @ fDATA = 160 MSPS Figure 18. Third-Order IMD Products vs. fOUT @ fDATA = 78 MSPS 70 90 –6dBFS 65 85 60 80 –3dBFS 55 75 –6dBFS 50 70 0dBFS 45 65 40 60 0dBFS –12dBFS 55 35 30 50 0 10 20 30 40 50 60 70 0 10 20 30 40 50 60 70 f (MHz) f (MHz) OUT OUT Figure 16. Out-of-Band SFDR vs. f @ f = 160 MSPS Figure 19. Third-Order IMD Products vs. f @ f = 160 MSPS OUT DATA OUT DATA Rev. C | Page 15 of 40 AMPLITUDE (dBm) AMPLITUDE (dBm) AMPLITUDE (dBm) 02253-014 02253-016 02253-015 IMD (dBc) IMD (dBc) IMD (dBc) 02253-019 02253-018 02253-017 AD9772A 90 90 0dBFS –3dBFS 85 85 f = 160MSPS DATA f = 65MSPS DATA 80 80 75 –6dBFS 75 70 f = 78MSPS DATA 65 70 60 65 55 60 50 –20 –15 –10 –5 0 3.0 3.1 3.2 3.3 3.4 3.5 3.6 A (dBFS) AVDD (V) OUT Figure 20. Third-Order IMD Products vs. AOUT @ fOUT = fDAC/11 Figure 23. Third-Order IMD Products vs. AVDD @ f = 10 MHz, OUT f = 320 MSPS DAC 90 90 85 85 f = 78MSPS DATA 80 80 PLL OFF 75 75 f = 160MSPS DATA 70 70 f = 65MSPS DATA 65 65 PLL ON, OPTIMUM DIV0/DIV1 SETTINGS 60 60 55 55 50 50 75 –20 –15 –10 –5 0 25 125 175 A (dBFS) OUT f (MHz) DAC Figure 21. Third-Order IMD Products vs. A @ f = f /5 Figure 24. SNR vs. f @ f = 10 MHz OUT OUT DAC DAC OUT 90 90 85 85 f = 78MSPS DATA f = 65MSPS –3dBFS DATA 80 80 75 75 –6dBFS 0dBFS 70 70 f = 160MSPS DATA 65 65 60 60 55 55 50 50 3.0 3.1 3.2 3.3 3.4 3.5 3.6 –40 –2008 20 40 600 AVDD (V) TEMPERATURE (°C) Figure 22. SFDR vs. AVDD @ f = 10 MHz, f = 320 MSPS OUT DAC Figure 25. In-Band SFDR vs. Temperature @ fOUT = fDATA/11 Rev. C | Page 16 of 40 SFDR (dBc) IMD (dBc) IMD (dBc) 02253-022 02253-021 02253-020 SNR (dBc) SFDR (dBc) IMD (dBc) 02253-025 02253-023 02253-024 AD9772A THEORY OF OPERATION FUNCTIONAL DESCRIPTION Table 9. Digital Modes Figure 26 shows a simplified block diagram of the AD9772A. Digital Digital Zero- Mode MOD0 MOD1 Filter Stuffing The AD9772A is a complete 2× oversampling, 14-bit DAC that Baseband 0 0 Low No includes a 2× interpolation filter, a phase-locked loop (PLL) Baseband 0 1 Low Yes clock multiplier, and a 1.20 V band gap voltage reference. Direct IF 1 0 High No Although the AD9772A digital interface can support input data Direct IF 1 1 High Yes rates as high as 160 MSPS, its internal DAC can operate up to 400 MSPS, thus providing direct IF conversion capabilities. The 14-bit DAC provides two complementary current outputs For applications requiring the highest dynamic range over a whose full-scale current is determined by an external resistor. wide bandwidth, users should consider operating the AD9772A The AD9772A features a flexible, low jitter differential clock in a baseband mode. Although the zero-stuffing option can be input, providing excellent noise rejection while accepting a sine used in this mode, the ratio of the signal to the image power wave input. An on-chip PLL clock multiplier produces all of the will be reduced. necessary synchronized clocks from an external reference clock For applications requiring the synthesis of IF signals, users source. Separate supply inputs are provided for each functional should consider operating the AD9772A in a direct IF mode. In block to ensure optimum noise and distortion performance. A this case, the zero-stuffing option should be considered when sleep mode is also included for power savings. synthesizing and selecting IFs beyond the input data rate, fDATA. CLKCOM CLKVDD MOD0 MOD1 RESET PLLLOCK DIV0 DIV1 If the reconstructed IF falls below fDATA, the zero-stuffing option AD9772A CLK+ PLLCOM may or may not be beneficial. Note that the dynamic range (that CLOCK DISTRIBUTION PLL CLOCK CLK– AND MODE SELECT MULTIPLIER LPF is, SNR/SFDR) can be optimized by disabling the PLL clock FILTER MUX PLLVDD 1× 1× /2× 2× /4× multiplier (that is, by connecting PLLVDD to PLLCOM) and by CONTROL CONTROL using an external low-jitter clock source operating at the DAC I ZERO update rate, f . DATA 2× FIR OUTA DAC EDGE- INPUTS STUFF 14-BIT DAC INTER- TRIGGERED I MUX OUTB (DB13 TO POLATION LATCHES 2× Interpolation Filter Description DB0) FILTER REFIO 1.2V REFERENCE The 2× interpolation filter is based on a 43-tap, half-band, SLEEP FSADJ AND CONTROL AMP symmetric FIR topology that can be configured for a low- or high-pass response, depending on the state of the MOD0 DCOM DVDD ACOM AVDD REFLO control input. The low-pass response is selected with MOD0 Figure 26. Simplified Functional Block Diagram low, and the high-pass response is selected with MOD0 high. Preceding the 14-bit DAC is a 2× digital interpolation filter that The low-pass frequency and the impulse response of the half- can be configured for a low-pass (that is, baseband mode) or band interpolation filter are shown in Figure 4 and Figure 5, high-pass (that is, direct IF mode) response. The input data is and the idealized filter coefficients are listed in Table 5. Note latched into the edge-triggered input latches on the rising edge that the impulse response of a FIR filter is also represented by of the differential input clock, as shown in Figure 2, and then its idealized filter coefficients. interpolated by a factor of 2 by the digital filter. For traditional The 2× interpolation filter essentially multiplies the input data rate baseband applications, the 2× interpolation filter has a low-pass to the DAC by a factor of 2, relative to its original input data rate, response. For direct IF applications, the filter response can be while reducing the magnitude of the first image associated with converted into a high-pass response to extract the higher image. the original input data rate occurring at fDATA − fFUNDAMENTAL. As a The output data of the 2× interpolation filter can update the result of the 2× interpolation, the digital filter frequency response is 14-bit DAC directly or undergo a zero-stuffing process to increase uniquely defined over its Nyquist zone of dc to f , with mirror DATA the DAC update rate by another factor of 2. This action enhances images occurring in adjacent Nyquist zones. the relative signal level and pass-band flatness of the higher frequency images. The benefits of an interpolation filter are clearly seen in Figure 27, which shows an example of the frequency and time DIGITAL MODES OF OPERATION domain representation of a discrete time sine wave signal before The AD9772A features four modes of operation controlled by and after it is applied to the 2× digital interpolation filter in a the digital inputs, MOD0 and MOD1. MOD0 controls the 2× low-pass configuration. Images of the sine wave signal appear digital filter response (that is, low-pass or high-pass), and around multiples of the input data rate (that is, fDATA) of the DAC, MOD1 controls the zero-stuffing option. The appropriate mode as predicted by sampling theory. These undesirable images also to select (see Table 9) depends on whether the application appear at the output of a reconstruction DAC, although they are requires the reconstruction of a baseband or IF signal. attenuated by the sin(x)/x roll-off response of the DAC. Rev. C | Page 17 of 40 02253-026 AD9772A In many band-limited applications, the images from the representation for a high-pass response of a discrete time sine reconstruction process must be suppressed by an analog filter wave. This action can also be modeled as a half-wave digital following the DAC. The complexity of this analog filter is typically mixing process in which the impulse response of the low-pass determined by the proximity of the desired fundamental to the filter is digitally mixed with a square wave having a frequency of first image and the required amount of image suppression. exactly fDATA/2. Because the even coefficients have an integer Adding to the complexity of this analog filter is the requirement value of 0 (see Table 5), this process simplifies into inverting the of compensating for the sin(x)/x response of the DAC. center coefficient of the low-pass filter (that is, inverting H(18)). Note that this also corresponds to inverting the peak of the Referring to Figure 27, the new first image associated with the impulse response shown in Figure 4. The resulting high-pass higher data rate of the DAC after interpolation is pushed out frequency response becomes the frequency inverted mirror further relative to the input signal, because it now occurs at 2× image of the low-pass filter response shown in Figure 5. f − f . The old first image associated with the DATA FUNDAMENTAL lower DAC data rate before interpolation is suppressed by the Note that the new first image occurs at fDATA + fFUNDAMENTAL. A digital filter. As a result, the transition band for the analog reduced transition region of 2 × fFUNDAMENTAL exists for image reconstruction filter is increased, thus reducing the complexity selection, thus mandating that the fFUNDAMENTAL be placed of the analog filter. Furthermore, the value of the sin(x)/x roll- sufficiently high for practical filtering purposes in direct IF off divided by the original input data pass band (that is, dc to applications. In addition, the lower sideband images occurring f /2) is significantly reduced. at f − f and its multiples (that is, N × f − DATA DATA FUNDAMENTAL DATA f ) experience a frequency inversion while the upper FUNDAMENTAL As previously mentioned, the 2× interpolation filter can be sideband images occurring at fDATA + fFUNDAMENTAL and its multiples converted into a high-pass response, thus suppressing the fun- (that is, N × fDATA + fFUNDAMENTAL) do not. damental while passing the original first image occurring at fDATA − fFUNDAMENTAL. Figure 28 shows the time and frequency 1/ 2 × f DATA TIME DOMAIN 1/f DATA f FUNDAMENTAL NEW FIRST IMAGE DIGITAL f DAC SIN(x)/x FUNDAMENTAL FIRST IMAGE FILTER RESPONSE RESPONSE FREQUENCY DOMAIN f 2 × f f 2 × f f 2 × f DATA DATA DATA DATA DATA DATA SUPPRESSED FIRST IMAGE 2× INTERPOLATION INPUT DATA FILTER DAC LATCH 2× f 2 × f DATA DATA Figure 27. Time and Frequency Domain Example of Low-Pass 2× Digital Interpolation Filter 1/2 × f DATA TIME DOMAIN 1/f DATA UPPER AND f FUNDAMENTAL FIRST IMAGE DAC SIN(x)/x LOWER IMAGE DIGITAL RESPONSE FILTER RESPONSE FREQUENCY DOMAIN f 2 × f f 2 × f f 2 × f DATA DATA DATA DATA DATA DATA SUPPRESSED f FUNDAMENTAL 2× INTERPOLATION INPUT DATA FILTER DAC LATCH 2× f DATA 2 × f DATA Figure 28. Time and Frequency Domain Example of High-Pass 2× Digital Interpolation Filter Rev. C | Page 18 of 40 02253-028 02253-027 AD9772A Zero-Stuffing Option Description The net effect is to increase the DAC update rate such that the zero in the sin(x)/x frequency response occurs at 4 × f DATA As shown in Figure 29, a zero or null in the frequency response accompanied by a corresponding reduction in output power as (after interpolation and DAC reconstruction) occurs at the final shown in Figure 29. Note that if the high-pass response of the DAC update rate (that is, 2× fDATA) due to the inherent sin(x)/x 2× interpolation filter is also selected, this action can be roll-off response of the DAC. In baseband applications, this roll- modeled as a quarter-wave digital mixing process, because this off in the frequency response may not be as problematic is equivalent to digitally mixing the impulse response of the because much of the desired signal energy remains below low-pass filter with a square wave having a frequency of exactly f /2 and the amplitude variation is not as severe. However, in DATA f (that is, f /4). DATA DAC direct IF applications interested in extracting an image above fDATA/2, this roll-off may be problematic due to the increased It is important to realize that the zero-stuffing option by itself pass-band amplitude variation as well as the reduced signal does not change the location of the images, but rather changes level of the higher images. their signal level, amplitude flatness, and relative weighting. For 0 instance, in the previous example, the pass-band amplitude flatness of the lower and upper sideband images centered WITH around fDATA are improved to 0.14 dB and 0.24 dB, respectively, ZERO-STUFFING –10 while the signal level changes to −6.5 dBFS and −7.5 dBFS. The lower or upper sideband image centered around 3 × f DATA WITHOUT exhibit an amplitude flatness of 0.77 dB and 1.29 dB with signal ZERO-STUFFING –20 levels of approximately −14.3 dBFS and −19.2 dBFS. PLL CLOCK MULTIPLIER OPERATION The phase-lock loop (PLL) clock multiplier circuitry, along with –30 the clock distribution circuitry, can produce the necessary internally synchronized 1×, 2×, and 4× clocks for the edge- –40 triggered latches, 2× interpolation filter, zero-stuffing 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 multiplier, and DAC. Figure 30 shows a functional block FREQUENCY (f ) DATA BASEBAND diagram of the PLL clock multiplier, which consists of a phase REGION detector, a charge pump, a voltage controlled oscillator (VCO), Figure 29. Effects of Zero-Stuffing on the Sin(x)/x Response of the DAC a prescaler, and digital control input/output. The clock For instance, if the digital data into the AD9772A represents a distribution circuitry generates all the internal clocks for a given baseband signal centered around f /4 with a pass band of DATA mode of operation. The charge pump and VCO are powered f /10, the reconstructed baseband signal output from the DATA from PLLVDD, and the differential clock input buffer, phase AD9772A experiences only a 0.18 dB amplitude variation over detector, prescaler, and clock distribution circuitry are powered its pass band, with the first image occurring at 7/4 × fDATA and from CLKVDD. To ensure optimum phase noise performance exhibiting 17 dB of attenuation relative to the fundamental. from the PLL clock multiplier and clock distribution circuitry, However, if the high-pass filter response is selected, the AD9772A PLLVDD and CLKVDD must originate from the same clean produces pairs of images at [(2N + 1) × fDATA] ± fDATA/4, where analog supply. N = 0, 1, and so on. Note that due to the sin(x)/x response of the CLK+ CLK– DAC, only the lower or upper sideband images centered around CLKVDD PLLLOCK + – f may be useful, although they are attenuated by −2.1 dB and DATA AD9772A −6.54 dB and have a pass-band amplitude roll-off of 0.6 dB and 1.3 dB, respectively. To improve on the pass-band flatness of the desired image LPF PHASE CHARGE DNC DETECTOR PUMP and/or to extract higher images (that is, 3 × fDATA ± fFUNDAMENTAL), the zero-stuffing option should be employed by bringing the 2.7V PLLVDD EXT/INT OUT1× TO MOD1 pin high. This option increases the effective DAC CLOCK CONTROL 3.6V update rate by another factor of 2 because a midscale sample CLOCK PLLCOM (that is, 10 0000 0000 0000) is inserted after every data sample DISTRIBUTION PRESCALER VCO originating from the 2× interpolation filter. A digital multiplexer switching at a rate of 4 × fDATA between the interpolation filter output and a data register containing the midscale data sample is CLKCOM used as shown in Figure 28 to implement this option. Therefore, the DAC output is now forced to return to its differential midscale Figure 30. Clock Multiplier with PLL Clock Multiplier Enabled current value (that is, I − I at 0 mA) after reconstructing OUTA OUTB each data sample from the digital filter. Rev. C | Page 19 of 40 ROLL-OFF (dBFS) 02253-029 MOD1 MOD0 RESET DIV1 DIV0 02253-030 AD9772A The PLL clock multiplier has two modes of operation. It can be As previously stated, applications requiring input data rates enabled for less demanding applications, providing a reference below 6 MSPS must disable the PLL clock multiplier and clock meeting the minimum specified input data rate of 6 MSPS. provide an external reference clock. However, for applications Alternatively, it can be disabled for applications below this data already containing a low phase noise (that is, low jitter) reference rate or for applications requiring higher phase noise performance. clock that is twice (or four times) the input data rate, users should In this case, a reference clock must be provided at twice the input consider disabling the PLL clock multiplier to achieve the best SNR data rate (that is, 2 × fDATA) without the zero-stuffing option selected performance from the AD9772A. Note that the SFDR performance or at four times the input data rate (that is, 4 × f ) with the zero- and wideband noise performance of the AD9772A remain DATA stuffing option selected. Note that multiple AD9772A devices unaffected with or without the PLL clock multiplier enabled. can be synchronized in either mode if driven by the same reference The effects of phase noise on the AD9772A SNR performance clock because the PLL clock multiplier, when enabled, ensures become more noticeable at higher reconstructed output fre- synchronization. RESET can be used for synchronization if the quencies and signal levels. Figure 31 compares the phase noise PLL clock multiplier is disabled. of a full-scale sine wave at exactly fDATA/4 for different data rates Figure 30 shows the proper configuration used to enable the (and therefore carrier frequencies) with the optimum DIV1 and PLL clock multiplier. In this case, the external clock source is DIV0 settings. The effects of phase noise, and its effect on a applied to CLK+ (and/or CLK−) and the PLL clock multiplier is signal’s CNR performance, become even more evident at higher fully enabled by connecting PLLVDD to CLKVDD. IF frequencies, as shown in Figure 32. In both instances, it is the narrow-band phase noise that limits the CNR performance. The settling/acquisition time characteristics of the PLL are also 0 dependent on the divide-by-N ratio as well as the input data –10 rate. In general, the acquisition time increases with increasing –20 data rate (for fixed divide-by-N ratio) or with an increasing divide-by-N ratio (for fixed input data rate). –30 –40 Because the VCO can operate over a 96 MHz to 400 MHz –50 range, the prescaler divide-by-ratio following the VCO must be PLL ENABLED, f = 160MSPS DATA –60 set according to Table 10 for a given input data rate (that is, PLL ENABLED, f = 100MSPS DATA f ) to ensure optimum phase noise and successful locking. In –70 DATA PLL ENABLED, f = 75MSPS DATA general, the best phase noise performance for any prescaler –80 PLL ENABLED, f = 50MSPS DATA setting is achieved with the VCO operating near its maximum –90 output frequency of 400 MHz. Note that the divide-by-N ratio –100 PLL ENABLED, f = 50MSPS DATA also depends on whether the zero-stuffing option is enabled –110 0 12 3 4 5 because this option requires the DAC to operate at 4× the input FREQUENCY OFFSET (MHz) data rate. The divide-by-N ratio is set by DIV1 and DIV0. Figure 31. Phase Noise of PLL Clock Multiplier with a Full-Scale Sine Wave at Exactly fOUT = fDATA/4 for Different fDATA Settings with Optimum DIV0/DIV1 With the PLL clock multiplier enabled, PLLLOCK serves as an Settings Using the Rohde & Schwarz FSEA30, RBW = 30 kHz active high control output that can be monitored upon system 10 power-up to indicate that the PLL is successfully locked to the input clock. Note that when the PLL clock multiplier is not –10 locked, PLLLOCK toggles between logic high and low in an asynchronous manner until locking is finally achieved. As a –30 result, it is recommended that PLLLOCK, if monitored, be sampled several times to detect proper locking 100 ms after –50 power-up. –70 Table 10. Recommended Prescaler Divide-by-N Ratio Settings f DATA –90 (MSPS) MOD1 DIV1 DIV0 Divide-by-N Ratio 48 to 160 0 0 0 1 –110 24 to 100 0 0 1 2 120 122 124 126 128 130 FREQUENCY (MHz) 12 to 50 0 1 0 4 6 to 25 0 1 1 8 Figure 32. Direct IF Mode Reveals Phase Noise Degradation with and Without PLL Clock Multiplier (IF = 125 MHz and fDATA = 100 MSPS) 24 to 100 1 0 0 1 12 to 50 1 0 1 2 To disable the PLL clock multiplier, connect PLLVDD to 6 to 25 1 1 0 4 Figure 33. LPF can then remain open PLLCOM as shown in 3 to 12.5 1 1 1 8 because this portion of the PLL circuitry is disabled. The Rev. C | Page 20 of 40 AMPLITUDE (dBm) NOISE DENSITY (dBm/Hz) 02253-031 02253-032 AD9772A differential clock input should be driven with a reference clock Logic 0. The following rising edge of the 2× clock causes the 1× that is twice the data input rate in baseband applications, or that clock to go to Logic 1 again and updates the data in both of the is four times the data input rate in direct IF applications in input latches. which the quarter-wave mixing option is employed (that is, DIGITAL DATA IN DATA MOD1 and MOD0 active high). The clock distribution circuitry remains enabled, providing a 1× internal clock at PLLLOCK. EXTERNAL t LPW 2× CLOCK Digital input data is latched into the AD9772A on every other t t PD PD rising edge of the differential clock input. The rising edge that DELAYED INTERNAL corresponds to the input latch immediately precedes the rising 1× CLOCK t edge of the 1× clock at PLLLOCK. Adequate setup and hold D LOAD-DEPENDENT, times for the input data, as shown in Figure 3, should be DELAYED 1× CLOCK AT PLLLOCK allowed. Note that enough delay is present between I OR I OUTA OUTB DATA ENTERS INPUT CLK+/CLK− and the data input latch to cause the minimum LATCHES ON THIS EDGE setup time for input data to be negative. This is noted in the Figure 34. Internal Timing of AD9772A with PLL Disabled Digital Filter Specifications section. PLLLOCK contains a Figure 35 and Figure 36 illustrate the details of the RESET relatively weak driver output, with its output delay (t ) OD sensitive to output capacitance loading. Therefore, PLLLOCK function timing. The RESET pin going from a high to a low should be buffered for fanouts greater than 1 and/or for load logic level enables the 1× clock output generated by the capacitance greater than 10 pF. If a data timing issue exists PLLLOCK pin. If RESET goes low before the rising edge of the 2× clock as shown in Figure 35, PLLLOCK goes high on the between the AD9772A and its external driver device, the following edge of the 2× clock. If RESET goes from a high to a 1× clock appearing at PLLLOCK can be inverted via an external low logic level 600 ps or later following the rising edge of the 2× gate to ensure proper setup and hold time. clock, as shown in Figure 36, there is a delay of one 2× clock CLK+ CLK– cycle before PLLLOCK goes high. In either case, as long as CLKVDD PLLLOCK + – RESET remains low, PLLLOCK changes state on every rising AD9772A edge of the 2× clock. As previously stated, the rising edge of the 2× clock immediately preceding the rising edge of PLLLOCK latches data into the AD9772A input latches. PHASE CHARGE LPF DETECTOR PUMP [ ] T EXTERNAL 1× CLOCK PLLVDD EXT/INT OUT1× CLOCK CONTROL T 1 CLOCK DISTRIBUTION PRESCALER VCO PLLCOM T 2 PLLLOCK T CLKCOM MOD1 MOD0 RESET DIV1 DIV0 RESET 3 Figure 33. Clock Multiplier with PLL Clock Multiplier Disabled CH1 2.00VΩ CH2 2.00VΩ M 10.0ns CH3 2.00VΩ SYNCHRONIZATION OF CLOCK/DATA USING Figure 35. RESET Timing with PLL Disabled RESET WITH PLL DISABLED [ T ] EXTERNAL The relationship between the internal and external clocks in 2× CLOCK this mode is shown in Figure 34. A clock at the output update T 1 data rate (2× the input data rate) must be applied to the CLK+ PLLLOCK and CLK− inputs. Internal dividers create the internal 1× clock necessary for the input latches. With the PLL disabled, a delayed T 2 T version of the 1× clock is present at the PLLLOCK pin. The DAC latch is updated on the rising edge of the external 2× clock that corresponds to the rising edge of the 1× clock. Updates to RESET 3 the input data should be synchronized to this rising edge as CH1 2.00VV CH2 2.00VV M 10.0ns CH4 1.20V shown in Figure 34. To ensure this synchronization, a Logic 1 CH3 2.00VΩ should be momentarily applied to the RESET pin on power-up Figure 36. RESET Timing with PLL Disabled and Insufficient Setup Time before CLK+/CLK− is applied. Momentarily applying a Logic 1 to the RESET pin brings the 1× clock at PLLLOCK to a Logic 1. On the next rising edge of the 2× clock, the 1× clock goes to Rev. C | Page 21 of 40 02253-033 02253-036 02253-035 02253-034 AD9772A where: DAC OPERATION I = V /R (4) The 14-bit DAC, along with the 1.2 V reference and reference REF REFIO SET control amplifier, is shown in Figure 37. The DAC consists of a The two current outputs typically drive a resistive load directly large PMOS current source array capable of providing up to or via a transformer. If dc coupling is required, IOUTA and IOUTB 20 mA of full-scale current, I . The array is divided into 31 OUTFS should be directly connected to matching resistive loads, RLOAD, equal currents that make up the five most significant bits that are tied to analog common, ACOM. Note that RLOAD can (MSBs). The next four bits, or middle bits, consist of 15 equal represent the equivalent load resistance seen by IOUTA or IOUTB, as th current sources whose values are 1/16 of an MSB current would be the case in a doubly terminated 50 Ω or 75 Ω cable. source. The remaining LSBs are binary-weighted fractions of The single-ended voltage output appearing at the I and I OUTA OUTB the middle bits’ current sources. All of these current sources are nodes is simply switched to one of the two output nodes (that is, IOUTA or IOUTB) via V = I × R (5) OUTA OUTA LOAD the PMOS differential current switches. Implementing the middle and lower bits with current sources instead of an R-2R ladder VOUTB = IOUTB × RLOAD (6) enhances its dynamic performance for multitone or low amplitude Note that the full-scale value of VOUTA and VOUTB should not signals and helps maintain the high output impedance of the DAC. exceed the specified output compliance range of 1.25 V to 2.7V TO 3.6V prevent signal compression. To maintain optimum distortion and linearity performance, the maximum voltages at V and OUTA REFLO AVDD ACOM V should not exceed ±500 mV p-p. OUTBB250pF 1.2V REF The differential voltage, V , appearing across I and I is REFIO DIFF OUTA OUTBB CURRENT 0.1µF SOURCE FSADJ ARRAY VDIFF = (IOUTA − IOUTB) × RLOAD (7) I REF R I SET OUTA I OUTA V = V – V Substituting the values of IOUTA, IOUTBB, and IREF, VDIFF can be DIFF OUTA OUTB 2kΩ SEGMENTED LSB expressed as SWITCHES SWITCHES R LOAD I OUTB I OUTB R LOAD VDIFF = [(2 DAC CODE − 16,383)/16,384] × AD9772A (32 × R /R ) × V (8) LOAD SET REFIO INTERPOLATED DIGITAL DATA The last two equations highlight some of the advantages of operating the AD9772A differentially. First, the differential Figure 37. Block Diagram of Internal DAC, 1.2 V Reference, and Reference Control Circuits operation helps cancel common-mode error sources, such as noise, distortion, and dc offsets, associated with IOUTA and IOUTB. The full-scale output current is regulated by the reference Second, the differential code-dependent current and control amplifier and can be set from 2 mA to 20 mA via an subsequent voltage, VDIFF, is twice the value of the single- ended external resistor, R , as shown in Figure 37. R , in SET SET voltage output (that is, V or V ), thus providing twice the OUTA OUTBB combination with both the reference control amplifier and signal power to the load. voltage reference, REFIO, sets the reference current, I , which REF is mirrored to the segmented current sources with the proper Note that the gain drift temperature performance for a single- scaling factor. The full-scale current, IOUTFS, is exactly 32 times ended (V and V ) or differential output (V ) of the OUTA OUTBBDIFF the value of IREF. AD9772A can be enhanced by selecting temperature tracking resistors for RLOAD and RSET due to their ratiometric relationship, DAC TRANSFER FUNCTION as shown in Equation 8. The AD9772A provides complementary current outputs, IOUTA REFERENCE OPERATION and IOUTBB. IOUTA provides a near full-scale current output, IOUTFS, when all bits are high (that is, DAC CODE = 16,383), whereas The AD9772A contains an internal 1.20 V band gap reference IOUTBB, the complementary output, provides no current. The that can easily be disabled and overridden by an external current output appearing at I and I is a function of both OUTA OUTBBreference. REFIO serves as either an output or input, depend- the input code and I and can be expressed as OUTFS ing on whether the internal or external reference is selected. If REFLO is tied to ACOM, as shown in Figure 38, the internal I = (DAC CODE/16,384) × I (1) OUTA OUTFS reference is activated, and REFIO provides a 1.20 V output. In I = (16,383 − DAC CODE)/16,384 × I (2) OUTB OUTFS this case, the internal reference must be compensated externally where DAC CODE = 0 to 16,383 (that is, decimal representation). with a ceramic chip capacitor of 0.1 μF or greater from REFIO to REFLO. If any additional loading is required, REFIO should As previously mentioned, IOUTFS is a function of the reference be buffered with an external amplifier having an input bias current (IREF), which is nominally set by a reference voltage current less than 100 nA. (VREFIO) and an external resistor (RSET). It can be expressed as I = 32 × I (3) OUTFS REF Rev. C | Page 22 of 40 02253-037 AD9772A 2.7V TO 3.6V OPTIONAL along with the AD1580 voltage reference. Note that because the EXTERNAL REF BUFFER input impedance of REFIO does interact with and load the REFLO AVDD digital potentiometer wiper to create a slight nonlinearity in the 250pF 1.2V REF programmable voltage divider ratio, a digital potentiometer REFIO ADDITIONAL CURRENT with 10 kΩ or less resistance is recommended. LOAD 0.1µF SOURCE FSADJ ARRAY 2.7V TO 3.6V 2kΩ AD9772A REFLO AVDD 10kΩ 250pF AD5220 Figure 38. Internal Reference Configuration 1.2V REF 1.2V REFIO CURRENT The internal reference can be disabled by connecting REFLO to AD1580 10kΩ SOURCE FSADJ AVDD. In this case, an external 1.2 V reference, such as the ARRAY AD1580, can be applied to REFIO as shown in Figure 39. The R AD9772A SET external reference can provide either a fixed reference voltage to enhance accuracy and drift performance or a varying reference Figure 40. Single-Supply Gain Control Circuit voltage to improve gain control. Note that the 0.1 μF compensation ANALOG OUTPUTS capacitor is not required because the internal reference is disabled and the high input impedance of REFIO minimizes any loading The AD9772A produces two complementary current outputs, of the external reference. I and I , which can be configured for single-ended or OUTA OUTB differential operation. I and I can be converted into 2.7V TO 3.6V OUTA OUTBB complementary single-ended voltage outputs, VOUTA and VOUTB, via a load resistor, RLOAD, as described in the DAC Transfer REFLO AVDD 10kΩ 250pF Function section, by using Equation 5 through Equation 8. The +1.2V REF differential voltage, VDIFF, existing between VOUTA and VOUTB, can V REFIO REFIO CURRENT also be converted to a single-ended voltage via a transformer or SOURCE FSADJ AD1580 ARRAY differential amplifier configuration. I = REF R SET V /R REFIO SET Figure 41 shows the equivalent analog output circuit of the REFERENCE AD9772A CONTROL AD9772A, which consists of a parallel combination of PMOS AMPLIFIER differential current switches associated with each segmented Figure 39. External Reference Configuration current source. The output impedance of IOUTA and IOUTBB is determined by the equivalent parallel combination of the PMOS REFERENCE CONTROL AMPLIFIER switches and is typically 200 kΩ in parallel with 3 pF. Due to the The AD9772A also contains an internal control amplifier that is nature of a PMOS device, the output impedance is also slightly used to regulate the DAC’s full-scale output current, IOUTFS. The dependent on the output voltage (that is, V and V ) and, OUTA OUTB control amplifier is configured as a V-I converter, as shown in to a lesser extent, the analog supply voltage, AVDD, and full- Figure 39, such that its current output, IREF, is determined by the scale current, I . Although the signal dependency of the OUTFS ratio of the V and an external resistor, R , as stated in REFIO SET output impedance can be a source of dc nonlinearity and ac Equation 4. I is copied to the segmented current sources with REF linearity (that is, distortion), its effects can be limited if certain the proper scaling factor to set I as stated in Equation 3. OUTFS precautions are taken. The control amplifier allows a wide (10:1) adjustment span of AVDD IOUTFS over a 2 mA to 20 mA range by setting IREF between 62.5 μA and 625 μA. The wide adjustment span of IOUTFS pro- vides several application benefits. The first benefit relates directly to the power dissipation of the AD9772A DAC, which AD9772A is proportional to I (see the Power Dissipation section). OUTFS The second benefit relates to the 20 dB adjustment, which is useful for system gain control purposes. I I OUTA OUTB I can be controlled using the single-supply circuit shown in REF R R LOAD LOAD Figure 40 for a fixed RSET. In this example, the internal refer- ence is disabled, and the voltage of REFIO is varied over its Figure 41. Equivalent Analog Output Circuit compliance range of 1.25 V to 0.10 V. REFIO can be driven by a I and I also have a negative and positive voltage OUTA OUTB single-supply DAC or digital potentiometer, thus allowing I REF compliance range. The negative output compliance threshold to be digitally controlled for a fixed R . This particular example SET of −1.0 V is set by the breakdown limits of the CMOS process. shows the AD5220, an 8-bit serial input digital potentiometer, Operation beyond this maximum limit may result in a breakdown Rev. C | Page 23 of 40 02253-039 02253-038 02253-041 02253-040 AD9772A of the output stage and affect the reliability of the AD9772A. produces a complementary output with the full-scale current The positive output compliance range is slightly dependent on split between the two outputs as a function of the input code. the full-scale output current, I . Operation beyond the OUTFS The digital interface is implemented using an edge-triggered positive compliance range induces clipping of the output signal, master slave latch and is designed to support an input data rate as which severely degrades the AD9772A linearity and distortion high as 160 MSPS. The clock can be operated at any duty cycle that performance. meets the specified latch pulse width, as shown in Figure 2 and Operating the AD9772A with reduced voltage output swings Figure 3. The setup and hold times can also be varied within the at I and I in a differential or single-ended output clock cycle as long as the specified minimum times are met. The OUTA OUTB configuration reduces the signal dependency of its output digital inputs (excluding CLK+ and CLK−) are CMOS compatible impedance, thus enhancing distortion performance. Although with its logic thresholds, V , set to approximately half the THRESHOLD the voltage compliance range of I and I extends from digital positive supply (that is, DVDD or CLKVDD) or OUTA OUTBB −1.0 V to +1.25 V, optimum distortion performance is achieved VTHRESHOLD = DVDD/2 (±20%) when the maximum full-scale signal at IOUTA and IOUTBB does not The internal digital circuitry of the AD9772A is capable of exceed approximately 0.5 V. Using a properly selected operating over a digital supply range of 3.1 V to 3.5 V. As a transformer with a grounded center tap allows the AD9772A to result, the digital inputs can also accommodate TTL levels when provide the required power and voltage levels to different loads DVDD is set to accommodate the maximum high level voltage while maintaining reduced voltage swings at I and I . OUTA OUTB of the TTL drivers V . Although a DVDD of 3.3 V OH(MAX) DC-coupled applications requiring a differential or single- typically ensures proper compatibility with most TTL logic ended output configuration should size RLOAD accordingly. Refer families, series 200 Ω resistors are recommended between the to the Output Configurations section for examples of various TTL logic driver and digital inputs to limit the peak current output configurations. through the ESD protection diodes if VOH(MAX) exceeds DVDD The most significant improvement in the AD9772A distortion by more than 300 mV. Figure 42 shows the equivalent digital and noise performance is realized using a differential output input circuit for the data and control inputs. configuration. The common-mode error sources of both I OUTA DVDD and I can be substantially reduced by the common-mode OUTBB rejection of a transformer or differential amplifier. These common-mode error sources include even-order distortion DIGITAL INPUT products and noise. The enhancement in distortion performance becomes more significant as the reconstructed waveform’s frequency content increases and/or its amplitude decreases. The Figure 42. Equivalent Digital Input distortion and noise performance of the AD9772A is also dependent on the full-scale current setting, I . Although I OUTFS OUTFS The AD9772A features a flexible differential clock input operating can be set between 2 mA and 20 mA, selecting an I of 20 mA OUTFS from separate supplies (that is, CLKVDD, CLKCOM) to achieve provides the best distortion and noise performance. optimum jitter performance. The two clock inputs, CLK+ and CLK−, can be driven from a single-ended or differential clock In summary, the AD9772A achieves the optimum distortion source. For single-ended operation, CLK+ should be driven by a and noise performance under the following conditions: single-ended logic source, and CLK− should be set to the logic • Positive voltage swing at IOUTA and IOUTBB limited to 0.5 V source’s threshold voltage via a resistor divider/capacitor network • Differential operation referenced to CLKVDD as shown in Figure 43. For differential • I set to 20 mA OUTFS operation, both CLK+ and CLK− should be biased to CLKVDD/2 • PLL clock multiplier disabled via a resistor divider network as shown in Figure 44. An RF transformer as shown in Figure 7 can also be used to convert a Note that the majority of the ac characterization curves for the AD9772A are performed with these operating conditions. single-ended clock input to a differential clock input. AD9772A DIGITAL INPUTS/OUTPUTS The AD9772A consists of several digital input pins used for R SERIES CLK+ data, clock, and control purposes. It also contains a single digital output pin, PLLLOCK, which is used to monitor the CLKVDD status of the internal PLL clock multiplier or provide a 1× clock 1kΩ CLK– output. The 14-bit parallel data inputs follow standard positive V THRESHOLD 1kΩ 0.1µF binary coding, where DB13 is the most significant bit (MSB) CLKCOM and DB0 is the least significant bit (LSB). I produces a full- OUTA scale output current when all data bits are at Logic 1. I OUTBB Figure 43. Single-Ended Clock Interface Rev. C | Page 24 of 40 02253-042 02253-043 AD9772A The power dissipation is directly proportional to the analog AD9772A supply current, I , and the digital supply current, I . I AVDD DVDD AVDD 1kΩ 0.1µF is directly proportional to I and is not sensitive to f . OUTFS DATA CLK+ 1kΩ Conversely, IDVDD is dependent on both the digital input ECL/PECL CLKVDD 0.1µF waveform and fDATA. Figure 45 shows IDVDD as a function of full- 1kΩ CLK– scale sine wave output ratios (fOUT/fDATA) for various update rates 0.1µF 1kΩ with DVDD = 3.3 V. The supply current from CLKVDD and CLKCOM PLLVDD is relatively insensitive to the digital input waveform but directly proportional to the update rate, as shown in Figure 46. Figure 44. Differential Clock Interface 100 f = 160MSPS DATA The quality of the clock and data input signals is important in 90 achieving the optimum performance. The external clock driver f = 125MSPS 80 DATA circuitry should provide the AD9772A with a low jitter clock 70 f = 100MSPS DATA input, which meets the minimum/maximum logic levels while 60 providing fast edges. Although fast clock edges help minimize 50 jitter manifesting as phase noise on a reconstructed waveform, f = 65MSPS DATA the high gain-bandwidth product of the AD9772A differential 40 comparator can tolerate sine wave inputs as low as 0.5 V p-p, 30 f = 50MSPS DATA with minimal degradation in its output noise floor. 20 f = 25MSPS DATA Digital signal paths should be kept short, and run lengths 10 should match to avoid propagation delay mismatch. The 0 0 0.1 0.2 0.3 0.4 0.5 insertion of a low value resistor network (that is, 50 Ω to 200 Ω) RATIO (f /f ) OUT DATA between the AD9772A digital inputs and driver outputs may be Figure 45. IDVDD vs. Ratio @ DVDD = 3.3 V helpful in reducing overshooting and ringing at the digital 25 inputs that contribute to data feedthrough. SLEEP MODE OPERATION I CLKVDD 20 The AD9772A has a sleep function that turns off the output current I PLLVDD and reduces the analog supply current to less than 6 mA over the 15 specified supply range of 3.1 V to 3.5 V. This mode can be activated by applying a Logic Level 1 to the SLEEP pin. The AD9772A takes less than 50 ns to power down and then approximately 15 μs 10 to power up. POWER DISSIPATION 5 The power dissipation, PD, of the AD9772A is dependent on several factors, including 0 0 50 100 150 200 • The power supply voltages (AVDD, PLLVDD, CLKVDD, f (MSPS) DATA and DVDD) Figure 46. I and I vs. f PLLVDD CLKVDD DATA • The full-scale current output (I ) OUTFS • The update rate (f ) DATA • The reconstructed digital input waveform Rev. C | Page 25 of 40 02253-044 CURRENT (mA) I (mA) DVDD 02253-046 02253-045 AD9772A APPLYING THE AD9772A passive reconstruction filter or cable. RDIFF is determined by the OUTPUT CONFIGURATIONS transformer’s impedance ratio and provides the proper source The following sections illustrate some typical output termination, resulting in a low voltage standing wave ratio configurations for the AD9772A. Unless otherwise noted, it is (VSWR). Note that approximately half the signal power is assumed that I is set to a nominal 20 mA for optimum OUTFS dissipated across R . DIFF performance. For applications requiring the optimum dynamic DIFFERENTIAL COUPLING USING AN OP AMP performance, a differential output configuration can consist of either an RF transformer or a differential op amp configuration. An op amp can also be used to perform a differential-to-single- The transformer configuration provides the optimum high ended conversion as shown in Figure 48. The AD9772A is frequency performance and is recommended for any application configured with two equal load resistors, R , each of 25 Ω. The LOAD allowing ac coupling. The differential op amp configuration is differential voltage developed across I and I is converted to OUTA OUTB suitable for applications requiring dc coupling, a bipolar output, a single-ended signal via the differential op amp configuration. An signal gain, and/or level shifting. optional capacitor can be installed across I and I , forming a OUTA OUTB real pole in a low-pass filter. The addition of this capacitor also A single-ended output is suitable for applications requiring a enhances the distortion performance of the op amp by preventing unipolar voltage output. A positive unipolar output voltage the DAC’s high slewing output from overloading the op amp input. results if IOUTA and/or IOUTBB is connected to an appropriately 500Ω sized load resistor, RLOAD, referred to ACOM. This configuration AD9772A 225Ω may be more suitable for a single-supply system requiring a dc- I OUTA coupled, ground-referred output voltage. Alternatively, an amplifier AD8055 225Ω I can be configured as an I-V converter, thus converting I or OUTB OUTA C OPT IOUTBB into a negative unipolar voltage. This configuration 500Ω 25Ω 25Ω provides the best dc linearity because IOUTA or IOUTBB is maintained at a virtual ground. Figure 48. DC Differential Coupling Using an Op Amp DIFFERENTIAL COUPLING USING A TRANSFORMER The common-mode rejection of this configuration is typically An RF transformer can be used as shown in Figure 47 to perform a determined by the resistor matching. In this circuit, the differential differential-to-single-ended signal conversion. A differentially op amp circuit using the AD8055 is configured to provide some coupled transformer output provides the optimum distortion additional signal gain. The op amp must operate from a dual performance for output signals whose spectral content lies within supply because its output is approximately ±1.0 V. A high speed the pass band of the transformer. An RF transformer such as the amplifier capable of preserving the differential performance of Mini-Circuits® T1-1T provides excellent rejection of common- the AD9772A while meeting other system-level objectives (such mode distortion (that is, even-order harmonics) and noise over a as cost and power) should be selected. The op amp’s differential wide frequency range. It also provides electrical isolation and the gain, gain-setting resistor values, and full-scale output swing ability to deliver twice the power to the load. Transformers with capabilities should be considered when optimizing this circuit. different impedance ratios can also be used for impedance The differential circuit shown in Figure 49 provides the matching purposes. Note that the transformer provides ac coupling necessary level shifting required in a single-supply system. In only, and its linearity performance degrades at the low end of its this case, AVDD, the positive analog supply for both the frequency range due to core saturation. AD9772A and the op amp, is also used to level-shift the AD9772A MINI-CIRCUITS differential output of the AD9772A to midsupply (that is, T1-1T I OUTA AVDD/2). The AD8057 is a suitable op amp for this application. OPTIONAL R LOAD 500Ω R DIFF AD9772A I 225Ω OUTB I OUTA AD8057 225Ω I OUTB Figure 47. Differential Output Using a Transformer C OPT 1kΩ AVDD The center tap on the primary side of the transformer must be 25Ω 25Ω 1kΩ connected to ACOM to provide the necessary dc current path for both I and I . The complementary voltages appearing OUTA OUTBB Figure 49. Single-Supply DC Differential Coupled Circuit at I and I (that is, V and V ) swing symmetrically OUTA OUTB OUTA OUTB SINGLE-ENDED, UNBUFFERED VOLTAGE OUTPUT around ACOM and should be maintained with the specified output compliance range of the AD9772A. A differential Figure 50 shows the AD9772A configured to provide a unipolar resistor, RDIFF, can be inserted into applications in which the output range of approximately 0 V to 0.5 V for a doubly termi- output of the transformer is connected to the load, RLOAD, via a nated 50 Ω cable because the nominal full-scale current, IOUTFS, Rev. C | Page 26 of 40 02253-047 02253-048 02253-049 AD9772A of 20 mA flows through the equivalent R of 25 Ω. In this To meet the first condition, PLLVDD must be driven by the LOAD case, R represents the equivalent load resistance seen by same power source as CLKVDD, with each supply input LOAD I . The unused output (I ) should be connected directly to independently decoupled using a 0.1 μF capacitor connected to OUTA OUTB ACOM. Different values of IOUTFS and RLOAD can be selected as long its respective ground. To meet the second condition, CLKVDD as the positive compliance range is adhered to. One additional can share the same power supply source as DVDD by using the consideration in this mode is the integral nonlinearity (INL), as decoupling network shown in Figure 52 to isolate digital noise discussed in the Analog Outputs section of this data sheet. For from the sensitive CLKVDD (and PLLVDD) supply. Alternatively, optimum INL performance, the single-ended, buffered voltage separate precision voltage regulators can be used to ensure that output configuration is suggested. the second condition is met. In systems seeking to simultaneously achieve high speed and AD9772A I = 20mA OUTFS V = 0V TO 0.5V OUTA high performance, the implementation and construction of the I OUTA printed circuit board design is often as important as the circuit 50Ω 50Ω I OUTB design. Proper RF techniques must be used in device selection, placement and routing, and supply bypassing and grounding. Figure 60 to Figure 67 illustrate the recommended printed Figure 50. 0 V to 0.5 V Unbuffered Voltage Output circuit board ground, power, and signal plane layouts that are SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT implemented on the AD9772A evaluation board. Figure 51 shows a single-ended, buffered output configuration Proper grounding and decoupling should be a primary in which the op amp U1 performs an I-V conversion on the objective in any high speed, high resolution system. The AD9772A output current. U1 maintains IOUTA (or IOUTB) at virtual AD9772A features separate analog and digital supply and ground, thus minimizing the nonlinear output impedance effect ground pins to optimize the management of analog and digital on the INL performance of the DAC, as discussed in the Analog ground currents in a system. AVDD, CLKVDD, and PLLVDD Outputs section. Although this single-ended configuration must be powered from a clean analog supply and decoupled to typically provides the best dc linearity performance, its ac their respective analog common (that is, ACOM, CLKCOM, and distortion performance at higher DAC update rates is often PLLCOM) as close to the chip as physically possible. Similarly, the limited by U1’s slewing capabilities. U1 provides a negative digital supplies (DVDD) should be decoupled to DCOM. unipolar output voltage, and its full-scale output voltage is For applications requiring a single 3.3 V supply for the analog, simply the product of RFB and IOUTFS. The full-scale output digital, and phase-lock loop supplies, a clean AVDD and/or should be set within U1’s voltage output swing capabilities CLKVDD can be generated using the circuit shown in Figure 52. by scaling I and/or R . An improvement in ac distortion OUTFS FB The circuit consists of a differential LC filter with separate power performance may result in a reduced I because the signal OUTFS supply and return lines. Lower noise can be attained using low ESR- current that U1 will be required to sink is subsequently reduced. type electrolytic and tantalum capacitors. C OPT FERRITE BEADS R TTL/CMOS FB AVDD 200Ω LOGIC + + 100µF 10µF TO 22µF 0.1µF AD9772A CIRCUITS I = 10mA OUTFS – ELECTROLYTIC –TANTALUM CERAMIC I ACOM OUTA U1 V = –I × R OUT OUTFS FB I OUTB 3.3V 200Ω POWER SUPPLY Figure 51. Unipolar Buffered Voltage Output Figure 52. Differential LC Filter for 3.3 V POWER AND GROUNDING CONSIDERATIONS Maintaining low noise on power supplies and ground is critical for achieving optimum results from the AD9772A. If properly The AD9772A contains the following power supply inputs: implemented, ground planes can perform a host of functions on AVDD, DVDD, CLKVDD, and PLLVDD. The AD9772A is high speed circuit boards, such as bypassing and shielding specified to operate over a 3.1 V to 3.5 V supply range, thus current transport. In mixed-signal designs, the analog and accommodating a 3.3 V power supply with up to ±6% digital portions of the board should be distinct from each other, regulation. However, the following two conditions must be with the analog ground plane confined to the areas covering the adhered to when selecting power supply sources for AVDD, analog signal traces, and the digital ground plane confined to DVDD, CLKVDD, and PLLVDD: areas covering the digital interconnects. • PLLVDD = CLKVDD = 3.1 V to 3.5 V when the PLL clock All analog ground pins of the DAC, reference, and other analog multiplier is enabled (otherwise, PLLVDD = PLLCOM) components should be tied directly to the analog ground plane. • DVDD = CLKVDD ± 0.30 V The two ground planes should be connected by a path ⅛ to ¼ inch wide underneath or within ½ inch of the DAC to maintain Rev. C | Page 27 of 40 02253-050 02253-051 02253-052 AD9772A optimum performance. Care should be taken to ensure that the drops in the signal ground paths. It is recommended that all ground plane is uninterrupted over crucial signal paths. On the connections be short, direct, and as physically close to the digital side, this includes the digital input lines running to the package as possible to minimize the sharing of conduction paths between different currents. When runs exceed an inch in DAC. On the analog side, this includes the DAC output signal, the reference signal, and the supply feeders. length, use of strip line techniques with proper termination resistors should be considered. The necessity and value of these The use of wide runs or planes in the routing of power lines is resistors depends on the logic family used. also recommended. This serves the dual role of providing a low series impedance power supply to the part and allowing some For a more detailed discussion of the implementation and capacitive decoupling to the appropriate ground plane. It is construction of high speed, mixed-signal printed circuit boards, essential that care be taken in the layout of signal and power refer to the AN-333 Application Note. ground interconnections to avoid inducing extraneous voltage Rev. C | Page 28 of 40 AD9772A APPLICATIONS INFORMATION –10 MULTICARRIER –20 The AD9772A’s wide dynamic range performance makes it well –30 suited for next-generation base station applications in which it –40 reconstructs multiple modulated carriers over a designated fre- quency band. Cellular multicarrier and multimode radios are –50 often referred to as software radios because the carrier tuning –60 and modulation scheme is software programmable and performed –70 digitally. The AD9772A is the recommended TxDAC® in the –80 Analog Devices, Inc., SoftCell® chipset, which comprises the –90 AD6622 (a quadrature digital upconverter IC), the AD6624 (an Rx digital downconverter IC that acts as a companion to the –100 AD6622), and the AD6644 (a 14-bit, 65 MSPS ADC). Figure 53 –110 0 5 10 15 20 25 shows a generic software radio Tx signal chain using the FREQUENCY (MHz) AD9772A and AD6622. Figure 55. Spectral Plot of AD9772A Reconstructing Four GSM-Modulated Carriers @ fDATA = 52 MSPS, PLLVDD = 0 Figure 54 shows a spectral plot of the AD9772A operating at 64.54 MSPS, reconstructing eight IS-136-modulated carriers spread Although the above IS-136 and GSM spectral plots are over a 25 MHz band. In this example, the AD9772A exhibits an representative of the AD9772A’s performance for a set of test SFDR performance of 74 dBc and a carrier-to-noise ratio (CNR) of conditions, the following recommendations are offered to 73 dB. Figure 55 shows a spectral plot of the AD9772A operating at maximize the performance and system integration of the 52 MSPS, reconstructing four equal GSM-modulated carriers AD9772A into multicarrier applications: spread over a 15 MHz band. The SFDR and CNR (in 100 kHz BW) 1. To achieve the highest possible CNR, the PLL clock are measured to be 76 dBc and 83.4 dB, respectively, and have a multiplier should be disabled (that is, PLLVDD to channel power of −13.5 dBFS. The test vectors were generated PLLCOM) and the AD9772A clock input should be driven using the Rohde & Schwarz WinIQSIM software. with a low jitter, low phase noise clock source at twice the input data rate. In this case, the divide-by-2 clock CLK AD6622 appearing at PLLLOCK should serve as the master clock CIC NCO for the digital upconverter IC(s), such as the AD6622. SPORT RCF PLLLOCK CLK+/ FILTER QAM CLK– PLLLOCK should be limited to a fanout of 1. CIC NCO AD9772A SPORT RCF FILTER QAM 2. The AD9772A achieves its optimum noise and distortion SUMMATION performance when the device is configured for baseband CIC NCO SPORT RCF OTHER AD6622s FOR FILTER QAM operation and the differential output and full-scale current, INCREASED CHANNEL CIC NCO CAPACITY I , are set to approximately 20 mA. OUTFS SPORT RCF FILTER QAM 3. Although the frequency roll-off of the 2× interpolation JTAG µPORT filter provides a maximum reconstruction bandwidth of Figure 53. Generic Multicarrier Signal Chain Using the AD6622 and AD9772A 0.422 × fDATA, the optimum adjacent image rejection (due to the interpolation process) can be achieved (that is, > 73 dBc) if –20 the maximum channel assignment is kept below 0.400 × fDATA. –30 4. To simplify the filter requirements (that is, mixer image –40 and LO rejection) of the subsequent IF stages, it is often advantageous to offset the frequency band from dc to relax –50 the transition band requirements of the IF filter. –60 5. Oversampling the frequency band often results in improved –70 SFDR and CNR performance. This implies that the data input rate to the AD9772A is greater than fPASSBAND/0.4 Hz, where –80 f is the maximum bandwidth that the AD9772A is PASSBAND –90 required to reconstruct and place carriers. The improved noise performance results in a reduction in the TxDAC’s noise –100 0 510 15 20 25 30 spectral density due to the added process gain realized with FREQUENCY (MHz) oversampling, and higher oversampling ratios provide greater Figure 54. Spectral Plot of AD9772A Reconstructing Eight IS-136-Modulated flexibility in the frequency planning. Carriers @ fDATA = 64.54 MSPS, PLLVDD = 0 Rev. C | Page 29 of 40 AMPLITUDE (dBm) 02253-054 02253-053 AMPLITUDE (dBm) 02253-055 AD9772A zero-stuffing operation is enabled (that is, when MOD1 is high). BASEBAND SINGLE-CARRIER APPLICATIONS Applications requiring higher IFs (that is, 140 MHz) using The AD9772A is also well suited for wideband single-carrier higher data rates should disable the zero-stuffing operation. In applications, such as WCDMA and multilevel quadrature addition, to minimize the effects of the PLL clock multipliers amplitude modulation (QAM), whose modulation scheme phase noise as shown in Figure 31, an external low jitter/phase requires wide dynamic range from the reconstruction DAC to noise clock source equal to 4 × fDATA is recommended. achieve the out-of-band spectral mask as well as the in-band CNR performance. Many of these applications strategically Figure 57 shows the actual output spectrum of the AD9772A reconstructing a 16-QAM test vector with a symbol rate of place the carrier frequency at one quarter of the DAC’s input 5 MSPS. The particular test vector was centered at f /4 with data rate (that is, fDATA/4) to simplify the digital modulator DATA f = 100 MSPS and f = 400 MHz. For many applications, design. Because this constitutes the first fixed IF frequency, the DATA DAC the pair of images appearing around f will be more attractive frequency tuning is accomplished at a later IF stage. To enhance DATA the modulation accuracy and reduce the shape factor of the because this pair has the flattest pass band and highest signal second IF SAW filter, many applications specify that the pass power. Higher frequency images can also be used, but such band of the IF SAW filter be greater than the channel images will have reduced pass-band flatness, dynamic range, bandwidth; however, the trade-off is that this requires that the and signal power, thus reducing the CNR and ACP performance. Figure 58 shows a dual-tone SFDR amplitude sweep at the various TxDAC meet the spectral mask requirements of the application IF images with f = 100 MSPS, f = 400 MHz, and the two within the extended pass band of the second IF, which may DATA DAC tones centered around f /4. Note that because an IF filter is include two or more adjacent channels. DATA assumed to precede the AD9772A, the SFDR was measured Figure 56 shows a spectral plot of the AD9772A reconstructing a over a 25 MHz window around the images occurring at 75 MHz, test vector similar to those encountered in WCDMA applications. 125 MHz, 275 MHz, and 325 MHz. However, WCDMA applications prescribe a root raised cosine –20 filter with an alpha = 0.22, which limits the theoretical ACPR of the TxDAC to about 70 dB, whereas the test vector represents –30 white noise that has been band-limited by a brick wall band- –40 pass filter with a pass band for which the maximum ACPR performance is theoretically 83 dB and the peak-to-rms ratio –50 is 12.4 dB. As Figure 56 reveals, the AD9772A is capable of –60 approximately 78 dB ACPR performance when one accounts for the additive noise/distortion contributed by the Rohde & Schwarz –70 FSEA30 spectrum analyzer. –80 –30 –90 –40 –50 –100 0 100 200 300 400 –60 FREQUENCY (MHz) –70 Figure 57. Spectral Plot of 16-QAM Signal in Direct IF Mode at fDATA = 100 MSPS –80 90 –90 75MHz 85 –100 125MHz –110 80 C0 C0 275MHz –120 C11 C11 Cu1 Cu1 75 –130 CENTER 16.25MHz 600kHz SPAN 6MHz 325MHz 70 Figure 56. AD9772A Achieves 78 dB ACPR Performance Reconstructing a 65 WCDMA-Like Test Vector with fDATA = 65.536 MSPS and PLLVDD = 0 60 DIRECT IF As discussed in the Digital Modes of Operation section, the 55 AD9772A can be configured to transform digital data representing 50 baseband signals into IF signals appearing at odd multiples of –14 –12 –10 –8 –6 –4 –2 0 A (dBFS) OUT the input data rate (that is, N × fDATA, where N = 1, 3, and so on). Figure 58. Dual-Tone Windowed SFDR vs. AOUT @ fDATA = 100 MSPS This is accomplished by configuring the MOD1 and MOD0 digital inputs high. Note that the maximum DAC update rate of 400 MSPS limits the data input rate in this mode to 100 MSPS when the Rev. C | Page 30 of 40 AMPLITUDE (dBm) 02253-056 SFDR (IN 25MHz WINDOW) (dBFS) AMPLITUDE (dBm) 02253-057 02253-058 AD9772A –10 Regardless of which image is selected for a given application, the adjacent images must be sufficiently filtered. In most cases, a SAW –20 filter providing differential inputs represents the optimum device –30 for this purpose. For single-ended SAW filters, a balanced-to- –40 unbalanced RF transformer is recommended. The high output –50 impedance of the AD9772A provides a certain amount of flexibility in selecting the optimum resistive load, RLOAD, as well –60 as any matching network. –70 For many applications, the data update rate for the DAC (that is, –80 f ) must be a fixed integer multiple of a system reference DATA clock (for example, GSM − 13 MHz). Furthermore, these –90 applications prefer to use standard IF frequencies, which offer a –110 66 68 70 72 74 large selection of SAW filter choices with various pass bands FREQUENCY (MHz) (for example, 70 MHz). In addition, these applications may Figure 59. Spectral Plot of Four Carriers at 60 MHz IF with f = 52 MSPS, DATA benefit from the AD9772A’s direct IF mode capabilities when used PLLVDD = 0 in conjunction with a digital upconverter, such as the AD6622. Because the AD6622 can digitally synthesize and tune up to four modulated carriers, it is possible to judiciously tune these carriers in a region falling within the pass band an IF filter while the AD9772A is reconstructing a waveform. Figure 59 shows an example in which four carriers are tuned around 18 MHz with a digital upconverter operating at 52 MSPS such that when reconstructed by the AD9772A in the IF mode, these carriers fall around a 70 MHz IF. Rev. C | Page 31 of 40 AMPLITUDE (dBm) 02253-059 AD9772A AD9772A EVALUATION BOARD The AD9772A-EB is an evaluation board for the AD9772A The AD9772A PLL clock multiplier can be disabled by config- TxDAC. Careful attention to the layout and circuit design, uring Jumper JP5 in the L position. In this case, the user must along with the prototyping area, allows the user to easily and supply a clock input at twice (2×) the data rate via J3 (CLOCK). effectively evaluate the AD9772A in different modes of operation. The 1× clock is available on the SMA connector J1 (PLLLOCK), and should be used to trigger a pattern generator directly or via Referring to Figure 60 and Figure 61, the performance of a programmable pulse generator. Note that PLLLOCK is capable AD9772A can be evaluated differentially or in a single-ended of providing a 0 V to 0.85 V output into a 50 Ω load. To enable fashion using a transformer, differential amplifier, or directly the PLL clock multiplier, JP5 must be configured for the coupled output. To evaluate the output differentially using the H position. In this case, the clock can be supplied via the ribbon transformer, remove Jumper JP12 and Jumper JP13 and cable (that is, JP8 installed) or J3 (CLOCK). The divide-by-N monitor the output at J6 (IOUT). To evaluate the output ratio can be set by configuring JP6 (DIV0) and JP7 (DIV1). differentially, remove the transformer (T2) and install jumpers JP12 and JP13. The output of the amplifier can be evaluated at The AD9772A can be configured for baseband or direct IF J13 (AMPOUT). To evaluate the AD9772A in a single-ended mode operation by configuring Jumper JP11 (MOD0) and fashion with a directly coupled output, remove the transformer Jumper JP10 (MOD1). For baseband operation, JP10 and JP11 and Jumper JP12 and Jumper JP13, and install Resistor R16 or should be configured in the L position. For direct IF operation, Resistor R17 with 0 Ω. JP10 and JP11 should be configured in the H position. For direct IF operation without zero-stuffing, JP11 should be configured in The digital data to the AD9772A comes across a ribbon cable the H position while JP10 should be configured in the low position. that interfaces to a 40-pin IDC connector. Proper termination or voltage scaling can be accomplished by installing the RN2 The AD9772A voltage reference can be enabled or disabled via and/or RN3 SIP resistor networks. The 22 Ω DIP resistor JP4. To enable the reference, configure JP4 in the internal position. network, RN1, must be installed and helps reduce the digital A voltage of approximately 1.2 V will appear at the TP6 (REFIO) data edge rates. A single-ended clock input can be supplied via test point. To disable the internal reference, configure JP4 in the the ribbon cable by installing JP8, or, more preferably, via the external position and drive TP6 with an external voltage reference. SMA connector, J3 (CLOCK). If the clock is supplied by J3, the Lastly, the AD9772A can be placed in the sleep mode by driving AD9772A can be configured for a differential clock interface by the TP11 test point with a logic level high input signal. installing Jumper JP1 and configuring JP2, JP3, and JP9 in the DF position. To configure the AD9772A clock input for a single-ended clock interface, remove JP1 and configure JP2, JP3, and JP9 in the SE position. Rev. C | Page 32 of 40 AD9772A SCHEMATICS RN2 RN3 VALUE VALUE RN1 1 1 VALUE IN13 1 16 MSB DB13 2 MSB 2 2 P1 P1 1 IN13 IN12 2 15 DB12 3 3 4 P1 P1 3 IN12 IN11 3 14 DB11 4 4 6 P1 P1 5 IN11 IN10 4 13 DB10 5 5 8 P1 P1 7 IN10 IN9 5 12 DB9 6 6 10 P1 P1 9 IN9 IN8 6 11 DB8 7 7 12 P1 P1 11 IN8 IN7 7 10 DB7 8 8 14 P1 P1 13 IN7 IN6 8 9 DB6 9 9 16 P1 P1 15 IN6 10 10 RN5 RN6 VALUE VALUE RN4 1 1 VALUE IN5 1 16 DB5 2 2 18 P1 P1 17 IN5 IN4 2 15 DB4 3 3 20 P1 P1 19 IN4 IN3 3 14 DB3 4 4 22 P1 P1 21 IN3 IN2 4 13 DB2 5 5 24 P1 P1 23 IN2 IN1 5 12 DB1 6 6 26 P1 P1 25 IN1 IN0 6 11 LSB DB0 7 7 28 P1 P1 27 LSB IN0 7 10 CLOCK 8 8 30 P1 P1 29 INCLOCK 8 RESET 9 9 9 32 P1 P1 31 INRESET INCLOCK 10 10 34 P1 P1 33 INRESET 36 P1 P1 35 38 P1 P1 37 40 P1 P1 39 R15 500Ω RED +V S TP20 JP12 C18 R4 AMP-A 500Ω 7 0.1µF 2 AD8055 AMPOUT IA –IN +V 6 1 C16 JP13 U2 OUT J13 R12 100pF AMP-B 500Ω 2 3 –V +IN IB R13 R11 R14 4 BLK 50Ω 50Ω 500Ω –V S TP19 C17 0.1µF RED FBEAD L1 2 TP22 1 DVDD_IN 1 J7 DVDD C13 10µF TP23 DGND 10V 1 J8 BLK RED L2 FBEAD 1 2 TP24 AVDD_IN 1 J9 AVDD C14 10µF TP25 10V 1 AGND J10 BLK RED FBEAD L3 2 TP26 1 CLKVDD_IN 1 J11 CLKVDD C15 10µF TP27 CLKGND 10V 1 J12 c BLK Figure 60. Drafting Schematic of Evaluation Board Rev. C | Page 33 of 40 02253-060 AD9772A RED BLK WHT WHT TP16 TP17 TP5 TP6 AVDD C5 0.1µF 3 EXT REF B R10 C6 REFLO JP4 C4 2 1µF 1.91kΩ AVDD A 0.1µF INT REF 1 DVDD RED TP14 R6 NOTE: 50Ω SHIELD AROUND R5, C1 C7 C8 48 47 46 45 44 43 42 41 40 39 38 37 TP11 CONNECTED TO PLLVDD 0.1µF 0.1µF SLEEP WHT C1 1 36 R5 TP15 PIN 1 VAL VAL 2 35 IDENTIFIER LPF BLK 3 34 (MSB) DB13 PLLVDD 4 33 DB12 5 32 DB11 CLKVDD U1 C9 C10 6 31 DB10 1µF 0.1µF 7 30 CLK– c DB9 AD9772A 8 29 CLK+ DB8 9 28 DIV0 DB7 10 27 DIV1 CLKVDD DB6 RESET 11 26 DB5 12 25 PLLLOCK DB4 3 B 13 14 15 16 17 18 19 20 21 22 23 24 TP10 JP5 c 2 WHT A 1 J1 3 1 2 B TP7 RED C11 TP3 c c JP6 0.1µF 2 WHT A TP28 3 1 WHT B TP4 JP7 C12 2 WHT A 1µF MOD0 1 DVDD c TP1 WHT 3 3 WHT TP12 CLOCK B B H H J3 JP11 JP10 2 2 L L MOD1 DVDD 1 1 1 3 2 TP2 c B DGND WHT SE JP1 JP2 2 NOTE: A DF DF LOCATE ALL DECOUPLING CAPACITORS (C5 TO C12) AS CLOSE AS POSSIBLE TO DUT, JP8 1 CLKVDD PREFERABLY UNDER DUT ON THE BOTTOM SIGNAL LAYER. EDGE T1 R2 1 CLOCK 1kΩ S R16 VAL P 6 3 2 C3 R8 SE B R3 C19 T2 JP3 10pF 50Ω 1kΩ 0.1µF 4 2 IA A 3 DF 3 S c J6 1 c 1 P IOUT 4 R9 2 2 OPT 3 6 R1 50Ω DF B 1 IB C2 R7 JP9 2 R17 A 10pF 50Ω SE VAL 1 c Figure 61. Drafting Schematic of Evaluation Board (Continued) Rev. C | Page 34 of 40 DB3 DB2 DB1 (LSB) DB0 I OUTA OUTB FSADJ REFIO REFLO 02253-061 A A AD9772A EVALUATION BOARD LAYOUT Figure 62. Silkscreen Layer—Top Figure 63. Component-Side PCB Layout (Layer 1) Rev. C | Page 35 of 40 02253-063 02253-062 AD9772A Figure 64. Ground Plane PCB Layout (Layer 2) Figure 65. Power Plane PCB Layout (Layer 3) Rev. C | Page 36 of 40 02253-065 02253-064 AD9772A Figure 66. Solder-Side PCB Layout (Layer 4) Figure 67. Silkscreen Layer—Bottom Rev. C | Page 37 of 40 02253-066 02253-067 AD9772A OUTLINE DIMENSIONS 9.20 9.00 SQ 0.75 1.60 8.80 0.60 MAX 0.45 48 37 1 36 PIN 1 7.20 TOP VIEW 7.00 SQ 1.45 (PINS DOWN) 0.20 6.80 1.40 0.09 1.35 7° 3.5° 12 25 0.15 0° 13 24 SEATING 0.05 0.08 0.27 PLANE VIEW A 0.50 COPLANARITY 0.22 BSC LEAD PITCH 0.17 VIEW A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BBC Figure 68. 48-Lead Low Profile Quad Flat Package [LQFP] (ST-48) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option AD9772AAST −40°C to +85°C 48-Lead LQFP ST-48 1 AD9772AASTZ −40°C to +85°C 48-Lead LQFP ST-48 AD9772AASTRL −40°C to +85°C 48-Lead LQFP ST-48 1 AD9772AASTZRL −40°C to +85°C 48-Lead LQFP ST-48 AD9772A-EB Evaluation Board 1 Z = RoHS Compliant Part. Rev. C | Page 38 of 40 051706-A AD9772A NOTES Rev. C | Page 39 of 40 AD9772A NOTES ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02253-0-2/08(C) Rev. C | Page 40 of 40