ANALOG DEVICES AD9765

10-/12-/14-Bit, 125 MSPS Dual TxDAC+ Digital-to-Analog Converters Data Sheet AD9763/AD9765/AD9767 FEATURES FUNCTIONAL BLOCK DIAGRAM DVDD1/ DCOM1/ 10-/12-/14-bit dual transmit digital-to-analog converters (DACs) DVDD2 DCOM2 AVDD ACOM CLK1 125 MSPS update rate I OUTA1 1 1 Excellent SFDR to Nyquist @ 5 MHz output: 75 dBc PORT1 LATCH DAC I OUTB1 Excellent gain and offset matching: 0.1% REFIO Fully independent or single-resistor gain control FSADJ1 REFERENCE WRT1/IQWRT FSADJ2 AD9763/ Dual-port or interleaved data DIGITAL GAINCTRL INTERFACE AD9765/ WRT2/IQSEL On-chip 1.2 V reference AD9767 BIAS SLEEP GENERATOR 5 V or 3.3 V operation Power dissipation: 380 mW @ 5 V I 2 2 OUTA2 PORT2 LATCH DAC Power-down mode: 50 mW @ 5 V I OUTB2 48-lead LQFP MODE CLK2/IQ RESET Figure 1. APPLICATIONS Communications The DACs utilize a segmented current source architecture Base stations combined with a proprietary switching technique to reduce Digital synthesis glitch energy and maximize dynamic accuracy. Each DAC provides Quadrature modulation differential current output, thus supporting single-ended or dif- 3D ultrasound ferential applications. Both DACs of the AD9763, AD9765, or AD9767 can be simultaneously updated and can provide a GENERAL DESCRIPTION nominal full-scale current of 20 mA. The full-scale currents The AD9763/AD9765/AD9767 are dual-port, high speed, between each DAC are matched to within 0.1%. 2-channel, 10-/12-/14-bit CMOS DACs. Each part integrates The AD9763/AD9765/AD9767 are manufactured on an two high quality TxDAC+® cores, a voltage reference, and digital advanced, low cost CMOS process. They operate from a single interface circuitry into a small 48-lead LQFP. The AD9763/ supply of 3.3 V to 5 V and consume 380 mW of power. AD9765/AD9767 offer exceptional ac and dc performance while supporting update rates of up to 125 MSPS. PRODUCT HIGHLIGHTS The AD9763/AD9765/AD9767 have been optimized for 1. The AD9763/AD9765/AD9767 are members of a pin- processing I and Q data in communications applications. The compatible family of dual TxDACs providing 8-, 10-, 12-, digital interface consists of two double-buffered latches as well and 14-bit resolution. as control logic. Separate write inputs allow data to be written to 2. Dual 10-/12-/14-Bit, 125 MSPS DACs. A pair of high the two DAC ports independent of one another. Separate clocks performance DACs for each part is optimized for low control the update rate of the DACs. distortion performance and provides flexible transmission of I and Q information. A mode control pin allows the AD9763/AD9765/AD9767 to 3. Matching. Gain matching is typically 0.1% of full scale, and interface to two separate data ports, or to a single interleaved offset error is better than 0.02%. high speed data port. In interleaving mode, the input data 4. Low Power. Complete CMOS dual DAC function operates on stream is demuxed into its original I and Q data and then 380 mW from a 3.3 V to 5 V single supply. The DAC full-scale latched. The I and Q data is then converted by the two DACs current can be reduced for lower power operation, and a sleep and updated at half the input data rate. mode is provided for low power idle periods. The GAINCTRL pin allows two modes for setting the full-scale 5. On-Chip Voltage Reference. The AD9763/AD9765/AD9767 current (I ) of the two DACs. I for each DAC can be set OUTFS OUTFS each include a 1.20 V temperature-compensated band gap independently using two external resistors, or I for both OUTFS voltage reference. DACs can be set by using a single external resistor. See the 6. Dual 10-/12-/14-Bit Inputs. The AD9763/AD9765/AD9767 Gain Control Mode section for important date code each feature a flexible dual-port interface, allowing dual or information on this feature. interleaved input data. Rev. G Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©1999-2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 00617-001 AD9763/AD9765/AD9767 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1  Digital Inputs .............................................................................. 24  Applications....................................................................................... 1  DAC Timing................................................................................ 24  General Description ......................................................................... 1  Sleep Mode Operation............................................................... 26  Functional Block Diagram .............................................................. 1  Power Dissipation....................................................................... 26  Product Highlights ........................................................................... 1  Applying the AD9763/AD9765/AD9767.................................... 28  Revision History ............................................................................... 2  Output Configurations .............................................................. 28  Specifications..................................................................................... 5  Differential Coupling Using a Transformer............................ 28  DC Specifications ......................................................................... 5  Differential Coupling Using an Op Amp................................ 28  Dynamic Specifications ............................................................... 6  Single-Ended, Unbuffered Voltage Output............................. 29  Digital Specifications ................................................................... 7  Single-Ended, Buffered Voltage Output Configuration........ 29  Absolute Maximum Ratings............................................................ 8  Power and Grounding Considerations.................................... 29  Thermal Resistance ...................................................................... 8  Applications Information .............................................................. 31  ESD Caution.................................................................................. 8  VDSL Example Applications Using the AD9765 and AD9767 ................................................................ 31  Pin Configuration and Function Descriptions............................. 9  Quadrature Amplitude Modulation (QAM) Example Using Typical Performance Characteristics ........................................... 11  the AD9763 ................................................................................. 32  AD9763........................................................................................ 11  CDMA ......................................................................................... 33  AD9765........................................................................................ 14  Evaluation Board ............................................................................ 34  AD9767........................................................................................ 17  General Description................................................................... 34  Terminology .................................................................................... 20  Schematics................................................................................... 34  Theory of Operation ...................................................................... 21  Evaluation Board Layout........................................................... 40  Functional Description.............................................................. 21  Outline Dimensions....................................................................... 42  Reference Operation .................................................................. 22  Ordering Guide .......................................................................... 42  Gain Control Mode .................................................................... 22  Setting the Full-Scale Current................................................... 22  DAC Transfer Function ............................................................. 23  Analog Outputs........................................................................... 23  REVISION HISTORY Revision History: AD9763/AD9765/AD9767 Revision History: AD9763 8/11—Rev. F to Rev. G 1/08—Rev. D to Rev. E Changes to Gain Control Mode Section and Setting the Full- Combined with AD9765 and AD9767 Data Sheets.......Universal Scale Current Section..................................................................... 22 Changes to Figure 1...........................................................................1 Changes to DAC Transfer Function Section............................... 23 Changes to Applications Section.....................................................1 Changes to Power Supply Rejection Section............................... 29 Changes to Timing Diagram Section .............................................7 Added Figure 4 and Figure 5............................................................9 6/09—Rev. E to Rev. F Changes to Table 6.......................................................................... 10 Replaced Figure 86 to Figure 90 with Figure 86 to Figure 91, Change to Typical Performance Characteristics Section Deleted Original Figure 91 to Figure 94...................................... 34 Conditions Statement .................................................................... 11 Added Figure 23 to Figure 56 ....................................................... 14 1/08—Revision E: Initial Combined Version Added Note to Figure 58 ............................................................... 20 Changes to Functional Description Section ............................... 22 Changes to Figure 59 and Figure 60............................................. 22 Changes to Gain Control Mode Section ..................................... 22 Rev. G | Page 2 of 44 Data Sheet AD9763/AD9765/AD9767 Replaced Reference Control Amplifier Section with Setting Changes to Interleaved Mode Timing Section............................25 the Full-Scale Current Section.......................................................22 Added Figure 64 ..............................................................................25 Changes to DAC Transfer Section ................................................23 Changes to Power and Grounding Considerations Section............30 Added Figure 80 and Figure 82 .....................................................31 Change to Analog Outputs Section ..............................................24 Changes to Dual-Port Mode Timing............................................24 Changes to Quadrature Amplitude Modulation (QAM) Changes to Interleaved Mode Timing Section............................25 Example Using the AD9763 Section.............................................32 Added Figure 64 ..............................................................................25 Changes to Figure 83 and Figure 84 .............................................32 Change to Differential Coupling Using a Transformer Section .....28 Changes to CDMA Section............................................................33 Changes to Power and Grounding Considerations Section............30 Changes to Figure 85 Caption .......................................................33 Added VDSL Example Applications Using the AD9765 and Changes to Figure 86 ......................................................................34 AD9767 Section...............................................................................31 Changes to Figure 88 ......................................................................36 Added Figure 79 to Figure 82 ........................................................31 Changes to Ordering Guide...........................................................40 Changes to Figure 84 ......................................................................32 Changes to CDMA Section............................................................33 9/06—Rev. B to Rev. C Changes to Figure 85 Caption .......................................................33 Updated Format ................................................................. Universal Changes to Figure 86 ......................................................................34 Changes to Figure 2 ..........................................................................5 Changes to Figure 88 ......................................................................36 Changes to Figure 3 ..........................................................................7 Changes to Ordering Guide...........................................................40 Changes to Functional Description Section................................12 Changes to Figure 25 and Figure 26 .............................................15 9/06—Rev. C to Rev. D Changes to Figure 28 and Figure 29 .............................................16 Updated Format.................................................................. Universal Changes to Power Dissipation Section.........................................17 Renumbered Figures.......................................................... Universal Changes to Power and Grounding Considerations Section......19 Changes to Specifications Section...................................................3 Changes to Figure 39 ......................................................................19 Changes to Applications Section...................................................21 Changes to Figure 45 ......................................................................22 Updated Outline Dimensions........................................................32 Changes to Evaluation Board Section ..........................................24 Changes to Ordering Guide...........................................................32 Changes to Figure 47 ......................................................................24 Updated Outline Dimensions........................................................30 10/01—Rev. B to Rev. C Changes to Ordering Guide...........................................................30 Changes to Figure 29 ......................................................................21 2/00—Rev. A to Rev. B 2/00—Rev. A to Rev. B 12/99—Rev. 0 to Rev. A 12/99—Rev. 0 to Rev. A 8/99—Revision 0: Initial Version Revision History: AD9765 Revision History: AD9767 1/08—Rev. C to Rev. E 1/08—Rev. C to Rev. E Combined with AD9763 and AD9767 Data Sheets ...... Universal Combined with AD9763 and AD9765 Data Sheets ...... Universal Changes to Figure 1...........................................................................1 Changes to Figure 1 ..........................................................................1 Changes to Applications Section.....................................................1 Changes to Features Section ............................................................1 Changes to Timing Diagram Section .............................................7 Changes to Applications Section.....................................................1 Change to Absolute Maximum Ratings .........................................8 Changes to Timing Diagram Section .............................................7 Added Figure 3 and Figure 5 ...........................................................9 Change to Absolute Maximum Ratings .........................................8 Changes to Table 6 ..........................................................................10 Added Figure 3 and Figure 4 ...........................................................9 Added Figure 6 to Figure 22 ..........................................................11 Changes to Table 6 ..........................................................................10 Added Figure 40 to Figure 56 ........................................................17 Added Figure 6 to Figure 39 ..........................................................11 Added Note to Figure 58 ................................................................20 Added Note to Figure 58 ................................................................20 Changes to Functional Description Section ................................22 Changes to Functional Description Section................................22 Changes to Reference Operation Section ....................................22 Changes to Reference Operation Section ....................................22 Changes to Figure 59 and Figure 60 .............................................22 Changes to Figure 59 and Figure 60 .............................................22 Changes to Gain Control Mode Section ......................................22 Changes to Gain Control Mode Section ......................................22 Replaced Reference Control Amplifier Section with Setting Replaced Reference Control Amplifier Section with Setting the Full-Scale Current Section.......................................................22 the Full-Scale Current Section ......................................................22 Changes to DAC Transfer Section ................................................23 Changes to DAC Transfer Section ................................................23 Rev. G | Page 3 of 44 AD9763/AD9765/AD9767 Data Sheet Changes to Dual-Port Mode Timing ........................................... 24 Changes to Interleaved Mode Timing Section ........................... 25 10/06—Rev. B to Rev. C Added Figure 64.............................................................................. 25 Updated Format..................................................................Universal Changes to Figure 2...........................................................................5 Change to Differential Coupling Using a Transformer Section......28 Changes to Power and Grounding Considerations Section............30 Changes to Figure 3...........................................................................7 Added Figure 79 and Figure 81..................................................... 31 Changes to Functional Description Section ............................... 12 Added to Quadrature Amplitude Modulation (QAM) Changes to Figure 25 and Figure 26............................................. 15 Example Using the AD9763 Section ............................................ 32 Changes to Figure 28 and Figure 29............................................. 16 Added Figure 83 and Figure 84..................................................... 32 Changes to Power Dissipation Section ........................................ 18 Changes to CDMA Section ........................................................... 33 Changes to Figure 39...................................................................... 19 Changes to Figure 85 Caption....................................................... 33 Changes to Power and Grounding Considerations Section ..... 19 Changes to Figure 86...................................................................... 34 Changes to Figure 45...................................................................... 22 Changes to Figure 88...................................................................... 36 Changes to Figure 47...................................................................... 24 Changes to Ordering Guide .......................................................... 40 Updated Outline Dimensions....................................................... 28 Changes to Ordering Guide .......................................................... 28 2/00—Rev. A to Rev. B 12/99—Rev. 0 to Rev. A 8/99—Revision 0: Initial Version Rev. G | Page 4 of 44 Data Sheet AD9763/AD9765/AD9767 SPECIFICATIONS DC SPECIFICATIONS T to T , AVDD = 3.3 V or 5 V, DVDD1 = DVDD2 = 3.3 V or 5 V, I = 20 mA, unless otherwise noted. MIN MAX OUTFS Table 1. AD9763 AD9765 AD9767 Parameter Min Typ Max Min Typ Max Min Typ Max Unit RESOLUTION 10 12 14 Bits 1 DC ACCURACY Integral Linearity Error (INL) −1 ±0.1 +1 LSB TA = 25°C −1.5 ±0.4 +1.5 −3.5 ±1.5 +3.5 LSB TMIN to TMAX −2.0 +2.0 −4.0 +4.0 LSB Differential Nonlinearity (DNL) LSB T = 25°C −0.5 ±0.07 +0.5 −0.75 ±0.3 +0.75 −2.5 ±1.0 +2.5 LSB A T to T −1.0 +1.0 −3.0 +3.0 LSB MIN MAX ANALOG OUTPUT Offset Error −0.02 +0.02 −0.02 +0.02 −0.02 +0.02 % of FSR Gain Error Without Internal Reference −2 ±0.25 +2 −2 ±0.25 +2 −2 ±0.25 +2 % of FSR Gain Error with Internal Reference −5 ±1 +5 −5 ±1 +5 −5 ±1 +5 % of FSR Gain Match −1.6 ±0.1 +1.6 −1.6 ±0.1 +1.6 −1.6 ±0.1 +1.6 % of FSR −0.14 +0.14 −0.14 +0.14 −0.14 +0.14 dB 2 Full-Scale Output Current 2.0 20.0 2.0 20.0 2.0 20.0 mA Output Compliance Range −1.0 +1.25 −1.0 +1.25 −1.0 +1.25 V Output Resistance 100 100 100 kΩ Output Capacitance 5 5 5 pF REFERENCE OUTPUT Reference Voltage 1.14 1.20 1.26 1.14 1.20 1.26 1.14 1.20 1.26 V 3 Reference Output Current 100 100 100 nA REFERENCE INPUT Input Compliance Range 0.1 1.25 0.1 1.25 0.1 1.25 V Reference Input Resistance 1 1 1 MΩ Small-Signal Bandwidth 0.5 0.5 0.5 MHz TEMPERATURE COEFFICIENTS Offset Drift 0 0 0 ppm of FSR/°C Gain Drift Without Internal Reference ±50 ±50 ±50 ppm of FSR/°C Gain Drift with Internal Reference ±100 ±100 ±100 ppm of FSR/°C Reference Voltage Drift ±50 ±50 ±50 ppm/°C POWER SUPPLY Supply Voltages AVDD 3 5 5.5 3 5 5.5 3 5 5.5 V DVDD1, DVDD2 2.7 5 5.5 2.7 5 5.5 2.7 5 5.5 V Analog Supply Current (IAVDD) 71 75 71 75 71 75 mA 4 Digital Supply Current (IDVDD) 5 7 5 7 5 7 mA 5 Digital Supply Current (IDVDD) 15 15 15 mA Supply Current Sleep Mode (I ) 8 12.0 8 12.0 8 12.0 mA AVDD 4 380 410 380 410 380 410 mW Power Dissipation (5 V, IOUTFS = 20 mA) 5 420 450 420 450 420 450 mW Power Dissipation (5 V, I = 20 mA) OUTFS 6 Power Dissipation (5 V, I = 20 mA) 450 450 450 mW OUTFS 7 Power Supply Rejection Ratio —AVDD –0.4 +0.4 –0.4 +0.4 –0.4 +0.4 % of FSR/V 7 Power Supply Rejection Ratio —DVDD –0.025 +0.025 –0.025 +0.025 –0.025 +0.025 % of FSR/V OPERATING RANGE –40 +85 –40 +85 –40 +85 °C 1 Measured at IOUTA, driving a virtual ground. 2 Nominal full-scale current, I , is 32 times the I current. OUTFS REF 3 An external buffer amplifier with input bias current <100 nA should be used to drive any external load. 4 Measured at f = 25 MSPS and f = 1.0 MHz. CLK OUT 5 Measured at fCLK = 100 MSPS and fOUT = 1 MHz. 6 Measured as unbuffered voltage output with I = 20 mA and R = 50 Ω at I and I , f = 100 MSPS, and f = 40 MHz. OUTFS LOAD OUTA OUTB CLK OUT 7 ±10% power supply variation. Rev. G | Page 5 of 44 AD9763/AD9765/AD9767 Data Sheet DYNAMIC SPECIFICATIONS TMIN to TMAX, AVDD = 3.3 V or 5 V, DVDD1 = DVDD2 = 3.3 V or 5 V, IOUTFS = 20 mA, differential transformer-coupled output, 50 Ω doubly terminated, unless otherwise noted. Table 2. AD9763 AD9765 AD9767 Parameter Min Typ Max Min Typ Max Min Typ Max Unit DYNAMIC PERFORMANCE Maximum Output Update Rate (f ) 125 125 125 MSPS CLK 1 Output Settling Time (tST) to 0.1% 35 35 35 ns Output Propagation Delay (tPD) 1 1 1 ns Glitch Impulse 5 5 5 pV-s 1 Output Rise Time (10% to 90%) 2.5 2.5 2.5 ns 1 Output Fall Time (90% to 10%) 2.5 2.5 2.5 ns Output Noise (I = 20 mA) 50 50 50 pA/√Hz OUTFS Output Noise (IOUTFS = 2 mA) 30 30 30 pA/√Hz AC LINEARITY Spurious-Free Dynamic Range to Nyquist fCLK = 100 MSPS, fOUT = 1.00 MHz 0 dBFS Output 69 78 70 81 71 82 dBc –6 dBFS Output 74 77 77 dBc –12 dBFS Output 69 72 73 dBc –18 dBFS Output 61 70 70 dBc fCLK = 65 MSPS, fOUT = 1.00 MHz 79 81 82 dBc fCLK = 65 MSPS, fOUT = 2.51 MHz 78 79 80 dBc fCLK = 65 MSPS, fOUT = 5.02 MHz 75 78 79 dBc f = 65 MSPS, f = 14.02 MHz 66 68 70 dBc CLK OUT f = 65 MSPS, f = 25 MHz 55 55 55 dBc CLK OUT f = 125 MSPS, f = 25 MHz 67 67 67 dBc CLK OUT fCLK = 125 MSPS, fOUT = 40 MHz 60 60 70 dBc Spurious-Free Dynamic Range Within a Window fCLK = 100 MSPS, fOUT = 1.00 MHz; 2 MHz Span 78 85 80 90 82 91 dBc f = 50 MSPS, f = 5.02 MHz; 10 MHz Span 80 88 88 dBc CLK OUT f = 65 MSPS, f = 5.03 MHz; 10 MHz Span 82 88 88 dBc CLK OUT fCLK = 125 MSPS, fOUT = 5.04 MHz; 10 MHz Span 82 88 88 dBc Total Harmonic Distortion fCLK = 100 MSPS, fOUT = 1.00 MHz −77 −69 −80 –70 −81 −71 dBc f = 50 MSPS, f = 2.00 MHz −77 −78 −79 dBc CLK OUT f = 125 MSPS, f = 4.00 MHz −74 −75 −83 dBc CLK OUT f = 125 MSPS, f = 10.00 MHz −72 −75 −80 dBc CLK OUT Multitone Power Ratio (Eight Tones at 110 kHz Spacing) fCLK = 65 MSPS, fOUT = 2.00 MHz to 2.99 MHz 0 dBFS Output 76 80 80 dBc −6 dBFS Output 74 79 79 dBc −12 dBFS Output 71 77 78 dBc −18 dBFS Output 67 75 76 dBc Channel Isolation fCLK = 125 MSPS, fOUT = 10 MHz 85 85 85 dBc f = 125 MSPS, f = 40 MHz 77 77 77 dBc CLK OUT 1 Measured single-ended into 50 Ω load. Rev. G | Page 6 of 44 Data Sheet AD9763/AD9765/AD9767 DIGITAL SPECIFICATIONS TMIN to TMAX, AVDD = 3.3 V or 5 V, DVDD1 = DVDD2 = 3.3 V or 5 V, IOUTFS = 20 mA, unless otherwise noted. Table 3. Parameter Min Typ Max Unit DIGITAL INPUTS Logic 1 Voltage @ DVDD1 = DVDD2 = 5 V 3.5 5 V Logic 1 Voltage @ DVDD1 = DVDD2 = 3.3 V 2.1 3 V Logic 0 Voltage @ DVDD1 = DVDD2 = 5 V 0 1.3 V Logic 0 Voltage @ DVDD1 = DVDD2 = 3.3 V 0 0.9 V Logic 1 Current −10 +10 μA Logic 0 Current −10 +10 μA Input Capacitance 5 pF Input Setup Time (tS) 2.0 ns Input Hold Time (t ) 1.5 ns H Latch Pulse Width (t , t ) 3.5 ns LPW CPW Timing Diagram See Table 3 and the DAC Timing section for more information about the timing specifications. t t S H DATA IN (WRT2) (WRT1/IQWRT) t LPW (CLK2) (CLK1/IQCLK) t CPW I OUTA OR I OUTB t PD Figure 2. Timing Diagram for Dual and Interleaved Modes Rev. G | Page 7 of 44 00617-002 AD9763/AD9765/AD9767 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 4. θ is specified for the worst-case conditions, that is, a device JA With soldered in a circuit board for surface-mount packages. Parameter Respect To Rating AVDD ACOM −0.3 V to +6.5 V Table 5. Thermal Resistance DVDD1, DVDD2 DCOM1/DCOM2 −0.3 V to +6.5 V Package Type θ Unit JA ACOM DCOM1/DCOM2 −0.3 V to +0.3 V 48-Lead LQFP 91 °C/W AVDD DVDD1/DVDD2 −6.5 V to +6.5 V MODE, DCOM1/DCOM2 −0.3 V to DVDD1/ CLK1/IQCLK, DVDD2 + 0.3 V ESD CAUTION CLK2/IQRESET, WRT1/IQWRT, WRT2/IQSEL Digital Inputs DCOM1/DCOM2 −0.3 V to DVDD1/ DVDD2 + 0.3 V I /I , ACOM −1.0 V to AVDD + 0.3 V OUTA1 OUTA2 IOUTB1/IOUTB2 REFIO, FSADJ1, ACOM −0.3 V to AVDD + 0.3 V FSADJ2 GAINCTRL, SLEEP ACOM −0.3 V to AVDD + 0.3 V Junction 150°C Temperature Storage −65°C to +150°C Temperature Range Lead Temperature 300°C (10 sec) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. G | Page 8 of 44 Data Sheet AD9763/AD9765/AD9767 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 48 47 46 45 44 43 42 41 40 39 38 37 48 47 46 45 44 43 42 41 40 39 38 37 1 36 DB9P1 (MSB) 1 36 NC DB13P1 (MSB) DB0P2 (LSB) PIN 1 PIN 1 2 35 DB8P1 2 35 NC DB12P1 DB1P2 3 34 DB7P1 3 34 NC DB11P1 DB2P2 4 33 4 33 DB10P1 DB3P2 DB6P1 NC 5 32 5 32 DB9P1 DB4P2 DB5P1 DB0P2 (LSB) AD9767 AD9763 6 31 6 31 DB8P1 DB5P2 DB4P1 DB1P2 TOP VIEW TOP VIEW (Not to Scale) 7 30 7 DB7P1 (Not to Scale) DB6P2 DB3P1 30 DB2P2 8 29 DB6P1 DB7P2 DB2P1 8 29 DB3P2 9 28 DB5P1 DB8P2 DB1P1 9 28 DB4P2 DB4P1 10 27 DB9P2 DB0P1 (LSB) 10 27 DB5P2 11 26 DB3P1 DB10P2 11 26 NC DB6P2 12 25 DB2P1 DB11P2 12 25 NC DB7P2 13 14 15 16 17 18 19 20 21 22 23 24 13 14 15 16 17 18 19 20 21 22 23 24 NC = NO CONNECT Figure 5. AD9767 Pin Configuration Figure 3. AD9763 Pin Configuration 48 47 46 45 44 43 42 41 40 39 38 37 1 36 DB11P1 (MSB) NC PIN 1 2 35 DB10P1 NC DB9P1 3 34 DB0P2 (LSB) 4 33 DB8P1 DB1P2 5 32 DB7P1 DB2P2 AD9765 6 31 DB6P1 DB3P2 TOP VIEW 7 (Not to Scale) 30 DB5P1 DB4P2 DB4P1 8 29 DB5P2 9 28 DB3P1 DB6P2 10 27 DB2P1 DB7P2 11 26 DB1P1 DB8P2 12 25 DB0P1 (LSB) DB9P2 13 14 15 16 17 18 19 20 21 22 23 24 NC = NO CONNECT Figure 4. AD9765 Pin Configuration Rev. G | Page 9 of 44 MODE NC NC MODE NC AVDD NC AVDD I DCOM1 DCOM1 I OUTA1 OUTA1 DVDD1 I DVDD1 I OUTB1 OUTB1 WRT1/IQWRT FSADJ1 WRT1/IQWRT FSADJ1 CLK1/IQCLK REFIO CLK1/IQCLK REFIO CLK2/IQRESET GAINCTRL CLK2/IQRESET GAINCTRL WRT2/IQSEL FSADJ2 WRT2/IQSEL FSADJ2 DCOM2 I DCOM2 I OUTB2 OUTB2 DVDD2 I DVDD2 I OUTA2 OUTA2 DB9P2 (MSB) ACOM DB11P2 (MSB) ACOM DB8P2 SLEEP DB10P2 SLEEP 00617-004 00617-003 DB1P1 MODE DB0P1 (LSB) AVDD DCOM1 I OUTA1 DVDD1 I OUTB1 WRT1/IQWRT FSADJ1 CLK1/IQCLK REFIO CLK2/IQRESET GAINCTRL WRT2/IQSEL FSADJ2 DCOM2 I OUTB2 DVDD2 I OUTA2 DB13P2 (MSB) ACOM DB12P2 SLEEP 00617-005 AD9763/AD9765/AD9767 Data Sheet Table 6. Pin Function Descriptions Pin No. AD9763 AD9765 AD9767 Mnemonic Description 1 to 10 1 to 12 1 to 14 DBxP1 Data Bit Pins (Port 1) 11 to 14, 13, 14, N/A NC No Connect 33 to 36 35, 36 15, 21 15, 21 15, 21 DCOM1, DCOM2 Digital Common 16, 22 16, 22 16, 22 DVDD1, DVDD2 Digital Supply Voltage 17 17 17 WRT1/IQWRT Input Write Signal for PORT 1 (IQWRT in Interleaving Mode) 18 18 18 CLK1/IQCLK Clock Input for DAC1 (IQCLK in Interleaving Mode) 19 19 19 CLK2/IQRESET Clock Input for DAC2 (IQRESET in Interleaving Mode) 20 20 20 WRT2/IQSEL Input Write Signal for PORT 2 (IQSEL in Interleaving Mode) 23 to 32 23 to 34 23 to 36 DBxP2 Data Bit Pins (Port 2) 37 37 37 SLEEP Power-Down Control Input 38 38 38 ACOM Analog Common 39, 40 39, 40 39, 40 IOUTA2, IOUTB2 Port 2 Differential DAC Current Outputs 41 41 41 FSADJ2 Full-Scale Current Output Adjust for DAC2 42 42 42 GAINCTRL Master/Slave Resistor Control Mode 43 43 43 REFIO Reference Input/Output 44 44 44 FSADJ1 Full-Scale Current Output Adjust for DAC1 45, 46 45, 46 45, 46 IOUTB1, IOUTA1 Port 1 Differential DAC Current Outputs 47 47 47 AVDD Analog Supply Voltage 48 48 48 MODE Mode Select (1 = dual port, 0 = interleaved) Rev. G | Page 10 of 44 Data Sheet AD9763/AD9765/AD9767 TYPICAL PERFORMANCE CHARACTERISTICS AD9763 AVDD = 3.3 V or 5 V, DVDD = 3.3 V, I = 20 mA, 50 Ω doubly terminated load, differential output, T = 25°C, SFDR up to Nyquist, OUTFS A unless otherwise noted. 90 80 0dBFS 75 80 –6dBFS f = 5MSPS CLK 70 –12dBFS f = 25MSPS CLK 70 65 60 f = 65MSPS CLK 60 55 f = 125MSPS CLK 50 50 1 10 100 0 5 10 15 20 25 30 35 f (MHz) f (MHz) OUT OUT Figure 6. SFDR vs. f @ 0 dBFS Figure 9. SFDR vs. fOUT @ 65 MSPS OUT 80 80 0dBFS 75 0dBFS –6dBFS 75 70 –6dBFS 65 –12dBFS 70 60 –12dBFS 55 65 50 0 0.5 1.0 1.5 2.0 2.5 0 10203040506070 f (MHz) OUT f (MHz) OUT Figure 7. SFDR vs. f @ 5 MSPS OUT Figure 10. SFDR vs. fOUT @ 125 MSPS 80 80 I = 20mA OUTFS 0dBFS 75 75 70 –6dBFS 65 70 I = 10mA OUTFS –12dBFS 60 65 I = 5mA OUTFS 55 60 50 02 468 10 12 0 5 10 15 20 25 30 35 f (MHz) f (MHz) OUT OUT Figure 8. SFDR vs. f @ 25 MSPS Figure 11. SFDR vs. fOUT and IOUTFS @ 65 MSPS and 0 dBFS OUT Rev. G | Page 11 of 44 SFDR (dBc) SFDR (dBc) SFDR (dBc) 00617-008 00617-007 00617-006 SFDR (dBc) SFDR (dBc) SFDR (dBc) 00617-011 00617-010 00617-009 AD9763/AD9765/AD9767 Data Sheet 70 85 910kHz/10MSPS 80 2.27MHz/25MSPS I = 20mA OUTFS 75 65 70 I = 10mA OUTFS 5.91MHz/65MSPS 65 60 11.37MHz/125MSPS 60 I = 5mA OUTFS 55 55 –20 –16 –12 –8 –4 0 20 40 60 80 100 120 140 A (dBFS) f (MSPS) OUT CLK Figure 12. Single-Tone SFDR vs. A @ f = f /11 Figure 15. SINAD vs. f and I @ f = 5 MHz and 0 dBFS OUT OUT CLK CLK OUTFS OUT 85 0.25 5MHz/25MSPS 0.20 80 0.15 1MHz/5MSPS 0.10 75 2MHz/10MSPS 0.05 70 0 –0.05 65 –0.10 13MHz/65MSPS –0.15 25MHz/125MSPS 60 –0.20 55 –0.25 –20 –16 –12 –8 –4 0 0 200 400 600 800 1000 A (dBFS) CODE OUT Figure 16. Typical INL Figure 13. Single-Tone SFDR vs. A @ f = f /5 OUT OUT CLK 0.30 80 3.38MHz/3.36MHz @ 25MSPS 0.25 0.965MHz/1.035MHz @ 7MSPS 75 0.20 6.75MHz/7.25MHz @ 65MSPS 0.15 70 0.10 65 16.9MHz/18.1MHz @ 125MSPS 0.05 0 60 –0.05 –0.10 55 0 200 400 600 800 1000 –20 –16 –12 –8 –4 0 CODE A (dBFS) OUT Figure 14. Dual-Tone SFDR vs. A @ f = f /7 Figure 17. Typical DNL OUT OUT CLK Rev. G | Page 12 of 44 SFDR (dBc) SFDR (dBc) SFDR (dBc) 00617-014 00617-013 00617-012 INL (LSB) DNL (LSB) SINAD (dBc) 00617-015 00617-017 00617-016 Data Sheet AD9763/AD9765/AD9767 85 0 f = 1MHz –10 OUT 80 –20 75 f = 10MHz OUT –30 70 –40 f = 25MHz OUT 65 –50 60 f = 40MHz OUT –60 55 –70 50 –80 f = 60MHz OUT 45 –90 –60 –40 –20 0 20 40 60 80 100 0 10203040 TEMPERATURE (°C) FREQUENCY (MHz) Figure 18. SFDR vs. Temperature @ fCLK = 125 MSPS, 0 dBFS Figure 21. Dual-Tone SFDR @ f = 125 MSPS CLK 0.05 1.0 0 –10 –20 0.03 GAIN ERROR 0.5 OFFSET ERROR –30 –40 0 0 –50 –60 –0.03 –0.5 –70 –80 –0.05 –1.0 –90 –40 –20 0 20 40 60 80 0 10203040 FREQUENCY (MHz) TEMPERATURE (°C) Figure 19. Gain and Offset Error vs. Temperature @ f = 125 MSPS Figure 22. Four-Tone SFDR @ fCLK = 125 MSPS CLK 10 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 0 10 203040 FREQUENCY (MHz) Figure 20. Single-Tone SFDR @ fCLK = 125 MSPS Rev. G | Page 13 of 44 OFFSET ERROR (%FS) SFDR (dBm) SFDR (dBc) 00617-020 00617-018 GAIN ERROR (%FS) 00617-019 SFDR (dBm) SFDR (dBm) 00617-022 00617-021 AD9763/AD9765/AD9767 Data Sheet AD9765 AVDD = 3.3 V or 5 V, DVDD = 3.3 V or 5 V, IOUTFS = 20 mA, 50 Ω doubly terminated load, differential output, TA = 25°C, SFDR up to Nyquist, unless otherwise noted. 90 85 f = 5MSPS CLK 80 f = 25MSPS CLK 0dBFS 80 75 –6dBFS 70 f = 125MSPS CLK 70 –12dBFS 65 60 60 55 f = 65MSPS CLK 50 50 110 100 03 5 10 15 20 25 305 f (MHz) f (MHz) OUT OUT Figure 23. SFDR vs. fOUT @ 0 dBFS Figure 26. SFDR vs. fOUT @ 65 MSPS 95 85 80 0dBFS 90 75 0dBFS 70 85 –6dBFS 65 –6dBFS –12dBFS –12dBFS 60 80 55 75 50 1.00 1.25 1.50 1.75 2.00 2.25 07 10 20 30 40 50 600 f (MHz) f (MHz) OUT OUT Figure 24. SFDR vs. fOUT @ 5 MSPS Figure 27. SFDR vs. fOUT @ 125 MSPS 90 85 I = 10mA OUTFS 80 85 0dBFS I = 20mA OUTFS 75 80 I = 5mA OUTFS –6dBFS 70 75 –12dBFS 65 70 60 65 55 60 50 01 2 4 6 8 102 03 5 10 15 20 250 f (MHz) f (MHz) OUT OUT Figure 25. SFDR vs. fOUT @ 25 MSPS Figure 28. SFDR vs. fOUT and IOUTFS @ 65 MSPS and 0 dBFS Rev. G | Page 14 of 44 SFDR (dBc) SFDR (dBc) SFDR (dBc) 00617-025 00617-023 00617-024 SFDR (dBc) SFDR (dBc) SFDR (dBc) 00617-028 00617-027 00617-026 Data Sheet AD9763/AD9765/AD9767 90 75 0.91MHz/10MSPS I = 20mA 85 OUTFS 2.27MHz/25MSPS 70 I = 10mA OUTFS 80 75 65 70 60 11.37MHz/125MSPS I = 5mA 65 OUTFS 5.91MHz/65MSPS 60 55 –20 –15 –10 –5 0 20 40 60 80 100 120 140 A (dBFS) f (MSPS) OUT CLK Figure 32. SINAD vs. f and I @ f = 5 MHz and 0 dBFS Figure 29. Single-Tone SFDR vs. AOUT @ fOUT = fCLK/11 CLK OUTFS OUT 0.6 90 1MHz/5MSPS 0.5 85 2MHz/10MSPS 0.4 5MHz/25MSPS 80 0.3 0.2 75 0.1 70 0 13MHz/65MSPS –0.1 65 25MHz/125MSPS –0.2 60 –0.3 55 –0.4 –20 –15 –10 –5 0 0 1000 2000 3000 4000 CODE A (dBFS) OUT Figure 33. Typical INL Figure 30. Single-Tone SFDR vs. AOUT @ fOUT = fCLK/5 0.05 80 3.38MHz/3.36MHz@25MSPS 0 0.965MHz/1.035MHz@7MSPS 75 –0.05 –0.10 70 –0.15 65 –0.20 6.75MHz/7.25MHz@65MSPS –0.25 16.9MHz/18.1MHz@125MSPS 60 –0.30 55 –0.35 –20 –15 –10 –5 0 0 500 1000 1500 2000 2500 3000 3500 4000 A (dBFS) OUT CODE Figure 31. Dual-Tone SFDR vs. A @ f = f /7 OUT OUT CLK Figure 34. Typical DNL Rev. G | Page 15 of 44 SFDR (dBc) SFDR (dBc) SFDR (dBc) 00617-031 00617-030 00617-029 SINAD (dBc) DNL (LSB) INL (LSB) 00617-033 00617-034 00617-032 AD9763/AD9765/AD9767 Data Sheet 85 0 f = 1MHz OUT –10 80 f = 10MHz OUT –20 75 –30 70 f = 25MHz –40 OUT 65 –50 60 f = 40MHz OUT –60 55 –70 f = 60MHz OUT 50 –80 45 –90 –60 –40 –20 0 20 40 60 80 100 04 10 20 300 TEMPERATURE (°C) FREQUENCY (MHz) Figure 35. SFDR vs. Temperature @ 125 MSPS, 0 dBFS Figure 38. Dual-Tone SFDR @ fCLK = 125 MSPS 0.05 1.0 0 –10 –20 0.03 0.5 GAIN ERROR OFFSET ERROR –30 –40 0 0 –50 –60 –0.03 –0.5 –70 –80 –0.05 –1.0 –90 –40 –20 0 20406080 04 10 20 300 TEMPERATURE (°C) FREQUENCY (MHz) Figure 36. Gain and Offset Error vs. Temperature @ fCLK = 125 MSPS Figure 39. Four-Tone SFDR @ fCLK = 125 MSPS 10 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 04 10 20 300 FREQUENCY (MHz) Figure 37. Single-Tone SFDR @ fCLK = 125 MSPS Rev. G | Page 16 of 44 OFFSET ERROR (%FS) SFDR (dBc) SFDR (dBm) GAIN ERROR (%FS) 00617-037 00617-035 00617-036 SFDR (dBm) SFDR (dBm) 00617-039 00617-038 Data Sheet AD9763/AD9765/AD9767 AD9767 AVDD = 3.3 V or 5 V, DVDD = 3.3 V or 5 V, IOUTFS = 20 mA, 50 Ω doubly terminated load, differential output, TA = 25°C, SFDR up to Nyquist, unless otherwise noted. 90 85 f = 5MSPS CLK 80 f = 25MSPS CLK 0dBFS 80 75 –6dBFS f = 125MSPS CLK 70 70 –12dBFS 65 60 60 55 f = 65MSPS CLK 50 50 110 100 03 5 10 15 20 25 305 f (MHz) f (MHz) OUT OUT Figure 40. SFDR vs. fOUT @ 0 dBFS Figure 43. SFDR vs. fOUT @ 65 MSPS 90 85 80 0dBFS 0dBFS 75 85 70 –6dBFS –6dBFS –12dBFS 65 –12dBFS 80 60 55 75 50 02 0.5 1.0 1.5 2.0.5 07 10 20 30 40 50 600 f (MHz) f (MHz) OUT OUT Figure 41. SFDR vs. fOUT @ 5 MSPS Figure 44. SFDR vs. fOUT @ 125 MSPS 90 90 0dBFS 85 85 I = 5mA OUTFS –12dBFS 80 80 75 I = 10mA OUTFS 75 70 65 70 –6dBFS 60 I = 20mA OUTFS 65 55 60 50 01 2 4 6 8 102 03 5 10 15 20 25 305 f (MHz) f (MHz) OUT OUT Figure 42. SFDR vs. fOUT @ 25 MSPS Figure 45. SFDR vs. fOUT and IOUTFS @ 65 MSPS and 0 dBFS Rev. G | Page 17 of 44 SFDR (dBc) SFDR (dBc) SFDR (dBc) 00617-042 00617-041 00617-040 SFDR (dBc) SFDR (dBc) SFDR (dBc) 00617-045 00617-044 00617-043 AD9763/AD9765/AD9767 Data Sheet 75 90 910kHz/10MSPS 85 2.27MHz/25MSPS 70 I = 20mA OUTFS 80 I = 10mA OUTFS 65 75 I = 5mA OUTFS 70 60 11.37MHz/125MSPS 65 5.91MHz/65MSPS 55 60 20 40 60 80 100 120 140 –20 –15 –10 –5 0 A (dBFS) f (MSPS) OUT CLK Figure 46. Single-Tone SFDR vs. A @ f = f /11 Figure 49. SINAD vs. f and I @ f = 5 MHz and 0 dBFS OUT OUT CLK CLK OUTFS OUT 90 2.5 1MHz/5MSPS 85 2.0 2MHz/10MSPS 80 1.5 75 1.0 5MHz/25MSPS 70 0.5 65 0 13MHz/65MSPS 60 –0.5 25MHz/125MSPS 55 –1.0 50 –1.5 –20 –15 –10 –5 0 0 4000 8000 12000 16000 A (dBFS) OUT CODE Figure 47. Single-Tone SFDR vs. A @ f = f /5 OUT OUT CLK Figure 50. Typical INL 85 0.4 0.965MHz/1.035MHz@7MSPS 0.2 80 3.38MHz/3.63MHz@25MSPS 0 75 –0.2 70 –0.4 –0.6 65 16.9MHz/18.1MHz@125MSPS –0.8 60 6.75MHz/7.25MHz@65MSPS –1.0 55 –1.2 50 –1.4 –25 –20 –15 –10 –5 0 0 200 400 600 800 1000 A (dBFS) CODE OUT Figure 51. Typical DNL Figure 48. Dual-Tone SFDR vs. A @ f = f /7 OUT OUT CLK Rev. G | Page 18 of 44 SFDR (dBc) SFDR (dBc) SFDR (dBc) 00617-048 00617-047 00617-046 SINAD (dBc) INL (LSB) DNL (LSB) 00617-051 00617-050 00617-049 Data Sheet AD9763/AD9765/AD9767 85 0 f = 1MHz OUT –10 80 f = 10MHz OUT –20 75 –30 70 f = 25MHz –40 OUT 65 –50 f = 40MHz OUT 60 –60 55 –70 f = 60MHz OUT 50 –80 45 –90 –60 –40 –20 0 20 40 60 80 100 04 10 20 300 TEMPERATURE (°C) FREQUENCY (MHz) Figure 52. SFDR vs. Temperature @ 125 MSPS, 0 dBFS Figure 55. Dual-Tone SFDR @ fCLK = 125 MSPS 0.05 1.0 0 –10 –20 0.03 0.5 GAIN ERROR OFFSET ERROR –30 –40 0 0 –50 –60 –0.03 –0.5 –70 –80 –0.05 –1.0 –90 –40 –20 0 20406080 04 10 20 300 TEMPERATURE (°C) FREQUENCY (MHz) Figure 53. Gain and Offset Error vs. Temperature @ fCLK = 125 MSPS Figure 56. Four-Tone SFDR @ fCLK = 125 MSPS 10 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 04 10 20 300 FREQUENCY (MHz) Figure 54. Single-Tone SFDR @ f = 125 MSPS CLK Rev. G | Page 19 of 44 OFFSET ERROR (%FS) SFDR (dBc) SFDR (dBm) GAIN ERROR (%FS) 00617-054 00617-052 00617-053 SFDR (dBm) SFDR (dBm) 00617-056 00617-055 AD9763/AD9765/AD9767 Data Sheet TERMINOLOGY Linearity Error (Integral Nonlinearity or INL) Temperature Drift Linearity error is defined as the maximum deviation of the Temperature drift is specified as the maximum change from the actual analog output from the ideal output, determined by a ambient (25°C) value to the value at either TMIN or TMAX. For straight line drawn from zero to full scale. offset and gain drift, the drift is reported in part per million (ppm) of full-scale range (FSR) per degree Celsius. For reference drift, Differential Nonlinearity (DNL) the drift is reported in ppm per degree Celsius (ppm/°C). DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code. Power Supply Rejection (PSR) PSR is the maximum change in the full-scale output as the Monotonicity supplies are varied from nominal to minimum and maximum A DAC is monotonic if the output either increases or remains specified voltages. constant as the digital input increases. Settling Time Offset Error Settling time is the time required for the output to reach and Offset error is the deviation of the output current from the ideal of remain within a specified error band about its final value, zero. For I , 0 mA output is expected when the inputs are all 0s. OUTA measured from the start of the output transition. For I , 0 mA output is expected when all inputs are set to 1s. OUTB Glitch Impulse Gain Error Asymmetrical switching times in a DAC give rise to undesired Gain error is the difference between the actual and ideal output output transients that are quantified by a glitch impulse. It is spans. The actual span is determined by the output when all inputs specified as the net area of the glitch in picovolts per second (pV-s). are set to 1s minus the output when all inputs are set to 0s. Spurious-Free Dynamic Range (SFDR) Output Compliance Range The difference, in decibels (dB), between the rms amplitude of The output compliance range is the range of allowable voltage at the output signal and the peak spurious signal over the specified the output of a current-output DAC. Operation beyond the bandwidth. maximum compliance limits may cause either output stage saturation or breakdown resulting in nonlinear performance. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal. It is expressed as a percentage or in decibels (dB). Rev. G | Page 20 of 44 Data Sheet AD9763/AD9765/AD9767 THEORY OF OPERATION 5V CLK1/IQCLK CLK2/IQRESET SLEEP AVDD Mini-Circuits TO HP3589A CLK T1-1T OR EQUIVALENT DIVIDER FSADJ1 PMOS SPECTRUM/ I OUTA1 R 1 CURRENT NETWORK SET SEGMENTED REFIO SOURCE ANALYZER 2kΩ LSB I SWITCHES FOR ARRAY OUTB1 SWITCH DAC1 DAC1 0.1µF LATCH PMOS 50Ω 50Ω I OUTA2 CURRENT FSADJ2 SEGMENTED SOURCE LSB SWITCHES FOR I ARRAY OUTB2 R 2 SWITCH SET DAC2 DAC2 2kΩ LATCH AD9763/ MODE AD9765/ MULTIPLEXING LOGIC 1.2V REF AD9767 DVDD1/ 5V DVDD2 WRT1/ DCOM1/ CHANNEL 1 LATCH CHANNEL 2 LATCH GAINCTRL IQWRT DCOM2 ACOM PORT 1 PORT 2 WRT2/ IQSEL DVDD1/DVDD2 50Ω DCOM1/DCOM2 DIGITAL RETIMED CLOCK OUTPUT* DATA LECROY 9210 TEKTRONIX *AWG2021 CLOCK RETIMED SUCH THAT PULSE AWG2021 DIGITAL DATA TRANSITIONS ON FALLING GENERATOR w/OPTION 4 EDGE OF 50% DUTY CYCLE CLOCK. Figure 57. Basic AC Characterization Test Setup for AD9763/AD9765/AD9767, Testing Port 1 in Dual-Port Mode, Using Independent GAINCTRL Resistors on FSADJ1 and FSADJ2 5V CLK1/IQCLK CLK2/IQRESET AVDD SLEEP V = V A – V B ACOM R 1 CLK DIFF OUT OUT SET DIVIDER 2kΩ FSADJ1 PMOS V 1A I OUT OUTA1 CURRENT I 1 REF 0.1µF SEGMENTED REFIO SOURCE LSB 1B V SWITCHES FOR I OUT R 1A ARRAY OUTB1 L SWITCH DAC1 DAC1 50Ω LATCH R 1B L PMOS V 2A R 2 50Ω SET I OUT CURRENT OUTA2 2kΩ FSADJ2 SEGMENTED SOURCE LSB SWITCHES FOR V 2B R 2A I OUT ARRAY OUTB2 L I 2 DAC2 SWITCH REF DAC2 50Ω LATCH R 2B L AD9763/ MODE 50Ω AD9765/ MULTIPLEXING LOGIC 1.2V REF AD9767 DVDD1/ 5V DCOM1/ DVDD2 CHANNEL 1 LATCH CHANNEL 2 LATCH DCOM2 GAINCTRL WRT1/ PORT 1 PORT 2 WRT2/ IQWRT IQSEL DIGITAL DATA INPUTS NOTES 1. IN THIS CONFIGURATION, THE 22nF CAPACITOR AND 256Ω RESISTOR ARE NOT REQUIRED BECAUSE R = 2kΩ. SET Figure 58. Simplified Block Diagram All of these current sources are switched to one of the two FUNCTIONAL DESCRIPTION output nodes (that is, I or I ) via the PMOS differential OUTA OUTB Figure 58 shows a simplified block diagram of the AD9763/ current switches. The switches are based on a new architecture AD9765/AD9767. The AD9763/AD9765/AD9767 consist of that drastically improves distortion performance. This new two DACs, each one with its own independent digital control switch architecture reduces various timing errors and provides logic and full-scale output current control. Each DAC contains matching complementary drive signals to the inputs of the a PMOS current source array capable of providing up to 20 mA differential current switches. of full-scale current (I ). OUTFS The analog and digital sections of the AD9763/AD9765/AD9767 The array is divided into 31 equal currents that make up the five have separate power supply inputs (that is, AVDD and DVDD1/ most significant bits (MSBs). The next four bits, or middle bits, DVDD2) that can operate independently at 3.3 V or 5 V. The consist of 15 equal current sources whose value is 1/16th of an digital section, which is capable of operating up to a 125 MSPS MSB current source. The remaining LSB is a binary weighted clock rate, consists of edge-triggered latches and segment decoding fraction of the middle bit current sources. Implementing the logic circuitry. The analog section includes the PMOS current middle and lower bits with current sources, instead of an R-2R sources, the associated differential switches, a 1.20 V band gap ladder, enhances the dynamic performance for multitone or low voltage reference, and two reference control amplifiers. amplitude signals and helps maintain the high output impedance of each DAC (that is, >100 kΩ). Rev. G | Page 21 of 44 00617-057 00617-058 AD9763/AD9765/AD9767 Data Sheet The full-scale output current of each DAC is regulated by GAIN CONTROL MODE separate reference control amplifiers and can be set from The AD9763/AD9765/AD9767 has two gain control modes, 2 mA to 20 mA via an external network connected to the full independent and master/slave. If the GAINCTRL terminal is low scale adjust (FSADJ) pin. The external network, in combination (connected to ground), the full-scale currents of DAC1 and DAC2 with both the reference control amplifier and voltage reference are set separately using two different R resistors. One resistor SET (VREFIO) sets the reference current IREF, which is replicated to the is connected to the FSADJ1 terminal, and the other resistor is segmented current sources with the proper scaling factor. The connected to the FSADJ2 terminal. This is independent mode. full-scale current (IOUTFS) is 32 × IREF. If the GAINCTRL terminal is set high (connected to AVDD), REFERENCE OPERATION the full-scale currents of DAC1 and DAC2 are set to the same value using one RSET resistor. In master/slave mode, full-scale current The AD9763/AD9765/AD9767 contain an internal 1.20 V band for both DAC1 and DAC2 is set via the FSADJ1 terminal. gap reference. This can easily be overridden by a low noise external reference with no effect on performance. REFIO serves as either SETTING THE FULL-SCALE CURRENT an input or output, depending on whether the internal or an Both of the DACs in the AD9763/AD9765/AD9767 contain a external reference is used. To use the internal reference, simply control amplifier that is used to regulate the full-scale output decouple the REFIO pin to ACOM with a 0.1 μF capacitor. The current (IOUTFS). The control amplifier is configured as a V-I internal reference voltage is present at REFIO. If the voltage at converter, as shown in Figure 59, so that its current output (I ) REF REFIO is used elsewhere in the circuit, an external buffer amplifier is determined by the ratio of the V and an external resistor, REFIO with an input bias current of less than 100 nA should be used. An R . SET example of the use of the internal reference is shown in Figure 59. I = V /R REF REFIO SET GAINCTRL AVDD OPTIONAL EXTERNAL The DAC full-scale current, IOUTFS, is an output current 32 times REFERENCE AD9763/ BUFFER AD9765/ larger than the reference current, IREF. AD9767 1.2V REF REFERENCE SECTION IOUTFS = 32 × IREF REFIO CURRENT ADDITIONAL SOURCE The control amplifier allows a wide (10:1) adjustment span of EXTERNAL 0.1µF ARRAY LOAD FSADJ1/ 256Ω I from 2 mA to 20 mA by setting I between 62.5 μA and OUTFS REF FSADJ2 ACOM I REF 22nF 625 μA. The wide adjustment range of I provides several OUTFS R SET benefits. The first relates directly to the power dissipation of the AD9763/AD9765/AD9767, which is proportional to IOUTFS (refer to Figure 59. Internal Reference Configuration the Power Dissipation section). The second relates to the 20 dB An external reference can be applied to REFIO as shown in adjustment, which is useful for system gain control purposes. Figure 60. The external reference can provide either a fixed To ensure that the AD9763/AD9765/AD9767 performs properly, reference voltage to enhance accuracy and drift performance connect a 22 nF capacitor and 256 Ω resistor network (shown in or a varying reference voltage for gain control. The 0.1 μF Figure 59 and Figure 60) from the FSADJ1 terminal to ground compensation capacitor is not required because the internal and from the FSADJ2 terminal to ground. reference is overridden and the relatively high input impedance of REFIO minimizes any loading of the external reference. GAINCTRL AVDD AD9763/ AD9765/ AD9767 AVDD 1.2V REFERENCE REF SECTION REFIO EXTERNAL CURRENT REFERENCE SOURCE ARRAY FSADJ1/ 256Ω FSADJ2 ACOM I REF 22nF R SET Figure 60. External Reference Configuration Gain Control Mode Rev. G | Page 22 of 44 00617-060 00617-059 Data Sheet AD9763/AD9765/AD9767 The gain drift temperature performance for a single-ended DAC TRANSFER FUNCTION (V and V ) or differential output (V ) of the OUTA OUTB DIFF Both DACs in the AD9763/AD9765/AD9767 provide comple- AD9763/AD9765/AD9767 can be enhanced by selecting mentary current outputs, IOUTA and IOUTB. IOUTA provides a near temperature tracking resistors for RLOAD and RSET due to their full-scale current output (IOUTFS) when all bits are high (that is, ratiometric relationship. DAC CODE = 1024/4095/16,384 for the AD9763/AD9765/ AD9767, respectively), while I , the complementary output, OUTB ANALOG OUTPUTS provides no current. The current output appearing at I and OUTA The complementary current outputs, I and I , in each OUTA OUTB IOUTB is a function of both the input code and IOUTFS. IOUTA for the DAC can be configured for single-ended or differential AD9763, AD9765, and AD9767, respectively, can be expressed as operation. IOUTA and IOUTB can be converted into complementary IOUTA = (DAC CODE/1024) × IOUTFS (1) single-ended voltage outputs, VOUTA and VOUTB, via a load resistor (RLOAD) as described in Equation 5 through Equation 7. IOUTA = (DAC CODE/4096) × IOUTFS The differential voltage (V ) existing between V and V DIFF OUTA OUTB I = (DAC CODE/16,384) × I OUTA OUTFS can be converted to a single-ended voltage via a transformer or I for the AD9763, AD9765, and AD9767, respectively, can be differential amplifier configuration. The ac performance of the OUTB expressed as AD9763/AD9765/AD9767 is optimum and specified using a differential transformer-coupled output in which the voltage I = ((1023 − DAC CODE)/1024) × I (2) OUTB OUTFS swing at IOUTA and IOUTB is limited to ±0.5 V. If a single-ended IOUTB = ((4095 − DAC CODE)/4096) × IOUTFS unipolar output is desired, select IOUTA. IOUTB = ((16,383 − DAC CODE)/16,384) × IOUTFS The distortion and noise performance of the AD9763/AD9765/ where DAC CODE = 0 to 1024, 0 to 4095, or 0 to 16,384 (decimal AD9767 can be enhanced when it is configured for differential representation). operation. The common-mode error sources of both I and OUTA I can be significantly reduced by the common-mode rejection OUTB I is a function of the reference current (I ). This is nominally OUTFS REF of a transformer or differential amplifier. These common-mode set by a reference voltage (V ) and an external resistor (R ). REFIO SET error sources include even-order distortion products and noise. It can be expressed as The enhancement in distortion performance becomes more IOUTFS = 32 × IREF (3) significant as the frequency content of the reconstructed waveform where IREF is set as discussed in the Setting the Full-Scale increases. This is due to the first-order cancellation of various Current section. dynamic common-mode distortion mechanisms, digital feed- through, and noise. The two current outputs typically drive a resistive load directly or via a transformer. If dc coupling is required, I and I Performing a differential-to-single-ended conversion via a trans- OUTA OUTB should be directly connected to matching resistive loads (R ) LOAD former also provides the ability to deliver twice the reconstructed that are tied to the analog common (ACOM). Note that R LOAD signal power to the load, assuming no source termination. Because can represent the equivalent load resistance seen by IOUTA or IOUTB, the output currents of IOUTA and IOUTB are complementary, they as is the case in a doubly terminated 50 Ω or 75 Ω cable. The single- become additive when processed differentially. A properly selected ended voltage output appearing at the IOUTA and IOUTB nodes is transformer allows the AD9763/AD9765/AD9767 to provide the required power and voltage levels to different loads. VOUTA = IOUTA × RLOAD (5) The output impedance of I and I is determined by the OUTA OUTB V = I × R (6) OUTB OUTB LOAD equivalent parallel combination of the PMOS switches associated Note that the full-scale value of V and V must not OUTA OUTB with the current sources and is typically 100 kΩ in parallel with exceed the specified output compliance range to maintain the 5 pF. It is also slightly dependent on the output voltage (that is, specified distortion and linearity performance. VOUTA and VOUTB) due to the nature of a PMOS device. As a result, VDIFF = (IOUTA − IOUTB) × RLOAD (7) maintaining IOUTA and/or IOUTB at a virtual ground via an I-V op amp configuration results in the optimum dc linearity. Note that Equation 7 highlights some of the advantages of operating the the INL/DNL specifications for the AD9763/AD9765/AD9767 are AD9763/AD9765/AD9767 differentially. First, the differential measured with I maintained at a virtual ground via an op amp. OUTA operation helps cancel common-mode error sources associated with I and I such as noise, distortion, and dc offsets. OUTA OUTB Second, the differential code-dependent current and subsequent voltage, VDIFF, is twice the value of the single-ended voltage output (that is, VOUTA or VOUTB), thus providing twice the signal power to the load. Rev. G | Page 23 of 44 AD9763/AD9765/AD9767 Data Sheet I and I also have a negative and positive voltage PORT 1 DAC1 OUTA OUTB INTERLEAVED INPUT LATCH DATA IN, PORT 1 compliance range that must be adhered to in order to achieve LATCH optimum performance. The negative output compliance range DAC1 DEINTERLEAVED of −1.0 V is set by the breakdown limits of the CMOS process. DATA OUT PORT 2 IQWRT INPUT DAC2 IQSEL Operation beyond this maximum limit may result in a breakdown LATCH LATCH of the output stage and affect the reliability of the DAC2 IQCLK AD9763/AD9765/AD9767. ÷2 IQRESET The positive output compliance range is slightly dependent on Figure 61. Latch Structure in Interleaved Mode the full-scale output current, I . When I is decreased OUTFS OUTFS Dual-Port Mode Timing from 20 mA to 2 mA, the positive output compliance range When the MODE pin is at Logic 1, the AD9763/AD9765/AD9767 degrades slightly from its nominal 1.25 V to 1.00 V. The optimum operates in dual-port mode (refer to Figure 57). The AD9763/ distortion performance for a single-ended or differential output AD9765/AD9767 functions as two distinct DACs. Each DAC is achieved when the maximum full-scale signal at IOUTA and IOUTB has its own completely independent digital input and control lines. does not exceed 0.5 V. Applications requiring the AD9763/ AD9765/AD9767 output (that is, VOUTA and/or VOUTB) to extend its The AD9763/AD9765/AD9767 features a double-buffered data output compliance range must size R accordingly. Operation LOAD path. Data enters the device through the channel input latches. beyond this compliance range adversely affects the linearity This data is then transferred to the DAC latch in each signal performance of the AD9763/AD9765/AD9767 and path. After the data is loaded into the DAC latch, the analog subsequently degrades its distortion performance. output settles to its new value. DIGITAL INPUTS For general consideration, the WRT lines control the channel input latches, and the CLK lines control the DAC latches. Both The digital inputs of the AD9763/AD9765/AD9767 consist of sets of latches are updated on the rising edge of their respective two independent channels. For the dual-port mode, each DAC has control signals. its own dedicated 10-/12-/14-bit data port: WRT line and CLK line. In the interleaved timing mode, the function of the digital control The rising edge of CLK must occur before or simultaneously pins changes as described in the Interleaved Mode Timing with the rising edge of WRT. If the rising edge of CLK occurs section. The 10-/12-/14-bit parallel data inputs follow straight after the rising edge of WRT, a minimum delay of 2 ns must be binary coding, where the most significant bits (MSBs) are DB9P1 maintained from the rising edge of WRT to the rising edge of CLK. and DB9P2 for the AD9763, DB11P1 and DB11P2 for the AD9765, Timing specifications for dual-port mode are shown in Figure 62 and DB13P1 and DB13P2 for the AD9767, and the least significant and Figure 63. bits (LSBs) are DB0P1 and DB0P2 for all three parts. I produces OUTA t t S H a full-scale output current when all data bits are at Logic 1. IOUTB DATA IN produces a complementary output with the full-scale current split between the two outputs as a function of the input code. WRT1/WRT2 t The digital interface is implemented using an edge-triggered LPW master/slave latch. The DAC outputs are updated following CLK1/CLK2 t either the rising edge or every other rising edge of the clock, CPW depending on whether dual or interleaved mode is used. The I OUTA OR DAC outputs are designed to support a clock rate as high as I OUTB t PD 125 MSPS. The clock can be operated at any duty cycle that Figure 62. Dual-Port Mode Timing meets the specified latch pulse width. The setup and hold times can also be varied within the clock cycle as long as the specified DATA IN D1 D2 D3 D4 D5 minimum times are met, although the location of these transition edges may affect digital feedthrough and distortion performance. WRT1/WRT2 Best performance is typically achieved when the input data transitions on the falling edge of a 50% duty cycle clock. CLK1/CLK2 DAC TIMING I OUTA XX D3 The AD9763/AD9765/AD9767 can operate in two timing modes, D2 D4 OR D1 I OUTB dual and interleaved, which are described in the following Figure 63. Dual-Port Mode Timing sections. The block diagram in Figure 61 represents the latch architecture in the interleaved timing mode. Rev. G | Page 24 of 44 00617-063 00617-062 00617-061 Data Sheet AD9763/AD9765/AD9767 t t S H Interleaved Mode Timing When the MODE pin is at Logic 0, the AD9763/AD9765/AD9767 DATA IN operate in interleaved mode (refer to Figure 61). In addition, WRT1 functions as IQWRT, CLK1 functions as IQCLK, WRT2 functions as IQSEL, and CLK2 functions as IQRESET. IQSEL Data enters the device on the rising edge of IQWRT. The logic level of IQSEL steers the data to either Channel Latch 1 (IQSEL = 1) or t * H to Channel Latch 2 (IQSEL = 0). For proper operation, IQSEL IQWRT must change state only when IQWRT and IQCLK are low. t LPW When IQRESET is high, IQCLK is disabled. When IQRESET goes low, the next rising edge on IQCLK updates both DAC IQCLK latches with the data present at their inputs. In the interleaved mode, IQCLK is divided by 2 internally. Following this first t I OUTA PD OR rising edge, the DAC latches are only updated on every other I OUTB rising edge of IQCLK. In this way, IQRESET can be used to *APPLIES TO FALLING EDGE OF IQCLK/IQWRT AND IQSEL ONLY. synchronize the routing of the data to the DACs. Figure 65. 5 V Only Interleaved Mode Timing Similar to the order of CLK and WRT in dual-port mode, INTERLEAVED IQCLK must occur before or simultaneously with IQWRT. xx D1 D2 D3 D4 D5 DATA Timing specifications for interleaved mode are shown in Figure 64 IQSEL and Figure 66. The digital inputs are CMOS compatible with logic thresholds, IQWRT V , set to approximately half the digital positive supply THRESHOLD (DVDDx), or IQCLK V = DVDDx/2(±20%) THRESHOLD IQRESET t t S H DAC OUTPUT xx D3 PORT 1 D1 DATA IN xx DAC OUTPUT D4 500 ps PORT 2 D2 Figure 66. Interleaved Mode Timing IQSEL The internal digital circuitry of the AD9763/AD9765/AD9767 is capable of operating at a digital supply of 3.3 V or 5 V. As a t * H result, the digital inputs can also accommodate TTL levels when IQWRT DVDD1/DVDD2 is set to accommodate the maximum high t LPW level voltage (VOH(MAX)) of the TTL drivers. A DVDD1/DVDD2 of 3.3 V typically ensures proper compatibility with bipolar TTL IQCLK logic families. Figure 67 shows the equivalent digital input circuit for the data and clock inputs. The sleep mode input is 500 ps similar, with the exception that it contains an active pull-down I OUTA t PD circuit, thus ensuring that the AD9763/AD9765/AD9767 OR I OUTB remains enabled if this input is left disconnected. DVDD1 *APPLIES TO FALLING EDGE OF IQCLK/IQWRT AND IQSEL ONLY. Figure 64. 5 V or 3.3 V Interleaved Mode Timing At 5 V it is permissible to drive IQWRT and IQCLK together as DIGITAL INPUT shown in Figure 65, but at 3.3 V the interleaved data transfer is not reliable. Figure 67. Equivalent Digital Input Rev. G | Page 25 of 44 00617-064 00617-067 00617-065 00617-066 AD9763/AD9765/AD9767 Data Sheet 80 Because the AD9763/AD9765/AD9767 is capable of being clocked AD9763 AD9765 up to 125 MSPS, the quality of the clock and data input signals AD9767 70 are important in achieving the optimum performance. Operating 60 the AD9763/AD9765/AD9767 with reduced logic swings and a corresponding digital supply (DVDD1/DVDD2) results in the 50 lowest data feedthrough and on-chip digital noise. The drivers of 40 the digital data interface circuitry should be specified to meet the minimum setup and hold times of the AD9763/AD9765/AD9767 30 as well as its required minimum and maximum input logic level 20 thresholds. 10 Digital signal paths should be kept short, and run lengths should be matched to avoid propagation delay mismatch. The insertion 0 –4 –3 –2 –1 0 1 2 3 4 of a low value (that is, 20 Ω to 100 Ω) resistor network between TIME OF DATA CHANGE RELATIVE TO RISING CLOCK EDGE (ns) the AD9763/AD9765/AD9767 digital inputs and driver outputs Figure 68. SNR vs. Clock Placement @ fOUT = 20 MHz and fCLK = 125 MSPS can be helpful in reducing any overshooting and ringing at the digital inputs that contribute to digital feedthrough. For longer SLEEP MODE OPERATION board traces and high data update rates, stripline techniques The AD9763/AD9765/AD9767 has a power-down function that with proper impedance and termination resistors should be turns off the output current and reduces the supply current to less considered to maintain “clean” digital inputs. than 8.5 mA over the specified supply range of 3.3 V to 5 V and The external clock driver circuitry provides the AD9763/AD9765/ over the full operating temperature range. This mode can be AD9767 with a low-jitter clock input meeting the minimum activated by applying a Logic Level 1 to the SLEEP pin. The and maximum logic levels while providing fast edges. Fast clock SLEEP pin logic threshold is equal to 0.5 × AVDD. This digital edges help minimize jitter manifesting itself as phase noise on a input also contains an active pull-down circuit that ensures the reconstructed waveform. Therefore, the clock input should be AD9763/AD9765/AD9767 remains enabled if this input is left driven by the fastest logic family suitable for the application. disconnected. The AD9763/AD9765/AD9767 require less than 50 ns to power down and approximately 5 μs to power back up. Note that the clock input can also be driven via a sine wave, which is centered around the digital threshold (that is, DVDDx/2) and POWER DISSIPATION meets the minimum and maximum logic threshold. This The power dissipation (PD) of the AD9763/AD9765/AD9767 is typically results in a slight degradation in the phase noise, which dependent on several factors, including becomes more noticeable at higher sampling rates and output frequencies. In addition, at higher sampling rates, the 20% • the power supply voltages (AVDD and DVDD1/DVDD2) tolerance of the digital logic threshold should be considered, • the full-scale current output (IOUTFS) because it affects the effective clock duty cycle and, • the update rate (fCLK) subsequently, cuts into the required data setup and hold times. • the reconstructed digital input waveform Input Clock and Data Timing Relationship The power dissipation is directly proportional to the analog SNR in a DAC is dependent on the relationship between the supply current (I ) and the digital supply current (I ). AVDD DVDD position of the clock edges and the point in time at which the I is directly proportional to I as shown in Figure 69, AVDD OUTFS, input data changes. The AD9763/AD9765/AD9767 are rising and is insensitive to f . CLK edge triggered and therefore exhibit SNR sensitivity when the Conversely, IDVDD is dependent on the digital input waveform, data transition is close to this edge. The goal when applying the the fCLK, and the digital supply (DVDD1/DVDD2). Figure 70 AD9763/AD9765/AD9767 is to make the data transition close and Figure 71 show IDVDD as a function of full-scale sine wave to the falling clock edge. This becomes more important as the output ratios (fOUT/fCLK) for various update rates with DVDD1 = sample rate increases. Figure 68 shows the relationship of SNR DVDD2 = 5 V and DVDD1 = DVDD2 = 3.3 V, respectively. Note to clock placement with different sample rates. Note that at the that I is reduced by more than a factor of 2 when DVDD lower sample rates, much more tolerance is allowed in clock DVDD1/DVDD2 is reduced from 5 V to 3.3 V. placement; much more care must be taken at higher rates. Rev. G | Page 26 of 44 SNR (dBc) 00617-068 Data Sheet AD9763/AD9765/AD9767 80 18 125MSPS 16 70 14 100MSPS 90 12 50 10 65MSPS 8 40 6 30 25MSPS 4 20 5MSPS 2 10 0 02 5 10 15 205 00 0.1 0.2 0.3 0.4.5 I RATIO (f /f ) OUTFS OUT CLK Figure 69. I vs. I AVDD OUTFS Figure 71. I vs. Ratio @ DVDD1 = DVDD2 = 3.3 V DVDD 35 30 125MSPS 25 100MSPS 20 65MSPS 15 10 25MSPS 5 5MSPS 0 00 0.1 0.2 0.3 0.4.5 RATIO (f /f ) OUT CLK Figure 70. I vs. Ratio @ DVDD1 = DVDD2 = 5 V DVDD Rev. G | Page 27 of 44 I (mA) I (mA) DVDD AVDD 00617-069 00617-070 I (mA) DVDD 00617-071 AD9763/AD9765/AD9767 Data Sheet APPLYING THE AD9763/AD9765/AD9767 for both IOUTA and IOUTB. The complementary voltages appearing OUTPUT CONFIGURATIONS at IOUTA and IOUTB (that is, VOUTA and VOUTB) swing symmetrically The following sections illustrate some typical output configurations around ACOM and must be maintained with the output compli- for the AD9763/AD9765/AD9767, with I set to a nominal OUTFS ance range of the AD9763/AD9765/AD9767 to achieve the 20 mA, unless otherwise noted. For applications requiring the specified performance. A differential resistor (R ) can be DIFF optimum dynamic performance, a differential output configuration inserted in applications where the output of the transformer is is suggested. A differential output configuration can consist of connected to the load (R ) via a passive reconstruction filter LOAD either an RF transformer or a differential op amp configuration. or cable. R is determined by the transformer’s impedance DIFF The transformer configuration provides the optimum high ratio and provides the proper source termination that results in a frequency performance and is recommended for any application low VSWR. Approximately half the signal power will be dissipated allowing for ac coupling. The differential op amp configuration across RDIFF. is suitable for applications requiring dc coupling, bipolar DIFFERENTIAL COUPLING USING AN OP AMP output, signal gain, and/or level shifting within the bandwidth of the chosen op amp. An op amp can also be used as shown in Figure 73 to perform a differential-to-single-ended conversion. The AD9763/AD9765/ A single-ended output is suitable for applications requiring AD9767 is configured with two equal load resistors (RLOAD) of a unipolar voltage output. A positive unipolar output voltage 25 Ω each. The differential voltage developed across IOUTA and results if IOUTA and/or IOUTB is connected to an appropriately I is converted to a single-ended signal via the differential OUTB sized load resistor (R ) referred to as ACOM. This configuration LOAD op amp configuration. An optional capacitor can be installed may be more suitable for a single-supply system requiring a across I and I , forming a real pole in a low-pass filter. OUTA OUTB dc-coupled, ground-referred output voltage. Alternatively, an The addition of this capacitor often enhances the op amp’s amplifier can be configured as an I-V converter, thus converting distortion performance by preventing the DAC’s high-slewing IOUTA or IOUTB into a negative unipolar voltage. This configura- output from overloading the op amp’s input. tion provides the best dc linearity because IOUTA or IOUTB is 500Ω maintained at a virtual ground. Note that IOUTA provides slightly I OUTA better performance than IOUTB. 225Ω AD9763/ AD9765/ DIFFERENTIAL COUPLING USING A AD8047 AD9767 225Ω I OUTB TRANSFORMER C OPT An RF transformer can be used as shown in Figure 72 to 500Ω 25Ω 25Ω perform a differential-to-single-ended signal conversion. A differentially coupled transformer output provides the optimum Figure 73. DC Differential Coupling Using an Op Amp distortion performance for output signals whose spectral content lies within the pass band of the transformer. An RF transformer The common-mode rejection of this configuration is typically such as the Mini-Circuits® T1-1T provides excellent rejection of determined by the resistor matching. In this circuit, the common-mode distortion (that is, even-order harmonics) and differential op amp circuit using the AD8047 is configured to noise over a wide frequency range. It also provides electrical provide some additional signal gain. The op amp must operate isolation and the ability to deliver twice the power to the load. from a dual supply because its output is approximately ±1.0 V. Transformers with different impedance ratios can also be used Select a high speed amplifier capable of preserving the for impedance matching purposes. Note that the transformer differential performance of the AD9763/AD9765/AD9767 provides ac coupling only. while meeting other system level objectives (that is, cost or power). Consider the op amp’s differential gain, gain setting Mini-Circuits T1-1T resistor values, and full-scale output swing capabilities when I OUTA optimizing this circuit. AD9763/ R AD9765/ LOAD AD9767 The differential circuit shown in Figure 74 provides the I OUTB necessary level shifting required in a single-supply system. OPTIONAL In this case, AVDD, which is the positive analog supply for both R DIFF the AD9763/AD9765/AD9767 and the op amp, is used to level Figure 72. Differential Output Using a Transformer shift the differential output of the AD9763/AD9765/AD9767 to The center tap on the primary side of the transformer must be midsupply (that is, AVDD/2). The AD8055 is a suitable op amp connected to ACOM to provide the necessary dc current path for this application. Rev. G | Page 28 of 44 00617-072 00617-073 Data Sheet AD9763/AD9765/AD9767 C 500Ω OPT I OUTA 225Ω AD9763/ R FB AD9765/ 200Ω AD8055 AD9767 225Ω I = 10mA OUTFS I OUTB C OPT I OUTA 1kΩ AVDD U1 AD9763/ V = I × R AD9765/ OUT OUTFS FB 25Ω 25Ω 500Ω AD9767 200Ω I OUTB Figure 74. Single-Supply DC Differential-Coupled Circuit Figure 76. Unipolar Buffered Voltage Output SINGLE-ENDED, UNBUFFERED VOLTAGE OUTPUT POWER AND GROUNDING CONSIDERATIONS Figure 75 shows the AD9763/AD9765/AD9767 configured to provide a unipolar output range of approximately 0 V to 0.5 V Power Supply Rejection for a doubly terminated 50 Ω cable, because the nominal full- Many applications seek high speed and high performance under scale current (I ) of 20 mA flows through the equivalent OUTFS less than ideal operating conditions. In these applications, the R of 25 Ω. In this case, R represents the equivalent load LOAD LOAD implementation and construction of the printed circuit board is resistance seen by I or I . The unused output (I or I ) OUTA OUTB OUTA OUTB as important as the circuit design. Proper RF techniques must can be connected directly to ACOM or via a matching RLOAD. be used for device selection, placement, and routing as well as Different values of IOUTFS and RLOAD can be selected as long as the power supply bypassing and grounding to ensure optimum positive compliance range is adhered to. One additional performance. Figure 92 to Figure 93 illustrate recommended consideration in this mode is the INL (see the Analog Outputs printed circuit board ground, power, and signal plane layouts section). For optimum INL performance, the single-ended, that are implemented on the AD9763/AD9765/AD9767 buffered voltage output configuration is suggested. evaluation board. I = 20mA OUTFS V = 0V TO 0.5V OUTA One factor that can measurably affect system performance is I OUTA AD9763/ the ability of the DAC output to reject dc variations or ac noise 50Ω 50Ω AD9765/ superimposed on the analog or digital dc power distribution. AD9767 I This is referred to as the power supply rejection ratio (PSRR). OUTB 25Ω For dc variations of the power supply, the resulting performance of the DAC directly corresponds to a gain error associated with Figure 75. 0 V to 0.5 V Unbuffered Voltage Output the DAC’s full-scale current, I . AC noise on the dc supplies OUTFS is common in applications where the power distribution is SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT generated by a switching power supply. Typically, switching CONFIGURATION power supply noise occurs over the spectrum of tens of Figure 76 shows a buffered single-ended output configuration kilohertz to several megahertz. The PSRR vs. frequency of the in which the U1 op amp performs an I-V conversion on the AD9763/AD9765/AD9767 AVDD supply over this frequency AD9763/AD9765/AD9767 output current. U1 maintains I OUTA range is shown in Figure 77. (or I ) at a virtual ground, thus minimizing the nonlinear OUTB 90 output impedance effect on the INL performance of the DAC, as described in the Analog Outputs section. Although this single- ended configuration typically provides the best dc linearity 85 performance, its ac distortion performance at higher DAC update rates may be limited by the slewing capabilities of U1. U1 provides a negative unipolar output voltage, and its full-scale 80 output voltage is simply the product of R and I . Set the FB OUTFS full-scale output within U1’s voltage output swing capabilities by scaling I and/or R . An improvement in ac distortion OUTFS FB 75 performance may result with a reduced I because the signal OUTFS current U1 has to sink will be subsequently reduced. 70 0.20.3 0.40.50.60.70.80.91.01.1 FREQUENCY (MHz) Figure 77. AVDD Power Supply Rejection Ratio vs. Frequency Rev. G | Page 29 of 44 00617-075 00617-074 PSRR (dB) 00617-077 00617-076 AD9763/AD9765/AD9767 Data Sheet Note that the data in Figure 77 is given in terms of current out Proper grounding and decoupling are primary objectives in any vs. voltage in. Noise on the analog power supply has the effect high speed, high resolution system. The AD9763/AD9765/AD9767 of modulating the internal current sources and therefore the features separate analog and digital supply and ground pins to output current. The voltage noise on AVDD, therefore, is added optimize the management of analog and digital ground currents in a nonlinear manner to the desired IOUT. PSRR is very code in a system. In general, decouple the analog supply (AVDD) to dependent, thus producing mixing effects that can modulate the analog common (ACOM) as close to the chip as physically low frequency power supply noise to higher frequencies. Worst- possible. Similarly, decouple the digital supply (DVDD1/DVDD2) case PSRR for either one of the differential DAC outputs occurs to the digital common (DCOM1/DCOM2) as close to the chip when the full-scale current is directed toward that output. As a as possible. result, the PSRR measurement in Figure 77 represents a worst- For those applications that require a single 5 V or 3.3 V supply case condition in which the digital inputs remain static and the for both the analog and digital supplies, a clean analog supply full-scale output current of 20 mA is directed to the DAC can be generated using the circuit shown in Figure 78. The output being measured. circuit consists of a differential LC filter with separate power An example serves to illustrate the effect of supply noise on the supply and return lines. Lower noise can be attained by using analog supply. Suppose a switching regulator with a switching low-ESR type electrolytic and tantalum capacitors. frequency of 250 kHz produces 10 mV of noise and, for simplicity’s FERRITE ELECTROLYTIC CERAMIC BEADS sake, all of this noise is concentrated at 250 kHz (that is, ignore AVDD TTL/CMOS 10µF LOGIC harmonics). To calculate how much of this undesired noise will TO CIRCUITS 100µF 0.1µF 22µF appear as current noise superimposed on the DAC full-scale ACOM current, IOUTFS, one must determine the PSRR in decibels using TANTALUM Figure 77 at 250 kHz. To calculate the PSRR for a given RLOAD, 5V such that the units of PSRR are converted from A/V to V/V, POWER SUPPLY adjust the curve in Figure 77 by the scaling factor 20 × log(R ). LOAD Figure 78. Differential LC Filter for Single 5 V and 3.3 V Applications For example, if R is 50 Ω, the PSRR is reduced by 34 dB (that LOAD is, the PSRR of the DAC at 250 kHz, which is 85 dB in Figure 77, becomes 51 dB V /V ). OUT IN Rev. G | Page 30 of 44 00617-078 Data Sheet AD9763/AD9765/AD9767 APPLICATIONS INFORMATION –20 VDSL EXAMPLE APPLICATIONS USING THE –30 AD9765 AND AD9767 –40 Very high frequency digital subscriber line (VDSL) technology is –50 growing rapidly in applications requiring data transfer over –60 relatively short distances. By using quadrature amplitude modulation (QAM) and transmitting the data in discrete multiple –70 tones (DMT), high data rates can be achieved. –80 As with other multitone applications, each VDSL tone is –90 capable of transmitting a given number of bits, depending on –100 the signal-to-noise ratio (SNR) in a narrow band around that –110 tone. For a typical VDSL application, the tones are evenly –120 spaced over the range of several kHz to 10 MHz. At the high 0.665 0.685 0.705 0.725 0.745 0.765 0.785 0.805 0.825 FREQUENCY (MHz) frequency end of this range, performance is generally limited by Figure 80. AD9767 Notch in Missing Bin at 750 kHz Is Down >60 dB cable characteristics and environmental factors such as external (Peak Amplitude = 0 dBm) interferers. Performance at the lower frequencies is much more –30 dependent on the performance of the components in the signal chain. In addition to in-band noise, intermodulation from other –40 tones can also potentially interfere with the data recovery for –50 a given tone. The two graphs in Figure 79 and Figure 81 –60 represent a 500-tone missing bin test vector, with frequencies –70 evenly spaced from 400 Hz to 10 MHz. This test is very commonly done to determine if distortion limits the number of –80 bits that can be transmitted in a tone. The test vector has a –90 series of missing tones around 750 kHz, which is represented in –100 Figure 79, and a series of missing tones around 5 MHz, which is represented in Figure 81. In both cases, the spurious-free –110 dynamic range (SFDR) between the transmitted tones and the –120 empty bins is greater than 60 dB. 4.85 4.90 4.95 5.00 5.05 5.10 5.15 FREQUENCY (MHz) –20 Figure 81. AD9765 Notch in Missing Bin at 5 MHz Is Down >60 dB –30 (Peak Amplitude = 0 dBm) –40 –20 –50 –60 –40 –70 –80 –60 –90 –100 –80 –110 –120 –100 0.665 0.685 0.705 0.725 0.745 0.765 0.785 0.805 0.825 FREQUENCY (MHz) Figure 79. AD9765 Notch in Missing Bin at 750 kHz Is Down >60 dB –120 (Peak Amplitude = 0 dBm) 4.85 4.90 4.95 5.00 5.05 5.10 5.15 FREQUENCY (MHz) Figure 82. AD9767 Notch in Missing Bin at 5 MHz Is Down >60 dB (Peak Amplitude = 0 dBm) Rev. G | Page 31 of 44 (dBm) 00617-079 (dBm) (dBm) (dBm) 00617-080 00617-082 00617-081 AD9763/AD9765/AD9767 Data Sheet between the two baseband channels. A quadrature mixer QUADRATURE AMPLITUDE MODULATION (QAM) modulates the I and Q components with the in-phase and EXAMPLE USING THE AD9763 quadrature carrier frequency and then sums the two outputs QAM is one of the most widely used digital modulation to provide the QAM signal. schemes in digital communications systems. This modulation technique can be found in FDM as well as spread spectrum 10 DAC (that is, CDMA) based systems. A QAM signal is a carrier DSP frequency that is modulated in both amplitude (that is, AM 0° CARRIER OR TO Σ FREQUENCY ASIC 90° MIXER modulation) and phase (that is, PM modulation). It can be 10 generated by independently modulating two carriers of DAC identical frequency but with a 90° phase difference. This results NYQUIST QUADRATURE FILTERS in an in-phase (I) carrier component and a quadrature (Q) carrier MODULATOR component at a 90° phase shift with respect to the I component. Figure 83. Typical Analog QAM Architecture The I and Q components are then summed to provide a QAM In this implementation, it is much more difficult to maintain signal at the specified carrier frequency. proper gain and phase matching between the I and Q channels. A common and traditional implementation of a QAM modulator The circuit implementation shown in Figure 84 helps improve the is shown in Figure 83. The modulation is performed in the matching between the I and Q channels, and it shows a path for analog domain in which two DACs are used to generate the upconversion using the AD8346 quadrature modulator. The baseband I and Q components. Each component is then typically AD9763 provides both I and Q DACs a common reference that applied to a Nyquist filter before being applied to a quadrature improves the gain matching and stability. RCAL can be used to mixer. The matching Nyquist filters shape and limit each compensate for any mismatch in gain between the two channels. component’s spectral envelope while minimizing intersymbol The mismatch can be attributed to the mismatch between R SET1 interference. The DAC is typically updated at the QAM symbol and R , the effective load resistance of each channel, and/or SET2 rate, or at a multiple of the QAM symbol rate if an interpolating the voltage offset of the control amplifier in each DAC. The filter precedes the DAC. The use of an interpolating filter typically differential voltage outputs of both DACs in the AD9763 are eases the implementation and complexity of the analog filter, which fed into the respective differential inputs of the AD8346 via can be a significant contributor to mismatches in gain and phase matching networks. AVDD ROHDE & SCHWARZ FSEA30B 0.1µF OR EQUIVALENT DCOM1/ DVDD1/ ACOM AVDD RA RA RL RL SPECTRUM ANALYZER VPBF DCOM2 DVDD2 LA I A RB BBIP OUT TEKTRONIX I DAC I AWG2021 VOUT CA CB LATCH DAC WITH RB OPTION 4 + I B BBIN OUT LA RL RL AD9763/ WRT1/IQWRT AD9765/ LOIP CLK1/IQCLK RA RA AD9767 RL PHASE RL LA BBQP I A RB OUT SPLITTER LOIN Q DAC Q CA CB C LATCH DAC FILTER RB I B BBQN OUT LA RL RL WRT2/IQSEL AD8346 VDIFF = 1.82V p-p SLEEP MODE FSADJ1 FSADJ2 REFIO DIFFERENTIAL RLC FILTER ROHDE & SCHWARZ RL = 200Ω 0.1µF SIGNAL GENERATOR 256Ω 256Ω RA = 2500Ω 2kΩ 2kΩ RB = 500Ω 22nF 22nF RP = 200Ω 20kΩ 20kΩ CA = 280pF AVDD CB = 45pF LA = 10µH RA AD976x AD8346 I = 11mA OUTFS RL AVDD = 5.0V NOTES V VCM = 1.2V 1. DAC FULL-SCALE OUTPUT CURRENT = I . MOD OUTFS RB 2. RA, RB, AND RL ARE THIN FILM RESISTOR NETWORKS 0 TO I WITH 0.1% MATCHING, 1% ACCURACY AVAILABLE V OUTFS DAC FROM OHMTEK ORNXXXXD SERIES OR EQUIVALENT. Figure 84. Baseband QAM Implementation Using an AD9763 and an AD8346 Rev. G | Page 32 of 44 PORT Q PORT I DIGITAL INTERFACE 00617-084 00617-083 Data Sheet AD9763/AD9765/AD9767 I and Q digital data can be fed into the AD9763 in two ways. In Distortion in the transmit path can lead to power being transmitted dual-port mode, the digital I information drives one input port, out of the defined band. The ratio of power transmitted in-band to and the digital Q information drives the other input port. If no out-of-band is often referred to as adjacent channel power (ACP). This is a regulatory issue due to the possibility of interference with interpolation filter precedes the DAC, the symbol rate is the rate at which the system clock drives the CLK and WRT pins on the other signals being transmitted by air. Regulatory bodies define a AD9763. In interleaved mode, the digital input stream at Port 1 spectral mask outside of the transmit band, and the ACP must fall contains the I and the Q information in alternating digital words. under this mask. If distortion in the transmit path causes the Using IQSEL and IQRESET, the AD9763 can be synchronized to ACP to be above the spectral mask, filtering or different the I and Q data streams. The internal timing of the AD9763 routes component selection is needed to meet the mask requirements. the selected I and Q data to the correct DAC output. In interleaved Figure 85 shows the results of using the AD9763/AD9765/ mode, if no interpolation filter precedes the AD9763, the symbol AD9767 with the AD8346 to reconstruct a wideband CDMA rate is half that of the system clock driving the digital data stream signal centered at 2.4 GHz. The baseband signal is sampled at and the IQWRT and IQCLK pins on the AD9763. 65 MSPS and has a chip rate of 8 MHz. CDMA –30 –40 Code division multiple access (CDMA) is an air transmit/receive scheme in which the signal in the transmit path is modulated –50 with a pseudorandom digital code (sometimes referred to as the –60 == spreading code). The effect of this is to spread the transmitted –70 signal across a wide spectrum. Similar to a discrete multitone –80 (DMT) waveform, a CDMA waveform containing multiple –90 subscribers can be characterized as having a high peak to average ratio (that is, crest factor), thus demanding highly linear –100 components in the transmit signal path. The bandwidth of the –110 c11 c11 cu1 spectrum is defined by the CDMA standard being used, and in –120 cu1 operation it is implemented by using a spreading code with C0 C0 –130 particular characteristics. CENTER 2.4GHz 3MHz SPAN 30MHz FREQUENCY Figure 85. CDMA Signal, 8 MHz Chip Rate Sampled at 65 MSPS, Recreated at 2.4 GHz, Adjacent Channel Power >60 dBm Rev. G | Page 33 of 44 (dB) 00617-085 AD9763/AD9765/AD9767 Data Sheet EVALUATION BOARD This board allows the user the flexibility to operate the AD9763/ GENERAL DESCRIPTION AD9765/AD9767 in various configurations. Possible output The AD9763/AD9765/AD9767-EBZ is an evaluation board configurations include transformer coupled, resistor terminated, for the AD9763/AD9765/AD9767 10-/12-/14-bit dual DAC. and single-ended and differential outputs. The digital inputs can be Careful attention to layout and circuit design, combined with a used in dual-port or interleaved mode and are designed to be prototyping area, allow the user to easily and effectively evaluate driven from various word generators, with the on-board option the AD9763/AD9765/AD9767 in any application where a high to add a resistor network for proper load termination. When resolution, high speed conversion is required. operating the AD9763/AD9765/AD9767, best performance is obtained by running the digital supply (DVDD1/DVDD2) at 3.3 V and the analog supply (AVDD) at 5 V. SCHEMATICS RED RED L1 L2 DVDDIN 1 DVDD AVDDIN 3 AVDD TB1 TB1 BEAD BEAD C9 C10 DCASE DCASE VAL VAL VOLT VOLT BLK BLK BLK BLK BLK BLK 2 4 TB1 TB1 BLK BLK DGND AGND 1 1 RCO M RCO M 1 RCO M 1 RCO M 22 22 R1 R1 22 R1 22 R1 2 2 2 2 INP31 INP23 INP9 INP1 R2 R2 R2 R2 3 3 3 3 INP32 INP24 INP10 INP2 R3 R3 R3 R3 4 4 4 4 INP33 INP25 INP11 INP3 R4 R4 R4 R4 5 5 5 5 INP34 INP26 INP12 INP4 R5 R5 R5 R5 6 6 6 6 INP35 INP27 INP13 INP5 R6 R6 R6 R6 7 7 7 7 INP36 INP28 INP14 INP6 R7 R7 R7 R7 8 8 8 8 INP29 INP7 R8 R8 R8 R8 9 9 9 9 INCK2 INP30 INCK1 INP8 R9 R9 R9 R9 10 10 10 10 RP15 RP10 RP9 RP16 Figure 86. Power Decoupling and Clocks on AD9763/AD9765/AD9767 Evaluation Board (1) Rev. G | Page 34 of 44 00617-086 Data Sheet AD9763/AD9765/AD9767 B C 2 1 A 3 Figure 87. Power Decoupling and Clocks on AD9763/AD9765/AD9767 Evaluation Board (2) Rev. G | Page 35 of 44 R16 R19 1K 1K JP9 DVDD RC0603 RC0603 JP2 DCLKIN1 DCLKIN2 DVDD DVDD DVDD R17 1K R1 8 1K C8 C7 DVDD CC0805 CC0805 RC0603 RC0603 .1UF .01UF C33 C34 SW1 CC0805 CC0805 .1UF .01UF T1-1TCUP C19 .1 4 10 7 6 1 +IN 1 PRE PRE +IN 3 5 11 9 J Q J Q JP1 5 2 15 U2 10 C18 .1 OUT U2 1 13 U6 U6 OUT CLK CLK 4 3 SO16 T3 -IN 26 12 7 SO16 K Q_ K Q_ JP13 -IN 8 DVDD DS90LV048B 2 CLR CLR DS90LV048B 15 SN74F112 14 R6 3 50 5 SN74F112 +IN DGND;8 DGND;8 U2 11 RC0603 DVDD;16 DVDD;16 OUT JP17 SO16 SW2 WHT -IN 6 DS90LV048B SMA200UP JP14 S1 3 WRT1IN +IN DGND;3,4,5 JP16 IQWRT U2 14 OUT DVDD SO16 SMA200UP -IN JP5 4 DS90LV048B WHT CLK1IN S2 1QCLK DGND;3,4,5 DVDD SMA200UP JP4 WHT CLK2IN S3 R30 VAL RESET /2 CLOCK DIVIDER DGND;3,4,5 16 13 SMA200UP JP3 EN VCC DVDD WHT WRT2IN S4 U2 IQSEL 9 12 DGND;3,4,5 EN GND SO16 R1 R2 R3 R4 DS90LV048B 50 50 50 50 WRT1 CLK1 CLK2 WRT2 WHT SLEEP SLEEP R13 50 RC0805 RC0805 CC0805 RC0805 CC0805 RC0805 RC0805 RC0603 B 2 C 3 1 A 00617-091 AD9763/AD9765/AD9767 Data Sheet L6 DNP R23 51 C31 DNP O2N LC0805 RC0603 DNP DNP JP19 CC0805 CC0805 C24 C23 L5 DNP R21 51 R22 DNP O2P LC0805 RC0603 RC0603 MODULATED OUTPUT AGND2;3,4,5 SMAEDGE R27 0 C28 AVDD2 J1 RC0603 .1UF 100PF C29 C20 CC0603 CC0603 BCASE AVDD2 10UF 2 C27 2 10V TP6 RED 100PF AVDD2 AGND2;17 2 R28 1K AGND2 TP5 JP18 BLK .1UF LOCAL OSC INPUT 2 CC0603 AGND2;3,4,5 SMAEDGE C30 R29 0 ETC1-1-13 3 4 J2 RC0603 SP 2 C26 100PF 1 5 T4 R20 C25 100PF 50 2 JP21 2 JP22 2 L4 DNP R26 51 C32 DNP O1N RC0603 LC0805 DNP DNP JP20 CC0805 CC0805 C22 C21 L3 DNP R25 51 R24 DNP O1P RC0603 RC0603 LC0805 Figure 88. Modulator on AD9763/AD9765/AD9767 Evaluation Board Rev. G | Page 36 of 44 1 16 IBBP QBBP 2 15 IBBN QBBN 3 14 G1A G4B 4 13 G1B G4A 5 12 LOIN VPS2 6 11 U3 LOIP VOUT 7 10 VPS1 G3 AD834 9 8 9 CC0603 CC0603 ENBL G2 RC0603 CC0603 CC0603 CC0603 RC0603 00617-092 Data Sheet AD9763/AD9765/AD9767 RIBBON RA Figure 89. Digital Input Signaling (1) Rev. G | Page 37 of 44 R62 R61 R60 R59 R58 R57 R56 R55 R54 R53 R52 R51 R50 R49 R33 470 470 470 470 470 470 470 470 470 470 470 470 470 470 470 P1 INP1 2 1 1 16 INP2 RP5 10 4 3 2 15 INP3 RP5 10 65 3 14 INP4 RP5 10 87 4 13 INP5 DUTP1 10 9 RP5 10 5 12 INP6 RP5 10 DUTP2 12 11 6 11 INP7 RP5 10 DUTP3 14 13 7 10 INP8 RP5 10 DUTP4 16 15 8 9 INP9 DUTP5 18 17 RP5 10 116 INP10 RP6 10 DUTP6 20 19 2 15 INP11 RP6 10 DUTP7 22 21 314 INP12 RP6 10 DUTP8 24 23 4 13 INP13 DUTP9 26 25 RP6 10 512 INP14 RP6 10 DUTP10 28 27 6 11 RP6 10 DUTP11 30 29 DUTP12 32 31 INCK1 DUTP13 34 33 8 9 RP6 10 DUTP14 36 35 DCLKIN1 38 37 40 39 SPARES 10 7 10 RP6 HDR040RA HDR040RA RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 00617-093 AD9763/AD9765/AD9767 Data Sheet RIBBON RA Figure 90. Digital Input Signaling (2) Rev. G | Page 38 of 44 P2 R41 R42 2 1 R34 R35 R48 R36 R37 R47 R38 R39 R46 R45 R44 R43 R40 470 470 470 470 470 470 470 470 470 470 470 470 470 470 470 4 3 6 5 8 7 10 9 12 11 INP23 DUTP23 14 13 116 RP7 10 INP24 16 15 DUTP24 2 15 INP25 RP7 10 DUTP25 18 17 314 INP26 RP7 10 DUTP26 20 19 4 13 INP27 RP7 10 DUTP27 22 21 512 RP7 10 INP28 DUTP28 24 23 6 11 RP7 10 INP29 DUTP29 26 25 710 RP7 10 INP30 28 27 DUTP30 8 9 INP31 RP7 10 DUTP31 30 29 116 INP32 RP8 10 DUTP32 32 31 2 15 INP33 RP8 10 DUTP33 34 33 314 INP34 RP8 10 INCK2 DUTP34 36 35 4 13 RP8 10 INP35 8 9 RP8 10 DUTP35 38 37 512 RP8 10 INP36 40 39 DUTP36 6 11 RP8 10 DCLKIN2 HDR040RA HDR040RA SPARES 10 7 10 RP8 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 00617-087 Data Sheet AD9763/AD9765/AD9767 Figure 91. Device Under Test/Analog Output Signal Conditioning Rev. G | Page 39 of 44 R31 10 BL1 DVDD RC0805 ACOM JP15 AGND;3,4,5 1 3 JP23 SMA200UP A B C1 C2 C3 T5 WHT 2 34 CC0805 CC0805 CC0805 R11 OUT1 AVDD 2 VAL .01UF 5 .1UF VAL S6 1 6 R5 R6 O1P C5 T1-1TCUP 50 50 C4 CC0805 MODE O1N JP8 CC0805 13 A B DVDD 10PF 10PF JP6 JP7 2 1 48 DUTP1 DB13P1MSB MODE R9 1.92K 2 47 WHT DUTP2 DB12P1 AVDD BL2 RC0805 3 46 DUTP3 DB11P1 IA1 REFIO 4 45 DUTP4 DB10P1 IB1 C16 R15 256 22NF 5 44 WHT DUTP5 DB9P1 FSADJ1 RC0805 6 43 DUTP6 DB8P1 REFIO 7 42 C17 DUTP7 DB7P1 ACOM1 R14 256 22NF C14 8 41 DUTP8 DB6P1 FSADJ2 RC0805 CC0805 9 40 DUTP9 DB5P1 IB2 .1UF R10 1.92K 10 39 JP10 DUTP10 DB4P1 IA2 11 38 C6 RC0805 WHT DUTP11 DB3P1 ACOM C15 JP12 JP11 12 37 CC0805 DUTP12 DB2P1 SLEEP SLEEP CC0805 U1 10PF 13 36 10PF DUTP13 DB1P1 DB0P2 DUTP36 AD9763/65/67 BL3 14 35 DUTP14 DB0P1 DB1P2 DUTP35 15 34 DCOM1 DB2P2 DUTP34 O2N R7 R8 16 33 50 DVDD1 DB3P2 DUTP33 50 T6 O2P 17 32 34 WRT1 WRT1 DB4P2 DUTP32 R32 10 18 31 2 5 CLK1 CLK1 DB5P2 DUTP31 R12 19 30 1 6 RC0805 VAL CLK2 CLK2 DB6P2 DUTP30 AGND;3,4,5 20 29 SMA200UP WRT2 WRT2 DB7P2 DUTP29 JP24 T1-1TCUP WHT 21 28 DCOM2 DB8P2 DUTP28 OUT2 22 27 DVDD2 DB9P2 DUTP27 S11 23 26 DUTP23 DB13P2MSB DB10P2 DUTP26 BL4 24 25 DUTP24 DB12P2 DB11P2 DUTP25 AVDD C11 C12 C13 .01UF .1UF CC0805 CC0805 CC0805 VAL RC0805 RC0805 RC0805 RC0805 RC07CUP RC07CUP CC0805 CC0805 00617-088 AD9763/AD9765/AD9767 Data Sheet EVALUATION BOARD LAYOUT Figure 92. Assembly, Top Side Rev. G | Page 40 of 44 00617-089 Data Sheet AD9763/AD9765/AD9767 Figure 93. Assembly, Bottom Side Rev. G | Page 41 of 44 00617-090 AD9763/AD9765/AD9767 Data Sheet OUTLINE DIMENSIONS 9.20 9.00 SQ 0.75 1.60 8.80 0.60 MAX 0.45 48 37 1 36 PIN 1 7.20 TOP VIEW 7.00 SQ 1.45 (PINS DOWN) 0.20 6.80 1.40 0.09 1.35 7° 3.5° 12 25 0.15 0° 13 24 SEATING 0.05 0.08 0.27 PLANE VIEW A 0.50 COPLANARITY 0.22 BSC LEAD PITCH 0.17 VIEW A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BBC Figure 94. 48-Lead Low Profile Quad Flat Package [LQFP] (ST-48) Dimensions shown in millimeters ORDERING GUIDE 1 Model Temperature Range Package Description Package Option AD9763ASTZ –40°C to +85°C 48-Lead Low Profile Quad Flat Package [LQFP] ST-48 AD9763ASTZRL –40°C to +85°C 48-Lead Low Profile Quad Flat Package [LQFP] ST-48 AD9763-EBZ Evaluation Board AD9765AST –40°C to +85°C 48-Lead Low Profile Quad Flat Package [LQFP] ST-48 AD9765ASTRL –40°C to +85°C 48-Lead Low Profile Quad Flat Package [LQFP] ST-48 AD9765ASTZ –40°C to +85°C 48-Lead Low Profile Quad Flat Package [LQFP] ST-48 AD9765ASTZRL –40°C to +85°C 48-Lead Low Profile Quad Flat Package [LQFP] ST-48 AD9765-EBZ Evaluation Board AD9767ASTZ –40°C to +85°C 48-Lead Low Profile Quad Flat Package [LQFP] ST-48 AD9767ASTZRL –40°C to +85°C 48-Lead Low Profile Quad Flat Package [LQFP] ST-48 AD9767-EBZ Evaluation Board 1 Z = RoHS Compliant Part. Rev. G | Page 42 of 44 051706-A Data Sheet AD9763/AD9765/AD9767 NOTES Rev. G | Page 43 of 44 AD9763/AD9765/AD9767 Data Sheet NOTES ©1999-2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00617-0-8/11(G) Rev. G | Page 44 of 44