ANALOG DEVICES AD9764

14-Bit, 125 MSPS a ® TxDAC D/A Converter AD9764 FUNCTIONAL BLOCK DIAGRAM FEATURES Member of Pin-Compatible TxDAC Product Family +5V 125 MSPS Update Rate 0.1mF 14-Bit Resolution Excellent SFDR and IMD REFLO COMP1 AVDD ACOM Differential Current Outputs: 2 mA to 20 mA +1.20V REF AD9764 50pF 0.1mF Power Dissipation: 190 mW @ 5 V to 45 mW @ 3 V REFIO 0.1mF CURRENT COMP2 Power-Down Mode: 25 mW @ 5 V FS ADJ SOURCE ARRAY On-Chip 1.20 V Reference R SET Single +5 V or +3 V Supply Operation +5V DVDD I OUTA Packages: 28-Lead SOIC and TSSOP SEGMENTED LSB I DCOM OUTB SWITCHES SWITCHES Edge-Triggered Latches CLOCK CLOCK LATCHES APPLICATIONS SLEEP Communication Transmit Channel: DIGITAL DATA INPUTS (DB13–DB0) Basestations ADSL/HFC Modems Differential current outputs are provided to support single- Instrumentation ended or differential applications. Matching between the two current outputs ensures enhanced dynamic performance in a PRODUCT DESCRIPTION differential output configuration. The current outputs may be The AD9764 is the 14-bit resolution member of the TxDAC tied directly to an output resistor to provide two complemen- series of high performance, low power CMOS digital-to-analog tary, single-ended voltage outputs or fed directly into a trans- converters (DACs). The TxDAC family, which consists of pin former. The output voltage compliance range is 1.25 V. compatible 8-, 10-, 12-, and 14-bit DACs, is specifically opti- mized for the transmit signal path of communication systems. The on-chip reference and control amplifier are configured for All of the devices share the same interface options, small outline maximum accuracy and flexibility. The AD9764 can be driven package and pinout, providing an upward or downward compo- by the on-chip reference or by a variety of external reference nent selection path based on performance, resolution and cost. voltages. The internal control amplifier, which provides a wide The AD9764 offers exceptional ac and dc performance while (>10:1) adjustment span, allows the AD9764 full-scale current supporting update rates up to 125 MSPS. to be adjusted over a 2 mA to 20 mA range while maintaining excellent dynamic performance. Thus, the AD9764 may operate The AD9764’s flexible single-supply operating range of 2.7 V to at reduced power levels or be adjusted over a 20 dB range to 5.5 V and low power dissipation are well suited for portable and provide additional gain ranging capabilities. low power applications. Its power dissipation can be further reduced to a mere 45 mW with a slight degradation in performance The AD9764 is available in 28-lead SOIC and TSSOP packages. by lowering the full-scale current output. Also, a power-down It is specified for operation over the industrial temperature range. mode reduces the standby power dissipation to approximately PRODUCT HIGHLIGHTS 25 mW. 1. The AD9764 is a member of the TxDAC product family that The AD9764 is manufactured on an advanced CMOS process. provides an upward or downward component selection path A segmented current source architecture is combined with a based on resolution (8 to 14 bits), performance and cost. proprietary switching technique to reduce spurious components 2. Manufactured on a CMOS process, the AD9764 uses a pro- and enhance dynamic performance. Edge-triggered input prietary switching technique that enhances dynamic perfor- latches and a 1.2 V temperature compensated bandgap refer- mance beyond that previously attainable by higher power/cost ence have been integrated to provide a complete monolithic bipolar or BiCMOS devices. DAC solution. Flexible supply options support +3 V and +5 V 3. On-chip, edge-triggered input CMOS latches readily interface CMOS logic families. to +3 V and +5 V CMOS logic families. The AD9764 can The AD9764 is a current-output DAC with a nominal full-scale support update rates up to 125 MSPS. output current of 20 mA and > 100 kW output impedance. 4. A flexible single-supply operating range of 2.7 V to 5.5 V, and TxDAC is a registered trademark of Analog Devices, Inc. a wide full-scale current adjustment span of 2 mA to 20 mA, allows the AD9764 to operate at reduced power levels. 5. The current output(s) of the AD9764 can be easily config- REV. B ured for various single-ended or differential circuit topologies. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: http://www.analog.com otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 1999 AD9764–SPECIFICATIONS DC SPECIFICATIONS (T to T , AVDD = +5 V, DVDD = +5 V, I = 20 mA, unless otherwise noted) MIN MAX OUTFS Parameter Min Typ Max Units RESOLUTION 14 Bits 1 DC ACCURACY Integral Linearity Error (INL) = +25°C –4.5–2.5 +4.5 LSB T A to T –6.5 +6.5 LSB T MIN MAX Differential Nonlinearity (DNL) = +25°C –2.5–1.5 +2.5 LSB T A T to T –4.5 +4.5 LSB MIN MAX ANALOG OUTPUT Offset Error –0.025 +0.025 % of FSR Gain Error (Without Internal Reference) –2–1 +2 % of FSR (With Internal Reference) –7–1 +7 % of FSR Gain Error 2 2.0 20.0 mA Full-Scale Output Current Output Compliance Range –1.0 1.25 V Output Resistance 100 kW Output Capacitance 5 pF REFERENCE OUTPUT Reference Voltage 1.08 1.20 1.32 V 3 Reference Output Current 100 nA REFERENCE INPUT Input Compliance Range 0.1 1.25 V Reference Input Resistance 1 MW 4 Small Signal Bandwidth (w/o C ) 1.4 MHz COMP1 TEMPERATURE COEFFICIENTS Offset Drift 0 ppm of FSR/°C Gain Drift (Without Internal Reference)–50 ppm of FSR/°C Gain Drift (With Internal Reference)–100 ppm of FSR/°C Reference Voltage Drift–50 ppm/°C POWER SUPPLY Supply Voltages 5 AVDD 2.7 5.0 5.5 V DVDD 2.7 5.0 5.5 V Analog Supply Current (I)2530mA AVDD 6 Digital Supply Current (I ) 1.5 4 mA DVDD Supply Current Sleep Mode (I ) 5.0 8.5 mA AVDD 6 Power Dissipation (5 V, I = 20 mA) 133 170 mW OUTFS 7 Power Dissipation (5 V, I = 20 mA) 190 mW OUTFS 7 Power Dissipation (3 V, I = 2 mA) 45 mW OUTFS 8 Power Supply Rejection Ratio —AVDD –0.4 +0.4 % of FSR/V 8 Power Supply Rejection Ratio —DVDD –0.025 +0.025 % of FSR/V OPERATING RANGE –40 +85 °C NOTES 1 Measured at I , driving a virtual ground. OUTA 2 Nominal full-scale current, I , is 32 · the I current. OUTFS REF 3 Use an external buffer amplifier to drive any external load. 4 Reference bandwidth is a function of external cap at COMP1 pin and signal level. 5 For operation below 3 V, it is recommended that the output current be reduced to 12 mA or less to maintain optimum performance. 6 Measured at f = 25 MSPS and f = 1.0 MHz. CLOCK OUT 7 Measured as unbuffered voltage output with I = 20 mA and 50 W R at I and I , f = 100 MSPS and f = 40 MHz. OUTFS LOAD OUTA OUTB CLOCK OUT 8 –5% Power supply variation. Specifications subject to change without notice. –2– REV. B AD9764 (T to T , AVDD = +5 V, DVDD = +5 V, I = 20 mA, Differential Transformer Coupled Output, MIN MAX OUTFS 50 V Doubly Terminated, unless otherwise noted) DYNAMIC SPECIFICATIONS Parameter Min Typ Max Units DYNAMIC PERFORMANCE Maximum Output Update Rate (f ) 125 MSPS CLOCK 1 Output Settling Time (t ) (to 0.1%) 35 ns ST Output Propagation Delay (t)1 ns PD Glitch Impulse 5 pV-s 1 Output Rise Time (10% to 90%) 2.5 ns 1 Output Fall Time (10% to 90%) 2.5 ns Output Noise (I = 20 mA) 50 pA/√Hz OUTFS Output Noise (I = 2 mA) 30 pA/√Hz OUTFS AC LINEARITY Spurious-Free Dynamic Range to Nyquist f = 25 MSPS; f = 1.00 MHz CLOCK OUT 0 dBFS Output = +25°C 75 82 dBc T A to T 73 dBc T MIN MAX –6 dBFS Output 85 dBc –12 dBFS Output 77 dBc –18 dBFS Output 70 dBc = 50 MSPS; f = 1.00 MHz 80 dBc f CLOCK OUT = 50 MSPS; f = 2.51 MHz 77 dBc f CLOCK OUT = 50 MSPS; f = 5.02 MHz 70 dBc f CLOCK OUT = 50 MSPS; f = 20.2 MHz 58 dBc f CLOCK OUT Spurious-Free Dynamic Range within a Window = 25 MSPS; f = 1.00 MHz; 2 MHz Span f CLOCK OUT = +25°C 78 89 dBc T A to T 76 dBc T MIN MAX = 50 MSPS; f = 5.02 MHz; 2 MHz Span 84 dBc f CLOCK OUT = 100 MSPS; f = 5.04 MHz; 4 MHz Span 84 dBc f CLOCK OUT Total Harmonic Distortion = 25 MSPS; f = 1.00 MHz f CLOCK OUT = +25°C –78 –74 dBc T A to T –72 dBc T MIN MAX = 50 MHz; f = 2.00 MHz –75 dBc f CLOCK OUT = 100 MHz; f = 2.00 MHz –75 dBc f CLOCK OUT Multitone Power Ratio (Eight Tones at 110 kHz Spacing) = 20 MSPS; f = 2.00 MHz to 2.99 MHz f CLOCK OUT 0 dBFS Output 73 dBc –6 dBFS Output 76 dBc –12 dBFS Output 73 dBc –18 dBFS Output 64 dBc NOTES 1 Measured single-ended into 50W load. Specifications subject to change without notice. REV. B –3– AD9764 DIGITAL SPECIFICATIONS Parameter Min Typ Max Units DIGITAL INPUTS Logic “1” Voltage @ DVDD = +5 V 3.5 5 V Logic “1” Voltage @ DVDD = +3 V 2.1 3 V Logic “0” Voltage @ DVDD = +5 V 0 1.3 V Logic “0” Voltage @ DVDD = +3 V 0 0.9 V Logic “1” Current –10 +10mA Logic “0” Current –10 +10mA Input Capacitance 5 pF ) 2.0 ns Input Setup Time (t S ) 1.5 ns Input Hold Time (t H Latch Pulsewidth (t ) 3.5 ns LPW Specifications subject to change without notice. DB0–DB13 t t S H CLOCK t LPW t PD t ST IOUTA OR 0.1% IOUTB 0.1% Figure 1. Timing Diagram ABSOLUTE MAXIMUM RATINGS* ORDERING GUIDE With Temperature Package Package Parameter Respect to Min Max Units Model Range Description Options* AVDD ACOM –0.3 +6.5 V AD9764AR –40°C to +85°C 28-Lead 300 mil SOIC R-28 DVDD DCOM –0.3 +6.5 V AD9764ARU –40°C to +85°C 28-Lead TSSOP RU-28 ACOM DCOM –0.3 +0.3 V AD9764-EB Evaluation Board AVDD DVDD –6.5 +6.5 V *R = Small Outline IC, RU = TSSOP. CLOCK, SLEEP DCOM –0.3 DVDD + 0.3 V Digital Inputs DCOM –0.3 DVDD + 0.3 V THERMAL CHARACTERISTICS I , I ACOM –1.0 AVDD + 0.3 V OUTA OUTB Thermal Resistance COMP1, COMP2 ACOM –0.3 AVDD + 0.3 V 28-Lead 300 mil SOIC REFIO, FSADJ ACOM –0.3 AVDD + 0.3 V q = 71.4°C/W JA REFLO ACOM –0.3 +0.3 V q = 23°C/W JC Junction Temperature +150 °C 28-Lead TSSOP Storage Temperature –65 +150 °C q = 97.9°C/W JA Lead Temperature q = 14.0°C/W JC (10 sec) +300 °C *Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD9764 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD ESD SENSITIVE DEVICE precautions are recommended to avoid performance degradation or loss of functionality. –4– REV. B AD9764 PIN CONFIGURATION 1 (MSB) DB13 28 CLOCK DB12 2 27 DVDD DB11 3 DCOM 26 DB10 4 25 NC DB9 AVDD 5 24 AD9764 DB8 6 23 COMP2 TOP VIEW (Not to Scale) DB7 7 I 22 OUTA 8 DB6 21 I OUTB DB5 9 20 ACOM DB4 10 19 COMP1 DB3 11 18 FS ADJ DB2 REFIO 12 17 DB1 13 16 REFLO DB0 SLEEP 14 15 NC = NO CONNECT PIN FUNCTION DESCRIPTIONS Pin No. Name Description 1 DB13 Most Significant Data Bit (MSB). 2–13 DB12–DB1 Data Bits 1–12. 14 DB0 Least Significant Data Bit (LSB). 15 SLEEP Power-Down Control Input. Active High. Contains active pull-down circuit; it may be left unterminated if not used. 16 REFLO Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal reference. 17 REFIO Reference Input/Output. Serves as reference input when internal reference disabled (i.e., Tie REFLO to AVDD). Serves as 1.2 V reference output when internal reference activated (i.e., Tie REFLO to ACOM). Requires 0.1mF capacitor to ACOM when internal reference activated. 18 FS ADJ Full-Scale Current Output Adjust. 19 COMP1 Bandwidth/Noise Reduction Node. Add 0.1 mF to AVDD for optimum performance. 20 ACOM Analog Common. 21 I Complementary DAC Current Output. Full-scale current when all data bits are 0s. OUTB 22 I DAC Current Output. Full-scale current when all data bits are 1s. OUTA 23 COMP2 Internal Bias Node for Switch Driver Circuitry. Decouple to ACOM with 0.1 mF capacitor. 24 AVDD Analog Supply Voltage (+2.7 V to +5.5 V). 25 NC No Internal Connection. 26 DCOM Digital Common. 27 DVDD Digital Supply Voltage (+2.7 V to +5.5 V). 28 CLOCK Clock Input. Data latched on positive edge of clock. REV. B –5– AD9764 DEFINITIONS OF SPECIFICATIONS Power Supply Rejection Linearity Error (Also Called Integral Nonlinearity or INL) The maximum change in the full-scale output as the supplies Linearity error is defined as the maximum deviation of the are varied over a specified range. actual analog output from the ideal output, determined by a Settling Time straight line drawn from zero to full scale. The time required for the output to reach and remain within a Differential Nonlinearity (or DNL) specified error band about its final value, measured from the DNL is the measure of the variation in analog value, normalized start of the output transition. to full scale, associated with a 1 LSB change in digital input Glitch Impulse code. Asymmetrical switching times in a DAC give rise to undesired Offset Error output transients that are quantified by a glitch impulse. It is The deviation of the output current from the ideal of zero is specified as the net area of the glitch in pV-s. called offset error. For I , 0 mA output is expected when the OUTA Spurious-Free Dynamic Range inputs are all 0s. For I , 0 mA output is expected when all OUTB The difference, in dB, between the rms amplitude of the output inputs are set to 1s. signal and the peak spurious signal over the specified bandwidth. Gain Error Total Harmonic Distortion The difference between the actual and ideal output span. The THD is the ratio of the sum of the rms value of the first six actual span is determined by the output when all inputs are set harmonic components to the rms value of the measured output to 1s minus the output when all inputs are set to 0s. signal. It is expressed as a percentage or in decibels (dB). Output Compliance Range Multitone Power Ratio The range of allowable voltage at the output of a current-output The spurious-free dynamic range for an output containing mul- DAC. Operation beyond the maximum compliance limits may tiple carrier tones of equal amplitude. It is measured as the cause either output stage saturation or breakdown, resulting in difference between the rms amplitude of a carrier tone to the nonlinear performance. peak spurious signal in the region of a removed tone. Temperature Drift Temperature drift is specified as the maximum change from the ambient (+25°C) value to the value at either T or T . For MIN MAX offset and gain drift, the drift is reported in ppm of full-scale range (FSR) per degree C. For reference drift, the drift is reported in ppm per degree C. +5V 0.1mF REFLO COMP1 AVDD ACOM +1.20V REF AD9764 50pF 0.1mF REFIO PMOS 0.1mF COMP2 CURRENT SOURCE FS ADJ ARRAY MINI-CIRCUITS R SET T1-1T 2kV DVDD TO HP3589A +5V I OUTA SPECTRUM/ SEGMENTED SWITCHES LSB I 100V NETWORK DCOM OUTB FOR DB13–DB5 SWITCHES ANALYZER 50V INPUT CLOCK LATCHES DVDD 50V SLEEP 50V DCOM 20pF RETIMED 50V 20pF CLOCK DIGITAL OUTPUT* DATA CLOCK * AWG2021 CLOCK RETIMED OUTPUT SUCH THAT DIGITAL DATA LECROY 9210 TEKTRONIX TRANSITIONS ON FALLING EDGE PULSE GENERATOR AWG-2021 OF 50% DUTY CYCLE CLOCK. Figure 2. Basic AC Characterization Test Setup –6– REV. B AD9764 Typical AC Characterization Curves (AVDD = +5 V, DVDD = +3 V, I = 20 mA, 50 V Doubly Terminated Load, Differential Output, T = +258C, SFDR up to Nyquist, unless otherwise noted) OUTFS A 90 90 90 –6dBFS –6dBFS 85 85 85 5 MSPS 0dBFS 80 –12dBFS 80 80 25 MSPS 75 75 75 50 MSPS –12dBFS 70 70 70 65 100 MSPS 65 65 0dBFS 60 60 60 55 55 55 50 50 50 45 45 45 40 40 40 0.1 1 10 100 0 0.5 1.0 1.5 2.0 2.5 02 46 810 12 FREQUENCY – MHz FREQUENCY – MHz FREQUENCY – MHz Figure 3. SFDR vs. f @ 0 dBFS Figure 4. SFDR vs. f @ 5 MSPS Figure 5. SFDR vs. f @ 25 MSPS OUT OUT OUT 90 90 90 85 85 85 –6dBFS 10mA @ 5V 80 80 20mA @ 5V 80 –12dBFS 5mA @ 5V 75 75 –6dBFS 75 70 70 –12dBFS 65 65 70 60 60 0dBFS 65 20mA @ 3V 55 55 0dBFS 5mA @ 3V 60 50 50 10mA @ 3V 55 45 45 50 40 40 0.0 2.0 4.0 6.0 8.0 10.0 05 10 15 20 25 010 20 30 40 50 FREQUENCY – MHz FREQUENCY – MHz FREQUENCY – MHz Figure 6. SFDR vs. f @ 50 MSPS Figure 7. SFDR vs. f @100 MSPS Figure 8. SFDR vs. f and OUT OUT OUT I @ 25 MSPS and 0 dBFS OUTFS 90 90 90 455kHz @ 5 MSPS 3.38/3.63MHz @ 25 MSPS 1MHz @ 5 MSPS 2.27MHz @ 25 MSPS 80 80 80 0.675/0.725MHz @ 5 MSPS 5MHz @ 25 MSPS 70 70 70 9.09MHz @ 100 MSPS 60 60 60 13.5/14.5MHz @ 100 MSPS 20MHz @ 100 MSPS 4.55MHz @ 50 MSPS 10MHz @ 50 MSPS 6.75/7.25 @ 50 MSPS 50 50 50 –30 –25 –20 –15 –10 –5 0 –30 –25 –20 –15 –10 –5 0 –30 –25 –20 –15 –10 –5 0 A – dBFS A – dBFS A – dBFS OUT OUT OUT Figure 9. Single-Tone SFDR vs. A Figure 10. Single-Tone SFDR vs. Figure 11. Dual-Tone SFDR vs. A OUT OUT @ f = f /11 A @ f = f /5 @ f = f /7 OUT CLOCK OUT OUT CLOCK OUT CLOCK REV. B –7– SFDR – dBc SFDR – dBc SFDR – dBc SFDR – dBc SFDR – dBc SFDR – dBc SFDR – dBc SFDR – dBc SFDR – dBc AD9764 80 –70 85 I @ –6dBFS DIFF I = 20mA, OUTFS –75 80 DVDD = +3V 2ND HARMONIC I = 20mA, OUTFS 70 DVDD = +5V –80 75 I = 10mA, OUTFS I @ –6dBFS 3RD HARMONIC A DVDD = +3V I @ 0dBFS DIFF I = 10mA, –85 70 OUTFS DVDD = +5V 60 4TH HARMONIC I = 5mA, OUTFS –90 65 I @ 0dBFS A DVDD = +3V I = 5mA, OUTFS DVDD = +5V 50 –95 60 1 10 100 000.0E+0 40.0E+6 80.0E+6 120.0E+6 0 10 20 30 40 50 60 70 80 90 100 f – MSPS OUTPUT FREQUENCY – MHz CLOCK Figure 12. THD vs. f @ Figure 13. SNR vs. f @ f = Figure 14. Differential vs. Single- CLOCK CLOCK OUT f = 2 MHz 2.0 MHz Ended SFDR vs. f @ 50 MSPS OUT OUT 2.0 2.0 80 1.5 1.5 75 2.5MHz 1.0 1.0 70 0.5 0.5 0.0 65 10MHz –0.5 0.0 60 –1.0 –0.5 55 –1.5 40MHz –1.0 50 –2.0 0 4000 8000 12000 16000 0 4000 8000 12000 16000 –40 –20 0 20 40 60 80 CODE CODE TEMPERATURE – 8C Figure 15. Typical INL Figure 16. Typical DNL Figure 17. SFDR vs. Temperature @ 100 MSPS, 0 dBFS 0 0 0 f = 50MSPS f = 50MSPS CLK f = 50MSPS CLK CLK –10 –10 –10 f = 6.25MHz f = 6.75MHz OUT1 f = 1.25MHz OUT1 OUT f = 6.75MHz –20 OUT2 f = 7.25MHz SFDR = 78dBc –20 –20 OUT2 f = 7.25MHz AMPLITUDE = 0dBFS SFDR = 69dBc OUT3 –30 f = 7.75MHz AMPLITUDE = 0dBFS –30 –30 OUT4 –40 SFDR = 66dBc –40 –40 AMPLITUDE = 0dBFS –50 –50 –50 –60 –60 –60 –70 –70 –70 –80 –80 –80 –90 –90 –100 –90 000.0E+0 7.5E+6 15.0E+6 22.5E+6 0E+0 5E+6 10E+6 15E+6 20E+6 25E+6 000.0E+0 7.5E+6 15.0E+6 22.5E+6 Figure 18. Single-Tone SFDR Figure 19. Dual-Tone SFDR Figure 20. Four-Tone SFDR –8– REV. B ERROR – LSB 10dB – Div dBc 10dB – Div ERROR – LSB SNR – dB 10dB – Div SFDR – dBc SFDR – dBc AD9764 +5V 0.1mF REFLO COMP1 AVDD ACOM +1.20V REF AD9764 50pF V REFIO REFIO PMOS 0.1mF COMP2 I CURRENT SOURCE REF FS ADJ 0.1mF ARRAY V = V – V R DIFF OUTA OUTB SET 2kV +5V DVDD I I OUTA OUTA V LSB OUTA SEGMENTED SWITCHES I I DCOM OUTB OUTB FOR DB13–DB5 SWITCHES V OUTB R LOAD CLOCK 50V R CLOCK LOAD LATCHES 50V SLEEP DIGITAL DATA INPUTS (DB13–DB0) Figure 21. Functional Block Diagram FUNCTIONAL DESCRIPTION I = (16383 – DAC CODE)/16384 · I (2) OUTB OUTFS Figure 21 shows a simplified block diagram of the AD9764. The where DAC CODE = 0 to 16383 (i.e., Decimal Representation). AD9764 consists of a large PMOS current source array that is As mentioned previously, I is a function of the reference OUTFS capable of providing up to 20 mA of total current. The array current I , which is nominally set by a reference voltage REF is divided into 31 equal currents that make up the five most V and external resistor R . It can be expressed as: REFIO SET significant bits (MSBs). The next four bits or middle bits consist of 15 equal current sources whose value is 1/16th of an MSB I = 32 · I (3) OUTFS REF current source. The remaining LSBs are binary weighted frac- where I = V /R (4) REF REFIO SET tions of the middle bits current sources. Implementing the The two current outputs will typically drive a resistive load middle and lower bits with current sources, instead of an R-2R directly or via a transformer. If dc coupling is required, I OUTA ladder, enhances its dynamic performance for multitone or low and I should be directly connected to matching resistive OUTB amplitude signals and helps maintain the DAC’s high output loads, R , that are tied to analog common, ACOM. Note LOAD impedance (i.e., >100 kW). that R may represent the equivalent load resistance seen by LOAD All of these current sources are switched to one or the other of I or I as would be the case in a doubly terminated OUTA OUTB or I ) via PMOS differen- the two output nodes (i.e., I OUTA OUTB 50W or 75W cable. The single-ended voltage output appearing tial current switches. The switches are based on a new architec- at the I and I nodes is simply: OUTA OUTB ture that drastically improves distortion performance. This new V = I · R (5) OUTA OUTA LOAD switch architecture reduces various timing errors and provides matching complementary drive signals to the inputs of the dif- V = I · R (6) OUTB OUTB LOAD ferential current switches. Note that the full-scale value of V and V should not OUTA OUTB The analog and digital sections of the AD9764 have separate exceed the specified output compliance range to maintain speci- power supply inputs (i.e., AVDD and DVDD) that can operate fied distortion and linearity performance. independently over a 2.7 volt to 5.5 volt range. The digital The differential voltage, V , appearing across I and DIFF OUTA section, which is capable of operating up to a 125 MSPS clock I is: OUTB rate, consists of edge-triggered latches and segment decoding V = (I – I ) · R (7) DIFF OUTA OUTB LOAD logic circuitry. The analog section includes the PMOS current sources, the associated differential switches, a 1.20 V bandgap Substituting the values of I , I and I ; V can be OUTA OUTB REF DIFF voltage reference and a reference control amplifier. expressed as: The full-scale output current is regulated by the reference con- V = {(2 DAC CODE – 16383)/16384} ·DIFF trol amplifier and can be set from 2 mA to 20 mA via an exter- V = {(32 R /R ) · V (8) DIFF LOAD SET REFIO nal resistor, R . The external resistor, in combination with SET These last two equations highlight some of the advantages of both the reference control amplifier and voltage reference operating the AD9764 differentially. First, the differential op- , sets the reference current I , which is mirrored over to V REFIO REF eration will help cancel common-mode error sources associated the segmented current sources with the proper scaling factor. with I and I such as noise, distortion and dc offsets. OUTA OUTB , is 32 times the value of I . The full-scale current, I OUTFS REF Second, the differential code-dependent current and subsequent voltage, V , is twice the value of the single-ended voltage DIFF DAC TRANSFER FUNCTION output (i.e., V or V ), thus providing twice the signal OUTA OUTB The AD9764 provides complementary current outputs, I OUTA power to the load. and I . I will provide a near full-scale current output, OUTB OUTA , when all bits are high (i.e., DAC CODE = 16383) while Note that the gain drift temperature performance for a single- I OUTFS , the complementary output, provides no current. The ended (V and V ) or differential output (V ) of the I OUTA OUTB DIFF OUTB and I is a function of AD9764 can be enhanced by selecting temperature tracking current output appearing at I OUTA OUTB and can be expressed as: resistors for R and R due to their ratiometric relation- both the input code and I LOAD SET OUTFS ship as shown in Equation 8. I = (DAC CODE/16384) · I (1) OUTA OUTFS REV. B –9– AD9764 provides several application benefits. The first benefit relates REFERENCE OPERATION directly to the power dissipation of the AD9764, which is pro- The AD9764 contains an internal 1.20 V bandgap reference portional to I (refer to the Power Dissipation section). The that can be easily disabled and overridden by an external OUTFS second benefit relates to the 20 dB adjustment, which is useful reference. REFIO serves as either an input or output, depending for system gain control purposes. on whether the internal or external reference is selected. If REFLO is tied to ACOM, as shown in Figure 22, the internal The small signal bandwidth of the reference control amplifier is reference is activated, and REFIO provides a 1.20 V output. In approximately 1.4 MHz and can be reduced by connecting an this case, the internal reference must be compensated externally external capacitor between COMP1 and AVDD. The output of with a ceramic chip capacitor of 0.1mF or greater from REFIO the control amplifier, COMP1, is internally compensated via a to REFLO. Also, REFIO should be buffered with an external 50 pF capacitor that limits the control amplifier small-signal amplifier having an input bias current less than 100 nA if any bandwidth and reduces its output impedance. Any additional additional loading is required. external capacitance further limits the bandwidth and acts as a +5V filter to reduce the noise contribution from the reference ampli- 0.1mF fier. Figure 24 shows the relationship between the external OPTIONAL capacitor and the small signal –3 dB bandwidth of the refer- EXTERNAL REF BUFFER REFLO COMP1 AVDD ence amplifier. Since the –3 dB bandwidth corresponds to the dominant pole, and hence the time constant, the settling time of +1.2V REF 50pF the control amplifier to a stepped reference input response can REFIO CURRENT be approximated. ADDITIONAL SOURCE FS ADJ 0.1mF LOAD ARRAY 2kV AD9764 1000 Figure 22. Internal Reference Configuration The internal reference can be disabled by connecting REFLO to AVDD. In this case, an external reference may then be applied to REFIO as shown in Figure 23. The external reference may 10 provide either a fixed reference voltage to enhance accuracy and drift performance or a varying reference voltage for gain control. Note that the 0.1mF compensation capacitor is not required since the internal reference is disabled, and the high input im- pedance (i.e., 1 MW) of REFIO minimizes any loading of the external reference. 0.1 AVDD 0.1 1 10 100 1000 COMP1 CAPACITOR – nF 0.1mF Figure 24. External COMP1 Capacitor vs. –3 dB Bandwidth The optimum distortion performance for any reconstructed REFLO COMP1 AVDD AVDD waveform is obtained with a 0.1mF external capacitor installed. +1.2V REF Thus, if I is fixed for an application, a 0.1mF ceramic chip 50pF REF V REFIO REFIO EXTERNAL capacitor is recommended. Also, since the control amplifier is CURRENT REF SOURCE FS ADJ optimized for low power operation, multiplying applications ARRAY requiring large signal swings should consider using an external R I = SET REF V /R REFERENCE control amplifier to enhance the application’s overall large signal REFIO SET AD9764 CONTROL multiplying bandwidth and/or distortion performance. AMPLIFIER There are two methods in which I can be varied for a fixed REF R . The first method is suitable for a single-supply system in Figure 23. External Reference Configuration SET which the internal reference is disabled, and the common-mode voltage of REFIO is varied over its compliance range of 1.25 V REFERENCE CONTROL AMPLIFIER to 0.10 V. REFIO can be driven by a single-supply amplifier or The AD9764 also contains an internal control amplifier that is DAC, thus allowing I to be varied for a fixed R . Since the used to regulate the DAC’s full-scale output current, I . REF SET OUTFS input impedance of REFIO is approximately 1 MW, a simple, The control amplifier is configured as a V-I converter, as shown low cost R-2R ladder DAC configured in the voltage mode in Figure 23, such that its current output, I , is determined by REF topology may be used to control the gain. This circuit is shown the ratio of the V and an external resistor, R , as stated REFIO SET in Figure 25 using the AD7524 and an external 1.2 V reference, in Equation 4. I is copied over to the segmented current REF the AD1580. sources with the proper scaling factor to set I as stated in OUTFS Equation 3. The control amplifier allows a wide (10:1) adjustment span of I over a 2 mA to 20 mA range by setting IREF between OUTFS 62.5mA and 625mA. The wide adjustment span of I OUTFS –10– REV. B BANDWIDTH – kHz AD9764 AVDD OPTIONAL AVDD BANDLIMITING CAPACITOR REFLO COMP1 AVDD +1.2V REF R V FB DD 50pF 1.2V OUT1 0.1V TO 1.2V REFIO AD7524 V CURRENT REF SOURCE OUT2 FS ADJ AD1580 ARRAY AGND R I = SET REF AD9764 V /R REF SET DB7–DB0 Figure 25. Single-Supply Gain Control Circuit The second method may be used in a dual-supply system in ANALOG OUTPUTS which the common-mode voltage of REFIO is fixed, and I is REF The AD9764 produces two complementary current outputs, varied by an external voltage, V , applied to R via an ampli- GC SET I and I , which may be configured for single-end OUTA OUTB fier. An example of this method is shown in Figure 26 in which or differential operation. I and I can be converted into OUTA OUTB the internal reference is used to set the common-mode voltage complementary single-ended voltage outputs, V and OUTA of the control amplifier to 1.20 V. The external voltage, V , is GC V , via a load resistor, R , as described in the DAC OUTB LOAD referenced to ACOM and should not exceed 1.2 V. The value of Transfer Function section by Equations 5 through 8. The R is such that I and I do not exceed 62.5mA SET REFMAX REFMIN differential voltage, V , existing between V and V DIFF OUTA OUTB and 625mA, respectively. The associated equations in Figure 26 can also be converted to a single-ended voltage via a transformer can be used to determine the value of R . SET or differential amplifier configuration. Figure 28 shows the equivalent analog output circuit of the AVDD OPTIONAL AD9764 consisting of a parallel combination of PMOS differen- BANDLIMITING CAPACITOR tial current switches associated with each segmented current source. The output impedance of I and I is determined OUTA OUTB REFLO COMP1 AVDD by the equivalent parallel combination of the PMOS switches +1.2V REF and is typically 100 kW in parallel with 5 pF. Due to the na- 50pF REFIO ture of a PMOS device, the output impedance is also slightly CURRENT FS ADJ SOURCE 1mF dependent on the output voltage (i.e., V and V ) and, to OUTA OUTB ARRAY R SET a lesser extent, the analog supply voltage, AVDD, and full-scale I REF AD9764 current, I . Although the output impedance’s signal depen- OUTFS I = (1.2–V )/R REF GC SET dency can be a source of dc nonlinearity and ac linearity (i.e., V GC WITH V < V AND 62.5mA # I # 625A GC REFIO REF distortion), its effects can be limited if certain precautions are noted. Figure 26. Dual-Supply Gain Control Circuit In some applications, the user may elect to use an external control amplifier to enhance the multiplying bandwidth, AD9764 distortion performance and/or settling time. External amplifiers capable of driving a 50 pF load such as the AD817 are suitable AVDD for this purpose. It is configured in such a way that it is in parallel with the weaker internal reference amplifier as shown in Figure 27. In this case, the external amplifier simply overdrives the weaker reference control amplifier. Also, since the internal control amplifier has a limited current output, it will sustain no damage if overdriven. I I OUTA OUTB EXTERNAL CONTROL AMPLIFIER R R AVDD LOAD LOAD V REF INPUT AVDD REFLO COMP1 Figure 28. Equivalent Analog Output Circuit +1.2V REF I and I also have a negative and positive voltage compli- 50pF OUTA OUTB REFIO CURRENT ance range. The negative output compliance range of –1.0 V is FS ADJ SOURCE set by the breakdown limits of the CMOS process. Operation ARRAY R SET AD9764 beyond this maximum limit may result in a breakdown of the output stage and affect the reliability of the AD9764. The posi- tive output compliance range is slightly dependent on the full- Figure 27. Configuring an External Reference Control scale output current, I . It degrades slightly from its nominal OUTFS Amplifier REV. B –11– AD9764 1.25 V for an I = 20 mA to 1.00 V for an I = 2 mA. In summary, the AD9764 achieves the optimum distortion and OUTFS OUTFS Operation beyond the positive compliance range will induce noise performance under the following conditions: clipping of the output signal which severely degrades the (1) Differential Operation. AD9764’s linearity and distortion performance. (2) Positive voltage swing at I and I limited to +0.5 V. OUTA OUTB For applications requiring the optimum dc linearity, I and/ OUTA (3) I set to 20 mA. OUTFS or I should be maintained at a virtual ground via an I-V op OUTB amp configuration. Maintaining I and/or I at a virtual OUTA OUTB (4) Analog Supply (AVDD) set at 5.0 V. ground keeps the output impedance of the AD9764 fixed, signifi- (5) Digital Supply (DVDD) set at 3.0 V to 3.3 V with appro- cantly reducing its effect on linearity. However, it does not priate logic levels. necessarily lead to the optimum distortion performance due to Note that the ac performance of the AD9764 is characterized limitations of the I-V op amp. Note that the INL/DNL speci- under the above mentioned operating conditions. fications for the AD9764 are measured in this manner using I . In addition, these dc linearity specifications remain OUTA DIGITAL INPUTS virtually unaffected over the specified power supply range of The AD9764’s digital input consists of 14 data input pins and a 2.7 V to 5.5 V. clock input pin. The 14-bit parallel data inputs follow standard Operating the AD9764 with reduced voltage output swings at positive binary coding where DB13 is the most significant bit I and I in a differential or single-ended output configu- OUTA OUTB (MSB), and DB0 is the least significant bit (LSB). I pro- OUTA ration reduces the signal dependency of its output impedance duces a full-scale output current when all data bits are at Logic thus enhancing distortion performance. Although the voltage 1. I produces a complementary output with the full-scale OUTB compliance range of I and I extends from –1.0 V to OUTA OUTB current split between the two outputs as a function of the input +1.25 V, optimum distortion performance is achieved when the code. maximum full-scale signal at I and I does not exceed OUTA OUTB The digital interface is implemented using an edge-triggered approximately 0.5 V. A properly selected transformer with a master slave latch. The DAC output is updated following the grounded center-tap will allow the AD9764 to provide the re- rising edge of the clock as shown in Figure 1 and is designed to quired power and voltage levels to different loads while main- support a clock rate as high as 125 MSPS. The clock can be taining reduced voltage swings at I and I . DC-coupled OUTA OUTB operated at any duty cycle that meets the specified latch pulse- applications requiring a differential or single-ended output con- width. The setup and hold times can also be varied within the figuration should size R accordingly. Refer to Applying the LOAD clock cycle as long as the specified minimum times are met, AD9764 section for examples of various output configurations. although the location of these transition edges may affect digital The most significant improvement in the AD9764’s distortion feedthrough and distortion performance. Best performance is and noise performance is realized using a differential output typically achieved when the input data transitions on the falling configuration. The common-mode error sources of both I OUTA edge of a 50% duty cycle clock. and I can be substantially reduced by the common-mode OUTB The digital inputs are CMOS-compatible with logic thresholds, rejection of a transformer or differential amplifier. These V set to approximately half the digital positive supply THRESHOLD, common-mode error sources include even-order distortion (DVDD) or products and noise. The enhancement in distortion performance becomes more significant as the reconstructed waveform’s V = DVDD/2 (–20%) THRESHOLD frequency content increases and/or its amplitude decreases. The internal digital circuitry of the AD9764 is capable of operating This is evident in Figure 14, which compares the differential over a digital supply range of 2.7 V to 5.5 V. As a result, the vs. single-ended performance of the AD9764 at 50 MSPS for digital inputs can also accommodate TTL levels when DVDD is 0.0 and –6.0 dBFS single tone waveforms over frequency. set to accommodate the maximum high level voltage of the TTL The distortion and noise performance of the AD9764 is also drivers V . A DVDD of 3 V to 3.3 V will typically ensure OH(MAX) slightly dependent on the analog and digital supply as well as the proper compatibility with most TTL logic families. Figure 29 full-scale current setting, I . Operating the analog supply at OUTFS shows the equivalent digital input circuit for the data and clock 5.0 V ensures maximum headroom for its internal PMOS current inputs. The sleep mode input is similar with the exception that sources and differential switches leading to improved distortion it contains an active pull-down circuit, thus ensuring that the performance as shown in Figure 8. Although I can be set OUTFS AD9764 remains enabled if this input is left disconnected. between 2 mA and 20 mA, selecting an I of 20 mA will OUTFS DVDD provide the best distortion and noise performance also shown in Figure 8. The noise performance of the AD9764 is affected by the digital supply (DVDD), output frequency, and increases DIGITAL with increasing clock rate as shown in Figure 13. Operating the INPUT AD9764 with low voltage logic levels between 3 V and 3.3 V will slightly reduce the amount of on-chip digital noise. Figure 29. Equivalent Digital Input –12– REV. B AD9764 30 Since the AD9764 is capable of being updated up to 125 MSPS, the quality of the clock and data input signals are important in 25 achieving the optimum performance. Operating the AD9764 with reduced logic swings and a corresponding digital supply (DVDD) will result in the lowest data feedthrough and on-chip 20 digital noise. The drivers of the digital data interface circuitry should be specified to meet the minimum setup and hold times 15 of the AD9764 as well as its required min/max input logic level thresholds. 10 Digital signal paths should be kept short and run lengths matched to avoid propagation delay mismatch. The insertion 5 of a low value resistor network (i.e., 20W to 100W) between the AD9764 digital inputs and driver outputs may be helpful in 0 22 4 6 8 10 1214 16180 reducing any overshooting and ringing at the digital inputs that I – mA OUTFS contribute to data feedthrough. For longer run lengths and high Figure 30. I vs. I AVDD OUTFS data update rates, strip line techniques with proper termination resistors should be considered to maintain “clean” digital inputs. Conversely, I is dependent on both the digital input wave- DVDD form, f , and digital supply DVDD. Figures 31 and 32 CLOCK The external clock driver circuitry should provide the AD9764 show I as a function of full-scale sine wave output ratios DVDD with a low jitter clock input meeting the min/max logic levels (f /f ) for various update rates with DVDD = 5 V and OUT CLOCK while providing fast edges. Fast clock edges will help minimize DVDD = 3 V, respectively. Note, how I is reduced by more DVDD any jitter that will manifest itself as phase noise on a recon- than a factor of 2 when DVDD is reduced from 5 V to 3 V. structed waveform. Thus, the clock input should be driven by the fastest logic family suitable for the application. 18 Note, that the clock input could also be driven via a sine wave, 125MSPS 16 which is centered around the digital threshold (i.e., DVDD/2) and meets the min/max logic threshold. This will typically result 14 100MSPS in a slight degradation in the phase noise, which becomes more 12 noticeable at higher sampling rates and output frequencies. 10 Also, at higher sampling rates, the 20% tolerance of the digital logic threshold should be considered since it will affect the effec- 8 tive clock duty cycle and, subsequently, cut into the required 50MSPS 6 data setup and hold times. 4 25MSPS SLEEP MODE OPERATION 2 The AD9764 has a power-down function that turns off the 5MSPS 0 output current and reduces the supply current to less than 0.01 0.1 1 8.5 mA over the specified supply range of 2.7 V to 5.5 V and RATIO – f /f OUT CLK temperature range. This mode can be activated by applying a Figure 31. I vs. Ratio @ DVDD = 5 V DVDD logic level “1” to the SLEEP pin. This digital input also con- tains an active pull-down circuit that ensures the AD9764 re- 8 mains enabled if this input is left disconnected. The SLEEP 125MSPS input with active pull-down requires <40mA of drive current. The power-up and power-down characteristics of the AD9764 6 100MSPS are dependent upon the value of the compensation capacitor connected to COMP1. With a nominal value of 0.1mF, the AD9764 takes less than 5ms to power down and approximately 4 3.25 ms to power back up. Note, the SLEEP MODE should not be used when the external control amplifier is used as shown in 50MSPS Figure 27. 2 25MSPS POWER DISSIPATION The power dissipation, P , of the AD9764 is dependent on D 5MSPS 0 several factors, including: (1) AVDD and DVDD, the power 0.01 0.1 1 RATIO – f /f OUT CLK supply voltages; (2) I , the full-scale current output; (3) OUTFS f , the update rate; and (4) the reconstructed digital input CLOCK Figure 32. I vs. Ratio @ DVDD = 3 V DVDD waveform. The power dissipation is directly proportional to the analog supply current, I , and the digital supply current, AVDD I . I is directly proportional to I as shown in DVDD AVDD OUTFS, Figure 30, and is insensitive to f . CLOCK REV. B –13– I – mA I – mA AVDD I – mA DVDD DVDD AD9764 APPLYING THE AD9764 DIFFERENTIAL USING AN OP AMP OUTPUT CONFIGURATIONS An op amp can also be used to perform a differential-to-single- The following sections illustrate some typical output configura- ended conversion as shown in Figure 34. The AD9764 is con- tions for the AD9764. Unless otherwise noted, it is assumed figured with two equal load resistors, R , of 25 W. The LOAD that I is set to a nominal 20 mA. For applications requir- differential voltage developed across I and I is con- OUTFS OUTA OUTB ing the optimum dynamic performance, a differential output verted to a single-ended signal via the differential op amp con- configuration is suggested. A differential output configuration figuration. An optional capacitor can be installed across I OUTA may consist of either an RF transformer or a differential op amp and I , forming a real pole in a low-pass filter. The addition OUTB configuration. The transformer configuration provides the opti- of this capacitor also enhances the op amp’s distortion perfor- mum high frequency performance and is recommended for any mance by preventing the DAC’s high slewing output from over- application allowing for ac coupling. The differential op amp loading the op amp’s input. configuration is suitable for applications requiring dc coupling, a 500V bipolar output, signal gain and/or level shifting. AD9764 A single-ended output is suitable for applications requiring a 225V I 22 OUTA unipolar voltage output. A positive unipolar output voltage will AD8047 result if I and/or I is connected to an appropriately 225V OUTA OUTB I 21 OUTB sized load resistor, R , referred to ACOM. This configura- LOAD C OPT tion may be more suitable for a single-supply system requiring a 500V dc coupled, ground referred output voltage. Alternatively, an 25V 25V amplifier could be configured as an I-V converter, thus convert- ing I or I into a negative unipolar voltage. This con- OUTA OUTB Figure 34. DC Differential Coupling Using an Op Amp figuration provides the best dc linearity since I or I is OUTA OUTB maintained at a virtual ground. Note, I provides slightly OUTA The common-mode rejection of this configuration is typically better performance than I . OUTB determined by the resistor matching. In this circuit, the differ- ential op amp circuit using the AD8047 is configured to provide DIFFERENTIAL COUPLING USING A TRANSFORMER some additional signal gain. The op amp must operate from a An RF transformer can be used to perform a differential-to- dual supply since its output is approximately –1.0 V. A high single-ended signal conversion as shown in Figure 33. A speed amplifier capable of preserving the differential perform- differentially coupled transformer output provides the optimum ance of the AD9764 while meeting other system level objectives distortion performance for output signals whose spectral content (i.e., cost, power) should be selected. The op amps differential lies within the transformer’s passband. An RF transformer such gain, its gain setting resistor values and full-scale output swing as the Mini-Circuits T1-1T provides excellent rejection of com- capabilities should all be considered when optimizing this circuit. mon-mode distortion (i.e., even-order harmonics) and noise The differential circuit shown in Figure 35 provides the neces- over a wide frequency range. It also provides electrical isolation sary level-shifting required in a single supply system. In this and the ability to deliver twice the power to the load. Trans- case, AVDD, which is the positive analog supply for both the formers with different impedance ratios may also be used for AD9764 and the op amp, is also used to level-shift the differ- impedance matching purposes. Note that the transformer ential output of the AD9764 to midsupply (i.e., AVDD/2). The provides ac coupling only. AD8041 is a suitable op amp for this application. MINI-CIRCUITS 500V T1-1T I 22 OUTA AD9764 225V AD9764 R LOAD I 22 OUTA AD8041 I 21 OUTB 225V I 21 OPTIONAL R OUTB DIFF C OPT 1kV AVDD Figure 33. Differential Output Using a Transformer 25V 25V 1kV The center tap on the primary side of the transformer must be connected to ACOM to provide the necessary dc current path Figure 35. Single-Supply DC Differential Coupled Circuit for both I and I . The complementary voltages appear- OUTA OUTB ing at I and I (i.e., V and V ) swing sym- OUTA OUTB OUTA OUTB SINGLE-ENDED UNBUFFERED VOLTAGE OUTPUT metrically around ACOM and should be maintained with the Figure 36 shows the AD9764 configured to provide a unipolar specified output compliance range of the AD9764. A differential output range of approximately 0 V to +0.5 V for a doubly termi- resistor, R , may be inserted in applications in which the DIFF nated 50W cable since the nominal full-scale current, I , of OUTFS output of the transformer is connected to the load, R , via a LOAD 20 mA flows through the equivalent R of 25W. In this case, LOAD passive reconstruction filter or cable. R is determined by the DIFF R represents the equivalent load resistance seen by I or LOAD OUTA transformer’s impedance ratio and provides the proper source I . The unused output (I or I ) can be connected to OUTB OUTA OUTB termination that results in a low VSWR. Note that approxi- ACOM directly or via a matching R . Different values of LOAD mately half the signal power will be dissipated across R . DIFF –14– REV. B AD9764 I and R can be selected as long as the positive compli- system. In general, AVDD, the analog supply, should be decoupled OUTFS LOAD ance range is adhered to. One additional consideration in this to ACOM, the analog common, as close to the chip as physi- mode is the integral nonlinearity (INL) as discussed in the Ana- cally possible. Similarly, DVDD, the digital supply, should be log Output section of this data sheet. For optimum INL perfor- decoupled to DCOM as close as physically as possible. mance, the single-ended, buffered voltage output configuration For those applications requiring a single +5 V or +3 V supply is suggested. for both the analog and digital supply, a clean analog supply may be generated using the circuit shown in Figure 38. The circuit consists of a differential LC filter with separate power AD9764 I = 20mA OUTFS V = 0 TO +0.5V OUTA supply and return lines. Lower noise can be attained using low I 22 OUTA ESR type electrolytic and tantalum capacitors. 50V 50V 21 I OUTB FERRITE 25V BEADS TTL/CMOS AVDD LOGIC 100mF 10-22mF 0.1mF CIRCUITS ELECT. TANT. CER. Figure 36. 0 V to +0.5 V Unbuffered Voltage Output ACOM SINGLE-ENDED BUFFERED VOLTAGE OUTPUT CONFIGURATION +5V OR +3V Figure 37 shows a buffered single-ended output configuration in POWER SUPPLY which the op amp U1 performs an I-V conversion on the AD9764 output current. U1 maintains I (or I ) at a OUTA OUTB Figure 38. Differential LC Filter for Single +5 V or +3 V virtual ground, thus minimizing the nonlinear output impedance Applications effect on the DAC’s INL performance as discussed in the Ana- Maintaining low noise on power supplies and ground is critical log Output section. Although this single-ended configuration to obtain optimum results from the AD9764. If properly typically provides the best dc linearity performance, its ac distor- implemented, ground planes can perform a host of functions on tion performance at higher DAC update rates may be limited by high speed circuit boards: bypassing, shielding current trans- U1’s slewing capabilities. U1 provides a negative unipolar port, etc. In mixed signal design, the analog and digital portions output voltage and its full-scale output voltage is simply the of the board should be distinct from each other, with the analog product of R and I . The full-scale output should be set FB OUTFS ground plane confined to the areas covering the analog signal within U1’s voltage output swing capabilities by scaling I OUTFS traces, and the digital ground plane confined to areas covering and/or R . An improvement in ac distortion performance may FB the digital interconnects. result with a reduced I since the signal current U1 will be OUTFS required to sink will be subsequently reduced. All analog ground pins of the DAC, reference and other analog components should be tied directly to the analog ground plane. C OPT The two ground planes should be connected by a path 1/8 to 1/4 inch wide underneath or within 1/2 inch of the DAC to R FB maintain optimum performance. Care should be taken to ensure 200V that the ground plane is uninterrupted over crucial signal paths. AD9764 I = 10mA OUTFS On the digital side, this includes the digital input lines running I OUTA 22 to the DAC as well as any clock signals. On the analog side, this U1 V = I 3 R OUT OUTFS FB includes the DAC output signal, reference signal and the supply I OUTB 21 feeders. 200V The use of wide runs or planes in the routing of power lines is also recommended. This serves the dual role of providing a low Figure 37. Unipolar Buffered Voltage Output series impedance power supply to the part, as well as providing some “free” capacitive decoupling to the appropriate ground POWER AND GROUNDING CONSIDERATIONS plane. It is essential that care be taken in the layout of signal and In systems seeking to simultaneously achieve high speed and power ground interconnects to avoid inducing extraneous volt- high performance, the implementation and construction of the age drops in the signal ground paths. It is recommended that all printed circuit board design is often as important as the circuit connections be short, direct and as physically close to the pack- design. Proper RF techniques must be used in device selection, age as possible in order to minimize the sharing of conduction placement and routing and supply bypassing and grounding. paths between different currents. When runs exceed an inch in Figures 42–47 illustrate the recommended printed circuit board length, strip line techniques with proper termination resistors ground, power and signal plane layouts that are implemented on should be considered. The necessity and value of this resistor the AD9764 evaluation board. will be dependent upon the logic family used. Proper grounding and decoupling should be a primary objective For a more detailed discussion of the implementation and con- in any high speed, high resolution system. The AD9764 features struction of high speed, mixed signal printed circuit boards, separate analog and digital supply and ground pins to optimize refer to Analog Devices’ application notes AN-280 and AN-333. the management of analog and digital ground currents in a REV. B –15– AD9764 MULTITONE PERFORMANCE CONSIDERATIONS AND ratio of 13.5 dB compared to a sine waves peak-to-rms ratio of CHARACTERIZATION 3 dB. A “snapshot” of this reconstructed multitone vector in the The frequency domain performance of high speed DACs has time domain as shown in Figure 39b reveals the higher signal traditionally been characterized by analyzing the spectral output content around the midscale value. As a result, a DAC’s of a reconstructed full-scale (i.e., 0 dBFS), single-tone sine wave “small-scale” dynamic and static linearity becomes increas- at a particular output frequency and update rate. Although this ingly critical in obtaining low intermodulation distortion and characterization data is useful, it is often insufficient to reflect a maintaining sufficient carrier-to-noise ratios for a given modula- DAC’s performance for a reconstructed multitone or spread- tion scheme. spectrum waveform. In fact, evaluating a DAC’s spectral A DAC’s small-scale linearity performance is also an important performance using a full-scale, single tone at the highest specified consideration in applications where additive dynamic range is frequency (i.e., f ) of a bandlimited waveform is typically H required for gain control purposes or “predistortion” signal indicative of a DAC’s “worst-case” performance for that given conditioning. For instance, a DAC with sufficient dynamic waveform. In the time domain, this full-scale sine wave repre- range can be used to provide additional gain control of its sents the lowest peak-to-rms ratio or crest factor (i.e., V /V PEAK reconstructed signal. In fact, the gain can be controlled in rms) that this bandlimited signal will encounter. 6 dB increments by simply performing a shift left or right on the DAC’s digital input word. Other applications may intentionally –10 predistort a DAC’s digital input signal to compensate for –20 nonlinearities associated with the subsequent analog compo- nents in the signal chain. For example, the signal compression –30 associated with a power amplifier can be compensated for by –40 predistorting the DAC’s digital input with the inverse nonlinear –50 transfer function of the power amplifier. In either case, the –60 DAC’s performance at reduced signal levels should be carefully evaluated. –70 –80 A full-scale single tone will induce all of the dynamic and static nonlinearities present in a DAC that contribute to its distortion –90 and hence SFDR performance. Referring to Figure 3, as the –100 frequency of this reconstructed full-scale, single-tone waveform –110 increases, the dynamic nonlinearities of any DAC (i.e., AD9764) 2.19 2.25 2.31 2.38 2.44 2.50 2.56 2.63 2.69 2.75 2.81 tend to dominate thus contributing to the rolloff in its SFDR FREQUENCY – MHz performance. However, unlike most DACs, which employ an R-2R Figure 39a. Multitone Spectral Plot ladder for the lower bit current segmentation, the AD9764 (as well as other TxDAC members) exhibits an improvement in 1.0000 distortion performance as the amplitude of a single tone is re- 0.8000 duced from its full-scale level. This improvement in distortion 0.6000 performance at reduced signal levels is evident if one compares the SFDR performance vs. frequency at different amplitudes 0.4000 (i.e., 0 dBFS, –6 dBFS and –12 dBFS) and sample rates as 0.2000 shown in Figures 4 through 7. Maintaining decent “small-scale” 0.0000 linearity across the full span of a DAC transfer function is also –0.2000 critical in maintaining excellent multitone performance. –0.4000 Although characterizing a DAC’s multitone performance tends to be application-specific, much insight into the potential per- –0.6000 formance of a DAC can also be gained by evaluating the DAC’s –0.8000 swept power (i.e., amplitude) performance for single, dual and –1.0000 multitone test vectors at different clock rates and carrier frequen- TIME cies. The DAC is evaluated at different clock rates when recon- Figure 39b. Time Domain “Snapshot” of the Multitone structing a specific waveform whose amplitude is decreased in Waveform 3 dB increments from full-scale (i.e., 0 dBFS). For each specific However, the inherent nature of a multitone, spread spectrum, waveform, a graph showing the SFDR (over Nyquist) perfor- or QAM waveform, in which the spectral energy of the wave- mance vs. amplitude can be generated at the different tested form is spread over a designated bandwidth, will result in a clock rates as shown in Figures 9–11. Note that the carrier(s)- higher peak-to-rms ratio when compared to the case of a simple to-clock ratio remains constant in each figure. In each case, an sine wave. As the reconstructed waveform’s peak-to-average improvement in SFDR performance is seen as the amplitude is ratio increases, an increasing amount of the signal energy is reduced from 0 dBFS to approximately –9.0 dBFS. concentrated around the DAC’s midscale value. Figure 39a is A multitone test vector may consist of several equal amplitude, just one example of a bandlimited multitone vector (i.e., eight spaced carriers each representative of a channel within a defined tones) centered around one-half the Nyquist bandwidth (i.e., bandwidth as shown in Figure 39a. In many cases, one or more f /4). This particular multitone vector, has a peak-to-rms CLOCK tones are removed so the intermodulation distortion performance –16– REV. B VOLTS MAGNITUDE – dBm AD9764 of the DAC can be evaluated. Nonlinearities associated with the AD9764 EVALUATION BOARD DAC will create spurious tones of which some may fall back into General Description the “empty” channel thus limiting a channel’s carrier-to-noise The AD9764-EB is an evaluation board for the AD9764 14-bit ratio. Other spurious components falling outside the band of DAC converter. Careful attention to layout and circuit design, interest may also be important, depending on the system’s spectral combined with a prototyping area, allows the user to easily and mask and filtering requirements. effectively evaluate the AD9764 in any application where high resolution, high speed conversion is required. This particular test vector was centered around one-half the Nyquist bandwidth (i.e., f /4) with a passband of f /16. CLOCK CLOCK This board allows the user the flexibility to operate the AD9764 Centering the tones at a much lower region (i.e., f /10) CLOCK in various configurations. Possible output configurations include would lead to an improvement in performance while centering transformer coupled, resistor terminated, inverting/noninverting the tones at a higher region (i.e., f /2.5) would result in a CLOCK and differential amplifier outputs. The digital inputs are designed degradation in performance. Figure 40a shows the SFDR vs. to be driven directly from various word generators with the amplitude at different sample rates up to the Nyquist frequency onboard option to add a resistor network for proper load termi- while Figure 40b shows the SFDR vs. amplitude within the nation. Provisions are also made to operate the AD9764 with passband of the test vector. In assessing a DAC’s multitone either the internal or external reference or to exercise the power- performance, it is also recommended that several units be tested down feature. under exactly the same conditions to determine any performance Refer to the application note AN-420, Using the AD9760/AD9764/ variability. AD9764-EB Evaluation Board for a thorough description and operating instructions for the AD9764 evaluation board. 80 75 70 10 MSPS 65 60 20 MSPS 55 50 MSPS 50 45 40 100 MSPS 35 30 –20 –15 –10 –5 0 A – dBFS OUT Figure 40a. Multitone SFDR vs. A (Up to Nyquist) OUT 80 10 MSPS 75 20 MSPS 70 65 60 50 MSPS 55 100 MSPS 50 45 40 –20 –15 –10 –5 0 A – dBFS OUT Figure 40b. Multitone SFDR vs. A (Within Multitone OUT Passband) REV. B –17– SFDR – dBc SFDR – dBc AD9764 Figure 41. Evaluation Board Schematic –18– REV. B DVDD DGND AVDD AGND AVEE AVCC B1 B2 B3 B4 B5 B6 TP19 TP3 TP4 TP6 TP7 TP2 TP18 TP5 CLK TP1 J1 C3 C4 C5 C6 JP1 A A A AB 10mF 10mF 10mF 10mF EXTCLK 3 1 2 R15 DVDD DVDD 49.9V R1 R7 R5 R3 16 PINDIP U1 AVDD TP8 1 1 1 1 RES PK C7 C8 C9 P1 1mF 0.1mF 0.1mF AD9764 2 3 4 5 6 7 8 9 10 2 3 4 5 6 7 8 9 10 2 3 4 5 6 7 8 9 10 2 3 4 5 6 7 8 9 10 2 1 C19 1 16 1 28 DB13 CLOCK A 4 3 C1 2 15 2 27 DB12 DVDD 6 5 C2 3 14 3 26 DB11 DCOM 8 7 C25 4 13 4 25 DB10 NC 10 9 C26 5 12 5 24 DB9 AVDD AVDD 11 C27 6 11 6 12 23 DB8 COMP2 OUT 1 C28 7 7 22 14 13 10 DB7 IOUTA OUT 2 C29 8 21 16 15 8 9 DB6 IOUTB 18 17 20 9 DB5 ACOM 20 19 10 19 COMP1 DB4 22 21 18 11 DB3 FS ADJ 24 23 16 PINDIP 17 12 DB2 REFIO 26 25 RES PK 16 13 DB1 REFLO 28 27 14 15 DB0 SLEEP TP11 TP10 TP9 TP13 30 29 C30 1 16 32 31 A C31 2 15 R16 34 33 CT1 AVDD C32 3 14 2kV 36 35 C33 4 13 C11 C10 38 37 A TP14 C34 5 12 0.1mF 0.1mF 1 40 39 C35 6 11 C36 7 10 2 JP4 JP2 3 10 98 76 54 32 10 98 76 54 32 10 98 76 54 32 10 98 76 54 32 PDIN TP12 A A A J2 AVDD 1 1 1 1 R2 R6 R4 R8 R17 49.9V DVDD DVDD AVCC R18 1kV AVCC AVCC U7 J3 A C21 C22 R42 3 B OUT1 JP6A JP7B 0.1mF 1mF REF43 C17 JP7A 1kV U4 2 6 JP3 0.1mF VIN VOUT 2 3 J6 J7 JP8 7 A R12 C18 C16 GND C12 6 U6 R20 1 A A OPEN AD8047 0.1mF 1mF 22pF B B B 49.9V 4 3 7 2 R37 R43 4 C20 A 49.9V 5kV 4 6 R10 CW A 3 0 A A AD8047 A A 1kV 2 5 A A A R14 A T1 4 AVEE 0 JP6B A EXTREFIN R36 1 JP5 C14 J5 1kV R45 6 1mF 1kV 3 2 1 A R13 R9 R35 A J4 OPEN A C15 1kV 1kV R44 C23 C24 OUT2 0.1mF 50V R46 0.1mF 1mF JP9 A A A 1kV B A R38 C13 A A 22pF 49.9V AVEE A A AD9764 Figure 42. Silkscreen Layer—Top Figure 43. Component Side PCB Layout (Layer 1) REV. B –19– AD9764 Figure 44. Ground Plane PCB Layout (Layer 2) Figure 45. Power Plane PCB Layout (Layer 3) –20– REV. B AD9764 Figure 46. Solder Side PCB Layout (Layer 4) Figure 47. Silkscreen Layer—Bottom REV. B –21– AD9764 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead, 300 Mil SOIC (R-28) 0.7125 (18.10) 0.6969 (17.70) 28 15 0.2992 (7.60) 0.2914 (7.40) 0.4193 (10.65) 1 14 0.3937 (10.00) PIN 1 0.1043 (2.65) 0.0291 (0.74) 3 458 0.0926 (2.35) 0.0098 (0.25) 88 0.0118 (0.30) 0.0500 0.0192 (0.49) SEATING 08 0.0500 (1.27) 0.0125 (0.32) (1.27) PLANE 0.0040 (0.10) 0.0138 (0.35) 0.0157 (0.40) 0.0091 (0.23) BSC 28-Lead TSSOP (RU-28) 0.386 (9.80) 0.378 (9.60) 28 15 0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25) 1 14 PIN 1 0.006 (0.15) 0.0433 (1.10) MAX 0.002 (0.05) 88 0.0256 (0.65) 0.0118 (0.30) 08 0.028 (0.70) SEATING 0.0079 (0.20) BSC 0.0075 (0.19) PLANE 0.020 (0.50) 0.0035 (0.090) –22– REV. B PRINTED IN U.S.A. C2467b–1–10/99