ANALOG DEVICES AD9762

12-Bit, 125 MSPS ® a TxDAC D/A Converter AD9762 FUNCTIONAL BLOCK DIAGRAM FEATURES Member of Pin-Compatible TxDAC Product Family +5V 125 MSPS Update Rate 0.1�F 12-Bit Resolution Excellent Spurious Free Dynamic Range Performance REFLO COMP1 AVDD ACOM SFDR to Nyquist @ 5 MHz Output: 70 dBc +1.20V REF AD9762 50pF Differential Current Outputs: 2 mA to 20 mA 0.1�F REFIO 0.1�F CURRENT COMP2 Power Dissipation: 175 mW @ 5 V to 45 mW @ 3 V SOURCE FS ADJ Power-Down Mode: 25 mW @ 5 V ARRAY R SET On-Chip 1.20 V Reference +5V DVDD IOUTA Single +5 V or +3 V Supply Operation SEGMENTED LSB DCOM IOUTB SWITCHES SWITCHES Package: 28-Lead SOIC and TSSOP CLOCK Edge-Triggered Latches CLOCK LATCHES SLEEP APPLICATIONS DIGITAL DATA INPUTS (DB11–DB0) Communication Transmit Channel: Basestations (Single/Multichannel Applications) ADSL/HFC Modems Differential current outputs are provided to support single- Direct Digital Synthesis (DDS) ended or differential applications. Matching between the two Instrumentation current outputs ensures enhanced dynamic performance in a differential output configuration. The current outputs may be PRODUCT DESCRIPTION tied directly to an output resistor to provide two complemen- The AD9762 is the 12-bit resolution member of the TxDAC tary, single-ended voltage outputs or fed directly into a trans- series of high performance, low power CMOS digital-to-analog former. The output voltage compliance range is 1.25 V. converters (DACs). The TxDAC family which consists of pin The on-chip reference and control amplifier are configured for compatible 8-, 10-, 12-, and 14-bit DACs is specifically opti- maximum accuracy and flexibility. The AD9762 can be driven mized for the transmit signal path of communication systems. by the on-chip reference or by a variety of external reference All of the devices share the same interface options, small outline voltages. The internal control amplifier which provides a wide package and pinout, thus providing an upward or downward (>10:1) adjustment span allows the AD9762 full-scale current component selection path based on performance, resolution and to be adjusted over a 2 mA to 20 mA range while maintaining cost. The AD9762 offers exceptional ac and dc performance excellent dynamic performance. Thus, the AD9762 may oper- while supporting update rates up to 125 MSPS. ate at reduced power levels or be adjusted over a 20 dB range to The AD9762’s flexible single-supply operating range of 2.7 V to provide additional gain ranging capabilities. 5.5 V and low power dissipation are well suited for portable and The AD9762 is available in 28-lead SOIC and TSSOP pack- low power applications. Its power dissipation can be further ages. It is specified for operation over the industrial tempera- reduced to a mere 45 mW without a significant degradation in ture range. performance by lowering the full-scale current output. Also, a power-down mode reduces the standby power dissipation to PRODUCT HIGHLIGHTS approximately 25 mW. 1. The AD9762 is a member of the TxDAC product family which The AD9762 is manufactured on an advanced CMOS process. provides an upward or downward component selection path A segmented current source architecture is combined with a based on resolution (8 to 14 bits), performance and cost. proprietary switching technique to reduce spurious components 2. Manufactured on a CMOS process, the AD9762 uses a pro- and enhance dynamic performance. Edge-triggered input prietary switching technique that enhances dynamic perfor- latches and a 1.2 V temperature compensated bandgap refer- mance beyond what was previously attainable by higher ence have been integrated to provide a complete monolithic power/cost bipolar or BiCMOS devices. DAC solution. Flexible supply options support +3 V and +5 V 3. On-chip, edge-triggered input CMOS latches interface readily CMOS logic families. to +3 V and +5 V CMOS logic families. The AD9762 can The AD9762 is a current-output DAC with a nominal full-scale support update rates up to 125 MSPS. output current of 20 mA and > 100 kΩ output impedance. 4. A flexible single-supply operating range of 2.7 V to 5.5 V and TxDAC is a registered trademark of Analog Devices, Inc. a wide full-scale current adjustment span of 2 mA to 20 mA allow the AD9762 to operate at reduced power levels. REV. B 5. The current output(s) of the AD9762 can be easily config- ured for various single-ended or differential circuit topologies. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties Tel: 781/329-4700 World Wide Web Site: http://www.analog.com which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 2000 AD9762–SPECIFICATIONS (T to T , AVDD = +5 V, DVDD = +5 V, I = 20 mA, unless otherwise noted) DC SPECIFICATIONS MIN MAX OUTFS Parameter Min Typ Max Units RESOLUTION 12 Bits 1 DC ACCURACY Integral Linearity Error (INL) T = +25°C –2.5 ±0.75 +2.5 LSB A T to T –4.0 ±1.0 +4.0 LSB MIN MAX Differential Nonlinearity (DNL) T = +25°C –1.5 ±0.5 +1.5 LSB A T to T –2.0 ±0.75 +2.0 LSB MIN MAX ANALOG OUTPUT Offset Error –0.025 +0.025 % of FSR Gain Error (Without Internal Reference) –10 ±2 +10 % of FSR Gain Error (With Internal Reference) –10 ±1 +10 % of FSR 2 Full-Scale Output Current 2.0 20.0 mA Output Compliance Range –1.0 +1.25 V Output Resistance 100 kΩ Output Capacitance 5 pF REFERENCE OUTPUT Reference Voltage 1.08 1.20 1.32 V 3 Reference Output Current 100 nA REFERENCE INPUT Input Compliance Range 0.1 1.25 V Reference Input Resistance 1 MΩ 4 Small Signal Bandwidth (w/o C ) 1.4 MHz COMP1 TEMPERATURE COEFFICIENTS Offset Drift 0 ppm of FSR/°C Gain Drift (Without Internal Reference) ±50 ppm of FSR/°C Gain Drift (With Internal Reference) ±100 ppm of FSR/°C Reference Voltage Drift ±50 ppm/°C POWER SUPPLY Supply Voltages 5 AVDD 2.7 5.0 5.5 V DVDD 2.7 5.0 5.5 V Analog Supply Current (I)2530mA AVDD 6 Digital Supply Current (I ) 1.5 2 mA DVDD ) 8.5 mA Supply Current Sleep Mode (I AVDD 6 Power Dissipation (5 V, I = 20 mA) 133 160 mW OUTFS 7 Power Dissipation (5 V, I = 20 mA) 190 mW OUTFS 7 (3 V, I = 2 mA) 45 mW Power Dissipation OUTFS Power Supply Rejection Ratio—AVDD –0.4 +0.4 % of FSR/V Power Supply Rejection Ratio—DVDD –0.025 +0.025 % of FSR/V OPERATING RANGE –40 +85 °C NOTES 1 Measured at IOUTA, driving a virtual ground. 2 Nominal full-scale current, I , is 32 × the I current. OUTFS REF 3 Use an external buffer amplifier to drive any external load. 4 Reference bandwidth is a function of external cap at COMP1 pin and signal level. Refer to Figure 41. 5 For operation below 3 V, it is recommended that the output current be reduced to 12 mA or less to maintain optimum performance. 6 Measured at f = 25 MSPS and f = 1.0 MHz. CLOCK OUT 7 Measured as unbuffered voltage output into 50 Ω R at IOUTA and IOUTB, f = 100 MSPS and f = 40 MHz. LOAD CLOCK OUT Specifications subject to change without notice. –2– REV. B AD9762 (T to T , AVDD = +5 V, DVDD = +5 V, I = 20 mA, Differential Transformer Coupled Output, MIN MAX OUTFS DYNAMIC SPECIFICATIONS 50� Doubly Terminated, unless otherwise noted) Parameter Min Typ Max Units DYNAMIC PERFORMANCE Maximum Output Update Rate (f ) 125 MSPS CLOCK 1 Output Settling Time (t ) (to 0.1%) 35 ns ST Output Propagation Delay (t)1 ns PD Glitch Impulse 5 pV-s 1 Output Rise Time (10% to 90%) 2.5 ns 1 Output Fall Time (10% to 90%) 2.5 ns Output Noise (I = 20 mA) 50 pA/√Hz OUTFS Output Noise (I = 2 mA) 30 pA/√Hz OUTFS AC LINEARITY Spurious-Free Dynamic Range to Nyquist f = 25 MSPS; f = 1.00 MHz CLOCK OUT T = +25°C 75 79 dBc A T to T 73 dBc MIN MAX f = 50 MSPS; f = 1.00 MHz 79 dBc CLOCK OUT f = 50 MSPS; f = 2.51 MHz 74 dBc CLOCK OUT f = 50 MSPS; f = 5.02 MHz 70 dBc CLOCK OUT f = 50 MSPS; f = 20.2 MHz 57 dBc CLOCK OUT f = 100 MSPS; f = 2.51 MHz 73 dBc CLOCK OUT f = 100 MSPS; f = 5.04 MHz 67 dBc CLOCK OUT f = 100 MSPS; f = 20.2 MHz 57 dBc CLOCK OUT f = 100 MSPS; f = 40.4 MHz 53 dBc CLOCK OUT Spurious-Free Dynamic Range within a Window f = 25 MSPS; f =1.00 MHz; 2 MHz Span CLOCK OUT T = +25°C 78 86 dBc A T to T 76 dBc MIN MAX f = 50 MSPS; f = 5.02 MHz; 2 MHz Span 84 dBc CLOCK OUT f = 100 MSPS; f = 5.04 MHz; 4 MHz Span 84 dBc CLOCK OUT Total Harmonic Distortion f = 25 MSPS; f = 1.00 MHz CLOCK OUT T = +25°C –78 –74 dBc A T to T –72 dBc MIN MAX f = 50 MHz; f = 2.00 MHz –75 dBc CLOCK OUT f = 100 MHz; f = 2.00 MHz –75 dBc CLOCK OUT Multitone Power Ratio (8 Tones at 110 kHz Spacing) f = 20 MSPS; f = 2.00 MHz to 2.99 MHz 73 dBc CLOCK OUT NOTES 1 Measured single ended into 50 Ω load. Specifications subject to change without notice. REV. B –3– AD9762 (T to T , AVDD = +5 V, DVDD = +5 V, I = 20 mA unless otherwise noted) DIGITAL SPECIFICATIONS MIN MAX OUTFS Parameter Min Typ Max Units DIGITAL INPUTS Logic “1” Voltage @ DVDD = +5 V 3.5 5 V Logic “1” Voltage @ DVDD = +3 V 2.1 3 V Logic “0” Voltage @ DVDD = +5 V 0 1.3 V Logic “0” Voltage @ DVDD = +3 V 0 0.9 V Logic “1” Current –10 +10 µA Logic “0” Current –10 +10 µA Input Capacitance 5 pF Input Setup Time (t ) 2.0 ns S Input Hold Time (t ) 1.5 ns H Latch Pulsewidth (t ) 3.5 ns LPW Specifications subject to change without notice. DB0–DB11 t t S H CLOCK t LPW t PD t ST IOUTA OR 0.1% IOUTB 0.1% Figure 1. Timing Diagram ABSOLUTE MAXIMUM RATINGS* ORDERING GUIDE With Temperature Package Package Parameter Respect to Min Max Units Model Range Description Option* AVDD ACOM –0.3 +6.5 V AD9762AR –40°C to +85°C 28-Lead 300 mil SOIC R-28 DVDD DCOM –0.3 +6.5 V AD9762ARU –40°C to +85°C 28-Lead TSSOP RU-28 ACOM DCOM –0.3 +0.3 V AD9762-EB Evaluation Board AVDD DVDD –6.5 +6.5 V CLOCK, SLEEP DCOM –0.3 DVDD + 0.3 V *R = SOIC, RU = TSSOP. Digital Inputs DCOM –0.3 DVDD + 0.3 V THERMAL CHARACTERISTICS IOUTA, IOUTB ACOM –1.0 AVDD + 0.3 V Thermal Resistance COMP1, COMP2 ACOM –0.3 AVDD + 0.3 V 28-Lead 300 mil SOIC REFIO, FSADJ ACOM –0.3 AVDD + 0.3 V θ = 71.4°C/W REFLO ACOM –0.3 +0.3 V JA θ = 23°C/W Junction Temperature +150 °C JC 28-Lead TSSOP Storage Temperature –65 +150 °C θ = 97.9°C/W Lead Temperature JA θ = 14.0°C/W (10 sec) +300 °C JC *Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may effect device reliability. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD9762 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD ESD SENSITIVE DEVICE precautions are recommended to avoid performance degradation or loss of functionality. REV. B –4– AD9762 PIN CONFIGURATION (MSB) DB11 1 28 CLOCK 2 DB10 27 DVDD DB9 3 26 DCOM DB8 NC 4 25 DB7 5 24 AVDD AD9762 DB6 6 COMP2 23 TOP VIEW (Not to Scale) DB5 7 22 IOUTA DB4 8 IOUTB 21 DB3 9 20 ACOM DB2 10 19 COMP1 DB1 11 18 FS ADJ DB0 12 17 REFIO NC REFLO 13 16 NC 14 15 SLEEP NC = NO CONNECT PIN DESCRIPTIONS Pin No. Name Description 1 DB11 Most Significant Data Bit (MSB). 2–11 DB10–DB1 Data Bits 1–10. 12 DB0 Least Significant Data Bit (LSB). 13, 14, 25 NC No Internal Connection. 15 SLEEP Power-down Control Input. Active High. Contains active pull-down circuit, thus may be left unterminated if not used. 16 REFLO Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal reference. 17 REFIO Reference Input/Output. Serves as reference input when internal reference disabled (i.e., Tie REFLO to AVDD). Serves as 1.2 V reference output when internal reference activated (i.e., Tie REFLO to ACOM). Requires 0.1µF capacitor to ACOM when internal reference activated. 18 FS ADJ Full-Scale Current Output Adjust. 19 COMP1 Bandwidth/Noise Reduction Node. Add 0.1 µF to AVDD for optimum performance. 20 ACOM Analog Common. 21 IOUTB Complementary DAC Current Output. Full-scale current when all data bits are 0s. 22 IOUTA DAC Current Output. Full-scale current when all data bits are 1s. 23 COMP2 Internal Bias Node for Switch Driver Circuitry. Decouple to ACOM with 0.1 µF capacitor. 24 AVDD Analog Supply Voltage (+2.7 V to +5.5 V). 26 DCOM Digital Common. 27 DVDD Digital Supply Voltage (+2.7 V to +5.5 V). 28 CLOCK Clock Input. Data latched on positive edge of clock. REV. B –5– AD9762 DEFINITIONS OF SPECIFICATIONS Power Supply Rejection Linearity Error (Also Called Integral Nonlinearity or INL) The maximum change in the full-scale output as the supplies Linearity error is defined as the maximum deviation of the are varied from nominal to minimum and maximum specified actual analog output from the ideal output, determined by a voltages. straight line drawn from zero to full scale. Settling Time Differential Nonlinearity (or DNL) The time required for the output to reach and remain within a DNL is the measure of the variation in analog value, normalized specified error band about its final value, measured from the to full scale, associated with a 1 LSB change in digital input start of the output transition. code. Glitch Impulse Monotonicity Asymmetrical switching times in a DAC give rise to undesired A D/A converter is monotonic if the output either increases or output transients that are quantified by a glitch impulse. It is remains constant as the digital input increases. specified as the net area of the glitch in pV-s. Offset Error Spurious-Free Dynamic Range The deviation of the output current from the ideal of zero is The difference, in dB, between the rms amplitude of the output called offset error. For I , 0 mA output is expected when the OUTA signal and the peak spurious signal over the specified bandwidth. inputs are all 0s. For I , 0 mA output is expected when all OUTB Total Harmonic Distortion inputs are set to 1s. THD is the ratio of the rms sum of the first six harmonic Gain Error components to the rms value of the measured output signal. It is The difference between the actual and ideal output span. The expressed as a percentage or in decibels (dB). actual span is determined by the output when all inputs are set Multitone Power Ratio to 1s minus the output when all inputs are set to 0s. The spurious-free dynamic range for an output containing mul- Output Compliance Range tiple carrier tones of equal amplitude. It is measured as the The range of allowable voltage at the output of a current-output difference between the rms amplitude of a carrier tone to the DAC. Operation beyond the maximum compliance limits may peak spurious signal in the region of a removed tone. cause either output stage saturation or breakdown resulting in nonlinear performance. Temperature Drift Temperature drift is specified as the maximum change from the ambient (+25°C) value to the value at either T or T . For MIN MAX offset and gain drift, the drift is reported in ppm of full-scale range (FSR) per degree C. For reference drift, the drift is reported in ppm per degree C. +5V 0.1�F REFLO COMP1 AVDD ACOM +1.20V REF AD9762 50pF 0.1�F REFIO PMOS 0.1�F COMP2 FS ADJ CURRENT SOURCE ARRAY MINI-CIRCUITS R SET T1-1T TO HP3589A 2k� +5V DVDD IOUTA SPECTRUM/ SEGMENTED SWITCHES LSB NETWORK DCOM 100� IOUTB SWITCHES FOR DB11–DB3 ANALYZER 50� INPUT CLOCK LATCHES DVDD 50� SLEEP 50� 20pF DCOM RETIMED 50� 20pF CLOCK DIGITAL OUTPUT* DATA CLOCK * AWG2021 CLOCK RETIMED OUTPUT SUCH THAT DIGITAL DATA TEKTRONIX LECROY 9210 TRANSITIONS ON FALLING EDGE AWG-2021 PULSE GENERATOR OF 50% DUTY CYCLE CLOCK. Figure 2. Basic AC Characterization Test Set-Up REV. B –6– AD9762 Typical AC Characterization Curves @ +5 V Supplies (AVDD = +5 V, DVDD = +5 V, I = 20 mA, 50� Doubly Terminated Load, Differential Output, T = +25�C, SFDR up to Nyquist, unless otherwise noted) OUTFS A 85 90 85 –6dBFS –6dBFS 80 80 0dBFS –12dBFS 25MSPS 80 5MSPS 75 –12dBFS 75 70 50MSPS 70 70 0dBFS 65 65 100MSPS 60 60 60 55 55 125MSPS 50 50 50 0.1 110 100 0.00 0.50 1.00 1.50 2.00 2.50 0.00 2.00 4.00 6.00 8.00 10.00 12.00 FREQUENCY – MHz FREQUENCY – MHz FREQUENCY – MHz Figure 3. SFDR vs. f @ 0 dBFS OUT Figure 4. SFDR vs. f @ 5 MSPS Figure 5. SFDR vs. f @ 25 MSPS OUT OUT 85 85 85 80 80 80 –6dBFS 75 75 75 –12dBFS 70 70 70 –6dBFS 65 65 65 –12dBFS –6dBFS –12dBFS 0dBFS 60 60 60 0dBFS 0dBFS 55 55 55 50 50 50 0.00 5.00 10.00 15.00 20.00 25.00 0.00 10.00 20.00 30.00 40.00 50.00 0.00 10.00 20.00 30.00 40.00 50.00 60.00 FREQUENCY – MHz FREQUENCY – MHz FREQUENCY – MHz Figure 6. SFDR vs. f @ 50 MSPS Figure 7. SFDR vs. f @100 MSPS Figure 8. SFDR vs. f @ 125 MSPS OUT OUT OUT 85 85 0.675/0.725MHz 455kHz 1MHz @ 5MSPS @ 5MSPS @ 5MSPS 80 3.38/3.63MHz 5.0MHz 2.27MHz 75 75 @ 25MSPS @ 25MSPS @ 25MSPS 10MHz 4.55MHz @ 50MSPS 70 @ 50MSPS 65 65 60 9.1MHz 13.5/14.5MHz @ 100MSPS @ 100MSPS 11.37MHz 55 55 20MHz 16.9/18.1MHz @ 125MSPS 50 25MHz @ 100MSPS @ 125MSPS 6.75/7.25MHz @ 125MSPS @ 50MSPS 45 45 40 –30 –25 –20 –15 –10 –5 0 –30 –25 –20 –15 –10 –5 0 –30 –25 –20 –15 –10 –5 0 A – dBFS A – dBFS A – dBFS OUT OUT OUT Figure 9. Single-Tone SFDR vs. A Figure 10. Single-Tone SFDR vs. Figure 11. Dual-Tone SFDR vs. A OUT OUT @ f = f /11 A @ f = f /5 @ f = f /7 OUT CLOCK OUT OUT CLOCK OUT CLOCK REV. B –7– SFDR – dBc SFDR – dBc SFDR – dBc SFDR – dBc SFDR – dBc SFDR – dBc SFDR – dBc SFDR – dBc SFDR – dBc AD9762 80 –70 75 IDIFF @ 0dBFS 75 2.5MHz 70 70 –75 10MHz IDIFF @ –6dBFS 2ND 65 65 HARMONIC 22.2MHz 60 –80 IOUTA @ 0dBFS 3RD 55 60 HARMONIC 50 –85 40MHz 55 45 IOUTA @ –6dBFS 40 –90 50 4TH 35 HARMONIC –95 30 45 28 4 6 10 12 14 16 1820 0 20 40 60 80 100 120 140 1 10 100 FREQUENCY – MSPS I – mA OUTPUT FREQUENCY – MHz OUTFS Figure 12. THD vs. f @ Figure 13. SFDR vs. f and I Figure 14. Differential vs. Single- CLOCK OUT OUTFS f = 2 MHz @ 100 MSPS, 0 dBFS Ended SFDR vs. f @ 100 MSPS OUT OUT 1.25 80 1 1.00 0.8 75 0.75 2.5MHz 0.6 0.50 70 0.25 0.4 0 65 0.2 10MHz –0.25 60 0 –0.50 –0.75 –0.2 55 40MHz –1.00 –0.4 50 –1.25 –40 –20 0 20 40 60 80 0 1000 2000 3000 4000 0 1000 2000 3000 4000 CODE TEMPERATURE – �C CODE Figure 15. Typical INL Figure 16. Typical DNL Figure 17. SFDR vs. Temperature @ 100 MSPS, 0 dBFS 0 0 –10 f = 100 MSPS f = 50 MSPS CLOCK CLOCK f = 100 MSPS CLOCK f = 2.41MHz f = 6.25MHz OUT OUT1 f = 13.5MHz OUT1 SFDR = 72dBc f = 6.75MHz OUT2 f = 14.5MHz OUT2 AMPLITUDE = 0dBFS f = 7.25MHz OUT3 SFDR = 62dBc f = 7.75MHz OUT4 AMPLITUDE = 0dBFS SFDR = 71dBc AMPLITUDE = 0dBFS –100 –100 –110 START: 0.3 MHz STOP: 50.0 MHz START: 0.3 MHz STOP: 50.0 MHz START: 0.3 MHz STOP: 25.0 MHz Figure 18. Single-Tone SFDR Figure 19. Dual-Tone SFDR Figure 20. Four-Tone SFDR REV. B –8– ERROR – LSB dBc 10dB – Div ERROR – LSB SFDR – dBc 10dB – Div SFDR – dBc SFDR – dBc 10dB – Div AD9762 Typical AC Characterization Curves @ +3 V Supplies (AVDD = +3 V, DVDD = +3 V, I = 20 mA, 50Ω Doubly Terminated Load, Differential Output, T = +25�C, SFDR up to Nyquist, unless otherwise noted) OUTFS A 90 85 85 0dBFS 80 –6dBFS 80 –12dBFS 80 5MSPS 75 75 –12dBFS 25MSPS 70 70 –6dBFS 70 50MSPS 65 65 100MSPS 0dBFS 60 60 60 125MSPS 55 55 50 50 50 0.1 110 100 0.00 0.50 1.00 1.50 2.00 2.50 02 46 8 10 12 FREQUENCY – MHz FREQUENCY – MHz FREQUENCY – MHz Figure 21. SFDR vs. f @ 0 dBFS Figure 22. SFDR vs. f @ 5 MSPS Figure 23. SFDR vs. f @ 25 MSPS OUT OUT OUT 85 85 85 80 80 80 75 –6dBFS 75 75 –12dBFS 0dBFS 70 70 70 –6dBFS –12dBFS 65 65 65 –12dBFS 0dBFS 60 60 60 –6dBFS 0dBFS 55 55 55 50 50 50 05 10 15 20 25 010 20 30 40 50 010 20 30 40 50 60 FREQUENCY – MHz FREQUENCY – MHz FREQUENCY – MHz Figure 24. SFDR vs. f @ 50 MSPS Figure 25. SFDR vs. f @ 100 MSPS Figure 26. SFDR vs. f @ 125 MSPS OUT OUT OUT 90 90 90 455kHz 1MHz 0.675/0.725MHz @ 5MSPS 4.55MHz @ 5MSPS @ 5MSPS 80 @ 50MSPS 80 80 2.27MHz 5.0MHz 3.38/3.63MHz @ 25MSPS @ 25MSPS @ 25MSPS 6.75/7.25MHz 70 70 70 @ 50MSPS 10MHz @ 50MSPS 9.1MHz 60 60 60 @ 100MSPS 16.9/18.1MHz 11.37MHz 20MHz @ 125MSPS @ 125MSPS @ 100MSPS 50 50 50 25MHz 13.5/14.5MHz @ 125MSPS @ 100MSPS 40 40 40 –30 –25 –20 –15 –10 –5 0 –30 –25 –20 –15 –10 –5 0 –30 –25 –20 –15 –10 –5 0 A – dBFS A – dBFS A – dBFS OUT OUT OUT Figure 27. Single-Tone SFDR vs. A Figure 28. Single-Tone SFDR vs. Figure 29. Dual-Tone SFDR vs. A OUT OUT @ f = f /11 A @ f = f /5 @ f = f /7 OUT CLOCK OUT OUT CLOCK OUT CLOCK REV. B –9– SFDR – dBc SFDR – dBc SFDR – dBc SFDR – dBc SFDR – dBc SFDR – dBc SFDR – dBc SFDR – dBc SFDR – dBc AD9762 –70 80 75 2.5MHz 75 70 –75 70 IDIFF @ 2ND –6dBFS HARMONIC 10MHz 65 3RD 65 –80 HARMONIC 60 22.2MHz 55 60 IDIFF @ –85 50 0dBFS 40MHz IOUTA @ 55 45 –6dBFS 4TH –90 40 HARMONIC 50 IOUTA @ 35 0dBFS –95 30 45 24 6 8 10 12 14 16 18 20 0 20 40 60 80 100 120 140 1 10 100 FREQUENCY – MSPS I – mA OUTPUT FREQUENCY – MHz OUTFS Figure 30. THD vs. f @ f = Figure 31. SFDR vs. f and I Figure 32. Differential vs. Single CLOCK OUT OUT OUTFS 2 MHz @ 100 MSPS, 0 dBFS Ended SFDR vs. f @ 100 MSPS OUT 1 1.25 80 1.00 0.8 75 0.75 2.5MHz 0.6 0.50 70 0.4 0.25 0 65 0.2 10MHz –0.25 0 60 –0.50 –0.2 –0.75 55 28.6MHz –1.00 –0.4 –1.25 50 0 1000 2000 3000 4000 0 1000 2000 3000 4000 –40 –20 0 20 40 60 80 CODE CODE TEMPERATURE – �C Figure 33. Typical INL Figure 34. Typical DNL Figure 35. SFDR vs. Temperature @ 100 MSPS, 0 dBFS 0 0 –10 f = 100 MSPS f = 100 MSPS f = 50 MSPS CLOCK CLOCK CLOCK f = 2.41MHz f = 13.5MHz f = 6.25MHz OUT OUT1 OUT1 SFDR = 72dBc f = 14.5MHz f = 6.75MHz OUT2 OUT2 AMPLITUDE = 0dBFS SFDR = 59.0dBc f = 7.25MHz OUT3 AMPLITUDE = 0dBFS f = 7.75MHz OUT4 SFDR = 71dBc AMPLITUDE = 0dBFS –100 –100 –110 START: 0.3 MHz STOP: 50.0 MHz START: 0.3 MHz STOP: 50.0 MHz START: 0.3 MHz STOP: 25.0 MHz Figure 36. Single-Tone SFDR Figure 37. Dual-Tone SFDR Figure 38. Four-Tone SFDR REV. B –10– ERROR – LSB dBc 10dB – Div ERROR – LSB SFDR – dBc 10dB – Div SFDR – dBc SFDR – dBc 10dB – Div AD9762 FUNCTIONAL DESCRIPTION I = (DAC CODE/4096) × I (1) OUTA OUTFS Figure 39 shows a simplified block diagram of the AD9762. I = (4095 – DAC CODE)/4096 × I (2) OUTB OUTFS The AD9762 consists of a large PMOS current source array where DAC CODE = 0 to 4095 (i.e., Decimal Representation). that is capable of providing up to 20 mA of total current. The array is divided into 31 equal currents that make up the 5 As mentioned previously, I is a function of the reference OUTFS most significant bits (MSBs). The next 4 bits or middle bits current I , which is nominally set by a reference voltage REF consist of 15 equal current sources whose value is 1/16th of an V and external resistor R . It can be expressed as: REFIO SET MSB current source. The remaining LSBs are binary weighted I = 32 × I (3) OUTFS REF fractions of the middle-bits current sources. Implementing the middle and lower bits with current sources, instead of an where I = V /R (4) REF REFIO SET R-2R ladder, enhances its dynamic performance for multitone The two current outputs will typically drive a resistive load or low amplitude signals and helps maintain the DAC’s high directly or via a transformer. If dc coupling is required, I OUTA output impedance (i.e., >100 kΩ). and I should be directly connected to matching resistive OUTB All of these current sources are switched to one or the other loads, R , which are tied to analog common, ACOM. Note, LOAD of the two output nodes (i.e., I or I ) via PMOS differen- R may represent the equivalent load resistance seen by LOAD OUTA OUTB tial current switches. The switches are based on a new archi- I or I as would be the case in a doubly terminated OUTA OUTB tecture that drastically improves distortion performance. This new 50Ω or 75Ω cable. The single-ended voltage output appearing switch architecture reduces various timing errors and provides at the I and I nodes is simply : OUTA OUTB matching complementary drive signals to the inputs of the V = I × R (5) OUTA OUTA LOAD differential current switches. V = I × R (6) OUTB OUTB LOAD The analog and digital sections of the AD9762 have separate Note the full-scale value of V and V should not exceed OUTA OUTB power supply inputs (i.e., AVDD and DVDD) that can operate the specified output compliance range to maintain specified independently over a 2.7 volt to 5.5 volt range. The digital distortion and linearity performance. section, which is capable of operating up to a 125 MSPS clock rate, consists of edge-triggered latches and segment decoding The differential voltage, V , appearing across I and DIFF OUTA logic circuitry. The analog section includes the PMOS current I is: OUTB sources, the associated differential switches, a 1.20 V bandgap V = (I – I ) × R (7) DIFF OUTA OUTB LOAD voltage reference and a reference control amplifier. Substituting the values of I , I , and I ; V can be OUTA OUTB REF DIFF The full-scale output current is regulated by the reference expressed as: control amplifier and can be set from 2 mA to 20 mA via an V = {(2 DAC CODE – 4095)/4096} × DIFF external resistor, R . The external resistor, in combination SET (32 R /R ) × V (8) LOAD SET REFIO with both the reference control amplifier and voltage refer- ence V , sets the reference current I , which is mirrored REFIO REF These last two equations highlight some of the advantages of over to the segmented current sources with the proper scaling operating the AD9762 differentially. First, the differential factor. The full-scale current, I , is thirty-two times the value OUTFS operation will help cancel common-mode error sources associated of I . REF with I and I such as noise, distortion and dc offsets. OUTA OUTB Second, the differential code dependent current and subsequent DAC TRANSFER FUNCTION voltage, V , is twice the value of the single-ended voltage DIFF The AD9762 provides complementary current outputs, I OUTA output (i.e., V or V ), thus providing twice the signal OUTA OUTB and I . I will provide a near full-scale current output, OUTB OUTA power to the load. I , when all bits are high (i.e., DAC CODE = 4095) while OUTFS Note, the gain drift temperature performance for a single-ended I , the complementary output, provides no current. The OUTB (V and V ) or differential output (V ) of the AD9762 OUTA OUTB DIFF current output appearing at I and I is a function of OUTA OUTB can be enhanced by selecting temperature tracking resistors for both the input code and I and can be expressed as: OUTFS R and R due to their ratiometric relationship as shown LOAD SET in Equation 8. +5V 0.1�F REFLO COMP1 AVDD ACOM +1.20V REF AD9762 50pF V REFIO REFIO PMOS 0.1�F COMP2 I CURRENT SOURCE REF FS ADJ 0.1�F ARRAY R V = V – V DIFF OUTA OUTB SET 2k� +5V DVDD I IOUTA OUTA V OUTA SEGMENTED SWITCHES LSB DCOM I IOUTB OUTB FOR DB11–DB3 SWITCHES V OUTB R LOAD 50� CLOCK R LOAD CLOCK LATCHES 50� SLEEP DIGITAL DATA INPUTS (DB11–DB0) Figure 39. Functional Block Diagram REV. B –11– AD9762 REFERENCE OPERATION The control amplifier allows a wide (10:1) adjustment span of The AD9762 contains an internal 1.20 V bandgap reference I over a 2 mA to 20 mA range by setting IREF between OUTFS that can be easily disabled and overridden by an external refer- 62.5µA and 625µA. The wide adjustment span of I OUTFS ence. REFIO serves as either an input or output depending on provides several application benefits. The first benefit relates whether the internal or an external reference is selected. If directly to the power dissipation of the AD9762, which is REFLO is tied to ACOM, as shown in Figure 40, the internal proportional to I (refer to the Power Dissipation section). OUTFS reference is activated and REFIO provides a 1.20 V output. In The second benefit relates to the 20 dB adjustment, which is this case, the internal reference must be compensated externally useful for system gain control purposes. with a ceramic chip capacitor of 0.1µF or greater from REFIO The small signal bandwidth of the reference control amplifier is to REFLO. Also, REFIO should be buffered with an external approximately 1.4 MHz and can be reduced by connecting an amplifier having an input bias current less than 100 nA if any external capacitor between COMP1 and AVDD. The output of additional loading is required. the control amplifier, COMP1, is internally compensated via a 50 pF capacitor that limits the control amplifier small-signal +5V bandwidth and reduces its output impedance. Any additional 0.1�F OPTIONAL external capacitance further limits the bandwidth and acts as a EXTERNAL filter to reduce the noise contribution from the reference ampli- REF BUFFER REFLO COMP1 AVDD fier. Figure 42 shows the relationship between the external +1.2V REF capacitor and the small signal –3 dB bandwidth of the 50pF REFIO CURRENT ADDITIONAL 1000 FS ADJ SOURCE 0.1�F LOAD ARRAY 2k� AD9762 Figure 40. Internal Reference Configuration The internal reference can be disabled by connecting REFLO to AVDD. In this case, an external reference may then be applied 10 to REFIO as shown in Figure 41. The external reference may provide either a fixed reference voltage to enhance accuracy and drift performance or a varying reference voltage for gain control. Note that the 0.1µF compensation capacitor is not required since the internal reference is disabled, and the high input impedance (i.e., 1 MΩ) of REFIO minimizes any loading of the 0 external reference. 0.1 1 10 100 1000 COMP1 CAPACITOR – nF AVDD Figure 42. External COMP1 Capacitor vs. –3 dB Bandwidth 0.1�F reference amplifier. Since the –3 dB bandwidth corresponds to the dominant pole, and hence the time constant, the settling REFLO COMP1 AVDD time of the control amplifier to a stepped reference input AVDD +1.2V REF response can be approximated. 50pF V REFIO REFIO The optimum distortion performance for any reconstructed EXTERNAL CURRENT REF SOURCE FS ADJ waveform is obtained with a 0.1µF external capacitor installed. ARRAY Thus, if I is fixed for an application, a 0.1µF ceramic chip REF R SET I = REF capacitor is recommended. Also, since the control amplifier is V /R REFERENCE REFIO SET AD9762 CONTROL optimized for low power operation, multiplying applications AMPLIFIER requiring large signal swings should consider using an external control amplifier to enhance the application’s overall large signal Figure 41. External Reference Configuration multiplying bandwidth and/or distortion performance. There are two methods in which I can be varied for a fixed REF REFERENCE CONTROL AMPLIFIER R . The first method is suitable for a single-supply system in SET The AD9762 also contains an internal control amplifier that is which the internal reference is disabled, and the common-mode used to regulate the DAC’s full-scale output current, I . OUTFS voltage of REFIO is varied over its compliance range of 1.25 V The control amplifier is configured as a V-I converter as shown to 0.10 V. REFIO can be driven by a single-supply amplifier or in Figure 41, such that its current output, I , is determined by REF DAC, thus allowing I to be varied for a fixed R . Since the REF SET the ratio of the V and an external resistor, R , as stated REFIO SET input impedance of REFIO is approximately 1 MΩ, a simple, in Equation 4. I is copied over to the segmented current REF low cost R-2R ladder DAC configured in the voltage mode sources with the proper scaling factor to set I as stated in OUTFS topology may be used to control the gain. This circuit is shown Equation 3. in Figure 43 using the AD7524 and an external 1.2 V reference, the AD1580. REV. B –12– BANDWIDTH – kHz AD9762 AVDD OPTIONAL AVDD BANDLIMITING CAPACITOR REFLO COMP1 AVDD +1.2V REF R V FB DD 50pF 1.2V OUT1 0.1V TO 1.2V REFIO AD7524 V CURRENT REF OUT2 SOURCE FS ADJ AD1580 ARRAY AGND R SET I = REF AD9762 V /R REF SET DB7–DB0 Figure 43. Single-Supply Gain Control Circuit The second method may be used in a dual-supply system in ANALOG OUTPUTS which the common-mode voltage of REFIO is fixed and I is The AD9762 produces two complementary current outputs, REF varied by an external voltage, V , applied to R via an ampli- I and I , which may be configured for single-ended or GC SET OUTA OUTB fier. An example of this method is shown in Figure 44 in which differential operation. I and I can be converted into OUTA OUTB the internal reference is used to set the common-mode voltage complementary single-ended voltage outputs, V and V , OUTA OUTB of the control amplifier to 1.20 V. The external voltage, V , is via a load resistor, R , as described in the DAC Transfer GC LOAD referenced to ACOM and should not exceed 1.2 V. The value Function section by Equations 5 through 8. The differential of R is such that I and I do not exceed 62.5µA voltage, V , existing between V and V can also be SET REFMAX REFMIN DIFF OUTA OUTB and 625µA, respectively. The associated equations in Figure 44 converted to a single-ended voltage via a transformer or differ- can be used to determine the value of R . ential amplifier configuration. The ac performance of the SET AD9762 is optimum and specified using a differential trans- AVDD former coupled output in which the voltage swing at I and OPTIONAL OUTA BANDLIMITING I is limited to ±0.5 V. If a single-ended unipolar output is OUTB CAPACITOR desirable, I should be selected. OUTA REFLO COMP1 AVDD The distortion and noise performance of the AD9762 can be +1.2V REF enhanced when the AD9762 is configured for differential opera- 50pF REFIO tion. The common-mode error sources of both I and I OUTA OUTB CURRENT FS ADJ SOURCE 1�F can be significantly reduced by the common-mode rejection of a ARRAY R SET transformer or differential amplifier. These common-mode I REF AD9762 error sources include even-order distortion products and noise. I = (1.2–V )/R The enhancement in distortion performance becomes more REF GC SET V GC WITH V < V AND 62.5�A � I � 625A GC REFIO REF significant as the frequency content of the reconstructed wave- form increases. This is due to the first order cancellation of Figure 44. Dual-Supply Gain Control Circuit various dynamic common-mode distortion mechanisms, digital In some applications, the user may elect to use an external con- feedthrough and noise. trol amplifier to enhance the multiplying bandwidth, distortion Performing a differential-to-single-ended conversion via a performance, and/or settling time. External amplifiers capable transformer also provides the ability to deliver twice the recon- of driving a 50 pF load such as the AD817 are suitable for this structed signal power to the load (i.e., assuming no source purpose. It is configured in such a way that it is in parallel with termination). Since the output currents of I and I are OUTA OUTB the weaker internal reference amplifier as shown in Figure 45. complementary, they become additive when processed differen- In this case, the external amplifier simply overdrives the weaker tially. A properly selected transformer will allow the AD9762 to reference control amplifier. Also, since the internal control provide the required power and voltage levels to different loads. amplifier has a limited current output, it will sustain no damage Refer to Applying the AD9762 section for examples of various if overdriven. output configurations. EXTERNAL The output impedance of I and I is determined by the OUTA OUTB CONTROL AMPLIFIER AVDD equivalent parallel combination of the PMOS switches associ- V REF ated with the current sources and is typically 100 kΩ in parallel INPUT with 5 pF. It is also slightly dependent on the output voltage REFLO COMP1 AVDD (i.e., V and V ) due to the nature of a PMOS device. OUTA OUTB +1.2V REF 50pF As a result, maintaining I and/or I at a virtual ground OUTA OUTB REFIO CURRENT via an I-V op amp configuration will result in the optimum dc FS ADJ SOURCE ARRAY linearity. Note, the INL/DNL specifications for the AD9762 R SET AD9762 are measured with I maintained at a virtual ground via an OUTA op amp. Figure 45. Configuring an External Reference Control Amplifier REV. B –13– AD9762 I and I also have a negative and positive voltage Since the AD9762 is capable of being updated up to 125 MSPS, OUTA OUTB compliance range that must be adhered to in order to achieve the quality of the clock and data input signals are important optimum performance. The negative output compliance range in achieving the optimum performance. The drivers of the of –1.0 V is set by the breakdown limits of the CMOS process. digital data interface circuitry should be specified to meet the Operation beyond this maximum limit may result in a break- minimum set-up and hold times of the AD9762 as well as its down of the output stage and affect the reliability of the AD9762. required min/max input logic level thresholds. Typically, the selection of the slowest logic family that satisfies the above The positive output compliance range is slightly dependent conditions will result in the lowest data feedthrough and noise. on the full-scale output current, I . It degrades slightly OUTFS from its nominal 1.25 V for an I = 20 mA to 1.00 V for an Digital signal paths should be kept short and run lengths OUTFS I = 2 mA. The optimum distortion performance for a matched to avoid propagation delay mismatch. The insertion of OUTFS single-ended or differential output is achieved when the maximum a low value resistor network (i.e., 20Ω to 100Ω) between the full-scale signal at I and I does not exceed 0.5 V. AD9762 digital inputs and driver outputs may be helpful in OUTA OUTB Applications requiring the AD9762’s output (i.e., V and/ reducing any overshooting and ringing at the digital inputs that OUTA or V ) to extend its output compliance range should size contribute to data feedthrough. For longer run lengths and high OUTB R accordingly. Operation beyond this compliance range data update rates, strip line techniques with proper termination LOAD will adversely affect the AD9762’s linearity performance and resistors should be considered to maintain “clean” digital subsequently degrade its distortion performance. inputs. Also, operating the AD9762 with reduced logic swings and a corresponding digital supply (DVDD) will also reduce DIGITAL INPUTS data feedthrough. The AD9762’s digital input consists of 12 data input pins and a The external clock driver circuitry should provide the AD9762 clock input pin. The 12-bit parallel data inputs follow standard with a low jitter clock input meeting the min/max logic levels positive binary coding where DB11 is the most significant bit while providing fast edges. Fast clock edges will help minimize (MSB) and DB0 is the least significant bit (LSB). I produces OUTA any jitter that will manifest itself as phase noise on a recon- a full-scale output current when all data bits are at Logic 1. structed waveform. Thus, the clock input should be driven by I produces a complementary output with the full-scale current OUTB the fastest logic family suitable for the application. split between the two outputs as a function of the input code. Note, the clock input could also be driven via a sine wave, The digital interface is implemented using an edge-triggered which is centered around the digital threshold (i.e., DVDD/2), master slave latch. The DAC output is updated following the and meets the min/max logic threshold. This will typically result rising edge of the clock as shown in Figure 1 and is designed in a slight degradation in the phase noise, which becomes more to support a clock rate as high as 125 MSPS. The clock can noticeable at higher sampling rates and output frequencies. be operated at any duty cycle that meets the specified latch Also, at higher sampling rates, the 20% tolerance of the digital pulsewidth. The set-up and hold times can also be varied within logic threshold should be considered since it will affect the the clock cycle as long as the specified minimum times are met; effective clock duty cycle and subsequently cut into the required although the location of these transition edges may affect digital data set-up and hold times. feedthrough and distortion performance. Best performance is typically achieved when the input data transitions on the falling edge SLEEP MODE OPERATION of a 50% duty cycle clock. The AD9762 has a power-down function which turns off the The digital inputs are CMOS compatible with logic thresholds, output current and reduces the supply current to less than V set to approximately half the digital positive supply 8.5 mA over the specified supply range of 2.7 V to 5.5 V and THRESHOLD (DVDD) or temperature range. This mode can be activated by applying a logic level “1” to the SLEEP pin. This digital input also V = DVDD/2 (±20%) THRESHOLD contains an active pull-down circuit that ensures the AD9762 The internal digital circuitry of the AD9762 is capable of operating remains enabled if this input is left disconnected. The SLEEP over a digital supply range of 2.7 V to 5.5 V. As a result, the input with active pull-down requires <40µA of drive current. digital inputs can also accommodate TTL levels when DVDD is The power-up and power-down characteristics of the AD9762 set to accommodate the maximum high level voltage of the TTL are dependent upon the value of the compensation capacitor drivers V . A DVDD of 3 V to 3.3 V will typically ensure OH(MAX) connected to COMP1. With a nominal value of 0.1µF, the proper compatibility with most TTL logic families. Figure 46 AD9762 takes less than 5µs to power down and approximately shows the equivalent digital input circuit for the data and clock 3.25 ms to power back up. Note, the SLEEP MODE should not inputs. The sleep mode input is similar with the exception that be used when the external control amplifier is used as shown in it contains an active pull-down circuit, thus ensuring that the Figure 45. AD9762 remains enabled if this input is left disconnected. DVDD POWER DISSIPATION The power dissipation, P , of the AD9762 is dependent on D several factors which include: (1) AVDD and DVDD, the power DIGITAL supply voltages; (2) I , the full-scale current output; (3) OUTFS INPUT f , the update rate; (4) and the reconstructed digital input CLOCK waveform. The power dissipation is directly proportional to the analog supply current, I , and the digital supply current, I . AVDD DVDD I is directly proportional to I as shown in Figure 47 Figure 46. Equivalent Digital Input AVDD OUTFS and is insensitive to f . CLOCK REV. B –14– AD9762 30 APPLYING THE AD9762 OUTPUT CONFIGURATIONS 25 The following sections illustrate some typical output configura- tions for the AD9762. Unless otherwise noted, it is assumed 20 that I is set to a nominal 20 mA. For applications requir- OUTFS ing the optimum dynamic performance, a differential output configuration is suggested. A differential output configuration 15 may consist of either an RF transformer or a differential op amp configuration. The transformer configuration provides the 10 optimum high frequency performance and is recommended for any application allowing for ac coupling. The differential op 5 amp configuration is suitable for applications requiring dc coupling, a bipolar output, signal gain and/or level shifting. 0 22 4 6 8 10 121416 180 A single-ended output is suitable for applications requiring a I – mA OUTFS unipolar voltage output. A positive unipolar output voltage will Figure 47. I vs. I AVDD OUTFS result if I and/or I is connected to an appropriately OUTA OUTB sized load resistor, R , referred to ACOM. This configura- Conversely, I is dependent on both the digital input wave- LOAD DVDD tion may be more suitable for a single-supply system requiring form, f , and digital supply DVDD. Figures 48 and 49 CLOCK a dc coupled, ground referred output voltage. Alternatively, an show I as a function of full-scale sine wave output ratios DVDD amplifier could be configured as an I-V converter thus converting (f /f ) for various update rates with DVDD = 5 V and OUT CLOCK I or I into a negative unipolar voltage. This configura- DVDD = 3 V, respectively. Note, how I is reduced by more OUTA OUTB DVDD tion provides the best dc linearity since I or I is than a factor of 2 when DVDD is reduced from 5 V to 3 V. OUTA OUTB maintained at a virtual ground. Note, I provides slightly OUTA 18 better performance than I . OUTB 125MSPS 16 DIFFERENTIAL COUPLING USING A TRANSFORMER 14 100MSPS An RF transformer can be used to perform a differential-to- 12 single-ended signal conversion as shown in Figure 50. A differentially coupled transformer output provides the optimum 10 distortion performance for output signals whose spectral content 8 lies within the transformer’s passband. An RF transformer such 50MSPS as the Mini-Circuits T1-1T provides excellent rejection of 6 common-mode distortion (i.e., even-order harmonics) and noise 4 25MSPS over a wide frequency range. It also provides electrical isolation 2 and the ability to deliver twice the power to the load. Trans- 5MSPS formers with different impedance ratios may also be used for 0 0.01 0.1 1 impedance matching purposes. Note that the transformer RATIO (f /f ) OUT CLK provides ac coupling only. Figure 48. I vs. Ratio @ DVDD = 5 V DVDD MINI-CIRCUITS T1-1T IOUTA 22 8 R AD9762 LOAD 125MSPS 21 IOUTB OPTIONAL R DIFF 6 100MSPS Figure 50. Differential Output Using a Transformer The center tap on the primary side of the transformer must be 4 connected to ACOM to provide the necessary dc current path 50MSPS for both I and I . The complementary voltages appear- OUTA OUTB ing at I and I (i.e., V and V ) swing symmetri- OUTA OUTB OUTA OUTB 2 25MSPS cally around ACOM and should be maintained with the specified output compliance range of the AD9762. A differential resistor, 5MSPS R , may be inserted in applications in which the output of DIFF 0 0.01 0.1 1 the transformer is connected to the load, R , via a passive LOAD RATIO (f /f ) OUT CLK reconstruction filter or cable. R is determined by the DIFF Figure 49. I vs. Ratio @ DVDD = 3 V transformer’s impedance ratio and provides the proper source DVDD termination which results in a low VSWR. Note that approxi- mately half the signal power will be dissipated across R . DIFF REV. B –15– I – mA AVDD I – mA I – mA DVDD DVDD AD9762 DIFFERENTIAL USING AN OP AMP this mode is the integral nonlinearity (INL) as discussed in the An op amp can also be used to perform a differential to single- Analog Output section of this data sheet. For optimum INL ended conversion as shown in Figure 51. The AD9762 is performance, the single-ended, buffered voltage output configu- configured with two equal load resistors, R , of 25 Ω. ration is suggested. LOAD The differential voltage developed across I and I is OUTA OUTB converted to a single-ended signal via the differential op amp AD9762 I = 20mA OUTFS configuration. An optional capacitor can be installed across V = 0 TO +0.5V OUTA IOUTA 22 I and I forming a real pole in a low-pass filter. The OUTA OUTB 50� 50� addition of this capacitor also enhances the op amps distortion 21 IOUTB performance by preventing the DACs high slewing output from 25� overloading the op amp’s input. 500� Figure 53. 0 V to +0.5 V Unbuffered Voltage Output AD9762 225� IOUTA 22 SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT AD8047 CONFIGURATION 225� IOUTB 21 Figure 54 shows a buffered single-ended output configuration C OPT in which the op amp U1 performs an I-V conversion on the 500� AD9762 output current. U1 maintains I (or I ) at a 25� 25� OUTA OUTB virtual ground, thus minimizing the nonlinear output imped- ance effect on the DAC’s INL performance as discussed in Figure 51. DC Differential Coupling Using an Op Amp the Analog Output section. Although this single-ended configu- ration typically provides the best dc linearity performance, its ac The common-mode rejection of this configuration is typically distortion performance at higher DAC update rates may be determined by the resistor matching. In this circuit, the differ- limited by U1’s slewing capabilities. U1 provides a negative ential op amp circuit using the AD8047 is configured to provide unipolar output voltage and its full-scale output voltage is sim- some additional signal gain. The op amp must operate off of a ply the product of R and I . The full-scale output should FB OUTFS dual supply since its output is approximately ±1.0 V. A high be set within U1’s voltage output swing capabilities by scaling speed amplifier capable of preserving the differential perfor- I and/or R . An improvement in ac distortion perfor- OUTFS FB mance of the AD9762 while meeting other system level objec- mance may result with a reduced I since the signal current OUTFS tives (i.e., cost, power) should be selected. The op amps U1 will be required to sink will be subsequently reduced. differential gain, its gain setting resistor values, and full-scale output swing capabilities should all be considered when opti- C OPT mizing this circuit. The differential circuit shown in Figure 52 provides the neces- R FB 200� sary level-shifting required in a single supply system. In this AD9762 I = 10mA OUTFS case, AVDD which is the positive analog supply for both the IOUTA 22 AD9762 and the op amp is also used to level-shift the differ- U1 V = I � R ential output of the AD9762 to midsupply (i.e., AVDD/2). The OUT OUTFS FB 21 IOUTB AD8041 is a suitable op amp for this application. 200� 500� AD9762 Figure 54. Unipolar Buffered Voltage Output 225� 22 IOUTA AD8041 225� POWER AND GROUNDING CONSIDERATIONS IOUTB 21 In systems seeking to simultaneously achieve high speed and C OPT 1k� AVDD high performance, the implementation and construction of the 25� 25� 1k� printed circuit board design is often as important as the circuit design. Proper RF techniques must be used in device selection; placement and routing; and supply bypassing and grounding. Figure 52. Single-Supply DC Differential Coupled Circuit Figures 60–65 illustrate the recommended printed circuit board ground, power and signal plane layouts which are implemented SINGLE-ENDED UNBUFFERED VOLTAGE OUTPUT on the AD9762 evaluation board. Figure 53 shows the AD9762 configured to provide a unipolar Proper grounding and decoupling should be a primary objective output range of approximately 0 V to +0.5 V for a doubly termi- in any high speed, high resolution system. The AD9762 features nated 50Ω cable since the nominal full-scale current, I , of OUTFS separate analog and digital supply and ground pins to optimize 20 mA flows through the equivalent R of 25Ω. In this LOAD the management of analog and digital ground currents in a case, R represents the equivalent load resistance seen by LOAD system. In general, AVDD, the analog supply, should be decoupled I or I . The unused output (I or I ) can be OUTA OUTB OUTA OUTB to ACOM, the analog common, as close to the chip as physi- connected to ACOM directly or via a matching R . Different LOAD cally possible. Similarly, DVDD, the digital supply, should be values of I and R can be selected as long as the positive OUTFS LOAD decoupled to DCOM as close as physically as possible. compliance range is adhered to. One additional consideration in REV. B –16– AD9762 For those applications that require a single +5 V or +3 V supply APPLICATIONS for both the analog and digital supply, a clean analog supply Using the AD9762 for QAM Modulation may be generated using the circuit shown in Figure 55. The QAM is one of the most widely used digital modulation schemes circuit consists of a differential LC filter with separate power in digital communication systems. This modulation technique supply and return lines. Lower noise can be attained using low can be found in both FDM as well as spreadspectrum (i.e., ESR type electrolytic and tantalum capacitors. CDMA) based systems. A QAM signal is a carrier frequency which is both modulated in amplitude (i.e., AM modulation) FERRITE and in phase (i.e., PM modulation). It can be generated by BEADS independently modulating two carriers of identical frequency TTL/CMOS AVDD LOGIC 100�F 10-22�F 0.1�F but with a 90° phase difference. This results in an in-phase (I) CIRCUITS TANT. CER. ELECT. carrier component and a quadrature (Q) carrier component at a ACOM 90° phase shift with respect to the I component. The I and Q components are then summed to provide a QAM signal at the specified carrier frequency. +5V OR +3V A common and traditional implementation of a QAM modu- POWER SUPPLY lator is shown in Figure 56. The modulation is performed in the Figure 55. Differential LC Filter for Single +5 V or +3 V analog domain in which two DACs are used to generate the Applications baseband I and Q components, respectively. Each component is then typically applied to a Nyquist filter before being applied to Maintaining low noise on power supplies and ground is critical a quadrature mixer. The matching Nyquist filters shape and to obtaining optimum results from the AD9762. If properly limit each component’s spectral envelope while minimizing implemented, ground planes can perform a host of functions on intersymbol interference. The DAC is typically updated at the high speed circuit boards: bypassing, shielding, current trans- QAM symbol rate or possibly a multiple of it if an interpolating port, etc. In mixed signal design, the analog and digital portions filter precedes the DAC. The use of an interpolating filter typi- of the board should be distinct from each other, with the analog cally eases the implementation and complexity of the analog ground plane confined to the areas covering the analog signal filter, which can be a significant contributor to mismatches in traces, and the digital ground plane confined to areas covering gain and phase between the two baseband channels. A quadra- the digital interconnects. ture mixer modulates the I and Q components with in-phase All analog ground pins of the DAC, reference and other analog and quadrature phase carrier frequency and then sums the two components should be tied directly to the analog ground plane. outputs to provide the QAM signal. The two ground planes should be connected by a path 1/8 to 1/4 inch wide underneath or within 1/2 inch of the DAC to 12 maintain optimum performance. Care should be taken to ensure AD9762 that the ground plane is uninterrupted over crucial signal paths. DSP 0 CARRIER TO On the digital side, this includes the digital input lines running OR Σ FREQUENCY 90 MIXER ASIC to the DAC as well as any clock signals. On the analog side, this 12 includes the DAC output signal, reference signal and the supply AD9762 feeders. NYQUIST QUADRATURE FILTERS MODULATOR The use of wide runs or planes in the routing of power lines is Figure 56. Typical Analog QAM Architecture also recommended. This serves the dual role of providing a low series impedance power supply to the part, as well as providing In this implementation, it is much more difficult to maintain some “free” capacitive decoupling to the appropriate ground proper gain and phase matching between the I and Q channels. plane. It is essential that care be taken in the layout of signal The circuit implementation shown in Figure 57 helps improve and power ground interconnects to avoid inducing extraneous upon the matching and temperature stability characteristics voltage drops in the signal ground paths. It is recommended that between the I and Q channels. Using a single voltage reference all connections be short, direct and as physically close to the derived from U1 to set the gain for both the I and Q channels package as possible in order to minimize the sharing of conduc- will improve the gain matching and stability. Further enhance- tion paths between different currents. When runs exceed an inch ments in gain matching and stability are achieved by using in length, strip line techniques with proper termination resistor separate matching resistor networks for both R and R . SET LOAD should be considered. The necessity and value of this resistor Additional trim capability via R and R can be added to CAL1 CAL2 will be dependent upon the logic family used. compensate for any initial mismatch in gain between the two channels. This may be attributed to any mismatch between U1 For a more detailed discussion of the implementation and and U2’s gain setting resistor, (R ); effective load resistance, construction of high speed, mixed signal printed circuit boards, SET (R ); and/or voltage offset of each DAC’s control amplifier. refer to Analog Devices’ application notes AN-280 and AN-333. LOAD The differential voltage outputs of U1 and U2 are fed into their respective differential inputs of a quadrature mixer via matching 50Ω filter networks. REV. B –17– AD9762 AD9762 EVALUATION BOARD General Description REFLO TO The AD9762-EB is an evaluation board for the AD9762 12-bit REFIO IOUTA U1 NYQUIST D/A converter. Careful attention to layout and circuit design I-CHANNEL FILTER FS ADJ IOUTB AND MIXER combined with a prototyping area allow the user to easily and R SET CLOCK 50�** 50�** 2k�* R R effectively evaluate the AD9762 in any application where high LOAD LOAD CLOCK R CAL1 resolution, high speed conversion is required. AVDD 50� This board allows the user the flexibility to operate the AD9762 REFLO CLOCK in various configurations. Possible output configurations include TO IOUTA REFIO NYQUIST U2 transformer coupled, resistor terminated, inverting/noninverting 0.1�F FILTER Q-CHANNEL FS ADJ IOUTB and differential amplifier outputs. The digital inputs are designed AND MIXER R SET 50�** 50�** to be driven directly from various word generators, with the 2k�* R LOAD R LOAD R on-board option to add a resistor network for proper load CAL2 * OHMTEK ORNA1001F 100� ** OHMTEK TOMC1603-50F termination. Provisions are also made to operate the AD9762 with either the internal or external reference, or to exercise the power-down feature. Figure 57. Baseband QAM Implementation Using Two AD9762s Refer to the application note AN-420 “Using the AD9760/ AD9762/AD9764-EB Evaluation Board” for a thorough It is also possible to generate a QAM signal completely in the description and operating instructions for the AD9762 digital domain via a DSP or ASIC, in which case only a single evaluation board. DAC of sufficient resolution and performance is required to reconstruct the QAM signal. Also available from several vendors are Digital ASICs which implement other digital modulation schemes such as PSK and FSK. This digital implementation has the benefit of generating perfectly matched I and Q components in terms of gain and phase, which is essential in maintaining optimum performance in a communication system. In this implementation, the reconstruction DAC must be operating at a sufficiently high clock rate to accommodate the highest specified QAM carrier frequency. Figure 58 shows a block diagram of such an implementation using the AD9762. 12 12 I DATA STEL-1130 TO LPF 12 QAM MIXER Q DATA AD9762 50� 50� 12 12 SIN COS 12 CARRIER STEL-1177 FREQUENCY NCO CLOCK Figure 58. Digital QAM Architecture REV. B –18– AD9762 Figure 59. AD9762 Evaluation Board Schematic REV. B –19– DVDD DGND AVDD AGND AVEE AVCC B1 B2 B3 B4 B5 B6 TP19 TP3 TP4 TP6 TP7 TP2 TP18 TP5 CLK TP1 J1 C3 C4 C5 C6 JP1 A A A AB 10�F 10�F 10�F 10�F EXTCLK 3 1 2 R15 DVDD DVDD 49.9� R1 R7 R5 R3 16 PINDIP U1 AVDD TP8 1 1 1 1 RES PK C7 C8 C9 P1 1�F 0.1�F 0.1�F AD976x 2 3 4 5 6 7 8 9 10 2 3 4 5 6 7 8 9 10 2 3 4 5 6 7 8 9 10 2 3 4 5 6 7 8 9 10 2 1 C19 1 16 1 28 DB13 CLOCK A 4 3 C1 2 15 2 27 DB12 DVDD 6 5 C2 3 14 3 26 DB11 DCOM 8 7 C25 4 13 4 25 DB10 NC 10 9 C26 5 12 5 24 DB9 AVDD AVDD 11 C27 6 11 6 12 23 DB8 COMP2 OUT 1 C28 7 7 22 14 13 10 DB7 IOUTA OUT 2 C29 8 21 16 15 8 9 DB6 IOUTB 18 17 20 9 DB5 ACOM 20 19 10 19 COMP1 DB4 22 21 18 11 DB3 FS ADJ 24 23 16 PINDIP 17 12 DB2 REFIO 26 25 RES PK 16 13 DB1 REFLO 28 27 14 15 DB0 SLEEP TP11 TP10 TP9 TP13 30 29 C30 1 16 32 31 A C31 2 15 R16 34 33 CT1 AVDD C32 3 14 2k� 36 35 C33 4 13 C11 C10 38 37 A TP14 C34 5 12 0.1�F 0.1�F 1 40 39 C35 6 11 C36 7 10 2 JP4 JP2 3 10 98 76 54 32 10 98 76 54 32 10 98 76 54 32 10 98 76 54 32 PDIN TP12 A A A J2 AVDD 1 1 1 1 R2 R6 R4 R8 R17 49.9� DVDD DVDD AVCC R18 1k� AVCC AVCC U7 J3 A C21 C22 R42 3 B OUT1 JP6A JP7B 0.1�F 1�F REF43 C17 JP7A 1k� U4 2 6 JP3 0.1�F VIN VOUT 2 3 J6 J7 JP8 7 A R12 C18 C16 GND C12 6 U6 R20 1 A A OPEN AD8047 0.1�F 1�F 22pF B B B 49.9� 4 3 T1 7 2 R37 R43 4 C20 A 49.9� 5k� 4 6 R10 CW A 3 0 A A AD8047 A A 1k� 2 5 A A A R14 A 4 AVEE 0 JP6B A EXTREFIN R36 1 JP5 C14 J5 1k� R45 6 1�F 1k� 3 2 1 A R13 R9 R35 A J4 OPEN A C15 1k� 1k� R44 C23 C24 OUT2 0.1�F 50� R46 0.1�F 1�F JP9 A A A 1k� B A R38 C13 A A 22pF 49.9� AVEE A A AD9762 Figure 60. Silkscreen Layer—Top Figure 61. Component Side PCB Layout (Layer 1) REV. B –20– AD9762 Figure 62. Ground Plane PCB Layout (Layer 2) Figure 63. Power Plane PCB Layout (Layer 3) REV. B –21– AD9762 Figure 64. Solder Side PCB Layout (Layer 4) Figure 65. Silkscreen Layer—Bottom REV. B –22– AD9762 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead, 300 Mil SOIC (R-28) 0.7125 (18.10) 0.6969 (17.70) 28 15 0.2992 (7.60) 0.2914 (7.40) 0.4193 (10.65) 1 14 0.3937 (10.00) PIN 1 0.1043 (2.65) 0.0291 (0.74) � 45� 0.0926 (2.35) 0.0098 (0.25) 8� 0.0500 0� 0.0118 (0.30) 0.0192 (0.49) SEATING 0.0500 (1.27) 0.0125 (0.32) (1.27) PLANE 0.0040 (0.10) 0.0138 (0.35) 0.0157 (0.40) 0.0091 (0.23) BSC 28-Lead, TSSOP (RU-28) 0.386 (9.80) 0.378 (9.60) 28 15 0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25) 1 14 PIN 1 0.006 (0.15) 0.0433 (1.10) MAX 0.002 (0.05) 8� 0.0256 (0.65) 0.0118 (0.30) 0� 0.028 (0.70) SEATING 0.0079 (0.20) BSC 0.0075 (0.19) 0.020 (0.50) PLANE 0.0035 (0.090) REV. B –23– PRINTED IN U.S.A. C2201b–1–3/00 (rev. B)