ANALOG DEVICES AD9761

® Dual 10-Bit TxDAC+ with 2 Interpolation Filters AD9761 FEATURES FUNCTIONAL BLOCK DIAGRAM Complete 10-Bit, 40 MSPS Dual Transmit DAC CLOCK DCOM DVDD ACOM AVDD Excellent Gain and Offset Matching Differential Nonlinearity Error: 0.5 LSB IOUTA I LATCH Effective Number of Bits: 9.5 2 I DAC IOUTB SLEEP Signal-to-Noise and Distortion Ratio: 59 dB REFLO Spurious-Free Dynamic Range: 71 dB FSADJ REFERENCE REFIO DAC DATA 2 Interpolation Filters INPUTS COMP1 20 MSPS/Channel Data Rate (10 BITS) BIAS COMP2 GENERATOR Single Supply: 3 V to 5.5 V COMP3 Low Power Dissipation: 93 mW (3 V Supply @ QOUTA LATCH Q 2 Q DAC 40 MSPS) QOUTB On-Chip Reference WRITE INPUT MUX AD9761 28-Lead SSOP CONTROL SELECT INPUT PRODUCT DESCRIPTION The AD9761 is a complete dual-channel, high speed, 10-bit CMOS DAC. The AD9761 has been developed specifically for PRODUCT HIGHLIGHTS use in wide bandwidth communication applications (e.g., spread 1. Dual 10-Bit, 40 MSPS DACs spectrum) where digital I and Q information is being processed A pair of high performance 40 MSPS DACs optimized for low during transmit operations. It integrates two 10-bit, 40 MSPS distortion performance provide for flexible transmission of I DACs, dual 2 interpolation filters, a voltage reference, and digi- and Q information. tal input interface circuitry. The AD9761 supports a 20 MSPS 2. 2 Digital Interpolation Filters per channel input data rate that is then interpolated by 2 up to Dual matching FIR interpolation filters with 62.5 dB stop- 40 MSPS before simultaneously updating each DAC. band rejection precede each DAC input, thus reducing the The interleaved I and Q input data stream is presented to the DACs’ reconstruction filter requirements. digital interface circuitry, which consists of I and Q latches as 3. Low Power well as some additional control logic. The data is de-interleaved Complete CMOS dual DAC function operates on a low back into its original I and Q data. An on-chip state machine 200 mW on a single supply from 3 V to 5.5 V. The DAC ensures the proper pairing of I and Q data. The data output from full-scale current can be reduced for lower power opera- each latch is then processed by a 2 digital interpolation filter tion, and a sleep mode is provided for power reduction that eases the reconstruction filter requirements. The interpo- during idle periods. lated output of each filter serves as the input of their respective 10-bit DAC. 4. On-Chip Voltage Reference The AD9761 includes a 1.20 V temperature-compensated The DACs utilize a segmented current source architecture com- band gap voltage reference. bined with a proprietary switching technique to reduce glitch energy and to maximize dynamic accuracy. Each DAC provides 5. Single 10-Bit Digital Input Bus differential current output, thus supporting single-ended or dif- The AD9761 features a flexible digital interface that allows ferential applications. Both DACs are simultaneously updated each DAC to be addressed in a variety of ways including dif- and provide a nominal full-scale current of 10 mA. Also, the ferent update rates. full-scale currents between each DAC are matched to within 6. Small Package 0.07 dB (i.e., 0.75%), thus eliminating the need for additional The AD9761 offers the complete integrated function in a gain calibration circuitry. compact 28-lead SSOP package. The AD9761 is manufactured on an advanced low cost CMOS 7. Product Family process. It operates from a single supply of 3 V to 5.5 V and The AD9761 Dual Transmit DAC has a pair of Dual Receive consumes 200 mW of power. To make the AD9761 complete, it ADC companion products, the AD9281 (8 bits) and AD9201 also offers an internal 1.20 V temperature-compensated band gap (10 bits). reference. REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. that may result from its use. No license is granted by implication or oth- Tel: 781/329-4700 www.analog.com erwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved. AD9761 AD9761–SPECIFICATIONS (T to T , AVDD = 5 V, DVDD = 5 V, I = 10 mA, unless otherwise noted.) DC SPECIFICATIONS MIN Max OUTFS Parameter Min Typ Max Unit RESOLUTION 10 Bits 1 DC ACCURACY Integral Nonlinearity Error (INL) T = 25°C –1.75 ±0.5 +1.75 LSB A T to T –2.75 ±0.7 +2.75 LSB MIN MAX Differential Nonlinearity (DNL) T = 25°C –1 ±0.4 +1.25 LSB A T to T –1 ±0.5 +1.75 LSB MIN MAX Monotonicity (10-Bit) Guaranteed over Rated Specification Temperature Range ANALOG OUTPUT Offset Error –0.05 ±0.025 +0.05 % of FSR Offset Matching between DACs –0.10 ±0.05 +0.10 % of FSR Gain Error (without Internal Reference) –5.5 ±1.0 +5.5 % of FSR Gain Error (with Internal Reference) –5.5 ±1.0 +5.5 % of FSR Gain Matching between DACs –1.0 ±0.25 +1.0 % of FSR 2 Full-Scale Output Current 10 mA Output Compliance Range –1.0 +1.25 V Output Resistance 100 k Output Capacitance 5 pF REFERENCE OUTPUT Reference Voltage 1.14 1.20 1.26 V 3 Reference Output Current 100 nA REFERENCE INPUT Input Compliance Range 0.1 1.25 V Reference Input Resistance 1 M TEMPERATURE COEFFICIENTS Unipolar Offset Drift 0 ppm/°C Gain Drift (without Internal Reference) ±50 ppm/°C Gain Drift (with Internal Reference) ±140 ppm/°C Gain Matching Drift (between DACs) ±25 ppm/°C Reference Voltage Drift ±50 ppm/°C POWER SUPPLY AVDD Voltage Range 3.0 5.0 5.5 V Analog Supply Current (I ) 26 29 mA AVDD DVDD Voltage Range 2.7 5.0 5.5 V 4 Digital Supply Current at 5 V (I ) 15 18 mA DVDD 4 Digital Supply Current at 3 V (I ) 5 mA DVDD 5 Nominal Power Dissipation AVDD and DVDD at 3 V 93 mW AVDD and DVDD at 5 V 200 250 mW Power Supply Rejection Ratio (PSRR)–AVDD –0.25 +0.25 % of FSR/V Power Supply Rejection Ratio (PSRR)–DVDD –0.02 +0.02 % of FSR/V OPERATING RANGE –40 +85 °C NOTES 1 Measured at IOUTA and QOUTA, driving a virtual ground. 2 Nominal full-scale current, I , is 16 the I current. OUTFS REF 3 Use an external amplifier to drive any external load. 4 Measured at f = 40 MSPS and f = 1 MHz. CLOCK OUT 5 Measured as unbuffered voltage output into 50  R at IOUTA, IOUTB, QOUTA, and QOUTB; f = 40 MSPS and f = 8 MHz. LOAD CLOCK OUT Specifications subject to change without notice. –2– REV. C REV. C –3– AD9761 AD9761–SPECIFICATIONS (T to T , AVDD = 5 V, DVDD = 5 V, I = 10 mA, Differential Transformer Coupled Output, MIN MAX OUTFS DYNAMIC SPECIFICATIONS 50  Doubly Terminated, unless otherwise noted.) Parameter Min Typ Max Unit DYNAMIC PERFORMANCE Maximum Output Update Rate 40 MSPS Output Settling Time (t to 0.025%) 35 ns ST Output Propagation Delay (t ) 55 Input Clock Cycles PD Glitch Impulse 5 pV-s Output Rise Time (10% to 90%) 2.5 ns Output Fall Time (10% to 90%) 2.5 ns AC LINEARITY TO NYQUIST Signal-to-Noise and Distortion (SINAD) f = 1 MHz; CLOCK = 40 MSPS 56 59 dB OUT Effective Number of Bits (ENOBs) 9.0 9.5 Bits Total Harmonic Distortion (THD) f = 1 MHz; CLOCK = 40 MSPS OUT T = 25°C –68 –58 dB A T to T –67 –53 dB MIN MAX Spurious-Free Dynamic Range (SFDR) f = 1 MHz; CLOCK = 40 MSPS; 10 MHz Span 59 68 dB OUT Channel Isolation f = 8 MHz; CLOCK = 40 MSPS; 10 MHz Span 90 dBc OUT Specifications subject to change without notice. (T to T , AVDD = 5 V, DVDD = 5 V, I = 10 mA unless otherwise noted.) DIGITAL SPECIFICATIONS MIN MAX OUTFS Parameter Min Typ Max Unit DIGITAL INPUTS Logic 1 Voltage @ DVDD = 5 V 3.5 5 V Logic 1 Voltage @ DVDD = 3 V 2.4 3 V Logic 0 Voltage @ DVDD = 5 V 0 1.3 V Logic 0 Voltage @ DVDD = 3 V 0 0.9 V Logic 1 Current –10 +10 µA Logic 0 Current –10 +10 µA Input Capacitance 5 pF Input Setup Time (t ) 3 ns S Input Hold Time (t ) 2 ns H CLOCK High 5 ns CLOCK Low 5 ns Invalid CLOCK/WRITE Window (t )* 1 5 ns CINV *t is an invalid window of 4 ns duration beginning 1 ns after the rising edge of WRITE in which the rising edge of CLOCK must not occur. CINV Specifications subject to change without notice. t H t S DB9–DB0 I DATA Q DATA DAC INPUTS SELECT NOTE: WRITE AND CLOCK CAN BE WRITE TIED TOGETHER. FOR TYPICAL EXAMPLES, REFER TO DIGITAL INPUTS AND INTERLEAVED INTERFACE CONSIDERATION SECTION. CLOCK t CINV Figure 1. Timing Diagram –2– REV. C REV. C –3– AD9761 AD9761 (T to T , AVDD = 2.7 V to 5.5 V, DVDD = 2.7 V to 5.5 V, I = 10 mA, unless MIN MAX OUTFS otherwise noted.) DIGITAL FILTER SPECIFICATIONS Parameter Min Typ Max Unit MAXIMUM INPUT CLOCK RATE (f ) 40 MSPS CLOCK DIGITAL FILTER CHARACTERISTICS 1 Pass Bandwidth : 0.005 dB 0.2010 f /f OUT CLOCK Pass Bandwidth: 0.01 dB 0.2025 f /f OUT CLOCK Pass Bandwidth: 0.1 dB 0.2105 f /f OUT CLOCK Pass Bandwidth: –3 dB 0.239 f /f OUT CLOCK Linear Phase (FIR Implementation) Stop-Band Rejection: 0.3 f to 0.7 f –62.5 dB CLOCK CLOCK 2 Group Delay 32 Input Clock Cycles 3 Impulse Response Duration –40 dB 28 Input Clock Cycles –60 dB 40 Input Clock Cycles NOTES 1 Excludes SINx/x characteristic of DAC. 2 Defined as the number of data clock cycles between impulse input and peak of output response. 3 55 input clock periods from input to I DAC, 56 to Q DAC. Propagation delay is delay from data input to DAC update. Specifications subject to change without notice. 0 Table I. Integer Filter Coefficients for 43-Tap Half-Band FIR Filter –20 Lower Coefficient Upper Coefficient Integer Value H(1) H(43) 1 –40 H(2) H(42) 0 H(3) H(41) –3 –60 H(4) H(40) 0 H(5) H(39) 8 –80 H(6) H(38) 0 H(7) H(37) –16 –100 H(8) H(36) 0 H(9) H(35) 29 –120 0 0.1 0.2 0.3 0.4 0.5 H(10) H(34) 0 FREQUENCY RESPONSE (DC to f /2) CLOCK H(11) H(33) –50 H(12) H(32) 0 Figure 2a. FIR Filter Frequency Response H(13) H(31) 81 1 H(14) H(30) 0 0.9 H(15) H(29) –131 0.8 H(16) H(28) 0 0.7 H(17) H(27) 216 0.6 H(18) H(26) 0 0.5 H(19) H(25) –400 0.4 H(20) H(24) 0 0.3 H(21) H(23) 1264 0.2 H(22) 1998 0.1 0 –0.1 –0.2 –0.3 0 5 10 15 20 25 30 35 40 TIME (Samples) Figure 2b. FIR Filter Impulse Response –4– REV. C REV. C –5– OUTPUT (dBFS) NORMALIZED OUTPUT AD9761 AD9761 THERMAL CHARACTERISTICS ORDERING GUIDE Thermal Resistance Package Package 28-Lead SSOP Model Description Option q = 109°C/W JA AD9761ARS 28-Lead Shrink Small Outline (SSOP) RS-28 AD9761ARSRL 28-Lead Shrink Small Outline (SSOP) RS-28 AD9761-EB Evaluation Board ABSOLUTE MAXIMUM RATINGS* With Parameter Respect to Min Max Unit AVDD ACOM –0.3 +6.5 V DVDD DCOM –0.3 +6.5 V ACOM DCOM –0.3 +0.3 V AVDD DVDD –6.5 +6.5 V CLOCK, WRITE DCOM –0.3 DVDD + 0.3 V SELECT, SLEEP DCOM –0.3 DVDD + 0.3 V Digital Inputs DCOM –0.3 DVDD + 0.3 V IOUTA, IOUTB ACOM –1.0 AVDD + 0.3 V QOUTA, QOUTB ACOM –1.0 AVDD + 0.3 V COMP1, COMP2 ACOM –0.3 AVDD + 0.3 V COMP3 ACOM –0.3 AVDD + 0.3 V REFIO, FSADJ ACOM –0.3 AVDD + 0.3 V REFLO ACOM –0.3 +0.3 V Junction Temperature 150 °C Storage Temperature –65 +150 °C Lead Temperature (10 sec) 300 °C *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. 3V TO 5.5V 2.7V TO 5.5V 0.1F 0.1F 0.1F COMP2 AVDD AVSS COMP1 COMP3 MINI-CIRCUITS DVDD DCOM T1-1T IOUTA I TO HP3589A LATCH 100 2x IOUTB DAC I SPECTRUM/NETWORK ANALYZER REFLO 50 INPUT TEKTRONIX 20pF 20pF 50 50 AWG-2021 REFIO DIGITAL 0.1F DB9–DB0 AD9761 DATA FSADJ R SET MINI-CIRCUITS 2k T1-1T QOUTA Q TO HP3589A LATCH CLOCK 2x QOUTB 100 Q DAC SPECTRUM/NETWORK OUT MARKER 1 ANALYZER SELECT 50 INPUT MUX WRITE 20pF 20pF 50 50 CONTROL RETIMED CLOCK SLEEP CLOCK OUTPUT* *AWG2021 CLOCK RETIMED SUCH THAT DIGITAL DATA TRANSITIONS ON FALLING EDGE OF 50% DUTY CYCLE CLOCK. LE CROY 9210 PULSE GENERATOR Figure 3. Basic AC Characterization Test Setup CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9761 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –4– REV. C REV. C –5– AD9761 AD9761 PIN CONFIGURATION 28 (MSB) DB9 1 RESET/SLEEP DB8 2 27 COMP1 DB7 3 26 IOUTA DB6 4 25 IOUTB DB5 5 24 ACOM AD9761 DB4 6 23 AVDD TOP VIEW (Not to Scale) DB3 7 22 COMP2 DB2 8 21 FSADJ DB1 9 20 REFIO (LSB) DB0 10 19 REFLO CLOCK 11 18 QOUTB WRITE 12 17 QOUTA SELECT 13 16 COMP3 DVDD 14 15 DCOM PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Description 1 DB9 Most Significant Data Bit (MSB). 2–9 DB8–DB1 Data Bits 1–8. 10 DB0 Least Significant Data Bit (LSB). 11 CLOCK Clock Input. Both DACs’ outputs updated on positive edge of clock and digital filters read respective input registers. 12 WRITE Write Input. DAC input registers latched on positive edge of write. 13 SELECT Select Input. Select high routes input data to I DAC; select low routes data to Q DAC. 14 DVDD Digital Supply Voltage (2.7 V to 5.5 V). 15 DCOM Digital Common. 16 COMP3 Internal Bias Node for Switch Driver Circuitry. Decouple to ACOM with 0.1 µF capacitor. 17 QOUTA Q DAC Current Output. Full-scale current when all data bits are 1s. 18 QOUTB Q DAC Complementary Current Output. Full-scale current when all data bits are 0s. 19 REFLO Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal reference. 20 REFIO Reference Input/Output. Serves as reference input when internal reference disabled. Serves as 1.2 V reference output when internal reference activated. Requires 0.1 µF capacitor to ACOM when internal reference activated. 21 FSADJ Full-Scale Current Output Adjust. Resistance to ACOM sets full-scale output current. 22 COMP2 Bandwidth/Noise Reduction Node. Add 0.1 µF to AVDD for optimum performance. 23 AVDD Analog Supply Voltage (3 V to 5.5 V). 24 ACOM Analog Common. 25 IOUTB I DAC Complementary Current Output. Full-scale current when all data bits are 0s. 26 IOUTA I DAC Current Output. Full-scale current when all data bits are 1s. 27 COMP1 Internal Bias Node for Switch Driver Circuitry. Decouple to AGND with 0.1 µF capacitor. 28 RESET/SLEEP Power-Down Control Input if Asserted for Four Clock Cycles or Longer. Reset control input if asserted for less than four clock cycles. Active high. Connect to DCOM if not used. Refer to RESET/ SLEEP Mode Operation section. –6– REV. C REV. C –7– AD9761 AD9761 DEFINITIONS OF SPECIFICATIONS Channel Isolation Linearity Error Channel Isolation is a measure of the level of crosstalk between (Also Called Integral Nonlinearity or INL) channels. It is measured by producing a full-scale 8 MHz signal Linearity error is defined as the maximum deviation of the output for one channel and measuring the leakage into the other actual analog output from the ideal output, determined by a channel. straight line drawn from zero to full scale. Spurious-Free Dynamic Range Differential Nonlinearity (DNL) The difference, in dB, between the rms amplitude of the output DNL is the measure of the variation in analog value, normalized signal and the peak spurious signal over the specified bandwidth. to full scale, associated with a 1 LSB change in digital input code. Total Harmonic Distortion Monotonicity THD is the ratio of the sum of the rms value of the first six A D/A converter is monotonic if the output either increases or harmonic components to the rms value of the measured output remains constant as the digital input increases. signal. It is expressed as a percentage or in decibels (dB). Offset Error Signal-to-Noise and Distortion (S/N+D, SINAD) Ratio The deviation of the output current from the ideal of zero is S/N+D is the ratio of the rms value of the measured output called offset error. For IOUTA, 0 mA output is expected when signal to the rms sum of all other spectral components below the the inputs are all 0s. For IOUTB, 0 mA output is expected when Nyquist frequency, including harmonics but excluding dc. The all inputs are set to 1s. value for S/N+D is expressed in decibels. Gain Error Effective Number of Bits (ENOB) The difference between the actual and ideal output span. The For a sine wave, SINAD can be expressed in terms of the number actual span is determined by the output when all inputs are set to of bits. Using the following formula, 1s minus the output when all inputs are set to 0s. N = (SINAD – 1.76)/6.02 Output Compliance Range it is possible to get a measure of performance expressed as N, the The range of allowable voltage at the output of a current-output effective number of bits. DAC. Operation beyond the maximum compliance limits may Thus, effective number of bits for a device for sine wave inputs cause either output stage saturation or breakdown, resulting in at a given input frequency can be calculated directly from its nonlinear performance. measured SINAD. Temperature Drift Pass Band Temperature drift is specified as the maximum change from the Frequency band in which any input applied therein ambient (25°C) value to the value at either T or T . For MIN MAX passes unattenuated to the DAC output. offset and gain drift, the drift is reported in ppm of full-scale range (FSR) per °C. For reference drift, the drift is reported in Stop-Band Rejection ppm per °C. The amount of attenuation of a frequency outside the pass band applied to the DAC, relative to a full-scale signal applied at the Power Supply Rejection DAC input within the pass band. The maximum change in the full-scale output as the supplies are varied from nominal to minimum and maximum specified Group Delay voltages. Number of input clocks between an impulse applied at the device input and peak DAC output current. Settling Time The time required for the output to reach and remain within a Impulse Response specified error band about its final value, measured from the start Response of the device to an impulse applied to the input. of the output transition. Glitch Impulse Asymmetrical switching times in a DAC give rise to undesired output transients that are quantified by a glitch impulse. It is specified as the net area of the glitch in pV-s. –6– REV. C REV. C –7– AD9761—Typical Performance Characteristics AD9761 Typical AC Characterization Curves @ 5 V Supplies (AVDD = 5 V, DVDD = 5 V, 50  Doubly Terminated Load, T = 25C, f = 40 MSPS, unless otherwise noted, worst of I or Q output A CLOCK performance shown.) 10.50 65 80 0 –10 –20 DIFF –6dBFS –30 9.67 60 DIFF 0dBFS 75 –40 S/E –6dBFS –50 S/E 0dBFS S/E 0dBFS –60 55 8.84 70 DIFF –6dBFS –70 –80 S/E –6dBFS DIFF 0dBFS –90 8.01 –100 50 65 START: 0Hz STOP: 40MHz 0 5.0 10.0 0 2.0 4.0 6.0 8.0 10.0 f (MHz) f (MHz) OUT OUT TPC 3. SFDR vs. f (DC to f /2) TPC 1. Single-Tone SFDR (DC TPC 2. SINAD (ENOBs) vs. OUT DATA to 2 f , f = 2 f ) f (DC to f /2) OUT DATA DATA CLOCK DATA 75 80 80 SFDR @ 40MSPS SFDR @ 40MSPS 75 75 70 SFDR @ 20MSPS 70 70 SFDR @ 20MSPS DIFF –6dBFS 65 65 SFDR @ 10MSPS SFDR @ 10MSPS 65 60 60 DIFF 0dBFS 55 55 60 50 50 S/E 0dBFS 45 SINAD @ 40MSPS 45 SINAD @ 40MSPS 55 SINAD @ 20MSPS SINAD @ 20MSPS 40 40 SINAD @ 10MSPS SINAD @ 10MSPS S/E –6dBFS 50 35 35 0 2.0 4.0 6.0 8.0 10.0 –30 –25 –20 –15 –10 –5 –0 –30 –25 –20 –15 –10 –5 0 A (dBFS) f (MHz) A (dBFS) OUT OUT OUT TPC 4. Out-of-Band SFDR vs. TPC 5. SINAD vs. A (DC to TPC 6. SINAD vs. A (DC to OUT OUT f (f /2 to 3/2 f ) f /2, Differential Output) f /2, Single-Ended Output) DATA OUT DATA DATA DATA 80 80 –45 SFDR @ 2.5mA SFDR @ 5mA –55 75 75 SFDR @ 10mA –65 SFDR @ 10mA 70 70 SFDR @ 5mA –75 SFDR @ 2.5mA 65 65 SINAD @ 2.5mA –85 SINAD @ 5mA SINAD @ 5mA SINAD @ 2.5mA SINAD @ 10mA 60 60 –95 SINAD @ 10mA 55 55 –105 2 4 6 8 10 2 4 6 8 10 0 START: 0Hz 0 STOP: 20MHz f (MHz) f (MHz) OUT OUT TPC 7. SINAD/SFDR vs. I TPC 8. SINAD/SFDR vs. I TPC 9. Wideband Spread- OUTFS OUTFS (DC to f /2, Differential Output) (DC to f /2, Single-Ended Output) Spectrum Spectral Plot (DC to f ) DATA DATA DATA –8– REV. C REV. C –9– dB dB 10dB (Div) dB dB dB ENOB 10dB (Div) dB dB AD9761—Typical Performance Characteristics AD9761 Typical AC Characterization Curves @ 3 V Supplies (AVDD = 3 V, DVDD = 3 V, 50  Doubly Terminated Load, T = 25C, f = 10 MSPS, unless otherwise noted, worst of I or Q output A CLOCK performance shown.) 65 10.50 0 85 –10 DIFF –6dBFS 80 S/E –6dBFS –20 DIFF 0dBFS –30 60 9.67 75 S/E 0dBFS –40 –50 70 –60 55 DIFF –6dBFS 8.84 DIFF 0dBFS –70 65 S/E –6dBFS S/E 0dBFS –80 –90 50 8.01 60 START: 0Hz STOP: 10MHz 0 0.5 1.0 1.5 2.0 2.5 0 0.5 1.0 1.5 2.0 2.5 f (MHz) f (MHz) OUT OUT TPC 10. Single-Tone SFDR (DC to TPC 11. SINAD (ENOBs) vs. f TPC 12. SFDR vs. f (DC to f /2) OUT OUT DATA 2 f , f = 2 f ) (DC to f /2) DATA CLOCK DATA DATA 80 80 75 SFDR @ 20MSPS SFDR @ 20MSPS 75 DIFF –6dBFS 70 SFDR @ 10MSPS SFDR @ 10MSPS 70 65 S/E 0dBFS 75 65 60 SFDR @ 40MSPS SFDR @ 40MSPS 60 55 70 S/E –6dBFS 55 50 DIFF 0dBFS 50 45 SINAD @ 40MSPS SINAD @ 20MSPS 65 45 SINAD @ 40MSPS 40 SINAD @ 10MSPS SINAD @ 20MSPS 40 SINAD @ 10MSPS 35 35 60 30 –30 –25 –20 –15 –10 –5 0 0 0.5 1.0 1.5 2.0 2.5 –30 –25 –20 –15 –10 –5 0 A (dBFS) OUT f (MHz) A (dBFS) OUT OUT TPC 13. Out-of-Band SFDR vs. TPC 14. SINAD vs. A (DC to TPC 15. SINAD vs. A (DC to OUT OUT f (f /2 to 3/2f ) f /2, Differential Output) f /2, Single-Ended Output) OUT DATA DATA DATA DATA 80 80 0 SFDR @ 10mA SFDR @ 5mA –10 75 75 SFDR @ 10mA –20 70 –30 70 SFDR @ 2.5mA SFDR @ 5mA –40 SFDR @ 2.5mA 65 65 SINAD @ 5mA –50 SINAD @ 2.5mA SINAD @ 10mA SINAD @ 5mA SINAD @ 2.5mA –60 SINAD @ 10mA 60 60 –70 55 55 –80 0 2 4 6 8 10 2 4 6 8 10 0 START: 0Hz STOP: 10MHz f (MHz) f (MHz) OUT OUT TPC 16. SINAD/SFDR vs. I TPC 18. Narrow-Band Spread- OUTFS TPC 17. SINAD/SFDR vs. I OUTFS (DC to f /2, Differential Output) Spectrum Spectral Plot (DC to f ) DATA (DC to f /2, Single-Ended Output) DATA DATA –8– REV. C REV. C –9– dB dB 10dB (Div) dB dB dB ENOB dB dB 10dB (Div) AD9761 AD9761 FUNCTIONAL DESCRIPTION Each DAC consists of a large PMOS current source array capable Figure 4 shows a simplified block diagram of the AD9761. The of providing up to 10 mA of full-scale current, I . Each array is OUTFS AD9761 is a complete dual-channel, high speed, 10-bit CMOS divided into 15 equal currents that make up the four most signifi- DAC capable of operating up to a 40 MHz clock rate. It has cant bits (MSBs). The next four bits or middle bits consist of 15 been optimized for the transmit section of wideband communica- equal current sources whose values are 1/16 of an MSB current tion systems employing I and Q modulation schemes. Excellent source. The remaining LSBs are binary weighted fractions of matching characteristics between channels reduce the need for the middle bits’ current sources. All of these current sources are any external calibration circuitry. Dual matching 2 interpola- switched to one of two output nodes (i.e., IOUTA or IOUTB) tion filters included in the I and Q data path simplify any post via PMOS differential current switches. band-limiting filter requirements. The AD9761 interfaces with a The full-scale output current, I , of each DAC is regulated OUTFS single 10-bit digital input bus that supports interleaved I and Q from the same voltage reference and control amplifier, thus input data. ensuring excellent gain matching and drift characteristics between DACs. I can be set from 1 mA to 10 mA via an CLOCK OUTFS DCOM DVDD ACOM AVDD external resistor, R . The external resistor in combination SET IOUTA with both the reference control amplifier and voltage reference, I LATCH 2 I DAC IOUTB V , sets the reference current, I , which is mirrored over SLEEP REFIO REF REFLO to the segmented current sources with the proper scaling factor. FSADJ REFERENCE I is exactly 16 times the value of I . OUTFS REF REFIO DAC DATA INPUTS COMP1 The I and Q DACs are simultaneously updated on the rising (10 BITS) BIAS COMP2 GENERATOR edge of CLOCK with digital data from their respective 2 COMP3 digital interpolation filters. The 2 interpolation filters essen- QOUTA LATCH Q 2 tially multiply the input data rate of each DAC by a factor of Q DAC QOUTB 2, relative to its original input data rate, while simultaneously WRITE INPUT MUX reducing the magnitude of the first image associated with the AD9761 CONTROL SELECT INPUT DAC’s original input data rate. Since the AD9761 supports a single 10-bit digital bus with interleaved I and Q input data, the original I and Q input data rate before interpolation is one-half Figure 4. Dual DAC Functional Block Diagram the CLOCK rate. After interpolation, the data rate into each I Referring to Figure 4, the AD9761 consists of an analog sec- and Q DAC becomes equal to the CLOCK rate. tion and a digital section. The analog section includes matched The benefits of an interpolation filter are illustrated in Figure 5, I and Q 10-bit DACs, a 1.20 V band gap voltage reference, and which shows an example of the frequency and time domain rep- a reference control amplifier. The digital section includes two 2 resentation of a discrete time sine wave signal before and after interpolation filters, segment decoding logic, and some additional it is applied to a digital interpolation filter. Images of the sine digital input interface circuitry. The analog and digital sections of wave signal appear around multiples of the DAC’s input data the AD9761 have separate power supply inputs (i.e., AVDD and rate as predicted by the sampling theory. These undesirable DVDD) that can operate independently. The digital supply can images will also appear at the output of a reconstruction DAC, operate over a 2.7 V to 5.5 V range, allowing it to accommodate although modified by the DAC’s sin(x)/(x) response. In many TTL as well as 3.3 V and 5 V CMOS logic families. The analog band-limited applications, these images must be suppressed by supply must be restricted from 3.0 V to 5.5 V to maintain opti- an analog filter following the DAC. The complexity of this ana- mum performance. TIME DOMAIN 2 1 f f CLOCK CLOCK ST FUNDAMENTAL 1 IMAGE FUNDAMENTAL DIGITAL SIN(X) DACs FILTER X NEW 1ST IMAGE FREQUENCY DOMAIN SUPPRESSED f f f f f f CLOCK CLOCK CLOCK CLOCK CLOCK CLOCK OLD ST 2 1 IMAGE 2 2 2 INTERPOLATION FILTER INPUT DATA LATCH DAC 2 f f CLOCK CLOCK 2 Figure 5. Time and Frequency Domain Example of Digital Interpolation Filter –10– REV. C REV. C –11– AD9761 AD9761 log filter is typically determined by the proximity of the desired IOUTA or IOUTB. The single-ended voltage output appearing fundamental to the first image and the required amount of image at IOUTA and IOUTB pins is simply suppression. V = I × R (5) IOUTA OUTA LOAD Referring to Figure 5, the “new” first image associated with the V = I × R (6) IOUTB OUTB LOAD DAC’s higher data rate after interpolation is “pushed” out fur- ther relative to the input signal. The “old” first image associated Note that the full-scale value of V and V should not IOUTA IOUTB with the lower DAC data rate before interpolation is suppressed exceed the specified output compliance range to maintain speci- by the digital filter. As a result, the transition band for the analog fied distortion and linearity performance. reconstruction filter is increased, thus reducing the complexity The differential voltage, V , appearing across IOUTA and IDIFF of the analog filter. IOUTB is The digital interpolation filters for I and Q paths are identi- V = I – I × R (7) ( ) IDIFF IOUTA IOUTB LOAD cal 43-tap half-band symmetric FIR filters. Each filter receives de-interleaved I or Q data from the digital input interface. The Substituting the values of I , I , and I , V can be IOUTA IOUTB REF IDIFF input CLOCK signal is internally divided by 2 to generate the expressed as filter clock. The filters are implemented with two parallel paths V = (2 DAC CODE –1023)/1024) × { } IDIFF running at the filter clock rate. The output from each path is 16 R /R × V (8) ( ) LOAD SET REFIO selected on opposite phases of the filter clock, thus producing interpolated filtered output data at the input clock rate. The These last two equations highlight some of the advantages of frequency response and impulse response of these filters are operating the AD9761 differentially. First, differential opera- shown in Figures 2a and 2b. Table I lists the idealized filter tion will help cancel common-mode error sources associated coefficients that correspond to the filter’s impulse response. with I and I , such as noise and distortion. Second, IOUTA IOUTB the differential code-dependent current and subsequent volt- The digital section of the AD9761 also includes an input interface age, V , is twice the value of the single-ended voltage output section designed to support interleaved I and Q input data from IDIFF (i.e., V or V ), thus providing twice the signal power to a single 10-bit bus. This section de-interleaves the I and Q input IOUTA IOUTB the load. data while ensuring its proper pairing for the 2 interpolation filters. A RESET/SLEEP input serves a dual function by providing REFERENCE OPERATION a reset function for this section as well as providing power-down The AD9761 contains an internal 1.20 V band gap reference that functionality. Refer to the Digital Inputs and Interleaved Interface can be easily disabled and overridden by an external reference. Considerations and RESET/SLEEP Mode Operation sections for REFIO serves as either an input or output depending on whether a more detailed discussion. the internal or an external reference is selected. If REFLO is tied to ACOM as shown in Figure 6, the internal reference is activated DAC TRANSFER FUNCTION and REFIO provides a 1.20 V output. In this case, the internal ref- Each I and Q DAC provides complementary current output erence must be filtered externally with a ceramic chip capacitor of pins: IOUT(A/B) and QOUT(A/B), respectively. Note that 0.1 µF or greater from REFIO to REFLO. Also, REFIO should be QOUTA and QOUTB operate identically to IOUTA and buffered with an external amplifier having a low input bias current IOUTB. IOUTA will provide a near full-scale current output, (i.e., <1 µA) if any additional loading is required. I , when all bits are high (i.e., DAC CODE = 1023), while OUTFS IOUTB, the complementary output, provides no current. The 0.1F current outputs of IOUTA and IOUTB are a function of both OPTIONAL EXTERNAL the input code and I and can be expressed as REF BUFFER FOR OUTFS ADDITIONAL LOADS REFLO COMP2 AVDD I = DAC CODE/1024 × I (1) ( ) OUTA OUTFS 50pF +1.2V REF (2) I = 1023 – DAC CODE /1024× I ( ) OUTB OUTFS REFIO CURRENT where: 0.1F SOURCE FSADJ ARRAY DAC CODE = 0 to 1023 (i.e., decimal representation). R SET 2k COMPENSATION As previously mentioned, I is a function of the reference CAPACITOR OUTFS AD9761 REQUIRED current, I , which is nominally set by a reference, V , and REF REFIO external resistor, R . It can be expressed as SET Figure 6. Internal Reference Configuration (3) I = 16× I OUTFS REF The internal reference can also be disabled by connecting where: REFLO to AVDD. In this case, an external reference may then be applied to REFIO as shown in Figure 7. The external reference (4) I =V /R REF REFIO SET may provide either a fixed reference voltage to enhance accura- The two current outputs will typically drive a resistive load cy and drift performance or a varying reference voltage for gain directly or via a transformer. If dc coupling is required, IOUTA control. Note that the 0.1 µF compensation capacitor is not and IOUTB should be directly connected to matching resistive required since the internal reference is disabled and the high loads, R , which are tied to analog common, ACOM. Note LOAD input impedance (i.e., 1 M) of REFIO minimizes any loading that R represents the equivalent load resistance seen by LOAD of the external reference. –10– REV. C REV. C –11– AD9761 AD9761 AVDD Depending on the requirements of the application, I REF can be adjusted by varying either R , or, in the external SET 0.1F reference mode, by varying the REFIO voltage. I can be REF varied for a fixed R by disabling the internal reference and SET REFLO COMP2 AVDD varying the voltage of REFIO over its compliance range of AVDD 50pF 1.25 V to 0.10 V. REFIO can be driven by a single-supply +1.2V REF amplifier or DAC, thus allowing I to be varied for a fixed REF REFIO EXT. – CURRENT V R . Since the input impedance of REFIO is approximately SET REF SOURCE FSADJ + ARRAY 1 M, a simple, low cost R-2R ladder DAC configured in R SET I = REF the voltage mode topology may be used to control the gain. V /R REF SET This circuit is shown in Figure 8 using the AD7524 and an AD9761 external 1.2 V reference, the AD1580. Figure 7. External Reference Configuration ANALOG OUTPUTS As previously stated, both the I and Q DACs produce two REFERENCE CONTROL AMPLIFIER complementary current outputs that may be configured for The AD9761 also contains an internal control amplifier that is single-ended or differential operation. I and I can be IOUTA IOUTB used to simultaneously regulate both DACs’ full-scale output converted into complementary single-ended voltage outputs, current, I . Since the I and Q I are derived from OUTFS OUTFS V and V , via a load resistor, R , as described in IOUTA IOUTB LOAD the same voltage reference and control circuitry, excellent the DAC Transfer Function section by Equations 5 through gain matching is ensured. The control amplifier is configured 8. The differential voltage, V , existing between V IDIFF IOUTA as a V-I converter as shown in Figure 7 such that its current and V , can also be converted to a single-ended voltage IOUTB output, I , is determined by the ratio of the V and an REF REFIO via a transformer or differential amplifier configuration. external resistor, R , as stated in Equation 4. I is copied SET REF Figure 9 shows an equivalent circuit of the AD9761’s I (or Q) over to the segmented current sources with the proper scaling DAC output. It consists of a parallel array of PMOS current factor to set I as stated in Equation 3. OUTFS sources in which each current source is switched to either The control amplifier allows a wide (10:1) adjustment span IOUTA or IOUTB via a differential PMOS switch. As a result, of I over a 1 mA to 10 mA range by setting I between OUTFS REF the equivalent output impedance of IOUTA and IOUTB 62.5 µA and 625 µA. The wide adjustment span of I OUTFS remains quite high (i.e., >100 k and 5 pF). provides several application benefits. The first benefit relates directly to the power dissipation of the AD9761’s analog AD9761 AVDD supply, AVDD, which is proportional to I (refer to the OUTFS Power Dissipation section). The second benefit relates to the 20 dB adjustment span, which may be useful for system gain control purposes. Optimum noise and dynamic performance for the AD9761 is IOUTA IOUTB obtained with a 0.1 µF external capacitor installed between COMP2 and AVDD. The bandwidth of the reference control R R LOAD LOAD amplifier is limited to approximately 5 kHz with a 0.1 µF capacitor installed. Since the –3 dB bandwidth corresponds to the dominant pole and therefore its dominant time con- Figure 9. Equivalent Circuit of the AD9761 DAC Output stant, the settling time of the control amplifier to a stepped IOUTA and IOUTB have a negative and positive voltage reference input response can be easily determined. Note that compliance range that must be adhered to achieve optimum the output of the control amplifier, COMP2, is internally performance. The negative output compliance range of –1 V is compensated via a 50 pF capacitor, thus ensuring its stabil- set by the breakdown limits of the CMOS process. Operation ity if no external capacitor is added. beyond this maximum limit may result in a breakdown of the output stage. AVDD OPTIONAL BAND LIMITING CAPACITOR AVDD REFLO COMP2 AVDD 50pF R V +1.2V REF FB DD 1.2V OUT1 AD7524 AD1580 0.1V TO 1.2V REFIO OUT2 V CURRENT REF – AGND SOURCE FSADJ + ARRAY R SET I = REF V /R REF SET DB7–DB0 AD9761 Figure 8. Single-Supply Gain Control Circuit –12– REV. C REV. C –13– AD9761 AD9761 The positive output compliance range is slightly dependent on the AD9761. If SELECT is low around the rising edge the full-scale output current, I . It degrades slightly from of WRITE, the data is latched into the Q register of the OUTFS its nominal 1.25 V for an I = 10 mA to 1.00 V for an AD9761. If SELECT is kept in one state while data is OUTFS I = 2 mA. Applications requiring the AD9761’s output repeatedly writing to the AD9761, the data will be written OUTFS (i.e., V and/or V ) to extend to its output compliance into the selected filter register at half the input data rate OUTA OUTB range should size R accordingly. Operation beyond this since the data is always assumed to be interleaved. LOAD compliance range will adversely affect the AD9761’s linearity The state machine controls the generation of the divided performance and subsequently degrade its distortion perfor- clock and thus pairing of I and Q data inputs. After the mance. Note that the optimum distortion performance of AD9761 is reset, the state machine keeps track of the paired the AD9761 is obtained by restricting its output(s) as seen at I and Q data. The state transition diagram is shown in Fig- IOUT(A/B) and QOUT(A/B) to within ±0.5 V. ure 11, in which all states are defined. A transition in state occurs upon the rising edge of CLOCK and is a function DIGITAL INPUTS AND INTERLEAVED INTERFACE of the current state as well as status of SELECT, WRITE, CONSIDERATIONS and SLEEP. The state machine is reset on the first rising The AD9761 digital interface consists of 10 data input pins, CLOCK edge while RESET remains high. Upon RESET a clock input pin, and three control pins. It is designed to returning low, a state transition will occur on the first rising support a clock rate up to 40 MSPS. The 10-bit parallel edge of CLOCK. The most recent I and Q data samples data inputs follow standard positive binary coding, where are transferred to the correct interpolation filter only upon DB9 is the most significant bit (MSB) and DB0 is the entering state FILTER DATA. least significant bit (LSB). IOUTA (or QOUTA) produces Note that it is possible to ensure proper pairing of I and Q data a full-scale output current when all data bits are at Logic 1. inputs without issuing RESET high. This may be accomplished IOUTB (or QOUTB) produces a complementary output, by writing two or more successive Q data inputs followed by with the full-scale current split between the two outputs as a a clock. In this case, the state machine will advance to either function of the input code. the RESET or FILTER DATA state. The state machine will advance to the ONE-I state upon writing I data followed by a clock. I I I DATA INPUT FILTER REGISTER REGISTER Q I AND Q DATA I or Q or N FILTER ONE, I I DATA N I Q or N Q Q INPUT INPUT Q DATA RESET REGISTER REGISTER I = WRITE AND SELECT FOLLOWED BY A CLOCK CLOCK Q = WRITE AND SELECT FOLLOWED BY A CLOCK 2 N = CLOCK ONLY, NO WRITE CLOCK SELECT STATE Figure 11. State Transition Diagram of AD9761 MACHINE RESET/SLEEP Digital Interface WRITE An example helps illustrate the digital timing and control requirements to ensure proper pairing of I and Q data. In Figure 10. Block Diagram of Digital Interface this example, the AD9761 is assumed to interface with a host processor on a dedicated data bus and the state machine The AD9761 interfaces with a single 10-bit digital input is reset by asserting a Logic Level 1 to the RESET/SLEEP bus that supports interleaved I and Q input data. Figure 10 input for a duration of one clock cycle. In the timing diagram shows a simplified block diagram of the digital interface shown in Figure 12, WRITE and CLOCK are tied together circuitry consisting of two banks of edge triggered registers, while SELECT is updated at the same instance as DATA. two multiplexers, and a state machine. Interleaved I and Q Since SELECT is high upon RESET returning low, I data is input data is presented at the DATA input bus, where it is latched into the I input register on the first rising WRITE. then latched into the selected I or Q input register on the On the next rising WRITE edge, the Q data is latched into rising edge of the WRITE input. The output of these input its input register and the outputs of both input registers are registers is transferred in pairs to their respective interpola- latched into their respective I and Q filter registers. The tor filters’ register after each Q write on the rising edge of sequence of events is repeated on the next rising WRITE edge the CLOCK input (refer to Timing Diagram in Figure 1). with the new I data being latched into the I input register. A state machine ensures the proper pairing of I and Q input data to the interpolation filter’s inputs. The digital inputs are CMOS compatible with logic thresholds, V , set to approximately half the digital positive THRESHOLD The SELECT signal at the time of the rising edge of the supply (DVDD) or V = DVDD/2 (±20%). THRESHOLD WRITE signal determines which input register latches the input data. If SELECT is high around the rising The internal digital circuitry of the AD9761 is capable of edge of WRITE, the data is latched into the I register of operating over a digital supply range of 2.7 V to 5.5 V. As a –12– REV. C REV. C –13– AD9761 AD9761 result, the digital inputs can also accommodate TTL levels The power-up and power-down characteristics of the AD9761 when DVDD is set to accommodate the maximum high are dependent upon the value of the compensation level voltage, V , of the TTL drivers. A DVDD of 3 V capacitor connected to COMP1 and COMP3. With a OH(MAX) to 3.3 V will typically ensure proper compatibility of most nominal value of 0.1 µF, the AD9761 takes less than 5 µs to TTL logic families. Figure 13 shows the equivalent digital power down and approximately 3.25 ms to power back up. input circuit for the data, sleep, and clock inputs. POWER DISSIPATION RESET The power dissipation of the AD9761 is dependent on several factors, including I Q I Q DATA 0 0 1 1 1. AVDD and DVDD, the power supply voltages. 2. I , the full-scale current output. OUTFS SELECT 3. f , the update rate. CLOCK CLOCK/WRITE 4. The reconstructed digital input waveform. The power dissipation is directly proportional to the analog Figure 12. Timing Diagram supply current, I , and the digital supply current, I . AVDD DVDD DVDD I is directly proportional to I , as shown in Fig- AVDD OUTFS ure 14, and is insensitive to f . CLOCK 30 DIGITAL INPUT 25 20 15 Figure 13. Equivalent Digital Input Since the AD9761 is capable of being updated up to 40 MSPS, 10 the quality of the clock and data input signals are important in achieving the optimum performance. The drivers of the 5 digital data interface circuitry should be specified to meet the minimum setup and hold times of the AD9761 as well 0 as its required min/max input logic level thresholds. The 1 2 3 4 5 6 7 8 9 10 I (mA) OUTFS external clock driver circuitry should provide the AD9761 with a low jitter clock input meeting the min/max logic Figure 14. I vs. I AVDD OUTFS levels while providing fast edges. Fast clock edges will help minimize any jitter that can manifest itself as phase noise Conversely, I is dependent on both the digital input DVDD on a reconstructed waveform. waveform, f , and digital supply, DVDD. Figures 15 CLOCK and 16 show I as a function of a full-scale sine wave DVDD Digital signal paths should be kept short, and run lengths output ratio’s (f /f ) for various update rates with OUT CLOCK matched to avoid propagation delay mismatch. The inser- DVDD = 5 V and DVDD = 3 V, respectively. tion of a low value resistor network (i.e., 20  to 100 ) between the AD9761 digital inputs and driver outputs 70 may be helpful in reducing any overshooting and ringing at 40MSPS 60 the digital inputs, which contributes to data feedthrough. Operating the AD9761 with reduced logic swings and a 50 corresponding digital supply (DVDD) will also reduce data feedthrough. 40 20MSPS RESET/SLEEP MODE OPERATION 30 The RESET/SLEEP input can be used either to power down 2.5MSPS 20 the AD9761 or reset its internal digital interface logic. If the 10MSPS RESET/SLEEP input is asserted for greater than one clock 5MSPS 10 cycle but under four clock cycles by applying a Logic 1, the internal state machine will be reset. If the RESET/SLEEP input 0 is asserted for four clock cycles or longer, the power-down func- 0 0.05 0.10 0.15 0.20 RATIO (f /f ) tion of the AD9761 will be initiated. The power-down function OUT CLK turns off the output current and reduces the supply current to less than 9 mA over the specified supply range of 3 V to 5.5 V Figure 15. I vs. Ratio @ DVDD = 5 V DVDD and temperature range. –14– REV. C REV. C –15– I (mA) DVDD I (mA) AVDD AD9761 AD9761 40 AD9761 35 MINI-CIRCUITS 40MSPS T1-1T IOUTA 30 R LOAD 25 IOUTB OPTIONAL 20 R DIFF 20MSPS 15 2.5MSPS 10 Figure 17. Differential Output Using a Transformer 10MSPS 5MSPS The center tap on the primary side of the transformer must 5 be connected to ACOM to provide the necessary dc current 0 path for both I and I . The complementary voltages OUTA OUTB 0 0.05 0.10 0.15 0.20 appearing at IOUTA and IOUTB (i.e., V and V ) RATIO (f /f ) OUTA OUTB OUT CLK swing symmetrically around ACOM and should be maintained with the specified output compliance range of the AD9761. Figure 16. I vs. Ratio @ DVDD = 3 V DVDD A differential resistor, R , may be inserted in applications DIFF in which the output of the transformer is connected to the APPLYING THE AD9761 load, R , via a passive reconstruction filter or cable Output Configurations LOAD requiring double termination. R is determined by the The following sections illustrate some typical output configu- DIFF transformer’s impedance ratio and provides the proper rations for the AD9761. Unless otherwise noted, it is assumed source termination, which results in a low VSWR. Note that I is set to a nominal 10 mA. For applications requir- OUTFS that approximately half the signal power will be dissipated ing the optimum dynamic performance, a differential output across R . configuration is suggested. A differential output configuration DIFF may consist of either an RF transformer or a differential op amp Differential Coupling Using an Op Amp configuration. The transformer configuration provides the An op amp can also be used to perform a differential optimum high frequency performance and is recommended to single-ended conversion as shown in Figure 18. The for any application allowing for ac coupling. The differential AD9761 is configured with two equal load resistors, R , LOAD op amp configuration is suitable for applications requiring dc of 50 . The differential voltage developed across IOUTA coupling, a bipolar output, signal gain, and/or level shifting. and IOUTB is converted to a single-ended signal via the differential op amp configuration. An optional capacitor A single-ended output is suitable for applications requiring can be installed across IOUTA and IOUTB forming a real a unipolar voltage output. A positive unipolar output voltage pole in a low-pass filter. The addition of this capacitor also will result if IOUTA and/or IOUTB is connected to an enhances the op amp’s distortion performance by prevent- appropriately sized load resistor, R , referred to ACOM. LOAD ing the DAC’s high slewing output from overloading the op This configuration may be more suitable for a single-supply amp’s input. system requiring a dc-coupled, ground referred output volt- age. Alternatively, an amplifier could be configured as an I-V converter, thus converting I or I into a negative 500 OUTA OUTB AD9761 unipolar voltage. This configuration provides the best dc 200 linearity since IOUTA or IOUTB is maintained at a virtual IOUTA AD8042 ground. IOUTB 200 Differential Coupling Using a Transformer C OPT An RF transformer can be used to perform a differential- R R LOAD LOAD 500 to-single-ended signal conversion as shown in Figure 17. A 50 50 differentially coupled transformer output provides the optimum distortion performance for output signals whose spectral content lies within the transformer’s pass band. An RF Figure 18. DC Differential Coupling Using an Op Amp transformer such as the Mini-Circuits T1-1T provides excellent rejection of common-mode distortion (i.e., even-order The common-mode rejection of this configuration is typically harmonics) and noise over a wide frequency range. It also determined by the resistor matching. In this circuit, the provides electrical isolation and the ability to deliver twice differential op amp circuit using the AD8042 is configured the power to the load. Transformers with different impedance to provide some additional signal gain. The op amp must ratios may also be used for impedance matching purposes. operate from a dual supply since its output is approximately Note that the transformer provides ac coupling only. ±1.0 V. A high speed amplifier capable of preserving the differential performance of the AD9761 while meeting other system level objectives (i.e., cost, power) should be selected. The op amp’s differential gain, gain setting resistor values, and full-scale output swing capabilities should all be consid- ered when optimizing this circuit. –14– REV. C REV. C –15– I (mA) DVDD AD9761 AD9761 AVDD The differential circuit shown in Figure 19 provides the neces- sary level-shifting required in a single-supply system. In this QUADRATURE UPCONVERTER case, AVDD, which is the positive analog supply for both the 500* 500* AD9761 and the op amp, is also used to level-shift the differ- V IN+ ential output of the AD9761 to midsupply (i.e., AVDD/2). V IN– AD9761 500* 500* 500 AD9761 IOUTA 200 IOUTA IOUTB AD8042 50** 50** IOUTB 200 C OPT 1k AVDD R R LOAD LOAD *OHMTEK TO MC-1603-5000D 1k 50 50 **OHMTEK TO MC-1603-1000D Figure 21. Differential, DC-Coupled Output Configuration with Level-Shifting Figure 19. Single-Supply DC Differential Coupled Circuit POWER AND GROUNDING CONSIDERATIONS Single-Ended Unbuffered Voltage Output In systems seeking to simultaneously achieve high speed and Figure 20 shows the AD9761 configured to provide a uni- high performance, the implementation and construction of polar output range of approximately 0 V to 0.5 V since the the printed circuit board design is often as important as the nominal full-scale current, I , of 10 mA flows through an OUTFS circuit design. Proper RF techniques must be used in device R of 50 . In the case of a doubly terminated low-pass LOAD selection, placement and routing, and supply bypassing and filter, R represents the equivalent load resistance seen by LOAD grounding. The evaluation board for the AD9761, which IOUTA or IOUTB. The unused output (IOUTA or IOUTB) uses a 4-layer PC board, serves as a good example for the can be connected to ACOM directly or via a matching R . LOAD previously mentioned considerations. The evaluation board Different values of I and R can be selected as long OUTFS LOAD provides an illustration of the recommended printed circuit as the positive compliance range is adhered to. board ground, power, and signal plane layout. Proper grounding and decoupling should be a primary objec- AD9761 tive in any high speed, high resolution system. The AD9761 I = 10mA OUTFS V = features separate analog and digital supply and ground pins OUT IOUTA 0V TO 0.5V to optimize the management of analog and digital ground 50 currents in a system. In general, AVDD, the analog supply, IOUTB should be decoupled to ACOM, the analog common, as 50 close to the chip as physically possible. Similarly, DVDD, the digital supply should be decoupled as close to DCOM as physically as possible. Figure 20. 0 V to 0.5 V Unbuffered Voltage Output For those applications requiring a single 5 V or 3.3 V supply Differential, DC-Coupled Output Configuration with for both the analog and digital supply, a clean analog supply Level Shifting may be generated using the circuit shown in Figure 22. Some applications may require the AD9761 differential outputs The circuit consists of a differential LC filter with separate to interface to a single-supply quadrature upconverter. power supply and return lines. Lower noise can be attained Although most of these devices provide differential inputs, using low ESR type electrolytic and tantalum capacitors. its common-mode voltage range does not typically extend AVDD to ground. As a result, the ground-referenced output signals TTL/CMOS + + 100F 0.1F shown in Figure 20 must be level shifted to within the 10F–22F LOGIC FERRITE CER. ELECT. TANT. CIRCUITS BEADS – – specified common-mode range of the single-supply quadrature ACOM upconverter. Figure 21 shows the addition of a resistor pull-up network that provides the level shifting function. The use of matched resistor networks will maintain maximum gain 5V OR 3V POWER SUPPLY matching and minimum offset performance between the I and Q channels. Note, the resistor pull-up network will introduce approximately 6 dB of signal attenuation. Figure 22. Differential LC Filter for Single 5 V or 3 V Applications –16– REV. C REV. C –17– AD9761 AD9761 Maintaining low noise on power supplies and ground is critical A common and traditional implementation of a QAM to obtaining optimum results from the AD9761. If properly modulator is shown in Figure 23. The modulation is performed implemented, ground planes can perform a host of functions in the analog domain in which two DACs are used to gen- on high speed circuit boards such as bypassing, shielding, erate the baseband I and Q components, respectively. Each current transport. In mixed signal design, the analog and component is then typically applied to a Nyquist filter digital portions of the board should be distinct from each before being applied to a quadrature mixer. The matching other, with the analog ground plane confined to the areas Nyquist filter shapes and limits each component’s spectral covering the analog signal traces and the digital ground plane envelope while minimizing intersymbol interference. The confined to areas covering the digital interconnects. DAC is typically updated at the QAM symbol rate or possibly a multiple of it if an interpolating filter precedes the DAC. All analog ground pins of the DAC, reference, and other The use of an interpolating filter typically eases the imple- analog components should be tied directly to the analog mentation and complexity of the analog filter, which can be ground plane. The two ground planes should be connected a significant contributor to mismatches in gain and phase by a path 1/8 to 1/4 inch wide underneath, or within 1/2 inch between the two baseband channels. A quadrature mixer of the DAC to maintain optimum performance. Care should modulates the I and Q components with in-phase and be taken to ensure that the ground plane is uninterrupted quadrature phase carrier frequency and then sums the two over crucial signal paths. On the digital side, this includes the outputs to provide the QAM signal. digital input lines running to the DAC as well as any clock signals. On the analog side, this includes the DAC output signal, reference signal, and the supply feeders. IOUT The use of wide runs or planes in the routing of power lines DSP 0 10 CARRIER OR S TO AD9761 FREQ is also recommended. This serves the dual role of providing 90 ASIC MIXER a low series impedance power supply to the part, as well as QOUT providing some free capacitive decoupling to the appropri- ate ground plane. It is essential that care be taken in the NYQUIST QUADRATURE layout of signal and power ground interconnects to avoid FILTERS MODULATOR inducing extraneous voltage drops in the signal ground Figure 23. Typical Analog QAM Architecture paths. It is recommended that all connections be short, direct, and as physically close to the package as possible in order EVALUATION BOARD to minimize the sharing of conduction paths between differ- The AD9761-EB is an evaluation board for the AD9761 ent currents. When runs exceed an inch in length, strip line dual 10-bit, 40 MSPS DAC. Careful attention to layout techniques with a proper termination resistor should be and circuit design along with prototyping area allows the considered. The necessity and value of this resistor will be user to easily and effectively evaluate the AD9761. This dependent upon the logic family used. board allows the user the flexibility to operate each of the For a more detailed discussion of the implementation and AD9761 DACs in a single-ended or differential output construction of high speed, mixed signal printed circuit configuration. Each of the DACs’ single-ended outputs are boards, refer to Analog Devices’ Application Notes AN-280 terminated in a 50  resistor. Evaluation using a transformer and AN-333. coupled output can be accomplished simply by installing a Mini-Circuits transformer (i.e., Model T2-1T) into the APPLICATIONS available socket. Using the AD9761 for QAM Modulation The digital inputs are designed to be driven directly from QAM is one of the most widely used digital modulation various word generators with the on-board option to add schemes in digital communication systems. This modulation a resistor network for proper load termination. Separate technique can be found in both FDM as well as spread 50  terminated SMA connectors are also provided for the spectrum (i.e., CDMA) based systems. A QAM signal is a CLOCK, WRITE, and SELECT inputs. Provisions are also carrier frequency that is modulated both in amplitude (i.e., made to operate the AD9761 with either the internal or an AM modulation) and in phase (i.e., PM modulation). It can external reference as well as to exercise the power-down be generated by independently modulating two carriers of feature. identical frequency but with a 90° phase difference. This results in an in-phase (I) carrier component and a quadrature (Q) carrier component at a 90° phase shift with respect to the I component. The I and Q components are then summed to provide a QAM signal at the specified carrier frequency. –16– REV. C REV. C –17– AD9761 AD9761 Figure 24a. Evaluation Board Schematic –18– REV. C REV. C –19– AD9761 AD9761 Figure 24b. Evaluation Board Schematic –18– REV. C REV. C –19– AD9761 AD9761 Figure 25. Silkscreen Layer—Top Figure 26. Component Side PCB Layout (Layer 1) –20– REV. C REV. C –21– AD9761 AD9761 Figure 27. Ground Plane PCB Layout (Layer 2) Figure 28. Power Plane PCB Layout (Layer 3) –20– REV. C REV. C –21– AD9761 AD9761 Figure 29. Solder Side PCB Layout (Layer 4) Figure 30. Silkscreen Layer—Bottom –22– REV. C REV. C –23– AD9761 AD9761 OUTLINE DIMENSIONS 28-Lead Shrink Small Outline Package [SSOP] (RS-28) Dimensions shown in millimeters 10.50 10.20 9.90 28 15 5.60 8.20 5.30 7.80 5.00 7.40 1 14 1.85 1.75 0.10 1.65 COPLANARITY 2.00 MAX 0.25 0.09 8 0.95 0.65 0.38 0.05 4 BSC 0.75 0.22 SEATING MIN 0 PLANE 0.55 COMPLIANT TO JEDEC STANDARDS MO-150AH –22– REV. C REV. C –23– AD9761 Revision History Location Page 6/03—Data Sheet changed from REV. B to REV. C. Renumbered TPCs and subsequent figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Universal Changes to Figure 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Updated ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 –24– REV. C C00615–0–6/03(C)