ANALOG DEVICES AD9754

14-Bit, 125 MSPS High Performance ® a TxDAC D/A Converter AD9754* FUNCTIONAL BLOCK DIAGRAM FEATURES +5V High Performance Member of Pin-Compatible TxDAC Product Family REFLO AVDD ACOM 150pF 125 MSPS Update Rate +1.20V REF AD9754 0.1mF 14-Bit Resolution REFIO 0.1mF CURRENT ICOMP Excellent Spurious Free Dynamic Range Performance FS ADJ SOURCE ARRAY SFDR to Nyquist @ 5 MHz Output: 83 dBc R SET +5V DVDD IOUTA Differential Current Outputs: 2 mA to 20 mA LSB SEGMENTED DCOM IOUTB SWITCHES SWITCHES Power Dissipation: 185 mW @ 5 V CLOCK Power-Down Mode: 20 mW @ 5 V CLOCK LATCHES SLEEP On-Chip 1.20 V Reference DIGITAL DATA INPUTS (DB13–DB0) CMOS-Compatible +2.7 V to +5.5 V Digital Interface Package: 28-Lead SOIC, TSSOP Packages The AD9754 is a current-output DAC with a nominal full-scale Edge-Triggered Latches output current of 20 mA and > 100 kW output impedance. APPLICATIONS Differential current outputs are provided to support single- Wideband Communication Transmit Channel: ended or differential applications. Matching between the two Direct IF current outputs ensures enhanced dynamic performance in a Basestations differential output configuration. The current outputs may be Wireless Local Loop tied directly to an output resistor to provide two complemen- Digital Radio Link tary, single-ended voltage outputs or fed directly into a trans- Direct Digital Synthesis (DDS) former. The output voltage compliance range is 1.25 V. Instrumentation The on-chip reference and control amplifier are configured for PRODUCT DESCRIPTION maximum accuracy and flexibility. The AD9754 can be driven The AD9754 is a 14-bit resolution, wideband, second genera- by the on-chip reference or by a variety of external reference tion member of the TxDAC series of high performance, low voltages. The internal control amplifier, which provides a wide power CMOS digital-to-analog-converters (DACs). The (>10:1) adjustment span, allows the AD9754 full-scale current TxDAC family, which consists of pin compatible 8-, 10-, 12- to be adjusted over a 2 mA to 20 mA range while maintaining and 14-bit DACs, is specifically optimized for the transmit excellent dynamic performance. Thus, the AD9754 may operate signal path of communication systems. All of the devices share at reduced power levels or be adjusted over a 20 dB range to the same interface options, small outline package and pinout, provide additional gain ranging capabilities. providing an upward or downward component selection path based on performance, resolution and cost. The AD9754 offers The AD9754 is available in 28-lead SOIC and TSSOP packages. exceptional ac and dc performance while supporting update It is specified for operation over the industrial temperature range. rates up to 125 MSPS. PRODUCT HIGHLIGHTS The AD9754’s flexible single-supply operating range of +4.5 V to 1. The AD9754 is a member of the wideband TxDAChigh per- +5.5 V and low power dissipation are well suited for portable and formance product family that provides an upward or downward low power applications. Its power dissipation can be further reduc- component selection path based on resolution (8 to 14 bits), ed to a mere 65 mW with a slight degradation in performance by performance and cost. The entire family of TxDACs is avail- lowering the full-scale current output. Also, a power-down mode able in industry standard pinouts. reduces the standby power dissipation to approximately 20 mW. 2. Manufactured on a CMOS process, the AD9754 uses a The AD9754 is manufactured on an advanced CMOS process. proprietary switching technique that enhances dynamic per- A segmented current source architecture is combined with a formance beyond that previously attainable by higher power/ proprietary switching technique to reduce spurious components cost bipolar or BiCMOS devices. and enhance dynamic performance. Edge-triggered input latches 3. On-chip, edge-triggered input CMOS latches readily inter- and a 1.2 V temperature compensated bandgap reference have face to +2.7 V to +5 V CMOS logic families. The AD9754 been integrated to provide a complete monolithic DAC solution. can support update rates up to 125 MSPS. The digital inputs support +2.7 V and +5 V CMOS logic families. 4. A flexible single-supply operating range of +4.5 V to +5.5 V, TxDAC is a registered trademark of Analog Devices, Inc. and a wide full-scale current adjustment span of 2 mA to *Protected by U.S. Patents Numbers 5450084, 5568145, 5689257, 5612697 and 20 mA, allows the AD9754 to operate at reduced power levels. 5703519. 5. The current output(s) of the AD9754 can be easily config- REV. A ured for various single-ended or differential circuit topologies. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties Tel: 781/329-4700 World Wide Web Site: http://www.analog.com which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 1999 AD9754–SPECIFICATIONS (T to T , AVDD = +5 V, DVDD = +5 V, I = 20 mA, unless otherwise noted) DC SPECIFICATIONS MIN MAX OUTFS Parameter Min Typ Max Units RESOLUTION 14 Bits 1 DC ACCURACY Integral Linearity Error (INL) T = +25°C –3.0–1.5 +3.0 LSB A Differential Nonlinearity (DNL) T = +25°C –2.0–0.75 +2.0 LSB A ANALOG OUTPUT Offset Error –0.02 +0.02 % of FSR Gain Error (Without Internal Reference) –2–0.5 +2 % of FSR Gain Error (With Internal Reference) –5–1.5 +5 % of FSR 2 Full-Scale Output Current 2.0 20.0 mA Output Compliance Range –1.0 1.25 V Output Resistance 100 kW Output Capacitance 5 pF REFERENCE OUTPUT Reference Voltage 1.14 1.20 1.26 V 3 Reference Output Current 100 nA REFERENCE INPUT Input Compliance Range 0.1 1.25 V Reference Input Resistance 1 MW Small Signal Bandwidth 0.5 MHz TEMPERATURE COEFFICIENTS Offset Drift 0 ppm of FSR/°C Gain Drift (Without Internal Reference)–50 ppm of FSR/°C Gain Drift (With Internal Reference)–100 ppm of FSR/°C Reference Voltage Drift–50 ppm/°C POWER SUPPLY Supply Voltages AVDD 4.5 5.0 5.5 V DVDD 2.7 5.0 5.5 V 4 Analog Supply Current (I ) 34 39 mA AVDD 5 ) 3.0 5 mA Digital Supply Current (I DVDD 6 ) 4.0 8 mA Supply Current Sleep Mode (I AVDD 5 (5 V, I = 20 mA) 185 220 mW Power Dissipation OUTFS 7 —AVDD –0.4 +0.4 % of FSR/V Power Supply Rejection Ratio 7 Power Supply Rejection Ratio —DVDD –0.025 +0.025 % of FSR/V OPERATING RANGE –40 +85 °C NOTES 1 Measured at IOUTA, driving a virtual ground. 2 Nominal full-scale current, I , is 32 · the I current. OUTFS REF 3 Use an external buffer amplifier to drive any external load. 4 Requires +5 V supply. 5 Measured at f = 25 MSPS and I = static full scale (20 mA). CLOCK OUT 6 Logic level for SLEEP pin must be referenced to AVDD. Min V = 3.5 V. IH 7 –5% Power supply variation. Specifications subject to change without notice. –2– REV. A AD9754 (T to T , AVDD = +5 V, DVDD = +5 V, I = 20 mA, Differential Transformer Coupled Output, MIN MAX OUTFS 50 V Doubly Terminated, unless otherwise noted) DYNAMIC SPECIFICATIONS Parameter Min Typ Max Units DYNAMIC PERFORMANCE Maximum Output Update Rate (f ) 125 MSPS CLOCK 1 Output Settling Time (t ) (to 0.1%) 35 ns ST Output Propagation Delay (t)1 ns PD Glitch Impulse 5 pV-s 1 Output Rise Time (10% to 90%) 2.5 ns 1 Output Fall Time (10% to 90%) 2.5 ns Output Noise (I = 20 mA) 50 pA/√Hz OUTFS Output Noise (I = 2 mA) 30 pA/√Hz OUTFS AC LINEARITY Spurious-Free Dynamic Range to Nyquist f = 25 MSPS; f = 1.00 MHz CLOCK OUT 0 dBFS Output = +25°C 75 86 dBc T A –6 dBFS Output 86 dBc –12 dBFS Output 78 dBc = 50 MSPS; f = 1.00 MHz 82 dBc f CLOCK OUT = 50 MSPS; f = 2.51 MHz 81 dBc f CLOCK OUT = 50 MSPS; f = 5.02 MHz 77 dBc f CLOCK OUT = 50 MSPS; f = 20.2 MHz 63 dBc f CLOCK OUT = 100 MSPS; f = 10 MHz 68 73 dBc f CLOCK OUT Spurious-Free Dynamic Range within a Window = 25 MSPS; f = 1.00 MHz; 2 MHz Span 84 93 dBc f CLOCK OUT = 50 MSPS; f = 5.02 MHz; 2 MHz Span 86 dBc f CLOCK OUT = 100 MSPS; f = 5.04 MHz; 4 MHz Span 86 dBc f CLOCK OUT Total Harmonic Distortion = 25 MSPS; f = 1.00 MHz f CLOCK OUT = +25°C –83 –75 dBc T A = 50 MHz; f = 2.00 MHz –78 dBc f CLOCK OUT = 100 MHz; f = 2.00 MHz –78 dBc f CLOCK OUT Multitone Power Ratio (8 Tones at 110 kHz Spacing) = 20 MSPS; f = 2.00 MHz to 2.99 MHz f CLOCK OUT 0 dBFS Output 85 dBc –6 dBFS Output 84 dBc –12 dBFS Output 87 dBc –18 dBFS Output 88 dBc NOTES 1 Measured single-ended into 50W load. Specifications subject to change without notice. REV. A –3– AD9754 DIGITAL SPECIFICATIONS (T to T , AVDD = +5 V, DVDD = +5 V, I = 20 mA unless otherwise noted) MIN MAX OUTFS Parameter Min Typ Max Units DIGITAL INPUTS 1 Logic “1” Voltage @ DVDD = +5 V 3.5 5 V Logic “1” Voltage @ DVDD = +3 V 2.1 3 V 1 0 1.3 V Logic “0” Voltage @ DVDD = +5 V Logic “0” Voltage @ DVDD = +3 V 0 0.9 V Logic “1” Current –10 +10mA Logic “0” Current –10 +10mA Input Capacitance 5 pF ) 2.0 ns Input Setup Time (t S ) 1.5 ns Input Hold Time (t H Latch Pulsewidth (t ) 3.5 ns LPW NOTES 1 When DVDD = +5 V and Logic 1 voltage »3.5 V and Logic 0 voltage »1.3 V, IVDD can increase by up to 10 mA depending on f . CLOCK Specifications subject to change without notice. DB0–DB11 t t S H CLOCK t LPW t PD t ST IOUTA OR 0.1% IOUTB 0.1% Figure 1. Timing Diagram ABSOLUTE MAXIMUM RATINGS* ORDERING GUIDE With Temperature Package Package Parameter Respect to Min Max Units Model Range Descriptions Options* AVDD ACOM –0.3 +6.5 V AD9754AR –40°C to +85°C 28-Lead 300 Mil SOIC R-28 DVDD DCOM –0.3 +6.5 V AD9754ARU –40°C to +85°C 28-Lead TSSOP RU-28 ACOM DCOM –0.3 +0.3 V AD9754-EB Evaluation Board AVDD DVDD –6.5 +6.5 V *R = Small Outline IC; RU = Thin Shrink Small Outline Package. CLOCK, SLEEP DCOM –0.3 DVDD + 0.3 V Digital Inputs DCOM –0.3 DVDD + 0.3 V THERMAL CHARACTERISTICS IOUTA, IOUTB ACOM –1.0 AVDD + 0.3 V Thermal Resistance ICOMP ACOM –0.3 AVDD + 0.3 V 28-Lead 300 Mil SOIC REFIO, FSADJ ACOM –0.3 AVDD + 0.3 V = 71.4°C/WqREFLO ACOM –0.3 AVDD +0.3 V JA = 23°C/WqJunction Temperature +150 °C JC 28-Lead TSSOP Storage Temperature –65 +150 °C = 97.9°C/WqLead Temperature JA = 14.0°C/Wq(10 sec) +300 °C JC *Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD9754 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD ESD SENSITIVE DEVICE precautions are recommended to avoid performance degradation or loss of functionality. REV. A –4– AD9754 PIN CONFIGURATION (MSB) DB13 1 28 CLOCK DB12 2 DVDD 27 DB11 3 26 DCOM DB10 4 NC 25 DB9 5 24 AVDD AD9754 DB8 6 23 ICOMP TOP VIEW (Not to Scale) DB7 7 22 IOUTA DB6 8 21 IOUTB 9 DB5 20 ACOM DB4 10 19 NC DB3 FS ADJ 11 18 DB2 12 17 REFIO DB1 REFLO 13 16 (LSB) DB0 14 15 SLEEP NC = NO CONNECT PIN FUNCTION DESCRIPTIONS Pin No. Name Description 1 DB13 Most Significant Data Bit (MSB). 2–13 DB12–DB1 Data Bits 1–12. 14 DB0 Least Significant Data Bit (LSB). 15 SLEEP Power-Down Control Input. Active High. Contains active pull-down circuit; it may be left unterminated if not used. 16 REFLO Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal reference. 17 REFIO Reference Input/Output. Serves as reference input when internal reference disabled (i.e., Tie REFLO to AVDD). Serves as 1.2 V reference output when internal reference activated (i.e., Tie REFLO to ACOM). Requires 0.1mF capacitor to ACOM when internal reference activated. 18 FS ADJ Full-Scale Current Output Adjust. 19, 25 NC No Connect. 20 ACOM Analog Common. 21 IOUTB Complementary DAC Current Output. Full-scale current when all data bits are 0s. 22 IOUTA DAC Current Output. Full-scale current when all data bits are 1s. 23 ICOMP Internal Bias Node for Switch Driver Circuitry. Decouple to ACOM with 0.1 mF capacitor. 24 AVDD Analog Supply Voltage (+4.5 V to +5.5 V). 26 DCOM Digital Common. 27 DVDD Digital Supply Voltage (+2.7 V to +5.5 V). 28 CLOCK Clock Input. Data latched on positive edge of clock. REV. A –5– AD9754 DEFINITIONS OF SPECIFICATIONS Power Supply Rejection Linearity Error (Also Called Integral Nonlinearity or INL) The maximum change in the full-scale output as the supplies Linearity error is defined as the maximum deviation of the are varied over a specified range. actual analog output from the ideal output, determined by a Settling Time straight line drawn from zero to full scale. The time required for the output to reach and remain within a Differential Nonlinearity (or DNL) specified error band about its final value, measured from the DNL is the measure of the variation in analog value, normalized start of the output transition. to full scale, associated with a 1 LSB change in digital input Glitch Impulse code. Asymmetrical switching times in a DAC give rise to undesired Offset Error output transients that are quantified by a glitch impulse. It is The deviation of the output current from the ideal of zero is specified as the net area of the glitch in pV-s. called offset error. For IOUTA, 0 mA output is expected when Spurious-Free Dynamic Range the inputs are all 0s. For IOUTB, 0 mA output is expected The difference, in dB, between the rms amplitude of the output when all inputs are set to 1s. signal and the peak spurious signal over the specified bandwidth. Gain Error Total Harmonic Distortion The difference between the actual and ideal output span. The THD is the ratio of the sum of the rms value of the first six actual span is determined by the output when all inputs are set harmonic components to the rms value of the measured output to 1s minus the output when all inputs are set to 0s. signal. It is expressed as a percentage or in decibels (dB). Output Compliance Range Multitone Power Ratio The range of allowable voltage at the output of a current-output The spurious-free dynamic range for an output containing mul- DAC. Operation beyond the maximum compliance limits may tiple carrier tones of equal amplitude. It is measured as the cause either output stage saturation or breakdown, resulting in difference between the rms amplitude of a carrier tone to the nonlinear performance. peak spurious signal in the region of a removed tone. Temperature Drift Temperature drift is specified as the maximum change from the ambient (+25°C) value to the value at either T or T . For MIN MAX offset and gain drift, the drift is reported in ppm of full-scale range (FSR) per °C. For reference drift, the drift is reported in ppm per °C. +5V REFLO AVDD ACOM 150pF +1.20V REF AD9754 0.1mF REFIO PMOS 0.1mF ICOMP CURRENT SOURCE FS ADJ ARRAY MINI-CIRCUITS R SET T1-1T TO HP3589A 2kV +5V DVDD IOUTA SPECTRUM/ SEGMENTED SWITCHES LSB DCOM 100V NETWORK IOUTB FOR DB13–DB5 SWITCHES ANALYZER 50V INPUT CLOCK LATCHES DVDD 50V 20pF SLEEP 50V DCOM RETIMED 50V 20pF CLOCK DIGITAL OUTPUT* DATA CLOCK * AWG2021 CLOCK RETIMED OUTPUT SUCH THAT DIGITAL DATA LECROY 9210 TEKTRONIX AWG-2021 TRANSITIONS ON FALLING EDGE PULSE GENERATOR w/OPTION 4 OF 50% DUTY CYCLE CLOCK. Figure 2. Basic AC Characterization Test Setup REV. A –6– AD9754 Typical AC Characterization Curves (AVDD = +5 V, DVDD = +3 V, I = 20 mA, 50 V Doubly Terminated Load, Differential Output, T = +258C, SFDR up to Nyquist, unless OUTFS A otherwise noted) 90 95 90 –6dBFS 25MSPS 85 90 5MSPS –6dBFS 0dBFS 80 80 85 –12dBFS 65MSPS 75 80 0dBFS 70 125MSPS 70 75 –12dBFS 65 70 60 50MSPS 60 65 55 60 50 50 55 50 45 40 45 40 0.1 110 100 0.0 0.4 0.8 1.2 1.6 2.0 02 46 8 10 f – MHz OUT FREQUENCY – MHz FREQUENCY – MHz Figure 3. SFDR vs. f @ 0 dBFS Figure 4. SFDR vs. f @ 5 MSPS Figure 5. SFDR vs. f @ 25 MSPS OUT OUT OUT 90 90 90 10mA FS 0dBFS 80 80 80 20mA FS –12dBFS –6dBFS 70 70 70 –6dBFS –12dBFS 60 60 60 5mA FS 0dBFS 50 50 50 40 40 40 60 0 05 10 15 20 25 30 010 20 30 40 50 21 468 102 f – MHz f – MHz f – MHz OUT OUT OUT Figure 6. SFDR vs. f @ 65 MSPS Figure 7. SFDR vs. f @125 MSPS Figure 8. SFDR vs. f and OUT OUT OUT I @ 25 MSPS and 0 dBFS OUTFS 90 100 85 2.27MHz 1MHz 85 @25MSPS 455kHz @5MSPS @5MSPS 90 80 80 75 80 20mA FS 70 75 11.37MHz 5MHz @125MSPS 65 70 @25MSPS 60 59.1MHz 70 @65MSPS 60 25MHz 55 10mA FS @125MSPS 50 65 5mA FS 13MHz 50 @65MSPS 45 40 40 60 –30 –25 –20 –15 –10 –5 0 –30 –25 –20 –15 –10 –5 0 0 20 40 60 80 100 120 140 A – dBFS A – dBFS OUT OUT f – MSPS CLOCK Figure 9. Single-Tone SFDR vs. A Figure 10. Single-Tone SFDR vs. OUT Figure 11. SNR vs. f and I CLOCK OUTFS @ f = f /11 A @ f = f /5 OUT CLOCK OUT OUT CLOCK @ f = 2 MHz and 0 dBFS OUT REV. A –7– SFDR – dBc SFDR – dB SFDR – dB SFDR – dBc SFDR – dB SFDR – dB SFDR – dBc SNR– dB SFDR – dB AD9754 1.0 1.0 90 0.5 f = 4MHz OUT 0.5 80 0 f = 10MHz OUT –0.5 0 70 –1.0 f = 29MHz OUT –0.5 60 –1.5 f = 40MHz OUT –1.0 –2.0 50 0 4k 8k 12k 16k 0 4k 8k 12k 16k –55 –5 95 45 CODE CODE TEMPERATURE – C Figure 12. Typical INL Figure 13. Typical DNL Figure 14. SFDR vs. Temperature @ 125 MSPS, 0 dBFS 0 f = 65MSPS CLOCK –10 f = 6.25MHz OUT1 f = 6.75MHz OUT2 –20 f = 7.25MHz OUT3 f = 7.75MHz OUT4 –30 SFDR > 70dBc AMPLITUDE = 0dBFS –40 –50 –60 –70 –80 –90 –100 03 5 10 15 20 250 FREQUENCY – MHz Figure 15. Four-Tone SFDR REV. A –8– ERROR – LSB ERROR – LSB SINGLE AMPLITUDE – dBm SFDR – dBc AD9754 FUNCTIONAL DESCRIPTION DAC TRANSFER FUNCTION Figure 16 shows a simplified block diagram of the AD9754. The The AD9754 provides complementary current outputs, IOUTA AD9754 consists of a large PMOS current source array that is and IOUTB. IOUTA will provide a near full-scale current out- capable of providing up to 20 mA of total current. The array put, I , when all bits are high (i.e., DAC CODE = 16383) OUTFS is divided into 31 equal currents that make up the five most while IOUTB, the complementary output, provides no current. significant bits (MSBs). The next four bits or middle bits consist The current output appearing at IOUTA and IOUTB is a func- of 15 equal current sources whose value is 1/16th of an MSB tion of both the input code and I and can be expressed as: OUTFS current source. The remaining LSBs are binary weighted frac- IOUTA = (DAC CODE/16384) · I (1) OUTFS tions of the middle bits current sources. Implementing the IOUTB = (16383 – DAC CODE)/16384 · I (2) OUTFS middle and lower bits with current sources, instead of an R-2R ladder, enhances its dynamic performance for multitone or low where DAC CODE = 0 to 16383 (i.e., Decimal Representation). amplitude signals and helps maintain the DAC’s high output As mentioned previously, I is a function of the reference OUTFS impedance (i.e., >100 kW). current I , which is nominally set by a reference voltage V REF REFIO All of these current sources are switched to one or the other of and external resistor R . It can be expressed as: SET the two output nodes (i.e., IOUTA or IOUTB) via PMOS I = 32 · I (3) OUTFS REF differential current switches. The switches are based on a new where I = V /R (4) architecture that drastically improves distortion performance. REF REFIO SET This new switch architecture reduces various timing errors and The two current outputs will typically drive a resistive load provides matching complementary drive signals to the inputs of directly or via a transformer. If dc coupling is required, IOUTA the differential current switches. and IOUTB should be directly connected to matching resistive loads, R , that are tied to analog common, ACOM. Note The analog and digital sections of the AD9754 have separate LOAD that R may represent the equivalent load resistance seen by power supply inputs (i.e., AVDD and DVDD). The digital sec- LOAD IOUTA or IOUTB as would be the case in a doubly terminated tion, which is capable of operating up to a 125 MSPS clock rate 50W or 75W cable. The single-ended voltage output appearing and over +2.7 V to +5.5 V operating range, consists of edge- at the IOUTA and IOUTB nodes is simply: triggered latches and segment decoding logic circuitry. The analog section, which can operate over a +4.5 V to +5.5 V range V = IOUTA · R (5) OUTA LOAD includes the PMOS current sources, the associated differential V = IOUTB · R (6) OUTB LOAD switches, a 1.20 V bandgap voltage reference and a reference control amplifier. Note that the full-scale value of V and V should not OUTA OUTB exceed the specified output compliance range to maintain speci- The full-scale output current is regulated by the reference con- fied distortion and linearity performance. trol amplifier and can be set from 2 mA to 20 mA via an exter- . The external resistor, in combination with nal resistor, R The differential voltage, V , appearing across IOUTA and SET DIFF , both the reference control amplifier and voltage reference V IOUTB is: REFIO , which is mirrored over to the sets the reference current I REF V = (IOUTA – IOUTB) · R (7) DIFF LOAD segmented current sources with the proper scaling factor. The Substituting the values of IOUTA, IOUTB and I ; V can REF DIFF , is 32 times the value of I . full-scale current, I OUTFS REF be expressed as: V = {(2 DAC CODE – 16383)/16384} ·DIFF V = {(32 R /R ) · V (8) DIFF LOAD SET REFIO +5V REFLO AVDD ACOM 150pF +1.20V REF AD9754 V REFIO REFIO PMOS 0.1mF ICOMP I CURRENT SOURCE REF FS ADJ 0.1mF ARRAY V = V – V R DIFF OUTA OUTB SET 2kV DVDD +5V I IOUTA OUTA V OUTA SEGMENTED SWITCHES LSB I DCOM IOUTB OUTB FOR DB13–DB5 SWITCHES V OUTB R LOAD CLOCK R 50V LOAD CLOCK LATCHES 50V SLEEP DIGITAL DATA INPUTS (DB13–DB0) Figure 16. Functional Block Diagram REV. A –9– AD9754 These last two equations highlight some of the advantages of REFERENCE CONTROL AMPLIFIER operating the AD9754 differentially. First, the differential op- The AD9754 also contains an internal control amplifier that is eration will help cancel common-mode error sources associated used to regulate the DAC’s full-scale output current, I . OUTFS with IOUTA and IOUTB such as noise, distortion and dc off- The control amplifier is configured as a V-I converter, as shown sets. Second, the differential code-dependent current and in Figure 18, such that its current output, I , is determined by REF subsequent voltage, V , is twice the value of the single- DIFF AVDD ended voltage output (i.e., V or V ), thus providing OUTA OUTB twice the signal power to the load. REFLO AVDD Note that the gain drift temperature performance for a single- AVDD 150pF +1.2V REF ended (VOUTA and VOUTB) or differential output (V ) of DIFF V the AD9754 can be enhanced by selecting temperature tracking REFIO REFIO EXTERNAL CURRENT REF resistors for R and R due to their ratiometric relation- LOAD SET SOURCE FS ADJ ARRAY ship as shown in Equation 8. R I = SET REF V /R REFERENCE REFIO SET CONTROL REFERENCE OPERATION AD9754 AMPLIFIER The AD9754 contains an internal 1.20 V bandgap reference that can be easily disabled and overridden by an external Figure 18. External Reference Configuration reference. REFIO serves as either an input or output, depending on whether the internal or external reference is selected. If the ratio of the V and an external resistor, R , as stated REFIO SET REFLO is tied to ACOM, as shown in Figure 17, the internal in Equation 4. I is copied over to the segmented current REF reference is activated, and REFIO provides a 1.20 V output. In sources with the proper scaling factor to set I as stated in OUTFS this case, the internal reference must be compensated externally Equation 3. with a ceramic chip capacitor of 0.1mF or greater from REFIO The control amplifier allows a wide (10:1) adjustment span of to REFLO. Also, REFIO should be buffered with an external I over a 2 mA to 20 mA range by setting IREF between OUTFS amplifier having an input bias current less than 100 nA if any 62.5mA and 625mA. The wide adjustment span of I OUTFS additional loading is required. provides several application benefits. The first benefit relates +5V directly to the power dissipation of the AD9754, which is pro- OPTIONAL EXTERNAL portional to I (refer to the Power Dissipation section). The OUTFS REF BUFFER REFLO AVDD 150pF second benefit relates to the 20 dB adjustment, which is useful +1.2V REF for system gain control purposes. REFIO CURRENT The small signal bandwidth of the reference control amplifier ADDITIONAL FS ADJ SOURCE 0.1mF LOAD is approximately 0.5 MHz. The output of the control amplifier ARRAY 2kV is internally compensated via a 150 pF capacitor that limits the AD9754 control amplifier small-signal bandwidth and reduces its output impedance. Since the –3 dB bandwidth corresponds to the Figure 17. Internal Reference Configuration dominant pole, and hence the time constant, the settling time of the control amplifier to a stepped reference input response can The internal reference can be disabled by connecting REFLO to be approximated In this case, the time constant can be approxi- AVDD. In this case, an external reference may then be applied mated to be 320 ns. to REFIO as shown in Figure 18. The external reference may provide either a fixed reference voltage to enhance accuracy and There are two methods in which I can be varied for a fixed REF drift performance or a varying reference voltage for gain control. R . The first method is suitable for a single-supply system in SET Note that the 0.1mF compensation capacitor is not required which the internal reference is disabled, and the common-mode since the internal reference is disabled, and the high input im- voltage of REFIO is varied over its compliance range of 1.25 V pedance (i.e., 1 MW) of REFIO minimizes any loading of the to 0.10 V. REFIO can be driven by a single-supply amplifier or external reference. DAC, thus allowing I to be varied for a fixed R . Since the REF SET AVDD AVDD REFLO AVDD 150pF +1.2V REF R V FB DD 1.2V OUT1 0.1V TO 1.2V REFIO AD7524 V CURRENT REF SOURCE OUT2 FS ADJ AD1580 ARRAY AGND R I = SET REF AD9754 V /R REF SET DB7–DB0 Figure 19. Single-Supply Gain Control Circuit REV. A –10– AD9754 input impedance of REFIO is approximately 1 MW, a simple, AVDD low cost R-2R ladder DAC configured in the voltage mode topology may be used to control the gain. This circuit is shown AD9754 in Figure 19 using the AD7524 and an external 1.2 V reference, the AD1580. The second method may be used in a dual-supply system in which the common-mode voltage of REFIO is fixed, and I is REF varied by an external voltage, V , applied to R via an ampli- GC SET IOUTA IOUTB fier. An example of this method is shown in Figure 25 in which R R the internal reference is used to set the common-mode voltage LOAD LOAD of the control amplifier to 1.20 V. The external voltage, V , is GC referenced to ACOM and should not exceed 1.2 V. The value of Figure 21. Equivalent Analog Output Circuit R is such that I and I do not exceed 62.5mA SET REFMAX REFMIN and 625mA, respectively. The associated equations in Figure 20 IOUTA and IOUTB also have a negative and positive voltage can be used to determine the value of R . compliance range. The negative output compliance range of SET –1.0 V is set by the breakdown limits of the CMOS process. AVDD Operation beyond this maximum limit may result in a break- down of the output stage and affect the reliability of the AD9754. REFLO AVDD 150pF The positive output compliance range is slightly dependent on +1.2V REF the full-scale output current, I . It degrades slightly from its OUTFS REFIO nominal 1.25 V for an I = 20 mA to 1.00 V for an I = OUTFS OUTFS CURRENT SOURCE 1mF FS ADJ 2 mA. Operation beyond the positive compliance range will ARRAY R induce clipping of the output signal which severely degrades SET I REF AD9754 the AD9754’s linearity and distortion performance. I = (1.2 – V )/R REF GC SET For applications requiring the optimum dc linearity, IOUTA WITH V V AND 62.5mA I 625A V GC REFIO REF GC and/or IOUTB should be maintained at a virtual ground via an I-V op amp configuration. Maintaining IOUTA and/or IOUTB Figure 20. Dual-Supply Gain Control Circuit at a virtual ground keeps the output impedance of the AD9754 ANALOG OUTPUTS fixed, significantly reducing its effect on linearity. However, The AD9754 produces two complementary current outputs, it does not necessarily lead to the optimum distortion perfor- IOUTA and IOUTB, which may be configured for single-end mance due to limitations of the I-V op amp. Note that the or differential operation. IOUTA and IOUTB can be converted INL/DNL specifications for the AD9754 are measured in into complementary single-ended voltage outputs, V and OUTA this manner using IOUTA. In addition, these dc linearity V , via a load resistor, R , as described in the DAC OUTB LOAD specifications remain virtually unaffected over the specified Transfer Function section by Equations 5 through 8. The power supply range of +4.5 V to +5.5 V. differential voltage, V , existing between V and V DIFF OUTA OUTB Operating the AD9754 with reduced voltage output swings at can also be converted to a single-ended voltage via a transformer IOUTA and IOUTB in a differential or single-ended output or differential amplifier configuration. configuration reduces the signal dependency of its output Figure 21 shows the equivalent analog output circuit of the impedance thus enhancing distortion performance. Although AD9754 consisting of a parallel combination of PMOS differen- the voltage compliance range of IOUTA and IOUTB extends tial current switches associated with each segmented current from –1.0 V to +1.25 V, optimum distortion performance is source. The output impedance of IOUTA and IOUTB is deter- achieved when the maximum full-scale signal at IOUTA and mined by the equivalent parallel combination of the PMOS IOUTB does not exceed approximately 0.5 V. A properly se- switches and is typically 100 kW in parallel with 5 pF. Due to lected transformer with a grounded center-tap will allow the the nature of a PMOS device, the output impedance is also AD9754 to provide the required power and voltage levels to slightly dependent on the output voltage (i.e., V and V ) OUTA OUTB different loads while maintaining reduced voltage swings at and, to a lesser extent, the analog supply voltage, AVDD, and IOUTA and IOUTB. DC-coupled applications requiring a full-scale current, I . Although the output impedance’s signal OUTFS differential or single-ended output configuration should size dependency can be a source of dc nonlinearity and ac linearity R accordingly. Refer to Applying the AD9754 section for LOAD (i.e., distortion), its effects can be limited if certain precautions examples of various output configurations. are noted. REV. A –11– AD9754 The most significant improvement in the AD9754’s distortion The digital inputs are CMOS-compatible with logic thresholds, and noise performance is realized using a differential output V set to approximately half the digital positive supply THRESHOLD, configuration. The common-mode error sources of both (DVDD) or IOUTA and IOUTB can be substantially reduced by the V = DVDD/2 (–20%) THRESHOLD common-mode rejection of a transformer or differential am- The internal digital circuitry of the AD9754 is capable of operating plifier. These common-mode error sources include even-order over a digital supply range of 2.7 V to 5.5 V. As a result, the distortion products and noise. The enhancement in distortion digital inputs can also accommodate TTL levels when DVDD is performance becomes more significant as the reconstructed set to accommodate the maximum high level voltage of the TTL waveform’s frequency content increases and/or its amplitude drivers V . A DVDD of 3 V to 3.3 V will typically ensure OH(MAX) decreases. proper compatibility with most TTL logic families. Figure 22 The distortion and noise performance of the AD9754 is also shows the equivalent digital input circuit for the data and clock slightly dependent on the analog and digital supply as well as the inputs. The sleep mode input is similar with the exception that full-scale current setting, I . Operating the analog supply at OUTFS it contains an active pull-down circuit, thus ensuring that the 5.0 V ensures maximum headroom for its internal PMOS current AD9754 remains enabled if this input is left disconnected. sources and differential switches leading to improved distortion performance. Although I can be set between 2 mA and OUTFS DVDD 20 mA, selecting an I of 20 mA will provide the best OUTFS distortion and noise performance also shown in Figure 13. The noise performance of the AD9754 is affected by the digital sup- DIGITAL INPUT ply (DVDD), output frequency, and increases with increasing clock rate as shown in Figure 8. Operating the AD9754 with low voltage logic levels between 3 V and 3.3 V will slightly reduce the amount of on-chip digital noise. Figure 22. Equivalent Digital Input In summary, the AD9754 achieves the optimum distortion and noise performance under the following conditions: Since the AD9754 is capable of being updated up to 125 MSPS, the quality of the clock and data input signals are important in (1) Differential Operation. achieving the optimum performance. Operating the AD9754 (2) Positive voltage swing at IOUTA and IOUTB limited to with reduced logic swings and a corresponding digital supply +0.5 V. (DVDD) will result in the lowest data feedthrough and on-chip digital noise. The drivers of the digital data interface circuitry (3) I set to 20 mA. OUTFS should be specified to meet the minimum setup and hold times (4) Analog Supply (AVDD) set at 5.0 V. of the AD9754 as well as its required min/max input logic level (5) Digital Supply (DVDD) set at 3.0 V to 3.3 V with appro- thresholds. priate logic levels. Digital signal paths should be kept short and run lengths Note that the ac performance of the AD9754 is characterized matched to avoid propagation delay mismatch. The insertion of under the above mentioned operating conditions. a low value resistor network (i.e., 20W to 100W) between the AD9754 digital inputs and driver outputs may be helpful in DIGITAL INPUTS reducing any overshooting and ringing at the digital inputs that The AD9754’s digital input consists of 14 data input pins and a contribute to data feedthrough. For longer run lengths and high clock input pin. The 14-bit parallel data inputs follow standard data update rates, strip line techniques with proper termination positive binary coding where DB13 is the most significant bit resistors should be considered to maintain “clean” digital inputs. (MSB), and DB0 is the least significant bit (LSB). IOUTA The external clock driver circuitry should provide the AD9754 produces a full-scale output current when all data bits are at with a low jitter clock input meeting the min/max logic levels Logic 1. IOUTB produces a complementary output with the while providing fast edges. Fast clock edges will help minimize full-scale current split between the two outputs as a function of any jitter that will manifest itself as phase noise on a recon- the input code. structed waveform. Thus, the clock input should be driven by The digital interface is implemented using an edge-triggered the fastest logic family suitable for the application. master slave latch. The DAC output is updated following the Note, that the clock input could also be driven via a sine wave, rising edge of the clock as shown in Figure 1 and is designed to which is centered around the digital threshold (i.e., DVDD/2) support a clock rate as high as 125 MSPS. The clock can be and meets the min/max logic threshold. This will typically result operated at any duty cycle that meets the specified latch pulse in a slight degradation in the phase noise, which becomes more width. The setup and hold times can also be varied within the noticeable at higher sampling rates and output frequencies. clock cycle as long as the specified minimum times are met, Also, at higher sampling rates, the 20% tolerance of the digital although the location of these transition edges may affect digital logic threshold should be considered since it will affect the effec- feedthrough and distortion performance. Best performance is tive clock duty cycle and, subsequently, cut into the required typically achieved when the input data transitions on the falling data setup and hold times. edge of a 50% duty cycle clock. REV. A –12– AD9754 35 INPUT CLOCK AND DATA TIMING RELATIONSHIP SNR in a DAC is dependent on the relationship between the position of the clock edges and the point in time at which the 30 input data changes. The AD9754 is positive edge triggered, and so exhibits SNR sensitivity when the data transition is close to 25 this edge. In general, the goal when applying the AD9754 is to make the data transitions close to the negative clock edge. This 20 becomes more important as the sample rate increases. Figure 23 shows the relationship of SNR to clock placement. 15 68 10 F = 65MSPS S 64 5 22 4 6 8 10 12 14 16 180 60 I – mA OUTFS Figure 24. I vs. I AVDD OUTFS 56 18 52 125MSPS 16 48 14 F = 125MSPS S 100MSPS 44 12 10 40 0 –8 –6 –4 –2 2 468 10 8 TIME (ns) OF DATA CHANGE RELATIVE TO RISING CLOCK EDGE 50MSPS 6 Figure 23. SNR vs. Clock Placement @ f = 10 MHz OUT 4 25MSPS 2 SLEEP MODE OPERATION 5MSPS The AD9754 has a power-down function that turns off the 0 0.01 0.1 1 output current and reduces the supply current to less than RATIO (f /f ) CLOCK OUT 8.5 mA over the specified supply range of 2.7 V to 5.5 V and temperature range. This mode can be activated by applying a Figure 25. I vs. Ratio @ DVDD = 5 V DVDD logic level “1” to the SLEEP pin. This digital input also con- tains an active pull-down circuit that ensures the AD9754 re- mains enabled if this input is left disconnected. The AD9754 8 takes less than 50 ns to power down and approximately 5ms to 125MSPS power back up. 6 100MSPS POWER DISSIPATION The power dissipation, P , of the AD9754 is dependent on D several factors, including: (1) AVDD and DVDD, the power 4 supply voltages; (2) I , the full-scale current output; (3) OUTFS f , the update rate; and (4) the reconstructed digital input CLOCK 50MSPS waveform. The power dissipation is directly proportional to the 2 analog supply current, I , and the digital supply current, AVDD 25MSPS I . I is directly proportional to I as shown in DVDD AVDD OUTFS, Figure 24, and is insensitive to f . CLOCK 5MSPS 0 Conversely, I is dependent on both the digital input wave- 0.01 0.1 1 DVDD RATIO (f /f ) CLOCK OUT form, f , and digital supply DVDD. Figures 25 and 26 CLOCK show I as a function of full-scale sine wave output ratios DVDD Figure 26. I vs. Ratio @ DVDD = 3 V DVDD (f /f ) for various update rates with DVDD = 5 V and OUT CLOCK DVDD = 3 V, respectively. Note, how I is reduced by more DVDD than a factor of 2 when DVDD is reduced from 5 V to 3 V. REV. A –13– SNR – dB I – mA I – mA I – mA DVDD DVDD AVDD AD9754 APPLYING THE AD9754 DIFFERENTIAL USING AN OP AMP OUTPUT CONFIGURATIONS An op amp can also be used to perform a differential-to-single- The following sections illustrate some typical output configura- ended conversion as shown in Figure 28. The AD9754 is con- tions for the AD9754. Unless otherwise noted, it is assumed figured with two equal load resistors, R , of 25 W. The LOAD that I is set to a nominal 20 mA. For applications requir- differential voltage developed across IOUTA and IOUTB is OUTFS ing the optimum dynamic performance, a differential output converted to a single-ended signal via the differential op amp configuration is suggested. A differential output configuration configuration. An optional capacitor can be installed across may consist of either an RF transformer or a differential op amp IOUTA and IOUTB, forming a real pole in a low-pass filter. configuration. The transformer configuration provides the opti- The addition of this capacitor also enhances the op amp’s dis- mum high frequency performance and is recommended for any tortion performance by preventing the DAC’s high slewing application allowing for ac coupling. The differential op amp output from overloading the op amp’s input. configuration is suitable for applications requiring dc coupling, a The common-mode rejection of this configuration is typically bipolar output, signal gain and/or level shifting. determined by the resistor matching. In this circuit, the differ- A single-ended output is suitable for applications requiring a ential op amp circuit is configured to provide some additional unipolar voltage output. A positive unipolar output voltage will signal gain. The op amp must operate from a dual supply since result if IOUTA and/or IOUTB is connected to an appropri- its output is approximately –1.0 V. A high speed amplifier such ately sized load resistor, R , referred to ACOM. This con- as the AD8055 or AD9632 capable of preserving the differential LOAD figuration may be more suitable for a single-supply system 500V requiring a dc coupled, ground referred output voltage. Alterna- tively, an amplifier could be configured as an I-V converter, thus AD9754 225V converting IOUTA or IOUTB into a negative unipolar voltage. IOUTA 22 This configuration provides the best dc linearity since IOUTA AD8055 225V or IOUTB is maintained at a virtual ground. Note, IOUTA 21 IOUTB C OPT provides slightly better performance than IOUTB. 500V 25V 25V DIFFERENTIAL COUPLING USING A TRANSFORMER An RF transformer can be used to perform a differential-to- single-ended signal conversion as shown in Figure 27. A Figure 28. DC Differential Coupling Using an Op Amp differentially coupled transformer output provides the optimum performance of the AD9754 while meeting other system level distortion performance for output signals whose spectral content objectives (i.e., cost, power) should be selected. The op amps lies within the transformer’s passband. An RF transformer such differential gain, its gain setting resistor values and full-scale as the Mini-Circuits T1-1T provides excellent rejection of output swing capabilities should all be considered when opti- common-mode distortion (i.e., even-order harmonics) and noise mizing this circuit. over a wide frequency range. It also provides electrical isolation and the ability to deliver twice the power to the load. Trans- The differential circuit shown in Figure 29 provides the neces- formers with different impedance ratios may also be used for sary level-shifting required in a single supply system. In this impedance matching purposes. Note that the transformer case, AVDD, which is the positive analog supply for both the provides ac coupling only. AD9754 and the op amp, is also used to level-shift the differ- ential output of the AD9754 to midsupply (i.e., AVDD/2). The MINI-CIRCUITS AD8041 is a suitable op amp for this application. T1-1T 22 IOUTA 500V AD9754 R LOAD AD9754 225V 21 22 IOUTB IOUTA OPTIONAL R DIFF AD8041 225V IOUTB 21 C OPT 1kV Figure 27. Differential Output Using a Transformer AVDD 1kV 25V 25V The center tap on the primary side of the transformer must be connected to ACOM to provide the necessary dc current path for both IOUTA and IOUTB. The complementary voltages Figure 29. Single-Supply DC Differential Coupled Circuit appearing at IOUTA and IOUTB (i.e., V and V ) OUTA OUTB swing symmetrically around ACOM and should be maintained with the specified output compliance range of the AD9754. A differential resistor, R , may be inserted in applications in DIFF which the output of the transformer is connected to the load, R , via a passive reconstruction filter or cable. R is deter- LOAD DIFF mined by the transformer’s impedance ratio and provides the proper source termination that results in a low VSWR. Note that approximately half the signal power will be dissipated across R . DIFF REV. A –14– AD9754 SINGLE-ENDED UNBUFFERED VOLTAGE OUTPUT POWER AND GROUNDING CONSIDERATIONS, POWER Figure 30 shows the AD9754 configured to provide a unipolar SUPPLY REJECTION output range of approximately 0 V to +0.5 V for a doubly termi- Many applications seek high speed and high performance under nated 50W cable since the nominal full-scale current, I , of less than ideal operating conditions. In these circuits, the imple- OUTFS 20 mA flows through the equivalent R of 25W. In this case, mentation and construction of the printed circuit board design LOAD R represents the equivalent load resistance seen by IOUTA is as important as the circuit design. Proper RF techniques must LOAD or IOUTB. The unused output (IOUTA or IOUTB) can be be used for device selection, placement and routing as well as connected to ACOM directly or via a matching R . Different power supply bypassing and grounding to ensure optimum LOAD values of I and R can be selected as long as the posi- performance. Figures 39-44 illustrate the recommended printed OUTFS LOAD tive compliance range is adhered to. One additional consider- circuit board ground, power and signal plane layouts which are ation in this mode is the integral nonlinearity (INL) as discussed implemented on the AD9754 evaluation board. in the Analog Output section of this data sheet. For optimum One factor that can measurably affect system performance is the INL performance, the single-ended, buffered voltage output ability of the DAC output to reject dc variations or ac noise configuration is suggested. superimposed on the analog or digital dc power distribution (i.e., AVDD, DVDD). This is referred to as Power Supply Rejection Ratio (PSRR). For dc variations of the power supply, AD9754 I = 20mA OUTFS V = 0 TO +0.5V OUTA the resulting performance of the DAC directly corresponds to a 22 IOUTA gain error associated with the DAC’s full-scale current, I . OUTFS 50V 50V AC noise on the dc supplies is common in applications where 21 IOUTB the power distribution is generated by a switching power supply. 25V Typically, switching power supply noise will occur over the spectrum from tens of kHz to several MHz. PSRR vs. frequency of the AD9754 AVDD supply, over this frequency range, is Figure 30. 0 V to +0.5 V Unbuffered Voltage Output given in Figure 32. SINGLE-ENDED BUFFERED VOLTAGE OUTPUT 90 CONFIGURATION Figure 31 shows a buffered single-ended output configuration in which the op amp U1 performs an I-V conversion on the AD9754 output current. U1 maintains IOUTA (or IOUTB) at a virtual ground, thus minimizing the nonlinear output impedance effect 80 on the DAC’s INL performance as discussed in the Analog Output section. Although this single-ended configuration typi- cally provides the best dc linearity performance, its ac distortion performance at higher DAC update rates may be limited by 70 U1’s slewing capabilities. U1 provides a negative unipolar output voltage and its full-scale output voltage is simply the product of R and I . The full-scale output should be set FB OUTFS within U1’s voltage output swing capabilities by scaling I OUTFS 60 and/or R . An improvement in ac distortion performance may 0.26 0.5 0.75 1.0 FB FREQUENCY – MHz result with a reduced I since the signal current U1 will be OUTFS required to sink will be subsequently reduced. Figure 32. Power Supply Rejection Ratio of AD9754 Note that the units in Figure 32 are given in units of (amps out)/ C OPT (volts in). Noise on the analog power supply has the effect of modulating the internal switches, and therefore the output R FB 200V current. The voltage noise on the dc power, therefore, will be I = 10mA AD9754 OUTFS added in a nonlinear manner to the desired I . Due to the OUT IOUTA 22 relative different sizes of these switches, PSRR is very code U1 V = I 3 R dependent. This can produce a mixing effect which can modu- OUT OUTFS FB IOUTB 21 late low frequency power supply noise to higher frequencies. 200V Worst case PSRR for either one of the differential DAC outputs will occur when the full-scale current is directed towards that output. As a result, the PSRR measurement in Figure 32 repre- Figure 31. Unipolar Buffered Voltage Output sents a worst case condition in which the digital inputs remain static and the full-scale output current of 20 mA is directed to the DAC output being measured. REV. A –15– PSRR – dB AD9754 An example serves to illustrate the effect of supply noise on the The use of wide runs or planes in the routing of power lines is analog supply. Suppose a switching regulator with a switching also recommended. This serves the dual role of providing a low frequency of 250 kHz produces 10 mV rms of noise and for series impedance power supply to the part, as well as providing simplicity sake (i.e., ignore harmonics), all of this noise is con- some “free” capacitive decoupling to the appropriate ground centrated at 250 kHz. To calculate how much of this undesired plane. It is essential that care be taken in the layout of signal and noise will appear as current noise super imposed on the DAC’s power ground interconnects to avoid inducing extraneous volt- full-scale current, I , one must determine the PSRR in dB age drops in the signal ground paths. It is recommended that all OUTFS using Figure 32 at 250 kHz. To calculate the PSRR for a given connections be short, direct and as physically close to the pack- R , such that the units of PSRR are converted from A/V to age as possible in order to minimize the sharing of conduction LOAD V/V, adjust the curve in Figure 32 by the scaling factor 20 · Log paths between different currents. When runs exceed an inch in (R ). For instance, if R is 50 W, the PSRR is reduced length, strip line techniques with proper termination resistors LOAD LOAD by 34 dB (i.e., PSRR of the DAC at 1 MHz which is 74 dB in should be considered. The necessity and value of this resistor Figure 32 becomes 40 dB V /V ). will be dependent upon the logic family used. OUT IN Proper grounding and decoupling should be a primary objective For a more detailed discussion of the implementation and in any high speed, high resolution system. The AD9754 features construction of high speed, mixed signal printed circuit boards, separate analog and digital supply and ground pins to optimize refer to Analog Devices’ application notes AN-280 and AN-333. the management of analog and digital ground currents in a system. In general, AVDD, the analog supply, should be decoupled MULTITONE PERFORMANCE CONSIDERATIONS AND to ACOM, the analog common, as close to the chip as physi- CHARACTERIZATION cally possible. Similarly, DVDD, the digital supply, should be The frequency domain performance of high speed DACs has decoupled to DCOM as close as physically as possible. traditionally been characterized by analyzing the spectral output of a reconstructed full-scale (i.e., 0 dBFS), single-tone sine wave For those applications requiring a single +5 V or +3 V supply at a particular output frequency and update rate. Although this for both the analog and digital supply, a clean analog supply characterization data is useful, it is often insufficient to reflect a may be generated using the circuit shown in Figure 33. The DAC’s performance for a reconstructed multitone or spread- circuit consists of a differential LC filter with separate power spectrum waveform. In fact, evaluating a DAC’s spectral supply and return lines. Lower noise can be attained using low performance using a full-scale, single tone at the highest specified ESR type electrolytic and tantalum capacitors. frequency (i.e., f ) of a bandlimited waveform is typically H indicative of a DAC’s “worst-case” performance for that given FERRITE BEADS waveform. In the time domain, this full-scale sine wave represents TTL/CMOS AVDD LOGIC the lowest peak-to-rms ratio or crest factor (i.e., V /V rms) PEAK 100mF 10-22mF 0.1mF CIRCUITS TANT. CER. that this bandlimited signal will encounter. ELECT. ACOM –10 –20 +5V OR +3V POWER SUPPLY –30 –40 Figure 33. Differential LC Filter for Single +5 V or +3 V –50 Applications –60 Maintaining low noise on power supplies and ground is critical –70 to obtain optimum results from the AD9754. If properly implemented, ground planes can perform a host of functions on –80 high speed circuit boards: bypassing, shielding current trans- –90 port, etc. In mixed signal design, the analog and digital portions –100 of the board should be distinct from each other, with the analog –110 ground plane confined to the areas covering the analog signal 2.19 2.25 2.31 2.38 2.44 2.50 2.56 2.63 2.69 2.75 2.81 traces, and the digital ground plane confined to areas covering FREQUENCY – MHz the digital interconnects. Figure 34a. Multitone Spectral Plot All analog ground pins of the DAC, reference and other analog However, the inherent nature of a multitone, spread spectrum, components should be tied directly to the analog ground plane. or QAM waveform, in which the spectral energy of the wave- The two ground planes should be connected by a path 1/8 to form is spread over a designated bandwidth, will result in a 1/4 inch wide underneath or within 1/2 inch of the DAC to higher peak-to-rms ratio when compared to the case of a simple maintain optimum performance. Care should be taken to ensure sine wave. As the reconstructed waveform’s peak-to-average that the ground plane is uninterrupted over crucial signal paths. ratio increases, an increasing amount of the signal energy is On the digital side, this includes the digital input lines running concentrated around the DAC’s midscale value. Figure 34a is to the DAC as well as any clock signals. On the analog side, this just one example of a bandlimited multitone vector (i.e., eight includes the DAC output signal, reference signal and the supply tones) centered around one-half the Nyquist bandwidth (i.e., feeders. REV. A –16– MAGNITUDE – dBm AD9754 f /4). This particular multitone vector, has a peak-to-rms well as other TxDAC members) exhibits an improvement in CLOCK ratio of 13.5 dB compared to a sine waves peak-to-rms ratio of distortion performance as the amplitude of a single tone is re- 3 dB. A “snapshot” of this reconstructed multitone vector in the duced from its full-scale level. This improvement in distortion time domain as shown in Figure 34b reveals the higher signal performance at reduced signal levels is evident if one compares content around the midscale value. As a result, a DAC’s “small- the SFDR performance vs. frequency at different amplitudes scale” dynamic and static linearity becomes increasingly criti- (i.e., 0 dBFS, –6 dBFS and –12 dBFS) and sample rates as cal in obtaining low intermodulation distortion and maintaining shown in Figures 4 through 7. Maintaining decent “small-scale” sufficient carrier-to-noise ratios for a given modulation scheme. linearity across the full span of a DAC transfer function is also critical in maintaining excellent multitone performance. A DAC’s small-scale linearity performance is also an important consideration in applications where additive dynamic range is Although characterizing a DAC’s multitone performance tends required for gain control purposes or “predistortion” signal to be application-specific, much insight into the potential perfor- conditioning. For instance, a DAC with sufficient dynamic mance of a DAC can also be gained by evaluating the DAC’s range can be used to provide additional gain control of its swept power (i.e., amplitude) performance for single, dual and reconstructed signal. In fact, the gain can be controlled in multitone test vectors at different clock rates and carrier frequen- 6 dB increments by simply performing a shift left or right on the cies. The DAC is evaluated at different clock rates when recon- DAC’s digital input word. Other applications may intentionally structing a specific waveform whose amplitude is decreased in 3 dB increments from full-scale (i.e., 0 dBFS). For each specific waveform, a graph showing the SFDR (over Nyquist) perfor- 1.0000 mance vs. amplitude can be generated at the different tested 0.8000 clock rates as shown in Figures 9–11. Note that the carrier(s)-to- 0.6000 clock ratio remains constant in each figure. In each case, an 0.4000 improvement in SFDR performance is seen as the amplitude is reduced from 0 dBFS to approximately –9.0 dBFS. 0.2000 0.0000 A multitone test vector may consist of several equal amplitude, spaced carriers each representative of a channel within a defined –0.2000 bandwidth as shown in Figure 37a. In many cases, one or more –0.4000 tones are removed so the intermodulation distortion performance –0.6000 of the DAC can be evaluated. Nonlinearities associated with the –0.8000 DAC will create spurious tones of which some may fall back into the “empty” channel thus limiting a channel’s carrier-to-noise –1.0000 TIME ratio. Other spurious components falling outside the band of interest may also be important, depending on the system’s spectral Figure 34b. Time Domain “Snapshot” of the Multitone mask and filtering requirements. Waveform This particular test vector was centered around one-half the predistort a DAC’s digital input signal to compensate for Nyquist bandwidth (i.e., f /4) with a passband of f /16. CLOCK CLOCK nonlinearities associated with the subsequent analog compo- Centering the tones at a much lower region (i.e., f /10) CLOCK nents in the signal chain. For example, the signal compression would lead to an improvement in performance while centering associated with a power amplifier can be compensated for by the tones at a higher region (i.e., f /2.5) would result in a CLOCK predistorting the DAC’s digital input with the inverse nonlinear degradation in performance. transfer function of the power amplifier. In either case, the DAC’s performance at reduced signal levels should be carefully evaluated. A full-scale single tone will induce all of the dynamic and static nonlinearities present in a DAC that contribute to its distortion and hence SFDR performance. Referring to Figure 3, as the frequency of this reconstructed full-scale, single-tone waveform increases, the dynamic nonlinearities of any DAC (i.e., AD9754) tend to dominate thus contributing to the roll-off in its SFDR performance. However, unlike most DACs, which employ an R-2R ladder for the lower bit current segmentation, the AD9754 (as REV. A –17– VOLTS AD9754 APPLICATIONS –30 VDSL Applications Using the AD9754 –40 Very High Frequency Digital Subscriber Line (VDSL) technol- ogy is growing rapidly in applications requiring data transfer –50 over relatively short distances. By using QAM modulation and –60 transmitting the data in multiple discrete tones, high data rates can be achieved. –70 As with other multitone applications, each VDSL tone is ca- –80 pable of transmitting a given number of bits, depending on the signal to noise ratio (SNR) in a narrow band around that tone. –90 The tones are evenly spaced over the range of several kHz to –100 10 MHz. At the high frequency end of this range, performance is generally limited by cable characteristics and environmental –110 4.8 5.0 5.2 factors, such as external interferers. Performance at the lower FREQUENCY – MHz frequencies is much more dependent on the performance of the Figure 35b. Notch in missing bin at 5 MHz is down components in the signal chain. In addition to in-band noise, >60 dB. Peak amplitude = 0 dBm. intermodulation from other tones can also potentially interfere with the recovery of data for a given tone. The two graphs in CDMA Figure 35 represent a 500 tone missing bin test vector, with Carrier Division Multiple Access, or CDMA, is an air transmit/ frequencies evenly spaced from 400 Hz to 10 MHz. This test is receive scheme where the signal in the transmit path is modu- very commonly done to determine if distortion will limit the lated with a pseudorandom digital code (sometimes referred to number of bits which can transmitted in a tone. The test vector as the spreading code). The effect of this is to spread the trans- has a series of missing tones around 750 kHz, which is represented mitted signal across a wide spectrum. Similar to a DMT wave- in Figure 35a, and a series of missing tones around 5 MHz, form, a CDMA waveform containing multiple subscribers can which is represented in Figure 35b. In both cases, the spurious be characterized as having a high peak to average ratio (i.e., free range between the transmitted tones and the empty bins is crest factor), thus demanding highly linear components in the greater than 60 dB. transmit signal path. The bandwidth of the spectrum is defined by the CDMA standard being used, and in operation is imple- –30 mented by using a spreading code with particular characteristics. –40 Distortion in the transmit path can lead to power being trans- mitted out of the defined band. The ratio of power transmitted –50 in-band to out-of-band is often referred to as Adjacent Channel Power (ACP). This is a regulatory issue due to the possibility of –60 interference with other signals being transmitted by air. Regula- –70 tory bodies define a spectral mask outside of the transmit band, and the ACP must fall under this mask. If distortion in the –80 transmit path cause the ACP to be above the spectral mask, –90 then filtering, or different component selection is needed to meet the mask requirements. –100 Figure 36 shows an example of the AD9754 used in a W-CDMA –110 transmitter application using the AD6122 CDMA 3 V transmit- 600k 800k 1.0M FREQUENCY – Hz ter IF subsystem. The AD6122 has functions, such as external gain control and low distortion characteristics, needed for the Figure 35a. Notch in missing bin at 750 kHz is down superior Adjacent Channel Power (ACP) requirements of >60 dB. Peak amplitude = 0 dBm. WCDMA. REV. A –18– AMPLITUDE – dBm AMPLITUDE – dBm AD9754 +3V DVDD 634V 100W REFLO AVDD 500V 500V REFIO AD9754 AD6122 500V IIPP IOUTA (“I DAC”) U1 FSADJ DAC C FILTER R SET1 2kV LATCHES IOUTB 500V IIPN I DATA 100V INPUT AVDD CLK LOIPP PHASE 42 LOIPN SPLITTER AVDD REFLO 500V 500V QOUTA IIQP LATCHES 500V Q DATA MODOPP U2 INPUT DAC 500V AD9754 MODOPN (“Q DAC”) QOUTB IIQN 100V TEMPERATURE 100V REFIO FSADJ SLEEP COMPENSATION R REFIN SET2 V V CC CC 1.9kV 0.1mF GAIN DCOM CONTROL R CAL SCALE 220V FACTOR GAIN ACOM CONTROL VGAIN TXOPP TXOPN Figure 36. CDMA Transmit Application Using AD9754 Figure 37 shows the AD9754 reconstructing a wideband, or AD9754 EVALUATION BOARD W-CDMA test vector with a bandwidth of 5 MHz, centered at General Description 15.625 MHz and being sampled at 62.5 MSPS. ACP for the The AD9754-EB is an evaluation board for the AD9754 14-bit given test vector is measured at 70 dB. DAC converter. Careful attention to layout and circuit design, combined with a prototyping area, allows the user to easily and –20 effectively evaluate the AD9754 in any application where high resolution, high speed conversion is required. –30 This board allows the user the flexibility to operate the AD9754 –40 in various configurations. Possible output configurations in- –50 clude transformer coupled, resistor terminated, inverting/ –60 noninverting and differential amplifier outputs. The digital inputs –70 are designed to be driven directly from various word generators with the onboard option to add a resistor network for proper –80 load termination. Provisions are also made to operate the –90 AD9754 with either the internal or external reference or to –100 exercise the power-down feature. –110 Refer to the application note AN-420 for a thorough description –120 and operating instructions for the AD9754 evaluation board. 13.125 15.625 18.125 FREQUENCY – MHz Figure 37. CDMA Signal, Sampled at 65 MSPS, Adjacent Channel Power >70 dB REV. A –19– REFERENCE LEVEL – dBm AD9754 Figure 38. Evaluation Board Schematic REV. A –20– DVDD DGND AVDD AGND AVEE AVCC B1 B2 B3 B4 B5 B6 TP19 TP3 TP2 TP4 TP6 TP7 TP18 TP5 CLK TP1 J1 JP1 C3 C4 A C5 A C6 A A B 10mF 10mF 10mF 10mF EXTCLK 1 2 3 R15 DVDD DVDD 49.9V R1 R7 R5 R3 16 PINDIP U1 AVDD TP8 1 1 1 1 RES PK C7 C8 C9 P1 AD975x 1mF 0.1mF 0.1mF 2 3 4 5 6 7 8 9 10 2 3 4 5 6 7 8 9 10 2 3 4 5 6 7 8 9 10 2 3 4 5 6 7 8 9 10 C19 1 16 2 1 1 28 DB13 A CLOCK 2 4 3 C1 15 2 27 DB12 DVDD 6 5 C2 3 14 3 26 DB11 DCOM 8 7 C25 4 13 4 25 DB10 NC 10 9 C26 5 12 5 24 DB9 AVDD AVDD 12 11 C27 6 11 6 23 DB8 ICOMP OUT 1 14 13 C28 7 10 7 22 DB7 IOUTA OUT 2 16 15 C29 8 9 8 21 DB6 IOUTB 18 17 9 20 DB5 ACOM 20 19 10 19 DB4 NC 22 21 11 18 DB3 FS ADJ 24 23 16 PINDIP 12 17 DB2 REFIO 25 RES PK 26 13 16 DB1 REFLO 28 27 14 15 DB0 SLEEP TP11 TP10 TP9 TP13 29 30 C30 1 16 32 31 A C31 2 15 R16 34 33 CT1 AVDD C32 3 14 2kV 36 35 C33 4 13 C11 C10 A 38 37 TP14 C34 5 12 0.1mF 0.1mF 1 40 39 C35 6 11 C36 7 10 2 JP4 3 JP2 10 98 76 54 32 10 98 76 54 32 10 98 76 54 32 10 98 76 54 32 PDIN TP12 A A A J2 AVDD 1 1 1 1 R6 R4 R2 R8 R17 49.9V DVDD DVDD AVCC R18 1kV AVCC U7 AVCC J3 A C21 C22 R42 3 B JP6A 0.1mF 1mF OUT1 JP7B REF43 C17 JP7A 1kV 2 6 JP3 U4 0.1mF VIN VOUT 2 3 J6 J7 JP8 7 A GND R12 C18 C16 C12 6 U6 R20 1 A A OPEN AD8047 0.1mF 1mF 22pF B B B 49.9V T1 4 3 7 2 R37 R43 4 A C20 4 49.9V 5kV 6 R10 CW 3 0 A A AD8047 A 1kV A A 2 5 A A A R14 A 4 AVEE 0 JP6B EXTREFIN A R36 JP5 1 C14 1kV J5 R45 1mF 6 1kV 3 2 1 R13 A R9 R35 J4 A OPEN A 1kV 1kV C15 R44 OUT2 C23 C24 0.1mF 50V R46 0.1mF 1mF A A JP9 A 1kV B A C13 A R38 A 49.9V 22pF AVEE A A AD9754 Figure 39. Silkscreen Layer—Top Figure 40. Component Side PCB Layout (Layer 1) REV. A –21– AD9754 Figure 41. Ground Plane PCB Layout (Layer 2) Figure 42. Power Plane PCB Layout (Layer 3) REV. A –22– AD9754 Figure 43. Solder Side PCB Layout (Layer 4) Figure 44. Silkscreen Layer—Bottom REV. A –23– AD9754 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead, 300 Mil SOIC (R-28) 0.7125 (18.10) 0.6969 (17.70) 28 15 0.2992 (7.60) 0.2914 (7.40) 0.4193 (10.65) 0.3937 (10.00) 1 14 PIN 1 0.1043 (2.65) 0.0291 (0.74) x 458 0.0926 (2.35) 0.0098 (0.25) 0.0500 (1.27) 88 0.0118 (0.30) 0.0500 0.0192 (0.49) 08 0.0157 (0.40) SEATING 0.0125 (0.32) (1.27) 0.0040 (0.10) 0.0138 (0.35) PLANE BSC 0.0091 (0.23) 28-Lead Thin Shrink Small Outline (RU-28) 0.386 (9.80) 0.378 (9.60) 15 28 0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25) 1 14 PIN 1 0.006 (0.15) 0.002 (0.05) 0.0433 (1.10) MAX 0.028 (0.70) 88 0.0118 (0.30) 0.0256 (0.65) 08 0.020 (0.50) SEATING 0.0079 (0.20) BSC 0.0075 (0.19) PLANE 0.0035 (0.090) –24– REV. A PRINTED IN U.S.A. C3333a–1–9/99