ANALOG DEVICES AD9752

12-Bit, 125 MSPS High Performance a ® TxDAC D/A Converter AD9752* FEATURES FUNCTIONAL BLOCK DIAGRAM +5V High Performance Member of Pin-Compatible TxDAC Product Family REFLO AVDD ACOM 150pF 125 MSPS Update Rate +1.20V REF AD9752 0.1mF 12-Bit Resolution REFIO 0.1mF CURRENT ICOMP Excellent Spurious Free Dynamic Range Performance FS ADJ SOURCE ARRAY SFDR to Nyquist @ 5 MHz Output: 79 dBc R SET +5V DVDD IOUTA Differential Current Outputs: 2 mA to 20 mA LSB SEGMENTED DCOM IOUTB SWITCHES SWITCHES Power Dissipation: 185 mW @ 5 V CLOCK Power-Down Mode: 20 mW @ 5 V CLOCK LATCHES SLEEP On-Chip 1.20 V Reference DIGITAL DATA INPUTS (DB11–DB0) CMOS-Compatible +2.7 V to +5.5 V Digital Interface Package: 28-Lead SOIC and TSSOP The AD9752 is a current-output DAC with a nominal full-scale Edge-Triggered Latches output current of 20 mA and > 100 kW output impedance. APPLICATIONS Differential current outputs are provided to support single- Wideband Communication Transmit Channel: ended or differential applications. Matching between the two Direct IF current outputs ensures enhanced dynamic performance in a Basestations differential output configuration. The current outputs may be Wireless Local Loop tied directly to an output resistor to provide two complemen- Digital Radio Link tary, single-ended voltage outputs or fed directly into a trans- Direct Digital Synthesis (DDS) former. The output voltage compliance range is 1.25 V. Instrumentation The on-chip reference and control amplifier are configured for maximum accuracy and flexibility. The AD9752 can be driven PRODUCT DESCRIPTION by the on-chip reference or by a variety of external reference The AD9752 is a 12-bit resolution, wideband, second generation voltages. The internal control amplifier, which provides a wide member of the TxDAC series of high performance, low power (>10:1) adjustment span, allows the AD9752 full-scale current CMOS digital-to-analog-converters (DACs). The TxDAC family, to be adjusted over a 2 mA to 20 mA range while maintaining which consists of pin compatible 8-, 10-, 12-, and 14-bit DACs, is excellent dynamic performance. Thus, the AD9752 may oper- specifically optimized for the transmit signal path of communica- ate at reduced power levels or be adjusted over a 20 dB range to tion systems. All of the devices share the same interface options, provide additional gain ranging capabilities. small outline package and pinout, thus providing an upward or downward component selection path based on performance, The AD9752 is available in 28-lead SOIC and TSSOP packages. resolution and cost. The AD9752 offers exceptional ac and dc It is specified for operation over the industrial temperature range. performance while supporting update rates up to 125 MSPS. PRODUCT HIGHLIGHTS The AD9752’s flexible single-supply operating range of 4.5 V to 1. The AD9752 is a member of the wideband TxDAC product 5.5 V and low power dissipation are well suited for portable and family that provides an upward or downward component selec- low power applications. Its power dissipation can be further tion path based on resolution (8 to 14 bits), performance and reduced to a mere 65 mW, without a significant degradation in cost. The entire family of TxDACs is available in industry performance, by lowering the full-scale current output. Also, a standard pinouts. power-down mode reduces the standby power dissipation to 2. Manufactured on a CMOS process, the AD9752 uses a approximately 20 mW. proprietary switching technique that enhances dynamic The AD9752 is manufactured on an advanced CMOS process. performance beyond that previously attainable by higher A segmented current source architecture is combined with a power/cost bipolar or BiCMOS devices. proprietary switching technique to reduce spurious components 3. On-chip, edge-triggered input CMOS latches interface readily and enhance dynamic performance. Edge-triggered input latches to +2.7 V to +5 V CMOS logic families. The AD9752 can and a 1.2 V temperature compensated bandgap reference have support update rates up to 125 MSPS. been integrated to provide a complete monolithic DAC solution. 4. A flexible single-supply operating range of 4.5 V to 5.5 V and The digital inputs support +2.7 V to +5 V CMOS logic families. a wide full-scale current adjustment span of 2 mA to 20 mA TxDAC is a registered trademark of Analog Devices, Inc. *Protected by U.S. Patents Numbers 5450084, 5568145, 5689257, 5612697 and allow the AD9752 to operate at reduced power levels. 5703519. 5. The current output(s) of the AD9752 can be easily config- REV. 0 ured for various single-ended or differential circuit topologies. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: http://www.analog.com otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 1999 AD9752–SPECIFICATIONS DC SPECIFICATIONS (T to T , AVDD = +5 V, DVDD = +5 V, I = 20 mA, unless otherwise noted) MIN MAX OUTFS Parameter Min Typ Max Units RESOLUTION 12 Bits 1 DC ACCURACY Integral Linearity Error (INL) T = +25°C –1.5–0.5 +1.5 LSB A T to T –2.0 +2.0 LSB MIN MAX Differential Nonlinearity (DNL) T = +25°C –0.75–0.25 +0.75 LSB A T to T –1.0 +1.0 LSB MIN MAX ANALOG OUTPUT Offset Error –0.02 +0.02 % of FSR Gain Error (Without Internal Reference) –2–0.5 +2 % of FSR Gain Error (With Internal Reference) –5–1.5 +5 % of FSR 2 Full-Scale Output Current 2.0 20.0 mA Output Compliance Range –1.0 1.25 V Output Resistance 100 kW Output Capacitance 5 pF REFERENCE OUTPUT Reference Voltage 1.14 1.20 1.26 V 3 Reference Output Current 100 nA REFERENCE INPUT Input Compliance Range 0.1 1.25 V Reference Input Resistance 1 MW Small Signal Bandwidth 0.5 MHz TEMPERATURE COEFFICIENTS Offset Drift 0 ppm of FSR/°C Gain Drift (Without Internal Reference)–50 ppm of FSR/°C Gain Drift (With Internal Reference)–100 ppm of FSR/°C Reference Voltage Drift–50 ppm/°C POWER SUPPLY Supply Voltages AVDD 4.5 5.0 5.5 V DVDD 2.7 5.0 5.5 V 4 Analog Supply Current (I ) 34 39 mA AVDD 5 Digital Supply Current (I ) 35 mA DVDD 6 Supply Current Sleep Mode (I ) 48 mA AVDD 5 Power Dissipation (5 V, I = 20 mA) 185 220 mW OUTFS 7 Power Supply Rejection Ratio —AVDD –0.4 +0.4 % of FSR/V 7 Power Supply Rejection Ratio —DVDD –0.025 +0.025 % of FSR/V OPERATING RANGE –40 +85 °C NOTES 1 Measured at IOUTA, driving a virtual ground. 2 Nominal full-scale current, I , is 32 · the I current. OUTFS REF 3 Use an external buffer amplifier to drive any external load. 4 Requires +5 V supply. 5 Measured at f = 25 MSPS and I = static full scale (20 mA). CLOCK OUT 6 Logic level for SLEEP pin must be referenced to AVDD. Min V = 3.5 V. IH 7 –5% Power supply variation. Specifications subject to change without notice. REV. 0 –2– AD9752 (T to T , AVDD = +5 V, DVDD = +5 V, I = 20 mA, Differential Transformer Coupled Output, MIN MAX OUTFS DYNAMIC SPECIFICATIONS 50 V Doubly Terminated, unless otherwise noted) Parameter Min Typ Max Units DYNAMIC PERFORMANCE ) 125 MSPS Maximum Output Update Rate (f CLOCK 1 Output Settling Time (t ) (to 0.1%) 35 ns ST Output Propagation Delay (t)1 ns PD Glitch Impulse 5 pV-s 1 Output Rise Time (10% to 90%) 2.5 ns 1 Output Fall Time (10% to 90%) 2.5 ns Output Noise (I = 20 mA) 50 pA/√Hz OUTFS Output Noise (I = 2 mA) 30 pA/√Hz OUTFS AC LINEARITY Spurious-Free Dynamic Range to Nyquist f = 25 MSPS; f = 1.00 MHz CLOCK OUT 0 dBFS Output T = +25°C 75 84 dBc A –6 dBFS Output 76 dBc –12 dBFS Output 81 dBc f = 50 MSPS; f = 1.00 MHz 81 dBc CLOCK OUT f = 50 MSPS; f = 2.51 MHz 81 dBc CLOCK OUT f = 50 MSPS; f = 5.02 MHz 76 dBc CLOCK OUT f = 50 MSPS; f = 14.02 MHz 62 dBc CLOCK OUT f = 50 MSPS; f = 20.2 MHz 60 dBc CLOCK OUT f = 100 MSPS; f = 2.5 MHz 78 dBc CLOCK OUT f = 100 MSPS; f = 5 MHz 76 dBc CLOCK OUT f = 100 MSPS; f = 20 MHz 63 dBc CLOCK OUT f = 100 MSPS; f = 40 MHz 55 dBc CLOCK OUT Spurious-Free Dynamic Range within a Window f = 25 MSPS; f = 1.00 MHz 84 93 dBc CLOCK OUT f = 50 MSPS; f = 5.02 MHz; 2 MHz Span 86 dBc CLOCK OUT f = 100 MSPS; f = 5.04 MHz; 4 MHz Span 86 dBc CLOCK OUT Total Harmonic Distortion f = 25 MSPS; f = 1.00 MHz CLOCK OUT T = +25°C –82 –74 dBc A f = 50 MHz; f = 2.00 MHz –76 dBc CLOCK OUT f = 100 MHz; f = 2.00 MHz –76 dBc CLOCK OUT Multitone Power Ratio (8 Tones at 110 kHz Spacing) f = 20 MSPS; f = 2.00 MHz to 2.99 MHz CLOCK OUT 0 dBFS Output 81 dBc –6 dBFS Output 81 dBc –12 dBFS Output 85 dBc –18 dBFS Output 86 dBc NOTES 1 Measured single ended into 50W load. Specifications subject to change without notice. REV. 0 –3– AD9752 DIGITAL SPECIFICATIONS (T to T , AVDD = +5 V, DVDD = +5 V, I = 20 mA, unless otherwise noted) MIN MAX OUTFS Parameter Min Typ Max Units DIGITAL INPUTS 1 Logic “1” Voltage @ DVDD = +5 V 3.5 5 V Logic “1” Voltage @ DVDD = +3 V 2.1 3 V 1 Logic “0” Voltage @ DVDD = +5 V 0 1.3 V Logic “0” Voltage @ DVDD = +3 V 0 0.9 V Logic “1” Current –10 +10mA Logic “0” Current –10 +10mA Input Capacitance 5 pF Input Setup Time (t ) 2.0 ns S Input Hold Time (t ) 1.5 ns H Latch Pulsewidth (t ) 3.5 ns LPW NOTES 1 When DVDD = +5 V and Logic 1 voltage »3.5 V and Logic 0 voltage »1.3 V. IVDD can increase by up to 10 mA, depending on f . CLOCK Specifications subject to change without notice. DB0–DB11 t t S H CLOCK t LPW t PD t ST IOUTA OR 0.1% IOUTB 0.1% Figure 1. Timing Diagram ABSOLUTE MAXIMUM RATINGS* ORDERING GUIDE With Temperature Package Package Parameter Respect to Min Max Units Model Range Description Options* AVDD ACOM –0.3 +6.5 V AD9752AR –40°C to +85°C 28-Lead 300 Mil SOIC R-28 DVDD DCOM –0.3 +6.5 V AD9752ARU –40°C to +85°C 28-Lead TSSOP RU-28 ACOM DCOM –0.3 +0.3 V AD9752-EB Evaluation Board AVDD DVDD –6.5 +6.5 V CLOCK, SLEEP DCOM –0.3 DVDD + 0.3 V *R = Small Outline IC; RU = Thin Shrink Small Outline Package. Digital Inputs DCOM –0.3 DVDD + 0.3 V THERMAL CHARACTERISTICS IOUTA, IOUTB ACOM –1.0 AVDD + 0.3 V Thermal Resistance ICOMP ACOM –0.3 AVDD + 0.3 V 28-Lead 300 Mil SOIC REFIO, FSADJ ACOM –0.3 AVDD + 0.3 V q = 71.4°C/W REFLO ACOM –0.3 +0.3 V JA q = 23°C/W Junction Temperature +150 °C JC 28-Lead TSSOP Storage Temperature –65 +150 °C q = 97.9°C/W Lead Temperature JA q = 14.0°C/W (10 sec) +300 °C JC *Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may effect device reliability. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD9752 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD ESD SENSITIVE DEVICE precautions are recommended to avoid performance degradation or loss of functionality. REV. 0 –4– AD9752 PIN CONFIGURATION (MSB) DB11 1 28 CLOCK DB10 2 27 DVDD DB9 3 26 DCOM DB8 4 25 NC DB7 5 24 AVDD AD9752 DB6 6 23 ICOMP TOP VIEW (Not to Scale) DB5 7 22 IOUTA DB4 8 21 IOUTB DB3 9 20 ACOM DB2 10 19 NC DB1 11 18 FS ADJ 12 DB0 17 REFIO 13 NC 16 REFLO NC 14 15 SLEEP NC = NO CONNECT PIN FUNCTION DESCRIPTIONS Pin No. Name Description 1 DB11 Most Significant Data Bit (MSB). 2–11 DB10–DB1 Data Bits 1–10. 12 DB0 Least Significant Data Bit (LSB). 13, 14, 19, 25 NC No Internal Connection. 15 SLEEP Power-Down Control Input. Active High. Contains active pull-down circuit, thus may be left unterminated if not used. 16 REFLO Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal reference. 17 REFIO Reference Input/Output. Serves as reference input when internal reference disabled (i.e., Tie REFLO to AVDD). Serves as 1.2 V reference output when internal reference activated (i.e., Tie REFLO to ACOM). Requires 0.1mF capacitor to ACOM when internal reference activated. 18 FS ADJ Full-Scale Current Output Adjust. 19 NC No Connect. 20 ACOM Analog Common. 21 IOUTB Complementary DAC Current Output. Full-scale current when all data bits are 0s. 22 IOUTA DAC Current Output. Full-scale current when all data bits are 1s. 23 ICOMP Internal Bias Node for Switch Driver Circuitry. Decouple to ACOM with 0.1 mF capacitor. 24 AVDD Analog Supply Voltage (+4.5 V to +5.5 V). 26 DCOM Digital Common. 27 DVDD Digital Supply Voltage (+2.7 V to +5.5 V). 28 CLOCK Clock Input. Data latched on positive edge of clock. REV. 0 –5– AD9752 DEFINITIONS OF SPECIFICATIONS Power Supply Rejection Linearity Error (Also Called Integral Nonlinearity or INL) The maximum change in the full-scale output as the supplies Linearity error is defined as the maximum deviation of the are varied from nominal to minimum and maximum specified actual analog output from the ideal output, determined by a voltages. straight line drawn from zero to full scale. Settling Time Differential Nonlinearity (or DNL) The time required for the output to reach and remain within a DNL is the measure of the variation in analog value, normalized specified error band about its final value, measured from the to full scale, associated with a 1 LSB change in digital input code. start of the output transition. Monotonicity Glitch Impulse A D/A converter is monotonic if the output either increases or Asymmetrical switching times in a DAC give rise to undesired remains constant as the digital input increases. output transients that are quantified by a glitch impulse. It is specified as the net area of the glitch in pV-s. Offset Error The deviation of the output current from the ideal of zero is Spurious-Free Dynamic Range called offset error. For IOUTA, 0 mA output is expected when The difference, in dB, between the rms amplitude of the output the inputs are all 0s. For IOUTB, 0 mA output is expected signal and the peak spurious signal over the specified bandwidth. when all inputs are set to 1s. Total Harmonic Distortion Gain Error THD is the ratio of the rms sum of the first six harmonic The difference between the actual and ideal output span. The components to the rms value of the measured input signal. It is actual span is determined by the output when all inputs are set expressed as a percentage or in decibels (dB). to 1s minus the output when all inputs are set to 0s. Multitone Power Ratio Output Compliance Range The spurious-free dynamic range for an output containing mul- The range of allowable voltage at the output of a current-output tiple carrier tones of equal amplitude. It is measured as the DAC. Operation beyond the maximum compliance limits may difference between the rms amplitude of a carrier tone to the cause either output stage saturation or breakdown resulting in peak spurious signal in the region of a removed tone. nonlinear performance. Temperature Drift Temperature drift is specified as the maximum change from the ambient (+25°C) value to the value at either T or T . For MIN MAX offset and gain drift, the drift is reported in ppm of full-scale range (FSR) per °C. For reference drift, the drift is reported in ppm per °C. +5V REFLO AVDD ACOM 150pF +1.20V REF AD9752 0.1mF REFIO PMOS 0.1mF ICOMP CURRENT SOURCE FS ADJ MINI-CIRCUITS ARRAY R SET T1-1T TO HP3589A 2kV +5V DVDD IOUTA SPECTRUM/ SEGMENTED SWITCHES LSB NETWORK 100V DCOM IOUTB FOR DB11–DB3 SWITCHES ANALYZER 50V INPUT CLOCK LATCHES DVDD 50V 20pF SLEEP DCOM 50V RETIMED 50V 20pF CLOCK DIGITAL OUTPUT* DATA * AWG2021 CLOCK RETIMED CLOCK SUCH THAT DIGITAL DATA OUTPUT TEKTRONIX LECROY 9210 TRANSITIONS ON FALLING EDGE AWG-2021 PULSE GENERATOR OF 50% DUTY CYCLE CLOCK. W/OPTION 4 Figure 2. Basic AC Characterization Test Setup REV. 0 –6– AD9752 Typical AC Characterization Curves @ +5 V Supplies (AVDD = +5 V, DVDD = +5 V, I = 20 mA, 50 V Doubly Terminated Load, Differential Output, T = +258C, SFDR up to Nyquist, unless otherwise noted) OUTFS A 90 90 90 50MSPS 25MSPS –12dBFS 80 80 80 0dBFS –6dBFS –6dBFS 70 70 70 125MSPS 65MSPS 0dBFS 60 60 60 –12dBFS 50 50 50 40 40 40 0 0 1 10 100 21 46 8 10 124 05 10 15 20 25 f – MHz f – MHz f – MHz OUT OUT OUT Figure 4. SFDR vs. f @ 25 MSPS Figure 3. SFDR vs. f @ 0 dBFS OUT Figure 5. SFDR vs. f @ 50 MSPS OUT OUT 90 90 90 10mA FS 80 80 –6dBFS –6dBFS 80 –12dBFS 20mA FS 70 70 0dBFS 5mA FS 70 0dBFS 60 60 –12dBFS 60 50 50 40 50 40 0 10 20 30 40 50 60 0 0 21 46 8 102 53 10 15 20 250 f – MHz OUT f – MHz f – MHz OUT OUT Figure 7. SFDR vs. f @ 125 MSPS Figure 8. SFDR vs. f and I Figure 6. SFDR vs. f @ 65 MSPS OUT OUT OUTFS OUT @ 25 MSPS and 0 dBFS 90 90 80 4.55MHz@50MSPS 10MHz@50MSPS 2.27MHz@25MSPS 80 80 20mA FS 5MHz@25MSPS 70 70 70 5.91MHz@65MSPS 5mA FS 60 60 10mA FS 60 13MHz@65MSPS 11.36MHz@125MSPS 50 50 25MHz@125MSPS 40 40 50 0 0 0 –30 –25 –20 –15 –10 –5 –30 –25 –20 –15 –10 –5 20 40 60 80 100 120 A – dBFS A – dBFS f – MSPS OUT OUT CLOCK Figure 9. Single-Tone SFDR vs. A Figure 10. Single-Tone SFDR vs. OUT Figure 11. SNR vs. f and I CLOCK OUTFS @ f = f /11 A @ f = f /5 OUT CLOCK OUT OUT CLOCK @ f = 2 MHz and 0 dBFS OUT REV. 0 –7– SFDR – dB SFDR – dB SFDR – dBc SFDR – dB SFDR – dB SFDR – dB SFDR – dBc SFDR – dBc SNR – dB AD9752 0.1 90 0.7 0.6 0.0 0.5 f = 4MHz OUT 80 0.4 –0.1 0.3 f = 10MHz OUT 0.2 –0.2 70 0.1 0.0 –0.3 f = 29MHz OUT –0.1 60 –0.2 –0.4 f = 40MHz OUT –0.3 –0.5 50 –0.4 0 0 1000 2000 3000 4000 –55 –30 –5 20 45 70 95 1000 2000 3000 4000 CODE TEMPERATURE – 8C CODE Figure 13. Typical DNL Figure 14. SFDR vs. Temperature @ Figure 12. Typical INL 125 MSPS, 0 dBFS 0 0 f = 125MSPS CLK f = 65MSPS CLK –10 –10 f = 6.25MHz f = 13.5MHz OUT1 OUT1 f = 6.75MHz –20 OUT2 –20 f = 14.5MHz OUT2 f = 7.25MHz OUT3 A = 0dBFS OUT –30 f = 7.75MHz –30 OUT4 SFDR = 68.4dBc SFDR = 69dBc –40 –40 AMPLITUDE = 0dBFS –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 –100 0 5.0 10.0 15.0 20.0 25.0 30.0 0 10 20 30 40 50 60 f – MHz OUT f – MHz OUT Figure 16. Four-Tone SFDR Figure 15. Dual-Tone SFDR REV. 0 –8– SIGNAL AMPLITUDE – dBm ERROR – LSB ERROR – LSB SIGNAL AMPLITUDE – dBm SFDR – dBc AD9752 +5V REFLO AVDD ACOM 150pF +1.20V REF AD9752 V REFIO REFIO PMOS 0.1mF ICOMP I CURRENT SOURCE REF FS ADJ 0.1mF ARRAY R V = V – V DIFF OUTA OUTB SET 2kV DVDD +5V I IOUTA OUTA V OUTA SEGMENTED SWITCHES LSB I DCOM OUTB IOUTB FOR DB11–DB3 SWITCHES V OUTB R LOAD CLOCK 50V R LOAD CLOCK LATCHES 50V SLEEP DIGITAL DATA INPUTS (DB11–DB0) Figure 17. Functional Block Diagram IOUTB = (4095 – DAC CODE)/4096 · I (2) FUNCTIONAL DESCRIPTION OUTFS Figure 17 shows a simplified block diagram of the AD9752. where DAC CODE = 0 to 4095 (i.e., Decimal Representation). The AD9752 consists of a large PMOS current source array that As mentioned previously, I is a function of the reference OUTFS is capable of providing up to 20 mA of total current. The array current I , which is nominally set by a reference voltage REF is divided into 31 equal currents that make up the five most V and external resistor R . It can be expressed as: REFIO SET significant bits (MSBs). The next four bits or middle bits consist of 15 equal current sources whose value is 1/16th of an MSB I = 32 · I (3) OUTFS REF current source. The remaining LSBs are binary weighted frac- where I = V /R (4) REF REFIO SET tions of the middle-bits current sources. Implementing the The two current outputs will typically drive a resistive load middle and lower bits with current sources, instead of an R-2R directly or via a transformer. If dc coupling is required, IOUTA ladder, enhances its dynamic performance for multitone or low and IOUTB should be directly connected to matching resistive amplitude signals and helps maintain the DAC’s high output loads, R , which are tied to analog common, ACOM. Note, LOAD impedance (i.e., >100 kW). R may represent the equivalent load resistance seen by LOAD All of these current sources are switched to one or the other of IOUTA or IOUTB as would be the case in a doubly terminated the two output nodes (i.e., IOUTA or IOUTB) via PMOS 50W or 75W cable. The single-ended voltage output appearing differential current switches. The switches are based on a new at the IOUTA and IOUTB nodes is simply : architecture that drastically improves distortion performance. V = IOUTA · R (5) OUTA LOAD This new switch architecture reduces various timing errors and provides matching complementary drive signals to the inputs of V = IOUTB · R (6) OUTB LOAD the differential current switches. Note the full-scale value of V and V should not exceed OUTA OUTB The analog and digital sections of the AD9752 have separate the specified output compliance range to maintain specified power supply inputs (i.e., AVDD and DVDD). The digital distortion and linearity performance. section, which is capable of operating up to a 125 MSPS clock The differential voltage, V , appearing across IOUTA and DIFF rate and over a +2.7 V to +5.5 V operating range, consists of IOUTB is: edge-triggered latches and segment decoding logic circuitry. V = (IOUTA – IOUTB) · R (7) DIFF LOAD The analog section, which can operate over a +4.5 V to +5.5 V range, includes the PMOS current sources, the associated differ- Substituting the values of I , I , and I ; V can be OUTA OUTB REF DIFF ential switches, a 1.20 V bandgap voltage reference and a refer- expressed as: ence control amplifier. V = {(2 DAC CODE – 4095)/4096} ·DIFF The full-scale output current is regulated by the reference con- (32 R /R ) · V (8) LOAD SET REFIO trol amplifier and can be set from 2 mA to 20 mA via an exter- These last two equations highlight some of the advantages of nal resistor, R . The external resistor, in combination with SET operating the AD9752 differentially. First, the differential op- both the reference control amplifier and voltage reference V , REFIO eration will help cancel common-mode error sources associated sets the reference current I , which is mirrored over to the REF with I and I such as noise, distortion and dc offsets. OUTA OUTB segmented current sources with the proper scaling factor. The Second, the differential code dependent current and subsequent full-scale current, I , is thirty-two times the value of I . OUTFS REF voltage, V , is twice the value of the single-ended voltage DIFF output (i.e., V or V ), thus providing twice the signal OUTA OUTB DAC TRANSFER FUNCTION power to the load. The AD9752 provides complementary current outputs, IOUTA and IOUTB. IOUTA will provide a near full-scale current output, Note, the gain drift temperature performance for a single-ended I , when all bits are high (i.e., DAC CODE = 4095) while OUTFS (V and V ) or differential output (V ) of the AD9752 OUTA OUTB DIFF IOUTB, the complementary output, provides no current. The can be enhanced by selecting temperature tracking resistors for current output appearing at IOUTA and IOUTB is a function R and R due to their ratiometric relationship as shown LOAD SET of both the input code and I and can be expressed as: OUTFS in Equation 8. IOUTA = (DAC CODE/4096) · I (1) OUTFS REV. 0 –9– AD9752 REFERENCE OPERATION REFERENCE CONTROL AMPLIFIER The AD9752 contains an internal 1.20 V bandgap reference The AD9752 also contains an internal control amplifier that is that can easily be disabled and overridden by an external refer- used to regulate the DAC’s full-scale output current, I . OUTFS ence. REFIO serves as either an input or output depending on The control amplifier is configured as a V-I converter as shown whether the internal or an external reference is selected. If in Figure 19, such that its current output, I , is determined by REF REFLO is tied to ACOM, as shown in Figure 18, the internal the ratio of the V and an external resistor, R , as stated REFIO SET reference is activated and REFIO provides a 1.20 V output. In in Equation 4. I is copied over to the segmented current REF this case, the internal reference must be compensated externally sources with the proper scaling factor to set I as stated in OUTFS with a ceramic chip capacitor of 0.1mF or greater from REFIO Equation 3. to REFLO. Also, REFIO should be buffered with an external The control amplifier allows a wide (10:1) adjustment span of amplifier having an input bias current less than 100 nA if any I over a 2 mA to 20 mA range by setting IREF between OUTFS additional loading is required. 62.5mA and 625mA. The wide adjustment span of I OUTFS provides several application benefits. The first benefit relates +5V directly to the power dissipation of the AD9752, which is OPTIONAL EXTERNAL proportional to I (refer to the Power Dissipation section). OUTFS REF BUFFER REFLO AVDD 150pF The second benefit relates to the 20 dB adjustment, which is +1.2V REF useful for system gain control purposes. REFIO The small signal bandwidth of the reference control amplifier is CURRENT ADDITIONAL FS ADJ SOURCE 0.1mF approximately 0.5 MHz. The output of the control amplifier is LOAD ARRAY internally compensated via a 150 pF capacitor that limits the 2kV AD9752 control amplifier small-signal bandwidth and reduces its output impedance. Since the –3 dB bandwidth corresponds to Figure 18. Internal Reference Configuration the dominant pole, and hence the time constant, the settling time of the control amplifier to a stepped reference input re- The internal reference can be disabled by connecting REFLO to sponse can be approximated. In this case, the time constant can AVDD. In this case, an external reference may then be applied be approximated to be 320 ns. to REFIO as shown in Figure 19. The external reference may provide either a fixed reference voltage to enhance accuracy and There are two methods in which I can be varied for a fixed REF drift performance or a varying reference voltage for gain control. R . The first method is suitable for a single-supply system in SET Note that the 0.1mF compensation capacitor is not required which the internal reference is disabled, and the common-mode since the internal reference is disabled, and the high input im- voltage of REFIO is varied over its compliance range of 1.25 V pedance (i.e., 1 MW) of REFIO minimizes any loading of the to 0.10 V. REFIO can be driven by a single-supply amplifier or external reference. DAC, thus allowing I to be varied for a fixed R . Since the REF SET AVDD input impedance of REFIO is approximately 1 MW, a simple, low cost R-2R ladder DAC configured in the voltage mode topology may be used to control the gain. This circuit is shown in Figure 20 using the AD7524 and an external 1.2 V reference, REFLO 150pF AVDD AVDD the AD1580. +1.2V REF V REFIO REFIO EXTERNAL CURRENT REF SOURCE FS ADJ ARRAY R I = SET REF V /R REFERENCE REFIO SET AD9752 CONTROL AMPLIFIER Figure 19. External Reference Configuration AVDD AVDD REFLO AVDD 150pF R V +1.2V REF FB DD 1.2V OUT1 0.1V TO 1.2V REFIO AD7524 V REF CURRENT SOURCE OUT2 FS ADJ AD1580 ARRAY AGND R SET I = REF AD9752 V /R REF SET DB7–DB0 Figure 20. Single-Supply Gain Control Circuit REV. 0 –10– AD9752 The second method may be used in a dual-supply system in IOUTA and IOUTB also have a negative and positive voltage which the common-mode voltage of REFIO is fixed and I is compliance range. The negative output compliance range of REF varied by an external voltage, V , applied to R via an ampli- –1.0 V is set by the breakdown limits of the CMOS process. GC SET fier. An example of this method is shown in Figure 21, in which Operation beyond this maximum limit may result in a break- the internal reference is used to set the common-mode voltage down of the output stage and affect the reliability of the AD9752. of the control amplifier to 1.20 V. The external voltage, V , is The positive output compliance range is slightly dependent on GC referenced to ACOM and should not exceed 1.2 V. The value the full-scale output current, I . It degrades slightly from its OUTFS of R is such that I and I do not exceed 62.5mA nominal 1.25 V for an I = 20 mA to 1.00 V for an I = SET REFMAX REFMIN OUTFS OUTFS and 625mA, respectively. The associated equations in Figure 21 2 mA. Operation beyond the positive compliance range will can be used to determine the value of R . induce clipping of the output signal which severely degrades SET the AD9752’s linearity and distortion performance. AVDD For applications requiring the optimum dc linearity, IOUTA and/or IOUTB should be maintained at a virtual ground via an REFLO AVDD 150pF I-V op amp configuration. Maintaining IOUTA and/or IOUTB +1.2V REF at a virtual ground keeps the output impedance of the AD9752 REFIO CURRENT fixed, significantly reducing its effect on linearity. However, SOURCE FS ADJ 1mF ARRAY it does not necessarily lead to the optimum distortion perfor- R SET I REF mance due to limitations of the I-V op amp. Note that the AD9752 INL/DNL specifications for the AD9752 are measured in I = (1.2–V )/R REF GC SET this manner using IOUTA. In addition, these dc linearity V GC WITH V < V AND 62.5mA # I # 625A GC REFIO REF specifications remain virtually unaffected over the specified Figure 21. Dual-Supply Gain Control Circuit power supply range of 4.5 V to 5.5 V. Operating the AD9752 with reduced voltage output swings at ANALOG OUTPUTS IOUTA and IOUTB in a differential or single-ended output The AD9752 produces two complementary current outputs, configuration reduces the signal dependency of its output IOUTA and IOUTB, which may be configured for single-end impedance thus enhancing distortion performance. Although or differential operation. IOUTA and IOUTB can be converted the voltage compliance range of IOUTA and IOUTB extends into complementary single-ended voltage outputs, V and OUTA from –1.0 V to +1.25 V, optimum distortion performance is V , via a load resistor, R , as described in the DAC OUTB LOAD achieved when the maximum full-scale signal at IOUTA and Transfer Function section by Equations 5 through 8. The IOUTB does not exceed approximately 0.5 V. A properly se- differential voltage, V , existing between V and V DIFF OUTA OUTB lected transformer with a grounded center-tap will allow the can also be converted to a single-ended voltage via a transformer AD9752 to provide the required power and voltage levels to or differential amplifier configuration. different loads while maintaining reduced voltage swings at Figure 22 shows the equivalent analog output circuit of the IOUTA and IOUTB. DC-coupled applications requiring a AD9752 consisting of a parallel combination of PMOS differen- differential or single-ended output configuration should size tial current switches associated with each segmented current R accordingly. Refer to Applying the AD9752 section for LOAD source. The output impedance of IOUTA and IOUTB is deter- examples of various output configurations. mined by the equivalent parallel combination of the PMOS The most significant improvement in the AD9752’s distortion switches and is typically 100 kW in parallel with 5 pF. Due to and noise performance is realized using a differential output the nature of a PMOS device, the output impedance is also configuration. The common-mode error sources of both slightly dependent on the output voltage (i.e., V and V ) OUTA OUTB IOUTA and IOUTB can be substantially reduced by the and, to a lesser extent, the analog supply voltage, AVDD, and common-mode rejection of a transformer or differential am- full-scale current, I . Although the output impedance’s OUTFS plifier. These common-mode error sources include even- signal dependency can be a source of dc nonlinearity and ac linear- order distortion products and noise. The enhancement in ity (i.e., distortion), its effects can be limited if certain precau- distortion performance becomes more significant as the recon- tions are noted. structed waveform’s frequency content increases and/or its amplitude decreases. AVDD The distortion and noise performance of the AD9752 is also slightly dependent on the analog and digital supply as well as the full-scale current setting, I . Operating the analog supply at OUTFS 5.0 V ensures maximum headroom for its internal PMOS current sources and differential switches leading to improved distortion performance. Although I can be set between 2 mA and OUTFS IOUTA IOUTB 20 mA, selecting an I of 20 mA will provide the best dis- R R OUTFS LOAD LOAD tortion and noise performance also shown in Figure 8. The noise performance of the AD9752 is affected by the digital sup- Figure 22. Equivalent Analog Output ply (DVDD), output frequency, and increases with increasing clock rate as shown in Figure 11. Operating the AD9752 with low voltage logic levels between 3 V and 3.3 V will slightly re- duce the amount of on-chip digital noise. REV. 0 –11– AD9752 In summary, the AD9752 achieves the optimum distortion and data interface circuitry should be specified to meet the mini- noise performance under the following conditions: mum setup and hold times of the AD9752 as well as its re- quired min/max input logic level thresholds. Typically, the (1) Differential Operation. selection of the slowest logic family that satisfies the above con- (2) Positive voltage swing at IOUTA and IOUTB limited to ditions will result in the lowest data feedthrough and noise. +0.5 V. Digital signal paths should be kept short and run lengths (3) I set to 20 mA. OUTFS matched to avoid propagation delay mismatch. The insertion of a low value resistor network (i.e., 20W to 100W) between the (4) Analog Supply (AVDD) set at 5.0 V. AD9752 digital inputs and driver outputs may be helpful in reduc- (5) Digital Supply (DVDD) set at 3.0 V to 3.3 V with appro- ing any overshooting and ringing at the digital inputs that con- priate logic levels. tribute to data feedthrough. For longer run lengths and high data Note that the ac performance of the AD9752 is characterized update rates, strip line techniques with proper termination resis- under the above mentioned operating conditions. tors should be considered to maintain “clean” digital inputs. Also, operating the AD9752 with reduced logic swings and a corre- DIGITAL INPUTS sponding digital supply (DVDD) will also reduce data feedthrough. The AD9752’s digital input consists of 12 data input pins and a The external clock driver circuitry should provide the AD9752 clock input pin. The 12-bit parallel data inputs follow standard with a low jitter clock input meeting the min/max logic levels positive binary coding where DB11 is the most significant bit while providing fast edges. Fast clock edges will help minimize (MSB) and DB0 is the least significant bit (LSB). IOUTA any jitter that will manifest itself as phase noise on a recon- produces a full-scale output current when all data bits are at structed waveform. Thus, the clock input should be driven by Logic 1. IOUTB produces a complementary output with the the fastest logic family suitable for the application. full-scale current split between the two outputs as a function of Note, the clock input could also be driven via a sine wave, which is the input code. centered around the digital threshold (i.e., DVDD/2), and meets The digital interface is implemented using an edge-triggered the min/max logic threshold. This will typically result in a slight master slave latch. The DAC output is updated following the degradation in the phase noise, which becomes more noticeable rising edge of the clock as shown in Figure 1 and is designed to at higher sampling rates and output frequencies. Also, at higher support a clock rate as high as 125 MSPS. The clock can be sampling rates, the 20% tolerance of the digital logic threshold operated at any duty cycle that meets the specified latch pulse- should be considered since it will affect the effective clock duty width. The setup and hold times can also be varied within the cycle and subsequently cut into the required data setup and clock cycle as long as the specified minimum times are met; hold times. although the location of these transition edges may affect digital feedthrough and distortion performance. Best performance is INPUT CLOCK/DATA TIMING RELATIONSHIP typically achieved when the input data transitions on the falling edge SNR in a DAC is dependent on the relationship between the of a 50% duty cycle clock. position of the clock edges and the point in time at which the input data changes. The AD9752 is positive edge triggered, and The digital inputs are CMOS compatible with logic thresholds, so exhibits SNR sensitivity when the data transition is close to V set to approximately half the digital positive supply THRESHOLD this edge. In general, the goal when applying the AD9752 is to (DVDD) or make the data transitions shortly after the positive clock edge. V = DVDD/2 (–20%) THRESHOLD This becomes more important as the sample rate increases. Figure The internal digital circuitry of the AD9752 is capable of operating 24 shows the relationship of SNR to clock placement with dif- over a digital supply range of 2.7 V to 5.5 V. As a result, the ferent sample rates and different frequencies out. Note that at digital inputs can also accommodate TTL levels when DVDD is the lower sample rates, much more tolerance is allowed in clock set to accommodate the maximum high level voltage of the TTL placement, while at higher rates, much more care must be taken. drivers V . A DVDD of 3 V to 3.3 V will typically ensure OH(MAX) proper compatibility with most TTL logic families. Figure 23 68 shows the equivalent digital input circuit for the data and clock inputs. The sleep mode input is similar with the exception that 64 F = 65MSPS S it contains an active pull-down circuit, thus ensuring that the 60 AD9752 remains enabled if this input is left disconnected. 56 DVDD 52 F = 125MSPS S DIGITAL 48 INPUT 44 40 –8 –6 –4 –2 0 2 4 6 8 10 Figure 23. Equivalent Digital Input TIME OF DATA CHANGE RELATIVE TO RISING CLOCK EDGE – ns Since the AD9752 is capable of being updated up to 125 MSPS, the quality of the clock and data input signals are important in Figure 24. SNR vs. Clock Placement @ f = 10 MHz OUT achieving the optimum performance. The drivers of the digital REV. 0 –12– SNR – dB AD9752 8 SLEEP MODE OPERATION 125MSPS The AD9752 has a power-down function which turns off the output current and reduces the supply current to less than 8.5 mA over the specified supply range of 2.7 V to 5.5 V and 6 100MSPS temperature range. This mode can be activated by applying a logic level “1” to the SLEEP pin. This digital input also con- tains an active pull-down circuit that ensures the AD9752 re- 4 mains enabled if this input is left disconnected. The AD9752 50MSPS takes less than 50 ns to power down and approximately 5 ms to power back up. 2 25MSPS POWER DISSIPATION The power dissipation, P , of the AD9752 is dependent on 5MSPS D 0 several factors which include: (1) AVDD and DVDD, the 0.01 0.1 1 RATIO (f /f ) CLOCK OUT power supply voltages; (2) I , the full-scale current output; OUTFS (3) f , the update rate; (4) and the reconstructed digital CLOCK Figure 27. I vs. Ratio @ DVDD = 3 V DVDD input waveform. The power dissipation is directly proportional to the analog supply current, I , and the digital supply cur- AVDD APPLYING THE AD9752 rent, I . I is directly proportional to I as shown in DVDD AVDD OUTFS OUTPUT CONFIGURATIONS Figure 25 and is insensitive to f . CLOCK The following sections illustrate some typical output configura- tions for the AD9752. Unless otherwise noted, it is assumed Conversely, I is dependent on both the digital input wave- DVDD that I is set to a nominal 20 mA. For applications requir- form, f , and digital supply DVDD. Figures 26 and 27 OUTFS CLOCK ing the optimum dynamic performance, a differential output show I as a function of full-scale sine wave output ratios DVDD configuration is suggested. A differential output configuration (f /f ) for various update rates with DVDD = 5 V and OUT CLOCK may consist of either an RF transformer or a differential op amp DVDD = 3 V, respectively. Note, how I is reduced by more DVDD configuration. The transformer configuration provides the opti- than a factor of 2 when DVDD is reduced from 5 V to 3 V. mum high frequency performance and is recommended for any 35 application allowing for ac coupling. The differential op amp configuration is suitable for applications requiring dc coupling, a bipolar output, signal gain and/or level shifting. 30 A single-ended output is suitable for applications requiring a 25 unipolar voltage output. A positive unipolar output voltage will result if IOUTA and/or IOUTB is connected to an appropri- 20 ately sized load resistor, R , referred to ACOM. This con- LOAD figuration may be more suitable for a single-supply system requiring a dc coupled, ground referred output voltage. Alterna- 15 tively, an amplifier could be configured as an I-V converter thus converting IOUTA or IOUTB into a negative unipolar voltage. 10 This configuration provides the best dc linearity since IOUTA or IOUTB is maintained at a virtual ground. Note, IOUTA 5 22 4 6 8 10 12 1416180 provides slightly better performance than IOUTB. I – mA OUTFS Figure 25. I vs. I DIFFERENTIAL COUPLING USING A TRANSFORMER AVDD OUTFS An RF transformer can be used to perform a differential-to- 18 single-ended signal conversion as shown in Figure 28. A 125MSPS differentially coupled transformer output provides the optimum 16 distortion performance for output signals whose spectral content 14 lies within the transformer’s passband. An RF transformer such 100MSPS 12 as the Mini-Circuits T1-1T provides excellent rejection of common-mode distortion (i.e., even-order harmonics) and noise 10 over a wide frequency range. It also provides electrical isolation 8 and the ability to deliver twice the power to the load. Trans- 50MSPS formers with different impedance ratios may also be used for 6 impedance matching purposes. Note that the transformer 4 provides ac coupling only. 25MSPS 2 5MSPS 0 0.01 0.1 1 RATIO (f /f ) CLOCK OUT Figure 26. I vs. Ratio @ DVDD = 5 V DVDD REV. 0 –13– I – mA I – mA AVDD DVDD I – mA DVDD AD9752 MINI-CIRCUITS 500V T1-1T IOUTA AD9752 225V IOUTA R AD9752 LOAD AD8041 225V IOUTB IOUTB C OPTIONAL R OPT DIFF 1kV AVDD 25V 25V 1kV Figure 28. Differential Output Using a Transformer The center tap on the primary side of the transformer must be connected to ACOM to provide the necessary dc current path Figure 30. Single-Supply DC Differential Coupled Circuit for both IOUTA and IOUTB. The complementary voltages appearing at IOUTA and IOUTB (i.e., V and V ) SINGLE-ENDED UNBUFFERED VOLTAGE OUTPUT OUTA OUTB swing symmetrically around ACOM and should be maintained Figure 31 shows the AD9752 configured to provide a unipolar with the specified output compliance range of the AD9752. A output range of approximately 0 V to +0.5 V for a doubly termi- differential resistor, R , may be inserted in applications in nated 50W cable since the nominal full-scale current, I , of DIFF OUTFS which the output of the transformer is connected to the load, 20 mA flows through the equivalent R of 25W. In this LOAD R , via a passive reconstruction filter or cable. R is deter- case, R represents the equivalent load resistance seen by LOAD DIFF LOAD mined by the transformer’s impedance ratio and provides the IOUTA or IOUTB. The unused output (IOUTA or IOUTB) proper source termination which results in a low VSWR. Note can be connected to ACOM directly or via a matching R . LOAD that approximately half the signal power will be dissipated across Different values of I and R can be selected as long as OUTFS LOAD R . the positive compliance range is adhered to. One additional DIFF consideration in this mode is the integral nonlinearity (INL) as DIFFERENTIAL USING AN OP AMP discussed in the ANALOG OUTPUT section of this data sheet. An op amp can also be used to perform a differential to single- For optimum INL performance, the single-ended, buffered ended conversion as shown in Figure 29. The AD9752 is con- voltage output configuration is suggested. figured with two equal load resistors, R , of 25 W. The LOAD differential voltage developed across IOUTA and IOUTB is AD9752 I = 20mA OUTFS converted to a single-ended signal via the differential op amp V = 0 TO +0.5V OUTA IOUTA configuration. An optional capacitor can be installed across 50V 50V IOUTA and IOUTB forming a real pole in a low-pass filter. IOUTB The addition of this capacitor also enhances the op amps distor- 25V tion performance by preventing the DACs high slewing output from overloading the op amp’s input. Figure 31. 0 V to +0.5 V Unbuffered Voltage Output 500V AD9752 SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT 225V IOUTA CONFIGURATION AD8055 Figure 32 shows a buffered single-ended output configuration in 225V IOUTB which the op amp U1 performs an I-V conversion on the AD9752 C OPT output current. U1 maintains IOUTA (or IOUTB) at a virtual 500V ground, thus minimizing the nonlinear output impedance effect 25V 25V on the DAC’s INL performance as discussed in the ANALOG OUTPUT section. Although this single-ended configuration Figure 29. DC Differential Coupling Using an Op Amp typically provides the best dc linearity performance, its ac distor- tion performance at higher DAC update rates may be limited by The common-mode rejection of this configuration is typically U1’s slewing capabilities. U1 provides a negative unipolar out- determined by the resistor matching. In this circuit, the differ- put voltage and its full-scale output voltage is simply the ential op amp circuit is configured to provide some additional product of R and I . The full-scale output should be set FB OUTFS signal gain. The op amp must operate off of a dual supply since within U1’s voltage output swing capabilities by scaling I OUTFS its output is approximately –1.0 V. A high speed amplifier such and/or R . An improvement in ac distortion performance may FB as the AD8055 or AD9632 capable of preserving the differential result with a reduced I since the signal current U1 will be OUTFS performance of the AD9752 while meeting other system level required to sink will be subsequently reduced. objectives (i.e., cost, power) should be selected. The op amps differential gain, its gain setting resistor values, and full-scale output swing capabilities should all be considered when opti- mizing this circuit. The differential circuit shown in Figure 30 provides the neces- sary level-shifting required in a single supply system. In this case, AVDD which is the positive analog supply for both the AD9752 and the op amp is also used to level-shift the differ- ential output of the AD9752 to midsupply (i.e., AVDD/2). The AD8041 is a suitable op amp for this application. REV. 0 –14– AD9752 C OPT frequency power supply noise to higher frequencies. Worst case PSRR for either one of the differential DAC outputs will occur R FB when the full-scale current is directed towards that output. As a 200V result, the PSRR measurement in Figure 33 represents a worst I = 10mA OUTFS AD9752 case condition in which the digital inputs remain static and the IOUTA full scale output current of 20 mA is directed to the DAC out- U1 V = I 3 R OUT OUTFS FB put being measured. IOUTB 200V An example serves to illustrate the effect of supply noise on the analog supply. Suppose a switching regulator with a switching frequency of 250 kHz produces 10 mV rms of noise and for Figure 32. Unipolar Buffered Voltage Output simplicity sake (i.e., ignore harmonics), all of this noise is con- centrated at 250 kHz. To calculate how much of this undesired POWER AND GROUNDING CONSIDERATIONS, POWER noise will appear as current noise super imposed on the DAC’s SUPPLY REJECTION full-scale current, I , one must determine the PSRR in dB OUTFS Many applications seek high speed and high performance under using Figure 33 at 250 kHz. To calculate the PSRR for a given less than ideal operating conditions. In these circuits, the imple- R , such that the units of PSRR are converted from A/V to LOAD mentation and construction of the printed circuit board design V/V, adjust the curve in Figure 33 by the scaling factor 20 · Log is as important as the circuit design. Proper RF techniques must (R ). For instance, if R is 50 W, the PSRR is reduced LOAD LOAD be used for device selection, placement and routing as well as by 34 dB (i.e., PSRR of the DAC at 1 MHz which is 74 dB in power supply bypassing and grounding to ensure optimum Figure 33 becomes 40 dB V /V ). OUT IN performance. Figures 42-47 illustrate the recommended printed Proper grounding and decoupling should be a primary objective circuit board ground, power and signal plane layouts which are in any high speed, high resolution system. The AD9752 features implemented on the AD9752 evaluation board. separate analog and digital supply and ground pins to optimize One factor that can measurably affect system performance is the the management of analog and digital ground currents in a ability of the DAC output to reject dc variations or ac noise system. In general, AVDD, the analog supply, should be de- superimposed on the analog or digital dc power distribution coupled to ACOM, the analog common, as close to the chip as (i.e., AVDD, DVDD). This is referred to as Power Supply physically possible. Similarly, DVDD, the digital supply, should Rejection Ratio (PSRR). For dc variations of the power supply, be decoupled to DCOM as close as physically as possible. the resulting performance of the DAC directly corresponds to a For those applications that require a single +5 V or +3 V supply gain error associated with the DAC’s full-scale current, I . OUTFS for both the analog and digital supply, a clean analog supply AC noise on the dc supplies is common in applications where may be generated using the circuit shown in Figure 34. The the power distribution is generated by a switching power supply. circuit consists of a differential LC filter with separate power Typically, switching power supply noise will occur over the supply and return lines. Lower noise can be attained using low spectrum from tens of kHz to several MHz. PSRR vs. frequency ESR type electrolytic and tantalum capacitors. of the AD9752 AVDD supply, over this frequency range, is given in Figure 33. FERRITE BEADS 90 AVDD TTL/CMOS LOGIC 100mF 10-22mF 0.1mF CIRCUITS ELECT. TANT. CER. ACOM 80 +5V OR +3V POWER SUPPLY Figure 34. Differential LC Filter for Single +5 V or +3 V 70 Applications Maintaining low noise on power supplies and ground is critical to obtaining optimum results from the AD9752. If properly implemented, ground planes can perform a host of functions on 60 high speed circuit boards: bypassing, shielding, current trans- 0.26 0.5 0.75 1.0 FREQUENCY – MHz port, etc. In mixed signal design, the analog and digital portions of the board should be distinct from each other, with the analog Figure 33. Power Supply Rejection Ratio of AD9752 ground plane confined to the areas covering the analog signal Note that the units in Figure 33 are given in units of (amps out)/ traces, and the digital ground plane confined to areas covering (volts in). Noise on the analog power supply has the effect of the digital interconnects. modulating the internal switches, and therefore the output All analog ground pins of the DAC, reference and other analog current. The voltage noise on the dc power, therefore, will be components should be tied directly to the analog ground plane. added in a nonlinear manner to the desired I . Due to the OUT The two ground planes should be connected by a path 1/8 relative different sizes of these switches, PSRR is very code depen- to 1/4 inch wide underneath or within 1/2 inch of the DAC to dent. This can produce a mixing effect which can modulate low REV. 0 –15– PSRR – dB AD9752 APPLICATIONS maintain optimum performance. Care should be taken to ensure VDSL Applications Using the AD9752 that the ground plane is uninterrupted over crucial signal paths. Very High Frequency Digital Subscriber Line (VDSL) technol- On the digital side, this includes the digital input lines running ogy is growing rapidly in applications requiring data transfer to the DAC as well as any clock signals. On the analog side, this over relatively short distances. By using QAM modulation and includes the DAC output signal, reference signal and the supply transmitting the data in multiple discrete tones, high data rates feeders. can be achieved. The use of wide runs or planes in the routing of power lines is As with other multitone applications, each VDSL tone is ca- also recommended. This serves the dual role of providing a low pable of transmitting a given number of bits, depending on the series impedance power supply to the part, as well as providing signal-to-noise ratio (SNR) in a narrow band around that tone. some “free” capacitive decoupling to the appropriate ground The tones are evenly spaced over the range of several kHz to plane. It is essential that care be taken in the layout of signal and 10 MHz. At the high frequency end of this range, performance power ground interconnects to avoid inducing extraneous volt- is generally limited by cable characteristics and environmental age drops in the signal ground paths. It is recommended that all factors, such as external interferers. Performance at the lower connections be short, direct and as physically close to the pack- frequencies is much more dependent on the performance of the age as possible in order to minimize the sharing of conduction components in the signal chain. In addition to in-band noise, paths between different currents. When runs exceed an inch in intermodulation from other tones can also potentially interfere length, strip line techniques with proper termination resistor with the recovery of data for a given tone. The two graphs in should be considered. The necessity and value of this resistor Figure 35 represent a 500 tone missing bin test vector, with will be dependent upon the logic family used. frequencies evenly spaced from 400 Hz to 10 MHz. This test is For a more detailed discussion of the implementation and very commonly done to determine if distortion will limit the construction of high speed, mixed signal printed circuit boards, number of bits which can be transmitted in a tone. The test refer to Analog Devices’ application notes AN-280 and vector has a series of missing tones around 750 kHz, which is AN-333. represented in Figure 35a and a series of missing tones around 5 MHz which is represented in Figure 35b. In both cases, the –30 spurious free range between the transmitted tones and the empty bins is greater than 60 dB. –40 Using the AD9752 for Quadrature Amplitude Modulation –50 (QAM) QAM is one of the most widely used digital modulation –60 schemes in digital communication systems. This modulation technique can be found in FDM as well as spreadspectrum (i.e., –70 CDMA) based systems. A QAM signal is a carrier frequency that is modulated in both amplitude (i.e., AM modulation) and –80 phase (i.e., PM modulation). It can be generated by indepen- dently modulating two carriers of identical frequency but with a –90 90° phase difference. This results in an in-phase (I) carrier com- ponent and a quadrature (Q) carrier component at a 90° phase –100 600k 800k 1M shift with respect to the I component. The I and Q components FREQUENCY – Hz are then summed to provide a QAM signal at the specified car- Figure 35a. Notch in Missing Bin at 750 kHz is Down rier frequency. >60 dB. (Peak Amplitude + 0 dBm). A common and traditional implementation of a QAM modu- lator is shown in Figure 36. The modulation is performed in the –30 analog domain in which two DACs are used to generate the baseband I and Q components, respectively. Each component is –40 then typically applied to a Nyquist filter before being applied to –50 a quadrature mixer. The matching Nyquist filters shape and limit each component’s spectral envelope while minimizing –60 intersymbol interference. The DAC is typically updated at the –70 QAM symbol rate or possibly a multiple of it if an interpolating filter precedes the DAC. The use of an interpolating filter typi- –80 cally eases the implementation and complexity of the analog filter, which can be a significant contributor to mismatches in –90 gain and phase between the two baseband channels. A quadra- –100 ture mixer modulates the I and Q components with in-phase and quadrature phase carrier frequency and then sums the two –110 4.85 5 5.15 outputs to provide the QAM signal. FREQUENCY – MHz Figure 35b. Notch in Missing Bin at 5 MHz is Down >60 dB. (Peak Amplitude + 0 dBm). REV. 0 –16– AMPLITUDE – dBm AMPLITUDE – dBm AD9752 subsystem. The AD6122 has functions, such as external gain 12 AD9752 control and low distortion characteristics, needed for the supe- DSP rior Adjacent Channel Power (ACP) requirements of W-CDMA. 0 CARRIER TO OR S FREQUENCY MIXER 90 ASIC CDMA 12 Carrier Division Multiple Access, or CDMA, is an air transmit/ AD9752 receive scheme where the signal in the transmit path is modu- NYQUIST QUADRATURE lated with a pseudorandom digital code (sometimes referred to FILTERS MODULATOR as the spreading code). The effect of this is to spread the trans- Figure 36. Typical Analog QAM Architecture mitted signal across a wide spectrum. Similar to a DMT wave- form, a CDMA waveform containing multiple subscribers can In this implementation, it is much more difficult to maintain be characterized as having a high peak to average ratio (i.e., proper gain and phase matching between the I and Q channels. crest factor), thus demanding highly linear components in the The circuit implementation shown in Figure 37 helps improve transmit signal path. The bandwidth of the spectrum is defined upon the matching and temperature stability characteristics by the CDMA standard being used, and in operation is imple- between the I and Q channels, as well as showing a path for up- mented by using a spreading code with particular characteristics. conversion using the AD8346 quadrature modulator. Using a single voltage reference derived from U1 to set the gain for both Distortion in the transmit path can lead to power being trans- the I and Q channels will improve the gain matching and stabil- mitted out of the defined band. The ratio of power transmitted ity. R can be used to compensate for any mismatch in gain CAL in-band to out-of-band is often referred to as Adjacent Channel between the two channels. This mismatch may be attributed to Power (ACP). This is a regulatory issue due to the possibility of the mismatch between R and R , effective load resistance SET1 SET2 interference with other signals being transmitted by air. Regula- of each channel, and/or the voltage offset of the control ampli- tory bodies define a spectral mask outside of the transmit band, fier in each DAC. The differential voltage outputs of U1 and U2 and the ACP must fall under this mask. If distortion in the are fed into the respective differential inputs of the AD8346 via transmit path cause the ACP to be above the spectral mask, matching networks. then filtering, or different component selection is needed to meet the mask requirements. Using the same matching techniques described above, Figure 38 shows an example of the AD9752 used in a W-CDMA transmit- ter application using the AD6122 CDMA 3 V transmitter IF +5V 1.82V 634V DVDD 100W 0.1mF 500V REFLO 500V AVDD REFIO VPBF AD9752 BBIP IOUTA 500V (“I DAC”) U1 FSADJ C DAC FILTER R SET1 2kV LATCHES + IOUTB 500V BBIN I DATA VOUT 100V INPUT AVDD CLK LOIP 500V 500V 100V PHASE AVDD REFLO SPLITTER BBQP QOUTA 500V LATCHES Q DATA LOIN U2 INPUT C FILTER DAC AD9752 500V (“Q DAC”) QOUTB BBQN 100V AD8346 REFIO FSADJ SLEEP 500mV p-p WITH R SET2 V =1.2V CM 1.9kV 0.1mF DCOM R CAL NOTE: 500V RESISTOR NETWORK - OHMTEK ORN5000D 220V 100V RESISTOR NETWORK - TOMC1603-100D ACOM Figure 37. Baseband QAM Implementation Using Two AD9752s REV. 0 –17– AD9752 +3V 634V DVDD 100W REFLO AVDD 500V 500V REFIO AD9752 AD6122 500V IIPP IOUTA (“I DAC”) U1 FSADJ DAC C FILTER R SET1 2kV LATCHES IOUTB 500V IIPN I DATA 100V INPUT AVDD PHASE CLK LOIPP 42 SPLITTER LOIPN AVDD REFLO 500V 500V QOUTA IIQP LATCHES 500V Q DATA U2 INPUT DAC 100V 500V AD9752 QOUTB (“Q DAC”) IIQN TEMPERATURE REFIO 100V FSADJ SLEEP COMPENSATION R REFIN SET2 V V CC CC 1.9kV 0.1mF GAIN DCOM CONTROL R CAL SCALE 220V FACTOR ACOM GAIN VGAIN CONTROL TXOPP TXOPN Figure 38. CDMA Transmit Application Using AD9752 Figure 39 shows the AD9752 reconstructing a wideband, or QAM carrier frequency. Figure 40 shows a block diagram of W-CDMA test vector with a bandwidth of 5 MHz, centered at such an implementation using the AD9752. 15.625 MHz and being sampled at 62.5 MSPS. ACP for the given 12 test vector is measured at 70 dB. 12 I DATA STEL-1130 TO LPF QAM 12 MIXER –20 Q DATA 50V 50V AD9752 –30 12 12 –40 SIN COS –50 12 CARRIER STEL-1177 FREQUENCY NCO –60 –70 CLOCK –80 Figure 40. Digital QAM Architecture –90 CL1 CO CO CU1 –100 AD9752 EVALUATION BOARD General Description –110 The AD9752-EB is an evaluation board for the AD9752 12-bit –120 D/A converter. Careful attention to layout and circuit design CENTER 16.384MHz 1.4096MHz SPAN 14.096MHz combined with a prototyping area allow the user to easily and Figure 39. CDMA Signal, Sampled at 65 MSPS, Adjacent effectively evaluate the AD9752 in any application where high Channel Power >70 dBm resolution, high speed conversion is required. It is also possible to generate a QAM signal completely in the This board allows the user the flexibility to operate the AD9752 digital domain via a DSP or ASIC, in which case only a single in various configurations. Possible output configurations include DAC of sufficient resolution and performance is required to transformer coupled, resistor terminated, inverting/noninverting reconstruct the QAM signal. Also available from several vendors and differential amplifier outputs. The digital inputs are designed are Digital ASICs which implement other digital modulation to be driven directly from various word generators, with the schemes such as PSK and FSK. This digital implementation has on-board option to add a resistor network for proper load the benefit of generating perfectly matched I and Q components termination. Provisions are also made to operate the AD9752 in terms of gain and phase, which is essential in maintaining with either the internal or external reference, or to exercise the optimum performance in a communication system. In this imple- power-down feature. mentation, the reconstruction DAC must be operating at a Refer to the application note AN-420 for a thorough description sufficiently high clock rate to accommodate the highest specified and operating instructions for the AD9752 evaluation board. REV. 0 –18– AD9752 Figure 41. Evaluation Board Schematic REV. 0 –19– DVDD DGND AVDD AGND AVEE AVCC B1 B2 B3 B4 B5 B6 TP19 TP3 TP4 TP6 TP7 TP2 TP18 TP5 CLK TP1 J1 C3 C4 C5 C6 JP1 A A A AB 10mF 10mF 10mF 10mF EXTCLK 3 1 2 R15 DVDD DVDD 49.9V R1 R7 R5 R3 16 PINDIP U1 AVDD TP8 1 1 1 1 RES PK C7 C8 C9 P1 1mF 0.1mF 0.1mF AD975x 2 3 4 5 6 7 8 9 10 2 3 4 5 6 7 8 9 10 2 3 4 5 6 7 8 9 10 2 3 4 5 6 7 8 9 10 2 1 C19 1 16 1 28 DB13 CLOCK A 4 3 C1 2 15 2 27 DB12 DVDD 6 5 C2 3 14 3 26 DB11 DCOM 8 7 C25 4 13 4 25 DB10 NC 10 9 C26 5 12 5 24 DB9 AVDD AVDD C27 6 12 11 11 6 23 DB8 COMP2 OUT 1 C28 14 13 7 10 7 22 DB7 IOUTA OUT 2 16 15 C29 8 9 8 21 DB6 IOUTB 18 17 20 9 DB5 ACOM 20 19 10 19 COMP1 DB4 22 21 11 18 DB3 FS ADJ 24 23 16 PINDIP 17 12 DB2 REFIO 26 25 RES PK 16 13 DB1 REFLO 28 27 14 15 DB0 SLEEP TP11 TP10 TP9 TP13 30 29 C30 1 16 32 31 A C31 2 15 R16 34 33 CT1 AVDD C32 3 14 2kV 36 35 C33 4 13 C11 C10 38 37 A TP14 C34 5 12 0.1mF 0.1mF 1 40 39 C35 6 11 C36 7 10 2 JP4 JP2 3 10 98 76 54 32 10 98 76 54 32 10 98 76 54 32 10 98 76 54 32 PDIN TP12 A A A J2 AVDD 1 1 1 1 R2 R6 R4 R8 R17 49.9V DVDD DVDD AVCC R18 1kV AVCC AVCC U7 J3 A C21 C22 R42 3 B OUT1 JP6A JP7B 0.1mF 1mF REF43 C17 JP7A 1kV U4 2 6 JP3 0.1mF VIN VOUT 2 3 J6 J7 JP8 7 A R12 C18 C16 GND 6 U6 R20 C12 1 A A OPEN AD8047 0.1mF 1mF 22pF B B B 49.9V 4 3 T1 7 2 R37 R43 4 A C20 49.9V 5kV 4 6 R10 CW A 3 0 A A AD8047 A A 1kV 2 5 R14 A A A A 4 AVEE 0 JP6B A EXTREFIN 1 R36 JP5 J5 C14 1kV R45 6 1mF 1kV 3 2 1 A R13 R9 R35 A J4 OPEN A C15 1kV 1kV R44 C23 C24 OUT2 0.1mF 50V R46 0.1mF 1mF JP9 A A A 1kV B A C13 A R38 A 49.9V 22pF AVEE A A AD9752 Figure 42. Silkscreen Layer—Top Figure 43. Component Side PCB Layout (Layer 1) REV. 0 –20– AD9752 Figure 44. Ground Plane PCB Layout (Layer 2) Figure 45. Power Plane PCB Layout (Layer 3) REV. 0 –21– AD9752 Figure 46. Solder Side PCB Layout (Layer 4) Figure 47. Silkscreen Layer—Bottom REV. 0 –22– AD9752 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead, 300 Mil SOIC (R-28) 0.7125 (18.10) 0.6969 (17.70) 28 15 0.2992 (7.60) 0.2914 (7.40) 0.4193 (10.65) 0.3937 (10.00) 1 14 PIN 1 0.1043 (2.65) 0.0291 (0.74) 3 458 0.0926 (2.35) 0.0098 (0.25) 0.0500 (1.27) 88 0.0118 (0.30) 0.0500 0.0192 (0.49) 08 0.0157 (0.40) SEATING 0.0125 (0.32) (1.27) 0.0040 (0.10) 0.0138 (0.35) PLANE BSC 0.0091 (0.23) 28-Lead TSSOP (RU-28) 0.386 (9.80) 0.378 (9.60) 28 15 1 14 PIN 1 0.006 (0.15) 0.002 (0.05) 0.0433 (1.10) MAX 0.028 (0.70) 88 0.0118 (0.30) 0.0256 (0.65) 08 0.020 (0.50) SEATING 0.0079 (0.20) BSC 0.0075 (0.19) PLANE 0.0035 (0.090) REV. 0 –23– 0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25) PRINTED IN U.S.A. C3332–8–1/99