ANALOG DEVICES AD9751

10-Bit, 300 MSPS ® a High Speed TxDAC+ D/A Converter * AD9751 FEATURES FUNCTIONAL BLOCK DIAGRAM 10-Bit Dual Muxed Port DAC DVDD DCOM AVDD ACOM 300 MSPS Output Update Rate Excellent SFDR and IMD Performance SFDR to Nyquist @ 25 MHz Output: 64 dB LATCH PORT1 I OUTA Internal Clock Doubling PLL MUX DAC Differential or Single-Ended Clock Input I PORT2 LATCH OUTB On-Chip 1.2 V Reference Single 3.3 V Supply Operation CLK+ REFIO Power Dissipation: 155 mW @ 3.3 V PLL CLK– REFERENCE FSADJ CLOCK CLKVDD 48-Lead LQFP MULTIPLIER PLLVDD CLKCOM AD9751 APPLICATIONS Communications: LMDS, LMCS, MMDS RESET LPF DIV0 DIV1 PLLLOCK Base Stations Digital Synthesis QAM and OFDM PRODUCT DESCRIPTION The DAC utilizes a segmented current source architecture com- The AD9751 is a dual muxed port, ultrahigh speed, single- bined with a proprietary switching technique to reduce glitch channel, 10-bit CMOS DAC. It integrates a high quality 10-bit energy and maximize dynamic accuracy. Differential current TxDAC+ core, a voltage reference, and digital interface circuitry outputs support single-ended or differential applications. The into a small 48-lead LQFP package. The AD9751 offers excep- differential outputs each provide a nominal full-scale current tional ac and dc performance while supporting update rates up from 2 mA to 20 mA. to 300 MSPS. The AD9751 is manufactured on an advanced low cost 0.35 µm The AD9751 has been optimized for ultrahigh speed applica- CMOS process. It operates from a single supply of 3.0 V to 3.6 V tions up to 300 MSPS where data rates exceed those possible on and consumes 155 mW of power. a single data interface port DAC. The digital interface consists of two buffered latches as well as control logic. These latches PRODUCT HIGHLIGHTS can be time multiplexed to the high speed DAC in several ways. 1. The AD9751 is a member of a pin compatible family of high This PLL drives the DAC latch at twice the speed of the exter- speed TxDAC+s, providing 10-, 12-, and 14-bit resolution. nally applied clock and is able to interleave the data from the 2. Ultrahigh Speed 300 MSPS Conversion Rate. two input channels. The resulting output data rate is twice that 3. Dual 10-Bit Latched, Multiplexed Input Ports. The AD9751 of the two input channels. With the PLL disabled, an external features a flexible digital interface allowing high speed data 2× clock may be supplied and divided by two internally. conversion through either a single or dual port input. The CLK inputs (CLK+/CLK–) can be driven either differen- 4. Low Power. Complete CMOS DAC function operates on tially or single-ended, with a signal swing as low as 1 V p-p. 155 mW from a 3.0 V to 3.6 V single supply. The DAC full- scale current can be reduced for lower power operation. 5. On-Chip Voltage Reference. The AD9751 includes a 1.20 V temperature compensated band gap voltage reference. *Protected by U.S. Patent numbers 5450084, 5568145, 5689257, and 5703519. REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. may result from its use. No license is granted by implication or otherwise Tel: 781/329-4700 www.analog.com under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved. DAC LATCH AD9751–SPECIFICATIONS DC SPECIFICATIONS (T to T , AVDD = DVDD = PLLVDD = CLKVDD = 3.3 V, I = 20 mA, unless otherwise noted.) MIN MAX OUTFS Parameter Min Typ Max Unit RESOLUTION 10 Bits 1 DC ACCURACY Integral Linearity Error (INL) –1 ±0.3 +1 LSB Differential Nonlinearity (DNL) –0.5 ±0.2 +0.5 LSB ANALOG OUTPUT Offset Error –0.025 ±0.01 +0.025 % of FSR Gain Error (Without Internal Reference) –5 ±0.5 +2 % of FSR Gain Error (With Internal Reference) –7 ±0.25 +2 % of FSR 2 Full-Scale Output Current 2.0 20.0 mA Output Compliance Range –1.0 +1.25 V Output Resistance 100 kΩ Output Capacitance 5 pF REFERENCE OUTPUT Reference Voltage 1.14 1.20 1.26 V 3 Reference Output Current 100 nA REFERENCE INPUT Input Compliance Range 0.1 1.25 V Reference Input Resistance 1 MΩ TEMPERATURE COEFFICIENTS Offset Drift 0 ppm of FSR/°C Gain Drift (Without Internal Reference) ±50 ppm of FSR/°C Gain Drift (With Internal Reference) ±100 ppm of FSR/°C Reference Voltage Drift ±50 ppm/°C POWER SUPPLY Supply Voltages AVDD 3.0 3.3 3.6 V DVDD 3.0 3.3 3.6 V PLLVDD 3.0 3.3 3.6 V CLKVDD 3.0 3.3 3.6 V 4 Analog Supply Current (I ) 33 36 mA AVDD 4 Digital Supply Current (I ) 3.5 4.5 mA DVDD 4 PLL Supply Current (I ) 4.5 5.1 mA PLLVDD 4 Clock Supply Current (I ) 10.0 11.5 mA CLKVDD 4 Power Dissipation (3 V, I = 20 mA) 155 165 mW OUTFS 5 Power Dissipation (3 V, I = 20 mA) 216 mW OUTFS 6 Power Supply Rejection Ratio —AVDD –0.1 +0.1 % of FSR/V 6 Power Supply Rejection Ratio —DVDD –0.04 +0.04 % of FSR/V OPERATING RANGE –40 +85 °C NOTES 1 Measured at I , driving a virtual ground. OUTA 2 Nominal full-scale current, I , is 32× the I current. OUTFS REF 3 An external buffer amplifier is recommended to drive any external load. 4 100 MSPS f with PLL on, f = 1 MHz, all supplies = 3.0 V. DAC OUT 5 300 MSPS f . DAC 6 ±5% power supply variation. Specifications subject to change without notice. –2– REV. C AD9751 (T to T , AVDD = DVDD = CLKVDD = 3.3 V, PLLVDD = 0 V, I = 20 mA, Differential MIN MAX OUTFS DYNAMIC SPECIFICATIONS Transformer-Coupled Output, 50 � Doubly Terminated, unless otherwise noted.) Parameter Min Typ Max Unit DYNAMIC PERFORMANCE Maximum Output Update Rate (f ) 300 MSPS DAC 1 Output Settling Time (t ) (to 0.1%) 11 ns ST 1 Output Propagation Delay (t ) 1ns PD 1 Glitch Impulse 5 pV-s 1 Output Rise Time (10% to 90%) 2.5 ns 1 Output Fall Time (90% to 10%) 2.5 ns Output Noise (I = 20 mA) 50 pA/√Hz OUTFS Output Noise (I = 2 mA) 30 pA/√Hz OUTFS AC LINEARITY Spurious-Free Dynamic Range to Nyquist f = 100 MSPS; f = 1.00 MHz DAC OUT 0 dBFS Output 70 80 dBc –6 dBFS Output 72 dBc –12 dBFS Output 72 dBc 2 f = 65 MSPS; f = 1.1 MHz 73 dBc DATA OUT 2 f = 65 MSPS; f = 5.1 MHz 73 dBc DATA OUT 2 f = 65 MSPS; f = 10.1 MHz 72 dBc DATA OUT 2 f = 65 MSPS; f = 20.1 MHz 68 dBc DATA OUT 2 f = 65 MSPS; f = 30.1 MHz 64 dBc DATA OUT f = 200 MSPS; f = 1.1 MHz 74 dBc DAC OUT f = 200 MSPS; f = 11.1 MHz 71 dBc DAC OUT f = 200 MSPS; f = 31.1 MHz 66 dBc DAC OUT f = 200 MSPS; f = 51.1 MHz 66 dBc DAC OUT f = 200 MSPS; f = 71.1 MHz 63 dBc DAC OUT f = 300 MSPS; f = 1.1 MHz 74 dBc DAC OUT f = 300 MSPS; f = 26.1 MHz 71 dBc DAC OUT f = 300 MSPS; f = 51.1 MHz 66 dBc DAC OUT f = 300 MSPS; f = 101.1 MHz 66 dBc DAC OUT f = 300 MSPS; f = 141.1 MHz 63 dBc DAC OUT Spurious-Free Dynamic Range within a Window f = 100 MSPS; f = 1 MHz; 2 MHz Span DAC OUT 0 dBFS 81 91 dBc f = 65 MSPS; f = 5.02 MHz; 2 MHz Span 81 dBc DAC OUT f = 150 MSPS; f = 5.04 MHz; 4 MHz Span 81 dBc DAC OUT Total Harmonic Distortion f = 100 MSPS; f = 1.00 MHz DAC OUT 0 dBFS –80 –69 dBc f = 65 MHz; f = 2.00 MHz –72 dBc DAC OUT f = 150 MHz; f = 2.00 MHz –72 dBc DAC OUT Multitone Power Ratio (Eight Tones at 110 kHz Spacing) f = 65 MSPS; f = 2.00 MHz to 2.77 MHz DAC OUT 0 dBFS Output 69 dBc –6 dBFS Output 67 dBc –12 dBFS Output 65 dBc NOTES 1 Measured single-ended into 50 Ω load. 2 Single-Port Mode (PLL disabled, DIV0 = 1, DIV1 = 0, data on Port 1). Specifications subject to change without notice. REV. C –3– AD9751 DIGITAL SPECIFICATIONS (T to T , AVDD = DVDD = PLLVDD = CLKVDD = 3.3 V, I = 20 mA, unless otherwise noted.) MIN MAX OUTFS Parameter Min Typ Max Unit DIGITAL INPUTS Logic 1 2.1 3 V Logic 0 0 0.9 V Logic 1 Current –10 +10 µA Logic 0 Current –10 +10 µA Input Capacitance 5 pF Input Setup Time (t ), T = 25°C 1.0 0.5 ns S A Input Hold Time (t ), T = 25°C 1.0 0.5 ns H A Latch Pulsewidth (t ), T = 25°C 1.5 ns LPW A Input Setup Time (t PLLVDD = 0 V), T = 25°C –1.0 –1.5 ns S, A Input Hold Time (t PLLVDD = 0 V), T = 25°C 2.5 1.7 ns H, A CLK to PLLLOCK Delay (t , PLLVDD = 0 V), T = 25°C 3.5 4.0 ns D A Latch Pulsewidth (t PLLVDD = 0 V), T = 25°C 1.5 ns LPW A PLLOCK (V ) 3.0 V OH PLLOCK (V ) 0.3 V OL CLK INPUTS Input Voltage Range 0 3 V Common-Mode Voltage 0.75 1.5 2.25 V Differential Voltage 0.5 1.5 V Min CLK Frequency* 6.25 MHz *Min CLK Frequency applies only when using internal PLL. When PLL is disabled, there is no minimum CLK frequency. Specifications subject to change without notice. –4– REV. C AD9751 ABSOLUTE MAXIMUM RATINGS* Parameter With Respect to Min Max Unit AVDD, DVDD, CLKVDD, PLLVDD ACOM, DCOM, CLKCOM, PLLCOM –0.3 +3.9 V AVDD, DVDD, CLKVDD, PLLVDD AVDD, DVDD, CLKVDD, PLLVDD –3.9 +3.9 V ACOM, DCOM, CLKCOM, PLLCOM ACOM, DCOM, CLKCOM, PLLCOM –0.3 +0.3 V REFIO, REFLO, FSADJ ACOM –0.3 AVDD + 0.3 V I , I ACOM –1.0 AVDD + 0.3 V OUTA OUTB Digital Data Inputs (DB9 to DB0) DCOM –0.3 DVDD + 0.3 V CLK+/CLK–, PLLLOCK CLKCOM –0.3 CLKVDD + 0.3 V DIV0, DIV1, RESET CLKCOM –0.3 CLKVDD + 0.3 V LPF PLLCOM –0.3 PLLVDD + 0.3 V Junction Temperature 150 °C Storage Temperature –65 +150 °C Lead Temperature (10 sec) 300 °C *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. t t S H ORDERING GUIDE Temperature Package Package PORT 1 DATA X Model Range Description Option DATA IN PORT 2 DATA Y AD9751AST –40°C to +85°C 48-Lead LQFP ST-48 AD9751ASTRL –40°C to +85°C 48-Lead LQFP ST-48 AD9751-EB Evaluation Board INPUT CLK (PLL ENABLED) t t LPW PD DATA Y DATA X I OR I THERMAL CHARACTERISTIC OUTA OUTB Thermal Resistance t PD θ = 91°C/W JA Figure 1. I/O Timing CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD9751 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are ESD SENSITIVE DEVICE recommended to avoid performance degradation or loss of functionality. REV. C –5– AD9751 PIN CONFIGURATION 48 47 46 45 44 43 42 41 40 39 38 37 RESET 1 36 RESERVED PIN 1 CLK+ 2 IDENTIFIER 35 RESERVED 3 CLK– 34 RESERVED 4 DCOM 33 RESERVED 5 DVDD 32 P2B0–LSB AD9751 6 PLLLOCK 31 P2B1 TOP VIEW 7 MSB–P1B9 30 P2B2 (Not to Scale) P1B8 8 29 P2B3 P1B7 9 28 P2B4 P1B6 10 27 P2B5 P1B5 11 26 P2B6 P1B4 12 25 P2B7 13 14 15 16 17 18 19 20 21 22 23 24 RESERVED = NO USER CONNECTIONS PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Description 1 RESET Internal Clock Divider Reset 2 CLK+ Differential Clock Input 3 CLK– Differential Clock Input 4, 22 DCOM Digital Common 5, 21 DVDD Digital Supply Voltage 6PLLLOCK Phase-Locked Loop Lock Indicator Output 7–16 P1B9–P1B0 Data Bits P1B9 to P1B0, Port 1 17–20, 33–36 RESERVED 23–32 P2B9–P2B0 Data Bits P2B9 to P2B0, Port 2 37, 38 DIV0, DIV1 Control Inputs for PLL and Input Port Selector Mode; see Tables I and II for details. 39 REFIO Reference Input/Output 40 FSADJ Full-Scale Current Output Adjust 41 AVDD Analog Supply Voltage 42 I Differential DAC Current Output OUTB 43 I Differential DAC Current Output OUTA 44 ACOM Analog Common 45 CLKCOM Clock and Phase-Locked Loop Common 46 LPF Phase-Locked Loop Filter 47 PLLVDD Phase-Locked Loop Supply Voltage 48 CLKVDD Clock Supply Voltage –6– REV. C P1B3 CLKVDD P1B2 PLLVDD P1B1 LPF LSB–P1B0 CLKCOM RESERVED ACOM RESERVED I OUTA RESERVED I OUTB RESERVED AVDD DVDD FSADJ DCOM REFIO MSB–P2B9 DIV1 P2B8 DIV0 AD9751 TERMINOLOGY Power Supply Rejection Linearity Error (Also Called Integral Nonlinearity or INL) The maximum change in the full-scale output as the supplies Linearity error is defined as the maximum deviation of the actual are varied from minimum to maximum specified voltages. analog output from the ideal output, determined by a straight Settling Time line drawn from zero to full scale. The time required for the output to reach and remain within a Differential Nonlinearity (DNL) specified error band around its final value, measured from the DNL is the measure of the variation in analog value, normalized start of the output transition. to full scale, associated with a 1 LSB change in digital input code. Glitch Impulse Monotonicity Asymmetrical switching times in a DAC cause undesired output A D/A converter is monotonic if the output either increases or transients that are quantified by a glitch impulse. It is specified remains constant as the digital input increases. as the net area of the glitch in pV-s. Offset Error Spurious-Free Dynamic Range The deviation of the output current from the ideal of zero is The difference, in dB, between the rms amplitude of the output called offset error. For I , 0 mA output is expected when the OUTA signal and the peak spurious signal over the specified bandwidth. inputs are all 0s. For I , 0 mA output is expected when the OUTB Total Harmonic Distortion (THD) inputs are all 1s. THD is the ratio of the rms sum of the first six harmonic com- Gain Error ponents to the rms value of the measured fundamental. It is The difference between the actual and ideal output span. The expressed as a percentage or in decibels (dB). actual span is determined by the output when all inputs are set Signal-to-Noise Ratio (SNR) to 1s minus the output when all inputs are set to 0s. SNR is the ratio of the rms value of the measured output signal Output Compliance Range to the rms sum of all other spectral components below the The range of allowable voltage at the output of a current-output Nyquist frequency, excluding the first six harmonics and dc. DAC. Operation beyond the maximum compliance limits may The value for SNR is expressed in decibels. cause either output stage saturation or breakdown, resulting in Adjacent Channel Power Ratio (ACPR) nonlinear performance. A ratio in dBc between the measured power within a channel Temperature Drift relative to its adjacent channel. Specified as the maximum change from the ambient (25°C) value to the value at either T or T . For offset and gain MIN MAX drift, the drift is reported in ppm of full-scale range (FSR) per degree C. For reference drift, the drift is reported in ppm per degree C. 3.0V TO 3.6V MINI TO ROHDE & AVDD CIRCUITS SCHWARZ DVDD I OUTA T1-1T FSEA30 SEGMENTED 1.2V REF SPECTRUM PMOS CURRENT SWITCHES FOR I DAC OUTB 50� ANALYZER SOURCE ARRAY DB0 TO DB9 REFIO PLLVDD FSADJ 0.1�F CLKVDD DAC LATCH R 50� SET RESET PLL 2k� LPF 2–1 MUX CIRCUITRY CLKCOM AD9751 DIV0 DCOM DIV1 PORT 1 LATCH PORT 2 LATCH ACOM DB0 – DB9 DB0 – DB9 CLK+ CLK– PLLLOCK DIGITAL DATA INPUTS 1k� 3.0V TO 3.6V MINI TEKTRONIX DG2020 1k� CIRCUITS OR T1-1T AWG2021 w/OPTION 4 HP8644 PLL ENABLED LECROY 9210 SIGNAL PULSE GENERATOR PLL DISABLED GENERATOR (FOR DATA RETIMING) Figure 2. Basic AC Characterization Test Setup REV. C –7– AD9751–Typical Performance Characteristics 90 90 90 0dBFS 0dBFS 80 80 80 –6dBFS –12dBFS –12dBFS 70 70 70 –6dBFS –6dBFS –12dBFS 60 60 60 0dBFS 50 50 50 40 40 40 0 10 20 30 40 50 60 70 80 90 100 0 5 10 15 20 25 30 35 0 20 40 60 80 100 120 140 160 f (MHz) f (MHz) f (MHz) OUT OUT OUT TPC 2. Single-Tone SFDR vs. f TPC 3. Single-Tone SFDR vs. f @ TPC 1. Single-Tone SFDR vs. f @ OUT OUT OUT @ f = 200 MSPS f = 300 MSPS f = 65 MSPS; Single Port Mode DAC DAC DAC 90 90 90 SFDR NEAR CARRIERS (2F1-F2, 2F2-F1) 80 80 SFDR NEAR CARRIERS 80 (2F1-F2, 2F2-F1) 200MSPS 70 70 70 SFDR OVER 60 60 60 NYQUIST BAND 65MSPS 50 SFDR OVER NYQUIST BAND 50 50 300MSPS 40 40 40 0 10 20 30 40 50 60 70 80 90 100 0 20 40 60 80 100 120 140 160 0 20 40 60 80 100 120 140 f (MHz) f (MHz) f (MHz) OUT OUT OUT TPC 5. Two-Tone IMD vs. f @ TPC 6. Two-Tone IMD vs. f @ TPC 4. SFDR vs. f @ 0 dBFS OUT OUT OUT f = 200 MSPS, 1 MHz Spacing f = 300 MSPS, 1 MHz Spacing DAC DAC between Tones, 0 dBFS between Tones, 0 dBFS 90 90 90 18.18/19.18MHz 11.82MHz @ 130MSPS @ 200MSPS 80 80 80 18.18MHz @ 200MSPS 27.27/28.27MHz 40MHz @ 200MSPS @ 300MSPS 70 70 70 11.82/12.82MHz @ 130MSPS 26MHz @ 130MSPS 60 60 60 27.27MHz @ 300MSPS 60MHz @ 300MSPS 50 50 50 40 40 40 –16 –14 –12 –10 –8 –6 –4 –2 0 –20 –18 –16 –14 –12 –10 –8 –6 –4 –2 0 –16 –14 –12 –10 –8 –6 –4 –2 0 A (dBm) A (dBm) A (dB) OUT OUT OUT TPC 8. Single-Tone SFDR vs. A TPC 7. Single-Tone SFDR vs. A @ OUT OUT TPC 9. Two-Tone IMD (Third Order @ f = f /5 f = f /11 OUT DAC OUT DAC Products) vs. A @ f = f /11 OUT OUT DAC –8– REV. C SFDR (dBc) SFDR (dBc) SFDR (dBc) SFDR (dBc) SFDR (dBc) SFDR (dBc) SFDR (dBc) SFDR (dBc) SFDR (dBc) AD9751 90 90 90 26MHz/27MHz 18.18MHz/19.18MHz 80 80 80 @ 130MSPS @ 200MSPS 60MHz/61MHz @ 300MSPS 26MHz/27MHz 40MHz/41MHz @ 130MSPS 70 @ 200MSPS 70 70 11.82MHz/12.82MHz @ 130MSPS 40MHz/41MHz 60 60 60 @ 200MSPS 27.27MHz/28.27MHz @ 300MSPS 50 50 50 60MHz/61MHz @ 300MSPS 40 40 40 –20 –18 –16 –14 –12 –10 –8 –6 –4 –2 0 –20 –18 –16 –14 –12 –10 –8 –6 –4 –2 0 –20 –18 –16 –14 –12 –10 –8 –6 –4 –2 0 A (dBm) A (dBm) A (dBm) OUT OUT OUT TPC 10. Two-Tone IMD (to Nyquist) TPC 11. Two-Tone IMD (Third Order TPC 12. Two-Tone IMD (to Nyquist) vs. A @ f = f /11 Products) vs. A @ f = f /5 vs. A @ f = f /5 OUT OUT DAC OUT OUT DAC OUT OUT DAC 90 75 80 85 75 70 10MHz I = 20mA 80 OUTFS 70 65 75 65 60 I = 5mA OUTFS 40MHz 70 60 55 65 55 80MHz 50 I = 10mA OUTFS 60 50 45 120MHz 55 45 50 40 40 50 100 150 200 250 300 0 20 40 60 80 100 120 140 160 –50 –30 –10 10 30 50 70 90 f (MHz) f (MHz) TEMPERATURE (�C) DAC OUT TPC 13. SINAD vs. f @ f = TPC 14. SFDR vs. I , f = TPC 15. SFDR vs. Temperature, DAC OUT OUTFS DAC 10 MHz, 0 dBFS 300 MSPS @ 0 dBFS f = 300 MSPS @ 0 dBFS DAC 0.18 0 0.10 f = 300MSPS DAC –10 f = 24MHz OUT1 0.14 f = 25MHz –20 OUT2 0.05 f = 26MHz OUT3 –30 f = 27MHz OUT4 f = 28MHz 0.10 OUT5 –40 0 f = 29MHz OUT6 –50 f = 30MHz OUT7 f = 31MHz OUT8 0.06 –60 –0.05 SFDR = 58dBc MAGNITUDE = 0dBFS –70 0.02 –80 –0.10 –90 –0.02 –100 –0.15 0 127 255 383 511 639 767 895 1024 0 20 40 60 80 100 120 140 0 127 255 383 511 639 767 895 1024 CODE FREQUENCY (MHz) CODE TPC 17. Typical DNL TPC 16. Typical INL TPC 18. Eight-Tone SFDR @ f ≈ OUT f /11, f = 300 MSPS DAC DAC REV. C –9– INL (LSB) SINAD (dBm) SFDR (dBc) DNL (LSB) SFDR (dBc) SFDR (dBc) SFDR (dBc) SFDR (dBc) AMPLITUDE (dBm) AD9751 FUNCTIONAL DESCRIPTION REFERENCE OPERATION Figure 3 shows a simplified block diagram of the AD9751. The The AD9751 contains an internal 1.20 V band gap reference. AD9751 consists of a PMOS current source array capable of This can easily be overdriven by an external reference with no providing up to 20 mA of full-scale current, I . The array is effect on performance. REFIO serves as either an input or output, OUTFS divided into 31 equal sources that make up the five most signifi- depending on whether the internal or an external reference is cant bits (MSBs). The next four bits, or middle bits, consist of used. To use the internal reference, simply decouple the REFIO 15 equal current sources whose value is 1/16th of an MSB cur- pin to ACOM with a 0.1 µF capacitor. The internal reference rent source. The remaining LSB is a binary weighted fraction of voltage will be present at REFIO. If the voltage at REFIO is to the middle bit current sources. Implementing the middle and be used elsewhere in the circuit, an external buffer amplifier with lower bits with current sources, instead of an R-2R ladder, an input bias current less than 100 nA should be used. An example enhances dynamic performance for multitone or low amplitude of the use of the internal reference is shown in Figure 4. signals and helps maintain the DAC’s high output impedance A low impedance external reference can be applied to REFIO, (i.e., >100 kΩ). as shown in Figure 5. The external reference may provide either All of the current sources are switched to one or the other of the a fixed reference voltage to enhance accuracy and drift perfor- two outputs (i.e., I or I ) via PMOS differential current mance or a varying reference voltage for gain control. Note that OUTA OUTB switches. The switches are based on a new architecture that the 0.1 µF compensation capacitor is not required since the inter- significantly improves distortion performance. This new switch nal reference is overdriven, and the relatively high input impedance architecture reduces various timing errors and provides match- of REFIO minimizes any loading of the external reference. ing complementary drive signals to the inputs of the differential current switches. REFERENCE CONTROL AMPLIFIER The AD9751 also contains an internal control amplifier that is The analog and digital sections of the AD9751 have separate used to regulate the DAC’s full-scale output current, I . OUTFS power supply inputs (i.e., AVDD and DVDD) that can operate The control amplifier is configured as a voltage-to-current con- independently over a 3.0 V to 3.6 V range. The digital section, verter as shown in Figure 4, so that its current output, I , is REF which is capable of operating at a 300 MSPS clock rate, consists determined by the ratio of V and an external resistor, R , REFIO SET of edge-triggered latches and segment decoding logic circuitry. as stated in Equation 4. I is applied to the segmented current REF The analog section includes the PMOS current sources, the sources with the proper scaling factor to set I as stated in OUTFS associated differential switches, a 1.20 V band gap voltage refer- Equation 3. ence, and a reference control amplifier. The control amplifier allows a wide (10:1) adjustment span of The full-scale output current is regulated by the reference I over a 2 mA to 20 mA range by setting I between OUTFS REF control amplifier and can be set from 2 mA to 20 mA via an 62.5 µA and 625 µA. The wide adjustment span of I provides OUTFS external resistor, R . The external resistor, in combination SET several application benefits. The first benefit relates directly to with both the reference control amplifier and voltage reference the power dissipation of the AD9751, which is proportional to V , sets the reference current I , which is replicated to the REFIO REF I (refer to the Power Dissipation section). The second OUTFS segmented current sources with the proper scaling factor. The benefit relates to the 20 dB adjustment, which is useful for sys- full-scale current, I , is 32 times the value of I . OUTFS REF tem gain control purposes. The small signal bandwidth of the reference control amplifier is approximately 500 kHz and can be used for low frequency, small signal multiplying applications. 3.0V TO 3.6V V = V A – V B DIFF OUT OUT AVDD DVDD I OUTA SEGMENTED 1.2V REF V A OUT PMOS CURRENT SWITCHES FOR DAC I OUTB SOURCE ARRAY DB0 TO DB9 REFIO V B R OUT LOAD PLLVDD 50� FSADJ R 0.1�F LOAD DAC LATCH CLKVDD R 50� SET CLK+ PLL 2k� CLK– CIRCUITRY 2–1 MUX CLKCOM AD9751 RESET DCOM LPF PORT 1 LATCH PORT 2 LATCH ACOM DIV0 DB0 – DB9 DB0 – DB9 DIV1 PLLLOCK DIGITAL DATA INPUTS Figure 3. Simplified Block Diagram –10– REV. C AD9751 OPTIONAL t t S H AVDD EXTERNAL AD9751 REFERENCE REFERENCE BUFFER SECTION PORT 1 DATA X 1.2V REF DATA IN REFIO PORT 2 DATA Y CURRENT ADDITIONAL SOURCE EXTERNAL 0.1�F FSADJ LOAD ARRAY I 2k� REF CLK t t LPW PD DATA Y Figure 4. Internal Reference Configuration DATA X I OR I OUTA OUTB 1/2 CYCLE + t PD AVDD AD9751 REFERENCE 7a. DAC Input Timing Requirements with SECTION AVDD PLL Active, Single Clock Cycle 1.2V REF REFIO EXTERNAL CURRENT REFERENCE DATA Y DATA W PORT 1 SOURCE FSADJ ARRAY DATA IN I 2k� REF PORT 2 DATA X DATA Z Figure 5. External Reference Configuration CLK PLL CLOCK MULTIPLIER OPERATION XXX I OR I The Phase-Locked Loop (PLL) is intrinsic to the operation of the OUTA OUTB DATA W DATA X AD9751 in that it produces the necessary internally synchronized DATA Y DATA Z 2× clock for the edge-triggered latches, multiplexer, and DAC. Figure 7b. DAC Input Timing Requirements with With PLLVDD connected to its supply voltage, the AD9751 is PLL Active, Multiple Clock Cycles in PLL active mode. Figure 6 shows a functional block diagram of the AD9751 clock control circuitry with PLL active. The Typically, the VCO can generate outputs of 100 MHz to 400 MHz. circuitry consists of a phase detector, charge pump, voltage The range control is used to keep the VCO operating within its controlled oscillator (VCO), input data rate range control, clock designed range while allowing input clocks as low as 6.25 MHz. logic circuitry, and control input/outputs. The ÷2 logic in the With the PLL active, logic levels at DIV0 and DIV1 determine feedback loop allows the PLL to generate the 2× clock needed the divide (prescaler) ratio of the range controller. Table I gives for the DAC output latch. the frequency range of the input clock for the different states of DIV0 and DIV1. Figure 7 defines the input and output timing for the AD9751 with the PLL active. CLK in Figure 7 represents the clock that Table I. CLK Rates for DIV0, DIV1 Levels with PLL Active is generated external to the AD9751. The input data at both Ports 1 and 2 is latched on the same CLK rising edge. CLK CLK Frequency DIV1 DIV0 Range Controller may be applied as a single-ended signal by tying CLK– to 50 MHz–150 MHz 0 0 ÷1 midsupply and applying CLK to CLK+, or as a differential 25 MHz–100 MHz 0 1 ÷2 signal applied to CLK+ and CLK–. 12.5 MHz–50 MHz 1 0 ÷4 RESET has no purpose when using the internal PLL and 6.25 MHz–25 MHz 1 1 ÷8 should be grounded. When the AD9751 is in PLL active mode, PLLLOCK is the output of the internal phase detector. A 392 Ω resistor and 1.0 µF capacitor connected in series from When locked, the lock output in this mode is Logic 1. LPF to PLLVDD are required to optimize the phase noise versus settling/acquisition time characteristics of the PLL. To obtain 1.0�F 392� optimum noise and distortion performance, PLLVDD should 3.0V TO 3.6V CLKVDD be set to a voltage level similar to DVDD and CLKVDD. (3.0V TO 3.6V) PLLLOCK LPF PLLVDD In general, the best phase noise performance for any PLL range control setting is achieved with the VCO operating near its DIFFERENTIAL PHASE CHARGE VCO TO DETECTOR PUMP maximum output frequency of 400 MHz. SINGLE-ENDED AMP RANGE DIV0 As stated earlier, applications requiring input data rates below CLK+ CONTROL DIV1 (�1, 2, 4, 8) 6.25 MSPS must disable the PLL clock multiplier and provide an CLK– TO INPUT �2 external 2× reference clock. At higher data rates however, applica- LATCHES TO DAC tions already containing a low phase noise (i.e., jitter) reference LATCH AD9751 clock that is twice the input data rate should consider disabling the CLKCOM PLL clock multiplier to achieve the best SNR performance from the AD9751. Note that the SFDR performance of the AD9751 remains Figure 6. Clock Circuitry with PLL Active unaffected with or without the PLL clock multiplier enabled. REV. C –11– AD9751 The effects of phase noise on the AD9751’s SNR performance DAC TIMING WITH PLL ACTIVE become more noticeable at higher reconstructed output fre- As described in Figure 7, in PLL ACTIVE mode, Port 1 and quencies and signal levels. Figure 8 compares the phase noise of Port 2 input latches are updated on the rising edge of CLK. On a full-scale sine wave at exactly f /4 at different data rates the same rising edge, data previously present in the input Port 2 DATA (thus carrier frequency) with the optimum DIV1, DIV0 setting. latch is written to the DAC output latch. The DAC output will update after a short propagation delay (t ). PD 0 Following the rising edge of CLK, at a time equal to half of its –10 period, the data in the Port 1 latch will be written to the DAC –20 output latch, again with a corresponding change in the DAC –30 output. Due to the internal PLL, the time at which the data in –40 the Port 1 and Port 2 input latches is written to the DAC latch is independent of the duty cycle of CLK. When using the PLL, –50 PLL ON, f = 50MSPS DATA the external clock can be operated at any duty cycle that meets –60 PLL ON, f = 100MSPS DATA the specified input pulsewidth. PLL ON, f = 125MSPS –70 DATA On the next rising edge of CLK, the cycle begins again with the PLL ON, f = 150MSPS DATA –80 two input port latches being updated and the DAC output latch –90 being updated with the current data in the Port 2 input latch. –100 PLL OFF, f = 50MSPS DATA PLL DISABLED MODE –110 0 1 234 5 When PLLVDD is grounded, the PLL is disabled. An external FREQUENCY OFFSET (MHz) clock must now drive the CLK inputs at the desired DAC output update rate. The speed and timing of the data present at input Figure 8. Phase Noise of PLL Clock Multiplier at Ports 1 and 2 is now dependent on whether or not the AD9751 f = f /4 at Different f Settings with DIV0/DIV1 OUT DATA DATA is interleaving the digital input data or only responding to data Optimized, Using R&S FSEA30 Spectrum Analyzer, on a single port. Figure 10 is a functional block diagram of the RBW = 30 kHz AD9751 clock control circuitry with the PLL disabled. SNR is partly a function of the jitter generated by the clock circuitry. As a result, any noise on PLLVDD or CLKVDD may PLLLOCK degrade the SNR at the output of the DAC. To minimize this TO DAC potential problem, PLLVDD and CLKVDD can be connected AD9751 LATCH to DVDD using an LC filter network similar to the one shown CLOCK CLKIN+ TO INPUT LOGIC in Figure 9. LATCHES CLKIN– (�1 OR �2) DIFFERENTIAL TO TO FERRITE INTERNAL SINGLE-ENDED BEADS AMP MUX CLKVDD 10�F–22�F PLLVDD 100�F 0.1�F TANT. TTL/CMOS ELECT. CER. RESET DIV0 DIV1 LOGIC PLLVDD CIRCUITS Figure 10. Clock Circuitry with PLL Disabled CLKCOM DIV0 and DIV1 no longer control the PLL, but are used to set the control on the input mux for either interleaving or not 3.3V interleaving the input data. The different modes for states of POWER SUPPLY DIV0 and DIV1 are given in Table II. Figure 9. LC Network for Power Filtering Table II. Input Mode for DIV0, DIV1 Levels with PLL Disabled Input Mode DIV1 DIV0 Interleaved (2×)0 0 Noninterleaved Port 1 Selected 0 1 Port 2 Selected 1 0 Invalid 1 1 –12– REV. C NOISE DENSITY (dBm/Hz) AD9751 INTERLEAVED (2�) MODE WITH PLL DISABLED NONINTERLEAVED MODE WITH PLL DISABLED The relationship between the internal and external clocks in this If the data at only one port is required, the AD9751 interface mode is shown in Figure 11. A clock at the output update data can operate as a simple double-buffered latch with no interleaving. rate (2× the input data rate) must be applied to the CLK inputs. On the rising edge of the 1× clock, input latch 1 or 2 is updated Internal dividers then create the internal 1× clock necessary for with the present input data (depending on the state of DIV0/ the input latches. Although the input latches are updated on the DIV1). On the next rising edge, the DAC latch is updated and a rising edge of the delayed internal 1× clock, the setup-and-hold time t later, the DAC output reflects this change. Figure 13 PD times given in the Digital Specifications table are with respect to represents the AD9751 timing in this mode. the rising edge of the external 2× clock. With the PLL disabled, a load-dependent delayed version of the 1× clock is present at t t S H the PLLLOCK pin. This signal can be used to synchronize the DATA IN external data. PORT 1 OR PORT 2 t t S H 1� CLOCK PORT 1 DATA X t DATA ENTERS LPW t PD INPUT LATCHES DATA IN ON THIS EDGE DATA Y PORT 2 DATA OUT I OR I XX OUTA OUTB PORT 1 OR EXTERNAL PORT 2 2� CLK t LPW t t PD PD Figure 13. Timing Requirements, Noninterleaved Mode DELAYED INTERNAL with PLL Disabled 1� CLK t D EXTERNAL DAC TRANSFER FUNCTION 1� CLK @ PLLLOCK The AD9751 provides complementary current outputs, I OUTA and I . I provides a near full-scale current output, DATA Y OUTB OUTA DATA X I OR I OUTA OUTB I , when all bits are high (i.e., DAC CODE = 1023) while OUTFS I , the complementary output, provides no current. The OUTB Figure 11. Timing Requirements, Interleaved (2×) Mode current output appearing at I and I is a function of OUTA OUTB with PLL Disabled both the input code and I , and can be expressed as OUTFS Updates to the data at input Ports 1 and 2 should be synchro- I = DAC CODE 1024 × I (1) () OUTA OUTFS nized to the specific rising edge of the external 2× clock that corresponds to the rising edge of the 1× internal clock, as shown I =− 1023 DAC CODE 1024 × I (2) () OUTB OUTFS in Figure 11. To ensure synchronization, a Logic 1 must be where DAC CODE = 0 to 1023 (i.e., decimal representation). momentarily applied to the RESET pin. Doing this and return- ing RESET to Logic 0 brings the 1× clock at PLLLOCK to a As mentioned previously, I is a function of the reference OUTFS Logic 1. On the next rising edge of the 2× clock, the 1× clock will current, I , which is nominally set by a reference voltage, REF go to Logic 0. On the second rising edge of the 2× clock, the 1× V , and external resistor R . It can be expressed as REFIO SET clock (PLLLOCK) will again go to Logic 1, as well as update II =× 32 (3) OUTFS REF the data in both of the input latches. The details of this are where shown in Figure 12. IV = R (4) REF REFIO SET The two current outputs typically drive a resistive load directly DATA ENTERS INPUT LATCHES or via a transformer. If dc coupling is required, I and I OUTA OUTB ON THESE EDGES should be directly connected to matching resistive loads, R , LOAD RESET that are tied to analog common, ACOM. Note that R may LOAD represent the equivalent load resistance seen by I or I OUTA OUTB PLLLOCK as would be the case in a doubly terminated 50 Ω or 75 Ω cable. The single-ended voltage output appearing at the I and OUTA EXTERNAL I nodes is simply OUTB 2� CLOCK VI=×R (5) OUTA OUTA LOAD t = 1.2ns RH (6) VI=×R OUTB OUTB LOAD t = 0.2ns RS Note that the full-scale values of V and V should not OUTA OUTB Figure 12. Reset Function Timing with PLL Disabled exceed the specified output compliance range to maintain specified distortion and linearity performance. For proper synchronization, sufficient delay must be present between the time RESET goes low and the rising edge of the 2× VI=−I ×R (7) DIFF() OUTA OUTB LOAD clock. RESET going low must occur either at least t ns before RS Substituting the values of I , I , and I , V can be the rising edge of the 2× clock or t ns afterwards. In the first RH OUTA OUTB REF DIFF expressed as case, the immediately occurring CLK rising edge will cause PLLLOCK to go low. In the second case, the next CLK rising V=− 2 DAC CODE 1023 1024 × () DIFF{} edge will toggle PLLLOCK. (8) RR ×V () LOAD SET REFIO REV. C –13– AD9751 Equations 7 and 8 highlight some of the advantages of operating optimum performance. The negative output compliance range the AD9751 differentially. First, the differential operation helps of –1.0 V is set by the breakdown limits of the CMOS process. cancel common-mode error sources associated with I and Operation beyond this maximum limit may result in a break- OUTA I such as noise, distortion, and dc offsets. Second, the down of the output stage and affect the reliability of the AD9751. OUTB differential code-dependent current and subsequent voltage, V , DIFF The positive output compliance range is slightly dependent on is twice the value of the single-ended voltage output (i.e., V OUTA the full-scale output current, I . It degrades slightly from its OUTFS or V ), thus providing twice the signal power to the load. OUTB nominal 1.25 V for an I = 20 mA to 1.00 V for an I OUTFS OUTFS Note that the gain drift temperature performance for a single- = 2 mA. The optimum distortion performance for a single- ended (V and V ) or differential output (V ) of the ended or differential output is achieved when the maximum OUTA OUTB DIFF AD9751 can be enhanced by selecting temperature tracking full-scale signal at I and I does not exceed 1.0 V. OUTA OUTB resistors for R and R due to their ratiometric relation- Applications requiring the AD9751’s output (i.e., V and/or LOAD SET OUTA ship, as shown in Equation 8. V ) to extend its output compliance range should size R OUTB LOAD accordingly. Operation beyond this compliance range will adversely ANALOG OUTPUTS affect the AD9751’s linearity performance and subsequently The AD9751 produces two complementary current outputs, degrade its distortion performance. I and I , that may be configured for single-ended or OUTA OUTB differential operation. I and I can be converted into DIGITAL INPUTS OUTA OUTB complementary single-ended voltage outputs, V and V , The AD9751’s digital input consists of two channels of 10 data OUTA OUTB via a load resistor, R , as described by Equations 5 through 8 input pins each and a pair of differential clock input pins. The LOAD in the DAC Transfer Function section. The differential voltage, 10-bit parallel data inputs follow standard straight binary coding V , existing between V and V can also be converted where DB9 is the most significant bit (MSB) and DB0 is the DIFF OUTA OUTB to a single-ended voltage via a transformer or differential ampli- least significant bit (LSB). I produces a full-scale output OUTA fier configuration. The ac performance of the AD9751 is optimum current when all data bits are at Logic 1. I produces a OUTB and is specified using a differential transformer-coupled output in complementary output with the full-scale current split between which the voltage swing at I and I is limited to ±0.5 V. the two outputs as a function of the input code. OUTA OUTB If a single-ended unipolar output is desirable, I should be OUTA The digital interface is implemented using an edge-triggered selected as the output, with I grounded. OUTB master slave latch. With the PLL active or disabled, the DAC The distortion and noise performance of the AD9751 can be output is updated twice for every input latch rising edge, as enhanced when it is configured for differential operation. The shown in Figures 7 and 11. The AD9751 is designed to support common-mode error sources of both I and I can be an input data rate as high as 150 MSPS, giving a DAC output OUTA OUTB significantly reduced by the common-mode rejection of a trans- update rate of 300 MSPS. The setup-and-hold times can also be former or differential amplifier. These common-mode error varied within the clock cycle as long as the specified minimum sources include even-order distortion products and noise. The times are met. Best performance is typically achieved when the enhancement in distortion performance becomes more signifi- input data transitions on the falling edge of a 50% duty cycle clock. cant as the frequency content of the reconstructed waveform The digital inputs are CMOS compatible with logic thresholds, increases. This is due to the first order cancellation of various VTHRESHOLD, set to approximately half the digital positive dynamic common-mode distortion mechanisms, digital feed- supply (DVDD) or through, and noise. DVDD Performing a differential-to-single-ended conversion via a VTHRESHOLD=±20% () transformer also provides the ability to deliver twice the recon- 2 structed signal power to the load (i.e., assuming no source The internal digital circuitry of the AD9751 is capable of oper- termination). Since the output currents of I and I are OUTA OUTB ating over a digital supply range of 3.0 V to 3.6 V. As a result, complementary, they become additive when processed differen- the digital inputs can also accommodate TTL levels when DVDD tially. A properly selected transformer will allow the AD9751 to is set to accommodate the maximum high level voltage of the provide the required power and voltage levels to different loads. TTL drivers V (max). A DVDD of 3.0 V to 3.6 V typically OH Refer to Applying the AD9751 section for examples of various ensures proper compatibility with most TTL logic families. output configurations. Figure 14 shows the equivalent digital input circuit for the data The output impedance of I and I is determined by the and clock inputs. OUTA OUTB equivalent parallel combination of the PMOS switches associ- DVDD ated with the current sources and is typically 100 kΩ in parallel with 5 pF. It is also slightly dependent on the output voltage (i.e., V and V ) due to the nature of a PMOS device. OUTA OUTB DIGITAL INPUT As a result, maintaining I and/or I at a virtual ground OUTA OUTB via an I-V op amp configuration will result in the optimum dc linearity. Note that the INL/DNL specifications for the AD9751 are measured with I and I maintained at virtual ground OUTA OUTB Figure 14. Equivalent Digital Input via an op amp. The AD9751 features a flexible differential clock input operating I and I also have a negative and positive voltage OUTA OUTB from separate supplies (i.e., CLKVDD, CLKCOM) to achieve compliance range that must be adhered to in order to achieve optimum jitter performance. The two clock inputs, CLK+ and –14– REV. C AD9751 CLK–, can be driven from a single-ended or differential clock INPUT CLOCK AND DATA TIMING RELATIONSHIP source. For single-ended operation, CLK+ should be driven by SNR in a DAC is dependent on the relationship between the a logic source while CLK– should be set to the threshold voltage position of the clock edges and the point in time at which the of the logic source. This can be done via a resistor divider/ input data changes. The AD9751 is rising edge triggered, and so capacitor network, as shown in Figure 15a. For differential opera- exhibits SNR sensitivity when the data transition is close to this tion, both CLK+ and CLK– should be biased to CLKVDD/2 edge. In general, the goal when applying the AD9751 is to make via a resistor divider network, as shown in Figure 15b. the data transition close to the falling clock edge. This becomes more important as the sample rate increases. Figure 16 shows Because the output of the AD9751 can be updated at up to the relationship of SNR to clock placement with different sample 300 MSPS, the quality of the clock and data input signals are rates. Note that the setup-and-hold times implied in Figure 16 important in achieving the optimum performance. The driv- appear to violate the maximums stated in the Digital Specifica- ers of the digital data interface circuitry should be specified tions table. The variation in Figure 16 is due to the skew present to meet the minimum setup-and-hold times of the AD9751 as between data bits inherent in the digital data generator used to well as its required min/max input logic level thresholds. perform these tests. Figure 16 is presented to show the effects of Digital signal paths should be kept short and run lengths matched violating setup-and-hold times, and to show the insensitivity of to avoid propagation delay mismatch. Inserting a low value the AD9751 to clock placement when data transitions fall out- resistor network (i.e., 20 Ω to 100 Ω) between the AD9751 digi- side of the so-called “bad window.” The setup-and-hold times tal inputs and driver outputs may be helpful in reducing any stated in the Digital Specifications table were measured on a bit- overshooting and ringing at the digital inputs that contribute to by-bit basis, therefore eliminating the skew present in the digital data feedthrough. For longer run lengths and high data update data generator. At higher data rates, it becomes very important rates, strip line techniques with proper termination resistors to account for the skew in the input digital data when defining should be considered to maintain “clean” digital inputs. timing specifications. The external clock driver circuitry should provide the AD9751 with a low jitter clock input, meeting the min/max logic levels 80 while providing fast edges. Fast clock edges help minimize any jitter that manifests itself as phase noise on a reconstructed wave- 70 form. Thus, the clock input should be driven by the fastest logic 60 family suitable for the application. 50 The clock input could also be driven via a sine wave that is centered around the digital threshold (i.e., DVDD/2) and meets 40 the min/max logic threshold. This typically results in a slight degradation in the phase noise, which becomes more noticeable 30 at higher sampling rates and output frequencies. Also, at higher 20 sampling rates, the 20% tolerance of the digital logic threshold should be considered since it affects the effective clock duty 10 cycle and, subsequently, cuts into the required data setup-and- hold times. 0 –3 –2 –1 0 1 2 3 TIME OF DATA TRANSITION RELATIVE TO PLACEMENT OF CLK RISING EDGE (ns), f = 10MHz, f = 300MHz OUT DAC AD9751 R SERIES CLK+ Figure 16. SNR vs. Time of Data Transition Relative to Clock Rising Edge CLKVDD POWER DISSIPATION 0.1�F CLK– The power dissipation, P , of the AD9751 is dependent on sev- D V THRESHOLD CLKCOM eral factors that include the power supply voltages (AVDD and DVDD), the full-scale current output I , the update rate OUTFS f , and the reconstructed digital input waveform. The power CLOCK Figure 15a. Single-Ended Clock Interface dissipation is directly proportional to the analog supply current, I , and the digital supply current, I . I is directly AVDD DVDD AVDD AD9751 0.1�F proportional to I , as shown in Figure 17, and is insensitive OUTFS CLK+ to f . Conversely, I is dependent on both the digital CLOCK DVDD 0.1�F input waveform, f , and digital supply DVDD. Figure 18 CLOCK CLKVDD shows I as a function of the ratio (f /f ) for various DVDD OUT DAC 0.1�F update rates. In addition, Figure 19 shows the effect the speed CLK– of f on the PLLVDD current, given the PLL divider ratio. DAC CLKCOM Figure 15b. Differential Clock Interface REV. C –15– SNR (dBc) AD9751 40 APPLYING THE AD9751 OUTPUT CONFIGURATIONS 35 The following sections illustrate some typical output configura- tions for the AD9751. Unless otherwise noted, it is assumed 30 that I is set to a nominal 20 mA. For applications requir- OUTFS 25 ing the optimum dynamic performance, a differential output configuration is suggested. A differential output configuration 20 may consist of either an RF transformer or a differential op amp configuration. The transformer configuration provides the opti- 15 mum high frequency performance and is recommended for any 10 application allowing for ac coupling. The differential op amp configuration is suitable for applications requiring dc coupling, a 5 bipolar output, signal gain, and/or level shifting within the band- width of the chosen op amp. 0 0 2.5 5 7.5 10 12.5 15 17.5 20 I (mA) A single-ended output is suitable for applications requiring a OUTFS unipolar voltage output. A positive unipolar output voltage will Figure 17. I vs. I AVDD OUTFS result if I and/or I is connected to an appropriately OUTA OUTB sized load resistor, R , referred to ACOM. This configura- LOAD tion may be more suitable for a single-supply system requiring a 20 dc-coupled, ground referred output voltage. Alternatively, an 18 amplifier could be configured as an I-V converter, thus converting I or I into a negative unipolar voltage. This configuration 16 OUTA OUTB provides the best dc linearity, since I or I is maintained OUTA OUTB 14 at a virtual ground. Note that I provides slightly better per- OUTA 300MSPS 12 formance than I . OUTB 10 200MSPS DIFFERENTIAL COUPLING USING A TRANSFORMER 8 An RF transformer can be used to perform a differential-to- 100MSPS 6 single-ended signal conversion, as shown in Figure 20. A 50MSPS differentially-coupled transformer output provides the optimum 4 25MSPS distortion performance for output signals whose spectral content 2 lies within the transformer’s pass band. An RF transformer such 0 as the Mini-Circuits T1–1T provides excellent rejection of 0.001 0.01 0.1 1 common-mode distortion (i.e., even-order harmonics) and RATIO (f /f ) OUT DAC noise over a wide frequency range. When I and I are OUTA OUTB Figure 18. I vs. f /f Ratio DVDD OUT DAC terminated to ground with 50 Ω, this configuration provides 0dBm power to a 50 Ω load on the secondary with a DAC full- scale current of 20 mA. A 2:1 transformer, such as the Coilcraft 10 WB2040-PC, can also be used in a configuration in which I OUTA DIV SETTING 11 9 and I are terminated to ground with 75 Ω. This configura- OUTB DIV SETTING 10 tion improves load matching and increases power to 2 dBm into 8 DIV SETTING 01 a 50 Ω load on the secondary. Transformers with different 7 impedance ratios may also be used for impedance matching 6 purposes. Note that the transformer provides ac coupling only. 5 MINI-CIRCUITS DIV SETTING 00 4 AD9751 T1-1T I OUTA 3 R LOAD 2 I OUTB 1 0 0 25 50 75 100 125 150 175 200 225 250 275 300 f (MHz) DAC Figure 20. Differential Output Using a Transformer Figure 19. PLLVDD vs. f DAC –16– REV. C I (mA) I (mA) AVDD PLL_V (mA) DVDD DD AD9751 The center tap on the primary side of the transformer must be 500� connected to ACOM to provide the necessary dc current path AD9751 225� for both I and I . The complementary voltages appearing OUTA OUTB I OUTA at I and I (i.e., V and V ) swing symmetrically OUTA OUTB OUTA OUTB AD8041 225� around ACOM and should be maintained with the specified I OUTB C OPT output compliance range of the AD9751. A differential resistor, 1k� AVDD R , may be inserted into applications where the output of the DIFF 25� 25� 1k� transformer is connected to the load, R , via a passive recon- LOAD struction filter or cable. R is determined by the transformer’s DIFF impedance ratio and provides the proper source termination that Figure 22. Single-Supply DC Differential Coupled Circuit results in a low VSWR. SINGLE-ENDED UNBUFFERED VOLTAGE OUTPUT DIFFERENTIAL COUPLING USING AN OP AMP Figure 23 shows the AD9751 configured to provide a unipolar An op amp can also be used to perform a differential-to- output range of approximately 0 V to 0.5 V for a doubly-termi- single-ended conversion, as shown in Figure 21. The AD9751 nated 50 Ω cable, since the nominal full-scale current, I , of OUTFS is configured with two equal load resistors, R , of 25 Ω. The LOAD 20 mA flows through the equivalent R of 25 Ω. In this case, LOAD differential voltage developed across I and I is con- OUTA OUTB R represents the equivalent load resistance seen by I or LOAD OUTA verted to a single-ended signal via the differential op amp I . The unused output (I or I ) can be connected to OUTB OUTA OUTB configuration. An optional capacitor can be installed across ACOM directly or via a matching R . Different values of LOAD I and I , forming a real pole in a low-pass filter. The OUTA OUTB I and R can be selected as long as the positive com- OUTFS LOAD addition of this capacitor also enhances the op amp’s distortion pliance range is adhered to. One additional consideration in performance by preventing the DAC’s high slewing output from this mode is the integral nonlinearity (INL), as discussed in the overloading the op amp’s input. Analog Outputs section. For optimum INL performance, the single-ended, buffered voltage output configuration is suggested. 500� AD9751 225� AD9751 I = 20mA OUTFS I OUTA V = 0V TO 0.5V OUTA I OUTA AD8047 225� I 50� 50� OUTB C OPT I OUTB 500� 25� 25� 25� Figure 23. 0 V to 0.5 V Unbuffered Voltage Output Figure 21. DC Differential Coupling Using an Op Amp SINGLE-ENDED BUFFERED VOLTAGE OUTPUT The common-mode rejection of this configuration is typically Figure 24 shows a buffered single-ended output configuration in determined by the resistor matching. In this circuit, the dif- which the op amp performs an I–V conversion on the AD9751 ferential op amp circuit using the AD8047 is configured to output current. The op amp maintains I (or I ) at a provide some additional signal gain. The op amp must operate OUTA OUTB virtual ground, thus minimizing the nonlinear output impedance from a dual supply since its output is approximately ±1.0 V. effect on the DAC’s INL performance as discussed in the A high speed amplifier capable of preserving the differential Analog Output section. Although this single-ended configura- performance of the AD9751, while meeting other system- tion typically provides the best dc linearity performance, its ac level objectives (i.e., cost, power), should be selected. The op distortion performance at higher DAC update rates may be amp’s differential gain, gain setting resistor values, and full- limited by the op amp’s slewing capabilities. The op amp pro- scale output swing capabilities should all be considered when vides a negative unipolar output voltage and its full-scale output optimizing this circuit. voltage is simply the product of R and I . The full-scale FB OUTFS The differential circuit shown in Figure 22 provides the nec- output should be set within the op amp’s voltage output swing essary level-shifting required in a single-supply system. In this capabilities by scaling I and/or R . An improvement in ac OUTFS FB case, AVDD, which is the positive analog supply for both the distortion performance may result with a reduced I , since OUTFS AD9751 and the op amp, is also used to level-shift the differ- the signal current the op amp will be required to sink will subse- ential output of the AD9751 to midsupply (i.e., AVDD/2). The quently be reduced. AD8041 is a suitable op amp for this application. REV. C –17– AD9751 C Note that the units in Figure 25 are given in units of (amps out/ OPT volts in). Noise on the analog power supply has the effect of modu- R FB lating the internal switches, and therefore the output current. 200� The voltage noise on AVDD is thus added in a nonlinear man- AD9751 ner to the desired I . Due to the relative different size of these OUT I OUTA switches, PSRR is very code-dependent. This can produce a V = I � R OUT OUTFS FB mixing effect that can modulate low frequency power supply I OUTB noise to higher frequencies. Worst-case PSRR for either one of 200� the differential DAC outputs occurs when the full-scale current is directed toward that output. As a result, the PSRR measure- ment in Figure 25 represents a worst-case condition in which Figure 24. Unipolar Buffered Voltage Output the digital inputs remain static and the full-scale output current of 20 mA is directed to the DAC output being measured. POWER AND GROUNDING CONSIDERATIONS, POWER SUPPLY REJECTION An example serves to illustrate the effect of supply noise on the Many applications seek high speed and high performance under analog supply. Suppose a switching regulator with a switching less than ideal operating conditions. In these applications, the frequency of 250 kHz produces 10 mV rms of noise and, for the implementation and construction of the printed circuit board is sake of simplicity (i.e., ignore harmonics), all of this noise is as important as the circuit design. Proper RF techniques must concentrated at 250 kHz. To calculate how much of this undes- be used for device selection, placement, and routing, as well ired noise will appear as current noise superimposed on the as power supply bypassing and grounding, to ensure optimum DAC’s full-scale current, I , one must determine the PSRR OUTFS performance. Figures 34 to 41 illustrate the recommended in dB using Figure 25 at 250 kHz. To calculate the PSRR for a printed circuit board ground, power, and signal plane layouts given R , such that the units of PSRR are converted from LOAD that are implemented on the AD9751 evaluation board. A/V to V/V, adjust the curve in Figure 25 by the scaling factor 20� log (R ). For instance, if R is 50 Ω, the PSRR is One factor that can measurably affect system performance is the LOAD LOAD reduced by 34 dB, i.e., PSRR of the DAC at 250 kHz, which is ability of the DAC output to reject dc variations or ac noise 85 dB in Figure 25, becomes 51 dB V /V . superimposed on the analog or digital dc power distribution. OUT IN This is referred to as the Power Supply Rejection Ratio. For dc Proper grounding and decoupling should be a primary objective variations of the power supply, the resulting performance of the in any high speed, high resolution system. The AD9751 features DAC directly corresponds to a gain error associated with the separate analog and digital supply and ground pins to optimize DAC’s full-scale current, I . AC noise on the dc supplies is OUTFS the management of analog and digital ground currents in a sys- common in applications where the power distribution is gener- tem. In general, AVDD, the analog supply, should be decoupled ated by a switching power supply. Typically, switching power to ACOM, the analog common, as close to the chip as physi- supply noise occurs over the spectrum from tens of kHz to sev- cally possible. Similarly, DVDD, the digital supply, should be eral MHz. The PSRR versus frequency of the AD9751 AVDD decoupled to DCOM as close to the chip as physically possible. supply over this frequency range is shown in Figure 25. For those applications that require a single 3.3 V supply for both the analog and digital supplies, a clean analog supply may be 85 generated using the circuit shown in Figure 26. The circuit 80 consists of a differential LC filter with separate power supply 75 and return lines. Lower noise can be attained by using low ESR type electrolytic and tantalum capacitors. 70 FERRITE 65 BEADS AVDD 60 10�F–22�F 100�F 0.1�F TTL/CMOS TANT. ELECT. CER. LOGIC 55 ACOM CIRCUITS 50 45 3.3V 40 0 24 6 8 10 12 POWER SUPPLY FREQUENCY (MHz) Figure 26. Differential LC Filter for a Single 3.3 V Application Figure 25. Power Supply Rejection Ratio –18– REV. C PSRR (dB) AD9751 APPLICATIONS A figure of merit for wideband signal synthesis is the ratio of signal QAM/PSK Synthesis power in the transmitted band to the power in an adjacent chan- Quadrature modulation (QAM or PSK) consists of two baseband nel. In Figure 29, the adjacent channel power ratio (ACPR) at PAM (Pulse Amplitude Modulated) data channels. Both chan- the output of the AD9751 is measured to be 62 dB. The limita- nels are modulated by a common frequency carrier. However, tion on making a measurement of this type is often not the DAC the carriers for each channel are phase-shifted 90° from each but the noise inherent in creating the digital data record using other. This orthogonality allows twice the spectral efficiency computer tools. To find how much this is limiting the perceived (data for a given bandwidth) of digital data transmitted via AM. DAC performance, the signal amplitude can be reduced, as Receivers can be designed to selectively choose the “in phase” shown in Figure 29. The noise contributed by the DAC will and “quadrature” carriers, and then recombine the data. remain constant as the signal amplitude is reduced. When the The recombination of the QAM data can be mapped as points signal amplitude is reduced to the level where the noise floor representing digital words in a two-dimensional constellation, as drops below that of the spectrum analyzer, ACPR will fall off at shown in Figure 27. Each point, or symbol, represents the trans- the same rate that the signal level is being reduced. Under the mission of multiple bits in one symbol period. conditions measured in Figure 28, this point occurs in Figure 29 at –4 dBFS. This shows that the data record is actually degrad- ing the measured ACPR by up to 4 dB. 0100 0101 0001 0000 80 0110 0111 0011 0010 70 1110 1111 1011 1010 60 1100 1101 1001 1000 Figure 27. 16 QAM Constellation, Gray Coded (Two 4-Level 50 PAM Signals with Orthogonal Carriers) Typically, the I and Q data channels are quadrature-modulated in the digital domain. The high data rate of the AD9751 allows 40 –20 –15 –10 –5 0 extremely wideband (>10 MHz) quadrature carriers to be syn- AMPLITUDE (dBFS) thesized. Figure 28 shows an example of a 25 MSymbol/S QAM signal, oversampled by 8 at a data rate of 200 MSPS Figure 29. ACPR vs. Amplitude for QAM Carrier modulated onto a 25 MHz carrier and reconstructed using the A single-channel active mixer such as the Analog Devices AD8343 AD9751. The power in the reconstructed signal is measured can then be used for the hop to the transmit frequency. Figure 30 to be –12.08 dBm. In the first adjacent band, the power is shows an applications circuit using the AD9751 and the AD8343. –73.67 dBm, while in the second adjacent band the power is The AD8343 is capable of mixing carriers from dc to 2.5 GHz. –76.91 dBm. Figure 31 shows the result of mixing the signal in Figure 28 up to a carrier frequency of 800 MHz. ACPR measured at the MARKER 1 [T1] RBW 5kHz RF ATT 0dB –74.49dBm VBW 50kHz output of the AD8343 is shown in Figure 31 to be 58 dB. 9.71442886MHz SWT 12.5 s UNIT dBm –30 1 [T1] –74.49bBM, –40 +9.71442886MHz CH PWR –73.67dBm ACP UP –76.91dBm –50 ACP LOW –12.08dBm –60 1RM –70 1 –80 –90 –100 –110 C11 C11 Cu1 –120 Cu1 C0 C0 –130 START 100kHz 12.49MHz/ STOP 125MHz COMMENT A: 25 MSYMBOL, 64 QAM, CARRIER = 25MHz Figure 28. Reconstructing Raised Cosine Signal at 120 MHz IF REV. C –19– REF LV1 (dBm) ACPR (dB) AD9751 DVDD AVDD CLK+ CLK– PLLLOCK PLL/DIVIDER PORT 1 50� INPUT DATA LATCHES 0.1�F INPUT I INPP OUTA OUTP DAC 0.1�F OUTM PORT 2 I INPM OUTB INPUT LOIM DATA LATCHES 50� 68� 68� INPUT AD9751 LOIP FSADJ REFIO ACOM1 ACOM DCOM RSET2 AD8343 ACTIVE MIXER 1.9k� 0.1�F 0.1�F LOINPUT 0.1�F M/A-COM ETC-1-1-13 WIDEBAND BALUN Figure 30. QAM Transmitter Architecture Using AD9751 and AD8343 Active Mixer MARKER 1 [T2] RBW 10kHz RF ATT 0dB –100.59dBm VBW 10kHz 859.91983968MHz SWT 2.8 s UNIT dBm to-noise (E/N ) ratio of 27.8 dB. Due to the loss and interferers O –20 1 [T2] –100.59bBm, inherent in the wireless path, this signal-to-noise ratio must be –30 +859.91983968MHz realized at the receiver to achieve the given bit error rate. CH PWR –64.88dBm ACP UP –62.26dBm –40 ACP LOW –7.38dBm Distortion effects on BER are much more difficult to determine 1 [T2] 33.48dB –50 accurately. Most often in simulation, the energies of the strongest –49.91983968MHz 2MA 2 [T2] 33.10dB distortion components are root-sum-squared with the noise, and –60 –49.91983968MHz 1 2 the result is treated as if it were all noise. That being said, using –70 the example above of 64 QAM with the BER of 1e-6, if the E/N O –80 ratio is much greater than the worst-case SFDR, the noise will –90 dominate the BER calculation. 1 –100 The AD9751 has a worst-case in-band SFDR of 47 dB at the C11 C11 Cu1 upper end of its frequency spectrum (see TPCs 2 and 3). When Cu1 –110 C0 C0 used to synthesize high level QAM signals as described above, –120 noise, as opposed to distortion, will dominate its performance CENTER 860MHz 11MHz/ SPAN 110MHz in these applications. COMMENT A: 25 MSYMBOL, 64 QAM CARRIER @ 825MHz Figure 31. Signal of Figure 27 Mixed to Carrier 1E0 Frequency of 800 MHz Effects of Noise and Distortion on Bit Error Rate (BER) 1E–1 Textbook analysis of Bit Error Rate (BER) performance is generally stated in terms of E (energy in watts-per-symbol or 1E–2 16 QAM 64 QAM watts-per-bit) and N (spectral noise density in watts/Hz). For 4 QAM O QAM signals, this performance is shown graphically in Figure 32. 1E–3 M represents the number of levels in each quadrature PAM signal (i.e., M = 8 for 64 QAM, M = 16 for 256 QAM). Figure 32 1E–4 implies gray coding in the QAM constellation, as well as the use of matched filters at the receiver, which is typical. The horizontal axis of Figure 32 can be converted to units of energy/ 1E–5 symbol by adding to the horizontal axis 10 log of the number of bits in the desired curve. For instance, to achieve a BER of 1e-6 1E–6 0 5 10 15 20 with 64 QAM, an energy per bit of 20 dB is necessary. To SNR/BIT (dB) calculate energy per symbol, add 10 log(6) or 7.8 dB. Therefore 64 QAM with a BER of 1e-6 (assuming no source or channel Figure 32. Probability of a Symbol Error for QAM coding) can theoretically be achieved with an energy/symbol- –20– REV. C REF LV1 (dBm) DAC LATCHES SYMBOL ERROR PROBABILITY AD9751 Pseudo Zero Stuffing/IF Mode output differentially using the transformer, it is recommended The excellent dynamic range of the AD9751 allows its use in that either the Mini-Circuits T1-1T (through-hole) or the Coil- applications where synthesis of multiple carriers is desired. In craft TTWB-1-B (SMT) be placed in the position of T1 on the addition, the AD9751 can be used in a pseudo zero stuffing evaluation board. To evaluate the output either single-ended mode, which improves dynamic range at IF frequencies. In this or direct-coupled, remove the transformer and bridge either mode, data from the two input channels is interleaved to the BL1 or BL2. DAC, which is running at twice the speed of either of the input The digital data to the AD9751 comes from two ribbon cables ports. However, the data at Port 2 is held constant at midscale. that interface to the 40-lead IDC connectors P1 and P2. Proper The effect of this is shown in Figure 31. The IF signal is the termination or voltage scaling can be accomplished by installing image, with respect to the input data rate, of the fundamental. the resistor pack networks RN1–RN12. RN1, RN4, RN7, and Normally, the sinx/x response of the DAC attenuates this image. RN10 are 22 Ω DIP resistor packs and should be installed as they Zero stuffing improves the passband flatness so that the image help reduce the digital edge rates and therefore peak current on amplitude is closer to that of the fundamental signal. Zero the inputs. stuffing can be an especially useful technique in the synthesis A single-ended clock can be applied via J3. By setting the SE/ of IF signals. DIFF labeled jumpers J2, J3, J4, and J6, the input clock can be 0 directed to the CLK+/CLK– inputs of the AD9751 in either a single-ended or differential manner. If a differentially applied clock is desired, a Mini-Circuits T1-1T transformer should be –10 used in the position of T2. Note that with a single-ended square AMPLITUDE wave clock input, T2, must be removed. A clock can also be OF IMAGE –20 applied via the ribbon cable on Port 1 (P1), Pin 33. By inserting USING ZERO STUFFING the EDGE jumper (JP1), this clock will be applied to the CLK+ AMPLITUDE OF IMAGE input of the AD9751. JP3 should be set in its SE position in this –30 WITHOUT application to bias CLK– to half the supply voltage. ZERO STUFFING The AD9751’s PLL clock multiplier can be enabled by inserting –40 JP7 in the IN position. As described in the Typical Performance Characteristics and Functional Description sections, with the PLL enabled, a clock at half the output data rate should be –50 applied as described in the last paragraph. The PLL takes care 0 0.5 1 1.5 2 FREQUENCY (Normalized to Input Data Rate) of the internal 2× frequency multiplication and all internal tim- ing requirements. In this application, the PLLLOCK output Figure 33. Effects of Pseudo Zero Stuffing on Spectrum indicates when lock is achieved on the PLL. With the PLL of AD9751 enabled, the DIV0 and DIV1 jumpers (JP8 and JP9) provide the PLL divider ratio as described in Table I. EVALUATION BOARD The PLL is disabled when JP7 is in the EX setting. In this mode, The AD9751-EB is an evaluation board for the AD9751 TxDAC. a clock at the speed of the output data rate must be applied to the Careful attention to layout and circuit design, combined with clock inputs. Internally, the clock is divided by 2. For data syn- prototyping area, allows the user to easily and effectively evalu- chronization, a 1× clock is provided on the PLLLOCK pin in this ate the AD9751 in different modes of operation. application. Care should be taken to read the timing requirements Referring to Figures 34 and 35, the AD9751’s performance described earlier for optimum performance. With the PLL disabled, can be evaluated differentially or single-ended either using a the DIV0 and DIV1 jumpers define the mode (interleaved, transformer or directly coupling the output. To evaluate the noninterleaved) as described in Table II. REV. C –21– EFFECT OF SINX/X ROLL-OFF AD9751 RN2 RN3 VALUE VALUE RN1 1 1 VALUE 1B13 116 P1B13 2 2 2 P1 P1 1 1B13 1B12 P1B12 215 3 3 4 P1 P1 3 1B12 1B11314 P1B11 4 4 6 P1 P1 5 1B11 1B10413 P1B10 5 5 8 P1 P1 7 1B10 OUT16 1B09 512 P1B09 6 6 10 P1 P1 9 1B09 1 DVDD PLANE EDGE 1B08 P1B08 611 7 7 J1 A 12 P1 P1 11 2 1B08 1 JP5 B 1B07710 P1B07 8 8 EXT 14 P1 P1 13 1B07 RESET 3 DGND: 3,4,5 2 1B0689 P1B06 9 TP3 9 16 P1 P1 15 WHT 1B06 CLK– R4 10 10 P1B13 MSB 50� P1B12 CLK+ P P1B11 RN5 RN6 VALUE P1B10 PLLVDD PLANE VALUE RESET RN4 P1B09 VALUE 1 1 P1B08 12 11 10 9 8 76 54 3 2 1 NOTE: C11 1B05116 P1B05 2 2 18 P1 17 P1B07 SHIELD AROUND P1 1B05 1.0�F 13 48 CLKVDD R5 AND C11 ARE 1B04215 P1B04 3 P1B06 3 R5 20 P1 P1 19 14 47 CONNECTED TO 1B04 392� P1B05 LPF P1B03 PLLVDD PLANE 1B03314 4 15 4 46 22 P1 P1 21 1B03 P1B04 16 45 1B02 P1B02 413 5 5 P1B03 24 P1 P1 23 1B02 17 44 1B01512 P1B01 6 P1B02 IA 6 18 43 26 P1 P1 25 U1 1B01 P1B01 IB 19 42 1B00611 P1B00 7 7 AD9751/AD9753/AD9755 28 P1 27 P1 P1B00 LSB 1B00 20 41 AVDD PLANE 1O17 OUT15 710 8 8 30 P1 P1 29 21 40 1O15 DVDD PLANE OUT16 1O16 89 9 R3 9 22 39 R2 32 P1 P1 31 JP10 50� 50� 23 38 10 MSB 10 R10 34 P1 P1 33 P2B13 24 37 OPT 1O15 C10 C9 1O17 36 P1 P1 35 P2B12 10pF 10pF 1O16 25 26 27 28 29 30 31 32 33 34 35 36 P2B11 38 P1 P1 37 RN8 RN9 P2B10 VALUE VALUE 40 P1 P1 39 P2B09 RN7 I BL1 OUT 1 1 VALUE P2B08 J5 1 2B13 P2B13 P2B07 116 2 2 T1 2 P2 P2 1 2B13 3 P2B06 2 2B12 P2B12 215 3 3 4 4 P2 P2 3 2B12 P2B05 2B11 314 P2B11 4 4 P2B04 2 6 P2 P2 5 2B11 P2B03 6 2B10 413 P2B10 5 5 8 P2 P2 7 2B10 P2B02 1 P 2B09 P2B09 S 512 6 6 P2B01 10 P2 P2 9 2B09 2B08 P2B08 P2B00 LSB 611 7 7 TP1 12 P2 P2 11 2B08 R1 BL2 1.91k� 2B07 710 P2B07 8 8 FSADJ WHT 14 P2 P2 13 2B07 2B0689 P2B06 9 9 TP2 C12 16 P2 P2 15 2B06 0.1�F NOTES REFIO 10 10 WHT 1. ALL DIGITAL INPUTS FROM RN1–RN12 MUST BE OF EQUAL LENGTH. 2. ALL DECOUPLING CAPS TO BE LOCATED JP8 1 3 RN11 RN12 AS CLOSE AS POSSIBLE TO DUT, AB VALUE VALUE PREFERABLY UNDER DUT ON BOTTOM RN10 2 DIV1 SIGNAL LAYER. 1 1 VALUE 3. CONNECT GNDS UNDER DUT USING AVDD_PLANE 2B05 116 P2B05 2 2 BOTTOM SIGNAL LAYER. JP9 P2 17 18 P2 2B05 1 3 4. CREATE PLANE CAPACITOR WITH 0.007" 2B04 P2B04 215 3 3 AB 20 P2 P2 19 DIELECTRIC BETWEEN LAYERS 2 AND 3. 2B04 DIV0 2 2B03 314 P2B03 4 4 22 P2 P2 21 2B03 2B02 413 P2B02 5 5 24 P2 P2 23 2B02 2B01 512 P2B01 6 6 26 P2 P2 25 2B01 2B00 P2B00 TP4 TP5 TP6 TP7 TP8 TP9 TP10 TP12 611 7 7 28 27 P2 P2 2B00 BLK BLK BLK BLK BLK BLK BLK BLK 710 P2OUT15 8 8 30 P2 P2 29 2OUT15 89 P2OUT16 9 9 32 P2 P2 31 2OUT16 10 10 P 34 P2 P2 33 36 P2 P2 35 38 P2 P2 37 40 P2 P2 39 Figure 34. Evaluation Board Circuitry –22– REV. C AD9751 OUT15 EDGE JP1 1 SE 2 A CLK+ JP2 B DF R8 CKLVDD 3 50� T2 2 R9 3 CLK JP4 A 3 B 1 1k� 4 1 J3 DF 2 JP6 2 P PGND: 3, 4, 5 1 SE 6 P R7 A C16 2 CLK– JP3 1k� 0.1�F 1 P B P S DF 3 P L1 TP13 DVDD FBEAD RED 1 12 J8 DVDD PLANE U1 BYPASS CAPS C13 TP14 10�F DGND PINS 5, 6 PINS 21, 22 10V BLK DVDD PLANE 1 J9 C1 C2 C3 C4 0.1�F 1�F 0.1�F 1�F L2 TP15 AVDD FBEAD RED 1 12 J10 AVDD PLANE PINS 41, 44 C14 AVDD PLANE TP16 10�F AGND 10V C5 C6 BLK 1 0.1�F 1�F J11 L3 TP17 CLKVDD FBEAD RED 1 12 PINS 45, 47 J12 CLKVDD CLKVDD 1 C15 C7 C8 A 2 10�F TP11 JP7 PLLVDD PLANE 0.1�F 1�F B CLKGND 10V BLK 1 3 J13 P P Figure 35. Evaluation Board Clock Circuitry REV. C –23– AD9751 Figure 36. Evaluation Board, Assembly—Top Figure 37. Evaluation Board, Assembly—Bottom –24– REV. C AD9751 Figure 38. Evaluation Board, Top Layer Figure 39. Evaluation Board, Layer 2, Ground Plane REV. C –25– AD9751 Figure 40. Evaluation Board, Layer 3, Power Plane Figure 41. Evaluation Board, Bottom Layer –26– REV. C AD9751 OUTLINE DIMENSIONS 48-Lead Low Profile Quad Flat Package [LQFP] (ST-48) Dimensions shown in millimeters 0.75 9.00 BSC 1.60 0.60 SQ MAX 0.45 48 37 1 36 PIN 1 SEATING 10� PLANE 7.00 1.45 6� TOP VIEW 0.20 (PINS DOWN) BSC SQ 2� 1.40 0.09 1.35 VIEW A 7� 3.5� 12 25 0.15 0� 13 24 SEATING 0.05 0.08 MAX 0.27 PLANE 0.50 COPLANARITY 0.22 BSC VIEW A 0.17 ROTATED 90� CCW COMPLIANT TO JEDEC STANDARDS MS-026BBC REV. C –27– AD9751 Revision History Location Page 9/03—Data Sheet changed from REV. B to REV. C. Updated ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Changes to Figure 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Changes to Figure 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1/03—Data Sheet changed from REV. A to REV. B. Changes to Figure 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Changes to Figure 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3/02—Data Sheet changed from REV. 0 to REV. A. Changes to PRODUCT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Changes to PRODUCT HIGHLIGHTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Changes to DIGITAL SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Changes to Figure 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Edits to TPC 1, TPC 2, and TPC 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Changes to FUNCTIONAL DESCRIPTION Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Changes to Figure 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 5 replaced with new Figure 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Changes to Figure 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Edits to Figure 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Change to Figure 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Change to ANALOG OUTPUTS Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Changes to DIGITAL INPUTS Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 –28– REV. C C02250–0–9/03(C)