ANALOG DEVICES AD9750

10-Bit, 125 MSPS High Performance a ® TxDAC D/A Converter AD9750 FUNCTIONAL BLOCK DIAGRAM FEATURES High Performance Member of Pin-Compatible +5V TxDAC Product Family REFLO AVDD ACOM 125 MSPS Update Rate 150pF +1.20V REF AD9750 10-Bit Resolution 0.1mF REFIO 0.1mF CURRENT ICOMP Excellent Spurious Free Dynamic Range Performance FS ADJ SOURCE ARRAY SFDR to Nyquist @ 5 MHz Output: 76 dBc R SET DVDD +5V IOUTA Differential Current Outputs: 2 mA to 20 mA SEGMENTED LSB DCOM IOUTB SWITCHES SWITCH Power Dissipation: 190 mW @ 5 V CLOCK Power-Down Mode: 20 mW @ 5 V CLOCK LATCHES SLEEP On-Chip 1.20 V Reference CMOS-Compatible +2.7 V to +5.5 V Digital Interface DIGITAL DATA INPUTS (DB9–DB0) Packages: 28-Lead SOIC and TSSOP The AD9750 is a current-output DAC with a nominal full-scale Edge-Triggered Latches output current of 20 mA and > 100 kW output impedance. APPLICATIONS Differential current outputs are provided to support single- Wideband Communication Transmit Channel: ended or differential applications. Matching between the two Direct IF current outputs ensures enhanced dynamic performance in a Basestations differential output configuration. The current outputs may be Wireless Local Loop tied directly to an output resistor to provide two complemen- Digital Radio Link tary, single-ended voltage outputs or fed directly into a trans- Direct Digital Synthesis (DDS) former. The output voltage compliance range is 1.25 V. Instrumentation The on-chip reference and control amplifier are configured for PRODUCT DESCRIPTION maximum accuracy and flexibility. The AD9750 can be driven The AD9750 is a 10-bit resolution, wideband, second generation by the on-chip reference or by a variety of external reference member of the TxDAC series of high performance, low power voltages. The internal control amplifier, which provides a wide CMOS digital-to-analog-converters (DACs). The TxDAC family, (>10:1) adjustment span, allows the AD9750 full-scale current which consists of pin compatible 8-, 10-, 12-, and 14-bit DACs, to be adjusted over a 2 mA to 20 mA range while maintaining is specifically optimized for the transmit signal path of commu- excellent dynamic performance. Thus, the AD9750 may oper- nication systems. All of the devices share the same interface ate at reduced power levels or be adjusted over a 20 dB range to options, small outline package and pinout, thus providing an up- provide additional gain ranging capabilities. ward or downward component selection path based on perfor- The AD9750 is available in 28-lead SOIC and TSSOP packages. mance, resolution and cost. The AD9750 offers exceptional ac and It is specified for operation over the industrial temperature range. dc performance while supporting update rates up to 125 MSPS. The AD9750’s flexible single-supply operating range of 4.5 V to PRODUCT HIGHLIGHTS 5.5 V and low power dissipation are well suited for portable and 1. The AD9750 is a member of the wideband TxDAChigh per- low power applications. Its power dissipation can be further formance product family that provides an upward or downward reduced to a mere 65 mW, without a significant degradation in component selection path based on resolution (8 to 14 bits), performance, by lowering the full-scale current output. Also, a performance and cost. The entire family of TxDACs is avail- power-down mode reduces the standby power dissipation to able in industry standard pinouts. apprixmatley 20 mW. 2. Manufactured on a CMOS process, the AD9750 uses a The AD9750 is manufactured on an advanced CMOS process. proprietary switching technique that enhances dynamic A segmented current source architecture is combined with a performance beyond that previously attainable by higher proprietary switching technique to reduce spurious components power/cost bipolar or BiCMOS devices. and enhance dynamic performance. Edge-triggered input latches 3. On-chip, edge-triggered input CMOS latches interface to and a 1.2 V temperature compensated bandgap reference have +2.7 V to +5 V CMOS logic families. The AD9750 can been integrated to provide a complete monolithic DAC solution. support update rates up to 125 MSPS. The digital inputs support +2.7 V and +5 V CMOS logic families. 4. A flexible single-supply operating range of +4.5 V to +5.5 V, TxDAC is a registered trademark of Analog Devices, Inc. and a wide full-scale current adjustment span of 2 mA to *Protected by U.S. Patents Numbers 5450084, 5568145, 5689257, 5612697 and 20 mA, allows the AD9750 to operate at reduced power levels. 5703519. 5. The current output(s) of the AD9750 can be easily config- REV. 0 ured for various single-ended or differential circuit topologies. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties Tel: 781/329-4700 World Wide Web Site: http://www.analog.com which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 1999 AD9750–SPECIFICATIONS (T to T , AVDD = +5 V, DVDD = +5 V, I = 20 mA, unless otherwise noted) DC SPECIFICATIONS MIN MAX OUTFS Parameter Min Typ Max Units RESOLUTION 10 Bits 1 DC ACCURACY Integral Linearity Error (INL) –1.0–0.1 +1.0 LSB Differential Nonlinearity (DNL) –0.5–0.1 +0.5 LSB ANALOG OUTPUT Offset Error –0.02 +0.02 % of FSR Gain Error (Without Internal Reference) –2–0.5 +2 % of FSR Gain Error (With Internal Reference) –5–1.5 +5 % of FSR 2 Full-Scale Output Current 2.0 20.0 mA Output Compliance Range –1.0 1.25 V Output Resistance 100 kW Output Capacitance 5 pF REFERENCE OUTPUT Reference Voltage 1.14 1.20 1.26 V 3 Reference Output Current 100 nA REFERENCE INPUT Input Compliance Range 0.1 1.25 V Reference Input Resistance 1 MW Small Signal Bandwidth 0.5 MHz TEMPERATURE COEFFICIENTS Offset Drift 0 ppm of FSR/°C Gain Drift (Without Internal Reference)–50 ppm of FSR/°C Gain Drift (With Internal Reference)–100 ppm of FSR/°C Reference Voltage Drift–50 ppm/°C POWER SUPPLY Supply Voltages AVDD 4.5 5.0 5.5 V DVDD 2.7 5.0 5.5 V 4 ) 33 39 mA Analog Supply Current (I AVDD 5 Digital Supply Current (I ) 5.0 7 mA DVDD 6 Supply Current Sleep Mode (I ) 4.0 8 mA AVDD 5 (5 V, I = 20 mA) 190 230 mW Power Dissipation OUTFS 7 Power Supply Rejection Ratio —AVDD –0.4 +0.4 % of FSR/V 7 Power Supply Rejection Ratio —DVDD –0.025 +0.025 % of FSR/V OPERATING RANGE –40 +85 °C NOTES 1 Measured at IOUTA, driving a virtual ground. 2 Nominal full-scale current, I , is 32 · the I current. OUTFS REF 3 Use an external buffer amplifier to drive any external load. 4 Requires +5 V supply. 5 Measured at f = 50 MSPS and I = static full scale (20 mA). CLOCK OUT 6 Logic level for SLEEP pin must be referenced to AVDD. Min V = 3.5 V. IH 7 –5% Power supply variation. Specifications subject to change without notice. –2– REV. 0 AD9750 (T to T , AVDD = +5 V, DVDD = +5 V, I = 20 mA, Differential Transformer Coupled Output, MIN MAX OUTFS DYNAMIC SPECIFICATIONS 50 V Doubly Terminated, unless otherwise noted) Parameter Min Typ Max Units DYNAMIC PERFORMANCE Maximum Output Update Rate (f ) 125 MSPS CLOCK 1 Output Settling Time (t ) (to 0.1%) 35 ns ST Output Propagation Delay (t)1 ns PD Glitch Impulse 5 pV-s 1 Output Rise Time (10% to 90%) 2.5 ns 1 Output Fall Time (10% to 90%) 2.5 ns Output Noise (I = 20 mA) 50 pA/√Hz OUTFS Output Noise (I = 2 mA) 30 pA/√Hz OUTFS AC LINEARITY Spurious-Free Dynamic Range to Nyquist f = 50 MSPS; f = 1.00 MHz CLOCK OUT 0 dBFS Output T = +25°C 71 82 dBc A f = 50 MSPS; f = 2.51 MHz 79 dBc CLOCK OUT f = 50 MSPS; f = 5.02 MHz 76 dBc CLOCK OUT f = 50 MSPS; f = 20.2 MHz 60 dBc CLOCK OUT f = 100 MSPS; f = 2.51 MHz 78 dBc CLOCK OUT f = 100 MSPS; f = 5.04 MHz 77 dBc CLOCK OUT f = 100 MSPS; f = 20.2 MHz 69 dBc CLOCK OUT f = 100 MSPS; f = 40.4 MHz 63 dBc CLOCK OUT Spurious-Free Dynamic Range within a Window f = 50 MSPS; f = 1.00 MHz 80 87 dBc CLOCK OUT f = 50 MSPS; f = 5.02 MHz; 2 MHz Span 86 dBc CLOCK OUT f = 100 MSPS; f = 5.04 MHz; 4 MHz Span 86 dBc CLOCK OUT Total Harmonic Distortion f = 50 MSPS; f = 1.00 MHz CLOCK OUT T = +25°C –80 dBc A f = 50 MHz; f = 2.00 MHz –76 dBc CLOCK OUT f = 100 MHz; f = 2.00 MHz –76 dBc CLOCK OUT NOTES 1 Measured single ended into 50W load. Specifications subject to change without notice. –3– REV. 0 AD9750 DIGITAL SPECIFICATIONS (T to T , AVDD = +5 V, DVDD = +5 V, I = 20 mA unless otherwise noted) MIN MAX OUTFS Parameter Min Typ Max Units DIGITAL INPUTS 1 Logic “1” Voltage @ DVDD = +5 V 3.5 5 V Logic “1” Voltage @ DVDD = +3 V 2.1 3 V 1 Logic “0” Voltage @ DVDD = +5 V 0 1.3 V Logic “0” Voltage @ DVDD = +3 V 0 0.9 V Logic “1” Current –10 +10mA Logic “0” Current –10 +10mA Input Capacitance 5 pF Input Setup Time (t ) 2.0 ns S Input Hold Time (t ) 1.5 ns H Latch Pulsewidth (t ) 3.5 ns LPW NOTES 1 When DVDD = +5 V, and Logic 1 voltage »3.5 V and Logic 0 voltage »1.3 V, IVDD can increase by up to 10 mA depending on f . CLOCK Specifications subject to change without notice. DB0–DB11 t t S H CLOCK t LPW t PD t ST IOUTA OR 0.1% IOUTB 0.1% Figure 1. Timing Diagram ABSOLUTE MAXIMUM RATINGS* ORDERING GUIDE With Temperature Package Package Parameter Respect to Min Max Units Model Ranges Descriptions Options* AVDD ACOM –0.3 +6.5 V AD9750AR –40°C to +85°C 28-Lead 300 Mil SOIC R-28 DVDD DCOM –0.3 +6.5 V AD9750ARU –40°C to +85°C 28-Lead TSSOP RU-28 ACOM DCOM –0.3 +0.3 V AD9750-EB Evaluation Board AVDD DVDD –6.5 +6.5 V *R = Small Outline IC; RU = Thin Shrink Small Outline Package. CLOCK, SLEEP DCOM –0.3 DVDD + 0.3 V Digital Inputs DCOM –0.3 DVDD + 0.3 V THERMAL CHARACTERISTICS IOUTA, IOUTB ACOM –1.0 AVDD + 0.3 V Thermal Resistance ICOMP ACOM –0.3 AVDD + 0.3 V 28-Lead 300 Mil SOIC REFIO, FSADJ ACOM –0.3 AVDD + 0.3 V q = 71.4°C/W JA REFLO ACOM –0.3 +0.3 V q = 23°C/W JC Junction Temperature +150 °C 28-Lead TSSOP Storage Temperature –65 +150 °C q = 97.9°C/W JA Lead Temperature q = 14.0°C/W JC (10 sec) +300 °C *Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may effect device reliability. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD9750 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD ESD SENSITIVE DEVICE precautions are recommended to avoid performance degradation or loss of functionality. REV. 0 –4– AD9750 PIN CONFIGURATION (MSB) DB9 1 28 CLOCK DB8 2 27 DVDD DB7 3 26 DCOM DB6 4 25 NC DB5 5 24 AVDD AD9750 DB4 6 23 ICOMP TOP VIEW (Not to Scale) DB3 7 22 IOUTA DB2 8 21 IOUTB DB1 9 20 ACOM DB0 10 19 NC NC 11 18 FS ADJ NC 12 17 REFIO 13 16 REFLO NC NC 14 15 SLEEP NC = NO CONNECT PIN FUNCTION DESCRIPTIONS Pin No. Name Description 1 DB9 Most Significant Data Bit (MSB). 2–9 DB8–DB1 Data Bits 1–8. 10 DB0 Least Significant Data Bit (LSB). 11–14, 19, 25 NC No Internal Connection. 15 SLEEP Power-Down Control Input. Active High. Contains active pull-down circuit, thus may be left unterminated if not used. 16 REFLO Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal reference. 17 REFIO Reference Input/Output. Serves as reference input when internal reference disabled (i.e., Tie REFLO to AVDD). Serves as 1.2 V reference output when internal reference activated (i.e., Tie REFLO to ACOM). Requires 0.1mF capacitor to ACOM when internal reference activated. 18 FS ADJ Full-Scale Current Output Adjust. 20 ACOM Analog Common. 21 IOUTB Complementary DAC Current Output. Full-scale current when all data bits are 0s. 22 IOUTA DAC Current Output. Full-scale current when all data bits are 1s. 23 ICOMP Internal Bias Node for Switch Driver Circuitry. Decouple to ACOM with 0.1 mF capacitor. 24 AVDD Analog Supply Voltage (+4.5 V to +5.5 V). 26 DCOM Digital Common. 27 DVDD Digital Supply Voltage (+2.7 V to +5.5 V). 28 CLOCK Clock Input. Data latched on positive edge of clock. REV. 0 –5– AD9750 DEFINITIONS OF SPECIFICATIONS Power Supply Rejection Linearity Error (Also Called Integral Nonlinearity or INL) The maximum change in the full-scale output as the supplies Linearity error is defined as the maximum deviation of the are varied from nominal to minimum and maximum specified actual analog output from the ideal output, determined by a voltages. straight line drawn from zero to full scale. Settling Time Differential Nonlinearity (or DNL) The time required for the output to reach and remain within a DNL is the measure of the variation in analog value, normalized specified error band about its final value, measured from the to full scale, associated with a 1 LSB change in digital input code. start of the output transition. Monotonicity Glitch Impulse A D/A converter is monotonic if the output either increases or Asymmetrical switching times in a DAC give rise to undesired remains constant as the digital input increases. output transients that are quantified by a glitch impulse. It is specified as the net area of the glitch in pV-s. Offset Error The deviation of the output current from the ideal of zero is Spurious-Free Dynamic Range called offset error. For IOUTA, 0 mA output is expected when The difference, in dB, between the rms amplitude of the output the inputs are all 0s. For IOUTB, 0 mA output is expected signal and the peak spurious signal over the specified bandwidth. when all inputs are set to 1s. Total Harmonic Distortion Gain Error THD is the ratio of the rms sum of the first six harmonic The difference between the actual and ideal output span. The components to the rms value of the measured input signal. It is actual span is determined by the output when all inputs are set expressed as a percentage or in decibels (dB). to 1s minus the output when all inputs are set to 0s. Multitone Power Ratio Output Compliance Range The spurious-free dynamic range for an output containing mul- The range of allowable voltage at the output of a current-output tiple carrier tones of equal amplitude. It is measured as the DAC. Operation beyond the maximum compliance limits may difference between the rms amplitude of a carrier tone to the cause either output stage saturation or breakdown resulting in peak spurious signal in the region of a removed tone. nonlinear performance. Temperature Drift Temperature drift is specified as the maximum change from the ambient (+25°C) value to the value at either T or T . For MIN MAX offset and gain drift, the drift is reported in ppm of full-scale range (FSR) per degree C. For reference drift, the drift is reported in ppm per degree C. +5V REFLO AVDD ACOM 150pF +1.20V REF AD9750 0.1mF REFIO PMOS 0.1mF ICOMP CURRENT SOURCE FS ADJ MINI-CIRCUITS ARRAY R SET T1-1T TO HP3589A 2kV +5V DVDD IOUTA SPECTRUM/ SEGMENTED SWITCHES LSB NETWORK 100V DCOM IOUTB FOR DB9–DB1 SWITCH ANALYZER 50V INPUT CLOCK LATCHES DVDD 50V 20pF SLEEP DCOM 50V RETIMED 50V 20pF CLOCK DIGITAL OUTPUT* DATA * AWG2021 CLOCK RETIMED CLOCK SUCH THAT DIGITAL DATA OUTPUT TEKTRONIX LECROY 9210 TRANSITIONS ON FALLING EDGE AWG-2021 PULSE GENERATOR OF 50% DUTY CYCLE CLOCK. W/OPTION 4 Figure 2. Basic AC Characterization Test Set-Up REV. 0 –6– AD9750 Typical AC Characterization Curves @ +5 V Supplies (AVDD = +5 V, DVDD = +5 V, I = 20 mA, 50 V Doubly Terminated Load, Differential Output, T = +258C, SFDR up to Nyquist, unless otherwise noted) OUTFS A 90 90 90 0dBF S 0dBF 25MSPS S –6dBF S 80 80 80 100MSPS 70 70 70 –6dBF S –12dBF S 60 60 60 65MSPS –12dBF S 50 50 50 125MSPS 40 40 40 0 0 1 10 21 46 8 102 53 10 15 20 250 f – MHz f – MHz f – MHz OUT OUT OUT Figure 3. SFDR vs. f @ 0 dBFS Figure 4. SFDR vs. f @ 25 MSPS Figure 5. SFDR vs. f @ 65 MSPS OUT OUT OUT 90 90 90 0dBF 20mAF S S 80 80 80 –6dBF S 70 70 70 0dBF S –12dBF S 10mAF 60 60 S 60 –12dBF S –6dBF 5mAF S S 50 50 50 40 40 40 0 0 10 20 30 40 50 0 10 20 30 40 50 60 2 46 8 10 12 f – MHz f – MHz f – MHz OUT OUT OUT Figure 6. SFDR vs. f @ 100 MSPS Figure 7. SFDR vs. f @125 MSPS Figure 8. SFDR vs. f and I @ OUT OUT OUT OUTFS 25 MSPS and 0 dBFS 90 70 90 455kHz/5MSPS 1MHz/5MHz 66 80 80 5.91/65MSPS 62 I = 20mA OUTFS 5MHz/25MHz 70 70 58 2.27MHz/25MHz 13MHz/65MHz 60 60 54 I = 5mA OUTFS 11.37MHz/125MSPS 25MHz/125MHz I = 10mA OUTFS 50 50 50 0 –25 –20 –15 –10 –5 0 –25 –20 –15 –10 –5 0 10 20 30 40 50 60 A – dBc f – MSPS A – dBF OUT CLOCK OUT S Figure 9. Single-Tone SFDR vs. A Figure 10. Single-Tone SFDR vs. Figure 11. SNR vs. f and I OUT CLOCK OUTFS @ f = f /11 A @ f = f /5 @ f = 2 MHz and 0 dBFS OUT CLOCK OUT OUT CLOCK OUT REV. 0 –7– SFDR – dBc SFDR – dBc SFDR – dBc SFDR – dBc SFDR – dBc SFDR – dBc SFDR – dBc SNR – dB SFDR – dBc AD9750 0.2 0.08 90 0.15 f = 2.5MHz OUT 0.04 80 0.1 0 0.05 70 f = 10MHz OUT –0.04 0 f = 40MHz OUT 60 –0.08 –0.05 –0.1 –0.12 50 1000 1000 0 200 400 600 800 0 200 400 600 800 –60 –40 –20 0 20 40 60 80 100 CODE CODE TEMPERATURE – 8C Figure 14. SFDR vs. Temperature Figure 12. Typical INL Figure 13. Typical DNL @ 125 MSPS, 0 dBFS –10 0 f = 125MSPS f = 65MSPS CLOCK CLOCK –10 f = 13.5MHz –20 OUT1 f = 6.25MHz OUT1 f = 14.5MHz OUT2 f = 6.75MHz –20 OUT2 AMPLITUDE = 0dBF –30 S f = 7.25MHz OUT3 SDFR = 75dBc –30 f = 7.75MHz –40 OUT4 AMPLITUDE = 0dBF –40 S –50 SFDR = 70dBc –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 –100 30 0 510 15 20 25 462 810 12 14 16 180 22 24 f – MHz f – MHz OUT OUT Figure 15. Two-Tone SFDR Figure 16. Four-Tone SFDR REV. 0 –8– ERROR – LSB AMPLITUDE – dBm ERROR – LSB AMPLITUDE – dBm SFDR – dBc AD9750 FUNCTIONAL DESCRIPTION IOUTB = (1023 – DAC CODE)/1024 · I (2) OUTFS Figure 17 shows a simplified block diagram of the AD9750. where DAC CODE = 0 to 1023 (i.e., Decimal Representation). The AD9750 consists of a large PMOS current source array that As mentioned previously, I is a function of the reference OUTFS is capable of providing up to 20 mA of total current. The array current I , which is nominally set by a reference voltage REF is divided into 31 equal currents that make up the five most V and external resistor R . It can be expressed as: REFIO SET significant bits (MSBs). The next four bits or middle bits consist of 15 equal current sources whose value is 1/16th of an MSB I = 32 · I (3) OUTFS REF current source. The remaining LSB is a binary weighted frac- where I = V /R (4) REF REFIO SET tions of the middle-bits current sources. Implementing the The two current outputs will typically drive a resistive load middle and lower bits with current sources, instead of an R-2R directly or via a transformer. If dc coupling is required, IOUTA ladder, enhances its dynamic performance for multitone or low and IOUTB should be directly connected to matching resistive amplitude signals and helps maintain the DAC’s high output loads, R , which are tied to analog common, ACOM. Note, LOAD impedance (i.e., >100 kW). R may represent the equivalent load resistance seen by LOAD All of these current sources are switched to one or the other of IOUTA or IOUTB as would be the case in a doubly terminated the two output nodes (i.e., IOUTA or IOUTB) via PMOS 50W or 75W cable. The single-ended voltage output appearing differential current switches. The switches are based on a new at the IOUTA and IOUTB nodes is simply : architecture that drastically improves distortion performance. V = IOUTA · R (5) OUTA LOAD This new switch architecture reduces various timing errors and provides matching complementary drive signals to the inputs of V = IOUTB · R (6) OUTB LOAD the differential current switches. Note the full-scale value of V and V should not exceed OUTA OUTB The analog and digital sections of the AD9750 have separate the specified output compliance range to maintain specified power supply inputs (i.e., AVDD and DVDD). The digital distortion and linearity performance. section, which is capable of operating up to a 125 MSPS clock The differential voltage, V , appearing across IOUTA and DIFF rate and over a +2.7 V to +5.5 V operating range, consists of IOUTB is: edge-triggered latches and segment decoding logic circuitry. V = (IOUTA – IOUTB) · R (7) The analog section, which can operate over a +4.5 V to +5.5 V DIFF LOAD range, includes the PMOS current sources, the associated differ- Substituting the values of IOUTA, IOUTB, and I ; V can REF DIFF ential switches, a 1.20 V bandgap voltage reference and a refer- be expressed as: ence control amplifier. V = {(2 DAC CODE – 1023)/1024} ·DIFF The full-scale output current is regulated by the reference con- (32 R /R ) · V (8) LOAD SET REFIO trol amplifier and can be set from 2 mA to 20 mA via an exter- These last two equations highlight some of the advantages of nal resistor, R . The external resistor, in combination with SET operating the AD9750 differentially. First, the differential op- both the reference control amplifier and voltage reference V , REFIO eration will help cancel common-mode error sources associated sets the reference current I , which is mirrored over to the REF with IOUTA and IOUTB such as noise, distortion and dc off- segmented current sources with the proper scaling factor. The sets. Second, the differential code dependent current and subse- full-scale current, I , is thirty-two times the value of I . OUTFS REF quent voltage, V , is twice the value of the single-ended DIFF voltage output (i.e., V or V ), thus providing twice the OUTA OUTB DAC TRANSFER FUNCTION signal power to the load. The AD9750 provides complementary current outputs, IOUTA and IOUTB. IOUTA will provide a near full-scale current output, Note, the gain drift temperature performance for a single-ended I , when all bits are high (i.e., DAC CODE = 1023) while OUTFS (V and V ) or differential output (V ) of the AD9750 OUTA OUTB DIFF IOUTB, the complementary output, provides no current. The can be enhanced by selecting temperature tracking resistors for current output appearing at IOUTA and IOUTB is a function R and R due to their ratiometric relationship as shown LOAD SET of both the input code and I and can be expressed as: OUTFS in Equation 8. IOUTA = (DAC CODE/1024) · I (1) OUTFS +5V AVDD REFLO ACOM 150pF +1.20V REF AD9750 V REFIO REFIO PMOS 0.1mF ICOMP I REF CURRENT SOURCE FS ADJ 0.1mF ARRAY V = V – V R DIFF OUTA OUTB SET 2kV +5V DVDD I OUTA IOUTA V OUTA SEGMENTED SWITCHES LSB I DCOM IOUTB OUTB FOR DB9–DB1 V SWITCH OUTB R LOAD CLOCK 50V R LOAD CLOCK LATCHES 50V SLEEP DIGITAL DATA INPUTS (DB9–DB0) Figure 17. Functional Block Diagram REV. 0 –9– AD9750 REFERENCE OPERATION REFERENCE CONTROL AMPLIFIER The AD9750 contains an internal 1.20 V bandgap reference The AD9750 also contains an internal control amplifier that is that can easily be disabled and overridden by an external refer- used to regulate the DAC’s full-scale output current, I . OUTFS ence. REFIO serves as either an input or output depending on The control amplifier is configured as a V-I converter as shown whether the internal or an external reference is selected. If in Figure 19, such that its current output, I , is determined by REF REFLO is tied to ACOM, as shown in Figure 18, the internal the ratio of the V and an external resistor, R , as stated REFIO SET reference is activated and REFIO provides a 1.20 V output. In in Equation 4. I is copied over to the segmented current REF this case, the internal reference must be compensated externally sources with the proper scaling factor to set I as stated in OUTFS with a ceramic chip capacitor of 0.1mF or greater from REFIO Equation 3. to REFLO. Also, REFIO should be buffered with an external The control amplifier allows a wide (10:1) adjustment span of amplifier having an input bias current less than 100 nA if any I over a 2 mA to 20 mA range by setting IREF between OUTFS additional loading is required. 62.5mA and 625mA. The wide adjustment span of I OUTFS provides several application benefits. The first benefit relates +5V directly to the power dissipation of the AD9750, which is OPTIONAL EXTERNAL proportional to I (refer to the Power Dissipation section). OUTFS REF BUFFER REFLO AVDD 150pF The second benefit relates to the 20 dB adjustment, which is +1.2V REF useful for system gain control purposes. REFIO The small signal bandwidth of the reference control amplifier is CURRENT ADDITIONAL FS ADJ SOURCE 0.1mF approximately 0.5 MHz. The output of the control amplifier is LOAD ARRAY internally compensated via a 150 pF capacitor that limits the 2kV AD9750 control amplifier small-signal bandwidth and reduces its output impedance. Since the –3 dB bandwidth corresponds to Figure 18. Internal Reference Configuration the dominant pole, and hence the time constant, the settling time of the control amplifier to a stepped reference input re- The internal reference can be disabled by connecting REFLO to sponse can be approximated. In this case, the time constant can AVDD. In this case, an external reference may then be applied be approximated to be 320 ns. to REFIO as shown in Figure 19. The external reference may provide either a fixed reference voltage to enhance accuracy and There are two methods in which I can be varied for a fixed REF drift performance or a varying reference voltage for gain control. R . The first method is suitable for a single-supply system in SET Note that the 0.1mF compensation capacitor is not required which the internal reference is disabled, and the common-mode since the internal reference is disabled, and the high input im- voltage of REFIO is varied over its compliance range of 1.25 V pedance (i.e., 1 MW) of REFIO minimizes any loading of the to 0.10 V. REFIO can be driven by a single-supply amplifier or external reference. DAC, thus allowing I to be varied for a fixed R . Since the REF SET input impedance of REFIO is approximately 1 MW, a simple, AVDD low cost R-2R ladder DAC configured in the voltage mode topology may be used to control the gain. This circuit is shown REFLO 150pF AVDD in Figure 20 using the AD7524 and an external 1.2 V reference, AVDD the AD1580. +1.2V REF V REFIO REFIO EXTERNAL The second method may be used in a dual-supply system in CURRENT REF SOURCE FS ADJ which the common-mode voltage of REFIO is fixed and I is REF ARRAY varied by an external voltage, V , applied to R via an ampli- GC SET R I = SET REF V /R REFERENCE fier. An example of this method is shown in Figure 21, in which REFIO SET CONTROL AD9750 the internal reference is used to set the common-mode voltage AMPLIFIER of the control amplifier to 1.20 V. The external voltage, V , is GC referenced to ACOM and should not exceed 1.2 V. The value of Figure 19. External Reference Configuration R is such that I and I do not exceed 62.5mA SET REFMAX REFMIN AVDD AVDD REFLO AVDD 150pF R V +1.2V REF FB DD 1.2V OUT1 0.1V TO 1.2V REFIO AD7524 V REF CURRENT SOURCE OUT2 FS ADJ AD1580 ARRAY AGND R SET I = REF AD9750 V /R REF SET DB7–DB0 Figure 20. Single-Supply Gain Control Circuit REV. 0 –10– AD9750 For applications requiring the optimum dc linearity, IOUTA and 625mA, respectively. The associated equations in Figure 21 and/or IOUTB should be maintained at a virtual ground via an can be used to determine the value of R . SET I-V op amp configuration. Maintaining IOUTA and/or IOUTB AVDD at a virtual ground keeps the output impedance of the AD9750 fixed, significantly reducing its effect on linearity. However, it does not necessarily lead to the optimum distortion perfor- REFLO 150pF AVDD +1.2V REF mance due to limitations of the I-V op amp. Note that the INL/DNL specifications for the AD9750 are measured in REFIO CURRENT SOURCE FS ADJ this manner using IOUTA. In addition, these dc linearity 1mF ARRAY specifications remain virtually unaffected over the specified R SET I REF AD9750 power supply range of 4.5 V to 5.5 V. I = (1.2–V )/R REF GC SET Operating the AD9750 with reduced voltage output swings at V GC WITH V < V AND 62.5mA # I # 625A GC REFIO REF IOUTA and IOUTB in a differential or single-ended output Figure 21. Dual-Supply Gain Control Circuit configuration reduces the signal dependency of its output impedance thus enhancing distortion performance. Although ANALOG OUTPUTS the voltage compliance range of IOUTA and IOUTB extends The AD9750 produces two complementary current outputs, from –1.0 V to +1.25 V, optimum distortion performance is IOUTA and IOUTB, which may be configured for single-end achieved when the maximum full-scale signal at IOUTA and or differential operation. IOUTA and IOUTB can be converted IOUTB does not exceed approximately 0.5 V. A properly se- into complementary single-ended voltage outputs, V and OUTA lected transformer with a grounded center-tap will allow the V , via a load resistor, R , as described in the DAC OUTB LOAD AD9750 to provide the required power and voltage levels to Transfer Function section by Equations 5 through 8. The different loads while maintaining reduced voltage swings at differential voltage, V , existing between V and V DIFF OUTA OUTB IOUTA and IOUTB. DC-coupled applications requiring a can also be converted to a single-ended voltage via a transformer differential or single-ended output configuration should size or differential amplifier configuration. R accordingly. Refer to Applying the AD9750 section for LOAD examples of various output configurations. Figure 22 shows the equivalent analog output circuit of the AD9750 consisting of a parallel combination of PMOS differen- The most significant improvement in the AD9750’s distortion tial current switches associated with each segmented current and noise performance is realized using a differential output source. The output impedance of IOUTA and IOUTB is deter- configuration. The common-mode error sources of both IOUTA mined by the equivalent parallel combination of the PMOS and IOUTB can be substantially reduced by the common-mode switches and is typically 100 kW in parallel with 5 pF. Due to rejection of a transformer or differential amplifier. These the nature of a PMOS device, the output impedance is also common-mode error sources include even-order distortion slightly dependent on the output voltage (i.e., V and V ) OUTA OUTB products and noise. The enhancement in distortion performance and, to a lesser extent, the analog supply voltage, AVDD, and becomes more significant as the reconstructed wave-form’s full-scale current, I . Although the output impedance’s OUTFS frequency content increases and/or its amplitude decreases. signal dependency can be a source of dc nonlinearity and ac linear- The distortion and noise performance of the AD9750 is also ity (i.e., distortion), its effects can be limited if certain precau- slightly dependent on the analog and digital supply as well as the tions are noted. full-scale current setting, I . Operating the analog supply at OUTFS 5.0 V ensures maximum headroom for its internal PMOS current AVDD sources and differential switches leading to improved distortion performance. Although I can be set between 2 mA and OUTFS 20 mA, selecting an I of 20 mA will provide the best dis- OUTFS tortion and noise performance also shown in Figure 8. The noise performance of the AD9750 is affected by the digital sup- ply (DVDD), output frequency, and increases with increasing IOUTA IOUTB clock rate as shown in Figure 11. Operating the AD9750 with R R LOAD LOAD low voltage logic levels between 3 V and 3.3 V will slightly re- duce the amount of on-chip digital noise. Figure 22. Equivalent Analog Output In summary, the AD9750 achieves the optimum distortion and noise performance under the following conditions: IOUTA and IOUTB also have a negative and positive voltage compliance range. The negative output compliance range of (1) Differential Operation. –1.0 V is set by the breakdown limits of the CMOS process. (2) Positive voltage swing at IOUTA and IOUTB limited to Operation beyond this maximum limit may result in a break- +0.5 V. down of the output stage and affect the reliability of the AD9750. (3) I set to 20 mA. OUTFS The positive output compliance range is slightly dependent on (4) Analog Supply (AVDD) set at 5.0 V. the full-scale output current, I . It degrades slightly from its OUTFS (5) Digital Supply (DVDD) set at 3.0 V to 3.3 V with appro- nominal 1.25 V for an I = 20 mA to 1.00 V for an I = OUTFS OUTFS priate logic levels. 2 mA. Operation beyond the positive compliance range will induce clipping of the output signal which severely degrades Note that the ac performance of the AD9750 is characterized the AD9750’s linearity and distortion performance. under the above mentioned operating conditions. REV. 0 –11– AD9750 DIGITAL INPUTS resistors should be considered to maintain “clean” digital in- The AD9750’s digital input consists of 10 data input pins and a puts. Also, operating the AD9750 with reduced logic swings and clock input pin. The 10-bit parallel data inputs follow standard a corresponding digital supply (DVDD) will also reduce data positive binary coding where DB9 is the most significant bit feedthrough. (MSB) and DB0 is the least significant bit (LSB). IOUTA The external clock driver circuitry should provide the AD9750 produces a full-scale output current when all data bits are at with a low jitter clock input meeting the min/max logic levels Logic 1. IOUTB produces a complementary output with the while providing fast edges. Fast clock edges will help minimize full-scale current split between the two outputs as a function of any jitter that will manifest itself as phase noise on a recon- the input code. structed waveform. Thus, the clock input should be driven by The digital interface is implemented using an edge-triggered the fastest logic family suitable for the application. master slave latch. The DAC output is updated following the Note, the clock input could also be driven via a sine wave, which is rising edge of the clock as shown in Figure 1 and is designed to centered around the digital threshold (i.e., DVDD/2), and meets support a clock rate as high as 125 MSPS. The clock can be the min/max logic threshold. This will typically result in a slight operated at any duty cycle that meets the specified latch pulse- degradation in the phase noise, which becomes more noticeable width. The setup and hold times can also be varied within the at higher sampling rates and output frequencies. Also, at higher clock cycle as long as the specified minimum times are met; sampling rates, the 20% tolerance of the digital logic threshold although the location of these transition edges may affect digital should be considered since it will affect the effective clock duty feedthrough and distortion performance. Best performance is cycle and subsequently cut into the required data setup and typically achieved when the input data transitions on the falling edge hold times. of a 50% duty cycle clock. The digital inputs are CMOS compatible with logic thresholds, INPUT CLOCK/DATA TIMING RELATIONSHIP V set to approximately half the digital positive supply SNR in a DAC is dependent on the relationship between the THRESHOLD (DVDD) or position of the clock edges and the point in time at which the input data changes. The AD9750 is positive edge triggered, and V = DVDD/2 (–20%) THRESHOLD so exhibits SNR sensitivity when the data transition is close to The internal digital circuitry of the AD9750 is capable of operating this edge. In general, the goal when applying the AD9750 is to over a digital supply range of 2.7 V to 5.5 V. As a result, the make the data transitions shortly after the rising edge. This digital inputs can also accommodate TTL levels when DVDD is becomes more important as the sample rate increases. Figure 24 set to accommodate the maximum high level voltage of the TTL shows the relationship of SNR to clock placement with different drivers V . A DVDD of 3 V to 3.3 V will typically ensure OH(MAX) sample rates and different frequencies out. Note that at the proper compatibility with most TTL logic families. Figure 23 lower sample rates, much more tolerance is allowed in clock shows the equivalent digital input circuit for the data and clock placement, while at higher rates, much more care must be taken. inputs. The sleep mode input is similar with the exception that it contains an active pull-down circuit, thus ensuring that the 60 AD9750 remains enabled if this input is left disconnected. 56 DVDD F = 65MSPS S 52 DIGITAL INPUT F = 125MSPS S 48 44 Figure 23. Equivalent Digital Input Since the AD9750 is capable of being updated up to 125 MSPS, 40 the quality of the clock and data input signals are important in –10 –5 0 5 10 15 achieving the optimum performance. The drivers of the digital TIME OF DATA CHANGE RELATIVE TO RISING CLOCK EDGE – ns data interface circuitry should be specified to meet the minimum setup and hold times of the AD9750 as well as its required min/ Figure 24. SNR vs. Clock Placement 2 f = 10 MHz OUT max input logic level thresholds. Typically, the selection of the slowest logic family that satisfies the above conditions will SLEEP MODE OPERATION result in the lowest data feedthrough and noise. The AD9750 has a power-down function which turns off the output current and reduces the supply current to less than Digital signal paths should be kept short and run lengths 8.5 mA over the specified supply range of 2.7 V to 5.5 V and matched to avoid propagation delay mismatch. The insertion of temperature range. This mode can be activated by applying a a low value resistor network (i.e., 20W to 100W) between the logic level “1” to the SLEEP pin. This digital input also con- AD9750 digital inputs and driver outputs may be helpful in tains an active pull-down circuit that ensures the AD9750 re- reducing any overshooting and ringing at the digital inputs that mains enabled if this input is left disconnected. The AD9750 contribute to data feedthrough. For longer run lengths and high takes less than 50 ns to power down and approximately 5ms to data update rates, strip line techniques with proper termination power back up. REV. 0 –12– SNR – dB AD9750 8 POWER DISSIPATION 125MSPS The power dissipation, P , of the AD9750 is dependent on D several factors which include: (1) AVDD and DVDD, the power supply voltages; (2) I , the full-scale current output; OUTFS 6 100MSPS (3) f , the update rate; (4) and the reconstructed digital CLOCK input waveform. The power dissipation is directly proportional to the analog supply current, I , and the digital supply cur- AVDD 4 rent, I . I is directly proportional to I as shown in DVDD AVDD OUTFS 50MSPS Figure 25 and is insensitive to f . CLOCK 2 Conversely, I is dependent on both the digital input wave- DVDD 25MSPS form, f , and digital supply DVDD. Figures 26 and 27 CLOCK show I as a function of full-scale sine wave output ratios DVDD 5MSPS (f /f ) for various update rates with DVDD = 5 V and OUT CLOCK 0 0.01 0.1 1 DVDD = 3 V, respectively. Note, how I is reduced by more DVDD RATIO (f /f ) CLOCK OUT than a factor of 2 when DVDD is reduced from 5 V to 3 V. Figure 27. I vs. Ratio @ DVDD = 3 V DVDD 35 APPLYING THE AD9750 30 OUTPUT CONFIGURATIONS The following sections illustrate some typical output configura- tions for the AD9750. Unless otherwise noted, it is assumed 25 that I is set to a nominal 20 mA. For applications requir- OUTFS ing the optimum dynamic performance, a differential output 20 configuration is suggested. A differential output configuration may consist of either an RF transformer or a differential op amp 15 configuration. The transformer configuration provides the opti- mum high frequency performance and is recommended for any 10 application allowing for ac coupling. The differential op amp configuration is suitable for applications requiring dc coupling, a 5 22 4 6 8 10 12 1416180 bipolar output, signal gain and/or level shifting. I – mA OUTFS A single-ended output is suitable for applications requiring a Figure 25. I vs. I AVDD OUTFS unipolar voltage output. A positive unipolar output voltage will result if IOUTA and/or IOUTB is connected to an appropri- 18 ately sized load resistor, R , referred to ACOM. This con- LOAD 125MSPS figuration may be more suitable for a single-supply system 16 requiring a dc coupled, ground referred output voltage. Alterna- 14 tively, an amplifier could be configured as an I-V converter thus 100MSPS 12 converting IOUTA or IOUTB into a negative unipolar voltage. This configuration provides the best dc linearity since IOUTA 10 or IOUTB is maintained at a virtual ground. Note, IOUTA 8 provides slightly better performance than IOUTB. 50MSPS 6 DIFFERENTIAL COUPLING USING A TRANSFORMER 4 25MSPS An RF transformer can be used to perform a differential-to- 2 single-ended signal conversion as shown in Figure 28. A 5MSPS differentially coupled transformer output provides the optimum 0 0.01 0.1 1 distortion performance for output signals whose spectral content RATIO (f /f ) CLOCK OUT lies within the transformer’s passband. An RF transformer such as the Mini-Circuits T1-1T provides excellent rejection of Figure 26. I vs. Ratio @ DVDD = 5 V DVDD common-mode distortion (i.e., even-order harmonics) and noise over a wide frequency range. It also provides electrical isolation and the ability to deliver twice the power to the load. Trans- formers with different impedance ratios may also be used for impedance matching purposes. Note that the transformer provides ac coupling only. REV. 0 –13– I – mA I – mA AVDD DVDD I – mA DVDD AD9750 MINI-CIRCUITS 500V T1-1T IOUTA AD9750 225V R IOUTA LOAD AD9750 AD8041 225V IOUTB IOUTB OPTIONAL R C DIFF OPT 1kV AVDD 25V 25V 1kV Figure 28. Differential Output Using a Transformer The center tap on the primary side of the transformer must be connected to ACOM to provide the necessary dc current path Figure 30. Single-Supply DC Differential Coupled Circuit for both IOUTA and IOUTB. The complementary voltages appearing at IOUTA and IOUTB (i.e., V and V ) swing OUTA OUTB SINGLE-ENDED UNBUFFERED VOLTAGE OUTPUT symmetrically around ACOM and should be maintained with Figure 31 shows the AD9750 configured to provide a unipolar the specified output compliance range of the AD9750. A differ- output range of approximately 0 V to +0.5 V for a doubly termi- ential resistor, R , may be inserted in applications in which DIFF nated 50W cable since the nominal full-scale current, I , of OUTFS the output of the transformer is connected to the load, R , LOAD 20 mA flows through the equivalent R of 25W. In this LOAD via a passive reconstruction filter or cable. R is determined DIFF case, R represents the equivalent load resistance seen by LOAD by the transformer’s impedance ratio and provides the proper IOUTA or IOUTB. The unused output (IOUTA or IOUTB) source termination which results in a low VSWR. Note that can be connected to ACOM directly or via a matching R . LOAD approximately half the signal power will be dissipated across R . DIFF Different values of I and R can be selected as long as OUTFS LOAD the positive compliance range is adhered to. One additional DIFFERENTIAL USING AN OP AMP consideration in this mode is the integral nonlinearity (INL) as An op amp can also be used to perform a differential to single- discussed in the ANALOG OUTPUT section of this data sheet. ended conversion as shown in Figure 29. The AD9750 is con- For optimum INL performance, the single-ended, buffered figured with two equal load resistors, R , of 25 W. The LOAD voltage output configuration is suggested. differential voltage developed across IOUTA and IOUTB is converted to a single-ended signal via the differential op amp I = 20mA configuration. An optional capacitor can be installed across AD9750 OUTFS V = 0 TO +0.5V OUTA IOUTA IOUTA and IOUTB forming a real pole in a low-pass filter. The addition of this capacitor also enhances the op amps distor- 50V 50V IOUTB tion performance by preventing the DACs high slewing output 25V from overloading the op amp’s input. 500V Figure 31. 0 V to +0.5 V Unbuffered Voltage Output AD9750 225V IOUTA SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT AD8055 225V CONFIGURATION IOUTB Figure 32 shows a buffered single-ended output configuration in C OPT 500V which the op amp U1 performs an I-V conversion on the AD9750 25V 25V output current. U1 maintains IOUTA (or IOUTB) at a virtual ground, thus minimizing the nonlinear output impedance effect on the DAC’s INL performance as discussed in the ANALOG Figure 29. DC Differential Coupling Using an Op Amp OUTPUT section. Although this single-ended configuration The common-mode rejection of this configuration is typically typically provides the best dc linearity performance, its ac distor- determined by the resistor matching. In this circuit, the differ- tion performance at higher DAC update rates may be limited by ential op amp circuit is configured to provide some additional U1’s slewing capabilities. U1 provides a negative unipolar out- signal gain. The op amp must operate off of a dual supply since put voltage and its full-scale output voltage is simply the its output is approximately –1.0 V. A high speed amplifier such product of R and I . The full-scale output should be set FB OUTFS as the AD8055 or AD8057 capable of preserving the differential within U1’s voltage output swing capabilities by scaling I OUTFS performance of the AD9750 while meeting other system level and/or R . An improvement in ac distortion performance may FB objectives (i.e., cost, power) should be selected. The op amps result with a reduced I since the signal current U1 will be OUTFS differential gain, its gain setting resistor values, and full-scale required to sink will be subsequently reduced. output swing capabilities should all be considered when opti- mizing this circuit. The differential circuit shown in Figure 30 provides the neces- sary level-shifting required in a single supply system. In this case, AVDD which is the positive analog supply for both the AD9750 and the op amp is also used to level-shift the differ- ential output of the AD9750 to midsupply (i.e., AVDD/2). The AD8041 is a suitable op amp for this application. REV. 0 –14– AD9750 C OPT different sizes of these switches, PSRR is very code-dependent. This can produce a mixing effect which can modulate low fre- R FB quency power supply noise to higher frequencies. Worst case 200V PSRR for either one of the differential DAC outputs will occur I = 10mA OUTFS AD9750 when the full-scale current is directed towards that output. As a IOUTA result, the PSRR measurement in Figure 33 represents a worst U1 V = I 3 R OUT OUTFS FB case condition in which the digital inputs remain static and the IOUTB full-scale output current of 20 mA is directed to the DAC out- 200V put being measured. An example serves to illustrate the effect of supply noise on the Figure 32. Unipolar Buffered Voltage Output analog supply. Suppose a switching regulator with a switching frequency of 250 kHz produces 10 mV rms of noise and, for POWER AND GROUNDING CONSIDERATIONS, POWER simplicity sake (i.e., ignore harmonics), all of this noise is con- SUPPLY REJECTION centrated at 250 kHz. To calculate how much of this undesired Many applications seek high speed and high performance under noise will appear as current noise superimposed on the DAC’s less than ideal operating conditions. In these circuits, the imple- full-scale current, I , one must determine the PSRR in dB OUTFS mentation and construction of the printed circuit board design using Figure 33 at 250 kHz. To calculate the PSRR for a given are as important as the circuit design. To ensure optimum per- R , such that the units of PSRR are converted from A/V to LOAD formance, proper RF techniques must be used for device selec- V/V, adjust the curve in Figure 33 by the scaling factor 20 · tion, placement and routing as well as power supply bypassing Log (R ). For instance, if R is 50 W, the PSRR is re- LOAD LOAD and grounding. Figures 39–44 illustrate the recommended duced by 34 dB (i.e., PSRR of the DAC at 1 MHz, which is printed circuit board ground, power and signal plane layouts 74 dB in Figure 33 becomes 40 dB V /V ). OUT IN which are implemented on the AD9750 evaluation board. Proper grounding and decoupling should be a primary objective One factor that can measurably affect system performance is the in any high speed, high resolution system. The AD9750 fea- ability of the DAC output to reject dc variations or ac noise tures separate analog and digital supply and ground pins to superimposed on the analog or digital dc power distribution optimize the management of analog and digital ground currents (i.e., AVDD, DVDD). This is referred to as Power Supply in a system. In general, AVDD, the analog supply, should be Rejection Ratio (PSRR). For dc variations of the power supply, decoupled to ACOM, the analog common, as close to the chip the resulting performance of the DAC directly corresponds to a as physically possible. Similarly, DVDD, the digital supply, gain error associated with the DAC’s full-scale current, I . OUTFS should be decoupled to DCOM as close as physically as possible. AC noise on the dc supplies is common in applications where For those applications that require a single +5 V or +3 V supply the power distribution is generated by a switching power supply. for both the analog and digital supply, a clean analog supply Typically, switching power supply noise will occur over the may be generated using the circuit shown in Figure 34. The spectrum from tens of kHz to several MHz. PSRR vs. frequency circuit consists of a differential LC filter with separate power of the AD9750 AVDD supply, over this frequency range, is supply and return lines. Lower noise can be attained using low given in Figure 33. ESR type electrolytic and tantalum capacitors. 90 FERRITE BEADS AVDD TTL/CMOS LOGIC 100mF 10-22mF 0.1mF CIRCUITS ELECT. TANT. CER. 80 ACOM +5V OR +3V POWER SUPPLY 70 Figure 34. Differential LC Filter for Single +5 V or +3 V Applications Maintaining low noise on power supplies and ground is critical 60 to obtaining optimum results from the AD9750. If properly 0.26 0.5 0.75 1.0 FREQUENCY – MHz implemented, ground planes can perform a host of functions on high speed circuit boards: bypassing, shielding, current trans- Figure 33. Power Supply Rejection Ratio of AD9750 port, etc. In mixed signal design, the analog and digital portions Note that the units in Figure 33 are given in units of (amps out)/ of the board should be distinct from each other, with the analog (volts in). Noise on the analog power supply has the effect of ground plane confined to the areas covering the analog signal modulating the internal switches, and therefore the output traces, and the digital ground plane confined to areas covering current. The voltage noise on the dc power will be added in a the digital interconnects. nonlinear manner to the desired I . Due to the relatively OUT REV. 0 –15– PSRR – dB AD9750 All analog ground pins of the DAC, reference and other analog A common and traditional implementation of a QAM modu- components should be tied directly to the analog ground plane. lator is shown in Figure 35. The modulation is performed in the The two ground planes should be connected by a path 1/8 analog domain in which two DACs are used to generate the to 1/4 inch wide underneath or within 1/2 inch of the DAC to baseband I and Q components, respectively. Each component is maintain optimum performance. Care should be taken to ensure then typically applied to a Nyquist filter before being applied to that the ground plane is uninterrupted over crucial signal paths. a quadrature mixer. The matching Nyquist filters shape and On the digital side, this includes the digital input lines running limit each component’s spectral envelope while minimizing to the DAC as well as any clock signals. On the analog side, this intersymbol interference. The DAC is typically updated at the includes the DAC output signal, reference signal and the supply QAM symbol rate or possibly a multiple of it if an interpolating feeders. filter precedes the DAC. The use of an interpolating filter typi- cally eases the implementation and complexity of the analog The use of wide runs or planes in the routing of power lines is filter, which can be a significant contributor to mismatches in also recommended. This serves the dual role of providing a low gain and phase between the two baseband channels. A quadra- series impedance power supply to the part, as well as providing ture mixer modulates the I and Q components with in-phase some “free” capacitive decoupling to the appropriate ground and quadrature phase carrier frequency and then sums the two plane. It is essential that care be taken in the layout of signal and outputs to provide the QAM signal. power ground interconnects to avoid inducing extraneous volt- age drops in the signal ground paths. It is recommended that all 12 connections be short, direct and as physically close to the pack- AD9750 age as possible in order to minimize the sharing of conduction DSP 0 paths between different currents. When runs exceed an inch in CARRIER TO OR S FREQUENCY MIXER 90 ASIC length, strip line techniques with proper termination resistor 12 should be considered. The necessity and value of this resistor AD9750 will be dependent upon the logic family used. NYQUIST QUADRATURE FILTERS MODULATOR For a more detailed discussion of the implementation and construction of high speed, mixed signal printed circuit boards, Figure 35. Typical Analog QAM Architecture refer to Analog Devices’ application notes AN-280 and In this implementation, it is much more difficult to maintain AN-333. proper gain and phase matching between the I and Q channels. The circuit implementation shown in Figure 36 helps improve APPLICATIONS upon the matching and temperature stability characteristics Using the AD9750 for Quadrature Amplitude Modulation between the I and Q channels, as well as showing a path for up- (QAM) conversion using the AD8346 quadrature modulator. Using a QAM is one of the most widely used digital modulation schemes in single voltage reference derived from U1 to set the gain for both digital communication systems. This modulation technique can the I and Q channels will improve the gain matching and stabil- be found in FDM as well as spreadspectrum (i.e., CDMA) ity. R can be used to compensate for any mismatch in gain CAL based systems. A QAM signal is a carrier frequency that is between the two channels. This mismatch may be attributed to modulated in both amplitude (i.e., AM modulation) and phase the mismatch between R and R , effective load resistance SET1 SET2 (i.e., PM modulation). It can be generated by independently of each channel, and/or the voltage offset of the control ampli- modulating two carriers of identical frequency but with a 90° fier in each DAC. The differential voltage outputs of U1 and phase difference. This results in an in-phase (I) carrier compo- U2 are fed into the respective differential inputs of the AD8346 nent and a quadrature (Q) carrier component at a 90° phase via matching networks. shift with respect to the I component. The I and Q components are then summed to provide a QAM signal at the specified carrier frequency. REV. 0 –16– AD9750 +5V 1.82V 634V DVDD 100W 0.1mF 500V REFLO 500V AVDD REFIO VPBF AD9750 BBIP IOUTA 500V (“I DAC”) U1 FSADJ C DAC FILTER R SET1 2kV LATCHES + IOUTB 500V BBIN I DATA VOUT 100V INPUT AVDD CLK LOIP 500V 500V 100V PHASE AVDD REFLO SPLITTER BBQP QOUTA 500V LATCHES Q DATA LOIN U2 INPUT C FILTER DAC AD9750 500V (“Q DAC”) QOUTB BBQN 100V AD8346 REFIO FSADJ SLEEP 500mV p-p WITH R SET2 V =1.2V CM 1.9kV 0.1mF DCOM R CAL NOTE: 500V RESISTOR NETWORK - OHMTEK ORN5000D 220V 100V RESISTOR NETWORK - TOMC1603-100D ACOM Figure 36. Baseband QAM Implementation Using Two AD9750s It is also possible to generate a QAM signal completely in the AD9750 EVALUATION BOARD digital domain via a DSP or ASIC, in which case only a single General Description DAC of sufficient resolution and performance is required to The AD9750-EB is an evaluation board for the AD9750 10-bit reconstruct the QAM signal. Also available from several vendors D/A converter. Careful attention to layout and circuit design are Digital ASICs which implement other digital modulation combined with a prototyping area allow the user to easily and schemes such as PSK and FSK. This digital implementation has effectively evaluate the AD9750 in any application where high the benefit of generating perfectly matched I and Q components resolution, high speed conversion is required. in terms of gain and phase, which is essential in maintaining This board allows the user the flexibility to operate the AD9750 in optimum performance in a communication system. In this imple- various configurations. Possible output configurations include mentation, the reconstruction DAC must be operating at a transformer coupled, resistor terminated, inverting/noninverting sufficiently high clock rate to accommodate the highest specified and differential amplifier outputs. The digital inputs are designed QAM carrier frequency. Figure 37 shows a block diagram of to be driven directly from various word generators, with the such an implementation using the AD9750. on-board option to add a resistor network for proper load ter- 12 mination. Provisions are also made to operate the AD9750 12 I DATA with either the internal or external reference, or to exercise the STEL-1130 TO LPF QAM MIXER 12 power-down feature. Q DATA 50V AD9750 50V Refer to the application note AN-420 for a thorough description 12 12 and operating instructions for the AD9750 evaluation board. SIN COS 12 CARRIER STEL-1177 FREQUENCY NCO CLOCK Figure 37. Digital QAM Architecture REV. 0 –17– AD9750 Figure 38. Evaluation Board Schematic REV. 0 –18– DVDD DGND AVDD AGND AVEE AVCC B1 B2 B3 B4 B5 B6 TP19 TP3 TP4 TP6 TP7 TP2 TP18 TP5 CLK TP1 J1 C3 C4 C5 C6 JP1 A A A AB 10mF 10mF 10mF 10mF EXTCLK 3 1 2 R15 DVDD DVDD 49.9V R1 R7 R5 R3 16 PINDIP U1 AVDD TP8 1 1 1 1 RES PK C7 C8 C9 P1 1mF 0.1mF 0.1mF AD975x 2 3 4 5 6 7 8 9 10 2 3 4 5 6 7 8 9 10 2 3 4 5 6 7 8 9 10 2 3 4 5 6 7 8 9 10 2 1 C19 1 16 1 28 DB13 CLOCK A 4 3 C1 2 15 2 27 DB12 DVDD 6 5 C2 3 14 3 26 DB11 DCOM 8 7 C25 4 13 4 25 DB10 NC 10 9 C26 5 12 5 24 DB9 AVDD AVDD C27 6 12 11 11 6 23 DB8 COMP2 OUT 1 C28 14 13 7 10 7 22 DB7 IOUTA OUT 2 16 15 C29 8 9 8 21 DB6 IOUTB 18 17 20 9 DB5 ACOM 20 19 10 19 COMP1 DB4 22 21 11 18 DB3 FS ADJ 24 23 16 PINDIP 17 12 DB2 REFIO 26 25 RES PK 16 13 DB1 REFLO 28 27 14 15 DB0 SLEEP TP11 TP10 TP9 TP13 30 29 C30 1 16 32 31 A C31 2 15 R16 34 33 CT1 AVDD C32 3 14 2kV 36 35 C33 4 13 C11 C10 38 37 A TP14 C34 5 12 0.1mF 0.1mF 1 40 39 C35 6 11 C36 7 10 2 JP4 JP2 3 10 98 76 54 32 10 98 76 54 32 10 98 76 54 32 10 98 76 54 32 PDIN TP12 A A A J2 AVDD 1 1 1 1 R2 R6 R4 R8 R17 49.9V DVDD DVDD AVCC R18 1kV AVCC AVCC U7 J3 A C21 C22 R42 3 B OUT1 JP6A JP7B 0.1mF 1mF REF43 C17 JP7A 1kV U4 2 6 JP3 0.1mF VIN VOUT 2 3 J6 J7 JP8 7 A R12 C18 C16 GND 6 U6 R20 C12 1 A A OPEN AD8047 0.1mF 1mF 22pF B B B 49.9V 4 3 T1 7 2 R37 R43 4 A C20 49.9V 5kV 4 6 R10 CW 3 0 A A AD8047 A 1kV A A 2 5 R14 A A A A 4 AVEE 0 JP6B A EXTREFIN 1 R36 JP5 J5 C14 1kV R45 6 1mF 1kV 3 2 1 R13 A R9 R35 A J4 OPEN C15 A 1kV 1kV R44 C23 C24 OUT2 0.1mF 50V R46 0.1mF 1mF JP9 A A A 1kV B A C13 A R38 A 49.9V 22pF AVEE A A AD9750 Figure 39. Silkscreen Layer—Top Figure 40. Component Side PCB Layout (Layer 1) REV. 0 –19– AD9750 Figure 41. Ground Plane PCB Layout (Layer 2) Figure 42. Power Plane PCB Layout (Layer 3) REV. 0 –20– AD9750 Figure 43. Solder Side PCB Layout (Layer 4) Figure 44. Silkscreen Layer—Bottom REV. 0 –21– AD9750 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead, 300 Mil SOIC (R-28) 0.7125 (18.10) 0.6969 (17.70) 28 15 0.2992 (7.60) 0.2914 (7.40) 0.4193 (10.65) 0.3937 (10.00) 1 14 PIN 1 0.1043 (2.65) 0.0291 (0.74) 3 458 0.0926 (2.35) 0.0098 (0.25) 0.0500 (1.27) 88 0.0500 0.0192 (0.49) 0.0118 (0.30) 08 0.0157 (0.40) SEATING 0.0125 (0.32) (1.27) 0.0138 (0.35) 0.0040 (0.10) PLANE BSC 0.0091 (0.23) 28-Lead TSSOP (RU-28) 0.386 (9.80) 0.378 (9.60) 15 28 1 14 PIN 1 0.006 (0.15) 0.002 (0.05) 0.0433 (1.10) MAX 0.028 (0.70) 88 0.0118 (0.30) 0.0256 (0.65) 08 0.020 (0.50) SEATING 0.0079 (0.20) BSC 0.0075 (0.19) PLANE 0.0035 (0.090) REV. 0 –22– 0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25) PRINTED IN U.S.A. C3377–8–1/99