ANALOG DEVICES AD9748

® 8-Bit, 210 MSPS TxDAC D/A Converter AD9748 FEATURES APPLICATIONS High performance member of pin-compatible Communications TxDAC product family Direct digital synthesis (DSS) Linearity Instrumentation 0.1 LSB DNL FUNCTIONAL BLOCK DIAGRAM 0.1 LSB INL 3.3V Twos complement or straight binary data format Differential current outputs: 2 mA to 20 mA 150pF AVDD ACOM 1.2V REF Power dissipation: 135 mW @ 3.3 V 0.1μF AD9748 REFIO CURRENT Power-down mode: 15 mW @ 3.3 V SOURCE FS ADJ ARRAY On-chip 1.20 V reference R SET 3.3V DVDD IOUTA CMOS-compatible digital interface SEGMENTED LSB DCOM IOUTB SWITCHES SWITCHES 32-lead LFCSP MODE CLK+ Edge-triggered latches LATCHES CLK– CMODE Fast settling: 11 ns to 0.1% full-scale 3.3V CLKVDD CLKCOM DIGITAL DATA INPUTS (DB7–DB0) SLEEP Figure 1. GENERAL DESCRIPTION 1 Edge-triggered input latches and a 1.2 V temperature- The AD9748 is an 8-bit resolution, wideband, third generation compensated band gap reference have been integrated to member of the TxDAC series of high performance, low power provide a complete monolithic DAC solution. The digital inputs CMOS digital-to-analog converters (DACs). The TxDAC support 3 V CMOS logic families. family, consisting of pin-compatible 8-, 10-, 12-, and 14-bit DACs, is specifically optimized for the transmit signal path of communication systems. All of the devices share the same PRODUCT HIGHLIGHTS interface options, small outline package, and pinout, providing an upward or downward component selection path based on 1. 32-lead LFCSP. performance, resolution, and cost. The AD9748 offers 2. The AD9748 is the 8-bit member of the pin-compatible exceptional ac and dc performance while supporting update TxDAC family, which offers excellent INL and DNL rates up to 210 MSPS. performance. 3. Differential or single-ended clock input (LVPECL or The AD9748’s low power dissipation makes it well suited for CMOS), supports 210 MSPS conversion rate. portable and low power applications. Its power dissipation can 4. Data input supports twos complement or straight binary be further reduced to 60 mW with a slight degradation in data coding. performance by lowering the full-scale current output. In 5. Low power: Complete CMOS DAC function operates on addition, a power-down mode reduces the standby power 135 mW from a 2.7 V to 3.6 V single supply. The DAC full- dissipation to approximately 15 mW. A segmented current scale current can be reduced for lower power operation, source architecture is combined with a proprietary switching and a sleep mode is provided for low power idle periods. technique to reduce spurious components and enhance 6. On-chip voltage reference: The AD9748 includes a 1.2 V dynamic performance. temperature-compensated band gap voltage reference. 1 Protected by U.S. Patent Numbers 5568145, 5689257, and 5703519. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 03211-001 AD9748 TABLE OF CONTENTS Features .............................................................................................. 1 Applying the AD9748 ................................................................ 15 Applications....................................................................................... 1 Differential Coupling Using a Transformer............................... 15 Functional Block Diagram .............................................................. 1 Differential Coupling Using an Op Amp................................ 16 General Description ......................................................................... 1 Single-Ended, Unbuffered Voltage Output............................. 16 Product Highlights ........................................................................... 1 Single-Ended, Buffered Voltage Output Configuration........ 16 Revision History ............................................................................... 2 Power and Grounding Considerations, Power Supply Rejection...................................................................................... 17 Specifications..................................................................................... 3 Evaluation Board ............................................................................ 18 DC Specifications ......................................................................... 3 General Description................................................................... 18 Dynamic Specifications ............................................................... 4 Outline Dimensions ....................................................................... 24 Digital Specifications ................................................................... 5 Ordering Guide .......................................................................... 24 Absolute Maximum Ratings............................................................ 6 REVISION HISTORY Thermal Characteristics .............................................................. 6 12/05—Rev. 0 to Rev. A ESD Caution.................................................................................. 6 Updated Format..................................................................Universal Changes to General Description and Product Highlights ...........1 Pin Configuration and Function Descriptions............................. 7 Changes to Table 1.............................................................................3 Changes to Table 2.............................................................................4 Terminology ...................................................................................... 8 Changes to Table 4.............................................................................6 Typical Performance Characteristics ............................................. 9 Inserted Figure 7; Renumbered Sequentially.................................9 Changes to Figure 8 and Figure 9....................................................9 Functional Description .................................................................. 11 Changes to Functional Description, Reference Operation, and Reference Control Amplifier Sections......................................... 11 Reference Operation .................................................................. 11 Inserted Figure 16; Renumbered Sequentially ........................... 11 Reference Control Amplifier .................................................... 11 Changes to DAC Transfer Function Section............................... 12 Changes to Digital Inputs Section................................................ 13 DAC Transfer Function ............................................................. 12 Changes to Figure 22, Figure 23, and Figure 24 ......................... 14 Changes to Figure 25...................................................................... 15 Analog Outputs........................................................................... 12 Changes to Figure 26, Figure 27, Figure 28, and Figure 29....... 16 Digital Inputs .............................................................................. 13 Updated Outline Dimensions....................................................... 24 Changes to Ordering Guide .......................................................... 24 Clock Input.................................................................................. 13 2/03—Revision 0: Initial Version DAC Timing................................................................................ 14 Power Dissipation....................................................................... 14 Rev. A | Page 2 of 24 AD9748 SPECIFICATIONS DC SPECIFICATIONS T to T , AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, I = 20 mA, unless otherwise noted. MIN MAX OUTFS Table 1. Parameter Min Typ Max Unit RESOLUTION 8 Bits 1 DC ACCURACY Integral Linearity Error (INL) ±0.25 ±0.1 +0.25 LSB Differential Nonlinearity (DNL) ±0.25 ±0.1 +0.25 LSB ANALOG OUTPUT Offset Error −0.02 +0.02 % of FSR Gain Error (Without Internal Reference) −0.5 ±0.1 +0.5 % of FSR Gain Error (With Internal Reference) −0.5 ±0.1 +0.5 % of FSR 2 Full-Scale Output Current 2.0 20.0 mA Output Compliance Range −1.0 +1.25 V Output Resistance 100 kΩ Output Capacitance 5 pF REFERENCE OUTPUT Reference Voltage 1.14 1.20 1.26 V 3 Reference Output Current 100 nA REFERENCE INPUT Input Compliance Range 0.1 1.25 V Reference Input Resistance (External Reference) 7 kΩ Small Signal Bandwidth 0.5 MHz TEMPERATURE COEFFICIENTS Offset Drift 0 ppm of FSR/°C Gain Drift (Without Internal Reference) ±50 ppm of FSR/°C Gain Drift (With Internal Reference) ±100 ppm of FSR/°C Reference Voltage Drift ±50 ppm/°C POWER SUPPLY Supply Voltages AVDD 2.7 3.3 3.6 V DVDD 2.7 3.3 3.6 V CLKVDD 2.7 3.3 3.6 V Analog Supply Current (I ) 33 36 mA AVDD 4 Digital Supply Current (I ) 8 9 mA DVDD Clock Supply Current (I ) 5 7 mA CLKVDD Supply Current Sleep Mode (IAVDD) 5 6 mA 4 Power Dissipation 135 145 mW 5 Power Dissipation 145 mW 6 Power Supply Rejection Ratio—AVDD −1 +1 % of FSR/V 6 Power Supply Rejection Ratio—DVDD −0.04 +0.04 % of FSR/V OPERATING RANGE −40 +85 °C 1 Measured at IOUTA, driving a virtual ground. 2 Nominal full-scale current, I , is 32 times the I current. OUTFS REF 3 An external buffer amplifier with input bias current <100 nA should be used to drive any external load. 4 Measured at f = 100 MSPS and f = 1 MHz. CLOCK OUT 5 Measured as unbuffered voltage output with IOUTFS = 20 mA, 50 Ω RLOAD at IOUTA and IOUTB, fCLOCK = 100 MSPS, and fOUT = 40 MHz. 6 ±5% power supply variation. Rev. A | Page 3 of 24 AD9748 DYNAMIC SPECIFICATIONS TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, IOUTFS = 20 mA, differential transformer coupled output, 50 Ω doubly terminated, unless otherwise noted. Table 2. Parameter Min Typ Max Unit DYNAMIC PERFORMANCE Maximum Output Update Rate (fCLOCK) 210 MSPS 1 Output Settling Time (tST) (to 0.1%) 11 ns Output Propagation Delay (t ) 1 ns PD Glitch Impulse 5 pV-s 1 Output Rise Time (10% to 90%) 2.5 ns 1 Output Fall Time (10% to 90%) 2.5 ns 2 Output Noise (IOUTFS = 20 mA) 50 pA/√Hz 2 Output Noise (I = 2 mA) 30 pA/√Hz OUTFS AC LINEARITY Signal-to-Noise and Distortion Ratio f = 50 MSPS; f = 5 MHz 50 dB CLOCK OUT f = 50 MSPS; f = 19 MHz 48 dB CLOCK OUT f = 100 MSPS; f = 5 MHz 50 dB CLOCK OUT fCLOCK = 100 MSPS; fOUT = 39 MHz 46 dB fCLOCK = 165 MSPS; fOUT = 5 MHz 50 dB fCLOCK = 165 MSPS; fOUT = 49 MHz 47 dB f = 210 MSPS; f = 9 MHz 50 dB CLOCK OUT f = 210 MSPS; f = 68 MHz 46 dB CLOCK OUT Total Harmonic Distortion fCLOCK = 25 MSPS; fOUT = 1 MHz −72 −61 dBc fCLOCK = 50 MSPS; fOUT = 12.5 MHz −65 dBc f = 100 MSPS; f = 25 MHz −60 dBc CLOCK OUT f = 165 MSPS; f = 41.3 MHz −58 dBc CLOCK OUT f = 210 MSPS; f = 68 MHz −65 dBc CLOCK OUT Spurious-Free Dynamic Range to Nyquist fCLOCK = 25 MSPS; fOUT = 1 MHz 0 dBFS Output 61 72 dBc f = 65 MSPS; f = 5 MHz 69 dBc CLOCK OUT f = 65 MSPS; f = 19 MHz 65 dBc CLOCK OUT f = 100 MSPS; f = 5 MHz 68 dBc CLOCK OUT fCLOCK = 100 MSPS; fOUT = 39 MHz 62 dBc fCLOCK = 165 MSPS; fOUT = 5 MHz 68 dBc fCLOCK = 165 MSPS; fOUT = 49 MHz 54 dBc f = 210 MSPS; f = 5 MHz 67 dBc CLOCK OUT f = 210 MSPS; f = 68 MHz 60 dBc CLOCK OUT 1 Measured single-ended into 50 Ω load. 2 Output noise is measured with a full-scale output set to 20 mA with no conversion activity. It is a measure of the thermal noise only. Rev. A | Page 4 of 24 AD9748 DIGITAL SPECIFICATIONS TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, IOUTFS = 20 mA, unless otherwise noted. Table 3. Parameter Min Typ Max Unit DIGITAL INPUTS Logic 1 Voltage 2.1 3 V Logic 0 Voltage 0 0.9 V Logic 1 Current −10 +10 μA Logic 0 Current −10 +10 μA Input Capacitance 5 pF Input Setup Time (tS) 2.0 ns Input Hold Time (tH) 1.5 ns Latch Pulse Width (tLPW) 1.5 ns 1 CLK INPUTS Input Voltage Range 0 3 V Common-Mode Voltage 0.75 1.5 2.25 V Differential Voltage 0.5 1.5 V 1 Applicable to CLK+ and CLK− inputs when configured for differential or PECL clock input mode. DB0–DB7 t t S H CLOCK t LPW t PD t ST IOUTA 0.1% OR 0.1% IOUTB Figure 2. Timing Diagram Rev. A | Page 5 of 24 03211-002 AD9748 ABSOLUTE MAXIMUM RATINGS Table 4. 1 THERMAL CHARACTERISTICS With Thermal Resistance Respect 32-Lead LFCSP Parameter to Min Max Unit θJA = 32.5°C/W AVDD ACOM −0.3 +3.9 V 1 DVDD DCOM −0.3 +3.9 V Thermal impedance measurements were taken on a 4-layer board in still air, in accordance with EIA/JESD51-7. CLKVDD CLKCOM −0.3 +3.9 V ACOM DCOM −0.3 +0.3 V ACOM CLKCOM −0.3 +0.3 V DCOM CLKCOM −0.3 +0.3 V AVDD DVDD −3.9 +3.9 V AVDD CLKVDD −3.9 +3.9 V DVDD CLKVDD −3.9 +3.9 V CLK+, CLK−, SLEEP DCOM −0.3 DVDD + 0.3 V Digital Inputs, MODE DCOM −0.3 DVDD + 0.3 V IOUTA, IOUTB ACOM −1.0 AVDD + 0.3 V REFIO, FS ADJ ACOM −0.3 AVDD + 0.3 V CLK+, CLK−, MODE CLKCOM −0.3 CLKVDD + 0.3 V Junction Temperature 150 °C Storage Temperature −65 +150 °C Range Lead Temperature 300 °C (10 sec) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may effect device reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. A | Page 6 of 24 AD9748 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DB1 1 24 FS ADJ PIN 1 (LSB) DB0 2 23 REFIO INDICATOR DVDD 3 22 ACOM NC 4 21 IOUTA AD9748 NC 5 20 IOUTB TOP VIEW NC 6 (Not to Scale) 19 ACOM NC 7 18 AVDD NC 8 17 AVDD NC = NO CONNECT Figure 3. Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Description 27 DB7 (MSB) Most Significant Data Bit (MSB). 28 to 32, 1 DB6 to DB1 Data Bits 6 to 1. 2 DB0 (LSB) Least Significant Data Bit (LSB). 3 DVDD Digital Supply Voltage (3.3 V). 4 to 9 NC No Internal Connection. 10, 26 DCOM Digital Common. 11 CLKVDD Clock Supply Voltage (3.3 V). 12 CLK+ Differential Clock Input. 13 CLK− Differential Clock Input. 14 CLKCOM Clock Common. 15 CMODE Clock Mode Selection. Connect to CLKCOM for single-ended clock receiver (drive CLK+ and float CLK–). Connect to CLKVDD for differential receiver. Float for PECL receiver (terminations on-chip). 16 MODE Selects Input Data Format. Connect to DCOM for straight binary, DVDD for twos complement. 17, 18 AVDD Analog Supply Voltage (3.3 V). 19, 22 ACOM Analog Common. 20 IOUTB Complementary DAC Current Output. Full-scale current when all data bits are 0s. 21 IOUTA DAC Current Output. Full-scale current when all data bits are 1s. 23 REFIO Reference Input/Output. Requires 0.1 μF capacitor to ACOM. 24 FS ADJ Full-Scale Current Output Adjust. 25 SLEEP Power-Down Control Input. Active high. Contains active pull-down circuit; it can be left unterminated if not used. Rev. A | Page 7 of 24 03211-003 NC 9 32 DB2 DCOM 10 31 DB3 CLKVDD 11 30 DB4 CLK+ 12 29 DB5 CLK– 13 28 DB6 CLKCOM 14 27 DB7 (MSB) CMODE 15 26 DCOM MODE 16 25 SLEEP AD9748 TERMINOLOGY Linearity Error (Also Called Integral Nonlinearity or INL) Power Supply Rejection Linearity error is defined as the maximum deviation of the The maximum change in the full-scale output as the supplies actual analog output from the ideal output, determined by a are varied from nominal to minimum and maximum specified straight line drawn from zero to full scale. voltages. Differential Nonlinearity (or DNL) Settling Time DNL is the measure of the variation in analog value, normalized The time required for the output to reach and remain within a to full scale, associated with a 1 LSB change in digital input code. specified error band about its final value, measured from the start of the output transition. Monotonicity A DAC is monotonic if the output increases or remains constant Glitch Impulse as the digital input increases. Asymmetrical switching times in a DAC give rise to undesired output transients that are quantified by a glitch impulse. It is Offset Error specified as the net area of the glitch in pV-s. The deviation of the output current from the ideal of zero is called the offset error. For IOUTA, 0 mA output is expected Spurious-Free Dynamic Range when the inputs are all 0s. For IOUTB, 0 mA output is expected The difference, in dB, between the rms amplitude of the output when all inputs are set to 1s. signal and the peak spurious signal over the specified bandwidth. Gain Error The difference between the actual and ideal output span. The TTotal Harmonic Distortion (THD) actual span is determined by the output when all inputs are set THD is the ratio of the rms sum of the first six harmonic to 1s minus the output when all inputs are set to 0s. components to the rms value of the measured input signal. It is expressed as a percentage or in decibels (dB). Output Compliance Range The range of allowable voltage at the output of a current output Multitone Power Ratio DAC. Operation beyond the maximum compliance limits can The spurious-free dynamic range containing multiple carrier cause either output stage saturation or breakdown, resulting in tones of equal amplitude. It is measured as the difference nonlinear performance. between the rms amplitude of a carrier tone to the peak spurious signal in the region of a removed tone. Temperature Drift Temperature drift is specified as the maximum change from the ambient (25°C) value to the value at either TMIN or TMAX. For offset and gain drift, the drift is reported in ppm of full-scale range (FSR) per °C. For reference drift, the drift is reported in ppm per °C. 3.3V AVDD ACOM 150pF 1.2V REF 0.1μF AD9748 REFIO CURRENT SOURCE MINI-CIRCUITS FS ADJ ARRAY T1-1T *AWG2021 CLOCK R ROHDE & SCHWARZ SET 3.3V DVDD IOUTA RETIMED SO THAT FSEA30 SEGMENTED LSB THE DIGITAL DATA DCOM SPECTRUM IOUTB 100Ω SWITCHES SWITCHES TRANSITIONS ON ANALYZER FALLING EDGE OF CLK+ MODE 50% DUTY CYCLE LATCHES CLK– CLOCK. 50Ω 50Ω 20pF 3.3V CLKVDD CMODE CLKCOM 20pF 50Ω DVDD DIGITAL DATA INPUTS (DB7–DB0) DCOM SLEEP RETIMED CLOCK DIGITAL OUTPUT* DATA CLOCK OUTPUT LECROY 9210 TEKTRONIX AWG-2021 PULSE GENERATOR WITH OPTION 4 Figure 4. Basic AC Characterization Test Setup (SOIC/TSSOP Packages) Rev. A | Page 8 of 24 03211-004 AD9748 TYPICAL PERFORMANCE CHARACTERISTICS 80 55 5mA THD@50MSPS 75 THD@100MSPS 50 70 THD@165MSPS 10mA 2.5mA 65 20mA THD@210MSPS 40 60 45 55 SINAD@165MSPS 50 35 SINAD@50MSPS 45 SINAD@100MSPS SINAD@210MSPS 40 30 1 10 100 1 10 100 f (MHz) OUT f (MHz) OUT Figure 5. SINAD vs. I @ 100 MSPS (Single-Ended Output) Figure 8. SINAD/THD vs. fOUT (Single-Ended Output) OUTFS 80 55 10mA THD@165MSPS 20mA 75 50 THD@210MSPS 70 5mA 65 THD@50MSPS 40 2.5mA 60 THD@100MSPS 45 55 SINAD@165MSPS 50 SINAD@50MSPS 35 45 SINAD@100MSPS SINAD@210MSPS 40 30 1 10 100 1 10 100 f (MHz) OUT f (MHz) OUT Figure 6. SINAD vs. IOUTFS @ 165 MSPS (Single-Ended Output) Figure 9. SINAD/THD vs. f (Differential Output) OUT 55 0 5mA f = 25MSPS CLOCK 20mA –10 f = 7.81MHz OUT 10mA SFDR = 65.0dBc 50 –20 AMPLITUDE = 0dBFS –30 2.5mA 40 –40 –50 45 –60 –70 35 –80 –90 30 –100 1 10 100 02 4 6 8 10 12 f (MHz) FREQUENCY (MHz) OUT Figure 7. SINAD vs. I @ 210 MSPS (Single-Ended Output) OUTFS Figure 10. Single-Tone Spectral Plot @ 25 MSPS (Single-Ended Output) Rev. A | Page 9 of 24 SINAD (dB) SINAD (dB) SINAD (dB) 03211-038 03211-006 03211-005 MAGNITUDE (dBm) SINAD/THD (dB) SINAD/THD (dB) 03211-039 03211-040 03211-009 AD9748 0 f = 125MSPS CLOCK –10 f = 27MHz OUT SFDR = 56.2dBc –20 AMPLITUDE = 0dBFS –30 –40 –50 –60 –70 –80 –90 –100 0 10 2030 40 5060 5ns/DIV FREQUENCY (MHz) Figure 11. Single-Tone Spectral Plot @ 125 MSPS (Single-Ended Output) Figure 13. Step Response (Single-Ended Output) 0 0 f = 165MSPS CLOCK f = 210MSPS CLOCK –10 –10 f = 49MHz f = 68MHz OUT OUT SFDR = 50.1dBc SFDR = 50dBc –20 –20 AMPLITUDE = 0dBFS AMPLITUDE = 0dBFS –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 0 10.5 105 –100 010 20 30 40 50 60 70 80 FREQUENCY (MHz) FREQUENCY (MHz) Figure 14. Single-Tone Spectral Plot @ 210 MSPS (Single-Ended Output) Figure 12. Single-Tone Spectral Plot @ 165 MSPS (Single-Ended Output) 3.3V AVDD ACOM 150pF 1.2V REF 0.1μF AD9748 REFIO CURRENT V = V = V SOURCE FS ADJ DIFF OUTA OUTB ARRAY R SET 3.3V DVDD IOUTA SEGMENTED LSB R IOUTB DCOM LOAD SWITCHES SWITCHES 50Ω R LOAD 50Ω MODE CLK+ LATCHES CMODE CLK– 3.3V CLKVDD CLKCOM DIGITAL DATA INPUTS (DB7–DB0) SLEEP Figure 15. Simplified Block Diagram Rev. A | Page 10 of 24 MAGNITUDE (dBm) MAGNITUDE (dBm) 03211-011 03211-010 50mV/DIV MAGNITUDE (dBm) 03211-013 03211-043 03211-012 AD9748 FUNCTIONAL DESCRIPTION current of less than 100 nA should be used. An example of the Figure 15 shows a simplified block diagram of the AD9748. The use of the internal reference is shown in Figure 17. AD9748 consists of a DAC, digital control logic, and full-scale output current control. The DAC contains a PMOS current AVDD source array capable of providing up to 20 mA of full-scale 84µA current (I ). The array is divided into 31 equal currents that OUTFS REFIO make up the five most significant bits (MSBs). The next three 7k bits consist of seven equal current sources whose value is ⅛ of an MSB current source. Implementing the lower bits with current sources, instead of an R-2R ladder, enhances its REFLO dynamic performance for multitone or low amplitude signals Figure 16. Equivalent Circuit of Internal Reference and helps maintain the DAC’s high output impedance (that is, 3.3V >100 kΩ). OPTIONAL EXTERNAL REF BUFFER All of these current sources are switched to one or the other of AVDD REFLO 150pF the two output nodes (that is, IOUTA or IOUTB) via PMOS 1.2V REF differential current switches. The switches are based on the REFIO CURRENT ADDITIONAL FS ADJ SOURCE architecture that was pioneered in the AD9764 family, with LOAD 0.1μF ARRAY further refinements to reduce distortion contributed by the 2kΩ AD9748 switching transient. This switch architecture also reduces various timing errors and provides matching complementary Figure 17. Internal Reference Configuration drive signals to the inputs of the differential current switches. An external reference can be applied to REFIO, as shown in The analog and digital sections of the AD9748 have separate Figure 18. The external reference can provide either a fixed power supply inputs (that is, AVDD and DVDD) that can reference voltage to enhance accuracy and drift performance or operate independently over a 2.7 V to 3.6 V range. The digital a varying reference voltage for gain control. Note that the 0.1 μF section, which is capable of operating at a rate of up to 210 MSPS, compensation capacitor is not required because the internal consists of edge-triggered latches and segment decoding logic reference is overridden, and the relatively high input impedance of circuitry. The analog section includes the PMOS current sources, REFIO minimizes any loading of the external reference. the associated differential switches, a 1.2 V band gap voltage reference, and a reference control amplifier. 3.3V The DAC full-scale output current is regulated by the reference control amplifier and can be set from 2 mA to 20 mA via an REFLO 150pF AVDD external resistor, R , connected to the full-scale adjust (FS ADJ) SET 1.2V REF pin. The external resistor, in combination with both the reference REFIO control amplifier and voltage reference, VREFIO, sets the reference CURRENT SOURCE FS ADJ current, IREF, which is replicated to the segmented current ARRAY sources with the proper scaling factor. The full-scale current, REFERENCE I , is 32 times I . OUTFS REF AD9748 CONTROL AMPLIFIER REFERENCE OPERATION Figure 18. External Reference Configuration The AD9748 contains an internal 1.2 V band gap reference. The internal reference cannot be disabled but can be easily overridden REFERENCE CONTROL AMPLIFIER by an external reference with no effect on performance. Figure 16 The AD9748 contains a control amplifier that is used to regulate shows an equivalent circuit of the band gap reference. REFIO the full-scale output current, IOUTFS. The control amplifier is serves as either an output or an input depending on whether the configured as a V-I converter, as shown in Figure 17, so that its internal or an external reference is used. To use the internal current output, I , is determined by the ratio of the V and REF REFIO reference, simply decouple the REFIO pin to ACOM with a an external resistor, R , as stated in Equation 4. I is copied SET REF 0.1 μF capacitor and connect REFLO to ACOM via a resistance to the segmented current sources with the proper scale factor to less than 5 Ω. The internal reference voltage are present at set I , as stated in Equation 3. OUTFS REFIO. If the voltage at REFIO is to be used anywhere else in the circuit, than an external buffer amplifier with an input bias Rev. A | Page 11 of 24 03211-044 03211-046 03211-045 AD9748 The control amplifier allows a wide (10:1) adjustment span of Substituting the values of IOUTA, IOUTB, I , and V can be REF DIFF I over a 2 mA to 20 mA range by setting I between 62.5 expressed as: OUTFS REF μA and 625 μA. The wide adjustment span of I provides OUTFS V = {(2 × DAC CODE − 255)/256} DIFF several benefits. The first relates directly to the power (32 × RLOAD/RSET) × VREFIO (8) dissipation of the AD9748, which is proportional to IOUTFS (see the Power Dissipation section). The second relates to a 20 dB Equation 7 and Equation 8 highlight some of the advantages of adjustment, which is useful for system gain control purposes. operating the AD9748 differentially. First, the differential operation helps cancel common-mode error sources associated The small signal bandwidth of the reference control amplifier is with IOUTA and IOUTB, such as noise, distortion, and dc approximately 500 kHz and can be used for low frequency small offsets. Second, the differential code dependent current and signal multiplying applications. subsequent voltage, V , is twice the value of the single-ended DIFF voltage output (that is, V or V ), thus providing twice the OUTA OUTB DAC TRANSFER FUNCTION signal power to the load. The AD9748 provides complementary current outputs, IOUTA and IOUTB. IOUTA provides a near full-scale current output, Note that the gain drift temperature performance for a single- I , when all bits are high (that is, DAC CODE = 255), while OUTFS ended (VOUTA and VOUTBB) or differential output (VDIFF) of the IOUTB, the complementary output, provides no current. The AD9748 can be enhanced by selecting temperature tracking current output appearing at IOUTA and IOUTB is a function of resistors for R and R due to their ratiometric relationship, LOAD SET both the input code and IOUTFS and can be expressed as: as shown in Equation 8. IOUTA = (DAC CODE/256) × IOUTFS (1) ANALOG OUTPUTS IOUTB = (255 − DAC CODE)/256 × IOUTFS (2) The complementary current outputs in each DAC, IOUTA, and IOUTB can be configured for single-ended or differential where DAC CODE = 0 to 255 (that is, decimal representation). operation. IOUTA and IOUTB can be converted into As mentioned previously, I is a function of the reference complementary single-ended voltage outputs, V and V , OUTFS OUTA OUTB current I , which is nominally set by a reference voltage, REF via a load resistor, RLOAD, as described in the DAC Transfer V , and external resistor, R . It can be expressed as: REFIO SET Function section by Equation 5 through Equation 8. The differential voltage, VDIFF, existing between VOUTA and VOUTB, can IOUTFS = 32 × IREF (3) also be converted to a single-ended voltage via a transformer or where differential amplifier configuration. The ac performance IREF = VREFIO/RSET (4) of the AD9748 is optimum and specified using a differential transformer-coupled output in which the voltage swing at The two current outputs typically drive a resistive load directly IOUTA and IOUTB is limited to ±0.5 V. or via a transformer. If dc coupling is required, then IOUTA and IOUTB should be directly connected to matching resistive The distortion and noise performance of the AD9748 can be loads, RLOAD, that are tied to analog common, ACOM. Note enhanced when it is configured for differential operation. The that RLOAD can represent the equivalent load resistance seen by common-mode error sources of both IOUTA and IOUTB can IOUTA or IOUTB as would be the case in a doubly terminated be significantly reduced by the common-mode rejection of a 50 Ω or 75 Ω cable. The single-ended voltage output appearing transformer or differential amplifier. These common-mode at the IOUTA and IOUTB nodes is simply error sources include even-order distortion products and noise. V = IOUTA × R (5) The enhancement in distortion performance becomes more OUTA LOAD significant as the frequency content of the reconstructed V = IOUTB × R (6) OUTB LOAD waveform increases and/or its amplitude decreases. This is due Note that the full-scale value of V and V should not OUTA OUTB to the first-order cancellation of various dynamic common- exceed the specified output compliance range to maintain mode distortion mechanisms, digital feedthrough, and noise. specified distortion and linearity performance. Performing a differential-to-single-ended conversion via a VDIFF = (IOUTA − IOUTB) × RLOAD (7) transformer also provides the ability to deliver twice the reconstructed signal power to the load (assuming no source termination). Because the output currents of IOUTA and IOUTB are complementary, they become additive when processed differentially. A properly selected transformer allows the AD9748 to provide the required power and voltage levels to different loads. Rev. A | Page 12 of 24 AD9748 The output impedance of IOUTA and IOUTB is determined CLOCK INPUT by the equivalent parallel combination of the PMOS switches A configurable clock input allows for one single-ended and two associated with the current sources and is typically 100 kΩ in differential modes. The mode selection is controlled by the parallel with 5 pF. It is also slightly dependent on the output CMODE input, as summarized in Table 6. Connecting CMODE voltage (that is, VOUTA and VOUTB) due to the nature of a PMOS to CLKCOM selects the single-ended clock input. In this mode, device. As a result, maintaining IOUTA and/or IOUTB at a the CLK+ input is driven with rail-to-rail swings and the CLK− virtual ground via an I-V op amp configuration results in the input is left floating. If CMODE is connected to CLKVDD, then optimum dc linearity. Note that the INL/DNL specifications for the differential receiver mode is selected. In this mode, both the AD9748 are measured with IOUTA maintained at a virtual inputs are high impedance. The final mode is selected by ground via an op amp. floating CMODE. This mode is also differential, but internal terminations for positive emitter-coupled logic (PECL) are IOUTA and IOUTB also have a negative and positive voltage activated. There is no significant performance difference compliance range that must be adhered to in order to achieve between any of the three clock input modes. optimum performance. The negative output compliance range of −1 V is set by the breakdown limits of the CMOS process. Table 6. Clock Mode Selection Operation beyond this maximum limit can result in a breakdown CMODE Pin Clock Input Mode of the output stage and affect the reliability of the AD9748. CLKCOM Single-ended CLKVDD Differential The positive output compliance range is slightly dependent on Float PECL the full-scale output current, I . It degrades slightly from its OUTFS In the single-ended input mode, the CLK+ pin must be driven nominal 1.2 V for an IOUTFS = 20 mA to 1 V for an IOUTFS = 2 mA. with rail-to-rail CMOS levels. The quality of the DAC output is The optimum distortion performance for a single-ended or directly related to the clock quality, and jitter is a key concern. differential output is achieved when the maximum full-scale Any noise or jitter in the clock translates directly into the DAC signal at IOUTA and IOUTB does not exceed 0.5 V. output. Optimal performance is achieved if the clock input has DIGITAL INPUTS a sharp rising edge, because the DAC latches are positive edge triggered. The AD9748 digital section consists of eight input bit channels and a clock input. The 8-bit parallel data inputs follow standard In the differential input mode, the clock input functions as a positive binary coding, where DB7 is the most significant bit high impedance differential pair. The common-mode level of (MSB) and DB0 is the least significant bit (LSB). IOUTA the CLK+ and CLK− inputs can vary from 0.75 V to 2.25 V, and produces a full-scale output current when all data bits are at the differential voltage can be as low as 0.5 V p-p. This mode Logic 1. IOUTB produces a complementary output with the can be used to drive the clock with a differential sine wave, full-scale current split between the two outputs as a function of because the high gain bandwidth of the differential inputs the input code. convert the sine wave into a single-ended square wave DVDD internally. The final clock mode allows for a reduced external component DIGITAL count when the DAC clock is distributed on the board using INPUT PECL logic. The internal termination configuration is shown in Figure 20. These termination resistors are untrimmed and can vary up to ±20%. However, matching between the resistors should generally be better than ±1%. Figure 19. Equivalent Digital Input The digital interface is implemented using an edge-triggered AD9748 master/slave latch. The DAC output updates on the rising edge CLK+ CLOCK of the clock and is designed to support a clock rate as high as TO DAC CORE CLK– RECEIVER 210 MSPS. The clock can be operated at any duty cycle that 50Ω 50Ω meets the specified latch pulse width. The setup and hold times can also be varied within the clock cycle as long as the specified V = 1.3V NOM TT minimum times are met, although the location of these transition edges can affect digital feedthrough and distortion Figure 20. Clock Termination in PECL Mode performance. Best performance is typically achieved when the input data transitions on the falling edge of a 50% duty cycle clock. Rev. A | Page 13 of 24 03211-016 03211-017 AD9748 Conversely, I is dependent on both the digital input DAC TIMING DVDD waveform, f , and digital supply DVDD. Figure 23 shows I CLOCK DVDD Input Clock and Data Timing Relationship as a function of full-scale sine wave output ratios (f /f ) OUT CLOCK Dynamic performance in a DAC is dependent on the for various update rates with DVDD = 3.3 V. relationship between the position of the clock edges and the 35 time at which the input data changes. The AD9748 is rising edge triggered, and so exhibits dynamic performance sensitivity 30 when the data transition is close to this edge. In general, the goal when applying the AD9748 is to make the data transition 25 close to the falling clock edge. This becomes more important as the sample rate increases. Figure 21 shows the relationship of 20 SFDR to clock placement with different sample rates. Note that at the lower sample rates, more tolerance is allowed in clock 15 placement, while at higher rates, more care must be taken. 80 10 75 20MHz SFDR 0 70 2 4 6 8 101214 161820 I (mA) 65 OUTFS 60 Figure 22. I vs. I AVDD OUTFS 55 20 50MHz SFDR 50 18 210MSPS 45 16 40 14 165MSPS 35 12 30 10 125MSPS 02 4 6 8 10 12 CLOCK PLACEMENT (ns) 8 Figure 21. SFDR vs. Clock Placement @ fOUT = 20 MHz and 50 MHz 6 (fCLOCK = 165 MSPS) 65MSPS 4 Sleep Mode Operation 2 The AD9748 has a power-down function that turns off the output 0 0.01 0.1 1 current and reduces the supply current to less than 6 mA over the RATIO (f /f ) OUT CLOCK specified supply range of 2.7 V to 3.6 V and the temperature range. Figure 23. IDVDD vs. Ratio @ DVDD = 3.3 V This mode can be activated by applying a Logic Level 1 to the SLEEP pin. The SLEEP pin logic threshold is equal to 0.5 Ω 11 AVDD. This digital input also contains an active pull-down 10 circuit that ensures that the AD9748 remains enabled if this 9 DIFF input is left disconnected. The AD9748 takes less than 50 ns to 8 power down and approximately 5 μs to power back up. 7 POWER DISSIPATION 6 PECL 5 The power dissipation, PD, of the AD9748 is dependent on SE 4 several factors that include the: 3 • Power supply voltages (AVDD, CLKVDD, and DVDD) 2 • Full-scale current output (IOUTFS) 1 • Update rate (fCLOCK) 0 • Reconstructed digital input waveform 0 50 100 150 200 250 f (MSPS) CLOCK The power dissipation is directly proportional to the analog Figure 24. I vs. f and Clock Mode CLKVDD CLOCK supply current, IAVDD, and the digital supply current, IDVDD. IAVDD is directly proportional to I , as shown in Figure 22, and is OUTFS insensitive to f . CLOCK Rev. A | Page 14 of 24 SFDR (dB) 03211-018 I (mA) CLKVDD I (mA) AVDD I (mA) DVDD 03211-041 03211-019 03211-042 AD9748 APPLYING THE AD9748 DIFFERENTIAL COUPLING USING A TRANSFORMER Output Configurations An RF transformer can be used to perform a differential-to- The following sections illustrate some typical output single-ended signal conversion, as shown in Figure 25. A configurations for the AD9748. Unless otherwise noted, it is differentially coupled transformer output provides the optimum assumed that I is set to a nominal 20 mA. For applications OUTFS distortion performance for output signals whose spectral requiring the optimum dynamic performance, a differential content lies within the transformer’s pass band. An RF transformer, output configuration is suggested. A differential output such as the Mini-Circuits® T1–1T, provides excellent rejection of configuration can consist of either an RF transformer or a common-mode distortion (that is, even-order harmonics) and differential op amp configuration. The transformer configuration noise over a wide frequency range. It also provides electrical provides the optimum high frequency performance and is isolation and the ability to deliver twice the power to the load. recommended for any application that allows ac coupling. The Transformers with different impedance ratios can also be used differential op amp configuration is suitable for applications for impedance matching purposes. Note that the transformer requiring dc coupling, bipolar output, signal gain, and/or provides ac coupling only. level shifting within the bandwidth of the chosen op amp. MINI-CIRCUITS T1-1T IOUTA A single-ended output is suitable for applications requiring a unipolar voltage output. A positive unipolar output voltage R AD9748 LOAD results if IOUTA and/or IOUTB is connected to an appropriately IOUTB sized load resistor, R , referred to ACOM. This configuration LOAD OPTIONAL R DIFF can be more suitable for a single-supply system requiring a dc- Figure 25. Differential Output Using a Transformer coupled, ground referred output voltage. Alternatively, an amplifier could be configured as an I-V converter, thus The center tap on the primary side of the transformer must be converting IOUTA or IOUTB into a negative unipolar voltage. connected to ACOM to provide the necessary dc current path This configuration provides the best dc linearity because for both IOUTA and IOUTB. The complementary voltages IOUTA or IOUTB is maintained at a virtual ground. appearing at IOUTA and IOUTB (that is, V and V ) OUTA OUTBB swing symmetrically around ACOM and should be maintained with the specified output compliance range of the AD9748. A differential resistor, RDIFF, can be inserted in applications where the output of the transformer is connected to the load, RLOAD, via a passive reconstruction filter or cable. RDIFF is determined by the transformer’s impedance ratio and provides the proper source termination that results in a low VSWR. Note that approximately half the signal power is dissipated across R . DIFF Rev. A | Page 15 of 24 03211-022 AD9748 SINGLE-ENDED, UNBUFFERED VOLTAGE OUTPUT DIFFERENTIAL COUPLING USING AN OP AMP Figure 28 shows the AD9748 configured to provide a unipolar An op amp can also be used to perform a differential-to-single- output range of approximately 0 V to 0.5 V for a doubly ended conversion, as shown in Figure 26. The AD9748 is terminated 50 Ω cable because the nominal full-scale current, configured with two equal load resistors, RLOAD, of 25 Ω. The I , of 20 mA flows through the equivalent R of 25 Ω. OUTFS LOAD differential voltage developed across IOUTA and IOUTB is In this case, R represents the equivalent load resistance seen LOAD converted to a single-ended signal via the differential op amp by IOUTA or IOUTB. The unused output (IOUTA or IOUTB) configuration. An optional capacitor can be installed across can be connected to ACOM directly or via a matching RLOAD. IOUTA and IOUTB, forming a real pole in a low-pass filter. The Different values of IOUTFS and RLOAD can be selected as long as addition of this capacitor also enhances the op amp’s distortion the positive compliance range is adhered to. One additional performance by preventing the DAC’s high slewing output from consideration in this mode is the integral nonlinearity (INL), overloading the op amp’s input. discussed in the Analog Outputs section. For optimum INL 500Ω performance, the single-ended, buffered voltage output AD9748 configuration is suggested. 225Ω IOUTA AD8047 225Ω I = 20mA OUTFS AD9748 V =0V TO0.5V IOUTB OUTA C IOUTA OPT 500Ω 50Ω 50Ω 25Ω 25Ω IOUTB 25Ω Figure 26. DC Differential Coupling Using an Op Amp Figure 28. 0 V to 0.5 V Unbuffered Voltage Output The common-mode rejection of this configuration is typically SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT determined by the resistor matching. In this circuit, the differential CONFIGURATION op amp circuit using the AD8047 is configured to provide some additional signal gain. The op amp must operate off a dual Figure 29 shows a buffered single-ended output configuration supply because its output is approximately ±1 V. A high speed in which the op amp U1 performs an I-V conversion on the amplifier capable of preserving the differential performance AD9748 output current. U1 maintains IOUTA (or IOUTB) at a of the AD9748 while meeting other system level objectives (that virtual ground, minimizing the nonlinear output impedance is, cost or power) should be selected. The op amp’s differential effect on the DAC’s INL performance as described in the gain, gain setting resistor values, and full-scale output swing Analog Outputs section. Although this single-ended capabilities should all be considered when optimizing this circuit. configuration typically provides the best dc linearity performance, its ac distortion performance at higher DAC The differential circuit shown in Figure 27 provides the update rates can be limited by U1’s slew rate capabilities. U1 necessary level shifting required in a single-supply system. In provides a negative unipolar output voltage, and its full-scale this case, AVDD, which is the positive analog supply for both output voltage is simply the product of R and I . The full- FB OUTFS the AD9748 and the op amp, is also used to level shift the scale output should be set within U1’s voltage output swing differential output of the AD9748 to midsupply (that is, capabilities by scaling I and/or R . An improvement in ac OUTFS FB AVDD/2). The AD8041 is a suitable op amp for this application. distortion performance can result with a reduced I because OUTFS 500Ω U1 is required to sink less signal current. AD9748 225Ω C OPT IOUTA AD8041 R FB 225Ω 200Ω IOUTB C OPT I =10mA 1kΩ OUTFS AD9748 AVDD IOUTA 25Ω 25Ω 1kΩ U1 V = I × R OUT OUTFS FB IOUTB Figure 27. Single-Supply DC Differential Coupled Circuit 200Ω Figure 29. Unipolar Buffered Voltage Output Rev. A | Page 16 of 24 03211-023 03211-024 03211-025 03211-026 AD9748 POWER AND GROUNDING CONSIDERATIONS, Note that the ratio in Figure 30 is calculated as amps out/volts POWER SUPPLY REJECTION in. Noise on the analog power supply has the effect of modulating the internal switches, and therefore the output current. The Many applications seek high speed and high performance under voltage noise on AVDD, therefore, is added in a nonlinear less than ideal operating conditions. In these application circuits, manner to the desired IOUT. Due to the relative different size of the implementation and construction of the printed circuit these switches, the PSRR is very code dependent. This can produce board is as important as the circuit design. Proper RF techniques a mixing effect that can modulate low frequency power supply must be used for device selection, placement, and routing as noise to higher frequencies. Worst-case PSRR for either one of well as power supply bypassing and grounding to ensure the differential DAC outputs occurs when the full-scale current optimum performance. Figure 35 to Figure 38 illustrate the is directed toward that output. As a result, the PSRR measurement recommended printed circuit board ground, power, and signal in Figure 30 represents a worst-case condition in which the plane layouts implemented on the AD9748 evaluation board. digital inputs remain static and the full-scale output current of One factor that can measurably affect system performance is 20 mA is directed to the DAC output being measured. the ability of the DAC output to reject dc variations or ac noise The following illustrates the effect of supply noise on the analog superimposed on the analog or digital dc power distribution. supply. Suppose a switching regulator with a switching This is referred to as the power supply rejection ratio (PSRR). frequency of 250 kHz produces 10 mV of noise and, for simplicity’s For dc variations of the power supply, the resulting performance sake (ignoring harmonics), all of this noise is concentrated at of the DAC directly corresponds to a gain error associated with 250 kHz. To calculate how much of this undesired noise appears as the DAC’s full-scale current, I . AC noise on the dc supplies OUTFS current noise superimposed on the DAC’s full-scale current, is common in applications where the power distribution is IOUTFS, users must determine the PSRR in dB using Figure 30 at generated by a switching power supply. Typically, switching 250 kHz. To calculate the PSRR for a given RLOAD, such that the power supply noise occurs over the spectrum from tens of units of PSRR are converted from A/V to V/V, adjust the curve kilohertz to several megahertz. The PSRR vs. frequency of the in Figure 30 by the scaling factor 20 Ω log (R ). For instance, AD9748 AVDD supply over this frequency range is shown in LOAD if R is 50 Ω, then the PSRR is reduced by 34 dB (that is, Figure 30. LOAD PSRR of the DAC at 250 kHz, which is 85 dB in Figure 30, 85 becomes 51 dB V /V ). OUT IN 80 Proper grounding and decoupling should be a primary 75 objective in any high speed, high resolution system. The 70 AD9748 features separate analog and digital supplies and 65 ground pins to optimize the management of analog and digital ground currents in a system. In general, AVDD, the analog 60 supply, should be decoupled to ACOM, the analog common, 55 as close to the chip as physically possible. Similarly, DVDD, the 50 digital supply, should be decoupled to DCOM as close to the chip as physically possible. 45 40 For those applications that require a single 3.3 V supply for both 0 24 68 10 12 the analog and digital supplies, a clean analog supply can be FREQUENCY (MHz) Figure 30. Power Supply Rejection Ratio (PSRR) generated using the circuit shown in Figure 31. The circuit consists of a differential LC filter with separate power supply and return lines. Lower noise can be attained by using low ESR type electrolytic and tantalum capacitors. FERRITE BEADS AVDD TTL/CMOS LOGIC 100μF 10μF–22μF 0.1μF CIRCUITS ELECT. TANT. CER. ACOM 3.3V POWER SUPPLY Figure 31. Differential LC Filter for Single 3.3 V Applications Rev. A | Page 17 of 24 PSRR (dB) 03211-027 03211-028 AD9748 EVALUATION BOARD GENERAL DESCRIPTION The AD9748 evaluation boards allow for easy setup and testing This board allows the user the flexibility to operate the AD9748 of the product in the LFCSP package. Careful attention to layout in various configurations. Possible output configurations and circuit design, combined with a prototyping area, allows the include transformer coupled, resistor terminated, and single user to evaluate the AD9748 easily and effectively in any and differential outputs. The digital inputs are designed to be application where high resolution, high speed conversion is driven from various word generators, with the on-board option required. to add a resistor network for proper load termination. Provisions are also made to exercise the power-down feature of the AD9748 and select the clock and data modes. Rev. A | Page 18 of 24 AD9748 RED L1 TP12 BEAD CVDD TB1 1 2 1 DB13X 4 3 BLK DB12X C2 C10 C3 6 5 DB11X 10μF 0.1μF 0.1μF TP2 8 7 6.3V DB10X TB1 2 10 9 DB9X 12 11 DB8X 14 13 RED DB7X L2 16 15 TP13 DB6X BEAD DVDD TB3 1 18 17 DB5X 20 19 DB4X BLK C7 C6 C4 22 21 DB3X 0.1μF 10μF 0.1μF TP4 24 23 DB2X 6.3V TB3 2 26 25 DB1X 28 27 DB0X RED 30 29 L3 TP5 BEAD 32 31 AVDD TB4 1 JP3 33 34 CKEXTX 36 35 BLK C9 C5 C8 38 37 0.1μF 10μF 0.1μF TP6 6.3V 40 39 TB4 2 J1 R3 R4 R15 R16 R17 R18 R19 R20 100Ω 100Ω 100Ω 100Ω 100Ω 100Ω 100Ω 100Ω 1 RP3 22Ω 16 DB13X DB13 2 RP3 22Ω 15 DB12X DB12 3 RP3 22Ω 14 DB11X DB11 4 RP3 22Ω 13 DB10X DB10 5 RP3 22Ω 12 DB9X DB9 6 RP3 22Ω 11 DB8 DB8X 22Ω 10 7 RP3 DB7X DB7 8 RP3 22Ω 9 DB6 DB6X 1 RP4 22Ω 16 DB5X DB5 2 RP4 22Ω 15 DB4 DB4X 22Ω 14 3 RP4 DB3 DB3X 4 RP4 22Ω 13 DB2 DB2X 22Ω 12 5 RP4 DB1 DB1X 6 RP4 22Ω 11 DB0X DB0 7 RP4 22Ω 10 8 RP4 22Ω 9 CKEXT CKEXTX R21 R24 R25 R26 R27 R28 100Ω 100Ω 100Ω 100Ω 100Ω 100Ω Figure 32. Evaluation Board Schematic—Power Supply and Digital Inputs Rev. A | Page 19 of 24 HEADER STRAIGHT UP MALE NO SHROUD 03211-029 AD9748 AVDD DVDD CVDD C17 C19 C19 C32 0.1μF 0.1μF 0.1μF SLEEP TP11 WHT R29 10kΩ 32 1 DB7 DB8 DB7 DB8 R11 2 31 DB6 DB9 DB6 DB9 50Ω 30 3 DVDD DB10 DVDD DB10 DNP 4 29 DB5 DB11 DB5 DB11 C13 5 28 DB4 DB12 DB4 DB12 27 6 DB3 DB3 DB13 DB13 7 26 TP3 TP1 JP8 DB2 DB2 DCOM1 25 8 DB1 SLEEP DB1 IOUT WHT WHT 9 24 DB0 FS ADJ DB0 10 23 DCOM REFIO 3 4 T1 U1 11 22 CVDD ACOM CVDD S3 12 21 CLK IA CLK 2 5 AGND: 3, 4, 5 13 20 CLKB IB CLKB 6 14 19 CCOM ACOM1 1 15 18 T1 – 1T CMODE AVDD AVDD C11 CMODE 16 17 0.1μF MODE AVDD1 JP9 AD9748LFCSP DNP C12 TP7 R30 10Ω WHT R10 CVDD 50Ω R1 2kΩ JP1 0.1% MODE Figure 33. Evaluation Board Schematic—Output Signal Conditioning CVDD 1 7 U4 C20 C35 2 10μF 0.1μF 16V AGND: 5 CVDD: 8 CVDD R5 120Ω 3 CLKB 6 U4 JP2 4 S5 CKEXT AGND: 3, 4, 5 C34 AGND: 5 0.1μF CVDD: 8 CLK R2 R6 120Ω 50Ω Figure 34. Evaluation Board Schematic—Clock Input Rev. A | Page 20 of 24 03211-031 03211-030 AD9748 Figure 35. Evaluation Board Layout—Primary Side Figure 36. Evaluation Board Layout—Secondary Side Rev. A | Page 21 of 24 03211-032 03211-033 AD9748 Figure 37. Evaluation Board Layout—Ground Plane Figure 38. Evaluation Board Layout—Power Plane Rev. A | Page 22 of 24 03211-035 03211-034 AD9748 Figure 39. Evaluation Board Layout Assembly—Primary Side Figure 40. Evaluation Board Layout Assembly—Secondary Side Rev. A | Page 23 of 24 03211-037 03211-036 AD9748 OUTLINE DIMENSIONS 5.00 0.60 MAX BSC SQ 0.60 MAX PIN 1 INDICATOR 25 32 1 24 PIN 1 INDICATOR 0.50 BSC TOP 3.25 4.75 EXPOSED VIEW BSC SQ PAD 3.10 SQ (BOTTOM VIEW) 2.95 0.50 0.40 17 8 16 9 0.30 0.25 MIN 0.80 MAX 3.50 REF 12° MAX 0.65 TYP 0.05 MAX 1.00 0.02 NOM 0.85 0.30 COPLANARITY 0.20 REF 0.80 0.23 0.08 SEATING 0.18 PLANE COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2 Figure 41. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 5 mm × 5 mm Body, Very Thin Quad (CP-32-2) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option AD9748ACP −40°C to +85°C 32-Lead LFCSP_VQ CP-32-2 AD9748ACPRL7 −40°C to +85°C 32-Lead LFCSP_VQ CP-32-2 1 AD9748ACPZ −40°C to +85°C 32-Lead LFCSP_VQ CP-32-2 1 AD9748ACPZRL7 −40°C to +85°C 32-Lead LFCSP_VQ CP-32-2 AD9748ACP-PCB Evaluation Board 1 Z = Pb-free part. © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C03211–0–12/05(A) Rev. A | Page 24 of 24