ANALOG DEVICES AD9746

Dual 8-/10-/12-/14-/16-Bit 250 MSPS Digital-to-Analog Converters AD9741/AD9743/AD9745/AD9746/AD9747 FEATURES GENERAL DESCRIPTION High dynamic range, dual DACs The AD9741/AD9743/AD9745/AD9746/AD9747 are pin- Low noise and intermodulation distortion compatible, high dynamic range, dual digital-to-analog Single carrier WCDMA ACLR = 80 dBc @ 61.44 MHz IF converters (DACs) with 8-/10-/12-/ 14-/16-bit resolutions Innovative switching output stage permits useable outputs and sample rates of up to 250 MSPS. The devices include beyond Nyquist frequency specific features for direct conversion transmit applications, LVCMOS inputs with dual-port or optional interleaved including gain and offset compensation, and they interface single-port operation seamlessly with analog quadrature modulators, such as the Differential analog current outputs are programmable from ADL5370. 8.6 mA to 31.7 mA full scale A proprietary, dynamic output architecture permits synthesis Auxiliary 10-bit current DACs with source/sink capability for of analog outputs even above Nyquist by shifting energy away external offset nulling from the fundamental and into the image frequency. Internal 1.2 V precision reference voltage source Full programmability is provided through a serial peripheral Operates from 1.8 V and 3.3 V supplies interface (SPI) port. In addition, some pin-programmable 315 mW power dissipation features are offered for those applications without a controller. Small footprint, Pb-free, 72-Lead LFCSP PRODUCT HIGHLIGHTS APPLICATIONS 1. Low noise and intermodulation distortion (IMD) enables Wireless infrastructure: high quality synthesis of wideband signals. WCDMA, CDMA2000, TD-SCDMA, WiMAX Wideband communications: 2. Proprietary switching output for enhanced dynamic LMDS/MMDS, point-to-point performance. Instrumentation: 3. Programmable current outputs and dual auxiliary DACs RF signal generators, arbitrary waveform generators provide flexibility and system enhancements. FUNCTIONAL BLOCK DIAGRAM CLKP CLKN IOUT1P 16-BIT DAC1 IOUT1N INTERFACE LOGIC IOUT2P 16-BIT PID<15:0> DAC2 IOUT2N GAIN 10 DAC CMOS INTERFACE GAIN DAC AUX1P P2D<15:0> INTERNAL OFFSET DAC REFERENCE AUX1N AND SERIAL AUX2P BIAS OFFSET PERIPHERAL DAC AUX2N INTERFACE Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. SDO SDIO SCLK CSB REFIO FSADJ 06569-001 AD9741/AD9743/AD9745/AD9746/AD9747 TABLE OF CONTENTS Features .............................................................................................. 1 Instruction Byte.......................................................................... 18 Applications....................................................................................... 1 MSB/LSB Transfers .................................................................... 19 General Description ......................................................................... 1 Serial Interface Port Pin Descriptions ..................................... 19 Product Highlights ........................................................................... 1 SPI Register Map ............................................................................ 20 Functional Block Diagram .............................................................. 1 SPI Register Descriptions .............................................................. 21 Revision History ............................................................................... 2 Digital Inputs and Outputs ........................................................... 22 Specifications..................................................................................... 3 Input Data Timing ..................................................................... 22 DC Specifications ......................................................................... 3 Dual-Port Mode Timing ........................................................... 22 AC Specifications.......................................................................... 5 Single-Port Mode Timing ......................................................... 22 Digital and Timing Specifications.............................................. 7 SPI Port, Reset, and Pin Mode.................................................. 22 Absolute Maximum Ratings............................................................ 8 Driving the DAC Clock Input .................................................. 23 Thermal Resistance ...................................................................... 8 Full-Scale Current Generation ................................................. 23 ESD Caution.................................................................................. 8 DAC Transfer Function ............................................................. 24 Pin Configurations and Function Descriptions ........................... 9 Analog Modes of Operation ..................................................... 24 Typical Performance Characteristics ........................................... 14 Auxiliary DACS .......................................................................... 25 Terminology .................................................................................... 17 Power Dissipation....................................................................... 25 Theory of Operation ...................................................................... 18 Outline Dimensions....................................................................... 27 Serial Peripheral Interface ......................................................... 18 Ordering Guide .......................................................................... 27 General Operation of the Serial Interface ............................... 18 REVISION HISTORY 5/07—Revision 0: Initial Version Rev. 0 | Page 2 of 28 AD9741/AD9743/AD9745/AD9746/AD9747 SPECIFICATIONS DC SPECIFICATIONS T to T , AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, I = 20 mA, full-scale digital input, maximum MIN MAX FS sample rate, unless otherwise noted. Table 1. AD9741, AD9743, and AD9745 AD9741 AD9743 AD9745 Parameter Unit Min Typ Max Min Typ Max Min Typ Max RESOLUTION 8 10 12 Bits ACCURACY Differential Nonlinearity (DNL) ±0.03 ±0.05 ±0.13 LSB Integral Nonlinearity (INL) ±0.05 ±0.10 ±0.25 LSB MAIN DAC OUTPUTS Offset Error ±0.001 ±0.001 ±0.001 %FSR Offset Error Temperature Coefficient 1.0 1.0 1.0 ppm/°C Gain Error ±2.0 ±2.0 ±2.0 %FSR Gain Error Temperature Coefficient 100 100 100 ppm/°C Gain Matching (DAC1 to DAC2) ±1.0 ±1.0 ±1.0 %FSR Full-Scale Output Current 8.6 31.7 8.6 31.7 8.6 31.7 mA Output Compliance Voltage −1.0 +1.0 −1.0 +1.0 −1.0 +1.0 V Output Resistance 10 10 10 MΩ AUXILIARY DAC OUTPUTS Resolution 10 10 10 Bits Full-Scale Output Current −2.0 +2.0 −2.0 +2.0 −2.0 +2.0 mA Output Compliance Voltage Range—Sink Current 0.8 1.6 0.8 1.6 0.8 1.6 V Output Compliance Voltage Range—Source Current 0 1.6 0 1.6 0 1.6 V Output Resistance 1 1 1 MΩ Monotonicity 10 10 10 Bits REFERENCE INPUT/OUTPUT Output Voltage 1.2 1.2 1.2 V Output Voltage Temperature Coefficient 10 10 10 ppm/°C External Input Voltage Range 1.15 1.3 1.15 1.3 1.15 1.3 V Input or Output Resistance 5 5 5 kΩ POWER SUPPLY VOLTAGES AVDD33, DVDD33 3.13 3.47 3.13 3.47 3.13 3.47 V CVDD18, DVDD18 1.70 1.90 1.70 1.90 1.70 1.90 V POWER SUPPLY CURRENTS IAVDD33 56 60 56 60 56 60 mA IDVDD33 10 14 10 14 11 15 mA ICVDD18 18 22 18 22 18 22 mA I 28 32 29 33 30 34 mA DVDD18 POWER DISSIPATION fDAC = 250 MSPS, fOUT = 20 MHz 300 345 300 345 305 350 mW DAC Outputs Disabled 115 115 120 mW Full Device Power-Down 3 3 3 mW OPERATING TEMPERATURE −40 +85 −40 +85 −40 +85 °C Rev. 0 | Page 3 of 28 AD9741/AD9743/AD9745/AD9746/AD9747 T to T , AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, I = 20 mA, full-scale digital input, maximum MIN MAX FS sample rate, unless otherwise noted. The AD9745 is repeated in Table 2 so the user can compare it with all other parts. Table 2. AD9745, AD9746, and AD9747 AD9745 AD9746 AD9747 Parameter Unit Min Typ Max Min Typ Max Min Typ Max RESOLUTION 12 14 16 Bits ACCURACY Differential Nonlinearity (DNL) ±0.13 ±0.5 ±2.0 LSB Integral Nonlinearity (INL) ±0.25 ±1.0 ±4.0 LSB MAIN DAC OUTPUTS Offset Error ±0.001 ±0.001 ±0.001 %FSR Offset Error Temperature Coefficient 0.1 0.1 0.1 ppm/°C Gain Error ±2.0 ±2.0 ±2.0 %FSR Gain Error Temperature Coefficient 100 100 100 ppm/°C Gain Matching (DAC1 to DAC2) ±1.0 ±1.0 ±1.0 %FSR Full-Scale Output Current 8.6 31.7 8.6 31.7 8.6 31.7 mA Output Compliance Voltage −1.0 +1.0 −1.0 +1.0 −1.0 +1.0 V Output Resistance 10 10 10 MΩ AUXILIARY DAC OUTPUTS Resolution 10 10 10 Bits Full-Scale Output Current −2.0 +2.0 −2.0 +2.0 −2.0 +2.0 mA Output Compliance Voltage Range—Sink Current 0.8 1.6 0.8 1.6 0.8 1.6 V Output Compliance Voltage Range—Source Current 0 1.6 0 1.6 0 1.6 V Output Resistance 1 1 1 MΩ Monotonicity 10 10 10 Bits REFERENCE INPUT/OUTPUT Output Voltage 1.2 1.2 1.2 V Output Voltage Temperature Coefficient 10 10 10 ppm/°C External Input Voltage Range 1.15 1.3 1.15 1.3 1.15 1.3 V Input or Output Resistance 5 5 5 kΩ POWER SUPPLY VOLTAGES AVDD33, DVDD33 3.13 3.47 3.13 3.47 3.13 3.47 V CVDD18, DVDD18 1.70 1.90 1.70 1.90 1.70 1.90 V POWER SUPPLY CURRENTS I 56 60 56 60 56 60 mA AVDD33 IDVDD33 11 15 12 16 12 16 mA ICVDD18 18 22 18 22 18 22 mA IDVDD18 30 34 31 35 32 36 mA POWER DISSIPATION fDAC = 250 MSPS, fOUT = 20 MHz 305 350 310 355 310 355 mW DAC Outputs Disabled 120 125 125 mW Full Device Power-Down 3 3 3 mW OPERATING TEMPERATURE −40 +85 −40 +85 −40 +85 °C Rev. 0 | Page 4 of 28 AD9741/AD9743/AD9745/AD9746/AD9747 AC SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IFS = 20 mA, full-scale digital input, maximum sample rate, unless otherwise noted. Table 3. AD9741, AD9743, and AD9745 AD9741 AD9743 AD9745 Parameter Min Typ Max Min Typ Max Min Typ Max Unit SPURIOUS FREE DYNAMIC RANGE (SFDR) f = 250 MSPS, f = 20 MHz 70 80 82 dBc DAC OUT f = 250 MSPS, f = 70 MHz 70 70 70 dBc DAC OUT 1 f = 250 MSPS, f = 180 MHz 64 64 66 dBc DAC OUT INTERMODULATION DISTORTION (IMD) f = 250 MSPS, f = 20 MHz 80 80 86 dBc DAC OUT f = 250 MSPS, f = 70 MHz 80 80 80 dBc DAC OUT 1 fDAC = 250 MSPS, fOUT = 180 MHz 72 72 74 dBc CROSSTALK fDAC = 250 MSPS, fOUT = 20 MHz 80 80 80 dBc fDAC = 250 MSPS, fOUT = 70 MHz 80 80 80 dBc 1 fDAC = 250 MSPS, fOUT = 180 MHz 80 80 80 dBc ADJACENT CHANNEL LEAKAGE RATIO (ACLR) SINGLE CARRIER WCDMA fDAC = 245.76 MSPS, fOUT = 15.36 MHz 54 66 76 dBc f = 245.76 MSPS, f = 61.44 MHz 54 66 76 dBc DAC OUT 1 f = 245.76 MSPS, f = 184.32 MHz 54 64 72 dBc DAC OUT NOISE SPECTRAL DENSITY (NSD) f = 245.76 MSPS, f = 15.36 MHz −132 −144 −155 dBm/Hz DAC OUT f = 245.76 MSPS, f = 61.44 MHz −132 −144 −155 dBm/Hz DAC OUT 1 fDAC = 245.76 MSPS, fOUT = 184.32 MHz −135 −147 −155 dBm/Hz 1 Mix Mode. Rev. 0 | Page 5 of 28 AD9741/AD9743/AD9745/AD9746/AD9747 T to T , AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, I = 20 mA, full-scale digital input, maximum MIN MAX FS sample rate, unless otherwise noted. The AD9745 is repeated in Table 4 so the user can compare it with all other parts. Table 4. AD9745, AD9746, and AD9747 AD9745 AD9746 AD9747 Parameter Unit Min Typ Max Min Typ Max Min Typ Max SPURIOUS FREE DYNAMIC RANGE (SFDR) f = 250 MSPS, f = 20 MHz 82 82 82 dBc DAC OUT fDAC = 250 MSPS, fOUT = 70 MHz 70 70 70 dBc 1 fDAC = 250 MSPS, fOUT = 180 MHz 66 66 66 dBc INTERMODULATION DISTORTION (IMD) fDAC = 250 MSPS, fOUT = 20 MHz 86 86 86 dBc fDAC = 250 MSPS, fOUT = 70 MHz 80 80 80 dBc 1 f = 250 MSPS, f = 180 MHz 74 74 74 dBc DAC OUT CROSSTALK fDAC = 250 MSPS, fOUT = 20 MHz 80 80 80 dBc f = 250 MSPS, f = 70 MHz 80 80 80 dBc DAC OUT 1 f = 250 MSPS, f = 180 MHz 80 80 80 dBc DAC OUT ADJACENT CHANNEL LEAKAGE RATIO (ACLR) SINGLE CARRIER WCDMA f = 245.76 MSPS, f = 15.36 MHz 76 78 82 dBc DAC OUT fDAC = 245.76 MSPS, fOUT = 61.44 MHz 76 78 80 dBc 1 fDAC = 245.76 MSPS, fOUT = 184.32 MHz 72 74 74 dBc NOISE SPECTRAL DENSITY (NSD) fDAC = 245.76 MSPS, fOUT = 15.36 MHz −155 −163 −165 dBm/Hz fDAC = 245.76 MSPS, fOUT = 61.44 MHz −155 −160 −162 dBm/Hz 1 fDAC = 245.76 MSPS, fOUT = 184.32 MHz −155 −158 −160 dBm/Hz 1 Mix Mode. Rev. 0 | Page 6 of 28 AD9741/AD9743/AD9745/AD9746/AD9747 DIGITAL AND TIMING SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IFS = 20 mA, full-scale digital input, maximum sample rate, unless otherwise noted. Table 5. AD9741/AD9743/AD9745/AD9746/AD9747 Parameter Min Typ Max Unit DAC CLOCK INPUTS (CLKP, CLKN) Differential Peak-to-Peak Voltage 400 800 1600 mV Single-Ended Peak-to-Peak Voltage 800 mV Common-Mode Voltage 300 400 500 mV Input Current 1 μA Input Frequency 250 MHz DATA CLOCK OUTPUT (DCO) Output Voltage High 2.4 V Output Voltage Low 0.4 V Output Current 10 mA DAC Clock to Data Clock Output Delay (tDCO) 2.0 2.2 2.8 ns DATA PORT INPUTS Input Voltage High 2.0 V Input Voltage Low 0.8 V Input Current 1 μA Data to DAC Clock Setup Time (t Dual-Port Mode) 400 ps DBS Data to DAC Clock Hold Time (t Dual-Port Mode) 1200 ps DBH DAC Clock to Analog Output Data Latency (Dual-Port Mode) 7 Cycles Data or IQSEL Input to DAC Clock Setup Time (tDBS Single-Port Mode) 400 ps Data or IQSEL Input to DAC Clock Hold Time (tDBH Single-Port Mode) 1200 ps DAC Clock to Analog Output Data Latency (Single-Port Mode) 8 Cycles SERIAL PERIPHERAL INTERFACE SCLK Frequency (fSCLK) 40 MHz SCLK Pulse Width High (t) 10 ns PWH SCLK Pulse Width Low (t) 10 ns PWL CSB to SCLK Setup Time (tS) 1 ns CSB to SCLK Hold Time (tH) 0 ns SDIO to SCLK Setup Time (tDS) 1 ns SDIO to SCLK Hold Time (t) 0 ns DH SCLK to SDIO/SDO Data Valid Time (t) 1 ns DV RESET Pulse Width High 10 ns WAKE-UP TIME AND OUTPUT LATENCY From DAC Outputs Disabled 200 μs From Full Device Power-Down 1200 μs DAC Clock to Analog Output Latency (Dual-Port Mode) 7 Cycles DAC Clock to Analog Output Latency (Single-Port Mode) 8 Cycles Rev. 0 | Page 7 of 28 AD9741/AD9743/AD9745/AD9746/AD9747 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 6. Thermal resistance tested using JEDEC standard 4-layer With Parameter Respect to Rating thermal test board with no airflow. AVDD33, DVDD33 AVSS DVSS −0.3 V to +3.6 V CVSS Table 7. DVDD18, CVDD18 AVSS DVSS −0.3 V to +1.98 V Package Type θ Unit JA CVSS CP-72-1 (Exposed Pad Soldered to PCB) 25 °C/W AVSS DVSS CVSS −0.3 V to +0.3 V DVSS AVSS CVSS −0.3 V to +0.3 V Stresses above those listed under Absolute Maximum Ratings CVSS AVSS DVSS −0.3 V to +0.3 V may cause permanent damage to the device. This is a stress REFIO AVSS −0.3 V to AVDD33 + 0.3 V rating only; functional operation of the device at these or any IOUT1P, IOUT1N, IOUT2P, AVSS −1.0 V to AVDD33 + 0.3 V IOUT2P, AUX1P, AUX1N, other conditions above those indicated in the operational AUX2P, AUX2N section of this specification is not implied. Exposure to absolute P1D15 to P1D0, DVSS −0.3 V to DVDD33 + 0.3 V maximum rating conditions for extended periods may affect P2D15 to P2D0 device reliability. CLKP, CLKN CVSS −0.3 V to CVDD18 + 0.3 V RESET, CSB, SCLK, SDIO, SDO DVSS –0.3 V to DVDD33 + 0.3 V ESD CAUTION Junction Temperature 125°C Storage Temperature −65°C to +150°C Rev. 0 | Page 8 of 28 AD9741/AD9743/AD9745/AD9746/AD9747 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS CVDD18 1 54 FSADJ PIN 1 INDICATOR CVSS 2 53 RESET CLKP 3 52 CSB CLKN 4 51 SCLK CVSS 5 50 SDIO CVDD18 6 49 SDO DVSS 7 48 DVSS AD9741 DVDD18 8 47 DVDD18 P1D7 9 46 NC (TOP VIEW) P1D6 10 45 NC P1D5 11 44 NC P1D4 12 43 NC P1D3 13 42 NC P1D2 14 41 NC P1D1 15 40 NC P1D0 16 39 NC NC 17 38 P2D0 NC 18 37 P2D1 NC = NO CONNECT Figure 2. AD9741 Pin Configuration Table 8. AD 9741 Pin Function Descriptions Pin No. Mnemonic Description 1, 6 CVDD18 Clock Supply Voltage (1.8 V). 2, 5 CVSS Clock Supply Common (0 V). 3 CLKP Differential DAC Clock Input. 4 CLKN Complementary Differential DAC Clock Input. 7, 28, 48 DVSS Digital Supply Common (0 V). 8, 47 DVDD18 Digital Core Supply Voltage (1.8 V). 9 to 16 P1D<7:0> Port 1 Data Bit Inputs. 17 to 24, 26, 30, 39 to 46 NC No Connect. 25 DCO Data Clock Output. Use to clock data source. 27 DVDD33 Digital I/O Supply Voltage (3.3 V). 29 IQSEL I/Q Framing Signal for Single-Port Mode Operation. 31 to 38 P2D<7:0> Port 2 Data Bit Inputs. 49 SDO Serial Peripheral Interface Data Output. 50 SDIO Serial Peripheral Interface Data Input and Optional Data Output. 51 SCLK Serial Peripheral Interface Clock Input. 52 CSB Serial Peripheral Interface Chip Select Input. Active low. 53 RESET Hardware Reset. Active high. 54 FSADJ Full-Scale Current Output Adjust. Connect a 10 kΩ resistor to AVSS. 55 REFIO Reference Input/Output. Connect a 0.1 μF capacitor to AVSS. 56, 57, 71, 72 AVDD33 Analog Supply Voltage (3.3 V). 58, 61, 64, 67, 70 AVSS Analog Supply Common (0 V). 59 IOUT2P DAC2 Current Output True. Sources full-scale current when input data bits are all 1. 60 IOUT2N DAC2 Current Output Complement. Sources full-scale current when data bits are all 0. 62 AUX2P Auxiliary DAC2 Default Current Output Pin. 63 AUX2N Auxiliary DAC2 Optional Output Pin. Enable through SPI. 65 AUX1N Auxiliary DAC1 Optional Output Pin. Enable through SPI. 66 AUX1P Auxiliary DAC1 Default Current Output Pin. 68 IOUT1N Complementary DAC1 Current Output. Sources full-scale current when data bits are all 0. 69 IOUT1P DAC1 Current Output. Sources full-scale current when data bits are all 1. EPAD AVSS Exposed Thermal Pad. Must be soldered to copper pour on top surface of PCB for mechanical stability and must be electrically tied to low impedance GND plane for low noise performance. Rev. 0 | Page 9 of 28 NC 19 72 AVDD33 NC 20 71 AVDD33 NC 21 70 AVSS NC 22 69 IOUT1P NC 23 68 IOUT1N NC 24 67 AVSS DCO 25 66 AUX1P NC 26 65 AUX1N DVDD33 27 64 AVSS DVSS 28 63 AUX2N IQSEL 29 62 AUX2P NC 30 61 AVSS P2D7 31 60 IOUT2N P2D6 32 59 IOUT2P P2D5 33 58 AVSS P2D4 34 57 AVDD33 P2D3 35 56 AVDD33 P2D2 36 55 REFIO 06569-006 AD9741/AD9743/AD9745/AD9746/AD9747 CVDD18 1 54 FSADJ PIN 1 CVSS 2 INDICATOR 53 RESET CLKP 3 52 CSB CLKN 4 51 SCLK CVSS 5 50 SDIO CVDD18 6 49 SDO DVSS 7 48 DVSS AD9743 DVDD18 8 47 DVDD18 P1D9 9 46 NC (TOP VIEW) P1D8 10 45 NC P1D7 11 44 NC P1D6 12 43 NC P1D5 13 42 NC P1D4 14 41 NC P1D3 15 40 P2D0 P1D2 16 39 P2D1 P1D1 17 38 P2D2 P1D0 18 37 P2D3 NC = NO CONNECT Figure 3. AD9743 Pin Configuration Table 9. AD 9743 Pin Function Descriptions Pin No. Mnemonic Description 1, 6 CVDD18 Clock Supply Voltage (1.8 V). 2, 5 CVSS Clock Supply Common (0 V). 3 CLKP Differential DAC Clock Input. 4 CLKN Complementary Differential DAC Clock Input. 7, 28, 48 DVSS Digital Supply Common (0 V). 8, 47 DVDD18 Digital Core Supply Voltage (1.8 V). 9 to 18 P1D<9:0> Port 1 Data Bit Inputs. 19 to 24, 26, 30, 41 to 46 NC No Connect. 25 DCO Data Clock Output. Use to clock data source. 27 DVDD33 Digital I/O Supply Voltage (3.3 V). 29 IQSEL I/Q Framing Signal for Single-Port Mode Operation. 31 to 40 P2D<9:0> Port 2 Data Bit Inputs. 49 SDO Serial Peripheral Interface Data Output. 50 SDIO Serial Peripheral Interface Data Input and Optional Data Output. 51 SCLK Serial Peripheral Interface Clock Input. 52 CSB Serial Peripheral Interface Chip Select Input. Active low. 53 RESET Hardware Reset. Active high. 54 FSADJ Full-Scale Current Output Adjust. Connect a 10 kΩ resistor to AVSS. 55 REFIO Reference Input/Output. Connect a 0.1 μF capacitor to AVSS. 56, 57, 71, 72 AVDD33 Analog Supply Voltage (3.3 V). 58, 61, 64, 67, 70 AVSS Analog Supply Common (0 V). 59 IOUT2P DAC2 Current Output True. Sources full-scale current when input data bits are all 1. 60 IOUT2N DAC2 Current Output Complement. Sources full-scale current when data bits are all 0. 62 AUX2P Auxiliary DAC2 Default Current Output Pin. 63 AUX2N Auxiliary DAC2 Optional Output Pin. Enable through SPI. 65 AUX1N Auxiliary DAC1 Optional Output Pin. Enable through SPI. 66 AUX1P Auxiliary DAC1 Default Current Output Pin. 68 IOUT1N Complementary DAC1 Current Output. Sources full-scale current when data bits are all 0. 69 IOUT1P DAC1 Current Output. Sources full-scale current when data bits are all 1. EPAD AVSS Exposed Thermal Pad. Must be soldered to copper pour on top surface of PCB for mechanical stability and must be electrically tied to low impedance GND plane for low noise performance. Rev. 0 | Page 10 of 28 NC 19 72 AVDD33 NC 20 71 AVDD33 NC 21 70 AVSS NC 22 69 IOUT1P NC 23 68 IOUT1N NC 24 67 AVSS DCO 25 66 AUX1P NC 26 65 AUX1N DVDD33 27 64 AVSS DVSS 28 AUX2N 63 IQSEL 29 62 AUX2P NC 30 61 AVSS P2D9 31 60 IOUT2N P2D8 32 59 IOUT2P P2D7 33 58 AVSS P2D6 34 57 AVDD33 P2D5 35 56 AVDD33 P2D4 36 55 REFIO 06569-005 AD9741/AD9743/AD9745/AD9746/AD9747 CVDD18 1 54 FSADJ PIN 1 CVSS 2 INDICATOR 53 RESET CLKP 3 52 CSB CLKN 4 51 SCLK CVSS 5 50 SDIO CVDD18 6 49 SDO DVSS 7 48 DVSS AD9745 DVDD18 8 47 DVDD18 P1D11 9 46 NC (TOP VIEW) P1D10 10 45 NC P1D9 11 44 NC P1D8 12 43 NC P1D7 13 42 P2D0 P1D6 14 41 P2D1 P1D5 15 40 P2D2 P1D4 16 39 P2D3 P1D3 17 38 P2D4 P1D2 18 37 P2D5 NC = NO CONNECT Figure 4. AD9745 Pin Configuration Table 10. AD9745 Pin Function Descriptions Pin No. Mnemonic Description 1, 6 CVDD18 Clock Supply Voltage (1.8 V). 2, 5 CVSS Clock Supply Common (0 V). 3 CLKP Differential DAC Clock Input. 4 CLKN Complementary Differential DAC Clock Input. 7, 28, 48 DVSS Digital Supply Common (0 V). 8, 47 DVDD18 Digital Core Supply Voltage (1.8 V). 9 to 20 P1D<11:0> Port 1 Data Bit Inputs. 21 to 24, 26, 30, 43 to 46 NC No Connect. 25 DCO Data Clock Output. Use to clock data source. 27 DVDD33 Digital I/O Supply Voltage (3.3 V). 29 IQSEL I/Q Framing Signal for Single-Port Mode Operation. 31 to 42 P2D<11:0> Port 2 Data Bit Inputs. 49 SDO Serial Peripheral Interface Data Output. 50 SDIO Serial Peripheral Interface Data Input and Optional Data Output. 51 SCLK Serial Peripheral Interface Clock Input. 52 CSB Serial Peripheral Interface Chip Select Input. Active low. 53 RESET Hardware Reset. Active high. 54 FSADJ Full-Scale Current Output Adjust. Connect 10 kΩ resistor to AVSS. 55 REFIO Reference Input/Output. Connect a 0.1 μF capacitor to AVSS. 56, 57, 71, 72 AVDD33 Analog Supply Voltage (3.3 V). 58, 61, 64, 67, 70 AVSS Analog Supply Common (0 V). 59 IOUT2P DAC2 Current Output True. Sources full-scale current when input data bits are all 1. 60 IOUT2N DAC2 Current Output Complement. Sources full-scale current when data bits are all 0. 62 AUX2P Auxiliary DAC2 Default Current Output Pin. 63 AUX2N Auxiliary DAC2 Optional Output Pin. Enable through SPI. 65 AUX1N Auxiliary DAC1 Optional Output Pin. Enable through SPI. 66 AUX1P Auxiliary DAC1 Default Current Output Pin. 68 IOUT1N Complementary DAC1 Current Output. Sources full-scale current when data bits are all 0. 69 IOUT1P DAC1 Current Output. Sources full-scale current when data bits are all 1. EPAD AVSS Exposed Thermal Pad. Must be soldered to copper pour on top surface of PCB for mechanical stability and must be electrically tied to low impedance GND plane for low noise performance. Rev. 0 | Page 11 of 28 P1D1 19 72 AVDD33 P1D0 20 71 AVDD33 NC 21 70 AVSS NC 22 69 IOUT1P NC 23 68 IOUT1N NC 24 67 AVSS DCO 25 66 AUX1P NC 26 65 AUX1N DVDD33 27 64 AVSS DVSS 28 63 AUX2N 29 IQSEL 62 AUX2P NC 30 61 AVSS P2D11 31 60 IOUT2N P2D10 32 59 IOUT2P P2D9 33 58 AVSS P2D8 34 57 AVDD33 P2D7 35 56 AVDD33 P2D6 36 55 REFIO 06569-004 AD9741/AD9743/AD9745/AD9746/AD9747 CVDD18 1 54 FSADJ PIN 1 CVSS 2 INDICATOR 53 RESET CLKP 3 52 CSB CLKN 4 51 SCLK CVSS 5 50 SDIO CVDD18 6 49 SDO DVSS 7 48 DVSS AD9746 DVDD18 8 47 DVDD18 P1D13 9 46 NC (TOP VIEW) P1D12 10 45 NC P1D11 11 44 P2D0 P1D10 12 43 P2D1 P1D9 13 42 P2D2 P1D8 14 41 P2D3 P1D7 15 40 P2D4 P1D6 16 39 P2D5 P1D5 17 38 P2D6 P1D4 18 37 P2D7 NC = NO CONNECT Figure 5. AD9746 Pin Configuration Table 11. AD9746 Pin Function Descriptions Pin No. Mnemonic Description 1, 6 CVDD18 Clock Supply Voltage (1.8 V). 2, 5 CVSS Clock Supply Common (0 V). 3 CLKP Differential DAC Clock Input. 4 CLKN Complementary Differential DAC Clock Input. 7, 28, 48 DVSS Digital Supply Common (0 V). 8, 47 DVDD18 Digital Core Supply Voltage (1.8 V). 9 to 22 P1D<13:0> Port 1 Data Bit Inputs. 23, 24, 26, 30, 45, 46 NC No Connect. 25 DCO Data Clock Output. Use to clock data source. 27 DVDD33 Digital I/O Supply Voltage (3.3 V). 29 IQSEL I/Q Framing Signal for Single-Port Mode Operation. 31 to 44 P2D<13:0> Port 2 Data Bit Inputs. 49 SDO Serial Peripheral Interface Data Output. 50 SDIO Serial Peripheral Interface Data Input and Optional Data Output. 51 SCLK Serial Peripheral Interface Clock Input. 52 CSB Serial Peripheral Interface Chip Select Input. Active low. 53 RESET Hardware Reset. Active high. 54 FSADJ Full-Scale Current Output Adjust. Connect a 10 kΩ resistor to AVSS. 55 REFIO Reference Input/Output. Connect a 0.1 μF capacitor to AVSS. 56, 57, 71, 72 AVDD33 Analog Supply Voltage (3.3 V). 58, 61, 64, 67, 70 AVSS Analog Supply Common (0 V). 59 IOUT2P DAC2 Current Output True. Sources full-scale current when input data bits are all 1. 60 IOUT2N DAC2 Current Output Complement. Sources full-scale current when data bits are all 0. 62 AUX2P Auxiliary DAC2 Default Current Output Pin. 63 AUX2N Auxiliary DAC2 Optional Output Pin. Enable through SPI. 65 AUX1N Auxiliary DAC1 Optional Output Pin. Enable through SPI. 66 AUX1P Auxiliary DAC1 Default Current Output Pin. 68 IOUT1N Complementary DAC1 Current Output. Sources full-scale current when data bits are all 0. 69 IOUT1P DAC1 Current Output. Sources full-scale current when data bits are all 1. EPAD AVSS Exposed Thermal Pad. Must be soldered to copper pour on top surface of PCB for mechanical stability and must be electrically tied to low impedance GND plane for low noise performance. Rev. 0 | Page 12 of 28 P1D3 19 72 AVDD33 P1D2 20 71 AVDD33 P1D1 21 70 AVSS P1D0 22 69 IOUT1P NC 23 68 IOUT1N NC 24 67 AVSS DCO 25 66 AUX1P NC 26 65 AUX1N DVDD33 27 64 AVSS DVSS 28 63 AUX2N IQSEL 29 62 AUX2P NC 30 61 AVSS P2D13 31 60 IOUT2N P2D12 32 59 IOUT2P P2D11 33 58 AVSS P2D10 34 57 AVDD33 P2D9 35 56 AVDD33 P2D8 36 55 REFIO 06569-003 AD9741/AD9743/AD9745/AD9746/AD9747 CVDD18 1 54 FSADJ PIN 1 CVSS 2 INDICATOR 53 RESET CLKP 3 52 CSB CLKN 4 51 SCLK CVSS 5 50 SDIO CVDD18 6 49 SDO DVSS 7 48 DVSS AD9747 DVDD18 8 47 DVDD18 P1D15 9 (TOP VIEW) 46 P2D0 P1D14 10 45 P2D1 P1D13 11 44 P2D2 P1D12 12 43 P2D3 P1D11 13 42 P2D4 P1D10 14 41 P2D5 P1D9 15 40 P2D6 P1D8 16 39 P2D7 P1D7 17 38 P2D8 P1D6 18 37 P2D9 NC = NO CONNECT Figure 6. AD9747 Pin Configuration Table 12. AD9747 Pin Function Descriptions Pin No. Mnemonic Description 1, 6 CVDD18 Clock Supply Voltage (1.8 V). 2, 5 CVSS Clock Supply Common (0 V). 3 CLKP Differential DAC Clock Input. 4 CLKN Complementary Differential DAC Clock Input. 7, 28, 48 DVSS Digital Supply Common (0 V). 8, 47 DVDD18 Digital Core Supply Voltage (1.8 V). 9 to 24 P1D<15:0> Port 1 Data Bit Inputs. 25 DCO Data Clock Output. Use to clock data source. 26, 30 NC No Connect. 27 DVDD33 Digital I/O Supply Voltage (3.3 V). 29 IQSEL I/Q Framing Signal for Single-Port Mode Operation. 31 to 46 P2D<15:0> Port 2 Data Bit Inputs. 49 SDO Serial Peripheral Interface Data Output. 50 SDIO Serial Peripheral Interface Data Input and Optional Data Output. 51 SCLK Serial Peripheral Interface Clock Input. 52 CSB Serial Peripheral Interface Chip Select Input. Active low. 53 RESET Hardware Reset. Active high. 54 FSADJ Full-Scale Current Output Adjust. Connect a 10 kΩ resistor to AVSS. 55 REFIO Reference Input/Output. Connect a 0.1 μF capacitor to AVSS. 56, 57, 71, 72 AVDD33 Analog Supply Voltage (3.3 V). 58, 61, 64, 67, 70 AVSS Analog Supply Common (0 V). 59 IOUT2P DAC2 Current Output. Sources full-scale current when input data bits are all 1. 60 IOUT2N Complementary DAC2 Current Output. Sources full-scale current when data bits are all 0. 62 AUX2P Auxiliary DAC2 Default Current Output Pin. 63 AUX2N Auxiliary DAC2 Optional Output Pin. Enable through SPI. 65 AUX1N Auxiliary DAC1 Optional Output Pin. Enable through SPI. 66 AUX1P Auxiliary DAC1 Default Current Output Pin. 68 IOUT1N Complementary DAC1 Current Output. Sources full-scale current when data bits are all 0. 69 IOUT1P DAC1 Current Output. Sources full-scale current when data bits are all 1. EPAD AVSS Exposed Thermal Pad. Must be soldered to copper pour on top surface of PCB for mechanical stability and must be electrically tied to low impedance GND plane for low noise performance. Rev. 0 | Page 13 of 28 P1D5 19 72 AVDD33 P1D4 20 71 AVDD33 P1D3 21 70 AVSS P1D2 22 69 IOUT1P P1D1 23 68 IOUT1N P1D0 24 67 AVSS DCO 25 66 AUX1P NC 26 65 AUX1N DVDD33 27 AVSS 64 DVSS 28 63 AUX2N IQSEL 29 62 AUX2P NC 30 61 AVSS P2D15 31 60 IOUT2N P2D14 32 59 IOUT2P P2D13 33 58 AVSS P2D12 34 57 AVDD33 P2D11 35 56 AVDD33 P2D10 36 55 REFIO 06569-002 AD9741/AD9743/AD9745/AD9746/AD9747 TYPICAL PERFORMANCE CHARACTERISTICS 100 100 90 90 250MSPS 125MSPS 80 80 125MSPS 250MSPS 70 70 60 60 50 50 40 40 0 2040 6080 100 120 0 2040 6080 100 120 f (MHz) f (MHz) OUT OUT Figure 7. AD9747 SFDR vs. f , Normal Mode Figure 10. AD9747 IMD vs. f , Normal Mode OUT OUT 100 100 90 90 80 80 70 70 60 60 50 50 40 40 125 150 175 200 225 250 125 150 175 200 225 250 f (MHz) f (MHz) OUT OUT Figure 8. AD9747 SFDR vs. fOUT, Mix Mode, 250 MSPS Figure 11. AD9747 IMD vs. fOUT, Mix Mode, 250 MSPS 90 –152 –154 85 NORMAL MODE –156 MIX MODE 80 –158 MIX MODE NORMAL MODE 75 –160 –162 70 –164 65 –166 60 –168 0 50 100 150 200 250 02 50 100 150 20050 f (MHz) f (MHz) OUT OUT Figure 9. AD9747 ACLR vs. fOUT, Single Carrier WCDMA, 245.76 MSPS Figure 12. AD9747 NSD vs. f , Single Carrier WCDMA, 245.76 MSPS OUT Rev. 0 | Page 14 of 28 ACLR (dBc) SFDR (dBc) SFDR (dBc) 06569-009 06569-008 06569-007 NSD (dBm/Hz) IMD (dBc) IMD (dBc) 06569-012 06569-011 06569-010 AD9741/AD9743/AD9745/AD9746/AD9747 100 100 90 90 10mAFS 20mAFS 80 80 20mAFS 30mAFS 70 70 10mAFS 30mAFS 60 60 50 50 40 40 0 20 40 60 80 100 120 0 2040 6080 100 120 f (MHz) f (MHz) OUT OUT Figure 13. AD9747 SFDR vs. Analog Output, 250 MSPS Figure 16. AD9747 IMD vs. Analog Output, 250 MSPS 100 100 90 90 0dBFS 80 0dBFS 80 –3dBFS –3dBFS 70 70 –6dBFS –6dBFS 60 60 50 50 40 40 0 20 40 60 80 100 120 0 2040 6080 100 120 f (MHz) f (MHz) IN IN Figure 14. AD9747 SFDR vs. Digital Input, 250 MSPS Figure 17. AD9747 IMD vs. Digital Input, 250 MSPS 90 90 85 85 80 80 75 75 70 70 RANGE OF IMD PERFORMANCE IS RANGE OF POSSIBLE SFDR ESSENTIALLY INDEPENDENT OF 65 PERFORMANCE IS DEPENDENT ON 65 INPUT DATA TIMING RELATIVE TO INPUT DATA TIMING RELATIVE TO THE DAC CLOCK. SEE INPUT DATA THE DAC CLOCK. SEE INPUT DATA TIMING SECTION. TIMING SECTION. 60 60 10 20 30 40 50 60 70 80 90 100 110 10 20 30 40 50 60 70 80 90 100 110 f (MHz) f (MHz) OUT OUT Figure 15. AD9747 SFDR vs. f Over Input Data Timing Figure 18. AD9747 IMD vs. f Over Input Data Timing OUT OUT Rev. 0 | Page 15 of 28 SFDR (dBc) SFDR (dBc) SFDR (dBc) 06569-038 06569-037 06569-036 IMD (dBc) IMD (dBc) IMD (dBc) 06569-041 06569-040 06569-039 AD9741/AD9743/AD9745/AD9746/AD9747 1 –130 0 –135 –1 –140 NORMAL MODE –2 –145 –150 –3 MIX MODE –155 –4 –160 –5 0 25 50 75 100 125 150 175 200 225 250 –165 f (MHz) OUT AD9741 AD9743 AD9745 AD9746 AD9747 Figure 19. Nominal Power in the Fundamental, I = 20 mA Figure 21. NSD vs. Bit Resolution, Single Carrier WCDMA, 245.76 MSPS, f FS CARRIER f = 61.44 MHz CARRIER 85 80 75 70 65 60 55 50 AD9741 AD9743 AD9745 AD9746 AD9747 Figure 20. ACLR vs. Bit Resolution, Single Carrier WCDMA, 245.76 MSPS, fCARRIER = 61.44 MHz Rev. 0 | Page 16 of 28 ACLR (dBc) A (dBm) OUT 06569-043 06569-042 NSD (dBm/Hz) 06569-044 AD9741/AD9743/AD9745/AD9746/AD9747 TERMINOLOGY Temperature Drift Integral Nonlinearity (INL) Temperature drift is specified as the maximum change in a The maximum deviation of the actual analog output from the parameter from ambient temperature (25°C) to either TMIN ideal output, as determined by a straight line drawn from zero or TMAX and is typically reported as ppm/°C. scale to full scale. Spurious-Free Dynamic Range (SFDR) Differential Nonlinearity (DNL) The difference in decibels between the peak amplitude of a test A measure of the maximum deviation in analog output associated tone and the peak amplitude of the largest spurious signal over with any single value change in the digital input code relative to the specified bandwidth. an ideal LSB. Intermodulation Distortion (IMD) Monotonicity The difference in decibels between the maximum peak ampli- A DAC is monotonic if the analog output increases or remains tude of two test tones and the maximum peak amplitude of constant in response to an increase in the digital input. the distortion products created from the sum or difference of Offset Error integer multiples of the test tones. The deviation of the output current from the ideal zero-scale Adjacent Channel Leakage Ratio (ACLR) current. For differential outputs, 0 mA is expected at I when OUTP The ratio between the measured power of a wideband signal all inputs are low, and 0 mA is expected at I when all inputs OUTN within a channel relative to the measured power in an empty are high. adjacent channel. Gain Error Noise Spectral Density (NSD) The deviation of the output current from the ideal full-scale The measured noise power over a 1 Hz bandwidth seen at the current. Actual full-scale output current is determined by analog output. subtracting the output (when all inputs are low) from the output (when all inputs are high). Output Compliance Range The range of allowable voltage seen by the analog output of a current output DAC. Operation beyond the compliance limits may cause output stage saturation and/or a breakdown resulting in nonlinear performance. Rev. 0 | Page 17 of 28 AD9741/AD9743/AD9745/AD9746/AD9747 THEORY OF OPERATION transfer, and a reference register address for the first byte of the The AD9741/AD9743/AD9745/AD9746/AD9747 combine data transfer. A logic high on the CSB pin followed by a logic many features to make them very attractive for wired and low resets the SPI port to its initial state and defines the start wireless communications systems. The dual DAC architecture of the instruction cycle. From this point, the next eight rising facilitates easy interfacing to common quadrature modulators SCLK edges define the eight bits of the instruction byte for the when designing single sideband transmitters. In addition, the current communication cycle. speed and performance of the devices allow wider bandwidths and more carriers to be synthesized than in previously available The remaining SCLK edges are for Phase 2 of the communication products. cycle, which is the data transfer between the serial port control- ler and the system controller. Phase 2 can be a transfer of 1, 2, 3, All features and options are software programmable through or 4 data bytes as determined by the instruction byte. Using the SPI port. multibyte transfers is usually preferred although single-byte SERIAL PERIPHERAL INTERFACE data transfers are useful to reduce CPU overhead or when only a single register access is required. SDO AD9747 All serial port data is transferred to and from the device in syn- SDIO SPI chronization with the SCLK pin. Input data is always latched SCLK PORT on the rising edge of SCLK whereas output data is always valid CSB after the falling edge of SCLK. Register contents change imme- Figure 22. SPI Port diately upon writing to the last bit of each transfer byte. The SPI port is a flexible, synchronous serial communications When synchronization is lost, the device has the ability to port allowing easy interfacing to many industry-standard asynchronously terminate an I/O operation whenever the CSB microcontrollers and microprocessors. The port is compatible pin is taken to logic high. Any unwritten register content data is with most synchronous transfer formats including both the lost if the I/O operation is aborted. Taking CSB low then resets the serial port controller and restarts the communication cycle. Motorola SPI and Intel® SSR protocols. The interface allows read and write access to all registers that INSTRUCTION BYTE configure the AD9741/AD9743/AD9745/AD9746/AD9747. The instruction byte contains the information shown in the Single or multiple byte transfers are supported as well as MSB- following bit map. first or LSB-first transfer formats. Serial data input/output can MSB LSB be accomplished through a single bidirectional pin (SDIO) or B7 B6 B5 B4 B3 B2 B1 B0 through two unidirectional pins (SDIO/SDO). R/W N1 N0 A4 A3 A2 A1 A0 The serial port configuration is controlled by Register 0x00, Bit 7, R/W, determines whether a read or a write data transfer Bits<7:6>. It is important to note that any change made to the occurs after the instruction byte write. Logic high indicates a serial port configuration occurs immediately upon writing to read operation. Logic 0 indicates a write operation. the last bit of this byte. Therefore, it is possible with a multibyte transfer to write to this register and change the configuration in Bits<6:5>, N1 and N0, determine the number of bytes to be the middle of a communication cycle. Care must be taken to transferred during the data transfer cycle. The bits decode as compensate for the new configuration within the remaining shown in Table 13. bytes of the current communication cycle. Table 13. Byte Transfer Count Use of a single-byte transfer when changing the serial port N1 N0 Description configuration is recommended to prevent unexpected device 0 0 Transfer one byte behavior. 0 1 Transfer two bytes GENERAL OPERATION OF THE SERIAL INTERFACE 1 0 Transfer three bytes 1 1 Transfer four bytes There are two phases to any communication cycle with the AD9741/AD9743/AD9745/AD9746/AD9747: Phase 1 and Bits<4:0>, A4, A3, A2, A1, and A0, determine which register is Phase 2. Phase 1 is the instruction cycle, which writes an accessed during the data transfer of the communications cycle. instruction byte into the device. This byte provides the serial For multibyte transfers, this address is a starting or ending port controller with information regarding Phase 2 of the address depending on the current data transfer mode. For MSB- communication cycle: the data transfer cycle. first format, the specified address is an ending address or the The Phase 1 instruction byte defines whether the upcoming most significant address in the current cycle. Remaining data transfer is read or write, the number of bytes in the data register addresses for multiple byte data transfers are generated Rev. 0 | Page 18 of 28 06569-013 AD9741/AD9743/AD9745/AD9746/AD9747 internally by the serial port controller by decrementing from The configuration of this pin is controlled by Register 0x00, the specified address. For LSB-first format, the specified address Bit 7. The default is Logic 0, which configures the SDIO pin is a beginning address or the least significant address in the as unidirectional. current cycle. Remaining register addresses for multiple byte Serial Data Out (SDO) data transfers are generated internally by the serial port Data is read from this pin for protocols that use separate lines controller by incrementing from the specified address. for transmitting and receiving data. The configuration of this MSB/LSB TRANSFERS pin is controlled by Register 0x00, Bit 7. If this bit is set to a Logic 1, the SDO pin does not output data and is set to a high The serial port can support both MSB-first and LSB-first data impedance state. formats. This functionality is controlled by Register 0x00, Bit 6. The default is Logic 0, which is MSB-first format. When using MSB-first format (LSBFIRST = 0), the instruction INSTRUCTION CYCLE DATA TRANSFER CYCLE and data bit must be written from MSB to LSB. Multibyte data CSB transfers in MSB-first format start with an instruction byte that includes the register address of the most significant data byte. SCLK Subsequent data bytes are loaded into sequentially lower R/W N1 N0 A4 A3 A2 A1 A0 D7 D6 D5 D3 D2 D1 D0 N N 0 0 0 0 SDIO address locations. In MSB-first mode, the serial port internal address generator decrements for each byte of the multibyte D7 D6 D5 D3 D2 D1 D0 N N 0 0 0 0 SDO data transfer. Figure 23. Serial Register Interface—MSB First When using LSB-first format (LSBFIRST = 1), the instruction and data bit must be written from LSB to MSB. Multibyte data transfers in LSB-first format start with an instruction byte that INSTRUCTION CYCLE DATA TRANSFER CYCLE includes the register address of the least significant data byte. CSB Subsequent data bytes are loaded into sequentially higher address locations. In LSB-first mode, the serial port internal SCLK address generator increments for each byte of the multibyte A0 A1 A2 A3 A4 N0 N1 R/W D0 D1 D2 D4 D5 D6 D7 0 0 0 N N N N data transfer. SDIO Use of a single-byte transfer when changing the serial port data D0 D1 D2 D4 D5 D6 D7 0 0 0 N N N N SDO format is recommended to prevent unexpected device behavior. Figure 24. Serial Register Interface Timing—LSB First SERIAL INTERFACE PORT PIN DESCRIPTIONS Chip Select Bar (CSB) –1 t f S SCLK Active low input starts and gates a communication cycle. It allows more than one device to be used on the same serial CSB communication lines. CSB must stay low during the entire t t PWH PWL communication cycle. Incomplete data transfers are aborted SCLK anytime the CSB pin goes high. SDO and SDIO pins go to a t DS t DH high impedance state when this input is high. INSTRUCTION BIT 7 INSTRUCTION BIT 6 SDIO Serial Clock (SCLK) Figure 25. Timing Diagram for SPI Register Write The serial clock pin is used to synchronize data to and from the device and to run the internal state machines. The maximum CSB frequency of SCLK is 40 MHz. All data input is registered on the rising edge of SCLK. All data is driven out on the falling edge of SCLK. SCLK t Serial Data I/O (SDIO) DV SDIO DATA BIT N DATA BIT N – 1 Data is always written into the device on this pin. However, SDO SDIO can also function as a bidirectional data output line. Figure 26. Timing Diagram for SPI Register Read Rev. 0 | Page 19 of 28 06569-017 06569-016 06569-015 06569-014 AD9741/AD9743/AD9745/AD9746/AD9747 SPI REGISTER MAP Reading any register returns previously written values for all defined register bits, unless otherwise noted. Change serial port configu- ration or execute software reset in single byte instruction only to avoid unexpected device behavior. Table 14. Register Name Address Default Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SPI Control 0x00 0x00 SDIODIR LSBFIRST SWRESET Data Control 0x02 0x00 DATTYPE ONEPORT INVDCO Power Down 0x03 0x00 PD_DCO PD_AUX2 PD_AUX1 PD_BIAS PC_CLK PD_DAC2 PD_DAC1 DAC Mode Select 0x0A 0x00 DAC1MOD<1:0> DAC2MOD<1:0> DAC1 Gain LSB 0x0B 0xF9 DAC1FSC<7:0> DAC1 Gain MSB 0x0C 0x01 DAC1FSC<9:8> AUX DAC1 LSB 0x0D 0x00 AUXDAC1<7:0> AUX DAC1 MSB 0x0E 0x00 AUX1PIN AUX1DIR AUXDAC1<9:8> DAC2 Gain LSB 0x0F 0xF9 DAC2FSC<7:0> DAC2 Gain MSB 0x10 0x01 DAC2FSC<9:8> AUX DAC2 LSB 0x11 0x00 AUXDAC2<7:0> AUX DAC2 MSB 0x12 0x00 AUX2PIN AUX2DIR AUXDAC2<9:8> Rev. 0 | Page 20 of 28 AD9741/AD9743/AD9745/AD9746/AD9747 SPI REGISTER DESCRIPTIONS Table 15. Register Address Bit Name Description SPI Control 0x00 7 SDIODIR 0, operate SPI in 4-wire mode, SDIO pin operates as an input only 1, operate SPI in 3-wire mode, SDIO pin operates as a bidirectional I/O line 6 LSBFIRST 0, LSBFIRST off, SPI serial data mode is MSB to LSB 1, LSBFIRST on, SPI serial data mode is LSB to MSB 5 SWRESET 0, resume normal operation following software RESET 1, software RESET; loads default values to all registers (except Register 0x00) Data Control 0x02 7 DATTYPE 0, DAC input data is twos complement binary format 1, DAC input data is unsigned binary format 6 ONEPORT 0, normal two port input mode 1, optional single port input mode, interleaved data received on Port 1 only 4 INVDCO 1, inverts data clock output signal Power Down 0x03 7 PD_DCO 1, power down data clock output 5 PD_AUX2 1, power down AUX2 DAC 4 PD_AUX1 1, power down AUX1 DAC 3 PD_BIAS 1, power down reference voltage bias circuit 2 PD_CLK 1, power down DAC clock input circuit 1 PD_DAC2 1, power down DAC2 analog output 0 PD_DAC1 1, power down DAC1 analog output DAC Mode Select 0x0A 3:2 DAC1MOD<1:0> 00, selects normal mode, DAC1 01, selects mix mode, DAC1 10, selects return-to-zero mode, DAC1 1:0 DAC2MOD<1:0> 00, selects normal mode, DAC2 01, selects mix mode, DAC2 10, selects return-to-zero mode, DAC2 DAC1 Gain 0x0B 7:0 DAC1FSC<7:0> DAC1 full-scale 10-bit adjustment word 0x0C 1:0 DAC1FSC<9:8> 0x03FF, sets full-scale current to the maximum value of 31.66 mA 0x01F9, sets full-scale current to the nominal value of 20.0 mA 0x0000, sets full-scale current to the minimum value of 8.64 mA AUX DAC1 0x0D 7:0 AUXDAC1<7:0> Auxiliary DAC1 10-bit output current adjustment word 0x0E 1:0 AUXDAC1<9:8> 0x03FF, sets output current magnitude to 2.0 mA 0x0200, sets output current magnitude to 1.0 mA 0x0000, sets output current magnitude to 0.0 mA 7 AUX1PIN 0, AUX1P output pin is active 1, AUX1N output pin is active 6 AUX1DIR 0, configures AUX1 DAC output to source current 1, configures AUX1 DAC output to sink current DAC2 Gain 0x0F 7:0 DAC2FSC<7:0> DAC2 full-scale 10-bit adjustment word 0x10 1:0 DAC2FSC<9:8> 0x03FF, sets full-scale current to the maximum value of 31.66 mA 0x01F9, sets full-scale current to the nominal value of 20.0 mA 0x0000, sets full-scale current to the minimum value of 8.64 mA AUX DAC2 0x11 7:0 AUXDAC2<7:0> Auxiliary DAC2 10-bit output current adjustment word 0x12 1:0 AUXDAC2<9:8> 0x03FF, sets output current magnitude to 2.0 mA 0x0200, sets output current to 1.0 mA 0x0000, sets output current to 0.0 mA 7 AUX2PIN 0, AUX2P output pin is active 1, AUX2N output pin is active 6 AUX2DIR 0, configures AUX2 DAC output to source current 1, configures AUX2 DAC output to sink current Rev. 0 | Page 21 of 28 AD9741/AD9743/AD9745/AD9746/AD9747 DIGITAL INPUTS AND OUTPUTS In Figure 27, data samples for DAC1 are labeled Ix and data The AD9741/AD9743/AD9745/AD9746/AD9747 can operate samples for DAC2 are labeled Qx. Note that the differential in two data input modes: dual-port mode and single-port mode. DAC clock input is shown in a logical sense (CLKP/CLKN). For the default dual-port mode (ONEPORT = 0), each DAC The data clock output is labeled DCO. receives data from a dedicated input port. In single-port mode (ONEPORT = 1), however, both DACs receive data from Port 1. Setup and hold times are referenced to the positive transition of In single-port mode, DAC1 and DAC2 data is interleaved and the DAC clock. Data should arrive at the input pins such that the IQSEL input is used to steer data to the correct DAC. the minimum setup and hold times are met. Note that the data clock output has a fixed time delay from the DAC clock and In single-port mode, when the IQSEL input is high, Port 1 may be a more convenient signal to use to confirm timing. data is delivered to DAC1 and when IQSEL is low, Port 1 data is delivered to DAC2. The IQSEL input should always coincide SINGLE-PORT MODE TIMING and be time-aligned with the other data bus signals. In single- The single-port mode timing diagram is shown in Figure 28. port mode, minimum setup and hold times apply to the IQSEL CLKP/CLKN input as well as to the input data signals. In dual-port mode, the t DCO IQSEL input is ignored. DCO t In dual-port mode, the data must be delivered at the sample rate DBH t DBS (up to 250 MSPS). In single-port mode, data must be delivered P1D<15:0> I1 Q1 I2 Q2 at twice the sample rate. Because the data inputs function only IQSEL up to 250 MSPS, it is only practical to operate the DAC clock at Figure 28. Data Interface Timing, Single-Port Mode up to 125 MHz in single-port mode. In single-port mode, data for both DACs is received on the In both dual-port and single-port modes, a data clock output Port 1 input bus. Ix and Qx data samples are interleaved and (DCO) signal is available as a fixed time base with which to arrive twice as fast as in dual-port mode. Accompanying the stimulate data from an FPGA. This output signal always data is the IQSEL input signal, which steers incoming data to its operates at the sample rate. It may be inverted by asserting respective DAC. When IQSEL is high, data is steered to DAC1 the INVDCO bit. and when IQSEL is low, data is steered to DAC2. IQSEL should INPUT DATA TIMING coincide as well as be time-aligned with incoming data. With most DACs, signal-to-noise ratio (SNR) is a function of SPI PORT, RESET, AND PIN MODE the relationship between the position of the clock edges and the In general, when the AD9741/AD9743/AD9745/AD9746/ point in time at which the input data changes. The AD9741/ AD9747 are powered up, an active high pulse applied to the AD9743/AD9745/AD9746/AD9747 are rising edge triggered RESET pin should follow. This insures the default state of all and thus exhibit greater SNR sensitivity when the data tran- control register bits. In addition, once the RESET pin goes low, sition is close to this edge. the SPI port can be activated, so CSB should be held high. The specified minimum setup and hold times define a window For applications without a controller, the AD9741/AD9743/ of time, within each data period, where the data is sampled AD9745/AD9746/AD9747 also support pin mode operation, correctly. Generally, users should position data to arrive which allows some functional options to be pin, selected with- relative to the DAC clock and well beyond the minimum out the use of the SPI port. Pin mode is enabled anytime the setup and minimum hold times. This becomes increasingly RESET pin is held high. In pin mode, the four SPI port pins more important at increasingly higher sample rates. take on secondary functions, as shown in Table 16. DUAL-PORT MODE TIMING Table 16. SPI Pin Functions (Pin Mode) The timing diagram for the dual-port mode is shown in Pin Name Pin Mode Description Figure 27. SCLK ONEPORT (Register 0x02, Bit 6), bit value (1/0) CLKP/CLKN equals pin state (high/low) t DCO SDIO DATTYPE (Register 0x02, Bit 7), bit value (1/0) DCO t t DBS DBH equals pin state (high/low) P1D<15:0> I1 I2 I3 I4 CSB Enable Mix Mode, if CSB is high, Register 0x0A is set to 0x05 putting both DAC1 and DAC2 into P2D<15:0> Q1 Q2 Q3 Q4 mix mode Figure 27. Data Interface Timing, Dual-Port Mode SDO Enable full power-down, if SDO is high, Register 0x03 is set to 0xFF Rev. 0 | Page 22 of 28 06569-018 06569-019 AD9741/AD9743/AD9745/AD9746/AD9747 It is important to use CVDD18 and CVSS for any clock bias In pin mode, all register bits are reset to their default values circuit as noise that is coupled onto the clock from another with the exception of those that are controlled by the SPI pins. power supply is multiplied by the DAC input signal and Note also that the RESET pin should be allowed to float and degrades performance. must be pulled low. Connect an external 10 kΩ resistor to FULL-SCALE CURRENT GENERATION DVSS. This avoids unexpected behavior in noisy environments. The full-scale currents on DAC1 and DAC2 are functions of DRIVING THE DAC CLOCK INPUT the current drawn through an external resistor connected to The DAC clock input requires a low jitter drive signal. It is a the FSADJ pin (Pin 54). The required value for this resistor is PMOS differential pair powered from the CVDD18 supply. 10 kΩ. An internal amplifier sets the current through the Each pin can safely swing up to 800 mV p-p at a common- resistor to force a voltage equal to the band gap voltage of 1.2 V. mode voltage of about 400 mV. Though these levels are not This develops a reference current in the resistor of 120 μA. directly LVDS-compatible, CLKP and CLKN can be driven by an ac-coupled, dc-offset LVDS signal, as shown in Figure 29. AD9747 DAC1 GAIN 0.1µF 1.2V BANDGAP DAC1 LVDS_P_IN CLKP REFIO 50Ω CURRENT DAC FULL SCALE 0.1µF FSADJ SCALING REFERENCE CURRENT V = 400mV CM 50Ω DAC2 10kΩ DAC2 GAIN LVDS_N_IN CLKN 0.1µF Figure 33. Reference Circuitry Figure 29. LVDS DAC Clock Drive Circuit REFIO (Pin 55) should be bypassed to ground with a 0.1 μF Using a CMOS or TTL clock is also acceptable for lower sample capacitor. The band gap voltage is present on this pin and can rates. It can be routed through an LVDS translator and then be buffered for use in external circuitry. The typical output ac-coupled as described previously, or alternatively, it can be impedance is near 5 kΩ. If desired, an external reference can transformer-coupled and clamped, as shown in Figure 30. be connected to REFIO to overdrive the internal reference. 0.1µF 50Ω TTL OR CMOS CLKP Internal current mirrors provide a means for adjusting the CLK INPUT DAC full-scale currents. The gain for DAC1 and DAC2 can be adjusted independently by writing to the DAC1FSC<9:0> and CLKN DAC2FSC<9:0> register bits. The default value of 0x01F9 for 50Ω BAV99ZXCT HIGH SPEED the DAC gain registers gives an I of 20 mA, where I equals FS FS DUAL DIODE V = 400mV CM 1.2 V ⎛ 3 ⎞ ⎛ ⎞ IFS= ×⎜72+ × DAC n FSC ⎟ ⎜ ⎟ Figure 30. TTL or CMOS DAC Clock Drive Circuit 10,000 ⎝ 16 ⎠ ⎝ ⎠ If a sine wave signal is available, it can be transformer-coupled The full-scale output current range is 8.6 mA to 31.7 mA for directly to the DAC clock inputs, as shown in Figure 31. register values 0x000 to 0x3FF. SINE WAVE CLKP 35 INPUT 50Ω 30 CLKN 25 V = 400mV CM Figure 31. Sine Wave DAC Clock Drive Circuit 20 The 400 mV common-mode bias voltage can be derived from the CVDD18 supply through a simple divider network, as 15 shown in Figure 32. V = 400mV 10 CM CVDD18 5 1kΩ 0 256 512 768 1024 DAC GAIN CODE 287Ω 0.1µF 1nF Figure 34. I vs. DAC Gain Code FS CVSS Figure 32. DAC Clock VCM Circuit Rev. 0 | Page 23 of 28 06569-023 06569-034 06569-021 06569-022 I (mA) FS 06569-025 06569-024 AD9741/AD9743/AD9745/AD9746/AD9747 systems and other applications requiring good frequency DAC TRANSFER FUNCTION domain performance, this is seldom problematic. Each DAC output of the AD9741/AD9743/AD9745/AD9746/ The quad-switch architecture also supports two additional AD9747 drives complementary current outputs IOUTP and IOUTN. modes of operation; mix mode and return-to-zero (RZ) mode. IOUTP provides a near full-scale current output (IFS) when all bits The waveforms of these two modes are shown in Figure 35. In are high. For example, mix mode, the output is inverted every other half clock cycle. N DAC CODE = 2 − 1 This effectively chops the DAC output at the sample rate. This where: chopping has the effect of frequency shifting the sinc roll-off N = 8-/10-/12-/14-/16-bits (for AD9741/AD9743/AD9745/ from dc to f . Additionally, there is a second subtle effect on DAC AD9746/AD9747 respectively), and IOUTN provides no current. the output spectrum. The shifted spectrum is shaped by a second sinc function with a first null at 2 × f . The reason for this DAC The current output appearing at IOUTP and IOUTN is a function of shaping is that the data is not continuously varying at twice the both the input code and IFS and can be expressed as clock rate, but is simply repeated. N I = (DAC DATA/2 ) × I (1) OUTP FS In RZ mode, the output is set to midscale on every other half N N I = ((2 − 1) − DAC DATA)/2 × I (2) OUTN FS clock cycle. The output is similar to the DAC output in normal N where DAC DATA = 0 to 2 − 1 (decimal representation). mode except that the output pulses are half the width and half the area. Because the output pulses have half the width, the The two current outputs typically drive a resistive load directly sinc function is scaled in frequency by 2 and has a first null at or via a transformer. If dc coupling is required, IOUTP and IOUTN 2 × fDAC. Because the area of the pulses is half that of the pulses should be connected to matching resistive loads (RLOAD) that are in normal mode, the output power is half the normal mode tied to analog common (AVSS). The single-ended voltage output power. output appearing at the IOUTP and IOUTN pins is V = I × R (3) OUTP OUTP LOAD INPUT DATA D D D D D D D D D D 1 2 3 4 5 6 7 8 9 10 V = I × R (4) OUTN OUTN LOAD DAC CLK Note that to achieve the maximum output compliance of 1 V at the nominal 20 mA output current, RLOAD must be set to 50 Ω. Also note that the full-scale value of VOUTP and VOUTN should 4-SWITCH t not exceed the specified output compliance range to maintain DAC OUTPUT specified distortion and linearity performance. (f MIX MODE) S There are two distinct advantages to operating the AD9741/ AD9743/AD9745/AD9746/AD9747 differentially. First, differ- ential operation helps cancel common-mode error sources 4-SWITCH t DAC OUTPUT associated with IOUTP and IOUTN, such as noise, distortion, and (RETURN TO ZERO MODE) dc offsets. Second, the differential code dependent current and subsequent output voltage (VDIFF) is twice the value of the single-ended voltage output (VOUTP or VOUTN), providing 2× Figure 35. Mix Mode and RZ Mode DAC Waveforms signal power to the load. The functions that shape the output spectrums for normal mode, V = (I – I ) × R (5) DIFF OUTP OUTN LOAD mix mode, and RZ mode, are shown in Figure 36. Switching between the modes reshapes the sinc roll off inherent at the ANALOG MODES OF OPERATION DAC output. This ability to change modes in the AD9741/ The AD9741/AD9743/AD9745/AD9746/AD9747 utilize a AD9743/AD9745/D9746/AD9747 makes the parts suitable for proprietary quad-switch architecture that lowers the distortion direct IF applications. The user can place a carrier anywhere in of the DAC output by eliminating a code dependent glitch that the first three Nyquist zones depending on the operating mode occurs with conventional dual-switch architectures. But whereas selected. The performance and maximum amplitude in all three this architecture eliminates the code dependent glitches, it creates zones are impacted by this sinc roll off depending on where the a constant glitch at a rate of 2 × fDAC. For communications carrier is placed, as shown in Figure 36. Rev. 0 | Page 24 of 28 06569-026 AD9741/AD9743/AD9745/AD9746/AD9747 QUADRATURE 0 MODULATOR V+ MIX RZ AD9747 –10 AUX QUAD MOD DAC1 OR I OR Q INPUTS DAC2 NORMAL –20 OPTIONAL AD9747 PASSIVE DAC1 OR –30 FILTERING DAC2 25Ω TO 50Ω 25Ω TO 50Ω –40 0.5 1.5 2 Figure 38. DAC DC Coupled to Quadrature Modulator with Passive DC Shift F S POWER DISSIPATION Figure 36. Transfer Function for Each Analog Operating Mode Figure 39 shows the power dissipation and current draw of the AUXILIARY DACS AD9741/AD9743/AD9745/AD9746/AD9747. It shows that the Two auxiliary DACs are provided on the AD9741/AD9743/ devices have a quiescent power dissipation of about 190 mW. AD9745/AD9746/AD9747. A functional diagram is shown Most of this comes from the AVDD33 supply. Total power in Figure 37. The auxiliary DACs are current output devices dissipation increases about 50% as the clock rate is increased with two output pins, AUXP and AUXN. The active pin can to the maximum clock rate of 250 MHz. be programmed to either source or sink current. When either 350 sinking or sourcing, the full-scale current magnitude is 2 mA. The available compliance range at the auxiliary DAC outputs 310 depends on whether the output is configured to a sink or source f = NYQUIST OUT current. When sourcing current, the compliance voltage is 0 V to 1.6 V, but when sinking current, the output compliance 270 voltage reduces to 0.8 V to 1.6 V. Either output can be used, but f = DC OUT only one output of the auxiliary DAC (P or N) is active at any 230 time. The inactive pin is always in a high impedance state (>100 kΩ). 190 0mA TO 2mA AUXP V BIAS 150 0 25 50 75 100 125 150 175 200 225 250 f (MHz) DAC AUXN 0mA SINK POSITIVE TO Figure 39. AD9747 Power Dissipation vs. f DAC OR OR 2mA SOURCE NEGATIVE 15 Figure 37. Auxiliary DAC Functional Diagram In a single side band transmitter application, the combination of 12 the input referred dc offset voltage of the quadrature modulator and the DAC output offset voltage can result in local oscillator 9 (LO) feedthrough at the modulator output, which degrades AD9747 system performance. The auxiliary DACs can be used to remove 6 the dc offset and the resulting LO feedthrough. The circuit configuration for using the auxiliary DACs for performing AD9741 dc offset correction depends on the details of the DAC and 3 modulator interface. An example of a dc-coupled configuration with low-pass filtering is outlined in the Power Dissipation 0 section. 0 25 50 75 100 125 150 175 200 225 250 f (MHz) DAC Figure 40. DVDD33 Current vs. f DAC Rev. 0 | Page 25 of 28 T(f) (dB) 06569-035 06569-027 P (mW) I (mA) TOTAL DVDD33 06569-029 06569-031 06569-030 AD9741/AD9743/AD9745/AD9746/AD9747 30 Figure 43 shows the power consumption for each power supply domain as well as the total power consumption. Individual bars within each group display the power in full active mode (blue) 24 vs. power for five increasing levels of power-down. 350 AD9747 18 FULL ACTIVE DCO OFF AUX OFF 300 DAC OFF CLK OFF 12 BIAS OFF 250 AD9741 6 200 150 0 0 25 50 75 100 125 150 175 200 225 250 100 f (MHz) DAC Figure 41. DVDD18 Current vs. fDAC 50 15 0 AVDD33 DVDD18 CVDD18 DVDD33 TOT PWR 13 Figure 43. Power Dissipation vs. Power-Down Mode The overall power consumption is dominated by AVDD33 and 11 significant power savings can be achieved simply by disabling the DAC outputs. Also, disabling the DAC outputs is a signifi- cant way to conserve power and still maintain a fast wake-up 9 time. Full power-down disables all circuitry for minimum power consumption. Note, however, that even in full power- 7 down, there is a small power draw (25 mW) due to incoming data activity. To lower power consumption to near zero, all 5 incoming data activity must be halted. 0 25 50 75 100 125 150 175 200 225 250 f (MHz) DAC Figure 42. CVDD18 Current vs. f DAC Rev. 0 | Page 26 of 28 I (mA) I (mA) CVDD18 DVDD18 06569-033 06569-032 P (mW) DISS 06569-045 AD9741/AD9743/AD9745/AD9746/AD9747 OUTLINE DIMENSIONS 0.60 10.00 0.42 0.60 BSC SQ 0.24 0.42 0.24 55 72 1 PIN 1 54 INDICATOR PIN 1 INDICATOR (BOTTOM VIEW) 0.50 9.75 BSC BSC SQ TOP VIEW 4.70 EXPOSED BSC SQ PAD 0.50 37 18 0.40 36 19 0.30 12° MAX 0.80 MAX 8.50 REF 1.00 0.65 TYP EXPOSED PAD MUST BE 0.85 SOLDERED TO PCB AND 0.05 MAX 0.80 CONNECTED TO AVSS. 0.02 NOM COPLANARITY 0.30 SEATING 0.08 0.20 REF PLANE 0.23 0.18 COMPLIANT TO JEDEC STANDARDS MO-220-VNND-4 Figure 44. 72-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 10 mm × 10 mm, Very Thin Quad (CP-72-1) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option 1 AD9741BCPZ −40°C to +85°C 72-Lead LFCSP_VQ CP-72-1 1 AD9741BCPZRL −40°C to +85°C 72-Lead LFCSP_VQ CP-72-1 1 AD9743BCPZ −40°C to +85°C 72-Lead LFCSP_VQ CP-72-1 1 AD9743BCPZRL −40°C to +85°C 72-Lead LFCSP_VQ CP-72-1 1 AD9745BCPZ −40°C to +85°C 72-Lead LFCSP_VQ CP-72-1 1 AD9745BCPZRL −40°C to +85°C 72-Lead LFCSP_VQ CP-72-1 1 AD9746BCPZ −40°C to +85°C 72-Lead LFCSP_VQ CP-72-1 1 AD9746BCPZRL −40°C to +85°C 72-Lead LFCSP_VQ CP-72-1 1 AD9747BCPZ −40°C to +85°C 72-Lead LFCSP_VQ CP-72-1 1 AD9747BCPZRL −40°C to +85°C 72-Lead LFCSP_VQ CP-72-1 1 AD9741-EBZ Evaluation Board 1 AD9743-EBZ Evaluation Board 1 AD9745-EBZ Evaluation Board 1 AD9746-EBZ Evaluation Board 1 AD9747-EBZ Evaluation Board 1 Z = RoHS Compliant Part. Rev. 0 | Page 27 of 28 111507-A AD9741/AD9743/AD9745/AD9746/AD9747 NOTES ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06569-0-5/07(0) Rev. 0 | Page 28 of 28