ANALOG DEVICES AD9744

14-Bit, 210 MSPS ® TxDAC D/A Converter AD9744 FEATURES APPLICATIONS High performance member of pin-compatible Wideband communication transmit channel TxDAC product family Direct IFs Excellent spurious-free dynamic range performance Base stations SFDR to Nyquist Wireless local loops 83 dBc @ 5 MHz output Digital radio links 80 dBc @ 10 MHz output Direct digital synthesis (DDS) 73 dBc @ 20 MHz output Instrumentation SNR @ 5 MHz output, 125 MSPS: 77 dB FUNCTIONAL BLOCK DIAGRAM Twos complement or straight binary data format 3.3V Differential current outputs: 2 mA to 20 mA Power dissipation: 135 mW @ 3.3 V REFLO AVDD ACOM 150pF Power-down mode: 15 mW @ 3.3 V 1.2V REF 0.1µF AD9744 REFIO CURRENT On-chip 1.2 V reference FS ADJ SOURCE CMOS-compatible digital interface ARRAY R SET 3.3V DVDD IOUTA 28-lead SOIC, 28-lead TSSOP, and 32-lead LFCSP packages SEGMENTED LSB DCOM IOUTB SWITCHES SWITCHES Edge-triggered latches CLOCK CLOCK LATCHES MODE DIGITAL DATA INPUTS (DB13–DB0) SLEEP Figure 1. GENERAL DESCRIPTION Edge-triggered input latches and a 1.2 V temperature compen- sated band gap reference have been integrated to provide a 1 The AD9744 is a 14-bit resolution, wideband, third generation complete monolithic DAC solution. The digital inputs support member of the TxDAC series of high performance, low power 3 V CMOS logic families. CMOS digital-to-analog converters (DACs). The TxDAC fam- ily, consisting of pin-compatible 8-, 10-, 12-, and 14-bit DACs, PRODUCT HIGHLIGHTS is specifically optimized for the transmit signal path of commu- 1. The AD9744 is the 14-bit member of the pin compatible TxDAC nication systems. All of the devices share the same interface family, which offers excellent INL and DNL performance. options, small outline package, and pinout, providing an up- 2. Data input supports twos complement or straight binary data ward or downward component selection path based on per- coding. formance, resolution, and cost. The AD9744 offers exceptional 3. High speed, single-ended CMOS clock input supports ac and dc performance while supporting update rates up to 210 MSPS conversion rate. 210 MSPS. 4. Low power: Complete CMOS DAC function operates on 135 mW from a 2.7 V to 3.6 V single supply. The DAC full- The AD9744’s low power dissipation makes it well suited for scale current can be reduced for lower power operation, and a portable and low power applications. Its power dissipation can sleep mode is provided for low power idle periods. be further reduced to a mere 60 mW with a slight degradation 5. On-chip voltage reference: The AD9744 includes a 1.2 V in performance by lowering the full-scale current output. Also, temperature compensated band gap voltage reference. a power-down mode reduces the standby power dissipation to 6. Industry-standard 28-lead SOIC, 28-lead TSSOP, and 32-lead approximately 15 mW. A segmented current source architecture LFCSP packages. is combined with a proprietary switching technique to reduce spurious components and enhance dynamic performance. 1 Protected by U.S. Patent Numbers 5568145, 5689257, and 5703519. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 www.analog.com or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2005 Analog Devices, Inc. All rights reserved. 02913-001 AD9744 TABLE OF CONTENTS Specifications..................................................................................... 3 REVISION HISTORY 4/05—Rev. A to Rev. B DC Specifications ......................................................................... 3 Updated Format..................................................................Universal Dynamic Specifications ............................................................... 4 Changes to General Description .....................................................1 Changes to Product Highlights .......................................................1 Digital Specifications ................................................................... 5 Changes to DC Specifications..........................................................3 Changes to Dynamic Specifications................................................4 Absolute Maximum Ratings............................................................ 6 Changes to Pin Function Description ............................................7 Thermal Characteristics .............................................................. 6 Changes to Figure 6 and Figure 9....................................................9 Inserted New Figure 10; Renumbered Sequentially .....................9 ESD Caution.................................................................................. 6 Changes to Figure 12, Figure 13, Figure 14, and Figure 15....... 10 Pin Configurations and Function Descriptions ........................... 7 Changes to Figure 22 Caption ...................................................... 11 Inserted New Figure 23; Renumbered Sequentially .................. 11 Terminology ...................................................................................... 8 Changes to Functional Description ............................................. 13 Changes to Reference Operation Section.................................... 13 Typical Performance Characteristics ............................................. 9 Added Figure 25; Renumbered Sequentially .............................. 13 Changes to Digital Inputs Section................................................ 15 Functional Description .................................................................. 13 Changes to Figure 31 and Figure 32............................................. 16 Reference Operation .................................................................. 13 Updated Outline Dimensions....................................................... 30 Changes to Ordering Guide .......................................................... 31 Reference Control Amplifier .................................................... 13 5/03—Rev. 0 to Rev. A DAC Transfer Function ............................................................. 14 Added 32-Lead LFCSP Package .......................................Universal Analog Outputs........................................................................... 14 Edits to Features.................................................................................1 Edits to Product Highlights..............................................................1 Digital Inputs .............................................................................. 15 Edits to DC Specifications................................................................2 Edits to Dynamic Specifications......................................................3 Clock Input.................................................................................. 15 Edits to Digital Specifications..........................................................4 DAC Timing................................................................................ 16 Edits to Absolute Maximum Ratings..............................................5 Edits to Thermal Characteristics.....................................................5 Power Dissipation....................................................................... 16 Edits to Ordering Guide ...................................................................5 Edits to Pin Configuration ...............................................................6 Applying the AD9744 ................................................................ 17 Edits to Pin Function Descriptions.................................................6 Differential Coupling Using a Transformer............................ 17 Edits to Figure 2.................................................................................7 Replaced TPCs 1, 4, 7, and 8............................................................8 Differential Coupling Using an Op Amp................................ 17 Edits to Figure 3.............................................................................. 10 Edits to Functional Description ................................................... 10 Single-Ended Unbuffered Voltage Output.............................. 18 Added Clock Input Section........................................................... 12 Single-Ended, Buffered Voltage Output Configuration........ 18 Added Figure 7................................................................................ 12 Edits to DAC Timing Section ....................................................... 12 Power and Grounding Considerations, Power Supply Edits to Sleep Mode Operation Section....................................... 13 Rejection ...................................................................................... 18 Edits to Power Dissipation Section .............................................. 13 Renumbered Figures 8 to Figure 26............................................. 13 Evaluation Board ............................................................................ 20 Added Figure 11 ............................................................................. 13 General Description................................................................... 20 Added Figure 27 to Figure 35 ....................................................... 21 Updated Outline Dimensions....................................................... 26 Outline Dimensions ....................................................................... 30 Ordering Guide........................................................................... 31 Rev. B | Page 2 of 32 AD9744 SPECIFICATIONS DC SPECIFICATIONS T to T , AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, I = 20 mA, unless otherwise noted. MIN MAX OUTFS Table 1. Parameter Min Typ Max Unit RESOLUTION 14 Bits 1 DC ACCURACY Integral Linearity Error (INL) −5 ±0.8 +5 LSB Differential Nonlinearity (DNL) −3 ±0.5 +3 LSB ANALOG OUTPUT Offset Error −0.02 +0.02 % of FSR Gain Error (Without Internal Reference) −0.5 ±0.1 +0.5 % of FSR Gain Error (With Internal Reference) −0.5 ±0.1 +0.5 % of FSR 2 Full-Scale Output Current 2 20 mA Output Compliance Range −1 +1.25 V Output Resistance 100 kΩ Output Capacitance 5 pF REFERENCE OUTPUT Reference Voltage 1.14 1.20 1.26 V 3 Reference Output Current 100 nA REFERENCE INPUT Input Compliance Range 0.1 1.25 V Reference Input Resistance (External Reference) 7 kΩ Small Signal Bandwidth 0.5 MHz TEMPERATURE COEFFICIENTS Offset Drift 0 ppm of FSR/°C Gain Drift (Without Internal Reference) ±50 ppm of FSR/°C Gain Drift (With Internal Reference) ±100 ppm of FSR/°C Reference Voltage Drift ±50 ppm/°C POWER SUPPLY Supply Voltages AVDD 2.7 3.3 3.6 V DVDD 2.7 3.3 3.6 V CLKVDD 2.7 3.3 3.6 V Analog Supply Current (I ) 33 36 mA AVDD 4 Digital Supply Current (I ) 8 9 mA DVDD Clock Supply Current (I ) 5 6 mA CLKVDD Supply Current Sleep Mode (IAVDD) 5 6 mA 4 Power Dissipation 135 145 mW 5 Power Dissipation 145 mW 6 Power Supply Rejection Ratio—AVDD −1 +1 % of FSR/V 6 Power Supply Rejection Ratio—DVDD −0.04 +0.04 % of FSR/V OPERATING RANGE −40 +85 °C 1 Measured at IOUTA, driving a virtual ground. 2 Nominal full-scale current, I , is 32 times the I current. OUTFS REF 3 An external buffer amplifier with input bias current <100 nA should be used to drive any external load. 4 Measured at f = 25 MSPS and f = 1 MHz. CLOCK OUT 5 Measured as unbuffered voltage output with IOUTFS = 20 mA and 50 Ω RLOAD at IOUTA and IOUTB, fCLOCK = 100 MSPS and fOUT = 40 MHz. 6 ±5% power supply variation. Rev. B | Page 3 of 32 AD9744 DYNAMIC SPECIFICATIONS TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, IOUTFS = 20 mA, differential transformer coupled output, 50 Ω doubly terminated, unless otherwise noted. Table 2. Parameter Min Typ Max Unit DYNAMIC PERFORMANCE Maximum Output Update Rate (fCLOCK) 210 MSPS 1 Output Settling Time (tST) (to 0.1%) 11 ns Output Propagation Delay (t ) 1 ns PD Glitch Impulse 5 pV-s 1 Output Rise Time (10% to 90%) 2.5 ns 1 Output Fall Time (10% to 90%) 2.5 ns 2 Output Noise (IOUTFS = 20 mA) 50 pA/√Hz 2 Output Noise (I = 2 mA) 30 pA/√Hz OUTFS 3 Noise Spectral Density −155 dBm/Hz AC LINEARITY Spurious-Free Dynamic Range to Nyquist f = 25 MSPS; f = 1.00 MHz CLOCK OUT 0 dBFS Output 77 90 dBc −6 dBFS Output 87 dBc −12 dBFS Output 82 dBc −18 dBFS Output 82 dBc f = 65 MSPS; f = 1.00 MHz 85 dBc CLOCK OUT f = 65 MSPS; f = 2.51 MHz 84 dBc CLOCK OUT f = 65 MSPS; f = 10 MHz 80 dBc CLOCK OUT fCLOCK = 65 MSPS; fOUT = 15 MHz 75 dBc fCLOCK = 65 MSPS; fOUT = 25 MHz 74 dBc f = 165 MSPS; f = 21 MHz 73 dBc CLOCK OUT f = 165 MSPS; f = 41 MHz 60 dBc CLOCK OUT f = 210 MSPS; f = 41 MHz 68 dBc CLOCK OUT fCLOCK = 210 MSPS; fOUT = 69 MHz 64 dBc Spurious-Free Dynamic Range Within a Window fCLOCK = 25 MSPS; fOUT = 1.00 MHz; 2 MHz Span 84 90 dBc f = 50 MSPS; f = 5.02 MHz; 2 MHz Span 90 dBc CLOCK OUT f = 65 MSPS; f = 5.03 MHz; 2.5 MHz Span 87 dBc CLOCK OUT f = 125 MSPS; f = 5.04 MHz; 4 MHz Span 87 dBc CLOCK OUT Total Harmonic Distortion fCLOCK = 25 MSPS; fOUT = 1.00 MHz −86 −77 dBc fCLOCK = 50 MSPS; fOUT = 2.00 MHz −77 dBc f = 65 MSPS; f = 2.00 MHz −77 dBc CLOCK OUT f = 125 MSPS; f = 2.00 MHz −77 dBc CLOCK OUT Signal-to-Noise Ratio fCLOCK = 65 MSPS; fOUT = 5 MHz; IOUTFS = 20 mA 82 dB fCLOCK = 65 MSPS; fOUT = 5 MHz; IOUTFS = 5 mA 88 dB f = 125 MSPS; f = 5 MHz; I = 20 mA 77 dB CLOCK OUT OUTFS f = 125 MSPS; f = 5 MHz; I = 5 mA 78 dB CLOCK OUT OUTFS f = 165 MSPS; f = 5 MHz; I = 20 mA 70 dB CLOCK OUT OUTFS fCLOCK = 165 MSPS; fOUT = 5 MHz; IOUTFS = 5 mA 70 dB fCLOCK = 210 MSPS; fOUT = 5 MHz; IOUTFS = 20 mA 74 dB fCLOCK = 210 MSPS; fOUT = 5 MHz; IOUTFS = 5 mA 67 dB Rev. B | Page 4 of 32 AD9744 Parameter Min Typ Max Unit Multitone Power Ratio (8 Tones at 400 kHz Spacing) fCLOCK = 78 MSPS; fOUT = 15.0 MHz to 18.2 MHz 0 dBFS Output 66 dBc −6 dBFS Output 68 dBc −12 dBFS Output 62 dBc −18 dBFS Output 61 dBc 1 Measured single-ended into 50 Ω load. 2 Output noise is measured with a full-scale output set to 20 mA with no conversion activity. It is a measure of the thermal noise only. 3 Noise spectral density is the average noise power normalized to a 1 Hz bandwidth, with the DAC converting and producing an output tone. DIGITAL SPECIFICATIONS T to T , AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, I = 20 mA, unless otherwise noted. MIN MAX OUTFS Table 3. Parameter Min Typ Max Unit 1 DIGITAL INPUTS Logic 1 Voltage 2.1 3 V Logic 0 Voltage 0 0.9 V Logic 1 Current −10 +10 µA Logic 0 Current −10 +10 µA Input Capacitance 5 pF Input Setup Time (t ) 2.0 ns S Input Hold Time (t ) 1.5 ns H Latch Pulse Width (tLPW) 1.5 ns 2 CLK INPUTS Input Voltage Range 0 3 V Common-Mode Voltage 0.75 1.5 2.25 V Differential Voltage 0.5 1.5 V 1 Includes CLOCK pin on SOIC/TSSOP packages and CLK+ pin on LFCSP package in single-ended clock input mode. 2 Applicable to CLK+ and CLK– inputs when configured for differential or PECL clock input mode. DB0–DB13 t t S H CLOCK t LPW t PD t ST IOUTA 0.1% OR 0.1% IOUTB Figure 2. Timing Diagram Rev. B | Page 5 of 32 02913-002 AD9744 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter With Respect to Min Max Unit AVDD ACOM −0.3 +3.9 V DVDD DCOM −0.3 +3.9 V CLKVDD CLKCOM −0.3 +3.9 V ACOM DCOM −0.3 +0.3 V ACOM CLKCOM −0.3 +0.3 V DCOM CLKCOM −0.3 +0.3 V AVDD DVDD −3.9 +3.9 V AVDD CLKVDD −3.9 +3.9 V DVDD CLKVDD −3.9 +3.9 V CLOCK, SLEEP DCOM −0.3 DVDD + 0.3 V Digital Inputs, MODE DCOM −0.3 DVDD + 0.3 V IOUTA, IOUTB ACOM −1.0 AVDD + 0.3 V REFIO, REFLO, FS ADJ ACOM −0.3 AVDD + 0.3 V CLK+, CLK−, CMODE CLKCOM −0.3 CLKVDD + 0.3 V Junction Temperature 150 °C Storage Temperature −65 +150 °C Lead Temperature (10 sec) 300 °C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may effect device reliability. 1 THERMAL CHARACTERISTICS Thermal Resistance 28-Lead 300-Mil SOIC θJA = 55.9°C/W 28-Lead TSSOP θ = 67.7°C/W JA 32-Lead LFCSP θ = 32.5°C/W JA 1 Thermal impedance measurements were taken on a 4-layer board in still air, in accordance with EIA/JESD51-7. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprie- tary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. B | Page 6 of 32 AD9744 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 1 28 (MSB) DB13 CLOCK DB12 2 27 DVDD 3 26 DB11 DCOM 4 25 DB10 MODE DB9 5 24 AVDD DB7 1 24 FS ADJ PIN 1 AD9744 INDICATOR 6 23 DB6 2 23 REFIO DB8 RESERVED TOP VIEW DVDD 3 22 ACOM 7 DB7 22 IOUTA (Not to Scale) AD9744 DB5 4 21 IOUTA DB4 5 TOP VIEW 20 IOUTB DB6 8 21 IOUTB DB3 6 (Not to Scale) 19 ACOM DB5 9 20 ACOM DB2 7 18 AVDD DB1 8 17 AVDD DB4 10 19 NC 11 18 DB3 FS ADJ DB2 12 17 REFIO DB1 13 16 REFLO (LSB) DB0 14 15 SLEEP NC = NO CONNECT NC = NO CONNECT Figure 4. 32-Lead LFCSP Figure 3. 28-Lead SOIC and TSSOP Table 5. Pin Function Descriptions SOIC/TSSOP LFCSP Pin No. Pin No. Mnemonic Description 1 27 DB13 Most Significant Data Bit (MSB). 2 to 13 28 to 32, DB12 to Data Bits 12 to 1. 1, 2, 4 to 8 DB1 14 9 DB0 Least Significant Data Bit (LSB). 15 25 SLEEP Power-Down Control Input. Active high. Contains active pull-down circuit; it may be left unterminated if not used. 16 N/A REFLO Reference Ground when Internal 1.2 V Reference Used. Connect to ACOM for both internal and external reference operation modes. 17 23 REFIO Reference Input/Output. Serves as reference input when using external reference. Serves as 1.2 V reference output when using internal reference. Requires 0.1 µF capacitor to ACOM when using internal reference. 18 24 FS ADJ Full-Scale Current Output Adjust. 19 N/A NC No Internal Connection. 20 19, 22 ACOM Analog Common. 21 20 IOUTB Complementary DAC Current Output. Full-scale current when all data bits are 0s. 22 21 IOUTA DAC Current Output. Full-scale current when all data bits are 1s. 23 N/A RESERVED Reserved. Do not connect to common or supply. 24 17, 18 AVDD Analog Supply Voltage (3.3 V). 25 16 MODE Selects Input Data Format. Connect to DCOM for straight binary, DVDD for twos complement. N/A 15 CMODE Clock Mode Selection. Connect to CLKCOM for single-ended clock receiver (drive CLK+ and float CLK−). Connect to CLKVDD for differential receiver. Float for PECL receiver (terminations on-chip). 26 10, 26 DCOM Digital Common. 27 3 DVDD Digital Supply Voltage (3.3 V). 28 N/A CLOCK Clock Input. Data latched on positive edge of clock. N/A 12 CLK+ Differential Clock Input. N/A 13 CLK− Differential Clock Input. N/A 11 CLKVDD Clock Supply Voltage (3.3 V). N/A 14 CLKCOM Clock Common. Rev. B | Page 7 of 32 (LSB) DB0 9 32 DB8 DCOM 10 31 DB9 CLKVDD 11 30 DB10 CLK+ 12 29 DB11 CLK– 13 28 DB12 CLKCOM 14 27 DB13 (MSB) CMODE 15 26 DCOM MODE 16 25 SLEEP 02913-003 02913-004 AD9744 TERMINOLOGY Linearity Error (Also Called Integral Nonlinearity or INL) Power Supply Rejection It is defined as the maximum deviation of the actual analog The maximum change in the full-scale output as the supplies output from the ideal output, determined by a straight line are varied from nominal to minimum and maximum specified drawn from zero to full scale. voltages. Differential Nonlinearity (or DNL) Settling Time DNL is the measure of the variation in analog value, normalized The time required for the output to reach and remain within a to full scale, associated with a 1 LSB change in digital input code. specified error band about its final value, measured from the start of the output transition. Monotonicity A DAC is monotonic if the output either increases or remains Glitch Impulse constant as the digital input increases. Asymmetrical switching times in a DAC give rise to undesired output transients that are quantified by a glitch impulse. It is Offset Error specified as the net area of the glitch in pV-s. The deviation of the output current from the ideal of zero is called the offset error. For IOUTA, 0 mA output is expected Spurious-Free Dynamic Range when the inputs are all 0s. For IOUTB, 0 mA output is expected The difference, in dB, between the rms amplitude of the output when all inputs are set to 1s. signal and the peak spurious signal over the specified bandwidth. Gain Error Total Harmonic Distortion (THD) The difference between the actual and ideal output span. The THD is the ratio of the rms sum of the first six harmonic actual span is determined by the output when all inputs are set components to the rms value of the measured input signal. It is to 1s minus the output when all inputs are set to 0s. expressed as a percentage or in decibels (dB). Output Compliance Range Multitone Power Ratio The range of allowable voltage at the output of a current output The spurious-free dynamic range containing multiple carrier DAC. Operation beyond the maximum compliance limits may tones of equal amplitude. It is measured as the difference cause either output stage saturation or breakdown, resulting in between the rms amplitude of a carrier tone to the peak spuri- nonlinear performance. ous signal in the region of a removed tone. Temperature Drift It is specified as the maximum change from the ambient (25°C) value to the value at either TMIN or TMAX. For offset and gain drift, the drift is reported in ppm of full-scale range (FSR) per °C. For reference drift, the drift is reported in ppm per °C. 3.3V REFLO AVDD ACOM 150pF 1.2V REF AD9744 0.1µF REFIO PMOS FS ADJ CURRENT SOURCE ARRAY MINI-CIRCUITS R SET T1-1T RHODE & SCHWARZ 2kΩ 3.3V DVDD IOUTA FSEA30 LSB SEGMENTED SWITCHES DCOM SPECTRUM IOUTB SWITCHES FOR DB13–DB5 ANALYZER CLOCK MODE LATCHES DVDD 50Ω SLEEP 50Ω DCOM RETIMED 50Ω CLOCK DIGITAL OUTPUT* DATA CLOCK *AWG2021 CLOCK RETIMED OUTPUT SO THAT THE DIGITAL DATA LECROY 9210 TEKTRONIX AWG-2021 TRANSITIONS ON FALLING EDGE PULSE GENERATOR WITH OPTION 4 OF 50% DUTY CYCLE CLOCK. Figure 5. Basic AC Characterization Test Set-Up (SOIC/TSSOP Packages) Rev. B | Page 8 of 32 02913-005 AD9744 TYPICAL PERFORMANCE CHARACTERISTICS 95 95 210MSPS (LFCSP) 90 90 125MSPS –6dBFS (LFCSP) 85 85 165MSPS (LFCSP) –12dBFS (LFCSP) 80 80 65MSPS 75 75 210MSPS 70 70 165MSPS 65 65 125MSPS (LFCSP) –12dBFS 60 60 0dBFS 0dBFS (LFCSP) 55 55 –6dBFS 50 50 45 45 010 20 30 40 50 60 1 10 100 f (MHz) f (MHz) OUT OUT Figure 9. SFDR vs. f @ 165 MSPS Figure 6. SFDR vs. f @ 0 dBFS OUT OUT 95 95 0dBFS (LFCSP) 90 90 85 85 –6dBFS (LFCSP) –6dBFS –12dBFS (LFCSP) 80 80 75 75 0dBFS –12dBFS 70 70 65 65 60 60 0dBFS 55 55 –12dBFS –6dBFS 50 50 45 45 0 5 10 15 20 25 010 20 30 40 50 60 70 80 f (MHz) f (MHz) OUT OUT @ 65 MSPS Figure 10. SFDR vs. f @ 210 MSPS Figure 7. SFDR vs. fOUT OUT 95 95 90 90 20mA 85 85 80 80 75 75 –6dBFS 10mA 70 70 –12dBFS 65 5mA 65 60 0dBFS 60 55 55 50 50 45 45 0 5 10 15 20 25 0 5 10 15 20 25 30 35 40 45 f (MHz) OUT f (MHz) OUT Figure 11. SFDR vs. f and I @ 65 MSPS and 0 dBFS OUT OUTFS @ 125 MSPS Figure 8. SFDR vs. fOUT Rev. B | Page 9 of 32 SFDR (dBc) SFDR (dBc) SFDR (dBc) 02913-012 02913-009 02913-006 SFDR (dBc) SFDR (dBc) SFDR (dBc) 02913-007 02913-010 02913-055 AD9744 95 95 65MSPS (8.3,10.3) 90 90 165MSPS (22.6, 24.6) 85 85 65MSPS 210MSPS (LFCSP) 80 80 75 75 210MSPS (29,31) 78MSPS (10.1, 12.1) 70 70 210MSPS 210MSPS (29,31) 65 65 LFCSP 125MSPS 125MSPS (16.9, 18.9) 165MSPS 60 60 55 55 50 50 45 45 –25 –20 –15 –10 –5 0 –25 –20 –15 –10 –5 0 A (dBFS) A (dBFS) OUT OUT Figure 12. Single-Tone SFDR vs. A @ f = f /11 Figure 15. Dual-Tone IMD vs. A @ f = f /7 OUT OUT CLOCK OUT OUT CLOCK 1.5 95 165MSPS (LFCSP) 90 1.0 65MSPS 85 125MSPS (LFCSP) 80 0.5 75 0 70 65 –0.5 60 165MSPS 55 125MSPS –1.0 210MSPS (LFCSP) 50 210MSPS –1.5 45 0 4096 8192 12288 16384 –25 –20 –15 –10 –5 0 CODE (dBFS) A OUT Figure 16. Typical INL Figure 13. Single-Tone SFDR vs. AOUT @ fOUT = fCLOCK/5 90 1.0 I FS = 20mA LFCSP OUT 0.8 85 I FS = 20mA OUT 0.6 80 I FS = 10mA LFCSP OUT 0.4 75 0.2 70 0 –0.2 65 I FS = 10mA OUT –0.4 I FS = 5mA OUT 60 I FS = 5mA LFCSP OUT –0.6 55 –0.8 50 –1.0 0 30 60 90 120 150 180 210 0 4096 8192 12288 16384 CODE f (MSPS) CLOCK Figure 17. Typical DNL Figure 14. SNR vs. fCLOCK and IOUTFS @ fOUT = 5 MHz and 0 dBFS Rev. B | Page 10 of 32 SNR (dB) SFDR (dBc) SFDR (dBc) 02913-011 02913-008 02913-013 SFDR (dBc) ERROR (LSB) ERROR (LSB) 02913-018 02913-015 02913-014 AD9744 95 0 f = 78MSPS CLOCK 90 –10 f = 15.0MHz 4MHz OUT1 f = 15.4MHz OUT2 85 –20 f = 15.8MHz OUT3 f = 16.2MHz OUT4 80 –30 SFDR = 75dBc AMPLITUDE = 0dBFS 75 –40 19MHz 70 –50 65 –60 34MHz 60 –70 49MHz 55 –80 50 –90 45 –100 –40 –20 020 40 60 80 1 6 11 16 21 26 31 36 TEMPERATURE (°C) FREQUENCY (MHz) Figure 18. SFDR vs. Temperature @ 165 MSPS, 0 dBFS Figure 21. Four-Tone SFDR 0 –20 –39.01dBm f = 78MSPS CLOCK 29.38000000MHz –10 –30 CHPWR –19.26dBm f = 15.0MHz OUT ACP UP –64.98dB –20 SFDR = 79dBc –40 ACP LOW +0.55dB AMPLITUDE = 0dBFS ALT1 UP –66.26dB –30 –50 ALT1 LOW –64.23dB –40 –60 –50 –70 –60 –80 –70 –90 C0 C0 C12 C12 –80 –100 C11 C11 CU1 –90 –110 CU1 CU2 CU2 –100 –120 1 6 11 16 21 26 31 36 CENTER 33.22 MHz 3 MHz SPAN 30 MHz FREQUENCY (MHz) FREQUENCY (MHz) Figure 19. Single-Tone SFDR Figure 22. Two-Carrier UMTS Spectrum, fCLOCK = 122.88 MSPS (ACLR = 64 dB) LFCSP Package 0 –20 RES BW = 30kHz f = 78MSPS CLOCK –10 –30 VBW = 300kHz f = 15.0MHz OUT1 ATTEN = 8dB f = 15.4MHz OUT2 –20 AVG = 50 –40 SFDR = 77dBc AMPLITUDE = 0dBFS –30 –50 –40 –60 –50 –70 –60 –80 –70 –90 –80 –100 –90 –110 –100 –120 1 6 11 16 21 26 31 36 CENTER 10MHz SPAN 18MHz LOWER UPPER FREQUENCY (MHz) FREQ OFFSET REF BW dBc dBm dBc dBm 5.000MHz 3.840MHz –74.62 –84.12 –75.04 –84.54 Figure 20. Dual-Tone SFDR Figure 23. Single-Carrier UMTS Spectrum, fCLOCK = 61.44 MSPS (ACLR = 74 dB) LFCSP Package Rev. B | Page 11 of 32 MAGNITUDE (dBm) MAGNITUDE (dBm) SFDR (dBc) 02913-019 02913-016 02913-020 MAGNITUDE (dBm) MAGNITUDE (dBm) MAGNITUDE (dBm) 02913-056 02913-017 02913-021 AD9744 3.3V REFLO AVDD ACOM 150pF +1.2V REF AD9744 V REFIO REFIO PMOS I FS ADJ REF CURRENT SOURCE 0.1µF ARRAY R SET V = V – V DIFF OUTA OUTB 2kΩ DVDD 3.3V IOUTA IOUTA V LSB OUTA SEGMENTED SWITCHES DCOM IOUTB IOUTB SWITCHES FOR DB13–DB5 V R LOAD OUTB 50Ω R LOAD CLOCK CLOCK MODE 50Ω LATCHES SLEEP DIGITAL DATA INPUTS (DB13–DB0) Figure 24. Simplified Block Diagram (SOIC/TSSOP Packages) Rev. B | Page 12 of 32 02913-022 AD9744 FUNCTIONAL DESCRIPTION input bias current of less than 100 nA should be used. An ex- Figure 24 shows a simplified block diagram of the AD9744. The ample of the use of the internal reference is shown in Figure 26. AD9744 consists of a DAC, digital control logic, and full-scale output current control. The DAC contains a PMOS current AVDD source array capable of providing up to 20 mA of full-scale cur- 84µA rent (I ). The array is divided into 31 equal currents that OUTFS make up the five most significant bits (MSBs). The next four REFIO bits, or middle bits, consist of 15 equal current sources whose 7kΩ value is 1/16th of an MSB current source. The remaining LSBs are binary weighted fractions of the middle bits current sources. Implementing the middle and lower bits with current sources, REFLO instead of an R-2R ladder, enhances its dynamic performance for multitone or low amplitude signals and helps maintain the Figure 25. Equivalent Circuit of Internal Reference DAC’s high output impedance (that is, >100 kΩ). 3.3V All of these current sources are switched to one or the other of OPTIONAL EXTERNAL the two output nodes, that is, IOUTA or IOUTB, via PMOS REF BUFFER REFLO AVDD 150pF differential current switches. The switches are based on the +1.2V REF architecture that was pioneered in the AD9764 family, with REFIO CURRENT ADDITIONAL further refinements to reduce distortion contributed by the FS ADJ SOURCE 0.1µF LOAD ARRAY switching transient. This switch architecture also reduces vari- 2kΩ AD9744 ous timing errors and provides matching complementary drive signals to the inputs of the differential current switches. Figure 26. Internal Reference Configuration The analog and digital sections of the AD9744 have separate An external reference can be applied to REFIO, as shown in power supply inputs, that is, AVDD and DVDD, that can Figure 27. The external reference may provide either a fixed operate independently over a 2.7 V to 3.6 V range. The reference voltage to enhance accuracy and drift performance or digital section, which is capable of operating at a rate of up a varying reference voltage for gain control. Note that the 0.1 µF to 210 MSPS, consists of edge-triggered latches and segment compensation capacitor is not required since the internal refer- decoding logic circuitry. The analog section includes the PMOS ence is overridden, and the relatively high input impedance of current sources, the associated differential switches, a 1.2 V REFIO minimizes any loading of the external reference. band gap voltage reference, and a reference control amplifier. 3.3V The DAC full-scale output current is regulated by the reference control amplifier and can be set from 2 mA to 20 mA via an REFLO AVDD AVDD external resistor, RSET, connected to the full-scale adjust 150pF +1.2V REF (FS ADJ) pin. The external resistor, in combination with both V REFIO REFIO EXTERNAL the reference control amplifier and voltage reference VREFIO, sets CURRENT REF SOURCE FS ADJ the reference current IREF, which is replicated to the segmented ARRAY R I = SET REF current sources with the proper scaling factor. The full-scale V /R REFIO SET REFERENCE current, I , is 32 times I . OUTFS REF AD9744 CONTROL AMPLIFIER REFERENCE OPERATION Figure 27. External Reference Configuration The AD9744 contains an internal 1.2 V band gap reference. The internal reference cannot be disabled, but can be easily overrid- REFERENCE CONTROL AMPLIFIER den by an external reference with no effect on performance. The AD9744 contains a control amplifier that is used to regulate Figure 25 shows an equivalent circuit of the band gap reference. the full-scale output current, IOUTFS. The control amplifier is REFIO serves as either an output or an input depending on configured as a V-I converter, as shown in Figure 26, so that its whether the internal or an external reference is used. To use the current output, I , is determined by the ratio of the V and REF REFIO internal reference, simply decouple the REFIO pin to ACOM an external resistor, R , as stated in Equation 4. I is copied SET REF with a 0.1 µF capacitor and connect REFLO to ACOM via a to the segmented current sources with the proper scale factor to resistance less than 5 Ω. The internal reference voltage will be set I , as stated in Equation 3. OUTFS present at REFIO. If the voltage at REFIO is to be used any- where else in the circuit, an external buffer amplifier with an Rev. B | Page 13 of 32 02913-057 02913-024 02913-023 AD9744 The control amplifier allows a wide (10:1) adjustment span of Substituting the values of IOUTA, IOUTB, I , and V can be REF DIFF I over a 2 mA to 20 mA range by setting I between expressed as OUTFS REF 62.5 µA and 625 µA. The wide adjustment span of I pro- OUTFS V =[(2× DAC CODE−16383)/16384] DIFF vides several benefits. The first relates directly to the power (8) () 32× R / R ×V dissipation of the AD9744, which is proportional to IOUTFS LOAD SET REFIO (refer to the Power Dissipation section). The second relates to Equation 7 and Equation 8 highlight some of the advantages the 20 dB adjustment, which is useful for system gain control of operating the AD9744 differentially. First, the differential purposes. operation helps cancel common-mode error sources associated The small signal bandwidth of the reference control amplifier is with IOUTA and IOUTB, such as noise, distortion, and dc approximately 500 kHz and can be used for low frequency small offsets. Second, the differential code dependent current and signal multiplying applications. subsequent voltage, V , is twice the value of the single-ended DIFF voltage output (that is, V or V ), thus providing twice the OUTA OUTB DAC TRANSFER FUNCTION signal power to the load. Both DACs in the AD9744 provide complementary current Note that the gain drift temperature performance for a single- outputs, IOUTA and IOUTB. IOUTA provides a near full-scale ended (VOUTA and VOUTB) or differential output (VDIFF) of the current output, I , when all bits are high (that is, DAC OUTFS AD9744 can be enhanced by selecting temperature tracking CODE = 16383), while IOUTB, the complementary output, resistors for RLOAD and RSET due to their ratiometric relationship, provides no current. The current output appearing at IOUTA as shown in Equation 8. and IOUTB is a function of both the input code and IOUTFS and can be expressed as ANALOG OUTPUTS IOUTA=(DAC CODE/16384)× I (1) The complementary current outputs in each DAC, IOUTA, OUTFS and IOUTB may be configured for single-ended or differential IOUTB=(16383− DAC CODE)/16384× I (2) operation. IOUTA and IOUTB can be converted into comple- OUTFS mentary single-ended voltage outputs, V and V , via a OUTA OUTB where DAC CODE = 0 to 16383 (that is, decimal representation). load resistor, R , as described in the DAC Transfer Function LOAD section by Equation 5 through Equation 8. The differential As mentioned previously, I is a function of the reference OUTFS voltage, VDIFF, existing between VOUTA and VOUTB, can also be current I , which is nominally set by a reference voltage, REF converted to a single-ended voltage via a transformer or V , and external resistor, R . It can be expressed as REFIO SET differential amplifier configuration. The ac performance of the AD9744 is optimum and specified using a differential trans- I =32× I (3) OUTFS REF former-coupled output in which the voltage swing at IOUTA where and IOUTB is limited to ±0.5 V. I = V /R (4) The distortion and noise performance of the AD9744 can be REF REFIO SET enhanced when it is configured for differential operation. The The two current outputs will typically drive a resistive load di- common-mode error sources of both IOUTA and IOUTB can rectly or via a transformer. If dc coupling is required, IOUTA be significantly reduced by the common-mode rejection of a and IOUTB should be directly connected to matching resistive transformer or differential amplifier. These common-mode loads, R , that are tied to analog common, ACOM. Note that LOAD error sources include even-order distortion products and noise. R may represent the equivalent load resistance seen by LOAD The enhancement in distortion performance becomes more IOUTA or IOUTB as would be the case in a doubly terminated significant as the frequency content of the reconstructed wave- 50 Ω or 75 Ω cable. The single-ended voltage output appearing form increases and/or its amplitude decreases. This is due to the at the IOUTA and IOUTB nodes is simply first-order cancellation of various dynamic common-mode distortion mechanisms, digital feedthrough, and noise. V = IOUTA× R (5) OUTA LOAD Performing a differential-to-single-ended conversion via a V = IOUTB× R (6) OUTB LOAD transformer also provides the ability to deliver twice the reconstructed signal power to the load (assuming no source Note that the full-scale value of VOUTA and VOUTB should not termination). Since the output currents of IOUTA and IOUTB exceed the specified output compliance range to maintain speci- are complementary, they become additive when processed fied distortion and linearity performance. differentially. A properly selected transformer will allow the ( ) AD9744 to provide the required power and voltage levels to V = IOUTA− IOUTB× R (7) DIFF LOAD different loads. Rev. B | Page 14 of 32 AD9744 The output impedance of IOUTA and IOUTB is determined CLOCK INPUT by the equivalent parallel combination of the PMOS switches SOIC/TSSOP Packages associated with the current sources and is typically 100 kΩ in The 28-lead package options have a single-ended clock input parallel with 5 pF. It is also slightly dependent on the output (CLOCK) that must be driven to rail-to-rail CMOS levels. The voltage (that is, VOUTA and VOUTB) due to the nature of a PMOS quality of the DAC output is directly related to the clock quality, device. As a result, maintaining IOUTA and/or IOUTB at a and jitter is a key concern. Any noise or jitter in the clock will virtual ground via an I-V op amp configuration will result in translate directly into the DAC output. Optimal performance the optimum dc linearity. Note that the INL/DNL specifications will be achieved if the CLOCK input has a sharp rising edge, for the AD9744 are measured with IOUTA maintained at a since the DAC latches are positive edge triggered. virtual ground via an op amp. LFCSP Package IOUTA and IOUTB also have a negative and positive voltage A configurable clock input is available in the LFCSP package, compliance range that must be adhered to in order to achieve which allows for one single-ended and two differential modes. optimum performance. The negative output compliance range The mode selection is controlled by the CMODE input, as of −1 V is set by the breakdown limits of the CMOS process. summarized in Table 6. Connecting CMODE to CLKCOM Operation beyond this maximum limit may result in a break- selects the single-ended clock input. In this mode, the CLK+ down of the output stage and affect the reliability of the input is driven with rail-to-rail swings and the CLK– input is AD9744. left floating. If CMODE is connected to CLKVDD, the differen- The positive output compliance range is slightly dependent on tial receiver mode is selected. In this mode, both inputs are high the full-scale output current, IOUTFS. It degrades slightly from its impedance. The final mode is selected by floating CMODE. nominal 1.2 V for an IOUTFS = 20 mA to 1 V for an IOUTFS = 2 mA. This mode is also differential, but internal terminations for The optimum distortion performance for a single-ended or positive emitter-coupled logic (PECL) are activated. There is no differential output is achieved when the maximum full-scale significant performance difference among any of the three clock signal at IOUTA and IOUTB does not exceed 0.5 V. input modes. Table 6. Clock Mode Selection DIGITAL INPUTS CMODE Pin Clock Input Mode The AD9744 digital section consists of 14 input bit channels CLKCOM Single-Ended and a clock input. The 14-bit parallel data inputs follow stan- CLKVDD Differential dard positive binary coding, where DB13 is the most significant Float PECL bit (MSB) and DB0 is the least significant bit (LSB). IOUTA produces a full-scale output current when all data bits are at The single-ended input mode operates in the same way as the Logic 1. IOUTB produces a complementary output with the CLOCK input in the 28-lead packages, as previously described. full-scale current split between the two outputs as a function of In the differential input mode, the clock input functions as a the input code. high impedance differential pair. The common-mode level of DVDD the CLK+ and CLK− inputs can vary from 0.75 V to 2.25 V, and the differential voltage can be as low as 0.5 V p-p. This mode can be used to drive the clock with a differential sine wave since DIGITAL INPUT the high gain bandwidth of the differential inputs will convert the sine wave into a single-ended square wave internally. The final clock mode allows for a reduced external component Figure 28. Equivalent Digital Input count when the DAC clock is distributed on the board using PECL logic. The internal termination configuration is shown in The digital interface is implemented using an edge-triggered Figure 29. These termination resistors are untrimmed and can master/slave latch. The DAC output updates on the rising edge vary up to ±20%. However, matching between the resistors of the clock and is designed to support a clock rate as high as should generally be better than ±1%. 210 MSPS. The clock can be operated at any duty cycle that meets the specified latch pulse width. The setup and hold times can also be varied within the clock cycle as long as the specified minimum times are met, although the location of these transition edges may affect digital feedthrough and distortion performance. Best performance is typically achieved when the input data transitions on the falling edge of a 50% duty cycle clock. Rev. B | Page 15 of 32 02913-025 AD9744 POWER DISSIPATION AD9744 CLK+ The power dissipation, PD, of the AD9744 is dependent on sev- CLOCK TO DAC CORE RECEIVER eral factors that include: CLK– 50Ω 50Ω • The power supply voltages (AVDD, CLKVDD, and DVDD) V = 1.3V NOM TT • The full-scale current output IOUTFS • The update rate fCLOCK Figure 29. Clock Termination in PECL Mode • The reconstructed digital input waveform DAC TIMING The power dissipation is directly proportional to the analog Input Clock and Data Timing Relationship supply current, I , and the digital supply current, I . I AVDD DVDD AVDD is directly proportional to I , as shown in Figure 31, and is OUTFS Dynamic performance in a DAC is dependent on the relation- insensitive to f . Conversely, I is dependent on both the CLOCK DVDD ship between the position of the clock edges and the time at digital input waveform, fCLOCK, and digital supply DVDD. which the input data changes. The AD9744 is rising edge trig- Figure 32 shows IDVDD as a function of full-scale sine wave gered, and so exhibits dynamic performance sensitivity when output ratios (fOUT/fCLOCK) for various update rates with the data transition is close to this edge. In general, the goal DVDD = 3.3 V. when applying the AD9744 is to make the data transition close to the falling clock edge. This becomes more important as the 35 sample rate increases. Figure 30 shows the relationship of SFDR to clock placement with different sample rates. Note that at the 30 lower sample rates, more tolerance is allowed in clock place- ment, while at higher rates, more care must be taken. 25 75 20 70 15 65 60 20MHz SFDR 10 55 50MHz SFDR 0 2 4 6 8 101214 161820 50 I (mA) OUTFS 45 Figure 31. IAVDD vs. IOUTFS 40 20 50MHz SFDR 35 18 –3 –2 –1 0 1 2 3 210MSPS ns 16 14 Figure 30. SFDR vs. Clock Placement @ f = 20 MHz and 50 MHz 165MSPS OUT 12 Sleep Mode Operation 10 125MSPS The AD9744 has a power-down function that turns off the out- 8 put current and reduces the supply current to less than 6 mA 6 over the specified supply range of 2.7 V to 3.6 V and tempera- 65MSPS 4 ture range. This mode can be activated by applying a logic level 1 to the SLEEP pin. The SLEEP pin logic threshold is equal to 2 0.5 Ω AVDD. This digital input also contains an active pull- 0 0.01 0.1 1 down circuit that ensures that the AD9744 remains enabled if RATIO (f /f ) OUT CLOCK this input is left disconnected. The AD9744 takes less than 50 ns to power down and approximately 5 µs to power back up. Figure 32. I vs. Ratio @ DVDD = 3.3 V DVDD Rev. B | Page 16 of 32 dB 02913-026 02913-027 I (mA) I (mA) AVDD DVDD 02913-029 02913-028 AD9744 11 for impedance matching purposes. Note that the transformer 10 provides ac coupling only. 9 MINI-CIRCUITS T1-1T 8 IOUTA 22 7 DIFF R AD9744 LOAD PECL 6 IOUTB 21 5 OPTIONAL R DIFF 4 SE 3 Figure 34. Differential Output Using a Transformer 2 The center tap on the primary side of the transformer must be 1 connected to ACOM to provide the necessary dc current path 0 0 50 100 150 200 250 for both IOUTA and IOUTB. The complementary voltages ap- f (MSPS) CLOCK pearing at IOUTA and IOUTB (that is, VOUTA and VOUTB) swing symmetrically around ACOM and should be maintained with Figure 33. ICLKVDD vs. fCLOCK and Clock Mode the specified output compliance range of the AD9744. A differ- APPLYING THE AD9744 ential resistor, R , may be inserted in applications where the DIFF Output Configurations output of the transformer is connected to the load, R , via a LOAD passive reconstruction filter or cable. R is determined by the DIFF The following sections illustrate some typical output configura- transformer’s impedance ratio and provides the proper source tions for the AD9744. Unless otherwise noted, it is assumed that termination that results in a low VSWR. Note that approxi- IOUTFS is set to a nominal 20 mA. For applications requiring the mately half the signal power will be dissipated across RDIFF. optimum dynamic performance, a differential output configu- ration is suggested. A differential output configuration may DIFFERENTIAL COUPLING USING AN OP AMP consist of either an RF transformer or a differential op amp An op amp can also be used to perform a differential-to- configuration. The transformer configuration provides the single-ended conversion, as shown in Figure 35. The AD9744 is optimum high frequency performance and is recommended for configured with two equal load resistors, RLOAD, of 25 Ω. The any application that allows ac coupling. The differential op amp differential voltage developed across IOUTA and IOUTB is configuration is suitable for applications requiring dc coupling, converted to a single-ended signal via the differential op amp a bipolar output, signal gain, and/or level shifting within the configuration. An optional capacitor can be installed across bandwidth of the chosen op amp. IOUTA and IOUTB, forming a real pole in a low-pass filter. The A single-ended output is suitable for applications requiring a addition of this capacitor also enhances the op amp’s distortion unipolar voltage output. A positive unipolar output voltage performance by preventing the DAC’s high slewing output from results if IOUTA and/or IOUTB are connected to an appro- overloading the op amp’s input. priately sized load resistor, RLOAD, referred to ACOM. This 500Ω configuration may be more suitable for a single-supply system AD9744 225Ω requiring a dc-coupled, ground referred output voltage. Alter- IOUTA 22 natively, an amplifier could be configured as an I-V converter, AD8047 225Ω thus converting IOUTA or IOUTB into a negative unipolar 21 IOUTB C OPT voltage. This configuration provides the best dc linearity since 500Ω IOUTA or IOUTB is maintained at a virtual ground. 25Ω 25Ω DIFFERENTIAL COUPLING USING A TRANS- FORMER Figure 35. DC Differential Coupling Using an Op Amp An RF transformer can be used to perform a differential-to- The common-mode rejection of this configuration is typically single-ended signal conversion, as shown in Figure 34. A determined by the resistor matching. In this circuit, the differ- differentially coupled transformer output provides the optimum ential op amp circuit using the AD8047 is configured to provide distortion performance for output signals whose spectral con- some additional signal gain. The op amp must operate off a dual tent lies within the transformer’s pass band. An RF transformer, supply since its output is approximately ±1 V. A high speed am- such as the Mini-Circuits T1–1T, provides excellent rejection of plifier capable of preserving the differential performance of the common-mode distortion (that is, even-order harmonics) and AD9744 while meeting other system level objectives (such as, noise over a wide frequency range. It also provides electrical cost or power) should be selected. The op amp’s differential isolation and the ability to deliver twice the power to the load. gain, gain setting resistor values, and full-scale output swing Transformers with different impedance ratios may also be used Rev. B | Page 17 of 32 I (mA) CLKVDD 02913-030 02913-031 02913-032 AD9744 capabilities should all be considered when optimizing this set within U1’s voltage output swing capabilities by scaling I OUTFS circuit. and/or R . An improvement in ac distortion performance may FB result with a reduced I since the signal current U1 will be OUTFS The differential circuit shown in Figure 36 provides the neces- required to sink less signal current. sary level shifting required in a single-supply system. In this C OPT case, AVDD, which is the positive analog supply for both the AD9744 and the op amp, is also used to level-shift the differen- R FB 200Ω tial output of the AD9744 to midsupply (that is, AVDD/2). The I =10mA OUTFS AD9744 AD8041 is a suitable op amp for this application. IOUTA 22 500Ω U1 V = I × R OUT OUTFS FB AD9744 IOUTB 21 225Ω 200Ω 22 IOUTA AD8041 225Ω 21 IOUTB C Figure 38. Unipolar Buffered Voltage Output OPT 1kΩ AVDD POWER AND GROUNDING CONSIDERATIONS, 25Ω 25Ω 1kΩ POWER SUPPLY REJECTION Figure 36. Single-Supply DC Differential Coupled Circuit Many applications seek high speed and high performance under less than ideal operating conditions. In these application SINGLE-ENDED UNBUFFERED VOLTAGE OUTPUT circuits, the implementation and construction of the printed Figure 37 shows the AD9744 configured to provide a unipolar circuit board is as important as the circuit design. Proper RF output range of approximately 0 V to 0.5 V for a doubly termi- techniques must be used for device selection, placement, and nated 50 Ω cable since the nominal full-scale current, I , of OUTFS routing as well as power supply bypassing and grounding to 20 mA flows through the equivalent R of 25 Ω. In this case, LOAD ensure optimum performance. Figure 43 to Figure 46 illustrate R represents the equivalent load resistance seen by IOUTA LOAD the recommended printed circuit board ground, power, and signal or IOUTB. The unused output (IOUTA or IOUTB) can be con- plane layouts implemented on the AD9744 evaluation board. nected to ACOM directly or via a matching RLOAD. Different One factor that can measurably affect system performance is values of IOUTFS and RLOAD can be selected as long as the positive the ability of the DAC output to reject dc variations or ac noise compliance range is adhered to. One additional consideration superimposed on the analog or digital dc power distribution. in this mode is the integral nonlinearity (INL), discussed in This is referred to as the power supply rejection ratio (PSRR). the Analog Outputs section. For optimum INL performance, the single-ended, buffered voltage output configuration is For dc variations of the power supply, the resulting performance suggested. of the DAC directly corresponds to a gain error associated with the DAC’s full-scale current, IOUTFS. AC noise on the dc supplies I =20mA is common in applications where the power distribution is gen- OUTFS AD9744 V =0VTO 0.5V OUTA IOUTA 22 erated by a switching power supply. Typically, switching power 50Ω 50Ω supply noise will occur over the spectrum from tens of kHz to 21 IOUTB several MHz. The PSRR vs. frequency of the AD9744 AVDD 25Ω supply over this frequency range is shown in Figure 39. 85 Figure 37. 0 V to 0.5 V Unbuffered Voltage Output 80 SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT 75 CONFIGURATION 70 Figure 38 shows a buffered single-ended output configuration in which the op amp U1 performs an I-V conversion on the 65 AD9744 output current. U1 maintains IOUTA (or IOUTB) at a 60 virtual ground, minimizing the nonlinear output impedance 55 effect on the DAC’s INL performance as described in the 50 Analog Outputs section. Although this single-ended configura- tion typically provides the best dc linearity performance, its ac 45 distortion performance at higher DAC update rates may be 40 limited by U1’s slew rate capabilities. U1 provides a negative 0 24 68 10 12 FREQUENCY (MHz) unipolar output voltage, and its full-scale output voltage is sim- ply the product of RFB and IOUTFS. The full-scale output should be Figure 39. Power Supply Rejection Ratio (PSRR) vs. Frequency Rev. B | Page 18 of 32 02913-034 02913-033 PSRR (dB) 02913-036 02913-035 AD9744 Note that the ratio in Figure 39 is calculated as amps out/volts Proper grounding and decoupling should be a primary objec- in. Noise on the analog power supply has the effect of modulat- tive in any high speed, high resolution system. The AD9744 ing the internal switches, and therefore the output current. The features separate analog and digital supplies and ground pins to voltage noise on AVDD, therefore, will be added in a nonlinear optimize the management of analog and digital ground currents manner to the desired IOUT. Due to the relative different size in a system. In general, AVDD, the analog supply, should be of these switches, the PSRR is very code dependent. This can decoupled to ACOM, the analog common, as close to the chip produce a mixing effect that can modulate low frequency power as physically possible. Similarly, DVDD, the digital supply, supply noise to higher frequencies. Worst-case PSRR for either should be decoupled to DCOM as close to the chip as physically one of the differential DAC outputs will occur when the full- possible. scale current is directed toward that output. As a result, the PSRR measurement in Figure 39 represents a worst-case condi- For those applications that require a single 3.3 V supply for both the analog and digital supplies, a clean analog supply may be tion in which the digital inputs remain static and the full-scale output current of 20 mA is directed to the DAC output being generated using the circuit shown in Figure 40. The circuit con- measured. sists of a differential LC filter with separate power supply and return lines. Lower noise can be attained by using low ESR type An example serves to illustrate the effect of supply noise on the electrolytic and tantalum capacitors. analog supply. Suppose a switching regulator with a switching FERRITE frequency of 250 kHz produces 10 mV of noise and, for BEADS AVDD simplicity’s sake (ignoring harmonics), all of this noise is con- TTL/CMOS LOGIC 100µF 10µF–22µF 0.1µF CIRCUITS centrated at 250 kHz. To calculate how much of this undesired ELECT. TANT. CER. ACOM noise will appear as current noise superimposed on the DAC’s full-scale current, IOUTFS, one must determine the PSRR in dB using Figure 39 at 250 kHz. To calculate the PSRR for a given 3.3V RLOAD, such that the units of PSRR are converted from A/V to POWER SUPPLY V/V, adjust the curve in Figure 39 by the scaling factor 20 Ω log Figure 40. Differential LC Filter for Single 3.3 V Applications (R ). For instance, if R is 50 Ω, the PSRR is reduced LOAD LOAD by 34 dB (that is, PSRR of the DAC at 250 kHz, which is 85 dB in Figure 39, becomes 51 dB V /V ). OUT IN Rev. B | Page 19 of 32 02913-037 AD9744 EVALUATION BOARD GENERAL DESCRIPTION This board allows the user the flexibility to operate the AD9744 in various configurations. Possible output configurations in- The TxDAC family evaluation boards allow for easy setup and clude transformer coupled, resistor terminated, and single and testing of any TxDAC product in the SOIC and LFCSP pack- differential outputs. The digital inputs are designed to be driven ages. Careful attention to layout and circuit design, combined from various word generators, with the on-board option to add with a prototyping area, allows the user to evaluate the AD9744 a resistor network for proper load termination. Provisions are easily and effectively in any application where high resolution, also made to operate the AD9744 with either the internal or high speed conversion is required. external reference or to exercise the power-down feature. J1 21 DB13X 4 3 DB12X 65 DB11X 87 DB10X RP5 RP1 10 9 OPT OPT DB9X 12 11 DB8X 14 13 DB7X RP3 22Ω 1 16 16 15 DB13X DB13 DB6X RP3 22Ω 2 15 DB12X DB12 18 17 DB5X RP3 22Ω 3 14 DB11 20 19 DB11X DB4X RP3 22Ω 4 13 DB10X DB10 22 21 DB3X RP3 22Ω 5 12 DB9X DB9 24 23 DB2X RP3 22Ω 6 11 DB8X DB8 26 25 DB1X RP3 22Ω 7 10 DB7X DB7 28 27 DB0X RP3 22Ω 8 9 DB6X DB6 30 29 RP4 22Ω 1 16 DB5X DB5 32 31 JP3 RP4 22Ω 2 15 DB4X DB4 34 33 CKEXTX RP4 22Ω 3 14 DB3X DB3 36 35 RP4 22Ω 4 13 DB2X DB2 38 37 RP4 22Ω 5 12 DB1X DB1 40 39 RP4 22Ω 6 11 DB0X DB0 RP4 22Ω 7 10 RP4 22Ω 8 9 CKEXTX CKEXT RIBBON RP6 RP2 RED OPT OPT L2 BEAD TP2 DVDD TB1 1 C4 + C7 C6 10µF BLK BLK BLK 0.1µF 0.1µF 25V TP4 TP7 TP8 TB1 2 RED L3 BEAD TP5 AVDD TB1 3 C5 + C9 C8 10µF BLK BLK BLK 0.1µF 0.1µF 25V TP6 TP10 TP9 TB1 4 Figure 41. SOIC Evaluation Board—Power Supply and Digital Inputs Rev. B | Page 20 of 32 1 DCOM 1 DCOM R1 R1 2 2 R2 R2 3 3 R3 4 4 R3 R4 5 5 R4 R5 R5 6 6 R6 7 7 R6 R7 8 R7 8 R8 R8 9 9 R9 10 10 R9 DCOM DCOM 1 1 R1 R1 2 2 R2 3 3 R3 R3 4 4 R4 R4 5 5 R5 R5 6 6 R6 R6 7 7 R7 R7 8 8 R8 R8 9 9 R9 R9 10 10 02913-038 R2 AD9744 AVDD CUT +C14 UNDER DUT C16 C17 10µF 0.1µF 0.1µF 16V JP6 DVDD DVDD +C15 JP10 C18 C19 10µF 1 3 0.1µF 0.1µF A B IX 16V 2 R5 OPT S2 CLOCK IOUTA R11 50Ω CKEXT S5 CLOCK DVDD JP4 R4 TP1 50Ω WHT 1 28 R2 C13 DB13 CLOCK DB13 10kΩ OPT 2 27 JP8 DB12 DB12 DVDD DVDD 3 26 JP2 IOUT DB11 DCOM DB11 4 25 DB10 DB10 MODE 5 24 DB9 DB9 AVDD MODE 3 T1 4 AVDD 6 23 DB8 DB8 RESERVED S3 7 22 DB7 DB7 IOUTA 2 5 U1 R6 8 21 DB6 DB6 IOUTB OPT AD9742 9 20 DB5 ACOM 1 6 DB5 19 10 DB4 T1-1T DB4 NC 11 18 REF DB3 FS ADJ DB3 TP3 12 17 C1 C2 WHT DB2 REFIO DB2 0.1µF 0.1µF 16 13 DB1 C12 DB1 REFLO JP9 15 C11 14 OPT DB0 DB0 SLEEP 0.1µF R1 AVDD 2kΩ 2 R10 AVDD AB SLEEP 1 3 S1 50Ω TP11 JP5 IOUTB EXT INT WHT REF R3 2 IY 10kΩ AB 1 3 JP11 Figure 42. SOIC Evaluation Board—Output Signal Conditioning Rev. B | Page 21 of 32 02913-039 AD9744 Figure 43. SOIC Evaluation Board—Primary Side Figure 44. SOIC Evaluation Board—Secondary Side Rev. B | Page 22 of 32 02913-041 02913-040 AD9744 Figure 45. SOIC Evaluation Board—Ground Plane Figure 46. SOIC Evaluation Board—Power Plane Rev. B | Page 23 of 32 02913-043 02913-042 AD9744 Figure 47. SOIC Evaluation Board Assembly—Primary Side Figure 48. SOIC Evaluation Board Assembly—Secondary Side Rev. B | Page 24 of 32 02913-045 02913-044 AD9744 RED L1 TP12 BEAD CVDD TB1 1 2 1 DB13X 4 3 BLK DB12X C2 C10 C3 6 5 DB11X 10µF 0.1µF 0.1µF TP2 8 7 6.3V DB10X TB1 2 10 9 DB9X 12 11 DB8X 14 13 RED DB7X L2 16 15 TP13 BEAD DB6X DVDD TB3 1 18 17 DB5X 20 19 DB4X BLK C7 C4 C6 22 21 DB3X 0.1µF 10µF 0.1µF TP4 24 23 DB2X 6.3V 26 25 TB3 2 DB1X 28 27 DB0X RED 30 29 L3 TP5 BEAD 32 31 TB4 1 AVDD JP3 33 34 CKEXTX 36 35 BLK C9 C5 C8 38 37 0.1µF 10µF 0.1µF TP6 6.3V 40 39 TB4 2 J1 R3 R4 R15 R16 R17 R18 R19 R20 100Ω 100Ω 100Ω 100Ω 100Ω 100Ω 100Ω 100Ω 1 RP3 22Ω 16 DB13X DB13 2 RP3 22Ω 15 DB12X DB12 22Ω 14 3 RP3 DB11X DB11 4 RP3 22Ω 13 DB10X DB10 5 RP3 22Ω 12 DB9X DB9 6 RP3 22Ω 11 DB8X DB8 22Ω 10 7 RP3 DB7 DB7X 8 RP3 22Ω 9 DB6X DB6 1 RP4 22Ω 16 DB5X DB5 2 RP4 22Ω 15 DB4 DB4X 22Ω 14 3 RP4 DB3X DB3 4 RP4 22Ω 13 DB2X DB2 5 RP4 22Ω 12 DB1 DB1X 6 RP4 22Ω 11 DB0X DB0 7 RP4 22Ω 10 8 RP4 22Ω 9 CKEXT CKEXTX R21 R24 R25 R26 R27 R28 100Ω 100Ω 100Ω 100Ω 100Ω 100Ω Figure 49. LFCSP Evaluation Board Schematic—Power Supply and Digital Inputs Rev. B | Page 25 of 32 HEADER STRAIGHT UP MALE NO SHROUD 02913-046 AD9744 AVDD DVDD CVDD C19 C19 C17 C32 0.1µF 0.1 0.1µF 0.1µF SLEEP TP11 WHT R29 10kΩ 32 1 DB7 DB8 DB7 DB8 2 31 R11 DB6 DB6 DB9 DB9 50Ω 30 3 DVDD DB10 DVDD DB10 DNP 4 29 DB5 DB11 DB5 DB11 C13 5 28 DB4 DB12 DB4 DB12 27 6 DB3 DB13 DB3 DB13 7 26 DB2 DCOM1 TP3 TP1 JP8 DB2 25 8 DB1 SLEEP DB1 IOUT WHT WHT 9 24 DB0 FS ADJ DB0 10 23 DCOM REFIO 3 4 T1 11 U1 22 CVDD CVDD ACOM S3 12 21 CLK IA CLK 5 2 AGND: 3, 4, 5 13 20 CLKB IB CLKB 6 14 19 CCOM ACOM1 1 15 18 CMODE AVDD AVDD C11 T1 – 1T 16 CMODE 17 0.1µF MODE AVDD1 JP9 AD9744LFCSP DNP C12 TP7 R30 10kΩ WHT R10 CVDD 50Ω R1 2kΩ JP1 0.1% MODE Figure 50. LFCSP Evaluation Board Schematic—Output Signal Conditioning CVDD 1 7 U4 C20 C35 2 10µF 0.1µF 16V AGND: 5 CVDD: 8 CVDD R5 120Ω 3 CLKB 6 JP2 U4 4 S5 CKEXT AGND: 3, 4, 5 C34 AGND: 5 CVDD: 8 0.1µF CLK R2 R6 120Ω 50Ω Figure 51. LFCSP Evaluation Board Schematic—Clock Input Rev. B | Page 26 of 32 02913-048 02913-047 AD9744 Figure 52. LFCSP Evaluation Board Layout—Primary Side Figure 53. LFCSP Evaluation Board Layout—Secondary Side Rev. B | Page 27 of 32 02913-050 02913-049 AD9744 Figure 54. LFCSP Evaluation Board Layout—Ground Plane Figure 55. LFCSP Evaluation Board Layout—Power Plane Rev. B | Page 28 of 32 02913-052 02913-051 AD9744 Figure 56. LFCSP Evaluation Board Layout Assembly—Primary Side Figure 57. LFCSP Evaluation Board Layout Assembly—Secondary Side Rev. B | Page 29 of 32 02913-054 02913-053 AD9744 OUTLINE DIMENSIONS 9.80 9.70 9.60 28 15 4.50 4.40 4.30 6.40 BSC 1 14 PIN 1 0.65 BSC 1.20 MAX 0.15 0.05 8° 0.75 0.30 0.20 0° 0.60 SEATING COPLANARITY 0.19 0.09 0.45 PLANE 0.10 COMPLIANT TO JEDEC STANDARDS MO-153AE Figure 58. 28-Lead Thin Shrink Small Outline Package [TSSOP] (RU-28) Dimensions shown in millimeters 18.10 (0.7126) 17.70 (0.6969) 28 15 7.60 (0.2992) 7.40 (0.2913) 10.65 (0.4193) 1 14 10.00 (0.3937) 2.65 (0.1043) 0.75 (0.0295) × 45° 2.35 (0.0925) 0.25 (0.0098) 0.30 (0.0118) 0.10 (0.0039) 8° 1.27 (0.0500) SEATING 0° 0.51 (0.0201) 1.27 (0.0500) COPLANARITY 0.32 (0.0126) BSC PLANE 0.33 (0.0130) 0.40 (0.0157) 0.10 0.23 (0.0091) COMPLIANT TO JEDEC STANDARDS MS-013AE CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure 59. 28-Lead Standard Small Outline Package [SOIC] Wide Body (RW-28) Dimensions shown in millimeters and (inches) Rev. B | Page 30 of 32 AD9744 5.00 0.60 MAX BSC SQ 0.60 MAX PIN 1 INDICATOR 25 32 1 24 PIN 1 INDICATOR 0.50 EXPOSED 3.45 BSC TOP 4.75 PAD VIEW 3.30 SQ BSC SQ (BOTTOM VIEW) 3.15 0.50 0.40 17 8 16 9 0.30 0.25 MIN 0.80 MAX 3.50 REF 12° MAX 0.65 TYP 0.05 MAX 1.00 0.02 NOM 0.85 0.30 COPLANARITY 0.80 0.20 REF 0.23 0.08 SEATING 0.18 PLANE COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2 Figure 60. 32-Lead Lead Frame Chip Scale Package [LFCSP] 5 mm × 5 mm Body (CP-32-3) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Options AD9744AR −40°C to +85°C 28-Lead, 300-Mil SOIC RW-28 AD9744ARRL −40°C to +85°C 28-Lead, 300-Mil SOIC RW-28 1 AD9744ARZ −40°C to +85°C 28-Lead, 300-Mil SOIC RW-28 1 AD9744ARZRL −40°C to +85°C 28-Lead, 300-Mil SOIC RW-28 AD9744ARU −40°C to +85°C 28-Lead TSSOP RU-28 AD9744ARURL7 −40°C to +85°C 28-Lead TSSOP RU-28 1 AD9744ARUZ −40°C to +85°C 28-Lead TSSOP RU-28 1 AD9744ARUZRL7 −40°C to +85°C 28-Lead TSSOP RU-28 AD9744ACP −40°C to +85°C 32-Lead LFCSP CP-32-3 AD9744ACPRL7 −40°C to +85°C 32-Lead LFCSP CP-32-3 1 AD9744ACPZ −40°C to +85°C 32-Lead LFCSP CP-32-3 1 AD9744ACPZRL7 −40°C to +85°C 32-Lead LFCSP CP-32-3 AD9744-EB Evaluation Board (SOIC) AD9744ACP-PCB Evaluation Board (LFCSP) 1 Z = Pb-free part. Rev. B | Page 31 of 32 AD9744 NOTES ©2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C02913–0–4/05(B) Rev. B | Page 32 of 32